Date   

Re: [edk2-platforms][PATCH v2 4/5] Vlv2TbltDevicePkg: PlatformPkg DSC: Added library for VariableSmmRuntimeDxe

Kun Qin
 

Thanks for your review, Michael.

Could any maintainer please help merging this specific patch? All other patches in this series are already merged into mainline by Liming here (https://edk2.groups.io/g/devel/message/73035).

Please let me know if it is preferable for me to send this single patch in a v3 after rewriting the commit message with reviewed-by tag.

Thanks in advance!

Regards,
Kun

On 03/30/2021 19:06, Kinney, Michael D wrote:
Reviewed-by: Michael D Kinney <michael.d.kinney@...>
Mike

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kun Qin
Sent: Tuesday, March 16, 2021 11:11 AM
To: devel@edk2.groups.io
Cc: Sun, Zailiang <zailiang.sun@...>; Qian, Yi <yi.qian@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: [edk2-devel] [edk2-platforms][PATCH v2 4/5] Vlv2TbltDevicePkg: PlatformPkg DSC: Added library for
VariableSmmRuntimeDxe

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3250

This change added NULL MmUnblockMemoryLib instance in PlatformPkg dsc
file to resolve new dependency by VariableSmmRuntimeDxe. The library
interface is consumed by variable module to better support variable
runtime cache feature.

Cc: Zailiang Sun <zailiang.sun@...>
Cc: Yi Qian <yi.qian@...>
Cc: Michael D Kinney <michael.d.kinney@...>>
Signed-off-by: Kun Qin <kuqin12@...>
---

Notes:
v2:
- Added Michael K. to cc list [Zailiang]

Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc | 1 +
Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc | 1 +
2 files changed, 2 insertions(+)

diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
index 409f31c982d7..33e93b74800c 100644
--- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
+++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
@@ -311,6 +311,7 @@ [LibraryClasses.IA32]
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
EfiRegTableLib|Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
+ MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf

[LibraryClasses.IA32.DXE_DRIVER]
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
diff --git a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
index 38bd825c8bdc..f7a876353649 100644
--- a/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
+++ b/Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
@@ -313,6 +313,7 @@ [LibraryClasses.X64]
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
EfiRegTableLib|Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
+ MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf

[LibraryClasses.X64.DXE_DRIVER]
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
--
2.30.0.windows.1




Re: [edk2-platforms][PATCH v2 1/1] MinPlatformPkg/Acpi/AcpiSmm: Add Standalone MM support

Nate DeSimone
 

Hi Michael,

Review comments inline.

Thanks,
Nate

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
Kubacki
Sent: Friday, March 26, 2021 6:45 PM
To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@...>; Desimone,
Nathaniel L <nathaniel.l.desimone@...>; Liming Gao
<gaoliming@...>; Dong, Eric <eric.dong@...>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 1/1]
MinPlatformPkg/Acpi/AcpiSmm: Add Standalone MM support

Sending a review reminder since it's been a few weeks.

Thanks,
Michael

On 3/8/2021 9:17 AM, Michael Kubacki wrote:
From: Michael Kubacki <michael.kubacki@...>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3248

Adds a new module called AcpiStandaloneMm that serves the same role as
AcpiSmm but in a Standalone MM environment.

This change follows a similar pattern to other changes that have added
Standalone MM support to a SMM module. The SMM INF name and file
path
remain unaltered to allow backward compatibility and much of the code
is shared between the driver instances with unique entry points for
each respective module type.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Liming Gao <gaoliming@...>
Cc: Eric Dong <eric.dong@...>
Signed-off-by: Michael Kubacki <michael.kubacki@...>
---

Notes:
V2 change: Add BZ link

Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/{AcpiSmm.c => AcpiMm.c}
| 33 +++++++++----------
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.c
| 34 ++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiTraditionalMm.c
| 34 ++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.h |
23 +++++++++++++
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.h
| 24 --------------
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
| 21 ++++++------
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/{AcpiSmm.inf =>
AcpiStandaloneMm.inf} | 32 +++++++++---------
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc | 2
++
8 files changed, 133 insertions(+), 70 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.c
similarity index 81%
rename from Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.c
rename to Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.c
index 809f75d3c588..2cf559f3fe09 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.c
@@ -1,12 +1,20 @@
/** @file
- Acpi Smm driver.
+ Functions shared between driver instances.

Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/

-#include "AcpiSmm.h"
+#include <PiMm.h>
+#include <Library/BoardAcpiEnableLib.h> #include <Library/DebugLib.h>
+#include <Library/MmServicesTableLib.h> #include <Library/PcdLib.h>
+#include <Protocol/SmmSwDispatch2.h>
+
+#include "AcpiMm.h"

/**
Enable SCI
@@ -53,20 +61,13 @@ DisableAcpiCallback (
}

/**
- Initializes the Acpi Smm Driver
-
- @param[in] ImageHandle - Pointer to the loaded image protocol for this
driver
- @param[in] SystemTable - Pointer to the EFI System Table
-
- @retval Status - EFI_SUCCESS
- @retval Assert, otherwise.
+ ACPI initialization logic shared between the Traditional MM and
+ Standalone MM driver instances.

**/
-EFI_STATUS
-EFIAPI
-InitializeAcpiSmm (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+VOID
+InitializeAcpiMm (
+ VOID
)
{
EFI_STATUS Status;
@@ -77,7 +78,7 @@ InitializeAcpiSmm (
//
// Locate the ICH SMM SW dispatch protocol
//
- Status = gSmst->SmmLocateProtocol
(&gEfiSmmSwDispatch2ProtocolGuid,
NULL, (VOID**)&SwDispatch);
+ Status = gMmst->MmLocateProtocol
(&gEfiSmmSwDispatch2ProtocolGuid,
+ NULL, (VOID**) &SwDispatch);
ASSERT_EFI_ERROR (Status);

//
@@ -103,6 +104,4 @@ InitializeAcpiSmm (
&SwHandle
);
ASSERT_EFI_ERROR (Status);
-
- return EFI_SUCCESS;
}
diff --git
a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.c
new file mode 100644
index 000000000000..f378942fdc07
--- /dev/null
+++
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.c
@@ -0,0 +1,34 @@
+/** @file
+ Standalone MM driver for ACPI initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiMm.h>
+
+#include "AcpiMm.h"
+
+/**
+ The Standalone MM driver entry point.
+
+ @param[in] ImageHandle - Pointer to the loaded image protocol for this
driver
+ @param[in] SystemTable - Pointer to the EFI MM System Table
+
+ @retval Status - EFI_SUCCESS
+ @retval Assert, otherwise.
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiStandaloneMmEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ )
+{
+ InitializeAcpiMm ();
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiTraditionalMm.c
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiTraditionalMm.c
new file mode 100644
index 000000000000..9512926b9e2e
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiTraditionalMm.c
@@ -0,0 +1,34 @@
+/** @file
+ Traditional MM driver for ACPI initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiMm.h>
+
+#include "AcpiMm.h"
+
+/**
+ The Traditional MM driver entry point.
+
+ @param[in] ImageHandle - Pointer to the loaded image protocol for this
driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval Status - EFI_SUCCESS
+ @retval Assert, otherwise.
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiTraditionalMmEntryPoint (
Please rename this to AcpiSmmEntryPoint(). To my knowledge the verbiage "Traditional MM" is not used anywhere else and "SMM" does a pretty good job of denoting this is the older path.

+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ InitializeAcpiMm ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.h
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.h
new file mode 100644
index 000000000000..051474b0e833
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiMm.h
@@ -0,0 +1,23 @@
+/** @file
+ Internal header file for the ACPI MM driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_MM_H_
+#define _ACPI_MM_H_
+
+/**
+ ACPI initialization logic shared between the Traditional MM and
+ Standalone MM driver instances.
+
+**/
+VOID
+InitializeAcpiMm (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.h
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.h
deleted file mode 100644
index e34ffb1b755b..000000000000
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/** @file
- Header file for the Smm platform driver.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_SMM_H_
-#define _ACPI_SMM_H_
-
-#include <PiSmm.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/SmmServicesTableLib.h> -#include
<Library/BoardAcpiEnableLib.h> -#include <Protocol/SmmSwDispatch2.h>
-
-#endif
-
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
index fbaf46752563..651d4a293e9b 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
@@ -1,7 +1,8 @@
### @file
-# Component information file for ACPI SMM module.
+# Component information file for ACPI Traditional MM module.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -14,18 +15,15 @@ [Defines]
VERSION_STRING = 1.0
MODULE_TYPE = DXE_SMM_DRIVER
PI_SPECIFICATION_VERSION = 1.20
- ENTRY_POINT = InitializeAcpiSmm
+ ENTRY_POINT = AcpiTraditionalMmEntryPoint

[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
+ BoardAcpiEnableLib
DebugLib
- HobLib
- IoLib
+ MmServicesTableLib
PcdLib
+ UefiDriverEntryPoint
UefiLib
- SmmServicesTableLib
- BoardAcpiEnableLib

[Packages]
MdePkg/MdePkg.dec
@@ -36,13 +34,12 @@ [Pcd]
gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi ##
CONSUMES

[Sources]
- AcpiSmm.h
- AcpiSmm.c
+ AcpiMm.h
+ AcpiMm.c
+ AcpiTraditionalMm.c

[Protocols]
gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES

-[Guids]
-
[Depex]
gEfiSmmSwDispatch2ProtocolGuid
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.inf
similarity index 50%
copy from Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
copy to
Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.inf
index fbaf46752563..f7d0861b512d 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+++
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.inf
@@ -1,7 +1,8 @@
### @file
-# Component information file for ACPI SMM module.
+# Component information file for ACPI Standalone MM module.
#
# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -9,40 +10,37 @@

[Defines]
INF_VERSION = 0x00010017
- BASE_NAME = AcpiSmm
- FILE_GUID = DF9A9FFC-A075-4867-A0B2-5E7540BB023E
+ BASE_NAME = AcpiStandaloneMm
+ FILE_GUID = F113611F-DEE7-4137-8623-0168675E9F6D
VERSION_STRING = 1.0
- MODULE_TYPE = DXE_SMM_DRIVER
- PI_SPECIFICATION_VERSION = 1.20
- ENTRY_POINT = InitializeAcpiSmm
+ MODULE_TYPE = MM_STANDALONE
+ PI_SPECIFICATION_VERSION = 0x00010032
+ ENTRY_POINT = AcpiStandaloneMmEntryPoint

[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
+ BoardAcpiEnableLib
DebugLib
- HobLib
- IoLib
+ MmServicesTableLib
PcdLib
- UefiLib
- SmmServicesTableLib
- BoardAcpiEnableLib
+ StandaloneMmDriverEntryPoint

[Packages]
MdePkg/MdePkg.dec
MinPlatformPkg/MinPlatformPkg.dec

+# Note: All PCDs consumed in the Standalone MM instance must be either
FixedAtBuild
+# or PatchableInModule
[Pcd]
gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi ##
CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi ##
CONSUMES

[Sources]
- AcpiSmm.h
- AcpiSmm.c
+ AcpiMm.h
+ AcpiMm.c
+ AcpiStandaloneMm.c

[Protocols]
gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES

-[Guids]
-
[Depex]
gEfiSmmSwDispatch2ProtocolGuid
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
index 0460fd5a3206..998ee7909568 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
@@ -117,6 +117,7 @@ [LibraryClasses.common.MM_STANDALONE]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
MemoryAllocationLib|StandaloneMmPkg/Library/StandaloneMmMemoryAll
ocationLib/StandaloneMmMemoryAllocationLib.inf

MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Stan
dal
oneMmServicesTableLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
SpiFlashCommonLib|MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/
SpiFlashCommonLibNull.inf

StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntry
Poi
nt/StandaloneMmDriverEntryPoint.inf

@@ -147,6 +148,7 @@ [Components]

MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+ MinPlatformPkg/Acpi/AcpiSmm/AcpiStandaloneMm.inf
MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
MinPlatformPkg/Acpi/Library/BoardAcpiLibNull/BoardAcpiEnableLibNull.inf

MinPlatformPkg/Acpi/Library/BoardAcpiLibNull/BoardAcpiTableLibNull.inf



Re: [PATCH v3 15/46] Intel/BoardModulePkg: sort load option in the first boot

Nate DeSimone
 

Hi Ling,

This appears to be a duplicate of a patch that has already been applied:

https://github.com/tianocore/edk2-platforms/commit/abf4c54

Was this message sent in error?

Thanks,
Nate

-----Original Message-----
From: Ling Jia <jialing@...>
Sent: Friday, March 12, 2021 3:01 AM
To: devel@edk2.groups.io
Cc: Leif Lindholm <leif@...>; Peng Xie
<xiepeng@...>; Yiqi Shu <shuyiqi@...>; Liu,
Zhiguang <zhiguang.liu@...>; Dong, Eric <eric.dong@...>;
Liming Gao <gaoliming@...>; Desimone, Nathaniel L
<nathaniel.l.desimone@...>; Agyeman, Prince
<prince.agyeman@...>; Ni, Ray <ray.ni@...>; Gao, Zhichao
<zhichao.gao@...>
Subject: [PATCH v3 15/46] Intel/BoardModulePkg: sort load option in the first
boot

From: "Liu, Zhiguang" <Zhiguang.Liu@...>

Currently, load option is only sorted when setup is the first priority in boot
option. However, Below change in UefiBootManagerLib puts setup in the
end, which causes the sort function won't be called.
MdeModulePkg/UefiBootManagerLib: Put BootMenu at the end of
BootOrder
SHA-1: 7f34681c488aee2563eaa2afcc6a2c8aa7c5b912

This patch will set a NV variable in the first boot, and sort the boot option in
first boot.

Reviewed-by: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Prince Agyeman <prince.agyeman@...>
Reviewed-by: Ray Ni <ray.ni@...>
Cc: Zhichao Gao <zhichao.gao@...>

Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---

Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLi
b.c | 72 ++++++++++----------
1 file changed, 37 insertions(+), 35 deletions(-)

diff --git
a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook
Lib.c
b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook
Lib.c
index d7612fb80a95..a37139a0074e 100644
---
a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook
Lib.c
+++
b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook
+++ Lib.c
@@ -20,6 +20,8 @@
#include "BoardBdsHook.h" +#define IS_FIRST_BOOT_VAR_NAME
L"IsFirstBoot"+ GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE
gBootMode; BOOLEAN gPPRequireUIConfirm; extern
UINTN mBootMenuOptionNumber;@@ -992,37 +994,6 @@
ConnectSequence (
EfiBootManagerConnectAll (); } --/**- The function is to consider the boot
order which is not in our expectation.- In the case that we need to re-sort
the boot option.-- @retval TRUE Need to sort Boot Option.- @retval
FALSE Don't need to sort Boot Option.-**/-BOOLEAN-
IsNeedSortBootOption (- VOID- )-{- EFI_BOOT_MANAGER_LOAD_OPTION
*BootOptions;- UINTN BootOptionCount;-- BootOptions =
EfiBootManagerGetLoadOptions (&BootOptionCount,
LoadOptionTypeBoot);-- //- // If setup is the first priority in boot option, we
need to sort boot option.- //- if ((BootOptionCount > 1) &&- (((StrnCmp
(BootOptions->Description, L"Enter Setup", StrLen (L"Enter Setup"))) == 0)
||- ((StrnCmp (BootOptions->Description, L"BootManagerMenuApp",
StrLen (L"BootManagerMenuApp"))) == 0))) {- return TRUE;- }-- return
FALSE;-}-- /** Connects Root Bridge **/@@ -1332,6 +1303,9 @@
BdsAfterConsoleReadyBeforeBootOptionCallback (
) { EFI_BOOT_MODE LocalBootMode;+ EFI_STATUS
Status;+ BOOLEAN IsFirstBoot;+ UINTN DataSize;
DEBUG ((DEBUG_INFO, "Event
gBdsAfterConsoleReadyBeforeBootOptionEvent callback starts\n")); //@@
-1376,14 +1350,42 @@ BdsAfterConsoleReadyBeforeBootOptionCallback (
// // PXE boot option may appear after boot option enumeration
//++ EfiBootManagerRefreshAllBootOption ();+ DataSize = sizeof
(BOOLEAN);+ Status = gRT->GetVariable (+
IS_FIRST_BOOT_VAR_NAME,+ &gEfiCallerIdGuid,+
NULL,+ &DataSize,+ &IsFirstBoot+ );+ if
(EFI_ERROR (Status)) {+ //+ // If can't find the variable, see it as the
first boot+ //+ IsFirstBoot = TRUE;+ }++ if (IsFirstBoot) {+ //+
// In the first boot, sort the boot option+ //+
EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot,
CompareBootOption);+ IsFirstBoot = FALSE;+ Status = gRT-
SetVariable (+ IS_FIRST_BOOT_VAR_NAME,+
&gEfiCallerIdGuid,+ EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS,+ sizeof (BOOLEAN),+
&IsFirstBoot+ );+ }+ break; } Print (L"Press F7 for
BootMenu!\n"); - EfiBootManagerRefreshAllBootOption (); - if
(IsNeedSortBootOption()) {- EfiBootManagerSortLoadOptionVariable
(LoadOptionTypeBoot, CompareBootOption);- } }--
2.25.1


Re: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5

Nate DeSimone
 

Hi Ling,

This appears to be a duplicate of a patch that has already been applied:

https://edk2.groups.io/g/devel/message/71894
https://github.com/tianocore/edk2-platforms/commit/12ef75dc

Was this message sent in error?

Thanks,
Nate

-----Original Message-----
From: Ling Jia <jialing@...>
Sent: Friday, March 12, 2021 2:56 AM
To: devel@edk2.groups.io
Cc: Leif Lindholm <leif@...>; Peng Xie
<xiepeng@...>; Yiqi Shu <shuyiqi@...>; Takuto
Naito <naitaku@...>; Chaganty, Rangasai V
<rangasai.v.chaganty@...>; Desimone, Nathaniel L
<nathaniel.l.desimone@...>; Luo, Heng <heng.luo@...>
Subject: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with
GCC5

From: Takuto Naito <naitaku@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224

- Fix the path of TigerLakeFspBinPkg
- Fix misuse of RETURN_ERROR
- Remove unused function CheckNationalSio.

Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Heng Luo <heng.luo@...>
Signed-off-by: Takuto Naito <naitaku@...>
Reviewed-by: Heng Luo <heng.luo@...>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>
---

Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit
Lib/PeiFspPolicyInitLib.inf | 2 +-

Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl
atformHookLib.c | 188 --------------------

Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat
eLib/DxeSiliconPolicyUpdateLate.c | 2 +-
3 files changed, 2 insertions(+), 190 deletions(-)

diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
nitLib/PeiFspPolicyInitLib.inf
b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
nitLib/PeiFspPolicyInitLib.inf
index 9d85d855f501..708fbac08fd6 100644
---
a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
nitLib/PeiFspPolicyInitLib.inf
+++
b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
nitLib/PeiFspPolicyInitLib.inf
@@ -52,7 +52,7 @@ [Packages]
MdeModulePkg/MdeModulePkg.dec

IntelFsp2Pkg/IntelFsp2Pkg.dec

TigerlakeSiliconPkg/SiPkg.dec

- TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec

+ TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec

TigerlakeOpenBoardPkg/OpenBoardPkg.dec

UefiCpuPkg/UefiCpuPkg.dec

IntelSiliconPkg/IntelSiliconPkg.dec

diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
ePlatformHookLib.c
b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
ePlatformHookLib.c
index 6209e5045061..cc5337698b8a 100644
---
a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
ePlatformHookLib.c
+++
b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
ePlatformHookLib.c
@@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED
EFI_SIO_TABLE mSioTableWinbond_x374[] = {
{0x30, 0x01} // Enable it with Activation bit

};



-/**

- Detect if a National 393 SIO is docked. If yes, enable the docked SIO

- and its serial port, and disable the onboard serial port.

-

- @retval EFI_SUCCESS Operations performed successfully.

-**/

-STATIC

-VOID

-CheckNationalSio (

- VOID

- )

-{

- UINT8 Data8;

-

- //

- // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).

- // We use (0x2e, 0x2f) which is determined by BADD default strapping

- //

-

- //

- // Read the Pc87393 signature

- //

- IoWrite8 (0x2e, 0x20);

- Data8 = IoRead8 (0x2f);

-

- if (Data8 == 0xea) {

- //

- // Signature matches - National PC87393 SIO is docked

- //

-

- //

- // Enlarge the LPC decode scope to accommodate the Docking LPC Switch

- // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated
at

- // SIO_BASE_ADDRESS + 0x10)

- //

- PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) &
(UINT16)~0x7F), 0x20);

-

- //

- // Enable port switch

- //

- IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);

-

- //

- // Turn on docking power

- //

- IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);

-

- IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);

-

- IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);

-

- //

- // Enable port switch

- //

- IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);

-

- //

- // GPIO setting

- //

- IoWrite8 (0x2e, 0x24);

- IoWrite8 (0x2f, 0x29);

-

- //

- // Enable chip clock

- //

- IoWrite8 (0x2e, 0x29);

- IoWrite8 (0x2f, 0x1e);

-

-

- //

- // Enable serial port

- //

-

- //

- // Select com1

- //

- IoWrite8 (0x2e, 0x7);

- IoWrite8 (0x2f, 0x3);

-

- //

- // Base address: 0x3f8

- //

- IoWrite8 (0x2e, 0x60);

- IoWrite8 (0x2f, 0x03);

- IoWrite8 (0x2e, 0x61);

- IoWrite8 (0x2f, 0xf8);

-

- //

- // Interrupt: 4

- //

- IoWrite8 (0x2e, 0x70);

- IoWrite8 (0x2f, 0x04);

-

- //

- // Enable bank selection

- //

- IoWrite8 (0x2e, 0xf0);

- IoWrite8 (0x2f, 0x82);

-

- //

- // Activate

- //

- IoWrite8 (0x2e, 0x30);

- IoWrite8 (0x2f, 0x01);

-

- //

- // Disable onboard serial port

- //

- IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);

-

- //

- // Power Down UARTs

- //

- IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);

- IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);

-

- //

- // Dissable COM1 decode

- //

- IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);

- IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);

-

- //

- // Disable COM2 decode

- //

- IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);

- IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);

-

- //

- // Disable interrupt

- //

- IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);

- IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);

-

- IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);

-

- //

- // Enable floppy

- //

-

- //

- // Select floppy

- //

- IoWrite8 (0x2e, 0x7);

- IoWrite8 (0x2f, 0x0);

-

- //

- // Base address: 0x3f0

- //

- IoWrite8 (0x2e, 0x60);

- IoWrite8 (0x2f, 0x03);

- IoWrite8 (0x2e, 0x61);

- IoWrite8 (0x2f, 0xf0);

-

- //

- // Interrupt: 6

- //

- IoWrite8 (0x2e, 0x70);

- IoWrite8 (0x2f, 0x06);

-

- //

- // DMA 2

- //

- IoWrite8 (0x2e, 0x74);

- IoWrite8 (0x2f, 0x02);

-

- //

- // Activate

- //

- IoWrite8 (0x2e, 0x30);

- IoWrite8 (0x2f, 0x01);

-

- } else {

-

- //

- // No National pc87393 SIO is docked, turn off dock power and

- // disable port switch

- //

- // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);

- // IoWrite8 (0x690, 0);

-

- //

- // If no National pc87393, just return

- //

- return ;

- }

-}

-

/**

Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports



diff --git
a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd
ateLib/DxeSiliconPolicyUpdateLate.c
b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp
dateLib/DxeSiliconPolicyUpdateLate.c
index 2eee9958beea..410a8d1073a9 100644
---
a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd
ateLib/DxeSiliconPolicyUpdateLate.c
+++
b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp
dateLib/DxeSiliconPolicyUpdateLate.c
@@ -88,8 +88,8 @@ SiliconPolicyUpdateLate (
// GOP Dxe Policy Initialization

//

Status = GopPolicyInitDxe (gImageHandle);

- RETURN_ERROR (Status);

DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));

+ ASSERT_EFI_ERROR (Status);

}



return Policy;

--
2.25.1


Re: [EXTERNAL] [edk2-devel] [PATCH 1/1] MdeModulePkg/BmpSupportLib: Allow BMP with extra data

Bret Barkelew <bret.barkelew@...>
 

I agree with the proposal for a deeper security review.

 

I also would suggest that we can provide tooling with BaseTools to check and/or correct the format of a BMP to match what the code expects (since there seems to be ambiguity in the spec/implementation). We’ve got a validator in Mu and would be happy to put together some patches to at least get this started for the community to hammer on.

 

- Bret

 

From: Gao, Zhichao via groups.io
Sent: Monday, March 29, 2021 6:35 PM
To: devel@edk2.groups.io; afish@...; Laszlo Ersek
Cc: Jeff Brasen; Bret Barkelew; Wang, Jian J; Wu, Hao A; Yao, Jiewen; Liming Gao; Ni, Ray
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH 1/1] MdeModulePkg/BmpSupportLib: Allow BMP with extra data

 

The patch would let the BMP file that with a bunch of data pass the check, no matter the data is valid or not. Do we have other docs to descript which data is allowed and valid?

 

Correct the Cc mail address and invite more experts for security review.

 

Thanks,

Zhichao

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Andrew Fish via groups.io
Sent: Thursday, March 25, 2021 11:00 AM
To: edk2-devel-groups-io <devel@edk2.groups.io>; Laszlo Ersek <lersek@...>
Cc: Jeff Brasen <jbrasen@...>; bret.barkelew@...; Wang, Jian J <jian.j.wang@...>; ao.a.wu@...
Subject: Re: [EXTERNAL] [edk2-devel] [PATCH 1/1] MdeModulePkg/BmpSupportLib: Allow BMP with extra data

 

 

 

On Mar 24, 2021, at 11:26 AM, Laszlo Ersek <lersek@...> wrote:

 

On 03/24/21 16:25, Jeff Brasen wrote:

Some of the logo files we received for the group that makes our assets like this (not sure what tool they were created with) look like they pad the BMP size to 8 bytes.

TranslateBmpToGopBlt: invalid BmpImage...
  BmpHeader->Size: 0xE1038
  BmpHeader->ImageOffset: 0x36
  BmpImageSize: 0xE1038
  DataSize: 0xE1000
TranslateBmpToGopBlt: invalid BmpImage...
  BmpHeader->Size: 0x2A3038
  BmpHeader->ImageOffset: 0x36
  BmpImageSize: 0x2A3038
  DataSize: 0x2A3000
TranslateBmpToGopBlt: invalid BmpImage...
  BmpHeader->Size: 0x5EEC38
  BmpHeader->ImageOffset: 0x36
  BmpImageSize: 0x5EEC38
  DataSize: 0x5EEC00

So, each of these has 2 bytes of padding at the end of the file. We could write a tool that would do the same size recalculation in order to update the size in the header and remove the two bytes but it seems that this is a valid BMP file and it doesn't seem correct that UEFI is rejecting it. I can update the commit message with more context if needed as well.


If there's a spec describing the BMP format,

 

Yes and there are various flavors as at some point I had some graphics given to me in a format that did not work (I think it was BITMAPV4HEADER) :(. 

 

 

edk2 supports ‘BM’ and the BITMAPINFOHEADER DIB. I seem to remember DIBs are defined by the size. So ‘BM' is a Microsoft Spec:

 

The quote in that spec is:

 

The file extension of a Windows DIB file is BMP. The file consists of a BITMAPFILEHEADER structure followed by the DIB itself. Unfortunately, because the BITMAPFILEHEADER structure is never actually passed to the API, not every application that generates BMP files fills out the data structure carefully. To add to this confusion, the "proper" definition of the structure is at odds with the documentation. Properly, the data structure contains the following fields:

 

The explanation of size field is:

DWORD that specifies the size of the file in bytes. The Microsoft Windows Software Development Kit (SDK) documentation claims otherwise. To be on the safe side, many applications calculate their own sizes for reading in a file.

 

I would say that is not exactly a ringing endorsement from a spec point of view on depending on that field. So it seems like that patch may be reasonable, but we should triple check it does not break any security related assumptions. 

 

Thanks,

 

Andrew Fish

 

and edk2 is needlessly
strict, and the check can be relaxed without security risks, then I
think a patch would be fair.

Thanks
Laszlo



 

 


Re: [EXTERNAL] [edk2-devel] [PATCH 1/1] BaseTools/Ecc: Update structpcd parsing method.

Bret Barkelew <bret.barkelew@...>
 

What does “update” mean in this context? What behavior is changing?

 

- Bret

 

From: Yuwei Chen via groups.io
Sent: Thursday, April 1, 2021 12:04 AM
To: devel@edk2.groups.io
Cc: mliang2x; Feng, Bob C; Liming Gao
Subject: [EXTERNAL] [edk2-devel] [PATCH 1/1] BaseTools/Ecc: Update structpcd parsing method.

 

From: mliang2x <mingyuex.liang@...>

Update the pcdparser method in Dec and DSC files.

Signed-off-by: Mingyue Liang <mingyuex.liang@...>
Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>
---
 .../Ecc/MetaFileWorkspace/MetaFileParser.py   | 464 ++++++++++--------
 1 file changed, 265 insertions(+), 199 deletions(-)

diff --git a/BaseTools/Source/Python/Ecc/MetaFileWorkspace/MetaFileParser.py b/BaseTools/Source/Python/Ecc/MetaFileWorkspace/MetaFileParser.py
index 9c27c8e16a05..588d3dbe6ed5 100644
--- a/BaseTools/Source/Python/Ecc/MetaFileWorkspace/MetaFileParser.py
+++ b/BaseTools/Source/Python/Ecc/MetaFileWorkspace/MetaFileParser.py
@@ -22,7 +22,7 @@ import Ecc.EccToolError as EccToolError
 from CommonDataClass.DataClass import *
 from Common.DataType import *
 from Common.StringUtils import *
-from Common.Misc import GuidStructureStringToGuidString, CheckPcdDatum, PathClass, AnalyzePcdData
+from Common.Misc import GuidStructureStringToGuidString, CheckPcdDatum, PathClass, AnalyzePcdData, AnalyzeDscPcd, AnalyzePcdExpression, ParseFieldValue, StructPattern
 from Common.Expression import *
 from CommonDataClass.Exceptions import *
 
@@ -31,6 +31,8 @@ from GenFds.FdfParser import FdfParser
 from Common.LongFilePathSupport import OpenLongFilePath as open
 from Common.LongFilePathSupport import CodecOpenLongFilePath
 
+CODEPattern = re.compile(r"{CODE\([a-fA-F0-9Xx\{\},\s]*\)}")
+
 ## A decorator used to parse macro definition
 def ParseMacro(Parser):
     def MacroParser(self):
@@ -174,6 +176,11 @@ class MetaFileParser(object):
         # UNI object and extra UNI object
         self._UniObj = None
         self._UniExtraObj = None
+        # StructPcd var
+        self._PcdCodeValue = ""
+        self._PcdDataTypeCODE = False
+        self._CurrentPcdName = ""
+        self._GuidDict = {}  # for Parser PCD value {GUID(gTokeSpaceGuidName)}
 
     ## Store the parsed data in table
     def _Store(self, *Args):
@@ -395,6 +402,40 @@ class MetaFileParser(object):
                 Macros.update(self._SectionsMacroDict[(self._SectionType, Scope1, Scope2)])
         return Macros
 
+    def ProcessMultipleLineCODEValue(self, Content):
+        CODEBegin = False
+        CODELine = ""
+        continuelinecount = 0
+        newContent = []
+        for Index in range(0, len(Content)):
+            Line = Content[Index]
+            if CODEBegin:
+                CODELine = CODELine + Line
+                continuelinecount +=1
+                if ")}" in Line:
+                    newContent.append(CODELine)
+                    for _ in range(continuelinecount):
+                        newContent.append("")
+                    CODEBegin = False
+                    CODELine = ""
+                    continuelinecount = 0
+            else:
+                if not Line:
+                    newContent.append(Line)
+                    continue
+                if "{CODE(" not in Line:
+                    newContent.append(Line)
+                    continue
+                elif CODEPattern.findall(Line):
+                    newContent.append(Line)
+                    continue
+                else:
+                    CODEBegin = True
+                    CODELine = Line
+
+        return newContent
+
+
     _SectionParser  = {}
     Finished        = property(_GetFinished, _SetFinished)
     _Macros         = property(_GetMacros)
@@ -812,6 +853,8 @@ class DscParser(MetaFileParser):
             Content = open(str(self.MetaFile.Path), 'r').readlines()
         except:
             EdkLogger.error("Parser", FILE_READ_FAILURE, ExtraData=self.MetaFile)
+
+        Content = self.ProcessMultipleLineCODEValue(Content)
         #
         # Insert a record for file
         #
@@ -1018,24 +1061,71 @@ class DscParser(MetaFileParser):
     #
     @ParseMacro
     def _PcdParser(self):
+        if self._PcdDataTypeCODE:
+            self._PcdCodeValue = self._PcdCodeValue + "\n " + self._CurrentLine
+            if self._CurrentLine.endswith(")}"):
+                self._CurrentLine = "|".join((self._CurrentPcdName, self._PcdCodeValue))
+                self._PcdDataTypeCODE = False
+                self._PcdCodeValue = ""
+            else:
+                self._ValueList = None
+                return
         TokenList = GetSplitValueList(self._CurrentLine, TAB_VALUE_SPLIT, 1)
+        self._CurrentPcdName = TokenList[0]
+        if len(TokenList) == 2 and TokenList[1].strip().startswith("{CODE"):
+            self._PcdDataTypeCODE = True
+            self._PcdCodeValue = TokenList[1].strip()
+
+        if self._PcdDataTypeCODE:
+            if self._CurrentLine.endswith(")}"):
+                self._PcdDataTypeCODE = False
+                self._PcdCodeValue = ""
+            else:
+                self._ValueList = None
+                return
         self._ValueList[0:1] = GetSplitValueList(TokenList[0], TAB_SPLIT)
+        PcdNameTockens = GetSplitValueList(TokenList[0], TAB_SPLIT)
+        if len(PcdNameTockens) == 2:
+            self._ValueList[0], self._ValueList[1] = PcdNameTockens[0], PcdNameTockens[1]
+        elif len(PcdNameTockens) == 3:
+            self._ValueList[0], self._ValueList[1] = ".".join((PcdNameTockens[0], PcdNameTockens[1])), PcdNameTockens[2]
+        elif len(PcdNameTockens) > 3:
+            self._ValueList[0], self._ValueList[1] = ".".join((PcdNameTockens[0], PcdNameTockens[1])), ".".join(PcdNameTockens[2:])
         if len(TokenList) == 2:
             self._ValueList[2] = TokenList[1]
         if self._ValueList[0] == '' or self._ValueList[1] == '':
             EdkLogger.error('Parser', FORMAT_INVALID, "No token space GUID or PCD name specified",
                             ExtraData=self._CurrentLine + " (<TokenSpaceGuidCName>.<TokenCName>|<PcdValue>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
+                            File=self.MetaFile, Line=self._LineIndex + 1)
         if self._ValueList[2] == '':
+            #
+            # The PCD values are optional for FIXEDATBUILD, PATCHABLEINMODULE, Dynamic/DynamicEx default
+            #
+            if self._SectionType in (MODEL_PCD_FIXED_AT_BUILD, MODEL_PCD_PATCHABLE_IN_MODULE, MODEL_PCD_DYNAMIC_DEFAULT, MODEL_PCD_DYNAMIC_EX_DEFAULT):
+                return
             EdkLogger.error('Parser', FORMAT_INVALID, "No PCD value given",
                             ExtraData=self._CurrentLine + " (<TokenSpaceGuidCName>.<TokenCName>|<PcdValue>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
+                            File=self.MetaFile, Line=self._LineIndex + 1)
+
+        # Validate the datum type of Dynamic Defaul PCD and DynamicEx Default PCD
+        ValueList = GetSplitValueList(self._ValueList[2])
+        if len(ValueList) > 1 and ValueList[1] in [TAB_UINT8, TAB_UINT16, TAB_UINT32, TAB_UINT64] \
+                              and self._ItemType in [MODEL_PCD_DYNAMIC_DEFAULT, MODEL_PCD_DYNAMIC_EX_DEFAULT]:
+            EdkLogger.error('Parser', FORMAT_INVALID, "The datum type '%s' of PCD is wrong" % ValueList[1],
+                            ExtraData=self._CurrentLine, File=self.MetaFile, Line=self._LineIndex + 1)
+
+        # Validate the VariableName of DynamicHii and DynamicExHii for PCD Entry must not be an empty string
+        if self._ItemType in [MODEL_PCD_DYNAMIC_HII, MODEL_PCD_DYNAMIC_EX_HII]:
+            DscPcdValueList = GetSplitValueList(TokenList[1], TAB_VALUE_SPLIT, 1)
+            if len(DscPcdValueList[0].replace('L', '').replace('"', '').strip()) == 0:
+                EdkLogger.error('Parser', FORMAT_INVALID, "The VariableName field in the HII format PCD entry must not be an empty string",
+                            ExtraData=self._CurrentLine, File=self.MetaFile, Line=self._LineIndex + 1)
         # if value are 'True', 'true', 'TRUE' or 'False', 'false', 'FALSE', replace with integer 1 or 0.
         DscPcdValueList = GetSplitValueList(TokenList[1], TAB_VALUE_SPLIT, 1)
         if DscPcdValueList[0] in ['True', 'true', 'TRUE']:
-            self._ValueList[2] = TokenList[1].replace(DscPcdValueList[0], '1', 1);
+            self._ValueList[2] = TokenList[1].replace(DscPcdValueList[0], '1', 1)
         elif DscPcdValueList[0] in ['False', 'false', 'FALSE']:
-            self._ValueList[2] = TokenList[1].replace(DscPcdValueList[0], '0', 1);
+            self._ValueList[2] = TokenList[1].replace(DscPcdValueList[0], '0', 1)
 
     ## [components] section parser
     @ParseMacro
@@ -1502,6 +1592,10 @@ class DecParser(MetaFileParser):
         self._include_flag = False
         self._package_flag = False
 
+        self._AllPCDs = [] # Only for check duplicate PCD
+        self._AllPcdDict = {}
+
+
     ## Parser starter
     def Start(self):
         Content = ''
@@ -1510,6 +1604,7 @@ class DecParser(MetaFileParser):
         except:
             EdkLogger.error("Parser", FILE_READ_FAILURE, ExtraData=self.MetaFile)
 
+        Content = self.ProcessMultipleLineCODEValue(Content)
         #
         # Insert a record for file
         #
@@ -1707,51 +1802,6 @@ class DecParser(MetaFileParser):
                 namelist[2] = ".".join((arrayindex,namelist[2]))
         return namelist
 
-    def StructPcdParser(self):
-        self._ValueList[0] = self._CurrentStructurePcdName
-
-        if "|" not in self._CurrentLine:
-            if "<HeaderFiles>" == self._CurrentLine:
-                self._include_flag = True
-                self._package_flag = False
-                self._ValueList = None
-                return
-            if "<Packages>" == self._CurrentLine:
-                self._package_flag = True
-                self._ValueList = None
-                self._include_flag = False
-                return
-
-            if self._include_flag:
-                self._ValueList[1] = "<HeaderFiles>_" + md5(self._CurrentLine.encode('utf-8')).hexdigest()
-                self._ValueList[2] = self._CurrentLine
-            if self._package_flag and "}" != self._CurrentLine:
-                self._ValueList[1] = "<Packages>_" + md5(self._CurrentLine.encode('utf-8')).hexdigest()
-                self._ValueList[2] = self._CurrentLine
-            if self._CurrentLine == "}":
-                self._package_flag = False
-                self._include_flag = False
-                self._ValueList = None
-        else:
-            PcdTockens = self._CurrentLine.split(TAB_VALUE_SPLIT)
-            PcdNames = self.ParsePcdName(PcdTockens[0].split(TAB_SPLIT))
-            if len(PcdNames) == 2:
-                if PcdNames[1].strip().endswith("]"):
-                    PcdName = PcdNames[1][:PcdNames[1].index('[')]
-                    Index = PcdNames[1][PcdNames[1].index('['):]
-                    self._ValueList[0] = TAB_SPLIT.join((PcdNames[0], PcdName))
-                    self._ValueList[1] = Index
-                    self._ValueList[2] = PcdTockens[1]
-                else:
-                    self._CurrentStructurePcdName = ""
-            else:
-                if self._CurrentStructurePcdName != TAB_SPLIT.join(PcdNames[:2]):
-                    EdkLogger.error('Parser', FORMAT_INVALID, "Pcd Name does not match: %s and %s " % (
-                    self._CurrentStructurePcdName, TAB_SPLIT.join(PcdNames[:2])),
-                                    File=self.MetaFile, Line=self._LineIndex + 1)
-                self._ValueList[1] = TAB_SPLIT.join(PcdNames[2:])
-                self._ValueList[2] = PcdTockens[1]
-
     ## PCD sections parser
     #
     #   [PcdsFixedAtBuild]
@@ -1763,159 +1813,175 @@ class DecParser(MetaFileParser):
     @ParseMacro
     def _PcdParser(self):
         if self._CurrentStructurePcdName:
-            self.StructPcdParser()
-            return
-        TokenList = GetSplitValueList(self._CurrentLine, TAB_VALUE_SPLIT, 1)
-        self._ValueList[0:1] = GetSplitValueList(TokenList[0], TAB_SPLIT)
-        # check PCD information
-        if self._ValueList[0] == '' or self._ValueList[1] == '':
-            EdkLogger.error('Parser', FORMAT_INVALID, "No token space GUID or PCD name specified",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        # check PCD datum information
-        if len(TokenList) < 2 or TokenList[1] == '':
-            EdkLogger.error('Parser', FORMAT_INVALID, "No PCD Datum information given",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-
-
-        ValueRe  = re.compile(r'^\s*L?\".*\|.*\"')
-        PtrValue = ValueRe.findall(TokenList[1])
-
-        # Has VOID* type string, may contain "|" character in the string.
-        if len(PtrValue) != 0:
-            ptrValueList = re.sub(ValueRe, '', TokenList[1])
-            ValueList    = GetSplitValueList(ptrValueList)
-            ValueList[0] = PtrValue[0]
-        else:
-            ValueList = GetSplitValueList(TokenList[1])
-
-
-        # check if there's enough datum information given
-        if len(ValueList) != 3:
-            EdkLogger.error('Parser', FORMAT_INVALID, "Invalid PCD Datum information given",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        # check default value
-        if ValueList[0] == '':
-            EdkLogger.error('Parser', FORMAT_INVALID, "Missing DefaultValue in PCD Datum information",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        # check datum type
-        if ValueList[1] == '':
-            EdkLogger.error('Parser', FORMAT_INVALID, "Missing DatumType in PCD Datum information",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        # check token of the PCD
-        if ValueList[2] == '':
-            EdkLogger.error('Parser', FORMAT_INVALID, "Missing Token in PCD Datum information",
-                            ExtraData=self._CurrentLine + \
-                                      " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        # check format of default value against the datum type
-        IsValid, Cause = CheckPcdDatum(ValueList[1], ValueList[0])
-        if not IsValid:
-            EdkLogger.error('Parser', FORMAT_INVALID, Cause, ExtraData=self._CurrentLine,
-                            File=self.MetaFile, Line=self._LineIndex+1)
-        if Cause == "StructurePcd":
-            self._CurrentStructurePcdName = TAB_SPLIT.join(self._ValueList[0:2])
             self._ValueList[0] = self._CurrentStructurePcdName
-            self._ValueList[1] = ValueList[1].strip()
 
-        if EccGlobalData.gConfig.UniCheckPCDInfo == '1' or EccGlobalData.gConfig.UniCheckAll == '1' or EccGlobalData.gConfig.CheckAll == '1':
-            # check Description, Prompt information
-            PatternDesc = re.compile('##\s*([\x21-\x7E\s]*)', re.S)
-            PatternPrompt = re.compile('#\s+@Prompt\s+([\x21-\x7E\s]*)', re.S)
-            Description = None
-            Prompt = None
-            # check @ValidRange, @ValidList and @Expression format valid
-            ErrorCodeValid = '0x0 <= %s <= 0xFFFFFFFF'
-            PatternValidRangeIn = '(NOT)?\s*(\d+\s*-\s*\d+|0[xX][a-fA-F0-9]+\s*-\s*0[xX][a-fA-F0-9]+|LT\s*\d+|LT\s*0[xX][a-fA-F0-9]+|GT\s*\d+|GT\s*0[xX][a-fA-F0-9]+|LE\s*\d+|LE\s*0[xX][a-fA-F0-9]+|GE\s*\d+|GE\s*0[xX][a-fA-F0-9]+|XOR\s*\d+|XOR\s*0[xX][a-fA-F0-9]+|EQ\s*\d+|EQ\s*0[xX][a-fA-F0-9]+)'
-            PatternValidRng = re.compile('^' + '(NOT)?\s*' + PatternValidRangeIn + '$')
-            for Comment in self._Comments:
-                Comm = Comment[0].strip()
-                if not Comm:
-                    continue
-                if not Description:
-                    Description = PatternDesc.findall(Comm)
-                if not Prompt:
-                    Prompt = PatternPrompt.findall(Comm)
-                if Comm[0] == '#':
-                    ValidFormt = Comm.lstrip('#')
-                    ValidFormt = ValidFormt.lstrip()
-                    if ValidFormt[0:11] == '@ValidRange':
-                        ValidFormt = ValidFormt[11:]
-                        ValidFormt = ValidFormt.lstrip()
-                        try:
-                            ErrorCode, Expression = ValidFormt.split('|', 1)
-                        except ValueError:
-                            ErrorCode = '0x0'
-                            Expression = ValidFormt
-                        ErrorCode, Expression = ErrorCode.strip(), Expression.strip()
-                        try:
-                            if not eval(ErrorCodeValid % ErrorCode):
-                                EdkLogger.warn('Parser', '@ValidRange ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        except:
-                            EdkLogger.warn('Parser', '@ValidRange ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        if not PatternValidRng.search(Expression):
-                            EdkLogger.warn('Parser', '@ValidRange Expression(%s) of PCD %s is incorrect format.' % (Expression, TokenList[0]))
-                    if ValidFormt[0:10] == '@ValidList':
-                        ValidFormt = ValidFormt[10:]
-                        ValidFormt = ValidFormt.lstrip()
-                        try:
-                            ErrorCode, Expression = ValidFormt.split('|', 1)
-                        except ValueError:
-                            ErrorCode = '0x0'
-                            Expression = ValidFormt
-                        ErrorCode, Expression = ErrorCode.strip(), Expression.strip()
-                        try:
-                            if not eval(ErrorCodeValid % ErrorCode):
-                                EdkLogger.warn('Parser', '@ValidList ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        except:
-                            EdkLogger.warn('Parser', '@ValidList ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        Values = Expression.split(',')
-                        for Value in Values:
-                            Value = Value.strip()
-                            try:
-                                eval(Value)
-                            except:
-                                EdkLogger.warn('Parser', '@ValidList Expression of PCD %s include a invalid value(%s).' % (TokenList[0], Value))
-                                break
-                    if ValidFormt[0:11] == '@Expression':
-                        ValidFormt = ValidFormt[11:]
-                        ValidFormt = ValidFormt.lstrip()
-                        try:
-                            ErrorCode, Expression = ValidFormt.split('|', 1)
-                        except ValueError:
-                            ErrorCode = '0x0'
-                            Expression = ValidFormt
-                        ErrorCode, Expression = ErrorCode.strip(), Expression.strip()
-                        try:
-                            if not eval(ErrorCodeValid % ErrorCode):
-                                EdkLogger.warn('Parser', '@Expression ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        except:
-                            EdkLogger.warn('Parser', '@Expression ErrorCode(%s) of PCD %s is not valid UINT32 value.' % (ErrorCode, TokenList[0]))
-                        if not Expression:
-                            EdkLogger.warn('Parser', '@Expression Expression of PCD %s is incorrect format.' % TokenList[0])
-            if not Description:
-                EdkLogger.warn('Parser', 'PCD %s Description information is not provided.' % TokenList[0])
-            if not Prompt:
-                EdkLogger.warn('Parser', 'PCD %s Prompt information is not provided.' % TokenList[0])
-            # check Description, Prompt localization information
-            if self._UniObj:
-                self._UniObj.CheckPcdInfo(TokenList[0])
+            if "|" not in self._CurrentLine:
+                if "<HeaderFiles>" == self._CurrentLine:
+                    self._include_flag = True
+                    self._package_flag = False
+                    self._ValueList = None
+                    return
+                if "<Packages>" == self._CurrentLine:
+                    self._package_flag = True
+                    self._ValueList = None
+                    self._include_flag = False
+                    return
 
-        if ValueList[0] in ['True', 'true', 'TRUE']:
-            ValueList[0] = '1'
-        elif ValueList[0] in ['False', 'false', 'FALSE']:
-            ValueList[0] = '0'
+                if self._include_flag:
+                    self._ValueList[1] = "<HeaderFiles>_" + md5(self._CurrentLine.encode('utf-8')).hexdigest()
+                    self._ValueList[2] = self._CurrentLine
+                if self._package_flag and "}" != self._CurrentLine:
+                    self._ValueList[1] = "<Packages>_" + md5(self._CurrentLine.encode('utf-8')).hexdigest()
+                    self._ValueList[2] = self._CurrentLine
+                if self._CurrentLine == "}":
+                    self._package_flag = False
+                    self._include_flag = False
+                    self._ValueList = None
+                    return
+            else:
+                PcdTockens = self._CurrentLine.split(TAB_VALUE_SPLIT)
+                PcdNames = self.ParsePcdName(PcdTockens[0].split(TAB_SPLIT))
+                if len(PcdNames) == 2:
+                    if PcdNames[1].strip().endswith("]"):
+                        PcdName = PcdNames[1][:PcdNames[1].index('[')]
+                        Index = PcdNames[1][PcdNames[1].index('['):]
+                        self._ValueList[0] = TAB_SPLIT.join((PcdNames[0],PcdName))
+                        self._ValueList[1] = Index
+                        self._ValueList[2] = PcdTockens[1]
+                    else:
+                        self._CurrentStructurePcdName = ""
+                else:
+                    if self._CurrentStructurePcdName != TAB_SPLIT.join(PcdNames[:2]):
+                        EdkLogger.error('Parser', FORMAT_INVALID, "Pcd Name does not match: %s and %s " % (self._CurrentStructurePcdName, TAB_SPLIT.join(PcdNames[:2])),
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+                    self._ValueList[1] = TAB_SPLIT.join(PcdNames[2:])
+                    self._ValueList[2] = PcdTockens[1]
 
-        self._ValueList[2] = ValueList[0].strip() + '|' + ValueList[1].strip() + '|' + ValueList[2].strip()
+        if not self._CurrentStructurePcdName:
+            if self._PcdDataTypeCODE:
+                if ")}" in self._CurrentLine:
+                    ValuePart, RestofValue = self._CurrentLine.split(")}")
+                    self._PcdCodeValue = self._PcdCodeValue + "\n " + ValuePart
+                    self._CurrentLine = "|".join((self._CurrentPcdName, self._PcdCodeValue, RestofValue))
+                    self._PcdDataTypeCODE = False
+                    self._PcdCodeValue = ""
+                else:
+                    self._PcdCodeValue = self._PcdCodeValue + "\n " + self._CurrentLine
+                    self._ValueList = None
+                    return
+            TokenList = GetSplitValueList(self._CurrentLine, TAB_VALUE_SPLIT, 1)
+            self._CurrentPcdName = TokenList[0]
+            if len(TokenList) == 2 and TokenList[1].strip().startswith("{CODE"):
+                if ")}" in self._CurrentLine:
+                    self._PcdDataTypeCODE = False
+                    self._PcdCodeValue = ""
+                else:
+                    self._PcdDataTypeCODE = True
+                    self._PcdCodeValue = TokenList[1].strip()
+                    self._ValueList = None
+                    return
+
+            self._ValueList[0:1] = GetSplitValueList(TokenList[0], TAB_SPLIT)
+            ValueRe = re.compile(r'^[a-zA-Z_][a-zA-Z0-9_]*')
+            # check PCD information
+            if self._ValueList[0] == '' or self._ValueList[1] == '':
+                EdkLogger.error('Parser', FORMAT_INVALID, "No token space GUID or PCD name specified",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex+1)
+            # check format of token space GUID CName
+            if not ValueRe.match(self._ValueList[0]):
+                EdkLogger.error('Parser', FORMAT_INVALID,
+                                "The format of the token space GUID CName is invalid. The correct format is '(a-zA-Z_)[a-zA-Z0-9_]*'",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+            # check format of PCD CName
+            if not ValueRe.match(self._ValueList[1]):
+                EdkLogger.error('Parser', FORMAT_INVALID,
+                                "The format of the PCD CName is invalid. The correct format is '(a-zA-Z_)[a-zA-Z0-9_]*'",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+
+            # check PCD datum information
+            if len(TokenList) < 2 or TokenList[1] == '':
+                EdkLogger.error('Parser', FORMAT_INVALID, "No PCD Datum information given",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex+1)
+
+
+            ValueRe = re.compile(r'^\s*L?\".*\|.*\"')
+            PtrValue = ValueRe.findall(TokenList[1])
+
+            # Has VOID* type string, may contain "|" character in the string.
+            if len(PtrValue) != 0:
+                ptrValueList = re.sub(ValueRe, '', TokenList[1])
+                ValueList = AnalyzePcdExpression(ptrValueList)
+                ValueList[0] = PtrValue[0]
+            else:
+                ValueList = AnalyzePcdExpression(TokenList[1])
+
+
+            # check if there's enough datum information given
+            if len(ValueList) != 3:
+                EdkLogger.error('Parser', FORMAT_INVALID, "Invalid PCD Datum information given",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+            # check default value
+            if ValueList[0] == '':
+                EdkLogger.error('Parser', FORMAT_INVALID, "Missing DefaultValue in PCD Datum information",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+            # check datum type
+            if ValueList[1] == '':
+                EdkLogger.error('Parser', FORMAT_INVALID, "Missing DatumType in PCD Datum information",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+            # check token of the PCD
+            if ValueList[2] == '':
+                EdkLogger.error('Parser', FORMAT_INVALID, "Missing Token in PCD Datum information",
+                                ExtraData=self._CurrentLine + \
+                                          " (<TokenSpaceGuidCName>.<PcdCName>|<DefaultValue>|<DatumType>|<Token>)",
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+
+            PcdValue = ValueList[0]
+            if PcdValue:
+                try:
+                    self._GuidDict.update(self._AllPcdDict)
+                    ValueList[0] = ValueExpressionEx(ValueList[0], ValueList[1], self._GuidDict)(True)
+                except BadExpression as Value:
+                    EdkLogger.error('Parser', FORMAT_INVALID, Value, ExtraData=self._CurrentLine, File=self.MetaFile, Line=self._LineIndex + 1)
+            # check format of default value against the datum type
+            IsValid, Cause = CheckPcdDatum(ValueList[1], ValueList[0])
+            if not IsValid:
+                EdkLogger.error('Parser', FORMAT_INVALID, Cause, ExtraData=self._CurrentLine,
+                                File=self.MetaFile, Line=self._LineIndex + 1)
+
+            if Cause == "StructurePcd":
+                self._CurrentStructurePcdName = TAB_SPLIT.join(self._ValueList[0:2])
+                self._ValueList[0] = self._CurrentStructurePcdName
+                self._ValueList[1] = ValueList[1].strip()
+
+            if ValueList[0] in ['True', 'true', 'TRUE']:
+                ValueList[0] = '1'
+            elif ValueList[0] in ['False', 'false', 'FALSE']:
+                ValueList[0] = '0'
+
+            # check for duplicate PCD definition
+            if (self._Scope[0], self._ValueList[0], self._ValueList[1]) in self._AllPCDs:
+                EdkLogger.error('Parser', FORMAT_INVALID,
+                                "The same PCD name and GUID have been already defined",
+                                ExtraData=self._CurrentLine, File=self.MetaFile, Line=self._LineIndex + 1)
+            else:
+                self._AllPCDs.append((self._Scope[0], self._ValueList[0], self._ValueList[1]))
+                self._AllPcdDict[TAB_SPLIT.join(self._ValueList[0:2])] = ValueList[0]
+
+            self._ValueList[2] = ValueList[0].strip() + '|' + ValueList[1].strip() + '|' + ValueList[2].strip()
 
     _SectionParser = {
         MODEL_META_DATA_HEADER          :   MetaFileParser._DefineParser,
--
2.26.2.windows.1





 


Re: MinPlatform Board port (GSoC 2021)

Nate DeSimone
 

Hi Benjamin,

 

I sent an email to Google on your #2 question and got the following response:

 

Email address, preferred name and legal name are different things. The legal name is what should match the proof of enrollment. The preferred name is what is public (what mentors will see and will be on the program site if their project is accepted) and preferred name can be whatever the student wishes it to be. This is described on the registration form as well for folks.

 

Feel free to direct students to our support email gsoc-support@... for these types of questions as well.

 

Hope that helps.

 

Thanks,

Nate

 

From: <devel@edk2.groups.io> on behalf of Nate DeSimone <nathaniel.l.desimone@...>
Reply-To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "Desimone, Nathaniel L" <nathaniel.l.desimone@...>
Date: Wednesday, March 31, 2021 at 5:00 PM
To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "benjamin.doron00@..." <benjamin.doron00@...>
Subject: Re: [edk2-devel] MinPlatform Board port (GSoC 2021)

 

Hi Benjamin,

 

Great to meet you and welcome to the TianoCore project! Glad you hear you are interested! Doing a board port to the Acer Aspire VN7-572G laptop sounds like a great GSoC project! I presume that since you already did a coreboot port that boot guard is disabled on this laptop and you have figured out how to flash images onto it 😊.

 

The only thing that might be a little challenging is getting a 2nd copy of that laptop for your mentor, so the possibility exists that when it comes to debugging problems you might be a little more on your own than you would be otherwise. I’m not too worried about that looking at your CB:35523, it seems like you know what you are doing.

 

For sure our conventions and infrastructure are different, but there are more parallels between MinPlatform and coreboot than might initially meet the eye. For example:

 

BoardInitBeforeMemoryInit() is roughly equivalent to bootblock_mainboard_init().

BoardInitBeforeSiliconInit() is roughly equivalent to mainboard_init().

SiliconPolicyUpdatePreMem() is roughly equivalent to mainboard_memory_init_params().

 

https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.c

https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.c

FSP Dispatch Mode Policy Init: https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c

FSP API Mode Policy Init: https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c

 

I’d recommend only implementing dispatch mode for new boards. We only had the API mode version because we were busy making a version of Kaby Lake FSP that supports dispatch mode (aka AmberLakeFspBinPkg) at the same time we were developing KabyLakeOpenBoardPkg back in 2019.

 

One difference is we group our board ports based on the SOC they use. So your new board port would go under Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G for example.

 

I will give you the same caution that I gave Pedro that you will need to be careful about IP cross-contamination. Since coreboot is a GPL project and TianoCore is a BSD+Patent project, we can’t use any of their code. So you need to be careful to NOT read the coreboot Kaby Lake code (with the one exception being your patch to add the VN7-572G, since you are the exclusive author of that work you can choose to re-license it as BSD.) In general, on the days you are doing TianoCore work don’t look at any coreboot code. That way the cycle of sleep and dreams clears your head of influence.

 

As to your questions:

 

  1. I wrote the prompt to be a bit more general. I’d recommend talking about your specific project to get MinPlatform working on the Acer Aspire VN7-572G. What specific additions or changes are you planning to make to KabylakeOpenBoardPkg to get the VN7-572G working for example? Also, talk a bit about timeline. The GSoC program breaks the summer up into two half’s: June 7 – July 16 and July 16 – August 16. What should your mentor expect to be done on July 16th? What should your mentor to expect to be done on August 16th?
  2. I’m not 100% sure, but my guess is your email address can be whatever you want. But the application form should contain your full legal name for tax purposes. That doesn’t mean we won’t use your preferred nickname when conversing.

 

Hope this helps and welcome to the project!

 

With Best Regards,

Nate

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Benjamin Doron
Sent: Tuesday, March 30, 2021 4:28 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] MinPlatform Board port (GSoC 2021)

 

Hi all,
This may be my first time participating in GSoC and contributing to TianoCore. I'm looking to complete the MinPlatform board port task for an Acer Aspire VN7-572G laptop, which is a Skylake-U platform supported by the Kabylake FSP.
 
I have previously written a coreboot port for the same board, still pending review. I hope the fact that some of the board-level understanding is complete does not preclude me from participating, but many implementation details don't seem to transfer. Also, I'm looking to learn more about firmware and produce something new. I've made some other contributions to coreboot as well.
 
I've also previously worked on an EDK2 fork, adding and developing features for UefiPayloadPkg on coreboot (I can link it if anyone wants to see and possibly work on upstreaming my commits a different time).
I have some knowledge of C programming.
 
Some questions:

  1. Regarding the project proposal, Google recommends to avoid copying the prompt. I can write briefly about MinPlatform, but the task outline doesn't leave much room for flexibility. How do I outline this properly?
  2. My legal name does not match my email/preferred name. How do I resolve this (without, for example, the form being rejected because my email and first name don't match)?

 
I have a technical question or two as well, but they can wait.
 
Looking forward to working on TianoCore!


Cancelled Event: TianoCore Design Meeting - APAC/NAMO - Friday, 2 April 2021 #cal-cancelled

devel@edk2.groups.io Calendar <noreply@...>
 

Cancelled: TianoCore Design Meeting - APAC/NAMO

This event has been cancelled.

When:
Friday, 2 April 2021
9:30am to 10:30am
(UTC+08:00) Asia/Shanghai

Where:
Microsoft Teams

Organizer: Ray Ni ray.ni@...

Description:

TOPIC

  1. NA

For more info, see here: https://www.tianocore.org/design-meeting/


Microsoft Teams meeting

Join on your computer or mobile app

Click here to join the meeting

Join with a video conferencing device

teams@...

Video Conference ID: 119 715 416 0

Alternate VTC dialing instructions

Learn More | Meeting options


[edk2-platforms][PATCH V2 7/7] Platform/ARM/Morello: Add virtio net support

chandni cherukuri
 

This patch registers a virtio net device for Morello
FVP platform.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/MorelloPlatform.dec | 6 ++
Platform/ARM/Morello/MorelloPlatformFvp.dsc | 7 +++
Platform/ARM/Morello/MorelloPlatformFvp.fdf | 6 ++
Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf | 2 +
Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h | 3 +
Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c | 58 ++++++++++++++++++++
6 files changed, 82 insertions(+)

diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morello/MorelloPlatform.dec
index 9a674593cb3c..6f5c1c1b59fc 100644
--- a/Platform/ARM/Morello/MorelloPlatform.dec
+++ b/Platform/ARM/Morello/MorelloPlatform.dec
@@ -55,6 +55,12 @@
gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017
gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x00000018

+ # Virtio Net device
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetBaseAddress|0x00000000|UINT32|0x00000019
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x0000001A
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x0000001B
+
[PcdsFeatureFlag.common]
gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007
gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0000001C
diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
index 35e02be5d5ab..e579fb917348 100644
--- a/Platform/ARM/Morello/MorelloPlatformFvp.dsc
+++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
@@ -47,6 +47,7 @@

[PcdsFeatureFlag.common]
gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSupported|TRUE

[PcdsFixedAtBuild.common]
# Virtio Disk
@@ -54,8 +55,14 @@
gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200
gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128

+ # Virtio Net
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetBaseAddress|0x1C180000
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSize|0x200
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetInterrupt|134
+
[Components.common]
OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+ OvmfPkg/VirtioNetDxe/VirtioNet.inf

# Platform driver
Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Morello/MorelloPlatformFvp.fdf
index dc3eccd2f3ba..851ee3159b3d 100644
--- a/Platform/ARM/Morello/MorelloPlatformFvp.fdf
+++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf
@@ -120,6 +120,12 @@ READ_LOCK_STATUS = TRUE
# Virtio Block Device support
INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf

+ # Networking stack
+ !include NetworkPkg/Network.fdf.inc
+
+ # Virtio Net support
+ INF OvmfPkg/VirtioNetDxe/VirtioNet.inf
+
# FAT filesystem + GPT/MBR partitioning
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
index e4882343fc77..c36c62f05a39 100644
--- a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
+++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
@@ -34,11 +34,13 @@
[FeaturePcd]
gArmMorelloTokenSpaceGuid.PcdRamDiskSupported
gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSupported

[FixedPcd]
gArmMorelloTokenSpaceGuid.PcdRamDiskBase
gArmMorelloTokenSpaceGuid.PcdRamDiskSize
gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetBaseAddress

[Depex]
gEfiRamDiskProtocolGuid
diff --git a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
index 77adffbfd984..b8bd40c104a2 100644
--- a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
+++ b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
@@ -11,4 +11,7 @@
#define MORELLO_VIRTIO_BLOCK_GUID \
{ 0x2B6E62D0, 0x9346, 0x4E1A, { 0xAA, 0x1E, 0xCB, 0x01, 0xC3, 0x23, 0x4A, 0x00 } }

+#define MORELLO_VIRTIO_NET_GUID \
+ { 0x4B428575, 0xD09B, 0x45EE, { 0xAC, 0x91, 0xB1, 0x36, 0xBE, 0xD6, 0x70, 0x2B } }
+
#endif //MORELLO_VIRTIO_DEVICES_FORMSET_H_
diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
index 7414e0666ce0..1566d3142fc3 100644
--- a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
+++ b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
@@ -40,6 +40,29 @@ STATIC VIRTIO_DEVICE_PATH mVirtioBlockDevicePath =
}
};

+STATIC VIRTIO_DEVICE_PATH mVirtioNetDevicePath =
+{
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ MORELLO_VIRTIO_NET_GUID,
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),
+ 0
+ }
+ }
+};
+
/**
Initialize platform Virtio devices.

@@ -51,8 +74,10 @@ InitVirtioDevices (
{
EFI_STATUS Status;
EFI_HANDLE mVirtIoBlkController;
+ EFI_HANDLE mVirtIoNetController;

mVirtIoBlkController = NULL;
+ mVirtIoNetController = NULL;

// Install protocol interface for storage device
if (FeaturePcdGet (PcdVirtioBlkSupported)) {
@@ -87,4 +112,37 @@ InitVirtioDevices (
}
}
}
+
+ // Install protocol interface for network device
+ if (FeaturePcdGet (PcdVirtioNetSupported)) {
+
+ Status = gBS->InstallProtocolInterface (
+ &mVirtIoNetController,
+ &gEfiDevicePathProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mVirtioNetDevicePath
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to install EFI_DEVICE_PATH protocol "
+ "for Virtio Net (Status = %r)\n",
+ __FUNCTION__, Status));
+ } else {
+ // Declare the Virtio Net device
+ Status = VirtioMmioInstallDevice (
+ FixedPcdGet32 (PcdVirtioNetBaseAddress),
+ mVirtIoNetController
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find Virtio Block MMIO device "
+ "(Status == %r)\n", __FUNCTION__, Status));
+ gBS->UninstallProtocolInterface (
+ mVirtIoNetController,
+ &gEfiDevicePathProtocolGuid,
+ &mVirtioNetDevicePath
+ );
+ } else {
+ DEBUG ((DEBUG_INIT, "%a: Installed Virtio Net\n", __FUNCTION__));
+ }
+ }
+ }
}
--
2.17.1


[edk2-platforms][PATCH V2 6/7] Platform-ARM-Morello: Add Readme.md file

chandni cherukuri
 

This patch adds Readme.md file for Morello Platform.
The document consists of information regarding the platform,
steps to build and boot till UEFI Shell on the Morello FVP
Platform.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/Readme.md | 46 ++++++++++++++++++++
1 file changed, 46 insertions(+)

diff --git a/Platform/ARM/Morello/Readme.md b/Platform/ARM/Morello/Readme.md
new file mode 100644
index 000000000000..8d441234f3b8
--- /dev/null
+++ b/Platform/ARM/Morello/Readme.md
@@ -0,0 +1,46 @@
+# Introduction
+
+Morello is an ARMv8-A platform that implements the capability architecture
+extension. Capability architecture specific changes will be added [here](https://git.morello-project.org/morello).
+
+The platform port in UEFI firmware provides ARMv8-A architecture enablement.
+
+Platform code is located at Platform/ARM/Morello.
+
+# Documentation
+
+Further information on Morello Platform is available at this [page](https://developer.arm.com/architectures/cpu-architecture/a-profile/morello).
+
+# Morello FVP
+
+Morello FVP can be downloaded from this [location](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps).
+
+# Supported Host and Toolchain
+
+- Host PC should be running Ubuntu Linux 18.04 LTS.
+- Please refer to the `edk2-platforms/Readme.md` for downloading the GCC toolchain.
+
+# Build Instructions
+
+Please refer to the `edk2-platforms/Readme.md` for build instructions.
+
+# Dependencies
+
+Once the FVP is running, the SCP will be the first to boot and will bring the AP
+core out of reset. The AP core will start executing Trusted Firmware-A at BL31
+and once it completes the execution, it will start executing UEFI.
+
+The SCP and TF-A binaries are required to boot to the UEFI Shell.
+
+## SCP Firmware
+
+The SCP firmware source code can be downloaded from this [page](https://github.com/ARM-software/SCP-firmware).
+
+Refer to the [SCP Readme](https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md)
+for building SCP firmware.
+
+## Trusted Firmware-A (TF-A)
+
+The Trusted Firmware-A source code can be downloaded from this [page](https://trustedfirmware-a.readthedocs.io/en/latest/).
+
+Refer to the [TF-A Readme](https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/docs/plat/arm/morello/index.rst?h=refs/heads/master) for building TF-A.
--
2.17.1


[edk2-platforms][PATCH V2 5/7] Platform/ARM/Morello: Add initial support for Morello Platform

chandni cherukuri
 

From: Anurag Koul <anurag.koul@...>

This patch adds the initial support for Morello FVP platform.

Co-authored-by: Chandni Cherukuri <chandni.cherukuri@...>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/MorelloPlatform.dec | 60 ++++
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 236 +++++++++++++++
Platform/ARM/Morello/MorelloPlatformFvp.dsc | 61 ++++
Platform/ARM/Morello/MorelloPlatformFvp.fdf | 303 ++++++++++++++++++++
4 files changed, 660 insertions(+)

diff --git a/Platform/ARM/Morello/MorelloPlatform.dec b/Platform/ARM/Morello/MorelloPlatform.dec
new file mode 100644
index 000000000000..9a674593cb3c
--- /dev/null
+++ b/Platform/ARM/Morello/MorelloPlatform.dec
@@ -0,0 +1,60 @@
+## @file
+# Describes the entire platform configuration.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Morello
+ PACKAGE_GUID = F09A2C11-7864-4B1D-869E-03EE2AD79288
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmMorelloTokenSpaceGuid = { 0x0A8C3A78, 0xA56F, 0x4788, { 0x83, 0xB4, 0xCD, 0x29, 0x62, 0x96, 0x77, 0x51 } }
+
+[PcdsFixedAtBuild]
+ # Ramdisk
+ gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
+
+ # Secondary DDR memory
+ gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000003
+
+ # Virtio Block device
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x00000000|UINT32|0x00000004
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x00000000|UINT32|0x00000005
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|0x00000000|UINT32|0x00000006
+
+ # PCIe
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A
+ gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B
+ gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D
+ gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E
+ gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x0000000F
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x00000012
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000016
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x00000018
+
+[PcdsFeatureFlag.common]
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008
diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
new file mode 100644
index 000000000000..dccd22248318
--- /dev/null
+++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
@@ -0,0 +1,236 @@
+## @file
+# Component description file for Morello Platform
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf
+ BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+ # Ramdisk Support
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
+[LibraryClasses.common.SEC]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+
+[LibraryClasses.common.PEIM]
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.DXE_CORE]
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+!endif
+
+[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
+
+ # System Memory (2GB - 16MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+
+ # Secondary DDR memory
+ gArmMorelloTokenSpaceGuid.PcdDramBlock2Base|0x8080000000
+
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+
+ # PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2A400000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|50000000
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95
+
+ # PL011 Serial Debug UART (DBG2)
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000
+
+ # SBSA Watchdog
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93
+
+ # PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C100000
+
+ # ARM Architectural Timer Frequency
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000
+
+ # ARM Cores and Clusters
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|2
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+ # ACPI Table Version
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+ # Runtime Variable storage
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+
+ # RAM Disk
+ gArmMorelloTokenSpaceGuid.PcdRamDiskBase|0x88000000
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSize|0x18000000
+
+ # PCIe
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000
+
+[PcdsDynamicHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ # PEI Phase modules
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ # DXE
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+ }
+
+ # Architectural Protocols
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/Metronome/Metronome.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ }
+
+ # ACPI Support
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ # FAT filesystem + GPT/MBR partitioning
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ # Bds
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+
+ # RAM Disk
+ MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
+
+ # Required by PCI
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+
+ # AHCI Support
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ # SATA Controller
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
new file mode 100644
index 000000000000..35e02be5d5ab
--- /dev/null
+++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
@@ -0,0 +1,61 @@
+## @file
+# Compoenent description file specific for Morello FVP Platform
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = morellofvp
+ PLATFORM_GUID = CB995FFD-EAEF-4d5E-8A4B-3213B39CD14A
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+!ifdef $(EDK2_OUT_DIR)
+ OUTPUT_DIRECTORY = $(EDK2_OUT_DIR)
+!else
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+!endif
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/Morello/MorelloPlatformFvp.fdf
+ BUILD_NUMBER = 1
+
+ # Network definition
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Platform/ARM/Morello/MorelloPlatform.dsc.inc
+!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
+!include DynamicTablesPkg/DynamicTables.dsc.inc
+!include Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc
+
+[LibraryClasses.common]
+ # Virtio Support
+ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
+ VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
+
+[PcdsFeatureFlag.common]
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|TRUE
+
+[PcdsFixedAtBuild.common]
+ # Virtio Disk
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C170000
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize|0x200
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt|128
+
+[Components.common]
+ OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+
+ # Platform driver
+ Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.fdf b/Platform/ARM/Morello/MorelloPlatformFvp.fdf
new file mode 100644
index 000000000000..dc3eccd2f3ba
--- /dev/null
+++ b/Platform/ARM/Morello/MorelloPlatformFvp.fdf
@@ -0,0 +1,303 @@
+## @file
+# FDF file of Morello FVP platform
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL33_AP_UEFI]
+BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x200
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of
+# different images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required)
+# followed by the pipe "|" character, followed by the size of the region, also
+# in hex with the leading "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00200000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a
+# flash device file. This section also defines order the components and modules
+# are positioned within the image. The [FV] section consists of define
+# statements, set statements and module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+ # ACPI Support
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ # Configuration Manager
+ INF Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
+
+ # Dynamic Table fdf
+ !include DynamicTablesPkg/DynamicTables.fdf.inc
+
+ # Multiple Console IO support
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ # Virtio Block Device support
+ INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+
+ # FAT filesystem + GPT/MBR partitioning
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ # FV FileSystem
+ INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+ INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
+
+ # UEFI applications
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ # Platform driver
+ INF Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
+
+ # Bds
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+ # Required by PCI
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+ # AHCI Support
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ # SATA Controller
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+BlockSize = 0x1000
+NumBlocks = 0x200
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+#
+# These SEC rules are used for ArmPlatformPkg/PrePeiCore module.
+# ArmPlatformPkg/PrePeiCore is declared as a SEC module to make GenFv patch
+# the UEFI Firmware to jump to ArmPlatformPkg/PrePeiCore entrypoint
+#
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) FIXED {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
--
2.17.1


[edk2-platforms][PATCH V2 4/7] Platform/ARM/Morello: Add Configuration Manager for Morello

chandni cherukuri
 

This patch implements the configuration manager for Morello
platform. It enables support for generating the following
ACPI tables for Morello FVP Platform:
1. FADT
2. DSDT
3. GTDT
4. MADT
5. SPCR
6. DBG2
7. PPTT
8. IORT
9. MCFG
10. SSDT

Structures have been created to add Common Platform information
and FVP/Testchip platform specific information so that the
same Dxe is usable for all variants of the platform.

Co-authored-by: Jessica Clarke <jrtc27@...>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc | 16 +
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf | 94 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 281 +++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h | 122 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h | 91 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 1172 ++++++++++++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c | 602 ++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl | 98 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl | 130 +++
9 files changed, 2606 insertions(+)

diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc
new file mode 100644
index 000000000000..71916783c24c
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc
@@ -0,0 +1,16 @@
+## @file
+# dsc include file for Configuration Manager
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+[BuildOptions]
+
+[Components.common]
+ # Configuration Manager
+ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
new file mode 100644
index 000000000000..6fc307df014c
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
@@ -0,0 +1,94 @@
+## @file
+# Configuration Manager Dxe
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ConfigurationManagerDxe
+ FILE_GUID = 6F9C3B47-6F7D-44B6-87E5-4B7F44A60147
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ConfigurationManagerDxeInitialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ AslTables/DsdtFvp.asl
+ AslTables/SsdtPciFvp.asl
+ ConfigurationManager.c
+ ConfigurationManager.h
+ ConfigurationManagerFvp.c
+ ConfigurationManagerFvp.h
+ Platform.h
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEdkiiConfigurationManagerProtocolGuid
+
+[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdPciBusCount
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdPciIoBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciIoTranslation
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation
+
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSize
+
+ ## PL011 Serial Debug UART
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ # SBSA Generic Watchdog
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+
+[Depex]
+ TRUE
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
new file mode 100644
index 000000000000..fea4a0efd24a
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -0,0 +1,281 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#ifndef CONFIGURATION_MANAGER_H_
+#define CONFIGURATION_MANAGER_H_
+
+/** The configuration manager version.
+*/
+#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0)
+
+/** The OEM ID
+*/
+#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' }
+#define CFG_MGR_OEM_REVISION 0x20181101
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&CommonPlatformInfo + \
+ OFFSET_OF (EDKII_COMMON_PLATFORM_REPOSITORY_INFO, Field))
+
+/** A helper macro that constructs the MPID based on the
+ Aff0, Aff1, Aff2, Aff3 values
+*/
+#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \
+ (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0))
+
+/** A helper macro for populating the GIC CPU information
+*/
+#define GICC_ENTRY( \
+ CPUInterfaceNumber, \
+ Mpidr, \
+ PmuIrq, \
+ VGicIrq, \
+ GicRedistBase, \
+ EnergyEfficiency, \
+ SpeIrq, \
+ ProximityDomain, \
+ ClockDomain \
+ ) { \
+ CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \
+ CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \
+ EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \
+ 0, /* UINT32 ParkingProtocolVersion */ \
+ PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \
+ 0, /* UINT64 ParkedAddress */ \
+ FixedPcdGet64 ( \
+ PcdGicInterruptInterfaceBase \
+ ), /* UINT64 PhysicalBaseAddress */ \
+ 0, /* UINT64 GICV */ \
+ 0, /* UINT64 GICH */ \
+ VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \
+ GicRedistBase, /* UINT64 GICRBaseAddress */ \
+ Mpidr, /* UINT64 MPIDR */ \
+ EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \
+ SpeIrq, /* UINT16 SpeOverflowInterrupt */ \
+ ProximityDomain, /* UINT32 ProximityDomain */ \
+ ClockDomain, /* UINT32 ClockDomain */ \
+ EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \
+ }
+
+/** A helper macro for populating the Processor Hierarchy Node flags
+*/
+#define PROC_NODE_FLAGS( \
+ PhysicalPackage, \
+ AcpiProcessorIdValid, \
+ ProcessorIsThread, \
+ NodeIsLeaf, \
+ IdenticalImplementation \
+ ) \
+ ( \
+ PhysicalPackage | \
+ (AcpiProcessorIdValid << 1) | \
+ (ProcessorIsThread << 2) | \
+ (NodeIsLeaf << 3) | \
+ (IdenticalImplementation << 4) \
+ )
+
+/** A helper macro for populating the Cache Type Structure's attributes
+*/
+#define CACHE_ATTRIBUTES( \
+ AllocationType, \
+ CacheType, \
+ WritePolicy \
+ ) \
+ ( \
+ AllocationType | \
+ (CacheType << 2) | \
+ (WritePolicy << 4) \
+ )
+
+/** A function that prepares Configuration Manager Objects for returning.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object.
+ @param [out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ );
+
+/** A helper function for returning the Configuration Manager Objects.
+
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+**/
+EFI_STATUS
+EFIAPI
+HandleCmObject (
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ );
+
+/** A helper function for returning the Configuration Manager Objects that
+ match the token.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in] Token A token identifying the object.
+ @param [in] HandlerProc A handler function to search the object
+ referenced by the token.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+HandleCmObjectRefByToken (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN CONST CM_OBJECT_HANDLER_PROC HandlerProc,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ );
+
+/** The number of CPUs
+*/
+#define PLAT_CPU_COUNT 4
+
+/** The number of platform generic timer blocks
+*/
+#define PLAT_GTBLOCK_COUNT 1
+
+/** The number of timer frames per generic timer block
+*/
+#define PLAT_GTFRAME_COUNT 2
+
+/** The number of Processor Hierarchy Nodes
+ - one package node
+ - two cluster nodes
+ - two cores in cluster 0
+ - two cores in cluster 1
+*/
+#define PLAT_PROC_HIERARCHY_NODE_COUNT 7
+
+/** The number of unique cache structures:
+ - cluster L3 unified cache
+ - core L1 instruction cache
+ - core L1 data cache
+ - core L2 cache
+ - slc unified cache
+*/
+#define PLAT_CACHE_COUNT 5
+
+/** The number of resources private to the cluster
+ - L3 cache
+*/
+#define CLUSTER_RESOURCE_COUNT 1
+
+/** The number of resources private to 'core instance
+ - L1 data cache
+ - L1 instruction cache
+ - L2 cache
+*/
+#define CORE_RESOURCE_COUNT 3
+
+/** The number of resources private to SoC
+ - slc cache
+*/
+#define SOC_RESOURCE_COUNT 1
+
+/** A structure describing the platform configuration
+ manager repository information
+*/
+typedef struct CommonPlatformRepositoryInfo {
+ /// Configuration Manager Information
+ CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo;
+
+ /// Boot architecture information
+ CM_ARM_BOOT_ARCH_INFO BootArchInfo;
+
+#ifdef HEADLESS_PLATFORM
+ /// Fixed feature flag information
+ CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags;
+#endif
+
+ /// Power management profile information
+ CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo;
+
+ /// GIC CPU interface information
+ CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT];
+
+ /// GIC distributor information
+ CM_ARM_GICD_INFO GicDInfo;
+
+ /// GIC Redistributor information
+ CM_ARM_GIC_REDIST_INFO GicRedistInfo;
+
+ /// Generic timer information
+ CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo;
+
+ /// Generic timer block information
+ CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT];
+
+ /// Generic timer frame information
+ CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT];
+
+ /// Watchdog information
+ CM_ARM_GENERIC_WATCHDOG_INFO Watchdog;
+
+ /** Serial port information for the
+ serial port console redirection port
+ */
+ CM_ARM_SERIAL_PORT_INFO SpcrSerialPort;
+
+ /// Serial port information for the DBG2 UART port
+ CM_ARM_SERIAL_PORT_INFO DbgSerialPort;
+
+ // Processor topology information
+ CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT];
+
+ // Cache information
+ CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT];
+
+ // Cluster private resources
+ CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_COUNT];
+
+ // Core private resources
+ CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT];
+
+ // SoC Resources
+ CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT];
+
+} EDKII_COMMON_PLATFORM_REPOSITORY_INFO;
+
+#endif // CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h
new file mode 100644
index 000000000000..4628b7a879aa
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h
@@ -0,0 +1,122 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#ifndef FVP_CONFIGURATION_MANAGER_H_
+#define FVP_CONFIGURATION_MANAGER_H_
+
+#include "ConfigurationManager.h"
+
+/** The number of ACPI tables to install
+*/
+#define PLAT_ACPI_TABLE_COUNT 10
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN_FVP(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&MorelloFvpRepositoryInfo + \
+ OFFSET_OF (EDKII_FVP_PLATFORM_REPOSITORY_INFO, Field))
+
+/** C array containing the compiled AML template.
+ These symbols are defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 dsdtfvp_aml_code[];
+extern CHAR8 ssdtpcifvp_aml_code[];
+
+/** A structure describing the FVP Platform specific information
+*/
+typedef struct FvpPlatformRepositoryInfo {
+ /// List of ACPI tables
+ CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+
+ /// GIC ITS information
+ CM_ARM_GIC_ITS_INFO GicItsInfo[2];
+
+ /// ITS Group node
+ CM_ARM_ITS_GROUP_NODE ItsGroupInfo[2];
+
+ /// ITS Identifier array
+ CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[2];
+
+ /// SMMUv3 node
+ CM_ARM_SMMUV3_NODE SmmuV3Info[1];
+
+ /// PCI Root complex node
+ CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[1];
+
+ /// Array of DeviceID mapping
+ CM_ARM_ID_MAPPING DeviceIdMapping[2][2];
+
+ /// PCI configuration space information
+ CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[1];
+
+} EDKII_FVP_PLATFORM_REPOSITORY_INFO;
+
+/** A structure describing the platform configuration
+ manager repository information
+*/
+typedef struct PlatformRepositoryInfo {
+
+ /// Common information
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepoInfo;
+
+ /// FVP Platform specific information
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * FvpPlatRepoInfo;
+
+} EDKII_PLATFORM_REPOSITORY_INFO;
+
+extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo;
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ );
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ );
+
+#endif // FVP_CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h
new file mode 100644
index 000000000000..e6af6e170e4a
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h
@@ -0,0 +1,91 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef PLATFORM_H_
+#define PLATFORM_H_
+
+#define ENABLE_MEM_MAPPED_TIMER
+
+#ifdef ENABLE_MEM_MAPPED_TIMER
+// REFCLK CNTControl
+#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000
+// REFCLK CNTRead
+#define MORELLO_CNT_READ_BASE_ADDRESS 0x2A800000
+#else
+#define MORELLO_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#define MORELLO_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+// GT Block Timer
+// AP_REFCLK CNTCTL
+#define MORELLO_GT_BLOCK_CTL_BASE 0x2A810000
+#define MORELLO_TIMER_FRAMES_COUNT 2
+
+// GT Block Timer Frames
+// AP_REFCLK_NS CNTBase0
+#define MORELLO_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000
+#define MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
+#define MORELLO_GT_BLOCK_FRAME0_GSIV 92
+
+// AP_REFCLK_S CNTBase1
+#define MORELLO_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000
+#define MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
+#define MORELLO_GT_BLOCK_FRAME1_GSIV 91
+
+#define GTDT_TIMER_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_SAVE_CONTEXT \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_LOSE_CONTEXT 0
+
+#define MORELLO_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \
+ GTDT_TIMER_ACTIVE_LOW | \
+ GTDT_TIMER_LEVEL_TRIGGERED)
+
+// GT Block Timer Flags
+#define GTX_TIMER_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED 0
+#define GTX_TIMER_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH 0
+
+#define MORELLO_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \
+ GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE 0
+#define GTX_TIMER_SAVE_CONTEXT \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT 0
+
+#define MORELLO_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \
+ GTX_TIMER_SECURE)
+#define MORELLO_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \
+ GTX_TIMER_NON_SECURE)
+
+// Watchdog
+#define SBSA_WATCHDOG_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
+#define SBSA_WATCHDOG_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH 0
+#define SBSA_WATCHDOG_SECURE \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE 0
+
+#define MORELLO_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | \
+ SBSA_WATCHDOG_ACTIVE_HIGH | \
+ SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+#endif // PLATFORM_H_
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
new file mode 100644
index 000000000000..65f0bcfc15d4
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -0,0 +1,1172 @@
+/** @file
+ Configuration Manager Dxe
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManagerFvp.h"
+#include "ConfigurationManager.h"
+#include "Platform.h"
+
+extern EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo;
+
+// The platform configuration repository information.
+EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo = {
+ // Configuration Manager information
+ { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID },
+
+ // Boot architecture information
+ { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags
+
+#ifdef HEADLESS_PLATFORM
+ // Fixed feature flag information
+ { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags
+#endif
+
+ // Power management profile information
+ { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile
+
+ /* GIC CPU Interface information
+ GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase,
+ EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain)
+ */
+ {
+ GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ },
+
+ // GIC Distributor Info
+ {
+ FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress
+ 0, // UINT32 SystemVectorBase
+ 3 // UINT8 GicVersion
+ },
+
+ // GIC Re-Distributor Info
+ {
+ // UINT64 DiscoveryRangeBaseAddress
+ FixedPcdGet64 (PcdGicRedistributorsBase),
+ // UINT32 DiscoveryRangeLength
+ SIZE_1MB
+ },
+
+ // Generic Timer Info
+ {
+ // The physical base address for the counter control frame
+ MORELLO_SYSTEM_TIMER_BASE_ADDRESS,
+ // The physical base address for the counter read frame
+ MORELLO_CNT_READ_BASE_ADDRESS,
+ // The secure PL1 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum),
+ // The secure PL1 timer flags
+ MORELLO_GTDT_GTIMER_FLAGS,
+ // The non-secure PL1 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerIntrNum),
+ // The non-secure PL1 timer flags
+ MORELLO_GTDT_GTIMER_FLAGS,
+ // The virtual timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),
+ // The virtual timer flags
+ MORELLO_GTDT_GTIMER_FLAGS,
+ // The non-secure PL2 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum),
+ // The non-secure PL2 timer flags
+ MORELLO_GTDT_GTIMER_FLAGS
+ },
+
+ // Generic Timer Block Information
+ {
+ {
+ // The physical base address for the GT Block Timer structure
+ MORELLO_GT_BLOCK_CTL_BASE,
+ // The number of timer frames implemented in the GT Block
+ MORELLO_TIMER_FRAMES_COUNT,
+ // Reference token for the GT Block timer frame list
+ REFERENCE_TOKEN (GTBlock0TimerInfo)
+ }
+ },
+
+ // GT Block Timer Frames
+ {
+ // Frame 0
+ {
+ 0, // UINT8 FrameNumber
+ MORELLO_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntBase
+ MORELLO_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base
+ MORELLO_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV
+ MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags
+ 0, // UINT32 VirtualTimerGSIV
+ 0, // UINT32 VirtualTimerFlags
+ MORELLO_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags
+ },
+ // Frame 1
+ {
+ 1, // UINT8 FrameNumber
+ MORELLO_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntBase
+ MORELLO_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base
+ MORELLO_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV
+ MORELLO_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags
+ 0, // UINT32 VirtualTimerGSIV
+ 0, // UINT32 VirtualTimerFlags
+ MORELLO_GTX_COMMON_FLAGS_S // UINT32 CommonFlags
+ },
+ },
+
+ // Watchdog Info
+ {
+ // The physical base address of the SBSA Watchdog control frame
+ FixedPcdGet64 (PcdGenericWatchdogControlBase),
+ // The physical base address of the SBSA Watchdog refresh frame
+ FixedPcdGet64 (PcdGenericWatchdogRefreshBase),
+ // The watchdog interrupt
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ // The watchdog flags
+ MORELLO_SBSA_WATCHDOG_FLAGS
+ },
+
+ // SPCR Serial Port
+ {
+ FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress
+ FixedPcdGet32 (PL011UartInterrupt), // Interrupt
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+ FixedPcdGet32 (PL011UartClkInHz), // Clock
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype
+ },
+
+ // Debug Serial Port
+ {
+ FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress
+ 0, // Interrupt -unused
+ FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate
+ FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_SBSA_GENERIC_UART // Port subtype
+ },
+
+ // Processor Hierarchy Nodes
+ {
+ // Package
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ CM_NULL_TOKEN,
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ SOC_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (SocResources)
+ },
+
+ // Cluster0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster0 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[0]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster0 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[1]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster1 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[2]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+
+ // Cluster1 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[3]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ },
+
+ // Cache information
+ {
+ // 'cluster's L3 cache
+ {
+ REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_1MB, // UINT32 Size
+ 2048, // UINT32 NumberOfSets
+ 8, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // 'core's L1 instruction cache
+ {
+ REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_64KB, // UINT32 Size
+ 256, // UINT32 NumberOfSets
+ 4, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // 'core's L1 data cache
+ {
+ REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_64KB, // UINT32 Size
+ 256, // UINT32 NumberOfSets
+ 4, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // cores's L2 cache
+ {
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_1MB, // UINT32 Size
+ 2048, // UINT32 NumberOfSets
+ 8, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // slc cache
+ {
+ REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_8MB, // UINT32 Size
+ 4096, // UINT32 NumberOfSets
+ 16, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ },
+ // Resources private to the 'cluster (shared among cores) in Cluster
+ {
+ { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Cluster
+ },
+ // Resources private to each individual 'core instance in Cluster
+ {
+ { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster
+ { REFERENCE_TOKEN (CacheInfo[2]) }, // -> 'core's L1 D-cache in Cluster
+ { REFERENCE_TOKEN (CacheInfo[3]) } // -> 'core's L2 cache in Cluster
+ },
+
+ // Resources private to the SoC
+ {
+ { REFERENCE_TOKEN (CacheInfo[4]) } // -> slc for SoC
+ },
+};
+
+/** A helper function for returning the Configuration Manager Objects.
+
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+**/
+EFI_STATUS
+EFIAPI
+HandleCmObject (
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ CmObjectDesc->ObjectId = CmObjectId;
+ CmObjectDesc->Size = ObjectSize;
+ CmObjectDesc->Data = (VOID*)Object;
+ CmObjectDesc->Count = ObjectCount;
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ CmObjectId,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return EFI_SUCCESS;
+}
+
+/** A helper function for returning the Configuration Manager Objects that
+ match the token.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in] Token A token identifying the object.
+ @param [in] HandlerProc A handler function to search the object
+ referenced by the token.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+HandleCmObjectRefByToken (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN CONST CM_OBJECT_HANDLER_PROC HandlerProc,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ EFI_STATUS Status;
+ CmObjectDesc->ObjectId = CmObjectId;
+ if (Token == CM_NULL_TOKEN) {
+ CmObjectDesc->Size = ObjectSize;
+ CmObjectDesc->Data = (VOID*)Object;
+ CmObjectDesc->Count = ObjectCount;
+ Status = EFI_SUCCESS;
+ } else {
+ Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ (VOID*)Token,
+ CmObjectId,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return Status;
+}
+
+/** A helper function for returning Configuration Manager Object(s) referenced
+ by token when the entire platform repository is in scope and the
+ CM_NULL_TOKEN value is not allowed.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token identifying the object.
+ @param [in] HandlerProc A handler function to search the object(s)
+ referenced by the token.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObjectSearchPlatformRepo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN CONST CM_OBJECT_HANDLER_PROC HandlerProc,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ EFI_STATUS Status;
+ CmObjectDesc->ObjectId = CmObjectId;
+ if (Token == CM_NULL_TOKEN) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: CM_NULL_TOKEN value is not allowed when searching"
+ " the entire platform repository.\n"
+ ));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ CmObjectId,
+ (VOID*)Token,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return Status;
+}
+
+/** Initialize the Platform Configuration Repository.
+
+ @param [in] PlatformRepo Pointer to the Platform Configuration Repository.
+
+ @retval
+ EFI_SUCCESS Success
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+InitializePlatformRepository (
+ IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/** Return a GT Block timer frame info list.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGTBlockTimerFrameInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo;
+
+ if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) {
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo);
+ CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->GTBlock0TimerInfo);
+ return EFI_SUCCESS;
+}
+
+/** Return GIC CPU Interface Info.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Object ID of the CM object requested
+ @param [in] SearchToken A unique token for identifying the requested
+ CM_ARM_GICC_INFO object.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGicCInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN SearchToken,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINT32 ObjIndex;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->CommonPlatRepoInfo;
+
+ for (ObjIndex = 0; ObjIndex < PLAT_CPU_COUNT; ObjIndex++) {
+ if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]);
+ CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return a list of Configuration Manager object references pointed to by the
+ given input token.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Object ID of the CM object requested
+ @param [in] SearchToken A unique token for identifying the requested
+ CM_ARM_OBJ_REF list.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetCmObjRefs (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN SearchToken,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ CommonPlatRepo = This->PlatRepoInfo->CommonPlatRepoInfo;
+
+ if (SearchToken == (CM_OBJECT_TOKEN)&CommonPlatRepo->ClusterResources) {
+ CmObject->Size = sizeof (CommonPlatRepo->ClusterResources);
+ CmObject->Data = (VOID*)&CommonPlatRepo->ClusterResources;
+ CmObject->Count = ARRAY_SIZE (CommonPlatRepo->ClusterResources);
+ return EFI_SUCCESS;
+ }
+ if (SearchToken == (CM_OBJECT_TOKEN)&CommonPlatRepo->CoreResources) {
+ CmObject->Size = sizeof (CommonPlatRepo->CoreResources);
+ CmObject->Data = (VOID*)&CommonPlatRepo->CoreResources;
+ CmObject->Count = ARRAY_SIZE (CommonPlatRepo->CoreResources);
+ return EFI_SUCCESS;
+ }
+ if (SearchToken == (CM_OBJECT_TOKEN)&CommonPlatRepo->SocResources) {
+ CmObject->Size = sizeof (CommonPlatRepo->SocResources);
+ CmObject->Data = (VOID*)&CommonPlatRepo->SocResources;
+ CmObject->Count = ARRAY_SIZE (CommonPlatRepo->SocResources);
+ return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return a standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ CommonPlatRepo = This->PlatRepoInfo->CommonPlatRepoInfo;
+
+ //First search the FVP/SoC platform specific objects and enter the below
+ //if condition only when this function returns EFI_NOT_FOUND status.
+ Status = GetStandardNameSpaceObjectPlat (This, CmObjectId, Token, CmObject);
+
+ if (Status == EFI_NOT_FOUND) {
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EStdObjCfgMgrInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->CmInfo,
+ sizeof (CommonPlatRepo->CmInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ } //switch
+ }
+
+ return Status;
+}
+
+/** Return an ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO * CommonPlatRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+ CommonPlatRepo = This->PlatRepoInfo->CommonPlatRepoInfo;
+ Status = EFI_NOT_FOUND;
+
+ //First search the FVP/SoC platform specific objects and enter the below
+ //if condition only when this function return EFI_NOT_FOUND status.
+ Status = GetArmNameSpaceObjectPlat (This, CmObjectId, Token, CmObject);
+
+ if (Status == EFI_NOT_FOUND) {
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EArmObjBootArchInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->BootArchInfo,
+ sizeof (CommonPlatRepo->BootArchInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+#ifdef HEADLESS_PLATFORM
+ case EArmObjFixedFeatureFlags:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->FixedFeatureFlags,
+ sizeof (CommonPlatRepo->FixedFeatureFlags),
+ 1,
+ CmObject
+ );
+ break;
+#endif
+ case EArmObjPowerManagementProfileInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->PmProfileInfo,
+ sizeof (CommonPlatRepo->PmProfileInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGenericTimerInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->GenericTimerInfo,
+ sizeof (CommonPlatRepo->GenericTimerInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjPlatformGenericWatchdogInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->Watchdog,
+ sizeof (CommonPlatRepo->Watchdog),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjPlatformGTBlockInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ CommonPlatRepo->GTBlockInfo,
+ sizeof (CommonPlatRepo->GTBlockInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGTBlockTimerFrameInfo:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ CommonPlatRepo->GTBlock0TimerInfo,
+ sizeof (CommonPlatRepo->GTBlock0TimerInfo),
+ ARRAY_SIZE (CommonPlatRepo->GTBlock0TimerInfo),
+ Token,
+ GetGTBlockTimerFrameInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicCInfo:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ CommonPlatRepo->GicCInfo,
+ sizeof (CommonPlatRepo->GicCInfo),
+ PLAT_CPU_COUNT,
+ Token,
+ GetGicCInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicDInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->GicDInfo,
+ sizeof (CommonPlatRepo->GicDInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicRedistributorInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->GicRedistInfo,
+ sizeof (CommonPlatRepo->GicRedistInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjSerialConsolePortInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->SpcrSerialPort,
+ sizeof (CommonPlatRepo->SpcrSerialPort),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjSerialDebugPortInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &CommonPlatRepo->DbgSerialPort,
+ sizeof (CommonPlatRepo->DbgSerialPort),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjProcHierarchyInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ CommonPlatRepo->ProcHierarchyInfo,
+ sizeof (CommonPlatRepo->ProcHierarchyInfo),
+ PLAT_PROC_HIERARCHY_NODE_COUNT,
+ CmObject
+ );
+ break;
+
+ case EArmObjCacheInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ CommonPlatRepo->CacheInfo,
+ sizeof (CommonPlatRepo->CacheInfo),
+ ARRAY_SIZE (CommonPlatRepo->CacheInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjCmRef:
+ Status = HandleCmObjectSearchPlatformRepo (
+ This,
+ CmObjectId,
+ Token,
+ GetCmObjRefs,
+ CmObject
+ );
+ break;
+
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }//switch
+ }
+ return Status;
+}
+
+/** Return an OEM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetOemNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }
+
+ return Status;
+}
+
+/** The GetObject function defines the interface implemented by the
+ Configuration Manager Protocol for returning the Configuration
+ Manager Objects.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+MorelloPlatformGetObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (GET_CM_NAMESPACE_ID (CmObjectId)) {
+ case EObjNameSpaceStandard:
+ Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ case EObjNameSpaceArm:
+ Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ case EObjNameSpaceOem:
+ Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ default: {
+ Status = EFI_INVALID_PARAMETER;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }
+
+ return Status;
+}
+
+/** The SetObject function defines the interface implemented by the
+ Configuration Manager Protocol for updating the Configuration
+ Manager Objects.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the Object.
+
+ @retval EFI_UNSUPPORTED This operation is not supported.
+**/
+EFI_STATUS
+EFIAPI
+MorelloPlatformSetObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/** A structure describing the configuration manager protocol interface.
+*/
+STATIC
+CONST
+EDKII_CONFIGURATION_MANAGER_PROTOCOL MorelloPlatformConfigManagerProtocol = {
+ CREATE_REVISION(1,0),
+ MorelloPlatformGetObject,
+ MorelloPlatformSetObject,
+ &MorelloRepositoryInfo
+};
+
+/**
+ Entrypoint of Configuration Manager Dxe.
+
+ @param ImageHandle
+ @param SystemTable
+
+ @return EFI_SUCCESS
+ @return EFI_LOAD_ERROR
+ @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+ConfigurationManagerDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ // Initialize the Platform Configuration Repository before installing the
+ // Configuration Manager Protocol
+ Status = InitializePlatformRepository (
+ MorelloPlatformConfigManagerProtocol.PlatRepoInfo
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Failed to initialize the Platform Configuration Repository." \
+ " Status = %r\n",
+ Status
+ ));
+ }
+
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gEdkiiConfigurationManagerProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID*)&MorelloPlatformConfigManagerProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Failed to get Install Configuration Manager Protocol." \
+ " Status = %r\n",
+ Status
+ ));
+ goto error_handler;
+ }
+
+error_handler:
+ return Status;
+}
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c
new file mode 100644
index 000000000000..c265dd2d0b15
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c
@@ -0,0 +1,602 @@
+/** @file
+ Configuration Manager Dxe
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManagerFvp.h"
+#include "Platform.h"
+
+EDKII_FVP_PLATFORM_REPOSITORY_INFO MorelloFvpRepositoryInfo = {
+ // ACPI Table List
+ {
+ // FADT Table
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
+ NULL
+ },
+ // GTDT Table
+ {
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
+ NULL
+ },
+ // MADT Table
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
+ NULL
+ },
+ // SPCR Table
+ {
+ EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
+ NULL
+ },
+ // DSDT Table
+ {
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)dsdtfvp_aml_code
+ },
+ // DBG2 Table
+ {
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
+ NULL
+ },
+ // PPTT Table
+ {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
+ NULL
+ },
+ // IORT Table
+ {
+ EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
+ NULL
+ },
+ // PCI MCFG Table
+ {
+ EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
+ NULL,
+ },
+ // SSDT table describing the PCI root complex
+ {
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpcifvp_aml_code
+ },
+ },
+
+ // GIC ITS
+ {
+ // GIC ITS - PCIe TCU
+ {
+ // The GIC ITS ID.
+ 0,
+ // The physical address for the Interrupt Translation Service
+ 0x30060000,
+ //Proximity Domain
+ 0
+ },
+ // GIC ITS - PCIe RC
+ {
+ // The GIC ITS ID.
+ 1,
+ // The physical address for the Interrupt Translation Service
+ 0x300A0000,
+ //Proximity Domain
+ 0
+ },
+ },
+
+ // ITS group node
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_FVP (ItsGroupInfo[0]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_FVP (ItsIdentifierArray[0])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_FVP (ItsGroupInfo[1]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_FVP (ItsIdentifierArray[1])
+ },
+ },
+
+ // ITS identifier array
+ {
+ {
+ // The ITS Identifier
+ 0
+ },
+ {
+ // The ITS Identifier
+ 1
+ },
+ },
+
+ // SMMUv3 Node
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_FVP (SmmuV3Info[0]),
+ // Number of ID mappings
+ 2,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_FVP (DeviceIdMapping[0][0]),
+ // SMMU Base Address
+ 0x4F400000,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 0x10B,
+ // PRI Interrupt if SPI based
+ 0,
+ // GERR interrupt if GSIV based
+ 0x10D,
+ // Sync interrupt if GSIV based
+ 0x10C,
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping, ignored as SMMU
+ // control interrupts are GSIV based
+ 1
+ },
+ },
+
+ // Root Complex node info
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_FVP (RootComplexInfo[0]),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_FVP (DeviceIdMapping[1][0]),
+
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+ // PCI segment number
+ 0,
+ // Memory address size limit
+ 42
+ },
+ },
+
+ // Array of Device ID mappings
+ {
+ // DeviceIdMapping[0][0] - [0][1]
+ {
+ /* Mapping SMMUv3 -> ITS Group
+ */
+
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_FVP (ItsGroupInfo[1]),
+ // Flags
+ 0
+ },
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x00000001,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN_FVP (ItsGroupInfo[0]),
+ // Flags
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ // DeviceIdMapping[1][0]
+ {
+ // Mapping for RootComplex -> SMMUv3
+
+ // Device ID mapping for Root complex node
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_FVP (SmmuV3Info[0]),
+ // Flags
+ 0
+ },
+ },
+ },
+ // PCI Configuration Space Info
+ {
+ // PCIe ECAM
+ {
+ FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address
+ 0x0, // Segment Group Number
+ FixedPcdGet32 (PcdPciBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdPciBusMax) // End Bus Number
+ },
+ },
+};
+
+EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = {
+ &CommonPlatformInfo,
+ &MorelloFvpRepositoryInfo
+};
+
+/** Return a device Id mapping array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetDeviceIdMappingArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo;
+
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n"));
+
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->Data = (VOID*)Token;
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Count = Count;
+ CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING);
+
+ return EFI_SUCCESS;
+}
+
+/** Return an ITS identifier array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsIdentifierArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]);
+ CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return an ITS group info.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsGroupInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsGroupInfo);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]);
+ CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+ PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo;
+ Status = EFI_NOT_FOUND;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EArmObjGicItsInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->GicItsInfo,
+ sizeof (PlatformRepo->GicItsInfo),
+ ARRAY_SIZE (PlatformRepo->GicItsInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjSmmuV3:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->SmmuV3Info,
+ sizeof (PlatformRepo->SmmuV3Info),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjItsGroup:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsGroupInfo,
+ sizeof (PlatformRepo->ItsGroupInfo),
+ ARRAY_SIZE (PlatformRepo->ItsGroupInfo),
+ Token,
+ GetItsGroupInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicItsIdentifierArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsIdentifierArray,
+ sizeof (PlatformRepo->ItsIdentifierArray),
+ ARRAY_SIZE (PlatformRepo->ItsIdentifierArray),
+ Token,
+ GetItsIdentifierArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjRootComplex:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->RootComplexInfo,
+ sizeof (PlatformRepo->RootComplexInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjIdMappingArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->DeviceIdMapping,
+ sizeof (PlatformRepo->DeviceIdMapping),
+ ARRAY_SIZE (PlatformRepo->DeviceIdMapping),
+ Token,
+ GetDeviceIdMappingArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjPciConfigSpaceInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->PciConfigInfo,
+ sizeof (PlatformRepo->PciConfigInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ default: {
+ break;
+ }
+ }//switch
+ return Status;
+}
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_FVP_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ PlatformRepo = This->PlatRepoInfo->FvpPlatRepoInfo;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EStdObjAcpiTableList:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->CmAcpiTableList,
+ sizeof (PlatformRepo->CmAcpiTableList),
+ ARRAY_SIZE (PlatformRepo->CmAcpiTableList),
+ CmObject
+ );
+ break;
+
+ default: {
+ break;
+ }
+ }
+
+ return Status;
+}
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl
new file mode 100644
index 000000000000..26072a95db76
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl
@@ -0,0 +1,98 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2021, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "ConfigurationManager.h"
+
+DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) {
+ Scope(_SB) {
+ Device(CP00) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP01) { // Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP02) { // Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP03) { // Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name(_STA, 0xF)
+ }
+
+ // VIRTIO DISK
+ Device(VR00) {
+ Name(_HID, "LNRO0005")
+ Name(_UID, 0)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(
+ ReadWrite,
+ FixedPcdGet32(PcdVirtioBlkBaseAddress),
+ FixedPcdGet32(PcdVirtioBlkSize)
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {
+ FixedPcdGet32(PcdVirtioBlkInterrupt)
+ }
+ })
+ }
+
+ // VIRTIO NET
+ Device(VR01) {
+ Name(_HID, "LNRO0005")
+ Name(_UID, 1)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C180000, 0x00000200)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 134 }
+ })
+ }
+
+ // VIRTIO RANDOM
+ Device(VR02) {
+ Name(_HID, "LNRO0005")
+ Name(_UID, 2)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C190000, 0x00000200)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 133 }
+ })
+ }
+
+ // VIRTIO P9 Device
+ Device(VR03) {
+ Name(_HID, "LNRO0005")
+ Name(_UID, 3)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1C1A0000, 0x00000200)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 135 }
+ })
+ }
+
+ // SMC91X
+ Device(NET0) {
+ Name(_HID, "LNRO0003")
+ Name(_UID, 0)
+
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x1D100000, 0x00001000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 130 }
+ })
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl
new file mode 100644
index 000000000000..bdf2f06aed69
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl
@@ -0,0 +1,130 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "ConfigurationManager.h"
+
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO",
+ CFG_MGR_OEM_REVISION)
+{
+ Scope (_SB) {
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 201)
+ LNK_DEVICE(2, LNKB, 202)
+ LNK_DEVICE(3, LNKC, 203)
+ LNK_DEVICE(4, LNKD, 204)
+
+ // PCI Root Complex
+ Device(PCI0) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdPciBusCount) // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPciMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPciMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdPciMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPciMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPciIoTranslation), // Translate
+ FixedPcdGet32 (PcdPciIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method (_CRS)
+ } // Device (PCI0)
+ } // _SB
+} // DB
--
2.17.1


[edk2-platforms][PATCH V2 3/7] Platform/ARM/Morello: Add PlatformDxe driver for Morello

chandni cherukuri
 

From: Anurag Koul <anurag.koul@...>

This patch adds the PlatformDxe Driver for Morello
platform. It includes the registration of the ramdisk
device.

Co-authored-by: Chandni Cherukuri <chandni.cherukuri@...>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf | 44 ++++++++++
Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h | 14 +++
Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c | 66 ++++++++++++++
Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c | 90 ++++++++++++++++++++
4 files changed, 214 insertions(+)

diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
new file mode 100644
index 000000000000..e4882343fc77
--- /dev/null
+++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
@@ -0,0 +1,44 @@
+## @file
+# Platform DXE driver for Morello FVP Platform
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 11FC8B5A-377D-47A8-AEE9-0093D3D3407F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmMorelloEntryPoint
+
+[Sources.common]
+ PlatformDxeFvp.c
+ VirtioDevices.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ OvmfPkg/OvmfPkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ VirtioMmioDeviceLib
+
+[Protocols]
+ gEfiRamDiskProtocolGuid
+
+[FeaturePcd]
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSupported
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported
+
+[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdRamDiskBase
+ gArmMorelloTokenSpaceGuid.PcdRamDiskSize
+ gArmMorelloTokenSpaceGuid.PcdVirtioBlkBaseAddress
+
+[Depex]
+ gEfiRamDiskProtocolGuid
diff --git a/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
new file mode 100644
index 000000000000..77adffbfd984
--- /dev/null
+++ b/Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
@@ -0,0 +1,14 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef MORELLO_VIRTIO_DEVICES_FORMSET_H_
+#define MORELLO_VIRTIO_DEVICES_FORMSET_H_
+
+#define MORELLO_VIRTIO_BLOCK_GUID \
+ { 0x2B6E62D0, 0x9346, 0x4E1A, { 0xAA, 0x1E, 0xCB, 0x01, 0xC3, 0x23, 0x4A, 0x00 } }
+
+#endif //MORELLO_VIRTIO_DEVICES_FORMSET_H_
diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c
new file mode 100644
index 000000000000..93c5ec670197
--- /dev/null
+++ b/Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c
@@ -0,0 +1,66 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/RamDisk.h>
+
+VOID
+InitVirtioDevices (
+ VOID
+ );
+
+/**
+ Entrypoint of Platform Dxe Driver
+
+ @param ImageHandle[in] The firmware allocated handle for the EFI image.
+ @param SystemTable[in] A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+**/
+EFI_STATUS
+EFIAPI
+ArmMorelloEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_RAM_DISK_PROTOCOL *RamDisk;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = EFI_SUCCESS;
+
+ InitVirtioDevices ();
+
+ if (FeaturePcdGet (PcdRamDiskSupported)) {
+ Status = gBS->LocateProtocol (
+ &gEfiRamDiskProtocolGuid,
+ NULL,
+ (VOID**)&RamDisk
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Couldn't find the RAM Disk protocol %r\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ Status = RamDisk->Register (
+ (UINTN)PcdGet32 (PcdRamDiskBase),
+ (UINTN)PcdGet32 (PcdRamDiskSize),
+ &gEfiVirtualCdGuid,
+ NULL,
+ &DevicePath
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n",
+ __FUNCTION__, Status));
+ }
+ }
+
+ return Status;
+}
diff --git a/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
new file mode 100644
index 000000000000..7414e0666ce0
--- /dev/null
+++ b/Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
@@ -0,0 +1,90 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Guid/MorelloVirtioDevicesFormSet.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/VirtioMmioDeviceLib.h>
+
+#pragma pack (1)
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} VIRTIO_DEVICE_PATH;
+#pragma pack ()
+
+STATIC VIRTIO_DEVICE_PATH mVirtioBlockDevicePath =
+{
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ MORELLO_VIRTIO_BLOCK_GUID,
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),
+ 0
+ }
+ }
+};
+
+/**
+ Initialize platform Virtio devices.
+
+**/
+VOID
+InitVirtioDevices (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE mVirtIoBlkController;
+
+ mVirtIoBlkController = NULL;
+
+ // Install protocol interface for storage device
+ if (FeaturePcdGet (PcdVirtioBlkSupported)) {
+
+ Status = gBS->InstallProtocolInterface (
+ &mVirtIoBlkController,
+ &gEfiDevicePathProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mVirtioBlockDevicePath
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to install EFI_DEVICE_PATH protocol "
+ "for Virtio Block device (Status = %r)\n",
+ __FUNCTION__, Status));
+ } else {
+ // Declare the Virtio BlockIo device
+ Status = VirtioMmioInstallDevice (
+ FixedPcdGet32 (PcdVirtioBlkBaseAddress),
+ mVirtIoBlkController
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find Virtio Block MMIO device "
+ "(Status == %r)\n", __FUNCTION__, Status));
+ gBS->UninstallProtocolInterface (
+ mVirtIoBlkController,
+ &gEfiDevicePathProtocolGuid,
+ &mVirtioBlockDevicePath
+ );
+ } else {
+ DEBUG ((DEBUG_INIT, "%a: Installed Virtio Block device\n",
+ __FUNCTION__));
+ }
+ }
+ }
+}
--
2.17.1


[edk2-platforms][PATCH V2 2/7] Platform/ARM/Morello: Add support for PciHostBridgeLib

chandni cherukuri
 

Morello FVP platform supports a PCIe root complex.
This patch implements PciHostBridgeLib to support PCIe.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 ++++++
Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c | 180 ++++++++++++++++++++
2 files changed, 228 insertions(+)

diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
new file mode 100644
index 000000000000..1d6c5b01d13d
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
@@ -0,0 +1,48 @@
+## @file
+# PCI Host Bridge Library instance for ARM Morello FVP platform.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = 6879CEAD-DC94-42EB-895C-096D36B8083C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ PciHostBridgeLibFvp.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciIoBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiCpuIo2ProtocolGuid
diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
new file mode 100644
index 000000000000..042cbbdca202
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
@@ -0,0 +1,180 @@
+/** @file
+ PCI Host Bridge Library instance for ARM Morello FVP platform.
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#define ROOT_COMPLEX_NUM 1
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08),
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+};
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
+ {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdPciMmio64Base),
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+ },
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ *Count = ARRAY_SIZE (mPciRootBridge);
+ return mPciRootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr))
+ );
+ DEBUG ((DEBUG_ERROR, "%s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, "Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
--
2.17.1


[edk2-platforms][PATCH V2 1/7] Platform/ARM/Morello: Add Platform library implementation

chandni cherukuri
 

From: Anurag Koul <anurag.koul@...>

This patch adds initial Morello Platform Library support.
It includes virtual memory map and helper functions for
platform initialization.

Co-authored-by: Chandni Cherukuri <chandni.cherukuri@...>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
---
Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf | 52 +++++
Platform/ARM/Morello/Include/MorelloPlatform.h | 63 +++++++
Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c | 99 ++++++++++
Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 198 ++++++++++++++++++++
Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S | 83 ++++++++
5 files changed, 495 insertions(+)

diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf
new file mode 100644
index 000000000000..c2d7da3701d2
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf
@@ -0,0 +1,52 @@
+## @file
+# Platform Library for Morello platform.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ArmMorelloLib
+ FILE_GUID = 36853D86-7200-47B4-9408-E962A00963FD
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[Sources.common]
+ PlatformLib.c
+ PlatformLibMem.c
+
+[Sources.AARCH64]
+ AArch64/Helper.S | GCC
+
+[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdDramBlock2Base
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[Guids]
+ gEfiHobListGuid ## CONSUMES ## SystemTable
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/Platform/ARM/Morello/Include/MorelloPlatform.h b/Platform/ARM/Morello/Include/MorelloPlatform.h
new file mode 100644
index 000000000000..8b3233025958
--- /dev/null
+++ b/Platform/ARM/Morello/Include/MorelloPlatform.h
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef MORELLO_PLATFORM_H_
+#define MORELLO_PLATFORM_H_
+
+#define MORELLO_DRAM_BLOCK1_SIZE SIZE_2GB
+
+// ****************************************************************************
+// Platform Memory Map
+// ****************************************************************************
+
+// SubSystem Peripherals - UART0
+#define MORELLO_UART0_BASE 0x2A400000
+#define MORELLO_UART0_SZ SIZE_64KB
+
+// SubSystem Peripherals - UART1
+#define MORELLO_UART1_BASE 0x2A410000
+#define MORELLO_UART1_SZ SIZE_64KB
+
+// SubSystem Peripherals - Generic Watchdog
+#define MORELLO_GENERIC_WDOG_BASE 0x2A440000
+#define MORELLO_GENERIC_WDOG_SZ SIZE_128KB
+
+// SubSystem Peripherals - GIC(600)
+#define MORELLO_GIC_BASE 0x30000000
+#define MORELLO_GICR_BASE 0x300C0000
+#define MORELLO_GIC_SZ SIZE_256KB
+#define MORELLO_GICR_SZ SIZE_1MB
+
+// SubSystem non-secure SRAM
+#define MORELLO_NON_SECURE_SRAM_BASE 0x06000000
+#define MORELLO_NON_SECURE_SRAM_SZ SIZE_64KB
+
+// AXI Expansion peripherals
+#define MORELLO_EXP_PERIPH_BASE 0x1C000000
+#define MORELLO_EXP_PERIPH_BASE_SZ 0x1300000
+
+// Platform information structure base address
+#define MORELLO_PLAT_INFO_STRUCT_BASE MORELLO_NON_SECURE_SRAM_BASE
+
+/*
+ * Platform information structure stored in Non-secure SRAM. Platform
+ * information are passed from the trusted firmware with the below structure
+ * format. The elements of MORELLO_PLAT_INFO should be always in sync with
+ * the lower level firmware.
+ */
+#pragma pack(1)
+
+typedef struct {
+ UINT64 LocalDdrSize; ///< Local DDR memory size in Bytes
+ UINT64 RemoteDdrSize; ///< Remote DDR memory size in Bytes
+ UINT8 SlaveCount; ///< Slave count in C2C mode
+ UINT8 Mode; ///< 0 - Single Chip, 1 - Chip to Chip (C2C)
+} MORELLO_PLAT_INFO;
+
+#pragma pack()
+
+#endif //MORELLO_PLATFORM_H_
diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c
new file mode 100644
index 000000000000..52318a62911a
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c
@@ -0,0 +1,99 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+STATIC ARM_CORE_INFO mCoreInfoTable[] = {
+ { 0x0, 0x0 }, // Cluster 0, Core 0
+ { 0x0, 0x1 }, // Cluster 0, Core 1
+ { 0x1, 0x0 }, // Cluster 1, Core 0
+ { 0x1, 0x1 } // Cluster 1, Core 1
+};
+
+/**
+ Return the current Boot Mode.
+
+ This function returns the boot reason on the platform.
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must be setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+ @param[in] MpId Processor ID
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+/**
+ Populate the Platform core information.
+
+ This function populates the ARM_MP_CORE_INFO_PPI with information about the cores.
+
+ @param[out] CoreCount Number of cores
+ @param[out] ArmCoreTable Table containing information about the cores
+
+**/
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = mCoreInfoTable;
+ return EFI_SUCCESS;
+}
+
+STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = {
+ PrePeiCoreGetMpCoreInfo
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+/**
+ Return the Platform specific PPIs
+
+ This function exposes the Morello Platform Specific PPIs.
+
+ @param[out] PpiListSize Size in Bytes of the Platform PPI List
+ @param[out] PpiList Platform PPI List
+
+**/
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c
new file mode 100644
index 000000000000..54a870cfb3ba
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c
@@ -0,0 +1,198 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <MorelloPlatform.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
+
+#if !defined(MDEPKG_NDEBUG)
+STATIC CONST CHAR8 *gTblAttrDesc[] = {
+ "UNCACHED_UNBUFFERED ",
+ "NONSECURE_UNCACHED_UNBUFFERED",
+ "WRITE_BACK ",
+ "NONSECURE_WRITE_BACK ",
+ "WB_NONSHAREABLE ",
+ "NONSECURE_WB_NONSHAREABLE ",
+ "WRITE_THROUGH ",
+ "NONSECURE_WRITE_THROUGH ",
+ "DEVICE ",
+ "NONSECURE_DEVICE "
+};
+#endif
+
+#define LOG_MEM(desc) DEBUG (( \
+ DEBUG_ERROR, \
+ desc, \
+ VirtualMemoryTable[Index].PhysicalBase, \
+ (VirtualMemoryTable[Index].PhysicalBase + \
+ VirtualMemoryTable[Index].Length - 1), \
+ VirtualMemoryTable[Index].Length, \
+ gTblAttrDesc[VirtualMemoryTable[Index].Attributes] \
+ ));
+
+/**
+ Returns the Virtual Memory Map of the platform.
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
+ on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
+ a Physical-to-Virtual Memory mapping. This array
+ must be ended by a zero-filled entry.
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR * VirtualMemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ MORELLO_PLAT_INFO * PlatInfo;
+ UINT64 DramBlock2Size;
+
+ Index = 0;
+ DramBlock2Size = 0;
+
+ PlatInfo = (MORELLO_PLAT_INFO *)MORELLO_PLAT_INFO_STRUCT_BASE;
+ if (PlatInfo->LocalDdrSize > MORELLO_DRAM_BLOCK1_SIZE) {
+ DramBlock2Size = PlatInfo->LocalDdrSize - MORELLO_DRAM_BLOCK1_SIZE;
+ }
+
+ if (DramBlock2Size != 0) {
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdDramBlock2Base),
+ DramBlock2Size
+ );
+ }
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ DEBUG ((
+ DEBUG_ERROR,
+ " Memory Map\n----------------------------------------------------------\n"
+ ));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Description : START - END " \
+ "[ SIZE ] { ATTR }\n"
+ ));
+
+ // SubSystem Peripherals - Generic Watchdog
+ VirtualMemoryTable[Index].PhysicalBase = MORELLO_GENERIC_WDOG_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_GENERIC_WDOG_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_GENERIC_WDOG_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("Generic Watchdog : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // SubSystem Peripherals - GIC-600
+ VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GIC_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_GIC_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_GIC_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("GIC-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // SubSystem Peripherals - GICR-600
+ VirtualMemoryTable[++Index].PhysicalBase = MORELLO_GICR_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_GICR_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_GICR_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("GICR-600 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // SubSystem non-secure SRAM
+ VirtualMemoryTable[++Index].PhysicalBase = MORELLO_NON_SECURE_SRAM_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_NON_SECURE_SRAM_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_NON_SECURE_SRAM_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ LOG_MEM ("non-secure SRAM : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // SubSystem Pheripherals - UART0
+ VirtualMemoryTable[++Index].PhysicalBase = MORELLO_UART0_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_UART0_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_UART0_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("UART0 : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // DDR Primary
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ LOG_MEM ("DDR Primary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // DDR Secondary
+ if (DramBlock2Size != 0) {
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].Length = DramBlock2Size;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ LOG_MEM ("DDR Secondary : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+ }
+
+ // Expansion Peripherals
+ VirtualMemoryTable[++Index].PhysicalBase = MORELLO_EXP_PERIPH_BASE;
+ VirtualMemoryTable[Index].VirtualBase = MORELLO_EXP_PERIPH_BASE;
+ VirtualMemoryTable[Index].Length = MORELLO_EXP_PERIPH_BASE_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // PCI Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) -
+ FixedPcdGet32 (PcdPciBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCI Configuration Space : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // PCI MMIO32/IO Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size) +
+ PcdGet32 (PcdPciIoSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCI MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // PCI MMIO64 Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCI MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ] { %a }\n");
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+ DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n"));
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S
new file mode 100644
index 000000000000..f6cc087a132c
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+//
+// First platform specific function to be called in the PEI phase
+//
+// This function is actually the first function called by the PrePi
+// or PrePeiCore modules. It allows to retrieve arguments passed to
+// the UEFI firmware through the CPU registers.
+//
+ASM_PFX(ArmPlatformPeiBootAction):
+ ret
+
+//
+// Return the core position from the value of its MpId register
+//
+// This function returns core position from the position 0 in the processor.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the core position
+//
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #7
+ ret
+
+//
+// Return the MpId of the primary core
+//
+// This function returns the MpId of the primary core.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return the MpId of the primary core
+//
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
+ ret
+
+//
+// Return a non-zero value if the callee is the primary core
+//
+// This function returns a non-zero value if the callee is the primary core.
+// Primary core is the core responsible to initialize hardware and run UEFI.
+// This function might be called from assembler before any stack is set.
+//
+// @return Return a non-zero value if the callee is the primary core.
+//
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
+ cmp w0, w1
+ cset x0, eq
+ ret
--
2.17.1


[edk2-platforms][PATCH V2 0/7] Add Morello FVP platform support

chandni cherukuri
 

Changes since V1:
- Added 2 new patches which provide virtio net support and documentation
for the Morello FVP platform.
- Resolved the coding style errors and ran Ecc.
- Replaced function macros with functions in ConfigurationManager.

Morello is an ARMv8-A platform that implements the capability architecture
extension. This patch series provides ARMv8-A architecture enablement
for the Morello FVP platform.

The changes can be seen at:
https://github.com/chandnich/edk2-platforms/tree/morello_plat_support_v2

Anurag Koul (3):
Platform/ARM/Morello: Add Platform library implementation
Platform/ARM/Morello: Add PlatformDxe driver for Morello
Platform/ARM/Morello: Add initial support for Morello Platform

Chandni Cherukuri (4):
Platform/ARM/Morello: Add support for PciHostBridgeLib
Platform/ARM/Morello: Add Configuration Manager for Morello
Platform-ARM-Morello: Add Readme.md file
Platform/ARM/Morello: Add virtio net support

Platform/ARM/Morello/MorelloPlatform.dec | 66 +
.../ConfigurationManagerFvp.dsc.inc | 16 +
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 236 ++++
Platform/ARM/Morello/MorelloPlatformFvp.dsc | 68 +
Platform/ARM/Morello/MorelloPlatformFvp.fdf | 309 +++++
.../ConfigurationManagerDxeFvp.inf | 94 ++
.../Drivers/PlatformDxe/PlatformDxeFvp.inf | 46 +
.../PciHostBridgeLib/PciHostBridgeLibFvp.inf | 48 +
.../Library/PlatformLib/PlatformLib.inf | 52 +
.../ConfigurationManager.h | 281 ++++
.../ConfigurationManagerFvp.h | 122 ++
.../ConfigurationManagerDxe/Platform.h | 91 ++
.../Guid/MorelloVirtioDevicesFormSet.h | 17 +
.../ARM/Morello/Include/MorelloPlatform.h | 63 +
.../ConfigurationManager.c | 1172 +++++++++++++++++
.../ConfigurationManagerFvp.c | 602 +++++++++
.../Drivers/PlatformDxe/PlatformDxeFvp.c | 66 +
.../Drivers/PlatformDxe/VirtioDevices.c | 148 +++
.../PciHostBridgeLib/PciHostBridgeLibFvp.c | 180 +++
.../Morello/Library/PlatformLib/PlatformLib.c | 99 ++
.../Library/PlatformLib/PlatformLibMem.c | 198 +++
.../AslTables/DsdtFvp.asl | 98 ++
.../AslTables/SsdtPciFvp.asl | 130 ++
.../Library/PlatformLib/AArch64/Helper.S | 83 ++
Platform/ARM/Morello/Readme.md | 46 +
25 files changed, 4331 insertions(+)
create mode 100644 Platform/ARM/Morello/MorelloPlatform.dec
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerFvp.dsc.inc
create mode 100644 Platform/ARM/Morello/MorelloPlatform.dsc.inc
create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.dsc
create mode 100644 Platform/ARM/Morello/MorelloPlatformFvp.fdf
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.inf
create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.inf
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/Platform.h
create mode 100644 Platform/ARM/Morello/Include/Guid/MorelloVirtioDevicesFormSet.h
create mode 100644 Platform/ARM/Morello/Include/MorelloPlatform.h
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerFvp.c
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c
create mode 100644 Platform/ARM/Morello/Drivers/PlatformDxe/VirtioDevices.c
create mode 100644 Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLib.c
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl
create mode 100644 Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl
create mode 100644 Platform/ARM/Morello/Library/PlatformLib/AArch64/Helper.S
create mode 100644 Platform/ARM/Morello/Readme.md

--
2.17.1


Re: [patch V4 16/29] NetworkPkg: Consume MdeLibs.dsc.inc for RegisterFilterLib

Maciej Rabeda
 

Reviewed-by: Maciej Rabeda <maciej.rabeda@...>

On 28-Mar-21 14:02, Dandan Bi wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

MdeLibs.dsc.inc was added for some basic/default library
instances provided by MdePkg and RegisterFilterLibNull Library
was also added into it as the first version of MdeLibs.dsc.inc.

So update platform dsc to consume MdeLibs.dsc.inc for
RegisterFilterLibNull which will be consumed by IoLib and BaseLib.

Cc: Maciej Rabeda <maciej.rabeda@...>
Cc: Jiaxin Wu <jiaxin.wu@...>
Cc: Siyuan Fu <siyuan.fu@...>
Signed-off-by: Dandan Bi <dandan.bi@...>
Acked-by: Ard Biesheuvel <ardb@...>
---
NetworkPkg/NetworkPkg.dsc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/NetworkPkg/NetworkPkg.dsc b/NetworkPkg/NetworkPkg.dsc
index 531da841e9..5e6619ad85 100644
--- a/NetworkPkg/NetworkPkg.dsc
+++ b/NetworkPkg/NetworkPkg.dsc
@@ -1,10 +1,10 @@
## @file
# UEFI 2.4 Network Module Package for All Architectures
#
# (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
-# Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,10 +18,12 @@ [Defines]
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
DEFINE NETWORK_ISCSI_ENABLE = TRUE
+!include MdePkg/MdeLibs.dsc.inc
+
[LibraryClasses]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf


Re: [PATCH v1] MdePkg/BaseLib: Add support for the XSETBV instruction

Wu, Jiaxin
 

Hi Liming and Jiewen,

Could you help review the patch?

Thanks,
Jiaxin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Wu,
Jiaxin
Sent: Wednesday, March 31, 2021 3:54 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Liming Gao
<gaoliming@...>; Liu, Zhiguang <zhiguang.liu@...>; Yao,
Jiewen <jiewen.yao@...>; Zhang, Hongbin1
<hongbin1.zhang@...>
Subject: [edk2-devel] [PATCH v1] MdePkg/BaseLib: Add support for the
XSETBV instruction

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.

Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509abd4e45439bbdfe2c2fa8780c950320a

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Yao Jiewen <jiewen.yao@...>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@...>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@...>
---
MdePkg/Include/Library/BaseLib.h | 25 +++++++++++++++++++++++-
MdePkg/Library/BaseLib/BaseLib.inf | 4 +++-
MdePkg/Library/BaseLib/Ia32/XSetBv.nasm | 34
+++++++++++++++++++++++++++++++++
MdePkg/Library/BaseLib/X64/XSetBv.nasm | 34
+++++++++++++++++++++++++++++++++
4 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/XSetBv.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h
b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb5..035d6b655d 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1,10 +1,10 @@
/** @file
Provides string functions, linked list functions, math functions,
synchronization
functions, file path functions, and CPU architecture-specific functions.

-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -7436,10 +7436,33 @@ UINT64
EFIAPI
AsmXGetBv (
IN UINT32 Index
);

+/**
+ Executes a XSETBV instruction to write a 64-bit value to a Extended Control
Register(XCR),
+ and returns the value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by Index.
The
+ 64-bit value written to the XCR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU
exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmXSetBv (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );

/**
Executes a VMGEXIT instruction (VMMCALL with a REP prefix)

Executes a VMGEXIT instruction. This function is only available on IA-32 and
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c..fe8f68bbcf 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,9 +1,9 @@
## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -182,10 +182,11 @@
Ia32/LShiftU64.nasm| GCC
Ia32/EnableCache.nasm| GCC
Ia32/DisableCache.nasm| GCC
Ia32/RdRand.nasm
Ia32/XGetBv.nasm
+ Ia32/XSetBv.nasm
Ia32/VmgExit.nasm

Ia32/DivS64x64Remainder.c
Ia32/InternalSwitchStack.c | MSFT
Ia32/InternalSwitchStack.nasm | GCC
@@ -316,10 +317,11 @@
X64/GccInlinePriv.c | GCC
X64/EnableDisableInterrupts.nasm
X64/DisablePaging64.nasm
X64/RdRand.nasm
X64/XGetBv.nasm
+ X64/XSetBv.nasm
X64/VmgExit.nasm
ChkStkGcc.c | GCC

[Sources.EBC]
Ebc/CpuBreakpoint.c
diff --git a/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
new file mode 100644
index 0000000000..9fa2f761cd
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XSetBv.nasm
+;
+; Abstract:
+;
+; AsmXSetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXSetBv (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXSetBv)
+ASM_PFX(AsmXSetBv):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ xsetbv
+ ret
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/X64/XSetBv.nasm
b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
new file mode 100644
index 0000000000..aa72419e7f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XSetBv.nasm
+;
+; Abstract:
+;
+; AsmXSetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXSetBv (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXSetBv)
+ASM_PFX(AsmXSetBv):
+ mov rax, rdx ; meanwhile, rax <- return value
+ shr rdx, 0x20 ; edx:eax contains the value to write
+ xsetbv
+ ret
\ No newline at end of file
--
2.16.2.windows.1





Re: [RFC PATCH 12/19] OvmfPkg/MemEncryptSevLib: Add support to validate system RAM

Brijesh Singh
 

Hi Yao,

On 4/1/21 1:37 AM, Yao, Jiewen wrote:
Hi
Would you please clarify why the IA32 version implementation is empty?

Does it mean IA32 does not need validate?
Or IA32 should never call this function?

Anyway, I recommend to add some comment to describe it clearly.
If it should never be called, I recommend to add ASSERT(FALSE).

AMD SEV, SEV-ES and SEV-SNP support is not available for the IA32
architecture. Nobody should be calling it. I will add an ASSERT().

Thanks


+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/SnpPageStateChange.c
@@ -0,0 +1,17 @@
+#include <Uefi/UefiBaseType.h>
+
+#include "../SnpPageStateChange.h"
+
+/**
+ The function is used to set the page state when SEV-SNP is active. The page state
+ transition consist of changing the page ownership in the RMP table, and using the
+ PVALIDATE instruction to update the Validated bit in RMP table.
+
+ */
+VOID
+SevSnpValidateSystemRamInternal (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ )
+{
+}

-----Original Message-----
From: Brijesh Singh <brijesh.singh@...>
Sent: Wednesday, March 24, 2021 11:32 PM
To: devel@edk2.groups.io
Cc: Brijesh Singh <brijesh.singh@...>; James Bottomley
<jejb@...>; Xu, Min M <min.m.xu@...>; Yao, Jiewen
<jiewen.yao@...>; Tom Lendacky <thomas.lendacky@...>; Justen,
Jordan L <jordan.l.justen@...>; Ard Biesheuvel
<ardb+tianocore@...>; Laszlo Ersek <lersek@...>
Subject: [RFC PATCH 12/19] OvmfPkg/MemEncryptSevLib: Add support to
validate system RAM

BZ: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&;data=04%7C01%7Cbrijesh.singh%40amd.com%7C599bf9c821c94c0241ed08d8f4d8b2a5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637528558846316719%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=4Lq97rE69lPFAsGjYb44e3u2mA9QlrJdayxTP9FG7w8%3D&amp;reserved=0

Many of the integrity guarantees of SEV-SNP are enforced through the
Reverse Map Table (RMP). Each RMP entry contains the GPA at which a
particular page of DRAM should be mapped. The guest can request the
hypervisor to add pages in the RMP table via the Page State Change VMGEXIT
defined in the GHCB specification section 2.5.1 and 4.1.6. Inside each RMP
entry is a Validated flag; this flag is automatically cleared to 0 by the
CPU hardware when a new RMP entry is created for a guest. Each VM page
can be either validated or invalidated, as indicated by the Validated
flag in the RMP entry. Memory access to a private page that is not
validated generates a #VC. A VM can use the PVALIDATE instruction to
validate the private page before using it.

During the guest creation, the boot ROM memory is pre-validated by the
AMD-SEV firmware. The MemEncryptSevSnpValidateSystemRam() can be called
during the SEC and PEI phase to validate the detected system RAM.

One of the fields in the Page State Change NAE is the RMP page size. The
page size input parameter indicates that either a 4KB or 2MB page should
be used while adding the RMP entry. During the validation, when possible,
the MemEncryptSevSnpValidateSystemRam() will use the 2MB entry. A
hypervisor backing the memory may choose to use the different page size
in the RMP entry. In those cases, the PVALIDATE instruction should return
SIZEMISMATCH. If a SIZEMISMATCH is detected, then validate all 512-pages
constituting a 2MB region.

Upon completion, the PVALIDATE instruction sets the rFLAGS.CF to 0 if
instruction changed the RMP entry and to 1 if the instruction did not
change the RMP entry. The rFlags.CF will be 1 only when a memory region
is already validated. We should not double validate a memory
as it could lead to a security compromise. If double validation is
detected, terminate the boot.

Cc: James Bottomley <jejb@...>
Cc: Min Xu <min.m.xu@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Laszlo Ersek <lersek@...>
Signed-off-by: Brijesh Singh <brijesh.singh@...>
---
OvmfPkg/Include/Library/MemEncryptSevLib.h | 15 ++
OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/SnpPageStateChange.c | 17
++
OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf | 4 +
OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c |
20 ++
OvmfPkg/Library/BaseMemEncryptSevLib/SnpPageStateChange.h | 37
+++
OvmfPkg/Library/BaseMemEncryptSevLib/X64/SecSnpSystemRamValidate.c |
23 ++
OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChangeInternal.c |
254 ++++++++++++++++++++
7 files changed, 370 insertions(+)

diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h
b/OvmfPkg/Include/Library/MemEncryptSevLib.h
index 03d9eda392..47d6802b61 100644
--- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
+++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
@@ -215,4 +215,19 @@ MemEncryptSevGetAddressRangeState (
IN UINTN Length
);

+/**
+ If SEV-SNP is active then set the page state of the specified virtual
+ address range. This should be called in SEC and PEI phases only.
+
+ @param[in] BaseAddress Base address
+ @param[in] NumPages Number of pages starting from the base
address
+
+**/
+VOID
+EFIAPI
+MemEncryptSevSnpValidateSystemRam (
+ IN PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ );
+
#endif // _MEM_ENCRYPT_SEV_LIB_H_
diff --git
a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/SnpPageStateChange.c
b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/SnpPageStateChange.c
new file mode 100644
index 0000000000..dace5c0bcf
--- /dev/null
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/SnpPageStateChange.c
@@ -0,0 +1,17 @@
+#include <Uefi/UefiBaseType.h>
+
+#include "../SnpPageStateChange.h"
+
+/**
+ The function is used to set the page state when SEV-SNP is active. The page
state
+ transition consist of changing the page ownership in the RMP table, and using
the
+ PVALIDATE instruction to update the Validated bit in RMP table.
+
+ */
+VOID
+SevSnpValidateSystemRamInternal (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ )
+{
+}
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf
b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf
index 279c38bfbc..8595e244c2 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLib.inf
@@ -31,15 +31,19 @@

[Sources]
SecMemEncryptSevLibInternal.c
+ SnpPageStateChange.h

[Sources.X64]
X64/MemEncryptSevLib.c
X64/SecVirtualMemory.c
+ X64/SecSnpSystemRamValidate.c
+ X64/SnpPageStateChangeInternal.c
X64/VirtualMemory.c
X64/VirtualMemory.h

[Sources.IA32]
Ia32/MemEncryptSevLib.c
+ Ia32/SnpPageStateChange.c

[LibraryClasses]
BaseLib
diff --git
a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
index 69852779e2..35a222e75e 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
+++
b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
@@ -17,6 +17,8 @@
#include <Register/Cpuid.h>
#include <Uefi/UefiBaseType.h>

+#include "SnpPageStateChange.h"
+
/**
Reads and sets the status of SEV features.

@@ -172,3 +174,21 @@
MemEncryptSevLocateInitialSmramSaveStateMapPages (
{
return RETURN_UNSUPPORTED;
}
+
+/**
+ If SEV-SNP is active then set the page state of the specified virtual
+ address range. This should be called in SEC and PEI phases only.
+
+ @param[in] BaseAddress Base address
+ @param[in] NumPages Number of pages starting from the base
address
+
+**/
+VOID
+EFIAPI
+MemEncryptSevSnpValidateSystemRam (
+ IN PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ )
+{
+ SevSnpValidateSystemRam (BaseAddress, NumPages);
+}
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/SnpPageStateChange.h
b/OvmfPkg/Library/BaseMemEncryptSevLib/SnpPageStateChange.h
new file mode 100644
index 0000000000..3040930999
--- /dev/null
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/SnpPageStateChange.h
@@ -0,0 +1,37 @@
+/** @file
+
+ SEV-SNP Page Validation functions.
+
+ Copyright (c) 2020 - 2021, AMD Incorporated. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SNP_PAGE_STATE_INTERNAL_H_
+#define SNP_PAGE_STATE_INTERNAL_H_
+
+//
+// SEV-SNP Page states
+//
+typedef enum {
+ SevSnpPagePrivate,
+ SevSnpPageShared,
+
+} SEV_SNP_PAGE_STATE;
+
+VOID
+SevSnpValidateSystemRam (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ );
+
+VOID
+SetPageStateInternal (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages,
+ IN SEV_SNP_PAGE_STATE State,
+ IN BOOLEAN UseLargeEntry
+ );
+
+#endif
diff --git
a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SecSnpSystemRamValidate.c
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SecSnpSystemRamValidate.c
new file mode 100644
index 0000000000..915706aad0
--- /dev/null
+++
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SecSnpSystemRamValidate.c
@@ -0,0 +1,23 @@
+/** @file
+
+ SEV-SNP Page Validation functions.
+
+ Copyright (c) 2020 - 2021, AMD Incorporated. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+
+#include "../SnpPageStateChange.h"
+
+VOID
+SevSnpValidateSystemRam (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages
+ )
+{
+ SetPageStateInternal (BaseAddress, NumPages, SevSnpPagePrivate, TRUE);
+}
diff --git
a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChangeInternal.c
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChangeInternal.c
new file mode 100644
index 0000000000..5a34db33fe
--- /dev/null
+++
b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChangeInternal.c
@@ -0,0 +1,254 @@
+/** @file
+
+ SEV-SNP Page Validation functions.
+
+ Copyright (c) 2020 - 2021, AMD Incorporated. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemEncryptSevLib.h>
+#include <Library/DebugLib.h>
+#include <Library/VmgExitLib.h>
+
+#include <Register/Amd/Ghcb.h>
+#include <Register/Amd/Msr.h>
+
+#include "../SnpPageStateChange.h"
+
+#define IS_ALIGNED(x, y) ((((x) & (y - 1)) == 0))
+#define PAGES_PER_LARGE_ENTRY 512
+#define EFI_LARGE_PAGE (EFI_PAGE_SIZE * PAGES_PER_LARGE_ENTRY)
+
+STATIC
+UINTN
+MemoryStateToGhcbOp (
+ IN SEV_SNP_PAGE_STATE State
+ )
+{
+ UINTN Cmd;
+
+ switch (State) {
+ case SevSnpPageShared: Cmd = SNP_PAGE_STATE_SHARED; break;
+ case SevSnpPagePrivate: Cmd = SNP_PAGE_STATE_PRIVATE; break;
+ default: ASSERT(0);
+ }
+
+ return Cmd;
+}
+
+STATIC
+VOID
+SnpPageStateFailureTerminate (
+ VOID
+ )
+{
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+
+ //
+ // Use the GHCB MSR Protocol to request termination by the hypervisor
+ //
+ Msr.GhcbPhysicalAddress = 0;
+ Msr.GhcbTerminate.Function = GHCB_INFO_TERMINATE_REQUEST;
+ Msr.GhcbTerminate.ReasonCodeSet = GHCB_TERMINATE_GHCB;
+ Msr.GhcbTerminate.ReasonCode = GHCB_TERMINATE_GHCB_GENERAL;
+ AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress);
+
+ AsmVmgExit ();
+
+ ASSERT (FALSE);
+ CpuDeadLoop ();
+}
+
+STATIC
+UINTN
+IssuePvalidate (
+ IN UINTN Address,
+ IN UINTN RmpPageSize,
+ IN BOOLEAN Validate
+ )
+{
+ IA32_EFLAGS32 EFlags;
+ UINTN Ret;
+
+ Ret = AsmPvalidate (RmpPageSize, Validate, Address, &EFlags);
+
+ //
+ // Check the rFlags.CF to verify that PVALIDATE updated the RMP
+ // entry. If there was a no change in the RMP entry then we are
+ // either double validating or invalidating the memory. This can
+ // lead to a security compromise.
+ //
+ if (EFlags.Bits.CF) {
+ DEBUG ((DEBUG_ERROR, "%a:%a: Double %a detected for address 0x%Lx\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Validate ? "Validate" : "Invalidate",
+ Address));
+ SnpPageStateFailureTerminate ();
+ }
+
+ return Ret;
+}
+
+/**
+ This function issues the PVALIDATE instruction to validate or invalidate the
memory
+ range specified. If PVALIDATE returns size mismatch then it tries validating
with
+ smaller page size.
+
+ */
+STATIC
+VOID
+PvalidateRange (
+ IN SNP_PAGE_STATE_CHANGE_INFO *Info,
+ IN UINTN StartIndex,
+ IN UINTN EndIndex,
+ IN BOOLEAN Validate
+ )
+{
+ UINTN Address, RmpPageSize, Ret, i;
+
+ for (; StartIndex < EndIndex; StartIndex++) {
+ Address = Info->Entry[StartIndex].GuestFrameNumber << EFI_PAGE_SHIFT;
+ RmpPageSize = Info->Entry[StartIndex].PageSize;
+
+ Ret = IssuePvalidate (Address, RmpPageSize, Validate);
+
+ //
+ // If we fail to validate due to size mismatch then try with the
+ // smaller page size. This senario will occur if the backing page in
+ // the RMP entry is 4K and we are validating it as a 2MB.
+ //
+ if ((Ret == PVALIDATE_RET_FAIL_SIZEMISMATCH) &&
+ (RmpPageSize == PVALIDATE_PAGE_SIZE_2M)) {
+ for (i = 0; i < PAGES_PER_LARGE_ENTRY; i++) {
+
+ Ret = IssuePvalidate (Address, PVALIDATE_PAGE_SIZE_4K, Validate);
+ if (Ret) {
+ break;
+ }
+
+ Address = Address + EFI_PAGE_SIZE;
+ }
+ }
+
+ if (Ret) {
+ DEBUG ((DEBUG_ERROR, "%a:%a: Failed to %a address 0x%Lx Error
code %d\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ Validate ? "Validate" : "Invalidate",
+ Address,
+ Ret));
+ SnpPageStateFailureTerminate ();
+ }
+ }
+}
+
+/**
+ The function is used to set the page state when SEV-SNP is active. The page
state
+ transition consist of changing the page ownership in the RMP table, and using
the
+ PVALIDATE instruction to update the Validated bit in RMP table.
+
+ When the UseLargeEntry is set to TRUE, then use the large RMP entry.
+ */
+VOID
+SetPageStateInternal (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINTN NumPages,
+ IN SEV_SNP_PAGE_STATE State,
+ IN BOOLEAN UseLargeEntry
+ )
+{
+ EFI_STATUS Status;
+ GHCB *Ghcb;
+ EFI_PHYSICAL_ADDRESS NextAddress, EndAddress;
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+ BOOLEAN InterruptState;
+ SNP_PAGE_STATE_CHANGE_INFO *Info;
+ UINTN i, RmpPageSize;
+
+ Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
+ Ghcb = Msr.Ghcb;
+
+ EndAddress = BaseAddress + EFI_PAGES_TO_SIZE (NumPages);
+
+ DEBUG ((DEBUG_VERBOSE, "%a:%a Address 0x%Lx - 0x%Lx State = %a
LargeEntry = %d\n",
+ gEfiCallerBaseName,
+ __FUNCTION__,
+ BaseAddress,
+ EndAddress,
+ State == SevSnpPageShared ? "Shared" : "Private",
+ UseLargeEntry));
+
+ for (; BaseAddress < EndAddress; BaseAddress = NextAddress) {
+
+ //
+ // Initialize the GHCB and setup scratch sw to point to shared buffer.
+ //
+ VmgInit (Ghcb, &InterruptState);
+ Info = (SNP_PAGE_STATE_CHANGE_INFO *) Ghcb->SharedBuffer;
+
+ SetMem (Info, sizeof (*Info), 0);
+
+ //
+ // Build page state change buffer
+ //
+ for (i = 0; (EndAddress > BaseAddress) && i < SNP_PAGE_STATE_MAX_ENTRY;
+ BaseAddress = NextAddress, i++) {
+ //
+ // Is this a 2MB aligned page? Check if we can use the Large RMP entry.
+ //
+ if (UseLargeEntry &&
+ IS_ALIGNED (BaseAddress, EFI_LARGE_PAGE) &&
+ ((EndAddress - BaseAddress) >> EFI_PAGE_SHIFT) >=
PAGES_PER_LARGE_ENTRY) {
+ RmpPageSize = PVALIDATE_PAGE_SIZE_2M;
+ NextAddress = BaseAddress + EFI_LARGE_PAGE;
+ } else {
+ RmpPageSize = PVALIDATE_PAGE_SIZE_4K;
+ NextAddress = BaseAddress + EFI_PAGE_SIZE;
+ }
+
+ Info->Entry[i].GuestFrameNumber = BaseAddress >> EFI_PAGE_SHIFT;
+ Info->Entry[i].PageSize = RmpPageSize;
+ Info->Entry[i].Op = MemoryStateToGhcbOp (State);
+ Info->Entry[i].CurrentPage = 0;
+ }
+
+ Info->Header.CurrentEntry = 0;
+ Info->Header.EndEntry = i - 1;
+
+ //
+ // If the request page state change is shared then invalidate the pages before
+ // adding the page in the RMP table.
+ //
+ if (State == SevSnpPageShared) {
+ PvalidateRange (Info, 0, i, FALSE);
+ }
+
+ //
+ // Issue the VMGEXIT and retry if hypervisor failed to process all the entries.
+ //
+ Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ VmgSetOffsetValid (Ghcb, GhcbSwScratch);
+ while (Info->Header.CurrentEntry <= Info->Header.EndEntry) {
+ Status = VmgExit (Ghcb, SVM_EXIT_SNP_PAGE_STATE_CHANGE, 0, 0);
+ if (EFI_ERROR (Status)) {
+ SnpPageStateFailureTerminate ();
+ }
+ }
+
+ //
+ // If the request page state change is shared then invalidate the pages before
+ // adding the page in the RMP table.
+ //
+ if (State == SevSnpPagePrivate) {
+ PvalidateRange (Info, 0, i, TRUE);
+ }
+
+ VmgDone (Ghcb, InterruptState);
+ }
+}
--
2.17.1


Re: [PATCH v1 1/1] UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.

Jason Lou
 

1. Since the time it takes to find specified GUID Extension Hob (CpuCrystalFrequencyHob: about 2000ns)
is much longer than it takes to calculate TSC frequency with CPUID (about 450ns), I recommend using
BaseCpuTimerLib instead of PeiCpuTimerLib.

2. The time it takes to get TSC frequency from global variable is shorter than it takes to calculate TSC
frequency with CPUID, but 450ns is really a short time, the impact on the platform is very limited.
In addition, in order to simplify the code, recommend using BaseCpuTimerLib instead of DxeCpuTimerLib.

If anyone has questions or concerns, please feel free to let me know. If not, I will submit code patch later,
thanks.

Jason Lou