Date   

[PATCH v8 04/10] SecurityPkg/Tcg: Make Tcg2PlatformDxe buildable and fix style issues

Stefan Berger <stefanb@...>
 

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h | 4 ++--
.../PeiDxeTpmPlatformHierarchyLib.c | 2 +-
SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 3 +--
3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h b/Securi=
tyPkg/Include/Library/TpmPlatformHierarchyLib.h
index a872fa09dc..8d61a4867b 100644
--- a/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
+++ b/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
@@ -11,8 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
=0D
**/=0D
=0D
-#ifndef _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
-#define _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+#ifndef TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+#define TPM_PLATFORM_HIERARCHY_LIB_H_=0D
=0D
/**=0D
This service will perform the TPM Platform Hierarchy configuration at t=
he SmmReadyToLock event.=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pei=
DxeTpmPlatformHierarchyLib.c
index d82a0ae1bd..0bb04a20fc 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
@@ -233,7 +233,7 @@ DisableTpmPlatformHierarchy (
=0D
/**=0D
This service defines the configuration of the Platform Hierarchy Author=
ization Value (platformAuth)=0D
- and Platform Hierarchy Authorization Policy (platformPolicy)=0D
+ and Platform Hierarchy Authorization Policy (platformPolicy).=0D
=0D
**/=0D
VOID=0D
diff --git a/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf b/Security=
Pkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
index af29c1cd98..635302fe6f 100644
--- a/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+++ b/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
@@ -1,4 +1,4 @@
-### @file=0D
+## @file=0D
# Platform specific TPM2 component.=0D
#=0D
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>=0D
@@ -31,7 +31,6 @@
[Packages]=0D
MdePkg/MdePkg.dec=0D
MdeModulePkg/MdeModulePkg.dec=0D
- MinPlatformPkg/MinPlatformPkg.dec=0D
SecurityPkg/SecurityPkg.dec=0D
=0D
[Sources]=0D
--=20
2.31.1


[PATCH v8 02/10] SecurityPkg/TPM: Fix bugs in imported PeiDxeTpmPlatformHierarchyLib

Stefan Berger <stefanb@...>
 

Fix some bugs in the original PeiDxeTpmPlatformHierarchyLib.c.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.c | 23 +++++--------------
.../PeiDxeTpmPlatformHierarchyLib.inf | 5 ++--
2 files changed, 8 insertions(+), 20 deletions(-)

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pei=
DxeTpmPlatformHierarchyLib.c
index 9812ab99ab..d82a0ae1bd 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
@@ -18,7 +18,6 @@
#include <Library/BaseMemoryLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
-#include <Library/PcdLib.h>=0D
#include <Library/RngLib.h>=0D
#include <Library/Tpm2CommandLib.h>=0D
#include <Library/Tpm2DeviceLib.h>=0D
@@ -27,7 +26,6 @@
// The authorization value may be no larger than the digest produced by th=
e hash=0D
// algorithm used for context integrity.=0D
//=0D
-#define MAX_NEW_AUTHORIZATION_SIZE SHA512_DIGEST_SIZE=0D
=0D
UINT16 mAuthSize;=0D
=0D
@@ -54,7 +52,7 @@ RdRandGenerateEntropy (
UINT8 *Ptr;=0D
=0D
Status =3D EFI_NOT_READY;=0D
- BlockCount =3D Length / 64;=0D
+ BlockCount =3D Length / sizeof(Seed);=0D
Ptr =3D (UINT8 *)Entropy;=0D
=0D
//=0D
@@ -65,10 +63,10 @@ RdRandGenerateEntropy (
if (EFI_ERROR (Status)) {=0D
return Status;=0D
}=0D
- CopyMem (Ptr, Seed, 64);=0D
+ CopyMem (Ptr, Seed, sizeof(Seed));=0D
=0D
BlockCount--;=0D
- Ptr =3D Ptr + 64;=0D
+ Ptr =3D Ptr + sizeof(Seed);=0D
}=0D
=0D
//=0D
@@ -78,7 +76,7 @@ RdRandGenerateEntropy (
if (EFI_ERROR (Status)) {=0D
return Status;=0D
}=0D
- CopyMem (Ptr, Seed, (Length % 64));=0D
+ CopyMem (Ptr, Seed, (Length % sizeof(Seed)));=0D
=0D
return Status;=0D
}=0D
@@ -164,8 +162,6 @@ RandomizePlatformAuth (
{=0D
EFI_STATUS Status;=0D
UINT16 AuthSize;=0D
- UINT8 *Rand;=0D
- UINTN RandSize;=0D
TPM2B_AUTH NewPlatformAuth;=0D
=0D
//=0D
@@ -174,19 +170,13 @@ RandomizePlatformAuth (
=0D
GetAuthSize (&AuthSize);=0D
=0D
- ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
NewPlatformAuth.size =3D AuthSize;=0D
=0D
//=0D
- // Allocate one buffer to store random data.=0D
+ // Create the random bytes in the destination buffer=0D
//=0D
- RandSize =3D MAX_NEW_AUTHORIZATION_SIZE;=0D
- Rand =3D AllocatePool (RandSize);=0D
-=0D
- RdRandGenerateEntropy (RandSize, Rand);=0D
- CopyMem (NewPlatformAuth.buffer, Rand, AuthSize);=0D
=0D
- FreePool (Rand);=0D
+ RdRandGenerateEntropy (NewPlatformAuth.size, NewPlatformAuth.buffer);=0D
=0D
//=0D
// Send Tpm2HierarchyChangeAuth command with the new Auth value=0D
@@ -194,7 +184,6 @@ RandomizePlatformAuth (
Status =3D Tpm2HierarchyChangeAuth (TPM_RH_PLATFORM, NULL, &NewPlatformA=
uth);=0D
DEBUG ((DEBUG_INFO, "Tpm2HierarchyChangeAuth Result: - %r\n", Status));=
=0D
ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
- ZeroMem (Rand, RandSize);=0D
}=0D
=0D
/**=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P=
eiDxeTpmPlatformHierarchyLib.inf
index b7a7fb0a08..7bf666794f 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
@@ -1,6 +1,5 @@
-### @file=0D
-#=0D
-# TPM Platform Hierarchy configuration library.=0D
+## @file=0D
+# TPM Platform Hierarchy configuration library.=0D
#=0D
# This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
# Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
--=20
2.31.1


[PATCH v8 01/10] SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from edk2-platforms

Stefan Berger <stefanb@...>
 

Import PeiDxeTpmPlatformHierarchyLib from edk2-platforms without any
modifications.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 266 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 45 +++
3 files changed, 338 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDx=
eTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDx=
eTpmPlatformHierarchyLib.inf

diff --git a/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h b/Securi=
tyPkg/Include/Library/TpmPlatformHierarchyLib.h
new file mode 100644
index 0000000000..a872fa09dc
--- /dev/null
+++ b/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
@@ -0,0 +1,27 @@
+/** @file=0D
+ TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+ Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+ Policy (platformPolicy) can be defined through this function.=0D
+=0D
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) Microsoft Corporation.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+#define _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+=0D
+/**=0D
+ This service will perform the TPM Platform Hierarchy configuration at t=
he SmmReadyToLock event.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ VOID=0D
+ );=0D
+=0D
+#endif=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pei=
DxeTpmPlatformHierarchyLib.c
new file mode 100644
index 0000000000..9812ab99ab
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
@@ -0,0 +1,266 @@
+/** @file=0D
+ TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+ Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+ Policy (platformPolicy) can be defined through this function.=0D
+=0D
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) Microsoft Corporation.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+ @par Specification Reference:=0D
+ https://trustedcomputinggroup.org/resource/tcg-tpm-v2-0-provisioning-g=
uidance/=0D
+**/=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <Library/RngLib.h>=0D
+#include <Library/Tpm2CommandLib.h>=0D
+#include <Library/Tpm2DeviceLib.h>=0D
+=0D
+//=0D
+// The authorization value may be no larger than the digest produced by th=
e hash=0D
+// algorithm used for context integrity.=0D
+//=0D
+#define MAX_NEW_AUTHORIZATION_SIZE SHA512_DIGEST_SIZE=0D
+=0D
+UINT16 mAuthSize;=0D
+=0D
+/**=0D
+ Generate high-quality entropy source through RDRAND.=0D
+=0D
+ @param[in] Length Size of the buffer, in bytes, to fill with.=0D
+ @param[out] Entropy Pointer to the buffer to store the entropy da=
ta.=0D
+=0D
+ @retval EFI_SUCCESS Entropy generation succeeded.=0D
+ @retval EFI_NOT_READY Failed to request random data.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+RdRandGenerateEntropy (=0D
+ IN UINTN Length,=0D
+ OUT UINT8 *Entropy=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN BlockCount;=0D
+ UINT64 Seed[2];=0D
+ UINT8 *Ptr;=0D
+=0D
+ Status =3D EFI_NOT_READY;=0D
+ BlockCount =3D Length / 64;=0D
+ Ptr =3D (UINT8 *)Entropy;=0D
+=0D
+ //=0D
+ // Generate high-quality seed for DRBG Entropy=0D
+ //=0D
+ while (BlockCount > 0) {=0D
+ Status =3D GetRandomNumber128 (Seed);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ CopyMem (Ptr, Seed, 64);=0D
+=0D
+ BlockCount--;=0D
+ Ptr =3D Ptr + 64;=0D
+ }=0D
+=0D
+ //=0D
+ // Populate the remained data as request.=0D
+ //=0D
+ Status =3D GetRandomNumber128 (Seed);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ CopyMem (Ptr, Seed, (Length % 64));=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ This function returns the maximum size of TPM2B_AUTH; this structure is =
used for an authorization value=0D
+ and limits an authValue to being no larger than the largest digest produ=
ced by a TPM.=0D
+=0D
+ @param[out] AuthSize Tpm2 Auth size=0D
+=0D
+ @retval EFI_SUCCESS Auth size returned.=0D
+ @retval EFI_DEVICE_ERROR Can not return platform auth due to=
device error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+GetAuthSize (=0D
+ OUT UINT16 *AuthSize=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ TPML_PCR_SELECTION Pcrs;=0D
+ UINTN Index;=0D
+ UINT16 DigestSize;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ while (mAuthSize =3D=3D 0) {=0D
+=0D
+ mAuthSize =3D SHA1_DIGEST_SIZE;=0D
+ ZeroMem (&Pcrs, sizeof (TPML_PCR_SELECTION));=0D
+ Status =3D Tpm2GetCapabilityPcrs (&Pcrs);=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs fail!\n"));=0D
+ break;=0D
+ }=0D
+=0D
+ DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs - %08x\n", Pcrs.count));=0D
+=0D
+ for (Index =3D 0; Index < Pcrs.count; Index++) {=0D
+ DEBUG ((DEBUG_ERROR, "alg - %x\n", Pcrs.pcrSelections[Index].hash));=
=0D
+=0D
+ switch (Pcrs.pcrSelections[Index].hash) {=0D
+ case TPM_ALG_SHA1:=0D
+ DigestSize =3D SHA1_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA256:=0D
+ DigestSize =3D SHA256_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA384:=0D
+ DigestSize =3D SHA384_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA512:=0D
+ DigestSize =3D SHA512_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SM3_256:=0D
+ DigestSize =3D SM3_256_DIGEST_SIZE;=0D
+ break;=0D
+ default:=0D
+ DigestSize =3D SHA1_DIGEST_SIZE;=0D
+ break;=0D
+ }=0D
+=0D
+ if (DigestSize > mAuthSize) {=0D
+ mAuthSize =3D DigestSize;=0D
+ }=0D
+ }=0D
+ break;=0D
+ }=0D
+=0D
+ *AuthSize =3D mAuthSize;=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ Set PlatformAuth to random value.=0D
+**/=0D
+VOID=0D
+RandomizePlatformAuth (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT16 AuthSize;=0D
+ UINT8 *Rand;=0D
+ UINTN RandSize;=0D
+ TPM2B_AUTH NewPlatformAuth;=0D
+=0D
+ //=0D
+ // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth=
being null=0D
+ //=0D
+=0D
+ GetAuthSize (&AuthSize);=0D
+=0D
+ ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
+ NewPlatformAuth.size =3D AuthSize;=0D
+=0D
+ //=0D
+ // Allocate one buffer to store random data.=0D
+ //=0D
+ RandSize =3D MAX_NEW_AUTHORIZATION_SIZE;=0D
+ Rand =3D AllocatePool (RandSize);=0D
+=0D
+ RdRandGenerateEntropy (RandSize, Rand);=0D
+ CopyMem (NewPlatformAuth.buffer, Rand, AuthSize);=0D
+=0D
+ FreePool (Rand);=0D
+=0D
+ //=0D
+ // Send Tpm2HierarchyChangeAuth command with the new Auth value=0D
+ //=0D
+ Status =3D Tpm2HierarchyChangeAuth (TPM_RH_PLATFORM, NULL, &NewPlatformA=
uth);=0D
+ DEBUG ((DEBUG_INFO, "Tpm2HierarchyChangeAuth Result: - %r\n", Status));=
=0D
+ ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
+ ZeroMem (Rand, RandSize);=0D
+}=0D
+=0D
+/**=0D
+ Disable the TPM platform hierarchy.=0D
+=0D
+ @retval EFI_SUCCESS The TPM was disabled successfully.=0D
+ @retval Others An error occurred attempting to disable the =
TPM platform hierarchy.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+DisableTpmPlatformHierarchy (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ // Make sure that we have use of the TPM.=0D
+ Status =3D Tpm2RequestUseTpm ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "%a:%a() - Tpm2RequestUseTpm Failed! %r\n", gEfiC=
allerBaseName, __FUNCTION__, Status));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Let's do what we can to shut down the hierarchies.=0D
+=0D
+ // Disable the PH NV.=0D
+ // IMPORTANT NOTE: We *should* be able to disable the PH NV here, but TP=
M parts have=0D
+ // been known to store the EK cert in the PH NV. If we d=
isable it, the=0D
+ // EK cert will be unreadable.=0D
+=0D
+ // Disable the PH.=0D
+ Status =3D Tpm2HierarchyControl (=0D
+ TPM_RH_PLATFORM, // AuthHandle=0D
+ NULL, // AuthSession=0D
+ TPM_RH_PLATFORM, // Hierarchy=0D
+ NO // State=0D
+ );=0D
+ DEBUG ((DEBUG_VERBOSE, "%a:%a() - Disable PH =3D %r\n", gEfiCallerBaseN=
ame, __FUNCTION__, Status));=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "%a:%a() - Disable PH Failed! %r\n", gEfiCallerB=
aseName, __FUNCTION__, Status));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ This service defines the configuration of the Platform Hierarchy Author=
ization Value (platformAuth)=0D
+ and Platform Hierarchy Authorization Policy (platformPolicy)=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ )=0D
+{=0D
+ if (PcdGetBool (PcdRandomizePlatformHierarchy)) {=0D
+ //=0D
+ // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAu=
th being null=0D
+ //=0D
+ RandomizePlatformAuth ();=0D
+ } else {=0D
+ //=0D
+ // Disable the hierarchy entirely (do not randomize it)=0D
+ //=0D
+ DisableTpmPlatformHierarchy ();=0D
+ }=0D
+}=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P=
eiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 0000000000..b7a7fb0a08
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
@@ -0,0 +1,45 @@
+### @file=0D
+#=0D
+# TPM Platform Hierarchy configuration library.=0D
+#=0D
+# This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+# Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+# Policy (platformPolicy) can be defined through this function.=0D
+#=0D
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) Microsoft Corporation.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+###=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PeiDxeTpmPlatformHierarchyLib=0D
+ FILE_GUID =3D 7794F92C-4E8E-4E57-9E4A-49A0764C7D73=
=0D
+ MODULE_TYPE =3D PEIM=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D TpmPlatformHierarchyLib|PEIM DXE_DRIV=
ER=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ BaseMemoryLib=0D
+ DebugLib=0D
+ MemoryAllocationLib=0D
+ PcdLib=0D
+ RngLib=0D
+ Tpm2CommandLib=0D
+ Tpm2DeviceLib=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ SecurityPkg/SecurityPkg.dec=0D
+ CryptoPkg/CryptoPkg.dec=0D
+ MinPlatformPkg/MinPlatformPkg.dec=0D
+=0D
+[Sources]=0D
+ PeiDxeTpmPlatformHierarchyLib.c=0D
+=0D
+[Pcd]=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy=0D
--=20
2.31.1


[PATCH v8 03/10] SecrutiyPkg/Tcg: Import Tcg2PlatformDxe from edk2-platforms

Stefan Berger <stefanb@...>
 

Import Tcg2PlatformDxe from edk2-platforms without any modifications.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c | 85 +++++++++++++++++++
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 44 ++++++++++
2 files changed, 129 insertions(+)
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf

diff --git a/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c b/SecurityPk=
g/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
new file mode 100644
index 0000000000..150cf748ff
--- /dev/null
+++ b/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
@@ -0,0 +1,85 @@
+/** @file=0D
+ Platform specific TPM2 component for configuring the Platform Hierarchy.=
=0D
+=0D
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <PiDxe.h>=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>=0D
+#include <Protocol/DxeSmmReadyToLock.h>=0D
+=0D
+/**=0D
+ This callback function will run at the SmmReadyToLock event.=0D
+=0D
+ Configuration of the TPM's Platform Hierarchy Authorization Value (plat=
formAuth)=0D
+ and Platform Hierarchy Authorization Policy (platformPolicy) can be def=
ined through this function.=0D
+=0D
+ @param Event Pointer to this event=0D
+ @param Context Event hanlder private data=0D
+ **/=0D
+VOID=0D
+EFIAPI=0D
+SmmReadyToLockEventCallBack (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ VOID *Interface;=0D
+=0D
+ //=0D
+ // Try to locate it because EfiCreateProtocolNotifyEvent will trigger it=
once when registration.=0D
+ // Just return if it is not found.=0D
+ //=0D
+ Status =3D gBS->LocateProtocol (=0D
+ &gEfiDxeSmmReadyToLockProtocolGuid,=0D
+ NULL,=0D
+ &Interface=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return ;=0D
+ }=0D
+=0D
+ ConfigureTpmPlatformHierarchy ();=0D
+=0D
+ gBS->CloseEvent (Event);=0D
+}=0D
+=0D
+/**=0D
+ The driver's entry point. Will register a function for callback during =
SmmReadyToLock event to=0D
+ configure the TPM's platform authorization.=0D
+=0D
+ @param[in] ImageHandle The firmware allocated handle for the EFI image=
.=0D
+ @param[in] SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+ @retval other Some error occurs when executing this entry poi=
nt.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+Tcg2PlatformDxeEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ VOID *Registration;=0D
+ EFI_EVENT Event;=0D
+=0D
+ Event =3D EfiCreateProtocolNotifyEvent (=0D
+ &gEfiDxeSmmReadyToLockProtocolGuid,=0D
+ TPL_CALLBACK,=0D
+ SmmReadyToLockEventCallBack,=0D
+ NULL,=0D
+ &Registration=0D
+ );=0D
+=0D
+ ASSERT (Event !=3D NULL);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
diff --git a/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf b/Security=
Pkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
new file mode 100644
index 0000000000..af29c1cd98
--- /dev/null
+++ b/SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
@@ -0,0 +1,44 @@
+### @file=0D
+# Platform specific TPM2 component.=0D
+#=0D
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+###=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010017=0D
+ BASE_NAME =3D Tcg2PlatformDxe=0D
+ FILE_GUID =3D 5CAB08D5-AD8F-4d8b-B828-D17A8D9FE977=
=0D
+ VERSION_STRING =3D 1.0=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ ENTRY_POINT =3D Tcg2PlatformDxeEntryPoint=0D
+#=0D
+# The following information is for reference only and not required by the =
build tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64 IPF=0D
+#=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ UefiBootServicesTableLib=0D
+ UefiDriverEntryPoint=0D
+ DebugLib=0D
+ UefiLib=0D
+ TpmPlatformHierarchyLib=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ MinPlatformPkg/MinPlatformPkg.dec=0D
+ SecurityPkg/SecurityPkg.dec=0D
+=0D
+[Sources]=0D
+ Tcg2PlatformDxe.c=0D
+=0D
+[Protocols]=0D
+ gEfiDxeSmmReadyToLockProtocolGuid ## SOMETIMES_CONSUMES ## N=
OTIFY=0D
+=0D
+[Depex]=0D
+ gEfiTcg2ProtocolGuid=0D
--=20
2.31.1


[PATCH v8 00/10] Ovmf: Disable the TPM2 platform hierarchy

Stefan Berger <stefanb@...>
 

This series imports code from the edk2-platforms project related to
disabling the TPM2 platform hierarchy in Ovmf. It addresses the Ovmf
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

I have patched the .dsc files and successfully test-built with most of
them. Some I could not build because they failed for other reasons
unrelated to this series.

I tested the changes with QEMU on x86 following the build of
OvmfPkgX64.dsc.

Neither one of the following commands should work anymore on first
try when run on Linux:

With IBM tss2 tools:
tsshierarchychangeauth -hi p -pwdn newpass

With Intel tss2 tools:
tpm2_changeauth -c platform newpass

Regards,
Stefan

v8:
- Fixed style issue in imported code; added patch 10

v7:
- Ditched ARM support in this series
- Using Tcg2PlatformDxe and Tcg2PlaformPei from edk2-platforms now
and revised most of the patches

v6:
- Removed unnecessary entries in .dsc files
- Added support for S3 resume failure case
- Assigned unique FILE_GUID to NULL implementation

v5:
- Modified patch 1 copies the code from edk2-platforms
- Modified patch 2 fixes bugs in the code
- Modified patch 4 introduces required PCD

v4:
- Fixed and simplified code imported from edk2-platforms

v3:
- Referencing Null implementation on Bhyve and Xen platforms
- Add support in Arm



Stefan Berger (10):
SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
SecurityPkg/TPM: Fix bugs in imported PeiDxeTpmPlatformHierarchyLib
SecrutiyPkg/Tcg: Import Tcg2PlatformDxe from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformDxe buildable and fix style issues
SecurityPkg: Introduce new PCD PcdRandomizePlatformHierarchy
OvmfPkg: Reference new Tcg2PlatformDxe in the build system for
compilation
SecurityPkg/Tcg: Import Tcg2PlatformPei from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformPei buildable and fix style issues
OvmfPkg: Reference new Tcg2PlatformPei in the build system
SecurityPkg: Add references to header and inf files to SecurityPkg

OvmfPkg/AmdSev/AmdSevX64.dsc | 8 +
OvmfPkg/AmdSev/AmdSevX64.fdf | 2 +
OvmfPkg/OvmfPkgIa32.dsc | 8 +
OvmfPkg/OvmfPkgIa32.fdf | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 8 +
OvmfPkg/OvmfPkgIa32X64.fdf | 2 +
OvmfPkg/OvmfPkgX64.dsc | 8 +
OvmfPkg/OvmfPkgX64.fdf | 2 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 255 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 43 +++
SecurityPkg/SecurityPkg.dec | 10 +
SecurityPkg/SecurityPkg.dsc | 12 +
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c | 85 ++++++
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 43 +++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c | 108 ++++++++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf | 52 ++++
17 files changed, 675 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf

--
2.31.1


[PATCH] Platform/Qemu/Sbsa: Update TF-A binaries with QEMU "max" cpu support

Marcin Juszkiewicz <marcin@...>
 

Update the TF-A binaries with support for QEMU "max" cpu.
This support was merged into TF-A:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9113

This allows to test SBSA Reference Platform with newer CPU features than
Cortex-A72 has.
---
Platform/Qemu/Sbsa/bl1.bin | Bin 19221 -> 19301 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 54002 -> 54002 bytes
2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
index f01cc8223e1550d056632a7e6b1e72658c6da9d2..314bd4cc28c5c14e3d6d02849=
666a66f94347f5c 100755
GIT binary patch
delta 4706
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diff --git a/Platform/Qemu/Sbsa/fip.bin b/Platform/Qemu/Sbsa/fip.bin
index 0132a1c2f7adc09d44fdf85ab1ab63dc37df1ea1..d562013e4186dfafb7f3d7b3d=
56a994954f76ce7 100644
GIT binary patch
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--=20
2.32.0


Re: [PATCH v3 1/2] Ext4Pkg: Improve Ext4IsBindingSupported() behavior

Pedro Falcato
 

On BY_DRIVER, Jeff reached the conclusion that we can't open the
BLOCK_IO protocol with BY_DRIVER since it's already owned by
DiskIoDxe. The finding makes sense and is consistent
with FatPkg's behaviour.
As for the GET_PROTOCOL issue, feel free to send a patch ;)

On Sun, Sep 12, 2021 at 11:40 AM Marvin Häuser <mhaeuser@posteo.de> wrote:

On 11/09/2021 00:11, Jeff Brasen via groups.io wrote:
A couple of improvements to improve performance.
Add check to return ACCESS_DENIED if already connected
Add check to verify superblock magic during supported to reduce start calls

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
---
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h | 14 +++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c | 54 +++++++++++++++++++++------
Features/Ext4Pkg/Ext4Dxe/Superblock.c | 35 +++++++++++++++++
3 files changed, 92 insertions(+), 11 deletions(-)

diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
index 64eab455db..a9b932ed52 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
@@ -1117,4 +1117,18 @@ Ext4GetVolumeName (
OUT UINTN *VolNameLen
);

+/**
+ Checks the superblock's magic value.
+
+ @param[in] DiskIo Pointer to the DiskIo.
+ @param[in] BlockIo Pointer to the BlockIo.
+
+ @returns Whether the partition has a valid EXT4 superblock magic value.
+**/
+BOOLEAN
+Ext4SuperblockCheckMagic (
+ IN EFI_DISK_IO_PROTOCOL *DiskIo,
+ IN EFI_BLOCK_IO_PROTOCOL *BlockIo
+ );
+
#endif
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c
index ea2e048d77..d9fbe9ea78 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c
@@ -631,7 +631,6 @@ Ext4Unload (
@retval EFI_ACCESS_DENIED The device specified by ControllerHandle and
RemainingDevicePath is already being managed by a different
driver or an application that requires exclusive access.
- Currently not implemented.
@retval EFI_UNSUPPORTED The device specified by ControllerHandle and
RemainingDevicePath is not supported by the driver specified by This.
**/
@@ -643,32 +642,65 @@ Ext4IsBindingSupported (
IN EFI_DEVICE_PATH *RemainingDevicePath OPTIONAL
)
{
- // Note to self: EFI_OPEN_PROTOCOL_TEST_PROTOCOL lets us not close the
- // protocol and ignore the output argument entirely
+ EFI_STATUS Status;
+ EFI_DISK_IO_PROTOCOL *DiskIo;
+ EFI_BLOCK_IO_PROTOCOL *BlockIo;

- EFI_STATUS Status;
+ DiskIo = NULL;
+ BlockIo = NULL;

+ //
+ // Open the IO Abstraction(s) needed to perform the supported test
+ //
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiDiskIoProtocolGuid,
- NULL,
- BindingProtocol->ImageHandle,
+ (VOID **) &DiskIo,
+ BindingProtocol->DriverBindingHandle,
ControllerHandle,
- EFI_OPEN_PROTOCOL_TEST_PROTOCOL
+ EFI_OPEN_PROTOCOL_BY_DRIVER
);

if (EFI_ERROR (Status)) {
return Status;
}
-
+ //
+ // Open the IO Abstraction(s) needed to perform the supported test
+ //
Status = gBS->OpenProtocol (
ControllerHandle,
&gEfiBlockIoProtocolGuid,
- NULL,
- BindingProtocol->ImageHandle,
+ (VOID **) &BlockIo,
+ BindingProtocol->DriverBindingHandle,
ControllerHandle,
- EFI_OPEN_PROTOCOL_TEST_PROTOCOL
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
);
+
+ if (!EFI_ERROR (Status)) {
+ if (!Ext4SuperblockCheckMagic (DiskIo, BlockIo)) {
+ Status = EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Close the I/O Abstraction(s) used to perform the supported test
+ //
+ if (DiskIo != NULL) {
+ gBS->CloseProtocol (
+ ControllerHandle,
+ &gEfiDiskIoProtocolGuid,
+ BindingProtocol->DriverBindingHandle,
+ ControllerHandle
+ );
+ }
+ if (BlockIo != NULL) {
+ gBS->CloseProtocol (
+ ControllerHandle,
+ &gEfiBlockIoProtocolGuid,
+ BindingProtocol->DriverBindingHandle,
+ ControllerHandle
+ );
+ }
GET_PROTOCOL protocols are not to be closed, I guess this was missed
when there was still the question whether to use BY_DRIVER for BlockIo.

Best regards,
Marvin

return Status;
}

diff --git a/Features/Ext4Pkg/Ext4Dxe/Superblock.c b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
index c321d8c3d8..0c965415c5 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Superblock.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
@@ -34,6 +34,41 @@ STATIC CONST UINT32 gSupportedIncompatFeat =
// this is desired, it's fairly trivial to look for EFI_VOLUME_CORRUPTED
// references and add some Ext4SignalCorruption function + function call.

+/**
+ Checks the superblock's magic value.
+
+ @param[in] DiskIo Pointer to the DiskIo.
+ @param[in] BlockIo Pointer to the BlockIo.
+
+ @returns Whether the partition has a valid EXT4 superblock magic value.
+**/
+BOOLEAN
+Ext4SuperblockCheckMagic (
+ IN EFI_DISK_IO_PROTOCOL *DiskIo,
+ IN EFI_BLOCK_IO_PROTOCOL *BlockIo
+ )
+{
+ UINT16 Magic;
+ EFI_STATUS Status;
+
+ Status = DiskIo->ReadDisk (
+ DiskIo,
+ BlockIo->Media->MediaId,
+ EXT4_SUPERBLOCK_OFFSET + OFFSET_OF (EXT4_SUPERBLOCK, s_magic),
+ sizeof (Magic),
+ &Magic
+ );
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+
+ if (Magic != EXT4_SIGNATURE) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
/**
Does brief validation of the ext4 superblock.
--
Pedro Falcato


Re: [PATCH v7 0/9] Ovmf: Disable the TPM2 platform hierarchy

Stefan Berger
 

On 9/10/21 10:46 PM, Yao, Jiewen wrote:
If you want, I would suggest to take 2 steps (2 separate patch sets).

1) To add the TCG2 platform auth handling the security pkg (just move the code from min-platform to securitypkg)
If nothing else is changed, it can be approved easily.

2) To enable QEMU support to make platform auth + TCG PP work together. (based upon 1)
Need consider how to do it in a secure way.
I am not clear what it's going to take to get this right. Is there are platform example that does things similar to Ovmf but does it in the right order?


Several packages are using BdsEntry() from here: https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Universal/BdsDxe/BdsEntry.c#L661

That's where the split of PlatformBootManagerBeforeConsole() and ...AfterConsole() comes from. It looks like we would have to do TPM PPI handling in the BeforeConsole function but cannot do it since there's no console at this point but end-of-dxe is triggered there and that SMM locking signal is also sent in that function.

EndOfDxe: https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c#L380

Smm Lock: https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c#L394


If we now move the console initialization ('Connect consoles') to 'before' PlatformBootManagerBeforeConsole() is that then correct? Or should the PPI module initialize the console when it needs it?

   Stefan




Thank you
Yao Jiewen

-----Original Message-----
From: Yao, Jiewen
Sent: Saturday, September 11, 2021 10:38 AM
To: Stefan Berger <stefanb@linux.ibm.com>; devel@edk2.groups.io;
stefanb@linux.vnet.ibm.com
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com
Subject: RE: [edk2-devel] [PATCH v7 0/9] Ovmf: Disable the TPM2 platform
hierarchy

Hi Stefan
I notice you signal EndOfDxe at PlatformBootManagerBeforeConsole()
https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBoo
tManagerLib/BdsPlatform.c#L380
I would say, if PP is done after EndOfDxe, then the order is NOT right.

This topic has been debated for years. Finally, we reach the conclusion with the
trusted console concept.

The recommended way is to connect *trusted console only* and process PP
before EndOfDxe, to ensure no 3rd party code can touch the platform hierarchy.
We did that at PlatformBootManagerBeforeConsole(). Here is console means all
console, including the trusted console and untrusted console populated by
untrusted device. The full console list can still be connected after EndOfDxe.
The platform can decide which console is trusted v.s. not-trusted.

Thank you
Yao Jiewen


-----Original Message-----
From: Stefan Berger <stefanb@linux.ibm.com>
Sent: Saturday, September 11, 2021 12:15 AM
To: Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io;
stefanb@linux.vnet.ibm.com
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com
Subject: Re: [edk2-devel] [PATCH v7 0/9] Ovmf: Disable the TPM2 platform
hierarchy


On 9/10/21 11:32 AM, Yao, Jiewen wrote:
According to the security policy, PP request must be processed before
EndOfDxe.
May I know when you trigger PP request?
OVMF has 3 implementations invoking it in
PlatformBootManagerAfterConsole():
https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBoo
tManagerLib/BdsPlatform.c#L1517

https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBoo
tManagerLibBhyve/BdsPlatform.c#L1451

https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PlatformBoo
tManagerLibGrub/BdsPlatform.c#L1316

  Stefan


Thank you
Yao Jiewen

-----Original Message-----
From: Stefan Berger <stefanb@linux.ibm.com>
Sent: Friday, September 10, 2021 10:25 PM
To: devel@edk2.groups.io; stefanb@linux.vnet.ibm.com
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com; Yao, Jiewen
<jiewen.yao@intel.com>
Subject: Re: [edk2-devel] [PATCH v7 0/9] Ovmf: Disable the TPM2 platform
hierarchy


On 9/9/21 1:35 PM, Stefan Berger wrote:
This series imports code from the edk2-platforms project related to
disabling the TPM2 platform hierarchy in Ovmf. It addresses the Ovmf
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

I have patched the .dsc files and successfully test-built with most of
them. Some I could not build because they failed for other reasons
unrelated to this series.

I tested the changes with QEMU on x86 following the build of
OvmfPkgX64.dsc.

Neither one of the following commands should work anymore on first
try when run on Linux:

With IBM tss2 tools:
tsshierarchychangeauth -hi p -pwdn newpass

With Intel tss2 tools:
tpm2_changeauth -c platform newpass
While disabling the platform hierarchy works, the unfortunate problem is
now that the signal to disable the TPM 2 platform hierarchy is received
before handling the physical presence interface (PPI) opcodes, which is
bad because some of the opcodes will not go through. The question now is
what is wrong? Are the PPI opcodes handled too late or the signal is
sent to early or is it the wrong signal?

Event = EfiCreateProtocolNotifyEvent (
            &gEfiDxeSmmReadyToLockProtocolGuid,
            TPL_CALLBACK,
            SmmReadyToLockEventCallBack,
            NULL,
            &Registration
            );

   Stefan

Regards,
Stefan

v7:
- Ditched ARM support in this series
- Using Tcg2PlatformDxe and Tcg2PlaformPei from edk2-platforms now
and revised most of the patches

v6:
- Removed unnecessary entries in .dsc files
- Added support for S3 resume failure case
- Assigned unique FILE_GUID to NULL implementation

v5:
- Modified patch 1 copies the code from edk2-platforms
- Modified patch 2 fixes bugs in the code
- Modified patch 4 introduces required PCD

v4:
- Fixed and simplified code imported from edk2-platforms

v3:
- Referencing Null implementation on Bhyve and Xen platforms
- Add support in Arm


Stefan Berger (9):
SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
SecurityPkg/TPM: Fix bugs in imported PeiDxeTpmPlatformHierarchyLib
SecrutiyPkg/Tcg: Import Tcg2PlatformDxe from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformDxe buildable
SecurityPkg: Introduce new PCD PcdRandomizePlatformHierarchy
OvmfPkg: Reference new Tcg2PlatformDxe in the build system for
compilation
SecurityPkg/Tcg: Import Tcg2PlatformPei from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformPei buildable
OvmfPkg: Reference new Tcg2PlatformPei in the build system

OvmfPkg/AmdSev/AmdSevX64.dsc | 8 +
OvmfPkg/AmdSev/AmdSevX64.fdf | 2 +
OvmfPkg/OvmfPkgIa32.dsc | 8 +
OvmfPkg/OvmfPkgIa32.fdf | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 8 +
OvmfPkg/OvmfPkgIa32X64.fdf | 2 +
OvmfPkg/OvmfPkgX64.dsc | 8 +
OvmfPkg/OvmfPkgX64.fdf | 2 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 255 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 44 +++
SecurityPkg/SecurityPkg.dec | 6 +
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c | 85 ++++++
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 43 +++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c | 107 ++++++++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf | 51 ++++
16 files changed, 658 insertions(+)
create mode 100644
SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.c
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.inf
create mode 100644
SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
create mode 100644
SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
create mode 100644
SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
create mode 100644
SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf


Re: [PATCH v6 04/10] Silicon/Phytium: Added PciSegmentLib to FT2000/4

Leif Lindholm
 

Hi Ling,

Having had a look at this version, I propose folding in this change:

diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
index 273443fd5d68..124909cc015e 100644
--- a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
@@ -1286,9 +1286,8 @@ PciSegmentReadBuffer (
if ((StartAddress & BIT0) != 0) {
//
// Read a byte if StartAddress is byte aligned,
- // Volatile ensure that the latest values are read every time.
//
- *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ MmioWrite8 ((UINTN)Buffer, PciSegmentRead8 (StartAddress));
StartAddress += sizeof (UINT8);
Size -= sizeof (UINT8);
Buffer = (UINT8 *)Buffer + 1;
@@ -1328,7 +1327,7 @@ PciSegmentReadBuffer (
//
// Read the last remaining byte if exist
//
- *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ MmioWrite8 ((UINTN)Buffer, PciSegmentRead8 (StartAddress));
}

return ReturnValue;



If you are OK with that, I feel that patches 1-6 and 9-10 are ready to
be merged.

I would like to discuss 7/10 to see if we can improve the readability
of the code, based on the additional information you provided.
(And I think there is no point to include 8/10 without 7/10?)

Best Regards,

Leif

On Fri, Sep 10, 2021 at 16:20:57 +0800, Ling Jia wrote:
The PCI Segment Library for Phytium platform.
with multiple RCs.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 9 +-
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++
3 files changed, 1464 insertions(+), 7 deletions(-)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index 28e52e15e3..093b2cd9db 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -35,7 +35,8 @@
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf

[LibraryClasses.common.DXE_DRIVER]
-
+ # Pci dependencies
+ PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf

################################################################################
#
@@ -262,12 +263,6 @@
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

- #
- # PCI Support
- #
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
- MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
-
#
# The following 2 module perform the same work except one operate variable.
# Only one of both should be put into fdf.
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000000..67360016ef
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,28 @@
+#/** @file
+# PCI Segment Library for Phytium platform with multiple RCs.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = fa5173d2-40fe-11eb-9b2f-cb20dc669fd3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000000..273443fd5d
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1434 @@
+/** @file
+ PCI Segment Library for SoC with multiple RCs.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+#define PCI_SEG_CONFIG_BASE 0x40000000
+#define PCIE_BIF_MODE 0x29100800
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param[in] A The address to validate.
+ @param[in] M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+
+#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \
+{ \
+ (Bus) = (((Address) >> 20) & 0xff); \
+ (Device) = (((Address) >> 15) & 0x1f); \
+ (Function) = (((Address) >> 12) & 0x07); \
+}
+
+
+/**
+ This function geted the config base of PCI device.
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The value of the config base of PCI device.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINT8 RootPortCount;
+ UINT8 Peu0RootPortCount;
+ UINT8 Peu1RootPortCount;
+ UINT32 BifMode;
+ UINT32 Peu0BifMode;
+ UINT32 Peu1BifMode;
+
+ EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function);
+ BifMode = MmioRead32 (PCIE_BIF_MODE);
+ Peu0BifMode = BifMode & 0x3;
+ Peu1BifMode = (BifMode >> 2) & 0x3;
+
+ if ((Peu0BifMode == 1)) {
+ Peu0RootPortCount = 3;
+ } else {
+ Peu0RootPortCount = 2;
+ }
+
+ if ((Peu1BifMode == 1)) {
+ Peu1RootPortCount = 3;
+ } else {
+ Peu1RootPortCount = 2;
+ }
+ RootPortCount = Peu0RootPortCount + Peu1RootPortCount;
+ //ignore device > 0 or function > 0 on root port
+ if (RootPortCount == 4) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if (RootPortCount == 5) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if (RootPortCount == 6) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5) || (Bus == 6)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ }
+
+ return PCI_SEG_CONFIG_BASE;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if (Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + (UINT32)Address);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + (UINT32)Address);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + (UINT32)Address);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to write
+ @param[in] Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if (Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + (UINT32)Address, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is bit 0.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param[in] AndData The value to AND with the read value from the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned,
+ // Volatile ensure that the latest values are read every time.
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
+ }
+
+ return ReturnValue;
+}
--
2.25.1


Re: [PATCH v7 0/9] Ovmf: Disable the TPM2 platform hierarchy

Yao, Jiewen
 

Hi Stefan
CI fails on your patch - https://github.com/tianocore/edk2/pull/1965

Would you please take a look and fix that?

It is always recommended to run CI by yourself before you submit the patch.

Thank you
Yao Jiewen

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Monday, September 13, 2021 3:08 PM
To: Stefan Berger <stefanb@linux.vnet.ibm.com>; devel@edk2.groups.io
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com
Subject: Re: [edk2-devel] [PATCH v7 0/9] Ovmf: Disable the TPM2 platform
hierarchy

According to the discussion, the OvmfPkg update requires more work.
We decide to push the SecurityPkg as first wave.

SecurityPkg: Reviewed by: Jiewen Yao <Jiewen.yao@intel.com>



-----Original Message-----
From: Stefan Berger <stefanb@linux.vnet.ibm.com>
Sent: Friday, September 10, 2021 1:35 AM
To: devel@edk2.groups.io
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com; Yao, Jiewen
<jiewen.yao@intel.com>; Stefan Berger <stefanb@linux.vnet.ibm.com>
Subject: [PATCH v7 0/9] Ovmf: Disable the TPM2 platform hierarchy

This series imports code from the edk2-platforms project related to
disabling the TPM2 platform hierarchy in Ovmf. It addresses the Ovmf
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

I have patched the .dsc files and successfully test-built with most of
them. Some I could not build because they failed for other reasons
unrelated to this series.

I tested the changes with QEMU on x86 following the build of
OvmfPkgX64.dsc.

Neither one of the following commands should work anymore on first
try when run on Linux:

With IBM tss2 tools:
tsshierarchychangeauth -hi p -pwdn newpass

With Intel tss2 tools:
tpm2_changeauth -c platform newpass

Regards,
Stefan

v7:
- Ditched ARM support in this series
- Using Tcg2PlatformDxe and Tcg2PlaformPei from edk2-platforms now
and revised most of the patches

v6:
- Removed unnecessary entries in .dsc files
- Added support for S3 resume failure case
- Assigned unique FILE_GUID to NULL implementation

v5:
- Modified patch 1 copies the code from edk2-platforms
- Modified patch 2 fixes bugs in the code
- Modified patch 4 introduces required PCD

v4:
- Fixed and simplified code imported from edk2-platforms

v3:
- Referencing Null implementation on Bhyve and Xen platforms
- Add support in Arm


Stefan Berger (9):
SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
SecurityPkg/TPM: Fix bugs in imported PeiDxeTpmPlatformHierarchyLib
SecrutiyPkg/Tcg: Import Tcg2PlatformDxe from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformDxe buildable
SecurityPkg: Introduce new PCD PcdRandomizePlatformHierarchy
OvmfPkg: Reference new Tcg2PlatformDxe in the build system for
compilation
SecurityPkg/Tcg: Import Tcg2PlatformPei from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformPei buildable
OvmfPkg: Reference new Tcg2PlatformPei in the build system

OvmfPkg/AmdSev/AmdSevX64.dsc | 8 +
OvmfPkg/AmdSev/AmdSevX64.fdf | 2 +
OvmfPkg/OvmfPkgIa32.dsc | 8 +
OvmfPkg/OvmfPkgIa32.fdf | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 8 +
OvmfPkg/OvmfPkgIa32X64.fdf | 2 +
OvmfPkg/OvmfPkgX64.dsc | 8 +
OvmfPkg/OvmfPkgX64.fdf | 2 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 255 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 44 +++
SecurityPkg/SecurityPkg.dec | 6 +
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c | 85 ++++++
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 43 +++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c | 107 ++++++++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf | 51 ++++
16 files changed, 658 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.c
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf

--
2.31.1





Re: [PATCH v7 0/9] Ovmf: Disable the TPM2 platform hierarchy

Yao, Jiewen
 

According to the discussion, the OvmfPkg update requires more work.
We decide to push the SecurityPkg as first wave.

SecurityPkg: Reviewed by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: Stefan Berger <stefanb@linux.vnet.ibm.com>
Sent: Friday, September 10, 2021 1:35 AM
To: devel@edk2.groups.io
Cc: mhaeuser@posteo.de; spbrogan@outlook.com;
marcandre.lureau@redhat.com; kraxel@redhat.com; Yao, Jiewen
<jiewen.yao@intel.com>; Stefan Berger <stefanb@linux.vnet.ibm.com>
Subject: [PATCH v7 0/9] Ovmf: Disable the TPM2 platform hierarchy

This series imports code from the edk2-platforms project related to
disabling the TPM2 platform hierarchy in Ovmf. It addresses the Ovmf
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

I have patched the .dsc files and successfully test-built with most of
them. Some I could not build because they failed for other reasons
unrelated to this series.

I tested the changes with QEMU on x86 following the build of
OvmfPkgX64.dsc.

Neither one of the following commands should work anymore on first
try when run on Linux:

With IBM tss2 tools:
tsshierarchychangeauth -hi p -pwdn newpass

With Intel tss2 tools:
tpm2_changeauth -c platform newpass

Regards,
Stefan

v7:
- Ditched ARM support in this series
- Using Tcg2PlatformDxe and Tcg2PlaformPei from edk2-platforms now
and revised most of the patches

v6:
- Removed unnecessary entries in .dsc files
- Added support for S3 resume failure case
- Assigned unique FILE_GUID to NULL implementation

v5:
- Modified patch 1 copies the code from edk2-platforms
- Modified patch 2 fixes bugs in the code
- Modified patch 4 introduces required PCD

v4:
- Fixed and simplified code imported from edk2-platforms

v3:
- Referencing Null implementation on Bhyve and Xen platforms
- Add support in Arm


Stefan Berger (9):
SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
SecurityPkg/TPM: Fix bugs in imported PeiDxeTpmPlatformHierarchyLib
SecrutiyPkg/Tcg: Import Tcg2PlatformDxe from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformDxe buildable
SecurityPkg: Introduce new PCD PcdRandomizePlatformHierarchy
OvmfPkg: Reference new Tcg2PlatformDxe in the build system for
compilation
SecurityPkg/Tcg: Import Tcg2PlatformPei from edk2-platforms
SecurityPkg/Tcg: Make Tcg2PlatformPei buildable
OvmfPkg: Reference new Tcg2PlatformPei in the build system

OvmfPkg/AmdSev/AmdSevX64.dsc | 8 +
OvmfPkg/AmdSev/AmdSevX64.fdf | 2 +
OvmfPkg/OvmfPkgIa32.dsc | 8 +
OvmfPkg/OvmfPkgIa32.fdf | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 8 +
OvmfPkg/OvmfPkgIa32X64.fdf | 2 +
OvmfPkg/OvmfPkgX64.dsc | 8 +
OvmfPkg/OvmfPkgX64.fdf | 2 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 255 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 44 +++
SecurityPkg/SecurityPkg.dec | 6 +
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c | 85 ++++++
.../Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf | 43 +++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c | 107 ++++++++
.../Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf | 51 ++++
16 files changed, 658 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.c
create mode 100644
SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierar
chyLib.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
create mode 100644 SecurityPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf

--
2.31.1


Re: [PATCH 05/23] MdePkg: Add TdxProbeLib to probe Intel Tdx

Min Xu
 

On September 11, 2021 9:15 AM, Erden Aktas wrote:
On Thu, Aug 12, 2021 at 2:57 PM Min Xu <min.m.xu@intel.com> wrote:
+
+#include <Library/BaseLib.h>
+#include "InternalTdxProbe.h"
+
+/**
+ TDX only works in X64. So allways return -1 to indicate Non-Td.
s/allways/always

Also, -1 or 1? PROBE_NOT_TD_GUEST is defined as 1.
TdxProbeLib will be removed in next version.
According to the discussion a new PCD (ConfidentialComputingCategory)
will be added to record the type of VM Guest, such as Legacy guest, SEV guest,
TDX guest, etc.
Thus this PCD will be checked when the SEV or TDX to be determined.


Re: [PATCH 03/23] OvmfPkg/ResetVector: Enable Intel TDX in ResetVector of Ovmf

Min Xu
 

On September 11, 2021 9:14 AM, Erdem Aktas wrote:

On Thu, Aug 12, 2021 at 2:57 PM Min Xu <min.m.xu@intel.com> wrote:

+;
+; Check if it is Intel Tdx
+;
+; Modified: EAX, EBX, ECX, EDX
+;
+; If it is Intel Tdx, EAX is zero
+; If it is not Intel Tdx, EAX is non-zero ;
+IsTdx:
IsTdx returns 0 when TDX is enabled in CPUID but IsTdxEnabled return 1
when TDX is enabled. Is this intentional?
I will make the return result of IsTdx and IsTdxEnabled consistent.
If it is Intel TDX, EAX is 1, otherwise it is 0.

here is how IsTdxEnabled defined.
; If TDX is enabled then EAX will be 1
; If TDX is disabled then EAX will be 0.
;
IsTdxEnabled:

+TdxApWait:
+ cmp byte[TDX_WORK_AREA_PGTBL_READY], 0
+ je TdxApWait
Don't we need memory fence before je TdxApWait. I did not check
what the compiler generates for this loop.
Below is the code compiler generated for this loop. (VS2017/release)
106 <1> TdxApWait:
107 0000070B 803D04B0800000 <1> cmp byte[TDX_WORK_AREA_PGTBL_READY], 0
108 00000712 74F7 <1> je TdxApWait
109 00000714 EB17 <1> jmp ExitInitTdxWorkarea

This is the code lfence is added.
106 <1> TdxApWait:
107 0000070B 803D04B0800000 <1> cmp byte[TDX_WORK_AREA_PGTBL_READY], 0
108 00000712 0FAEE8 <1> lfence
109 00000715 74F4 <1> je TdxApWait
110 00000717 EB17 <1> jmp ExitInitTdxWorkarea

I am not sure if lfence is needed.
Thanks!
Min


Re: [PATCH] SecurityPkg: Add debug log for indicating IBB verified OBB successfully

Min Xu
 

Reviewed-by: Min Xu <min.m.xu@intel.com>

-----Original Message-----
From: Yang, Longlong <longlong.yang@intel.com>
Sent: Monday, September 13, 2021 11:17 AM
To: devel@edk2.groups.io
Cc: Yang, Longlong <longlong.yang@intel.com>; Yao, Jiewen
<jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>; Xu, Min M
<min.m.xu@intel.com>; Zhang, Qi1 <qi1.zhang@intel.com>
Subject: [PATCH] SecurityPkg: Add debug log for indicating IBB verified OBB
successfully

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3615

Debug message should be added for indicating IBB is successfully verifying the
OBB.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Min M Xu <min.m.xu@intel.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Signed-off-by: Longlong Yang <longlong.yang@intel.com>
---
SecurityPkg/FvReportPei/FvReportPei.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/SecurityPkg/FvReportPei/FvReportPei.c
b/SecurityPkg/FvReportPei/FvReportPei.c
index e82413e090..f31d5961b8 100644
--- a/SecurityPkg/FvReportPei/FvReportPei.c
+++ b/SecurityPkg/FvReportPei/FvReportPei.c
@@ -344,6 +344,8 @@ CheckStoredHashFv (
StoredHashFvPpi->FvNumber, BootMode);
if (!EFI_ERROR (Status)) {

+ DEBUG ((DEBUG_INFO, " OBB verification passed (%r)\r\n",
+ Status));
+
//
// Report the FVs to PEI core and/or DXE core.
//
--
2.31.1.windows.1


[Patch V2 2/2] UefiPayloadPkg: Remove ACPI board Hob.

thiyagukb
 

ACPI board Hob is not spec defined guid HOB, and the information it
contains can be found in ACPI table.
So remove it, and in BlSupportDxe to parse ACPI table and set PCDs.
Updated other modules to consume dynamic PCDs instead of HOBs.

Signed-off-by: Guo Dong <guo.dong@intel.com>
---
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h | 9 +++++++--
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 15 +++++++++++++--
UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h | 30 ------------------------------
UefiPayloadPkg/Include/Library/BlParseLib.h | 1 -
UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c | 45 ++++-----------------------------------------
UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf | 9 +++------
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c | 28 ++++++++++++----------------
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf | 5 ++++-
UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c | 57 ++++++---------------------------------------------------
UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf | 12 +++++++-----
UefiPayloadPkg/UefiPayloadEntry/PrintHob.c | 28 ----------------------------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 264 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 3 ---
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf | 1 -
UefiPayloadPkg/UefiPayloadPkg.dec | 26 +++++++++++++++++++++++++-
UefiPayloadPkg/UefiPayloadPkg.dsc | 7 +++++++
18 files changed, 247 insertions(+), 468 deletions(-)

diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
index 04e968a232..1d9da112c0 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
@@ -84,6 +84,152 @@ ReserveResourceInGcd (
}


+/**
+ Set the platform related PCDs using ACPI table
+
+ @param[in] AcpiTableBase ACPI table start address in memory
+
+ @retval RETURN_SUCCESS Successfully set PCDs based ACPI table.
+ @retval RETURN_NOT_FOUND Failed to find the required info
+
+**/
+RETURN_STATUS
+SetPcdsUsingAcpiTable (
+ IN UINT64 AcpiTableBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
+ EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
+ UINT32 *Entry32;
+ UINTN Entry32Num;
+ EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
+ EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
+ UINT64 *Entry64;
+ UINTN Entry64Num;
+ UINTN Idx;
+ UINT32 *Signature;
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *MmCfgHdr;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *MmCfgBase;
+ UINT64 PcieBaseAddress;
+ UINT64 PcieBaseSize;
+
+ Rsdp = (EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)(UINTN)AcpiTableBase;
+ DEBUG ((DEBUG_INFO, "Rsdp at 0x%p\n", Rsdp));
+ DEBUG ((DEBUG_INFO, "Rsdt at 0x%x, Xsdt at 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));
+
+ //
+ // Search Rsdt First
+ //
+ Fadt = NULL;
+ MmCfgHdr = NULL;
+ Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);
+ if (Rsdt != NULL) {
+ Entry32 = (UINT32 *)(Rsdt + 1);
+ Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+ for (Idx = 0; Idx < Entry32Num; Idx++) {
+ Signature = (UINT32 *)(UINTN)Entry32[Idx];
+ if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+ DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+ }
+
+ if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
+ DEBUG ((DEBUG_INFO, "Found MM config address in Rsdt\n"));
+ }
+
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
+ goto Done;
+ }
+ }
+ }
+
+ //
+ // Search Xsdt Second
+ //
+ Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);
+ if (Xsdt != NULL) {
+ Entry64 = (UINT64 *)(Xsdt + 1);
+ Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
+ for (Idx = 0; Idx < Entry64Num; Idx++) {
+ Signature = (UINT32 *)(UINTN)Entry64[Idx];
+ if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+ DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
+ }
+
+ if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
+ DEBUG ((DEBUG_INFO, "Found MM config address in Xsdt\n"));
+ }
+
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
+ goto Done;
+ }
+ }
+ }
+
+ if (Fadt == NULL) {
+ return RETURN_NOT_FOUND;
+ }
+
+Done:
+
+ if (MmCfgHdr != NULL) {
+ MmCfgBase = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)((UINT8*) MmCfgHdr + sizeof (*MmCfgHdr));
+ PcieBaseAddress = MmCfgBase->BaseAddress;
+ PcieBaseSize = (MmCfgBase->EndBusNumber + 1 - MmCfgBase->StartBusNumber) * 4096 * 32 * 8;
+ } else {
+ PcieBaseAddress = 0;
+ PcieBaseSize = 0;
+ }
+ DEBUG ((DEBUG_INFO, "PmCtrl Reg 0x%lx\n", Fadt->Pm1aCntBlk));
+ DEBUG ((DEBUG_INFO, "PmTimer Reg 0x%lx\n", Fadt->PmTmrBlk));
+ DEBUG ((DEBUG_INFO, "Reset Reg 0x%lx\n", Fadt->ResetReg.Address));
+ DEBUG ((DEBUG_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));
+ DEBUG ((DEBUG_INFO, "PmEvt Reg 0x%lx\n", Fadt->Pm1aEvtBlk));
+ DEBUG ((DEBUG_INFO, "PmGpeEn Reg 0x%lx\n", Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2));
+ DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", PcieBaseAddress));
+ DEBUG ((DEBUG_INFO, "PcieBaseSize 0x%lx\n", PcieBaseSize));
+
+ //
+ // Verify values for proper operation
+ //
+ ASSERT(Fadt->Pm1aCntBlk != 0);
+ ASSERT(Fadt->PmTmrBlk != 0);
+ ASSERT(Fadt->ResetReg.Address != 0);
+ ASSERT(Fadt->Pm1aEvtBlk != 0);
+ ASSERT(Fadt->Gpe0Blk != 0);
+
+ Status = PcdSet32S (PcdAcpiPm1aControlAddress, Fadt->Pm1aCntBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiPm1aEventAddress, Fadt->Pm1aEvtBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiGpe0EnableAddress, Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdAcpiResetRegister, Fadt->ResetReg.Address);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet8S (PcdAcpiResetValue, Fadt->ResetValue);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiPm1TimerRegister, Fadt->PmTmrBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdPciExpressBaseAddress, PcieBaseAddress);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdPciExpressBaseSize, PcieBaseSize);
+ ASSERT_EFI_ERROR (Status);
+
+ return RETURN_SUCCESS;
+}
+
+
/**
Main entry for the bootloader support DXE module.

@@ -101,12 +247,13 @@ BlDxeEntryPoint (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HOB_GUID_TYPE *GuidHob;
- EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;
- ACPI_BOARD_INFO *AcpiBoardInfo;
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;
+ UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob;

Status = EFI_SUCCESS;
+
//
// Report MMIO/IO Resources
//
@@ -131,17 +278,14 @@ BlDxeEntryPoint (
}

//
- // Set PcdPciExpressBaseAddress and PcdPciExpressBaseSize by HOB info
+ // Install Acpi Table
//
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- if (GuidHob != NULL) {
- AcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
- Status = PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo->PcieBaseAddress);
- ASSERT_EFI_ERROR (Status);
- Status = PcdSet64S (PcdPciExpressBaseSize, AcpiBoardInfo->PcieBaseSize);
- ASSERT_EFI_ERROR (Status);
- }
-
+ GuidHob = GetFirstGuidHob (&gUniversalPayloadAcpiTableGuid);
+ if (GuidHob != NULL) {
+ AcpiTableHob = (UNIVERSAL_PAYLOAD_ACPI_TABLE *)GET_GUID_HOB_DATA (GuidHob);
+ DEBUG ((DEBUG_ERROR, "Install Acpi Table at 0x%lx \n", AcpiTableHob->Rsdp));
+ Status = SetPcdsUsingAcpiTable ((UINT64)(UINTN)AcpiTableHob->Rsdp);
+ ASSERT_EFI_ERROR (Status);
+ }
return EFI_SUCCESS;
}
-
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
index 3332a30eae..0790a5572a 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
@@ -19,9 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h>
#include <Library/HobLib.h>

+#include <Guid/Acpi.h>
#include <Guid/SmBios.h>
-#include <Guid/SystemTableInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>
+#include <UniversalPayload/AcpiTable.h>
+#include <UniversalPayload/SmbiosTable.h>
#include <Guid/GraphicsInfoHob.h>

+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <UniversalPayload/AcpiTable.h>
+
#endif
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
index 1ccb250991..5d39a9b3f2 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
@@ -42,9 +42,8 @@
HobLib

[Guids]
- gUefiSystemTableInfoGuid
- gUefiAcpiBoardInfoGuid
gEfiGraphicsInfoHobGuid
+ gUniversalPayloadAcpiTableGuid

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
@@ -53,6 +52,18 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress

[Depex]
TRUE
diff --git a/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h b/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h
deleted file mode 100644
index 043b748ae4..0000000000
--- a/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/** @file
- This file defines the hob structure for board related information from acpi table
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __ACPI_BOARD_INFO_GUID_H__
-#define __ACPI_BOARD_INFO_GUID_H__
-
-///
-/// Board information GUID
-///
-extern EFI_GUID gUefiAcpiBoardInfoGuid;
-
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved0[2];
- UINT8 ResetValue;
- UINT64 PmEvtBase;
- UINT64 PmGpeEnBase;
- UINT64 PmCtrlRegBase;
- UINT64 PmTimerRegBase;
- UINT64 ResetRegAddress;
- UINT64 PcieBaseAddress;
- UINT64 PcieBaseSize;
-} ACPI_BOARD_INFO;
-
-#endif
diff --git a/UefiPayloadPkg/Include/Library/BlParseLib.h b/UefiPayloadPkg/Include/Library/BlParseLib.h
index 8058c1a17b..6310a02f95 100644
--- a/UefiPayloadPkg/Include/Library/BlParseLib.h
+++ b/UefiPayloadPkg/Include/Library/BlParseLib.h
@@ -13,7 +13,6 @@
#include <UniversalPayload/AcpiTable.h>
#include <UniversalPayload/SmbiosTable.h>
#include <Guid/SystemTableInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>

#ifndef __BOOTLOADER_PARSE_LIB__
#define __BOOTLOADER_PARSE_LIB__
diff --git a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
index b86382d709..541327709c 100644
--- a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
+++ b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
@@ -1,7 +1,7 @@
/** @file
ACPI Timer implements one instance of Timer Library.

- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -10,47 +10,11 @@
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
-#include <Library/HobLib.h>
#include <Library/DebugLib.h>
-
-#include <Guid/AcpiBoardInfoGuid.h>
#include <IndustryStandard/Acpi.h>

#define ACPI_TIMER_COUNT_SIZE BIT24

-UINTN mPmTimerReg = 0;
-
-/**
- The constructor function enables ACPI IO space.
-
- If ACPI I/O space not enabled, this function will enable it.
- It will always return RETURN_SUCCESS.
-
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-AcpiTimerLibConstructor (
- VOID
- )
-{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *pAcpiBoardInfo;
-
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
-
- mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;
-
- return EFI_SUCCESS;
-}
-
/**
Internal function to read the current tick counter of ACPI.

@@ -64,10 +28,9 @@ InternalAcpiGetTimerTick (
VOID
)
{
- if (mPmTimerReg == 0) {
- AcpiTimerLibConstructor ();
- }
- return IoRead32 (mPmTimerReg);
+
+ ASSERT (PcdGet32 (PcdAcpiPm1TimerRegister) != 0);
+ return IoRead32 (PcdGet32 (PcdAcpiPm1TimerRegister));
}

/**
diff --git a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
index 3e177cadc0..0fea86c83a 100644
--- a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
+++ b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
@@ -1,7 +1,7 @@
## @file
# ACPI Timer Library Instance.
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,8 +14,6 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib

- CONSTRUCTOR = AcpiTimerLibConstructor
-
#
# The following information is for reference only and not required by the build tools.
#
@@ -33,8 +31,7 @@
[LibraryClasses]
BaseLib
IoLib
- HobLib
DebugLib

-[Guids]
- gUefiAcpiBoardInfoGuid
+[Pcd]
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
index d37c91cc9f..3c79649b56 100644
--- a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
@@ -8,9 +8,7 @@
**/

#include <PiDxe.h>
-#include <Guid/AcpiBoardInfoGuid.h>
-
-#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
#include <Library/PciSegmentInfoLib.h>
#include <Library/DebugLib.h>

@@ -21,6 +19,17 @@ STATIC PCI_SEGMENT_INFO mPciSegment0 = {
255 // End bus number
};

+
+RETURN_STATUS
+EFIAPI
+PciSegmentInfoInitialize (
+ VOID
+ )
+{
+ mPciSegment0.BaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
+ return RETURN_SUCCESS;
+}
+
/**
Return an array of PCI_SEGMENT_INFO holding the segment information.

@@ -36,24 +45,11 @@ GetPciSegmentInfo (
UINTN *Count
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *AcpiBoardInfo;
-
ASSERT (Count != NULL);
if (Count == NULL) {
return NULL;
}

- if (mPciSegment0.BaseAddress == 0) {
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- AcpiBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);
- mPciSegment0.BaseAddress = AcpiBoardInfo->PcieBaseAddress;
- }
*Count = 1;
return &mPciSegment0;
}
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
index ec4dbaaa55..cc6ca83706 100644
--- a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
@@ -16,6 +16,7 @@
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PciSegmentInfoLib | DXE_DRIVER
+ CONSTRUCTOR = PciSegmentInfoInitialize

#
# The following information is for reference only and not required by the build tools.
@@ -32,5 +33,7 @@

[LibraryClasses]
PcdLib
- HobLib
DebugLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
\ No newline at end of file
diff --git a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
index 2e4b7fe592..9e2e58f977 100644
--- a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -10,54 +10,8 @@
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
-#include <Library/HobLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Guid/AcpiBoardInfoGuid.h>

-ACPI_BOARD_INFO mAcpiBoardInfo;
-
-/**
- The constructor function to initialize mAcpiBoardInfo.
-
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-ResetSystemLibConstructor (
- VOID
- )
-{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *AcpiBoardInfoPtr;
-
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- AcpiBoardInfoPtr = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
- CopyMem (&mAcpiBoardInfo, AcpiBoardInfoPtr, sizeof (ACPI_BOARD_INFO));
-
- return EFI_SUCCESS;
-}
-
-
-VOID
-AcpiPmControl (
- UINTN SuspendType
- )
-{
- UINTN PmCtrlReg;
-
- ASSERT (SuspendType <= 7);
-
- PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
- IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (SuspendType << 10));
- IoOr16 (PmCtrlReg, BIT13);
- CpuDeadLoop ();
-}

/**
Calling this function causes a system-wide reset. This sets
@@ -74,7 +28,7 @@ ResetCold (
VOID
)
{
- IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
+ IoWrite8 ((UINTN)PcdGet64 (PcdAcpiResetRegister), PcdGet8 (PcdAcpiResetValue));
CpuDeadLoop ();
}

@@ -91,7 +45,8 @@ ResetWarm (
VOID
)
{
- IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
+ IoWrite8 ((UINTN)PcdGet64 (PcdAcpiResetRegister), PcdGet8 (PcdAcpiResetValue));
+
CpuDeadLoop ();
}

@@ -113,17 +68,17 @@ ResetShutdown (
//
// GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
- IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);
+ IoWrite16 (PcdGet32 (PcdAcpiGpe0EnableAddress), 0);

//
// Clear Power Button Status
//
- IoWrite16((UINTN) mAcpiBoardInfo.PmEvtBase, BIT8);
+ IoWrite16(PcdGet32 (PcdAcpiPm1aEventAddress), BIT8);

//
// Transform system into S5 sleep state
//
- PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
+ PmCtrlReg = PcdGet32 (PcdAcpiPm1aControlAddress);
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
diff --git a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
index e7341c341a..77d73e7404 100644
--- a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
+++ b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -1,7 +1,7 @@
## @file
# Library instance for ResetSystem library class for bootloader
#
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,7 +14,6 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib

- CONSTRUCTOR = ResetSystemLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
@@ -32,9 +31,12 @@
[LibraryClasses]
DebugLib
IoLib
- HobLib
BaseMemoryLib

-[Guids]
- gUefiAcpiBoardInfoGuid
+[Pcd]
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress

diff --git a/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c b/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
index 5fb638d4a4..6a92bffed1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
@@ -9,7 +9,6 @@
#include <UniversalPayload/PciRootBridges.h>
#include <UniversalPayload/ExtraData.h>
#include <Guid/MemoryTypeInformation.h>
-#include <Guid/AcpiBoardInfoGuid.h>

#define ROW_LIMITER 16

@@ -276,32 +275,6 @@ PrintSmbiosTablGuidHob (
return EFI_SUCCESS;
}

-/**
- Print the information in Acpi BoardInfo Guid Hob.
- @param[in] HobRaw A pointer to the start of gUefiAcpiBoardInfoGuid HOB.
- @retval EFI_SUCCESS If it completed successfully.
-**/
-EFI_STATUS
-PrintAcpiBoardInfoGuidHob (
- IN UINT8 *HobRaw,
- IN UINT16 HobLength
- )
-{
- ACPI_BOARD_INFO *AcpBoardInfo;
- AcpBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (HobRaw);
- ASSERT (HobLength >= sizeof (*AcpBoardInfo));
- DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", AcpBoardInfo->Revision));
- DEBUG ((DEBUG_INFO, " Reserved0 = 0x%x\n", AcpBoardInfo->Reserved0));
- DEBUG ((DEBUG_INFO, " ResetValue = 0x%x\n", AcpBoardInfo->ResetValue));
- DEBUG ((DEBUG_INFO, " PmEvtBase = 0x%lx\n", AcpBoardInfo->PmEvtBase));
- DEBUG ((DEBUG_INFO, " PmGpeEnBase = 0x%lx\n", AcpBoardInfo->PmGpeEnBase));
- DEBUG ((DEBUG_INFO, " PmCtrlRegBase = 0x%lx\n", AcpBoardInfo->PmCtrlRegBase));
- DEBUG ((DEBUG_INFO, " PmTimerRegBase = 0x%lx\n", AcpBoardInfo->PmTimerRegBase));
- DEBUG ((DEBUG_INFO, " ResetRegAddress = 0x%lx\n", AcpBoardInfo->ResetRegAddress));
- DEBUG ((DEBUG_INFO, " PcieBaseAddress = 0x%lx\n", AcpBoardInfo->PcieBaseAddress));
- DEBUG ((DEBUG_INFO, " PcieBaseSize = 0x%lx\n", AcpBoardInfo->PcieBaseSize));
- return EFI_SUCCESS;
-}

/**
Print the information in Pci RootBridge Info Guid Hob.
@@ -415,7 +388,6 @@ GUID_HOB_PRINT_HANDLE GuidHobPrintHandleTable[] = {
{&gUniversalPayloadSerialPortInfoGuid, PrintSerialGuidHob, "gUniversalPayloadSerialPortInfoGuid(Serial Port Info)"},
{&gUniversalPayloadSmbios3TableGuid, PrintSmbios3GuidHob, "gUniversalPayloadSmbios3TableGuid(SmBios Guid)"},
{&gUniversalPayloadSmbiosTableGuid, PrintSmbiosTablGuidHob, "gUniversalPayloadSmbiosTableGuid(SmBios Guid)"},
- {&gUefiAcpiBoardInfoGuid, PrintAcpiBoardInfoGuidHob, "gUefiAcpiBoardInfoGuid(Acpi Guid)"},
{&gUniversalPayloadPciRootBridgeInfoGuid, PrintPciRootBridgeInfoGuidHob, "gUniversalPayloadPciRootBridgeInfoGuid(Pci Guid)"},
{&gEfiMemoryTypeInformationGuid, PrintMemoryTypeInfoGuidHob, "gEfiMemoryTypeInformationGuid(Memory Type Information Guid)"},
{&gUniversalPayloadExtraDataGuid, PrintExtraDataGuidHob, "gUniversalPayloadExtraDataGuid(PayLoad Extra Data Guid)"}
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
index 64a76e84b1..8ccf0f3ac8 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -9,85 +9,6 @@

STATIC UINT32 mTopOfLowerUsableDram = 0;

-/**
- Callback function to build resource descriptor HOB
-
- This function build a HOB based on the memory map entry info.
- It creates only EFI_RESOURCE_MEMORY_MAPPED_IO and EFI_RESOURCE_MEMORY_RESERVED
- resources.
-
- @param MemoryMapEntry Memory map entry info got from bootloader.
- @param Params A pointer to ACPI_BOARD_INFO.
-
- @retval EFI_SUCCESS Successfully build a HOB.
- @retval EFI_INVALID_PARAMETER Invalid parameter provided.
-**/
-EFI_STATUS
-MemInfoCallbackMmio (
- IN MEMROY_MAP_ENTRY *MemoryMapEntry,
- IN VOID *Params
- )
-{
- EFI_PHYSICAL_ADDRESS Base;
- EFI_RESOURCE_TYPE Type;
- UINT64 Size;
- EFI_RESOURCE_ATTRIBUTE_TYPE Attribue;
- ACPI_BOARD_INFO *AcpiBoardInfo;
-
- AcpiBoardInfo = (ACPI_BOARD_INFO *)Params;
- if (AcpiBoardInfo == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Skip types already handled in MemInfoCallback
- //
- if (MemoryMapEntry->Type == E820_RAM || MemoryMapEntry->Type == E820_ACPI) {
- return EFI_SUCCESS;
- }
-
- if (MemoryMapEntry->Base == AcpiBoardInfo->PcieBaseAddress) {
- //
- // MMCONF is always MMIO
- //
- Type = EFI_RESOURCE_MEMORY_MAPPED_IO;
- } else if (MemoryMapEntry->Base < mTopOfLowerUsableDram) {
- //
- // It's in DRAM and thus must be reserved
- //
- Type = EFI_RESOURCE_MEMORY_RESERVED;
- } else if ((MemoryMapEntry->Base < 0x100000000ULL) && (MemoryMapEntry->Base >= mTopOfLowerUsableDram)) {
- //
- // It's not in DRAM, must be MMIO
- //
- Type = EFI_RESOURCE_MEMORY_MAPPED_IO;
- } else {
- Type = EFI_RESOURCE_MEMORY_RESERVED;
- }
-
- Base = MemoryMapEntry->Base;
- Size = MemoryMapEntry->Size;
-
- Attribue = EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_TESTED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
-
- BuildResourceDescriptorHob (Type, Attribue, (EFI_PHYSICAL_ADDRESS)Base, Size);
- DEBUG ((DEBUG_INFO , "buildhob: base = 0x%lx, size = 0x%lx, type = 0x%x\n", Base, Size, Type));
-
- if (MemoryMapEntry->Type == E820_UNUSABLE ||
- MemoryMapEntry->Type == E820_DISABLED) {
- BuildMemoryAllocationHob (Base, Size, EfiUnusableMemory);
- } else if (MemoryMapEntry->Type == E820_PMEM) {
- BuildMemoryAllocationHob (Base, Size, EfiPersistentMemory);
- }
-
- return EFI_SUCCESS;
-}


/**
@@ -211,168 +132,6 @@ MemInfoCallback (
}


-
-/**
- Find the board related info from ACPI table
-
- @param AcpiTableBase ACPI table start address in memory
- @param AcpiBoardInfo Pointer to the acpi board info strucutre
-
- @retval RETURN_SUCCESS Successfully find out all the required information.
- @retval RETURN_NOT_FOUND Failed to find the required info.
-
-**/
-RETURN_STATUS
-ParseAcpiInfo (
- IN UINT64 AcpiTableBase,
- OUT ACPI_BOARD_INFO *AcpiBoardInfo
- )
-{
- EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
- EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
- UINT32 *Entry32;
- UINTN Entry32Num;
- EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
- EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
- UINT64 *Entry64;
- UINTN Entry64Num;
- UINTN Idx;
- UINT32 *Signature;
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *MmCfgHdr;
- EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *MmCfgBase;
-
- Rsdp = (EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)(UINTN)AcpiTableBase;
- DEBUG ((DEBUG_INFO, "Rsdp at 0x%p\n", Rsdp));
- DEBUG ((DEBUG_INFO, "Rsdt at 0x%x, Xsdt at 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));
-
- //
- // Search Rsdt First
- //
- Fadt = NULL;
- MmCfgHdr = NULL;
- Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);
- if (Rsdt != NULL) {
- Entry32 = (UINT32 *)(Rsdt + 1);
- Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
- for (Idx = 0; Idx < Entry32Num; Idx++) {
- Signature = (UINT32 *)(UINTN)Entry32[Idx];
- if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
- Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
- DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
- }
-
- if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
- MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
- DEBUG ((DEBUG_INFO, "Found MM config address in Rsdt\n"));
- }
-
- if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
- goto Done;
- }
- }
- }
-
- //
- // Search Xsdt Second
- //
- Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);
- if (Xsdt != NULL) {
- Entry64 = (UINT64 *)(Xsdt + 1);
- Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
- for (Idx = 0; Idx < Entry64Num; Idx++) {
- Signature = (UINT32 *)(UINTN)Entry64[Idx];
- if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
- Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
- DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
- }
-
- if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
- MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
- DEBUG ((DEBUG_INFO, "Found MM config address in Xsdt\n"));
- }
-
- if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
- goto Done;
- }
- }
- }
-
- if (Fadt == NULL) {
- return RETURN_NOT_FOUND;
- }
-
-Done:
-
- AcpiBoardInfo->PmCtrlRegBase = Fadt->Pm1aCntBlk;
- AcpiBoardInfo->PmTimerRegBase = Fadt->PmTmrBlk;
- AcpiBoardInfo->ResetRegAddress = Fadt->ResetReg.Address;
- AcpiBoardInfo->ResetValue = Fadt->ResetValue;
- AcpiBoardInfo->PmEvtBase = Fadt->Pm1aEvtBlk;
- AcpiBoardInfo->PmGpeEnBase = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;
-
- if (MmCfgHdr != NULL) {
- MmCfgBase = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)((UINT8*) MmCfgHdr + sizeof (*MmCfgHdr));
- AcpiBoardInfo->PcieBaseAddress = MmCfgBase->BaseAddress;
- AcpiBoardInfo->PcieBaseSize = (MmCfgBase->EndBusNumber + 1 - MmCfgBase->StartBusNumber) * 4096 * 32 * 8;
- } else {
- AcpiBoardInfo->PcieBaseAddress = 0;
- AcpiBoardInfo->PcieBaseSize = 0;
- }
- DEBUG ((DEBUG_INFO, "PmCtrl Reg 0x%lx\n", AcpiBoardInfo->PmCtrlRegBase));
- DEBUG ((DEBUG_INFO, "PmTimer Reg 0x%lx\n", AcpiBoardInfo->PmTimerRegBase));
- DEBUG ((DEBUG_INFO, "Reset Reg 0x%lx\n", AcpiBoardInfo->ResetRegAddress));
- DEBUG ((DEBUG_INFO, "Reset Value 0x%x\n", AcpiBoardInfo->ResetValue));
- DEBUG ((DEBUG_INFO, "PmEvt Reg 0x%lx\n", AcpiBoardInfo->PmEvtBase));
- DEBUG ((DEBUG_INFO, "PmGpeEn Reg 0x%lx\n", AcpiBoardInfo->PmGpeEnBase));
- DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", AcpiBoardInfo->PcieBaseAddress));
- DEBUG ((DEBUG_INFO, "PcieBaseSize 0x%lx\n", AcpiBoardInfo->PcieBaseSize));
-
- //
- // Verify values for proper operation
- //
- ASSERT(Fadt->Pm1aCntBlk != 0);
- ASSERT(Fadt->PmTmrBlk != 0);
- ASSERT(Fadt->ResetReg.Address != 0);
- ASSERT(Fadt->Pm1aEvtBlk != 0);
- ASSERT(Fadt->Gpe0Blk != 0);
-
- DEBUG_CODE_BEGIN ();
- BOOLEAN SciEnabled;
-
- //
- // Check the consistency of SCI enabling
- //
-
- //
- // Get SCI_EN value
- //
- if (Fadt->Pm1CntLen == 4) {
- SciEnabled = (IoRead32 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
- } else {
- //
- // if (Pm1CntLen == 2), use 16 bit IO read;
- // if (Pm1CntLen != 2 && Pm1CntLen != 4), use 16 bit IO read as a fallback
- //
- SciEnabled = (IoRead16 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
- }
-
- if (!(Fadt->Flags & EFI_ACPI_5_0_HW_REDUCED_ACPI) &&
- (Fadt->SmiCmd == 0) &&
- !SciEnabled) {
- //
- // The ACPI enabling status is inconsistent: SCI is not enabled but ACPI
- // table does not provide a means to enable it through FADT->SmiCmd
- //
- DEBUG ((DEBUG_ERROR, "ERROR: The ACPI enabling status is inconsistent: SCI is not"
- " enabled but the ACPI table does not provide a means to enable it through FADT->SmiCmd."
- " This may cause issues in OS.\n"));
- }
- DEBUG_CODE_END ();
-
- return RETURN_SUCCESS;
-}
-
-
/**
It will build HOBs based on information from bootloaders.

@@ -385,8 +144,6 @@ BuildHobFromBl (
)
{
EFI_STATUS Status;
- ACPI_BOARD_INFO AcpiBoardInfo;
- ACPI_BOARD_INFO *NewAcpiBoardInfo;
EFI_PEI_GRAPHICS_INFO_HOB GfxInfo;
EFI_PEI_GRAPHICS_INFO_HOB *NewGfxInfo;
EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GfxDeviceInfo;
@@ -460,27 +217,6 @@ BuildHobFromBl (
DEBUG ((DEBUG_INFO, "Detected ACPI Table at 0x%lx\n", AcpiTableHob->Rsdp));
}

- //
- // Create guid hob for acpi board information
- //
- Status = ParseAcpiInfo (AcpiTableHob->Rsdp, &AcpiBoardInfo);
- ASSERT_EFI_ERROR (Status);
- if (!EFI_ERROR (Status)) {
- NewAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));
- ASSERT (NewAcpiBoardInfo != NULL);
- CopyMem (NewAcpiBoardInfo, &AcpiBoardInfo, sizeof (ACPI_BOARD_INFO));
- DEBUG ((DEBUG_INFO, "Create acpi board info guid hob\n"));
- }
-
- //
- // Parse memory info and build memory HOBs for reserved DRAM and MMIO
- //
- DEBUG ((DEBUG_INFO , "Building ResourceDescriptorHobs for reserved memory:\n"));
- Status = ParseMemoryInfo (MemInfoCallbackMmio, &AcpiBoardInfo);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
//
// Parse platform specific information.
//
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
index 82590bf7c6..460253e4b6 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
@@ -24,11 +24,8 @@
#include <Library/BlParseLib.h>
#include <Library/PlatformSupportLib.h>
#include <Library/UefiCpuLib.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <Guid/SerialPortInfoGuid.h>
#include <Guid/MemoryMapInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>
#include <Guid/GraphicsInfoHob.h>
#include <UniversalPayload/SmbiosTable.h>
#include <UniversalPayload/AcpiTable.h>
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..7b5ff184e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -63,7 +63,6 @@
gUefiSystemTableInfoGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
- gUefiAcpiBoardInfoGuid
gUniversalPayloadSmbiosTableGuid
gUniversalPayloadAcpiTableGuid

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..6394af5048 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -59,7 +59,6 @@
gUefiSystemTableInfoGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
- gUefiAcpiBoardInfoGuid
gEfiSmbiosTableGuid
gEfiAcpiTableGuid
gUefiSerialPortInfoGuid
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayloadPkg.dec
index 8f0a7e3f95..94b0e057ce 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -33,7 +33,6 @@
gEdkiiBootManagerMenuFileGuid = { 0xdf939333, 0x42fc, 0x4b2a, { 0xa5, 0x9e, 0xbb, 0xae, 0x82, 0x81, 0xfe, 0xef }}

gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}}
- gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}
gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }

@@ -77,3 +76,28 @@ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x80|UINT32|0x
gUefiPayloadPkgTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000|UINT32|0x00000017

gUefiPayloadPkgTokenSpaceGuid.PcdPcdDriverFile|{ 0x57, 0x72, 0xcf, 0x80, 0xab, 0x87, 0xf9, 0x47, 0xa3, 0xfe, 0xD5, 0x0B, 0x76, 0xd8, 0x95, 0x41 }|VOID*|0x00000018
+
+[PcdsDynamic, PcdsDynamicEx]
+## Defines the 32-bit Timer register access address that resides within the ACPI BAR.
+# @Prompt ACPI PM1 timer register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister |0|UINT32|0x00000019
+
+## Defines the Reset register access address that resides within the ACPI BAR.
+# @Prompt ACPI reset register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister |0|UINT64|0x00000020
+
+## Defines the reset value writing to ACPI reset register.
+# @Prompt Reset value to ACPI reset register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue |0|UINT8|0x00000021
+
+## Defines the system port address of the PM1a Control Register Block.
+# @Prompt PM1a control register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress |0|UINT32|0x00000022
+
+## Defines the system port address of the PM1a Event Register Block.
+# @Prompt PM1a event register register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress |0|UINT32|0x00000023
+
+## Defines the General-Purpose Event 0 Enable Register
+# @Prompt ACPI GPE0 enable register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress |0|UINT32|0x00000024
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 856d5ea786..a0b0cfe454 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -409,6 +409,13 @@
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE

+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress|0
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.
--
2.33.0.windows.2


[Patch V2 1/2] UefiPayloadPkg:Use universal spec defined GUID SystemTableInfo is SBL and CBL specific. so move it to SBL and CBL parse lib.

thiyagukb
 

Signed-off-by: Guo Dong <guo.dong@intel.com>
---
UefiPayloadPkg/Include/Library/BlParseLib.h | 25 +++++++++++++++++++++----
UefiPayloadPkg/Library/CbParseLib/CbParseLib.c | 35 ++++++++++++++++++++++++++++-------
UefiPayloadPkg/Library/SblParseLib/SblParseLib.c | 39 ++++++++++++++++++++++++++++++++++-----
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 32 ++++++++++++--------------------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 1 -
5 files changed, 95 insertions(+), 37 deletions(-)

diff --git a/UefiPayloadPkg/Include/Library/BlParseLib.h b/UefiPayloadPkg/Include/Library/BlParseLib.h
index 20a526d15c..8058c1a17b 100644
--- a/UefiPayloadPkg/Include/Library/BlParseLib.h
+++ b/UefiPayloadPkg/Include/Library/BlParseLib.h
@@ -10,6 +10,8 @@
#include <Guid/GraphicsInfoHob.h>
#include <Guid/MemoryMapInfoGuid.h>
#include <Guid/SerialPortInfoGuid.h>
+#include <UniversalPayload/AcpiTable.h>
+#include <UniversalPayload/SmbiosTable.h>
#include <Guid/SystemTableInfoGuid.h>
#include <Guid/AcpiBoardInfoGuid.h>

@@ -56,9 +58,9 @@ ParseMemoryInfo (
);

/**
- Acquire acpi table and smbios table from slim bootloader
+ Acquire smbios table from slim bootloader

- @param SystemTableInfo Pointer to the system table info
+ @param SystemTableInfo Pointer to the SMBIOS table info

@retval RETURN_SUCCESS Successfully find out the tables.
@retval RETURN_NOT_FOUND Failed to find the tables.
@@ -66,8 +68,23 @@ ParseMemoryInfo (
**/
RETURN_STATUS
EFIAPI
-ParseSystemTable (
- OUT SYSTEM_TABLE_INFO *SystemTableInfo
+ParseSmbiosTable (
+ OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
+ );
+
+/**
+ Acquire acpi table from slim bootloader
+
+ @param AcpiTableHob Pointer to the ACPI table info
+
+ @retval RETURN_SUCCESS Successfully find out the tables.
+ @retval RETURN_NOT_FOUND Failed to find the tables.
+
+**/
+RETURN_STATUS
+EFIAPI
+ParseAcpiTableInfo (
+ OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
);


diff --git a/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c b/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c
index 4e23cff50e..2ed771507e 100644
--- a/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c
+++ b/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c
@@ -408,7 +408,7 @@ ParseMemoryInfo (


/**
- Acquire acpi table and smbios table from coreboot
+ Acquire smbios table from coreboot

@param SystemTableInfo Pointer to the system table info

@@ -418,8 +418,8 @@ ParseMemoryInfo (
**/
RETURN_STATUS
EFIAPI
-ParseSystemTable (
- OUT SYSTEM_TABLE_INFO *SystemTableInfo
+ParseSmbiosTable (
+ OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
)
{
EFI_STATUS Status;
@@ -430,15 +430,36 @@ ParseSystemTable (
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
- SystemTableInfo->SmbiosTableBase = (UINT64) (UINTN)MemTable;
- SystemTableInfo->SmbiosTableSize = MemTableSize;
+ SmbiosTable->SmBiosEntryPoint = (UINT64) (UINTN)MemTable;
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Acquire acpi table from slim coreboot
+
+ @param AcpiTableHob Pointer to the ACPI table info

+ @retval RETURN_SUCCESS Successfully find out the tables.
+ @retval RETURN_NOT_FOUND Failed to find the tables.
+
+**/
+
+RETURN_STATUS
+EFIAPI
+ParseAcpiTableInfo (
+ OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
+ )
+{
+ EFI_STATUS Status;
+ VOID *MemTable;
+ UINT32 MemTableSize;
+
Status = ParseCbMemTable (SIGNATURE_32 ('I', 'P', 'C', 'A'), &MemTable, &MemTableSize);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
- SystemTableInfo->AcpiTableBase = (UINT64) (UINTN)MemTable;
- SystemTableInfo->AcpiTableSize = MemTableSize;
+ AcpiTableHob->Rsdp = (UINT64) (UINTN)MemTable;

return Status;
}
diff --git a/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c b/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c
index 7214fd87d2..4e597dc6ea 100644
--- a/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c
+++ b/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c
@@ -110,9 +110,9 @@ ParseMemoryInfo (
}

/**
- Acquire acpi table and smbios table from slim bootloader
+ Acquire smbios table from slim bootloader

- @param SystemTableInfo Pointer to the system table info
+ @param SystemTableInfo Pointer to the SMBIOS table info

@retval RETURN_SUCCESS Successfully find out the tables.
@retval RETURN_NOT_FOUND Failed to find the tables.
@@ -120,8 +120,8 @@ ParseMemoryInfo (
**/
RETURN_STATUS
EFIAPI
-ParseSystemTable (
- OUT SYSTEM_TABLE_INFO *SystemTableInfo
+ParseSmbiosTable (
+ OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
)
{
SYSTEM_TABLE_INFO *TableInfo;
@@ -132,7 +132,36 @@ ParseSystemTable (
return RETURN_NOT_FOUND;
}

- CopyMem (SystemTableInfo, TableInfo, sizeof (SYSTEM_TABLE_INFO));
+ SmbiosTable->SmBiosEntryPoint = TableInfo->SmbiosTableBase;
+
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ Acquire acpi table from slim bootloader
+
+ @param AcpiTableHob Pointer to the ACPI table info
+
+ @retval RETURN_SUCCESS Successfully find out the tables.
+ @retval RETURN_NOT_FOUND Failed to find the tables.
+
+**/
+RETURN_STATUS
+EFIAPI
+ParseAcpiTableInfo (
+ OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
+ )
+{
+ SYSTEM_TABLE_INFO *TableInfo;
+
+ TableInfo = (SYSTEM_TABLE_INFO *)GetGuidHobDataFromSbl (&gUefiSystemTableInfoGuid);
+ if (TableInfo == NULL) {
+ ASSERT (FALSE);
+ return RETURN_NOT_FOUND;
+ }
+
+ AcpiTableHob->Rsdp = TableInfo->AcpiTableBase;

return RETURN_SUCCESS;
}
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
index ae16f25c7c..64a76e84b1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -385,8 +385,6 @@ BuildHobFromBl (
)
{
EFI_STATUS Status;
- SYSTEM_TABLE_INFO SysTableInfo;
- SYSTEM_TABLE_INFO *NewSysTableInfo;
ACPI_BOARD_INFO AcpiBoardInfo;
ACPI_BOARD_INFO *NewAcpiBoardInfo;
EFI_PEI_GRAPHICS_INFO_HOB GfxInfo;
@@ -437,41 +435,35 @@ BuildHobFromBl (


//
- // Create guid hob for system tables like acpi table and smbios table
- //
- Status = ParseSystemTable(&SysTableInfo);
- ASSERT_EFI_ERROR (Status);
- if (!EFI_ERROR (Status)) {
- NewSysTableInfo = BuildGuidHob (&gUefiSystemTableInfoGuid, sizeof (SYSTEM_TABLE_INFO));
- ASSERT (NewSysTableInfo != NULL);
- CopyMem (NewSysTableInfo, &SysTableInfo, sizeof (SYSTEM_TABLE_INFO));
- DEBUG ((DEBUG_INFO, "Detected Acpi Table at 0x%lx, length 0x%x\n", SysTableInfo.AcpiTableBase, SysTableInfo.AcpiTableSize));
- DEBUG ((DEBUG_INFO, "Detected Smbios Table at 0x%lx, length 0x%x\n", SysTableInfo.SmbiosTableBase, SysTableInfo.SmbiosTableSize));
- }
- //
- // Creat SmBios table Hob
+ // Create smbios table guid hob
//
SmBiosTableHob = BuildGuidHob (&gUniversalPayloadSmbiosTableGuid, sizeof (UNIVERSAL_PAYLOAD_SMBIOS_TABLE));
ASSERT (SmBiosTableHob != NULL);
SmBiosTableHob->Header.Revision = UNIVERSAL_PAYLOAD_SMBIOS_TABLE_REVISION;
SmBiosTableHob->Header.Length = sizeof (UNIVERSAL_PAYLOAD_SMBIOS_TABLE);
- SmBiosTableHob->SmBiosEntryPoint = SysTableInfo.SmbiosTableBase;
DEBUG ((DEBUG_INFO, "Create smbios table gUniversalPayloadSmbiosTableGuid guid hob\n"));
+ Status = ParseSmbiosTable(SmBiosTableHob);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Detected Smbios Table at 0x%lx\n", SmBiosTableHob->SmBiosEntryPoint));
+ }

//
- // Creat ACPI table Hob
+ // Create acpi table guid hob
//
AcpiTableHob = BuildGuidHob (&gUniversalPayloadAcpiTableGuid, sizeof (UNIVERSAL_PAYLOAD_ACPI_TABLE));
ASSERT (AcpiTableHob != NULL);
AcpiTableHob->Header.Revision = UNIVERSAL_PAYLOAD_ACPI_TABLE_REVISION;
AcpiTableHob->Header.Length = sizeof (UNIVERSAL_PAYLOAD_ACPI_TABLE);
- AcpiTableHob->Rsdp = SysTableInfo.AcpiTableBase;
- DEBUG ((DEBUG_INFO, "Create smbios table gUniversalPayloadAcpiTableGuid guid hob\n"));
+ DEBUG ((DEBUG_INFO, "Create ACPI table gUniversalPayloadAcpiTableGuid guid hob\n"));
+ Status = ParseAcpiTableInfo(AcpiTableHob);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Detected ACPI Table at 0x%lx\n", AcpiTableHob->Rsdp));
+ }

//
// Create guid hob for acpi board information
//
- Status = ParseAcpiInfo (SysTableInfo.AcpiTableBase, &AcpiBoardInfo);
+ Status = ParseAcpiInfo (AcpiTableHob->Rsdp, &AcpiBoardInfo);
ASSERT_EFI_ERROR (Status);
if (!EFI_ERROR (Status)) {
NewAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
index 331724c687..82590bf7c6 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
@@ -27,7 +27,6 @@
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <Guid/SerialPortInfoGuid.h>
-#include <Guid/SystemTableInfoGuid.h>
#include <Guid/MemoryMapInfoGuid.h>
#include <Guid/AcpiBoardInfoGuid.h>
#include <Guid/GraphicsInfoHob.h>
--
2.33.0.windows.2


[PATCH 2/2] OvmfPkg: Transfer PlatformBootManager library to driver

thiyagukb
 

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c | 21 +++++----------------
OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h | 1 +
OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/BdsPlatform.c | 40 ++++++++++++++++++++++++++++++++++++++++
OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/PlatformBootManagerDriver.inf | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 136 insertions(+), 16 deletions(-)

diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
index 71f63b2448..2eb8682dce 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -12,6 +12,7 @@
#include <Library/PlatformBmPrintScLib.h>
#include <Library/Tcg2PhysicalPresenceLib.h>
#include <Library/XenPlatformLib.h>
+#include <Library/DxeServicesLib.h>


//
@@ -94,24 +95,12 @@ PlatformRegisterFvBootOption (
EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- Status = gBS->HandleProtocol (
- gImageHandle,
- &gEfiLoadedImageProtocolGuid,
- (VOID **) &LoadedImage
- );
- ASSERT_EFI_ERROR (Status);
-
- EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
- DevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle);
- ASSERT (DevicePath != NULL);
- DevicePath = AppendDevicePathNode (
- DevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
- );
+ Status = GetFileDevicePathFromAnyFv(FileGuid, EFI_SECTION_PE32, 0, &DevicePath);
+ if (EFI_ERROR (Status)){
+ Status = GetFileDevicePathFromAnyFv(FileGuid, EFI_SECTION_USER_INTERFACE, 0, &DevicePath);
+ }
ASSERT (DevicePath != NULL);

Status = EfiBootManagerInitializeLoadOption (
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h
index 153e215101..d6ffadfdaf 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h
@@ -63,6 +63,7 @@ Abstract:
#include <Guid/DebugAgentGuid.h>

#include <OvmfPlatforms.h>
+#include <Library/PlatformBootManagerLib.h>

extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[];
extern ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode;
diff --git a/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/BdsPlatform.c b/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/BdsPlatform.c
new file mode 100644
index 0000000000..7dc9a47eff
--- /dev/null
+++ b/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/BdsPlatform.c
@@ -0,0 +1,40 @@
+/** @file
+ Platform BDS customizations.
+
+ Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PlatformBootManagerLib.h>
+#include <Protocol/PlatformBootManagerOverride.h>
+
+
+STATIC UNIVERSAL_PAYLOAD_PLATFORM_BOOT_MANAGER_OVERRIDE_PROTOCOL mUniversalPayloadPlatformBootManager = {
+ PlatformBootManagerBeforeConsole,
+ PlatformBootManagerAfterConsole,
+ PlatformBootManagerWaitCallback,
+ PlatformBootManagerUnableToBoot,
+};
+
+// Entry point of this driver
+//
+EFI_STATUS
+EFIAPI
+InitPlatformBootManagerLib (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gUniversalPayloadPlatformBootManagerOverrideProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mUniversalPayloadPlatformBootManager
+ );
+ return Status;
+}
\ No newline at end of file
diff --git a/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/PlatformBootManagerDriver.inf b/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/PlatformBootManagerDriver.inf
new file mode 100644
index 0000000000..6ffb76096a
--- /dev/null
+++ b/OvmfPkg/QemuUniversalPayload/PlatformBootManagerDriver/PlatformBootManagerDriver.inf
@@ -0,0 +1,90 @@
+## @file
+# Platform BDS customizations library.
+#
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformBootManager
+ FILE_GUID = FB65006C-AC9F-4992-AD80-184B2BDBBD13
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitPlatformBootManagerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[Sources]
+ BdsPlatform.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SourceLevelDebugPkg/SourceLevelDebugPkg.dec
+ OvmfPkg/OvmfPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ ShellPkg/ShellPkg.dec
+ UefiPayloadPkg/UefiPayloadPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ UefiBootManagerLib
+ BootLogoLib
+ DevicePathLib
+ PciLib
+ NvVarsFileLib
+ QemuFwCfgLib
+ QemuFwCfgS3Lib
+ QemuLoadImageLib
+ QemuBootOrderLib
+ ReportStatusCodeLib
+ UefiLib
+ PlatformBmPrintScLib
+ Tcg2PhysicalPresenceLib
+ XenPlatformLib
+ DxeServicesLib
+ UefiDriverEntryPoint
+ PlatformBootManagerLib
+
+[Pcd]
+ gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits ## CONSUMES
+
+[Pcd.IA32, Pcd.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock
+
+[Protocols]
+ gEfiDecompressProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
+ gEfiS3SaveStateProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
+ gEfiDxeSmmReadyToLockProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
+ gEfiLoadedImageProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
+ gEfiFirmwareVolume2ProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
+ gUniversalPayloadPlatformBootManagerOverrideProtocolGuid # PROTOCOL ALWAYS_PRODUCED
+
+[Guids]
+ gEfiEndOfDxeEventGroupGuid
+ gEfiGlobalVariableGuid
+ gRootBridgesConnectedEventGroupGuid
+ gUefiShellFileGuid
+
+[Depex]
+ TRUE
\ No newline at end of file
--
2.26.2.windows.1


[PATCH 1/2] UefiPayloadPkg: Remove ACPI board Hob.

thiyagukb
 

BlSupportDxe would parse ACPI table and set PCDs.
Updated other modules to consume dynamic PCDs instead of HOBs.

Tested boot to shell with both SBL (universal and SblOpen)

Signed-off-by: Guo Dong <guo.dong@intel.com>
---
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h | 9 +++++++--
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 15 +++++++++++++--
UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h | 30 ------------------------------
UefiPayloadPkg/Include/Library/BlParseLib.h | 1 -
UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c | 45 ++++-----------------------------------------
UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf | 9 +++------
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c | 28 ++++++++++++----------------
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf | 5 ++++-
UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c | 57 ++++++---------------------------------------------------
UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf | 12 +++++++-----
UefiPayloadPkg/UefiPayloadEntry/PrintHob.c | 28 ----------------------------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 264 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 3 ---
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf | 1 -
UefiPayloadPkg/UefiPayloadPkg.dec | 26 +++++++++++++++++++++++++-
UefiPayloadPkg/UefiPayloadPkg.dsc | 7 +++++++
18 files changed, 247 insertions(+), 468 deletions(-)

diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
index 04e968a232..1d9da112c0 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
@@ -84,6 +84,152 @@ ReserveResourceInGcd (
}


+/**
+ Set the platform related PCDs using ACPI table
+
+ @param[in] AcpiTableBase ACPI table start address in memory
+
+ @retval RETURN_SUCCESS Successfully set PCDs based ACPI table.
+ @retval RETURN_NOT_FOUND Failed to find the required info
+
+**/
+RETURN_STATUS
+SetPcdsUsingAcpiTable (
+ IN UINT64 AcpiTableBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
+ EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
+ UINT32 *Entry32;
+ UINTN Entry32Num;
+ EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
+ EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
+ UINT64 *Entry64;
+ UINTN Entry64Num;
+ UINTN Idx;
+ UINT32 *Signature;
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *MmCfgHdr;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *MmCfgBase;
+ UINT64 PcieBaseAddress;
+ UINT64 PcieBaseSize;
+
+ Rsdp = (EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)(UINTN)AcpiTableBase;
+ DEBUG ((DEBUG_INFO, "Rsdp at 0x%p\n", Rsdp));
+ DEBUG ((DEBUG_INFO, "Rsdt at 0x%x, Xsdt at 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));
+
+ //
+ // Search Rsdt First
+ //
+ Fadt = NULL;
+ MmCfgHdr = NULL;
+ Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);
+ if (Rsdt != NULL) {
+ Entry32 = (UINT32 *)(Rsdt + 1);
+ Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+ for (Idx = 0; Idx < Entry32Num; Idx++) {
+ Signature = (UINT32 *)(UINTN)Entry32[Idx];
+ if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+ DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+ }
+
+ if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
+ DEBUG ((DEBUG_INFO, "Found MM config address in Rsdt\n"));
+ }
+
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
+ goto Done;
+ }
+ }
+ }
+
+ //
+ // Search Xsdt Second
+ //
+ Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);
+ if (Xsdt != NULL) {
+ Entry64 = (UINT64 *)(Xsdt + 1);
+ Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
+ for (Idx = 0; Idx < Entry64Num; Idx++) {
+ Signature = (UINT32 *)(UINTN)Entry64[Idx];
+ if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+ DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
+ }
+
+ if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
+ DEBUG ((DEBUG_INFO, "Found MM config address in Xsdt\n"));
+ }
+
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
+ goto Done;
+ }
+ }
+ }
+
+ if (Fadt == NULL) {
+ return RETURN_NOT_FOUND;
+ }
+
+Done:
+
+ if (MmCfgHdr != NULL) {
+ MmCfgBase = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)((UINT8*) MmCfgHdr + sizeof (*MmCfgHdr));
+ PcieBaseAddress = MmCfgBase->BaseAddress;
+ PcieBaseSize = (MmCfgBase->EndBusNumber + 1 - MmCfgBase->StartBusNumber) * 4096 * 32 * 8;
+ } else {
+ PcieBaseAddress = 0;
+ PcieBaseSize = 0;
+ }
+ DEBUG ((DEBUG_INFO, "PmCtrl Reg 0x%lx\n", Fadt->Pm1aCntBlk));
+ DEBUG ((DEBUG_INFO, "PmTimer Reg 0x%lx\n", Fadt->PmTmrBlk));
+ DEBUG ((DEBUG_INFO, "Reset Reg 0x%lx\n", Fadt->ResetReg.Address));
+ DEBUG ((DEBUG_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));
+ DEBUG ((DEBUG_INFO, "PmEvt Reg 0x%lx\n", Fadt->Pm1aEvtBlk));
+ DEBUG ((DEBUG_INFO, "PmGpeEn Reg 0x%lx\n", Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2));
+ DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", PcieBaseAddress));
+ DEBUG ((DEBUG_INFO, "PcieBaseSize 0x%lx\n", PcieBaseSize));
+
+ //
+ // Verify values for proper operation
+ //
+ ASSERT(Fadt->Pm1aCntBlk != 0);
+ ASSERT(Fadt->PmTmrBlk != 0);
+ ASSERT(Fadt->ResetReg.Address != 0);
+ ASSERT(Fadt->Pm1aEvtBlk != 0);
+ ASSERT(Fadt->Gpe0Blk != 0);
+
+ Status = PcdSet32S (PcdAcpiPm1aControlAddress, Fadt->Pm1aCntBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiPm1aEventAddress, Fadt->Pm1aEvtBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiGpe0EnableAddress, Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdAcpiResetRegister, Fadt->ResetReg.Address);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet8S (PcdAcpiResetValue, Fadt->ResetValue);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdAcpiPm1TimerRegister, Fadt->PmTmrBlk);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdPciExpressBaseAddress, PcieBaseAddress);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet64S (PcdPciExpressBaseSize, PcieBaseSize);
+ ASSERT_EFI_ERROR (Status);
+
+ return RETURN_SUCCESS;
+}
+
+
/**
Main entry for the bootloader support DXE module.

@@ -101,12 +247,13 @@ BlDxeEntryPoint (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HOB_GUID_TYPE *GuidHob;
- EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;
- ACPI_BOARD_INFO *AcpiBoardInfo;
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;
+ UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob;

Status = EFI_SUCCESS;
+
//
// Report MMIO/IO Resources
//
@@ -131,17 +278,14 @@ BlDxeEntryPoint (
}

//
- // Set PcdPciExpressBaseAddress and PcdPciExpressBaseSize by HOB info
+ // Install Acpi Table
//
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- if (GuidHob != NULL) {
- AcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
- Status = PcdSet64S (PcdPciExpressBaseAddress, AcpiBoardInfo->PcieBaseAddress);
- ASSERT_EFI_ERROR (Status);
- Status = PcdSet64S (PcdPciExpressBaseSize, AcpiBoardInfo->PcieBaseSize);
- ASSERT_EFI_ERROR (Status);
- }
-
+ GuidHob = GetFirstGuidHob (&gUniversalPayloadAcpiTableGuid);
+ if (GuidHob != NULL) {
+ AcpiTableHob = (UNIVERSAL_PAYLOAD_ACPI_TABLE *)GET_GUID_HOB_DATA (GuidHob);
+ DEBUG ((DEBUG_ERROR, "Install Acpi Table at 0x%lx \n", AcpiTableHob->Rsdp));
+ Status = SetPcdsUsingAcpiTable ((UINT64)(UINTN)AcpiTableHob->Rsdp);
+ ASSERT_EFI_ERROR (Status);
+ }
return EFI_SUCCESS;
}
-
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
index 3332a30eae..0790a5572a 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.h
@@ -19,9 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h>
#include <Library/HobLib.h>

+#include <Guid/Acpi.h>
#include <Guid/SmBios.h>
-#include <Guid/SystemTableInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>
+#include <UniversalPayload/AcpiTable.h>
+#include <UniversalPayload/SmbiosTable.h>
#include <Guid/GraphicsInfoHob.h>

+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <UniversalPayload/AcpiTable.h>
+
#endif
diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
index 1ccb250991..5d39a9b3f2 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
@@ -42,9 +42,8 @@
HobLib

[Guids]
- gUefiSystemTableInfoGuid
- gUefiAcpiBoardInfoGuid
gEfiGraphicsInfoHobGuid
+ gUniversalPayloadAcpiTableGuid

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
@@ -53,6 +52,18 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress

[Depex]
TRUE
diff --git a/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h b/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h
deleted file mode 100644
index 043b748ae4..0000000000
--- a/UefiPayloadPkg/Include/Guid/AcpiBoardInfoGuid.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/** @file
- This file defines the hob structure for board related information from acpi table
-
- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __ACPI_BOARD_INFO_GUID_H__
-#define __ACPI_BOARD_INFO_GUID_H__
-
-///
-/// Board information GUID
-///
-extern EFI_GUID gUefiAcpiBoardInfoGuid;
-
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved0[2];
- UINT8 ResetValue;
- UINT64 PmEvtBase;
- UINT64 PmGpeEnBase;
- UINT64 PmCtrlRegBase;
- UINT64 PmTimerRegBase;
- UINT64 ResetRegAddress;
- UINT64 PcieBaseAddress;
- UINT64 PcieBaseSize;
-} ACPI_BOARD_INFO;
-
-#endif
diff --git a/UefiPayloadPkg/Include/Library/BlParseLib.h b/UefiPayloadPkg/Include/Library/BlParseLib.h
index 8058c1a17b..6310a02f95 100644
--- a/UefiPayloadPkg/Include/Library/BlParseLib.h
+++ b/UefiPayloadPkg/Include/Library/BlParseLib.h
@@ -13,7 +13,6 @@
#include <UniversalPayload/AcpiTable.h>
#include <UniversalPayload/SmbiosTable.h>
#include <Guid/SystemTableInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>

#ifndef __BOOTLOADER_PARSE_LIB__
#define __BOOTLOADER_PARSE_LIB__
diff --git a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
index b86382d709..541327709c 100644
--- a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
+++ b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
@@ -1,7 +1,7 @@
/** @file
ACPI Timer implements one instance of Timer Library.

- Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -10,47 +10,11 @@
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
-#include <Library/HobLib.h>
#include <Library/DebugLib.h>
-
-#include <Guid/AcpiBoardInfoGuid.h>
#include <IndustryStandard/Acpi.h>

#define ACPI_TIMER_COUNT_SIZE BIT24

-UINTN mPmTimerReg = 0;
-
-/**
- The constructor function enables ACPI IO space.
-
- If ACPI I/O space not enabled, this function will enable it.
- It will always return RETURN_SUCCESS.
-
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-AcpiTimerLibConstructor (
- VOID
- )
-{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *pAcpiBoardInfo;
-
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
-
- mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;
-
- return EFI_SUCCESS;
-}
-
/**
Internal function to read the current tick counter of ACPI.

@@ -64,10 +28,9 @@ InternalAcpiGetTimerTick (
VOID
)
{
- if (mPmTimerReg == 0) {
- AcpiTimerLibConstructor ();
- }
- return IoRead32 (mPmTimerReg);
+
+ ASSERT (PcdGet32 (PcdAcpiPm1TimerRegister) != 0);
+ return IoRead32 (PcdGet32 (PcdAcpiPm1TimerRegister));
}

/**
diff --git a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
index 3e177cadc0..0fea86c83a 100644
--- a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
+++ b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
@@ -1,7 +1,7 @@
## @file
# ACPI Timer Library Instance.
#
-# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,8 +14,6 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib

- CONSTRUCTOR = AcpiTimerLibConstructor
-
#
# The following information is for reference only and not required by the build tools.
#
@@ -33,8 +31,7 @@
[LibraryClasses]
BaseLib
IoLib
- HobLib
DebugLib

-[Guids]
- gUefiAcpiBoardInfoGuid
+[Pcd]
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
index d37c91cc9f..3c79649b56 100644
--- a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
@@ -8,9 +8,7 @@
**/

#include <PiDxe.h>
-#include <Guid/AcpiBoardInfoGuid.h>
-
-#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
#include <Library/PciSegmentInfoLib.h>
#include <Library/DebugLib.h>

@@ -21,6 +19,17 @@ STATIC PCI_SEGMENT_INFO mPciSegment0 = {
255 // End bus number
};

+
+RETURN_STATUS
+EFIAPI
+PciSegmentInfoInitialize (
+ VOID
+ )
+{
+ mPciSegment0.BaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
+ return RETURN_SUCCESS;
+}
+
/**
Return an array of PCI_SEGMENT_INFO holding the segment information.

@@ -36,24 +45,11 @@ GetPciSegmentInfo (
UINTN *Count
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *AcpiBoardInfo;
-
ASSERT (Count != NULL);
if (Count == NULL) {
return NULL;
}

- if (mPciSegment0.BaseAddress == 0) {
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- AcpiBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);
- mPciSegment0.BaseAddress = AcpiBoardInfo->PcieBaseAddress;
- }
*Count = 1;
return &mPciSegment0;
}
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
index ec4dbaaa55..cc6ca83706 100644
--- a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
+++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.inf
@@ -16,6 +16,7 @@
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PciSegmentInfoLib | DXE_DRIVER
+ CONSTRUCTOR = PciSegmentInfoInitialize

#
# The following information is for reference only and not required by the build tools.
@@ -32,5 +33,7 @@

[LibraryClasses]
PcdLib
- HobLib
DebugLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
\ No newline at end of file
diff --git a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
index 2e4b7fe592..9e2e58f977 100644
--- a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -10,54 +10,8 @@
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
-#include <Library/HobLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Guid/AcpiBoardInfoGuid.h>

-ACPI_BOARD_INFO mAcpiBoardInfo;
-
-/**
- The constructor function to initialize mAcpiBoardInfo.
-
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-ResetSystemLibConstructor (
- VOID
- )
-{
- EFI_HOB_GUID_TYPE *GuidHob;
- ACPI_BOARD_INFO *AcpiBoardInfoPtr;
-
- //
- // Find the acpi board information guid hob
- //
- GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
- ASSERT (GuidHob != NULL);
-
- AcpiBoardInfoPtr = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
- CopyMem (&mAcpiBoardInfo, AcpiBoardInfoPtr, sizeof (ACPI_BOARD_INFO));
-
- return EFI_SUCCESS;
-}
-
-
-VOID
-AcpiPmControl (
- UINTN SuspendType
- )
-{
- UINTN PmCtrlReg;
-
- ASSERT (SuspendType <= 7);
-
- PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
- IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (SuspendType << 10));
- IoOr16 (PmCtrlReg, BIT13);
- CpuDeadLoop ();
-}

/**
Calling this function causes a system-wide reset. This sets
@@ -74,7 +28,7 @@ ResetCold (
VOID
)
{
- IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
+ IoWrite8 ((UINTN)PcdGet64 (PcdAcpiResetRegister), PcdGet8 (PcdAcpiResetValue));
CpuDeadLoop ();
}

@@ -91,7 +45,8 @@ ResetWarm (
VOID
)
{
- IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
+ IoWrite8 ((UINTN)PcdGet64 (PcdAcpiResetRegister), PcdGet8 (PcdAcpiResetValue));
+
CpuDeadLoop ();
}

@@ -113,17 +68,17 @@ ResetShutdown (
//
// GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
- IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);
+ IoWrite16 (PcdGet32 (PcdAcpiGpe0EnableAddress), 0);

//
// Clear Power Button Status
//
- IoWrite16((UINTN) mAcpiBoardInfo.PmEvtBase, BIT8);
+ IoWrite16(PcdGet32 (PcdAcpiPm1aEventAddress), BIT8);

//
// Transform system into S5 sleep state
//
- PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
+ PmCtrlReg = PcdGet32 (PcdAcpiPm1aControlAddress);
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
diff --git a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
index e7341c341a..77d73e7404 100644
--- a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
+++ b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -1,7 +1,7 @@
## @file
# Library instance for ResetSystem library class for bootloader
#
-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,7 +14,6 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib

- CONSTRUCTOR = ResetSystemLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
@@ -32,9 +31,12 @@
[LibraryClasses]
DebugLib
IoLib
- HobLib
BaseMemoryLib

-[Guids]
- gUefiAcpiBoardInfoGuid
+[Pcd]
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress

diff --git a/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c b/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
index 5fb638d4a4..6a92bffed1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
@@ -9,7 +9,6 @@
#include <UniversalPayload/PciRootBridges.h>
#include <UniversalPayload/ExtraData.h>
#include <Guid/MemoryTypeInformation.h>
-#include <Guid/AcpiBoardInfoGuid.h>

#define ROW_LIMITER 16

@@ -276,32 +275,6 @@ PrintSmbiosTablGuidHob (
return EFI_SUCCESS;
}

-/**
- Print the information in Acpi BoardInfo Guid Hob.
- @param[in] HobRaw A pointer to the start of gUefiAcpiBoardInfoGuid HOB.
- @retval EFI_SUCCESS If it completed successfully.
-**/
-EFI_STATUS
-PrintAcpiBoardInfoGuidHob (
- IN UINT8 *HobRaw,
- IN UINT16 HobLength
- )
-{
- ACPI_BOARD_INFO *AcpBoardInfo;
- AcpBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (HobRaw);
- ASSERT (HobLength >= sizeof (*AcpBoardInfo));
- DEBUG ((DEBUG_INFO, " Revision = 0x%x\n", AcpBoardInfo->Revision));
- DEBUG ((DEBUG_INFO, " Reserved0 = 0x%x\n", AcpBoardInfo->Reserved0));
- DEBUG ((DEBUG_INFO, " ResetValue = 0x%x\n", AcpBoardInfo->ResetValue));
- DEBUG ((DEBUG_INFO, " PmEvtBase = 0x%lx\n", AcpBoardInfo->PmEvtBase));
- DEBUG ((DEBUG_INFO, " PmGpeEnBase = 0x%lx\n", AcpBoardInfo->PmGpeEnBase));
- DEBUG ((DEBUG_INFO, " PmCtrlRegBase = 0x%lx\n", AcpBoardInfo->PmCtrlRegBase));
- DEBUG ((DEBUG_INFO, " PmTimerRegBase = 0x%lx\n", AcpBoardInfo->PmTimerRegBase));
- DEBUG ((DEBUG_INFO, " ResetRegAddress = 0x%lx\n", AcpBoardInfo->ResetRegAddress));
- DEBUG ((DEBUG_INFO, " PcieBaseAddress = 0x%lx\n", AcpBoardInfo->PcieBaseAddress));
- DEBUG ((DEBUG_INFO, " PcieBaseSize = 0x%lx\n", AcpBoardInfo->PcieBaseSize));
- return EFI_SUCCESS;
-}

/**
Print the information in Pci RootBridge Info Guid Hob.
@@ -415,7 +388,6 @@ GUID_HOB_PRINT_HANDLE GuidHobPrintHandleTable[] = {
{&gUniversalPayloadSerialPortInfoGuid, PrintSerialGuidHob, "gUniversalPayloadSerialPortInfoGuid(Serial Port Info)"},
{&gUniversalPayloadSmbios3TableGuid, PrintSmbios3GuidHob, "gUniversalPayloadSmbios3TableGuid(SmBios Guid)"},
{&gUniversalPayloadSmbiosTableGuid, PrintSmbiosTablGuidHob, "gUniversalPayloadSmbiosTableGuid(SmBios Guid)"},
- {&gUefiAcpiBoardInfoGuid, PrintAcpiBoardInfoGuidHob, "gUefiAcpiBoardInfoGuid(Acpi Guid)"},
{&gUniversalPayloadPciRootBridgeInfoGuid, PrintPciRootBridgeInfoGuidHob, "gUniversalPayloadPciRootBridgeInfoGuid(Pci Guid)"},
{&gEfiMemoryTypeInformationGuid, PrintMemoryTypeInfoGuidHob, "gEfiMemoryTypeInformationGuid(Memory Type Information Guid)"},
{&gUniversalPayloadExtraDataGuid, PrintExtraDataGuidHob, "gUniversalPayloadExtraDataGuid(PayLoad Extra Data Guid)"}
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
index 64a76e84b1..8ccf0f3ac8 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -9,85 +9,6 @@

STATIC UINT32 mTopOfLowerUsableDram = 0;

-/**
- Callback function to build resource descriptor HOB
-
- This function build a HOB based on the memory map entry info.
- It creates only EFI_RESOURCE_MEMORY_MAPPED_IO and EFI_RESOURCE_MEMORY_RESERVED
- resources.
-
- @param MemoryMapEntry Memory map entry info got from bootloader.
- @param Params A pointer to ACPI_BOARD_INFO.
-
- @retval EFI_SUCCESS Successfully build a HOB.
- @retval EFI_INVALID_PARAMETER Invalid parameter provided.
-**/
-EFI_STATUS
-MemInfoCallbackMmio (
- IN MEMROY_MAP_ENTRY *MemoryMapEntry,
- IN VOID *Params
- )
-{
- EFI_PHYSICAL_ADDRESS Base;
- EFI_RESOURCE_TYPE Type;
- UINT64 Size;
- EFI_RESOURCE_ATTRIBUTE_TYPE Attribue;
- ACPI_BOARD_INFO *AcpiBoardInfo;
-
- AcpiBoardInfo = (ACPI_BOARD_INFO *)Params;
- if (AcpiBoardInfo == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Skip types already handled in MemInfoCallback
- //
- if (MemoryMapEntry->Type == E820_RAM || MemoryMapEntry->Type == E820_ACPI) {
- return EFI_SUCCESS;
- }
-
- if (MemoryMapEntry->Base == AcpiBoardInfo->PcieBaseAddress) {
- //
- // MMCONF is always MMIO
- //
- Type = EFI_RESOURCE_MEMORY_MAPPED_IO;
- } else if (MemoryMapEntry->Base < mTopOfLowerUsableDram) {
- //
- // It's in DRAM and thus must be reserved
- //
- Type = EFI_RESOURCE_MEMORY_RESERVED;
- } else if ((MemoryMapEntry->Base < 0x100000000ULL) && (MemoryMapEntry->Base >= mTopOfLowerUsableDram)) {
- //
- // It's not in DRAM, must be MMIO
- //
- Type = EFI_RESOURCE_MEMORY_MAPPED_IO;
- } else {
- Type = EFI_RESOURCE_MEMORY_RESERVED;
- }
-
- Base = MemoryMapEntry->Base;
- Size = MemoryMapEntry->Size;
-
- Attribue = EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_TESTED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
-
- BuildResourceDescriptorHob (Type, Attribue, (EFI_PHYSICAL_ADDRESS)Base, Size);
- DEBUG ((DEBUG_INFO , "buildhob: base = 0x%lx, size = 0x%lx, type = 0x%x\n", Base, Size, Type));
-
- if (MemoryMapEntry->Type == E820_UNUSABLE ||
- MemoryMapEntry->Type == E820_DISABLED) {
- BuildMemoryAllocationHob (Base, Size, EfiUnusableMemory);
- } else if (MemoryMapEntry->Type == E820_PMEM) {
- BuildMemoryAllocationHob (Base, Size, EfiPersistentMemory);
- }
-
- return EFI_SUCCESS;
-}


/**
@@ -211,168 +132,6 @@ MemInfoCallback (
}


-
-/**
- Find the board related info from ACPI table
-
- @param AcpiTableBase ACPI table start address in memory
- @param AcpiBoardInfo Pointer to the acpi board info strucutre
-
- @retval RETURN_SUCCESS Successfully find out all the required information.
- @retval RETURN_NOT_FOUND Failed to find the required info.
-
-**/
-RETURN_STATUS
-ParseAcpiInfo (
- IN UINT64 AcpiTableBase,
- OUT ACPI_BOARD_INFO *AcpiBoardInfo
- )
-{
- EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
- EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
- UINT32 *Entry32;
- UINTN Entry32Num;
- EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
- EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
- UINT64 *Entry64;
- UINTN Entry64Num;
- UINTN Idx;
- UINT32 *Signature;
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *MmCfgHdr;
- EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *MmCfgBase;
-
- Rsdp = (EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)(UINTN)AcpiTableBase;
- DEBUG ((DEBUG_INFO, "Rsdp at 0x%p\n", Rsdp));
- DEBUG ((DEBUG_INFO, "Rsdt at 0x%x, Xsdt at 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));
-
- //
- // Search Rsdt First
- //
- Fadt = NULL;
- MmCfgHdr = NULL;
- Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);
- if (Rsdt != NULL) {
- Entry32 = (UINT32 *)(Rsdt + 1);
- Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
- for (Idx = 0; Idx < Entry32Num; Idx++) {
- Signature = (UINT32 *)(UINTN)Entry32[Idx];
- if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
- Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
- DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
- }
-
- if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
- MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
- DEBUG ((DEBUG_INFO, "Found MM config address in Rsdt\n"));
- }
-
- if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
- goto Done;
- }
- }
- }
-
- //
- // Search Xsdt Second
- //
- Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);
- if (Xsdt != NULL) {
- Entry64 = (UINT64 *)(Xsdt + 1);
- Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
- for (Idx = 0; Idx < Entry64Num; Idx++) {
- Signature = (UINT32 *)(UINTN)Entry64[Idx];
- if (*Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
- Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
- DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
- }
-
- if (*Signature == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {
- MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)Signature;
- DEBUG ((DEBUG_INFO, "Found MM config address in Xsdt\n"));
- }
-
- if ((Fadt != NULL) && (MmCfgHdr != NULL)) {
- goto Done;
- }
- }
- }
-
- if (Fadt == NULL) {
- return RETURN_NOT_FOUND;
- }
-
-Done:
-
- AcpiBoardInfo->PmCtrlRegBase = Fadt->Pm1aCntBlk;
- AcpiBoardInfo->PmTimerRegBase = Fadt->PmTmrBlk;
- AcpiBoardInfo->ResetRegAddress = Fadt->ResetReg.Address;
- AcpiBoardInfo->ResetValue = Fadt->ResetValue;
- AcpiBoardInfo->PmEvtBase = Fadt->Pm1aEvtBlk;
- AcpiBoardInfo->PmGpeEnBase = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;
-
- if (MmCfgHdr != NULL) {
- MmCfgBase = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)((UINT8*) MmCfgHdr + sizeof (*MmCfgHdr));
- AcpiBoardInfo->PcieBaseAddress = MmCfgBase->BaseAddress;
- AcpiBoardInfo->PcieBaseSize = (MmCfgBase->EndBusNumber + 1 - MmCfgBase->StartBusNumber) * 4096 * 32 * 8;
- } else {
- AcpiBoardInfo->PcieBaseAddress = 0;
- AcpiBoardInfo->PcieBaseSize = 0;
- }
- DEBUG ((DEBUG_INFO, "PmCtrl Reg 0x%lx\n", AcpiBoardInfo->PmCtrlRegBase));
- DEBUG ((DEBUG_INFO, "PmTimer Reg 0x%lx\n", AcpiBoardInfo->PmTimerRegBase));
- DEBUG ((DEBUG_INFO, "Reset Reg 0x%lx\n", AcpiBoardInfo->ResetRegAddress));
- DEBUG ((DEBUG_INFO, "Reset Value 0x%x\n", AcpiBoardInfo->ResetValue));
- DEBUG ((DEBUG_INFO, "PmEvt Reg 0x%lx\n", AcpiBoardInfo->PmEvtBase));
- DEBUG ((DEBUG_INFO, "PmGpeEn Reg 0x%lx\n", AcpiBoardInfo->PmGpeEnBase));
- DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", AcpiBoardInfo->PcieBaseAddress));
- DEBUG ((DEBUG_INFO, "PcieBaseSize 0x%lx\n", AcpiBoardInfo->PcieBaseSize));
-
- //
- // Verify values for proper operation
- //
- ASSERT(Fadt->Pm1aCntBlk != 0);
- ASSERT(Fadt->PmTmrBlk != 0);
- ASSERT(Fadt->ResetReg.Address != 0);
- ASSERT(Fadt->Pm1aEvtBlk != 0);
- ASSERT(Fadt->Gpe0Blk != 0);
-
- DEBUG_CODE_BEGIN ();
- BOOLEAN SciEnabled;
-
- //
- // Check the consistency of SCI enabling
- //
-
- //
- // Get SCI_EN value
- //
- if (Fadt->Pm1CntLen == 4) {
- SciEnabled = (IoRead32 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
- } else {
- //
- // if (Pm1CntLen == 2), use 16 bit IO read;
- // if (Pm1CntLen != 2 && Pm1CntLen != 4), use 16 bit IO read as a fallback
- //
- SciEnabled = (IoRead16 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
- }
-
- if (!(Fadt->Flags & EFI_ACPI_5_0_HW_REDUCED_ACPI) &&
- (Fadt->SmiCmd == 0) &&
- !SciEnabled) {
- //
- // The ACPI enabling status is inconsistent: SCI is not enabled but ACPI
- // table does not provide a means to enable it through FADT->SmiCmd
- //
- DEBUG ((DEBUG_ERROR, "ERROR: The ACPI enabling status is inconsistent: SCI is not"
- " enabled but the ACPI table does not provide a means to enable it through FADT->SmiCmd."
- " This may cause issues in OS.\n"));
- }
- DEBUG_CODE_END ();
-
- return RETURN_SUCCESS;
-}
-
-
/**
It will build HOBs based on information from bootloaders.

@@ -385,8 +144,6 @@ BuildHobFromBl (
)
{
EFI_STATUS Status;
- ACPI_BOARD_INFO AcpiBoardInfo;
- ACPI_BOARD_INFO *NewAcpiBoardInfo;
EFI_PEI_GRAPHICS_INFO_HOB GfxInfo;
EFI_PEI_GRAPHICS_INFO_HOB *NewGfxInfo;
EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GfxDeviceInfo;
@@ -460,27 +217,6 @@ BuildHobFromBl (
DEBUG ((DEBUG_INFO, "Detected ACPI Table at 0x%lx\n", AcpiTableHob->Rsdp));
}

- //
- // Create guid hob for acpi board information
- //
- Status = ParseAcpiInfo (AcpiTableHob->Rsdp, &AcpiBoardInfo);
- ASSERT_EFI_ERROR (Status);
- if (!EFI_ERROR (Status)) {
- NewAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));
- ASSERT (NewAcpiBoardInfo != NULL);
- CopyMem (NewAcpiBoardInfo, &AcpiBoardInfo, sizeof (ACPI_BOARD_INFO));
- DEBUG ((DEBUG_INFO, "Create acpi board info guid hob\n"));
- }
-
- //
- // Parse memory info and build memory HOBs for reserved DRAM and MMIO
- //
- DEBUG ((DEBUG_INFO , "Building ResourceDescriptorHobs for reserved memory:\n"));
- Status = ParseMemoryInfo (MemInfoCallbackMmio, &AcpiBoardInfo);
- if (EFI_ERROR(Status)) {
- return Status;
- }
-
//
// Parse platform specific information.
//
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
index 82590bf7c6..460253e4b6 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
@@ -24,11 +24,8 @@
#include <Library/BlParseLib.h>
#include <Library/PlatformSupportLib.h>
#include <Library/UefiCpuLib.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <Guid/SerialPortInfoGuid.h>
#include <Guid/MemoryMapInfoGuid.h>
-#include <Guid/AcpiBoardInfoGuid.h>
#include <Guid/GraphicsInfoHob.h>
#include <UniversalPayload/SmbiosTable.h>
#include <UniversalPayload/AcpiTable.h>
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..7b5ff184e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -63,7 +63,6 @@
gUefiSystemTableInfoGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
- gUefiAcpiBoardInfoGuid
gUniversalPayloadSmbiosTableGuid
gUniversalPayloadAcpiTableGuid

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..6394af5048 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -59,7 +59,6 @@
gUefiSystemTableInfoGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
- gUefiAcpiBoardInfoGuid
gEfiSmbiosTableGuid
gEfiAcpiTableGuid
gUefiSerialPortInfoGuid
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayloadPkg.dec
index 8f0a7e3f95..94b0e057ce 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -33,7 +33,6 @@
gEdkiiBootManagerMenuFileGuid = { 0xdf939333, 0x42fc, 0x4b2a, { 0xa5, 0x9e, 0xbb, 0xae, 0x82, 0x81, 0xfe, 0xef }}

gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}}
- gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}
gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }

@@ -77,3 +76,28 @@ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x80|UINT32|0x
gUefiPayloadPkgTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000|UINT32|0x00000017

gUefiPayloadPkgTokenSpaceGuid.PcdPcdDriverFile|{ 0x57, 0x72, 0xcf, 0x80, 0xab, 0x87, 0xf9, 0x47, 0xa3, 0xfe, 0xD5, 0x0B, 0x76, 0xd8, 0x95, 0x41 }|VOID*|0x00000018
+
+[PcdsDynamic, PcdsDynamicEx]
+## Defines the 32-bit Timer register access address that resides within the ACPI BAR.
+# @Prompt ACPI PM1 timer register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister |0|UINT32|0x00000019
+
+## Defines the Reset register access address that resides within the ACPI BAR.
+# @Prompt ACPI reset register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister |0|UINT64|0x00000020
+
+## Defines the reset value writing to ACPI reset register.
+# @Prompt Reset value to ACPI reset register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue |0|UINT8|0x00000021
+
+## Defines the system port address of the PM1a Control Register Block.
+# @Prompt PM1a control register address
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress |0|UINT32|0x00000022
+
+## Defines the system port address of the PM1a Event Register Block.
+# @Prompt PM1a event register register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress |0|UINT32|0x00000023
+
+## Defines the General-Purpose Event 0 Enable Register
+# @Prompt ACPI GPE0 enable register
+gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress |0|UINT32|0x00000024
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 856d5ea786..a0b0cfe454 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -409,6 +409,13 @@
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE

+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1TimerRegister|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetRegister|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiResetValue|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aControlAddress|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiPm1aEventAddress|0
+ gUefiPayloadPkgTokenSpaceGuid.PcdAcpiGpe0EnableAddress|0
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.
--
2.26.2.windows.1


Re: [PATCH 02/23] OvmfPkg/Sec: Update the check logic in SevEsIsEnabled

Min Xu
 

On September 11, 2021 9:14 AM, Erdem Aktas wrote:

RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429

SevEsIsEnabled return TRUE if SevEsWorkArea->SevEsEnabled is non-zero.
s/return/returns

It is correct when SevEsWorkArea is only used by SEV. After Intel TDX
is enabled in Ovmf, the SevEsWorkArea is shared by TDX and SEV. (This
is to avoid the waist of memory region in MEMFD). The value of
s/waist/waste
Thanks for reminder. Will fixed in next version.


[PATCH] IntelSiliconPkg/VTd: Fix typos in Vtd core drivers

Sheng Wei
 

It is DMA Remapping Hardware Unit Definition (DRHD).
The abbreviation is "DRHD".

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3622

Change-Id: Ia214c05b122b90fd58889763561165f3fa57b186
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Kowalewski Robert <robert.kowalewski@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
---
.../IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c | 12 ++++++------
.../IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 12 ++++++------
.../IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c | 6 +++---
3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c
index 2154690d..e9c99d0a 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c
@@ -539,14 +539,14 @@ RegisterPciDevice (
}

/**
- Process DMAR DHRD table.
+ Process DMAR DRHD table.

@param[in] VTdUnitInfo The VTd engine unit information.
@param[in] DmarDrhd The DRHD table.

**/
VOID
-ProcessDhrd (
+ProcessDrhd (
IN VTD_UNIT_INFO *VTdUnitInfo,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
)
@@ -581,10 +581,10 @@ ProcessDhrd (

if ((DmarDrhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) != 0) {
VTdUnitInfo->PciDeviceInfo.IncludeAllFlag = TRUE;
- DEBUG ((DEBUG_INFO," ProcessDhrd: with INCLUDE ALL\n"));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: with INCLUDE ALL\n"));
} else {
VTdUnitInfo->PciDeviceInfo.IncludeAllFlag = FALSE;
- DEBUG ((DEBUG_INFO," ProcessDhrd: without INCLUDE ALL\n"));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: without INCLUDE ALL\n"));
}

VTdUnitInfo->PciDeviceInfo.PciDeviceDataNumber = 0;
@@ -600,7 +600,7 @@ ProcessDhrd (
return;
}

- DEBUG ((DEBUG_INFO," ProcessDhrd: "));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: "));
switch (DmarDevScopeEntry->Type) {
case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT:
DEBUG ((DEBUG_INFO,"PCI Endpoint"));
@@ -708,7 +708,7 @@ ParseDmarAcpiTableDrhd (
switch (DmarHeader->Type) {
case EFI_ACPI_DMAR_TYPE_DRHD:
ASSERT (VtdIndex < VtdUnitNumber);
- ProcessDhrd (&VTdInfo->VtdUnitInfo[VtdIndex], (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader);
+ ProcessDrhd (&VTdInfo->VtdUnitInfo[VtdIndex], (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader);
VtdIndex++;

break;
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
index 2d9b4374..7b6bcca9 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
@@ -662,7 +662,7 @@ GetPciBusDeviceFunction (
}

/**
- Process DMAR DHRD table.
+ Process DMAR DRHD table.

@param[in] VtdIndex The index of VTd engine.
@param[in] DmarDrhd The DRHD table.
@@ -670,7 +670,7 @@ GetPciBusDeviceFunction (
@retval EFI_SUCCESS The DRHD table is processed.
**/
EFI_STATUS
-ProcessDhrd (
+ProcessDrhd (
IN UINTN VtdIndex,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
)
@@ -690,7 +690,7 @@ ProcessDhrd (

if ((DmarDrhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) != 0) {
mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag = TRUE;
- DEBUG ((DEBUG_INFO," ProcessDhrd: with INCLUDE ALL\n"));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: with INCLUDE ALL\n"));

Status = ScanPciBus((VOID *)VtdIndex, DmarDrhd->SegmentNumber, 0, ScanBusCallbackRegisterPciDevice);
if (EFI_ERROR (Status)) {
@@ -698,7 +698,7 @@ ProcessDhrd (
}
} else {
mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag = FALSE;
- DEBUG ((DEBUG_INFO," ProcessDhrd: without INCLUDE ALL\n"));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: without INCLUDE ALL\n"));
}

DmarDevScopeEntry = (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)((UINTN)(DmarDrhd + 1));
@@ -709,7 +709,7 @@ ProcessDhrd (
return Status;
}

- DEBUG ((DEBUG_INFO," ProcessDhrd: "));
+ DEBUG ((DEBUG_INFO," ProcessDrhd: "));
switch (DmarDevScopeEntry->Type) {
case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT:
DEBUG ((DEBUG_INFO,"PCI Endpoint"));
@@ -877,7 +877,7 @@ ParseDmarAcpiTableDrhd (
switch (DmarHeader->Type) {
case EFI_ACPI_DMAR_TYPE_DRHD:
ASSERT (VtdIndex < mVtdUnitNumber);
- Status = ProcessDhrd (VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader);
+ Status = ProcessDrhd (VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader);
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
index d920d136..1bb74f40 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c
@@ -356,14 +356,14 @@ GetVtdEngineNumber (
}

/**
- Process DMAR DHRD table.
+ Process DMAR DRHD table.

@param[in] VTdInfo The VTd engine context information.
@param[in] VtdIndex The index of VTd engine.
@param[in] DmarDrhd The DRHD table.
**/
VOID
-ProcessDhrd (
+ProcessDrhd (
IN VTD_INFO *VTdInfo,
IN UINTN VtdIndex,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
@@ -415,7 +415,7 @@ ParseDmarAcpiTableDrhd (
switch (DmarHeader->Type) {
case EFI_ACPI_DMAR_TYPE_DRHD:
ASSERT (VtdIndex < VtdUnitNumber);
- ProcessDhrd (VTdInfo, VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader);
+ ProcessDrhd (VTdInfo, VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader);
VtdIndex++;

break;
--
2.16.2.windows.1

2161 - 2180 of 82656