Date   

Re: [Patch v3 00/40] MP Initialize Library

Fan, Jeff <jeff.fan@...>
 

Laszlo,

I sent one evaluate patch for you by adding back GDT table load in CpuDxe. Could you please help to verify if it could fix IA32 S3 issue?

Another solution is to remove hardcode from PiSmmCpuDxeSmm driver. But I do not prefer to do it this time. :-)

Thanks!
Jeff

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Laszlo Ersek
Sent: Thursday, July 28, 2016 11:21 PM
To: Fan, Jeff
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/28/16 15:55, Fan, Jeff wrote:
Laszlo,

Many thanks for your verification.

Your dump information and analysis result are very useful. I guess the issue happened at
UefiCpuPkg\PiSmmCpuDxeSmm\Ia32\MpFuncs.nasm:80 a32 jmp dword 0x20:0x0

The Proteted mode CS in current GDT table is not 0x20. But the PiSmmCpuDxeSmm hardcode it to 0x20.
Ah, good point; I recall:

commit 0d4c1db81aab86963536deb8253f35546c4398ea
Author: Michael Kinney <michael.d.kinney@...>
Date: Fri Oct 30 17:32:27 2015 +0000

UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim

as another related patch.

I will try it fix it tomorrow and feedback to you.
Thank you, I'll attempt to test it soon after.

Cheers
Laszlo

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Thursday, July 28, 2016 9:24 PM
To: Fan, Jeff; edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/25/16 04:52, Jeff Fan wrote:
We add MP Initialize Library defined in UefiCpuPkg/Include/Library/MpInitLib.h.
It will provide basic functionalities of MP services and could be
consumed by CPU MP PEI and CPU MP DXE to produce CPU MP PPI and CPU
MP Protocol. Then most of code could be shared between PEI and DXE modules.

PeiMpInitLib and DxeMpInitLib are added to make the CpuMpPei and
CpuDxe more simply.

I also updated the Ovmf Platform and Quark platform to consume MP
Initialize library. I have tested Ovmf platform and have not tested Quark yet.

v3:
1. Update Patch #2, #4 - #8, #28, #33, #36, #38 per Giri's comments to
a. Update SDM date to June, 2016
b. Mention BCD format in CPU_MICROCODE_DATE
c. Rename ProcessorChecksum to Checksum to match SDM.
d. Add whitespace after MpInitLibInitialize
e. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec.
f. Rename NumApsExecutingLoction to NumApsExecutingLocation
g. Add whitespace after ; in .nasm file
h. Rename *RellocateAp* to *RelocateAp*
2. Update Patch #16, #17, #29-#32 to
a. Use CamelCase for mStopCheckAllApsStatus and CheckAndUpdateApsStatus().
3. Update Patch #36 and #39 to
a. Add PeiMpInitLib instance in UefiCpuPkg.dsc
b. Add DxeMpInitLib instance in UefiCpuPkg.dsc
4. Update Patch #39 and #40 to
a. move the code of consuming MP Initialize library from patch #40 to
patch #39.
5. Update Patch #1, #3 - #8, #16 to
a. Add Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>

I fork the whole tree with the updated v3 patches at
https://github.com/vanjeff/edk2/tree/MpInitLibV3 for review.
I rebased your branch (originally at 09948b72fbb7) on top of current master (= 39dbc4d55347), and built it. It builds fine.

Scenarios that I tested, and seem to work:

* Q35, Ia32, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: FAIL (see details below)

* i440fx, X64, without -D SMM_REQUIRE, 8 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: pass

I re-verified the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86>, which requires CpuMpPei to actually *work* on both boot paths, and it works fine.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass

On the normal boot path, I also verified that the MTRR setup was consistent across the VCPUs (otherwise Linux would have complained), plus the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86> was working fine too. I also checked that the UEFI variable services worked, bound to the BSP, and then bound to the first AP as well. (Using the "taskset" Linux command, with "efibootmgr", to list the variables.) I quickly checked that Secure Boot was still recognized by the guest (Fedora) as enabled.

- S3 resume: pass

Repeated the BZ#86 check and the variable access checks from within the resumed guest, all pass.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Windows 8.1 guest:
- normal boot path: pass

On the normal boot path, I checked Secure Boot enablement with PowerShell.

- S3 resume: pass.

Now, about the one failure case. QEMU logs the following:

KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
extra data[0]: 80000b0d
extra data[0]: 80000b0d
extra data[1]: 31
extra data[1]: 31
extra data[0]: 80000b0d
extra data[1]: 31

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6
I didn't try to analyze this in depth, but from the hex-encoded instruction stream, it looks like KVM dislikes the 0x66 prefix in front of a JMP instruction (EA, if I recall correctly). Given that this is logged all at once for three processors (out of 4 -- see the description of that test case above), I believe one of the far jumps in the AP mode switching code is incorrect, on the S3 resume path, for Ia32 + SMM.

Perhaps one of the "a32" or "o32" NASM prefixes should be tweaked. Similar examples: <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13258.html>, <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13259.html>.

Thanks!
Laszlo
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edk2-devel mailing list
edk2-devel@...
https://lists.01.org/mailman/listinfo/edk2-devel


Re: [Patch v3 00/40] MP Initialize Library

Laszlo Ersek
 

On 07/29/16 10:57, Fan, Jeff wrote:
Laszlo,

I sent one evaluate patch for you by adding back GDT table load in CpuDxe. Could you please help to verify if it could fix IA32 S3 issue?
Yes, I'll try to look into it shortly. I'll have to retest the other
cases as well.

Thanks!
Laszlo

Another solution is to remove hardcode from PiSmmCpuDxeSmm driver. But I do not prefer to do it this time. :-)

Thanks!
Jeff

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Laszlo Ersek
Sent: Thursday, July 28, 2016 11:21 PM
To: Fan, Jeff
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/28/16 15:55, Fan, Jeff wrote:
Laszlo,

Many thanks for your verification.

Your dump information and analysis result are very useful. I guess the issue happened at
UefiCpuPkg\PiSmmCpuDxeSmm\Ia32\MpFuncs.nasm:80 a32 jmp dword 0x20:0x0

The Proteted mode CS in current GDT table is not 0x20. But the PiSmmCpuDxeSmm hardcode it to 0x20.
Ah, good point; I recall:

commit 0d4c1db81aab86963536deb8253f35546c4398ea
Author: Michael Kinney <michael.d.kinney@...>
Date: Fri Oct 30 17:32:27 2015 +0000

UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim

as another related patch.

I will try it fix it tomorrow and feedback to you.
Thank you, I'll attempt to test it soon after.

Cheers
Laszlo

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Thursday, July 28, 2016 9:24 PM
To: Fan, Jeff; edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/25/16 04:52, Jeff Fan wrote:
We add MP Initialize Library defined in UefiCpuPkg/Include/Library/MpInitLib.h.
It will provide basic functionalities of MP services and could be
consumed by CPU MP PEI and CPU MP DXE to produce CPU MP PPI and CPU
MP Protocol. Then most of code could be shared between PEI and DXE modules.

PeiMpInitLib and DxeMpInitLib are added to make the CpuMpPei and
CpuDxe more simply.

I also updated the Ovmf Platform and Quark platform to consume MP
Initialize library. I have tested Ovmf platform and have not tested Quark yet.

v3:
1. Update Patch #2, #4 - #8, #28, #33, #36, #38 per Giri's comments to
a. Update SDM date to June, 2016
b. Mention BCD format in CPU_MICROCODE_DATE
c. Rename ProcessorChecksum to Checksum to match SDM.
d. Add whitespace after MpInitLibInitialize
e. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec.
f. Rename NumApsExecutingLoction to NumApsExecutingLocation
g. Add whitespace after ; in .nasm file
h. Rename *RellocateAp* to *RelocateAp*
2. Update Patch #16, #17, #29-#32 to
a. Use CamelCase for mStopCheckAllApsStatus and CheckAndUpdateApsStatus().
3. Update Patch #36 and #39 to
a. Add PeiMpInitLib instance in UefiCpuPkg.dsc
b. Add DxeMpInitLib instance in UefiCpuPkg.dsc
4. Update Patch #39 and #40 to
a. move the code of consuming MP Initialize library from patch #40 to
patch #39.
5. Update Patch #1, #3 - #8, #16 to
a. Add Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>

I fork the whole tree with the updated v3 patches at
https://github.com/vanjeff/edk2/tree/MpInitLibV3 for review.
I rebased your branch (originally at 09948b72fbb7) on top of current master (= 39dbc4d55347), and built it. It builds fine.

Scenarios that I tested, and seem to work:

* Q35, Ia32, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: FAIL (see details below)

* i440fx, X64, without -D SMM_REQUIRE, 8 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: pass

I re-verified the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86>, which requires CpuMpPei to actually *work* on both boot paths, and it works fine.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass

On the normal boot path, I also verified that the MTRR setup was consistent across the VCPUs (otherwise Linux would have complained), plus the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86> was working fine too. I also checked that the UEFI variable services worked, bound to the BSP, and then bound to the first AP as well. (Using the "taskset" Linux command, with "efibootmgr", to list the variables.) I quickly checked that Secure Boot was still recognized by the guest (Fedora) as enabled.

- S3 resume: pass

Repeated the BZ#86 check and the variable access checks from within the resumed guest, all pass.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Windows 8.1 guest:
- normal boot path: pass

On the normal boot path, I checked Secure Boot enablement with PowerShell.

- S3 resume: pass.

Now, about the one failure case. QEMU logs the following:

KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
extra data[0]: 80000b0d
extra data[0]: 80000b0d
extra data[1]: 31
extra data[1]: 31
extra data[0]: 80000b0d
extra data[1]: 31

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6
I didn't try to analyze this in depth, but from the hex-encoded instruction stream, it looks like KVM dislikes the 0x66 prefix in front of a JMP instruction (EA, if I recall correctly). Given that this is logged all at once for three processors (out of 4 -- see the description of that test case above), I believe one of the far jumps in the AP mode switching code is incorrect, on the S3 resume path, for Ia32 + SMM.

Perhaps one of the "a32" or "o32" NASM prefixes should be tweaked. Similar examples: <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13258.html>, <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13259.html>.

Thanks!
Laszlo
_______________________________________________
edk2-devel mailing list
edk2-devel@...
https://lists.01.org/mailman/listinfo/edk2-devel


Re: [Patch] Vlv2TbltDevicePkg:Signal EndOfDxe Event.

Lu, ShifeiX A <shifeix.a.lu@...>
 

Thanks Laszlo!
I will follow it.


Shifei

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Laszlo Ersek
Sent: Friday, July 29, 2016 3:51 PM
To: Wei, David; Lu, ShifeiX A
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch] Vlv2TbltDevicePkg:Signal EndOfDxe Event.

On 07/29/16 04:31, Wei, David wrote:
Reviewed-by: David Wei <david.wei@...>



Thanks,
David Wei

Intel SSG BIOS Team
I recommend using the new EfiEventGroupSignal() function from UefiLib instead.

Please refer to the following commits:

ca8f50e88e03 MdePkg/UefiLib: move InternalEmptyFunction to UefiLib.c 772fb7cb13de MdePkg/UefiLib: introduce EfiEventGroupSignal
ff55dd3befb4 IntelFrameworkPkg/FrameworkUefiLib: move InternalEmptyFunction to UefiLib.c
6212b9481d82 IntelFrameworkPkg/FrameworkUefiLib: implement EfiEventGroupSignal dfc9514794fc ArmVirtPkg/PlatformIntelBdsLib: rebase to EfiEventGroupSignal 36e8e6992d0c OvmfPkg/PlatformBdsLib: rebase to EfiEventGroupSignal

Thanks
Laszlo


-----Original Message-----
From: Lu, ShifeiX A
Sent: Friday, July 29, 2016 10:27 AM
To: edk2-devel@...
Cc: Wei; Wei, David <david.wei@...>
Subject: [Patch] Vlv2TbltDevicePkg:Signal EndOfDxe Event.

According to PI spec,EndOfDxe Event should be signaled before
DxeSmmReadyToLock protocol installation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex <shifeix.a.lu@...>
---
.../Library/PlatformBdsLib/BdsPlatform.c | 37 +++++++++++++++++++++-
.../Library/PlatformBdsLib/PlatformBdsLib.inf | 3 +-
2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
index 195d734..5df3396 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -1,8 +1,8 @@
/** @file

- Copyright (c) 2004 - 2015, Intel Corporation. All rights
reserved.<BR>
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights
+ reserved.<BR>


This program and the accompanying materials are licensed and made
available under

the terms and conditions of the BSD License that accompanies this distribution.

The full text of the license may be found at

http://opensource.org/licenses/bsd-license.php.

@@ -203,10 +203,29 @@ ShellImageCallback ( {
BdsSetConsoleMode (TRUE);
DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n")); }

+/**
+ An empty function to pass error checking of CreateEventEx ().
+
+ @param Event Event whose notification function is being invoked.
+ @param Context Pointer to the notification function's context,
+ which is implementation-dependent.
+
+**/
+STATIC
+VOID
+EFIAPI
+EmptyCallbackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ return;
+}
+
//
// BDS Platform Functions
//
/**
Platform Bds init. Incude the platform firmware vendor, revision @@
-223,12 +242,28 @@ PlatformBdsInit (
VOID
)
{
EFI_STATUS Status;
EFI_EVENT ShellImageEvent;
+ EFI_EVENT EndOfDxeEvent;
EFI_GUID ShellEnvProtocol = SHELL_ENVIRONMENT_INTERFACE_PROTOCOL;

+ //
+ // Signal EndOfDxe PI Event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ EmptyCallbackFunction,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ if (!EFI_ERROR (Status)) {
+ gBS->SignalEvent (EndOfDxeEvent); }
+
#ifdef __GNUC__
SerialPortWrite((UINT8 *)">>>>BdsEntry[GCC]\r\n", 19);
#else
SerialPortWrite((UINT8 *)">>>>BdsEntry\r\n", 14);
#endif
diff --git
a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
index 45578e8..c64bab9 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
@@ -1,9 +1,9 @@
#/** @file
# Component name for module PlatformBootManagerLib # -# Copyright
(c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008 - 2016, Intel Corporation. All rights
+reserved.<BR>
#

# This program and the accompanying materials are licensed and made
available under

# the terms and conditions of the BSD License that accompanies this distribution.

# The full text of the license may be found at

# http://opensource.org/licenses/bsd-license.php.

@@ -95,10 +95,11 @@
gEfiMemoryTypeInformationGuid
gEfiCapsuleVendorGuid
gEfiGlobalVariableGuid
gEfiNormalSetupGuid
gEfiPartTypeSystemPartGuid
+ gEfiEndOfDxeEventGroupGuid

[Pcd]
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
_______________________________________________
edk2-devel mailing list
edk2-devel@...
https://lists.01.org/mailman/listinfo/edk2-devel


[Patch] Vlv2TbltDevicePkg:Signal EndOfDxe Event.

lushifex <shifeix.a.lu@...>
 

According to PI spec,EndOfDxe Event should be signaled
before DxeSmmReadyToLock protocol installation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: lushifex <shifeix.a.lu@...>
---
Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c | 7 ++++++-
Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf | 3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
index 195d734..82ad974 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -1,8 +1,8 @@
/** @file

- Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>


This program and the accompanying materials are licensed and made available under

the terms and conditions of the BSD License that accompanies this distribution.

The full text of the license may be found at

http://opensource.org/licenses/bsd-license.php.

@@ -224,10 +224,15 @@ PlatformBdsInit (
)
{
EFI_STATUS Status;
EFI_EVENT ShellImageEvent;
EFI_GUID ShellEnvProtocol = SHELL_ENVIRONMENT_INTERFACE_PROTOCOL;
+
+ //
+ // Signal EndOfDxe PI Event
+ //
+ EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);

#ifdef __GNUC__
SerialPortWrite((UINT8 *)">>>>BdsEntry[GCC]\r\n", 19);
#else
SerialPortWrite((UINT8 *)">>>>BdsEntry\r\n", 14);
diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
index 45578e8..c64bab9 100644
--- a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
@@ -1,9 +1,9 @@
#/** @file
# Component name for module PlatformBootManagerLib
#
-# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
#

# This program and the accompanying materials are licensed and made available under

# the terms and conditions of the BSD License that accompanies this distribution.

# The full text of the license may be found at

# http://opensource.org/licenses/bsd-license.php.

@@ -95,10 +95,11 @@
gEfiMemoryTypeInformationGuid
gEfiCapsuleVendorGuid
gEfiGlobalVariableGuid
gEfiNormalSetupGuid
gEfiPartTypeSystemPartGuid
+ gEfiEndOfDxeEventGroupGuid

[Pcd]
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
--
2.6.2.windows.1


Re: [PATCH v5] Platforms/ARM/Juno: Create SMBIOS/DMI data for Juno

Leif Lindholm <leif.lindholm@...>
 

On Thu, Jul 28, 2016 at 09:41:57AM -0500, Jeremy Linton wrote:
SMBIOS data is consumed by a wide range of enterprise applications.

Fill in the basic requirements of the SMBIOS specification by hardcoding
the minimum required structures and data using Juno information. Only the
juno revision, memory ranges and CPU types are dynamic.

Add the resulting Juno SmbiosPlatformDxe and MdeModulePkg/SmbiosDxe to the
build and firmware image. With these changes, the EFI BDS, EFI shell,
and Linux dmidecode command return useful information.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@...>
Thanks, Jeremy.
Pushed to OpenPlatformPkg.

---
Platforms/ARM/Juno/ArmJuno.dsc | 12 +
Platforms/ARM/Juno/ArmJuno.fdf | 6 +
.../ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 865 +++++++++++++++++++++
.../Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 68 ++
4 files changed, 951 insertions(+)
create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c
create mode 100644 Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf

diff --git a/Platforms/ARM/Juno/ArmJuno.dsc b/Platforms/ARM/Juno/ArmJuno.dsc
index 84c2441..c51d8f2 100644
--- a/Platforms/ARM/Juno/ArmJuno.dsc
+++ b/Platforms/ARM/Juno/ArmJuno.dsc
@@ -178,6 +178,12 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }

+ #
+ # SMBIOS entry point version
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
+
[PcdsPatchableInModule]
# Console Resolution (Full HD)
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920
@@ -312,6 +318,12 @@
}

#
+ # SMBIOS/DMI
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
+ #
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
diff --git a/Platforms/ARM/Juno/ArmJuno.fdf b/Platforms/ARM/Juno/ArmJuno.fdf
index a01db20..04d9a3c 100644
--- a/Platforms/ARM/Juno/ArmJuno.fdf
+++ b/Platforms/ARM/Juno/ArmJuno.fdf
@@ -202,6 +202,12 @@ FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092
INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf

#
+ # SMBIOS/DMI
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF OpenPlatformPkg/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
+ #
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c
new file mode 100644
index 0000000..fe5498e
--- /dev/null
+++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -0,0 +1,865 @@
+/** @file
+ This driver installs SMBIOS information for ARM Juno platforms
+
+ Copyright (c) 2015, ARM Limited. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <ArmPlatform.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+
+#define TYPE0_STRINGS \
+ "EFI Development Kit II / ARM LTD\0" /* Vendor */ \
+ "EDK II\0" /* BiosVersion */ \
+ __DATE__"\0" /* BiosReleaseDate */
+
+#define TYPE1_STRINGS \
+ "ARM LTD\0" /* Manufacturer */ \
+ "ARM Juno Development Platform\0" /* Product Name */ \
+ "None\0" /* Version */ \
+ " \0" /* 20 character buffer */
+
+#define TYPE2_STRINGS \
+ "ARM LTD\0" /* Manufacturer */ \
+ "ARM Juno Development Platform\0" /* Product Name */ \
+ "R0\0" /* Version */ \
+ "Serial Not Set\0" /* Serial */ \
+ "Base of Chassis\0" /* board location */ \
+ "R1\0" /* Version */ \
+ "R2\0" /* Version */
+
+#define TYPE3_STRINGS \
+ "ARM LTD\0" /* Manufacturer */ \
+ "None\0" /* Version */ \
+ "Serial Not Set\0" /* Serial */
+
+#define TYPE4_STRINGS \
+ "BGA-1156\0" /* socket type */ \
+ "ARM LTD\0" /* manufactuer */ \
+ "Cortex-A57\0" /* processor 1 description */ \
+ "Cortex-A53\0" /* processor 2 description */ \
+ "Cortex-A72\0" /* processor 2 description */ \
+ "0xd03\0" /* A53 part number */ \
+ "0xd07\0" /* A57 part number */ \
+ "0xd08\0" /* A72 part number */
+
+#define TYPE7_STRINGS \
+ "L1 Instruction\0" /* L1I */ \
+ "L1 Data\0" /* L1D */ \
+ "L2\0" /* L2 */
+
+#define TYPE9_STRINGS \
+ "PCIE_SLOT0\0" /* Slot0 */ \
+ "PCIE_SLOT1\0" /* Slot1 */ \
+ "PCIE_SLOT2\0" /* Slot2 */ \
+ "PCIE_SLOT3\0" /* Slot3 */
+
+#define TYPE16_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE17_STRINGS \
+ "RIGHT SIDE\0" /* location */ \
+ "BANK 0\0" /* bank description */
+
+#define TYPE19_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE32_STRINGS \
+ "\0" /* nothing */
+
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+ SMBIOS_TABLE_TYPE0 Base;
+ INT8 Strings[sizeof(TYPE0_STRINGS)];
+} ARM_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE1 Base;
+ UINT8 Strings[sizeof(TYPE1_STRINGS)];
+} ARM_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE2 Base;
+ UINT8 Strings[sizeof(TYPE2_STRINGS)];
+} ARM_TYPE2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE3 Base;
+ UINT8 Strings[sizeof(TYPE3_STRINGS)];
+} ARM_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE4 Base;
+ UINT8 Strings[sizeof(TYPE4_STRINGS)];
+} ARM_TYPE4;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof(TYPE7_STRINGS)];
+} ARM_TYPE7;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS)];
+} ARM_TYPE9;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE16 Base;
+ UINT8 Strings[sizeof(TYPE16_STRINGS)];
+} ARM_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ UINT8 Strings[sizeof(TYPE17_STRINGS)];
+} ARM_TYPE17;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE19 Base;
+ UINT8 Strings[sizeof(TYPE19_STRINGS)];
+} ARM_TYPE19;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE32 Base;
+ UINT8 Strings[sizeof(TYPE32_STRINGS)];
+} ARM_TYPE32;
+
+// SMBIOS tables often reference each other using
+// fixed constants, define a list of these constants
+// for our hardcoded tables
+enum SMBIOS_REFRENCE_HANDLES {
+ SMBIOS_HANDLE_A57_L1I = 0x1000,
+ SMBIOS_HANDLE_A57_L1D,
+ SMBIOS_HANDLE_A57_L2,
+ SMBIOS_HANDLE_A53_L1I,
+ SMBIOS_HANDLE_A53_L1D,
+ SMBIOS_HANDLE_A53_L2,
+ SMBIOS_HANDLE_MOTHERBOARD,
+ SMBIOS_HANDLE_CHASSIS,
+ SMBIOS_HANDLE_A72_CLUSTER,
+ SMBIOS_HANDLE_A57_CLUSTER,
+ SMBIOS_HANDLE_A53_CLUSTER,
+ SMBIOS_HANDLE_MEMORY,
+ SMBIOS_HANDLE_DIMM
+};
+
+#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure
+
+#pragma pack()
+
+// BIOS information (section 7.1)
+STATIC ARM_TYPE0 mArmDefaultType0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, // SMBIOS_TABLE_STRING Vendor
+ 2, // SMBIOS_TABLE_STRING BiosVersion
+ 0xE800,// UINT16 BiosSegment
+ 3, // SMBIOS_TABLE_STRING BiosReleaseDate
+ 0, // UINT8 BiosSize
+ {
+ 0,0,0,0,0,0,
+ 1, //PCI supported
+ 0,
+ 1, //PNP supported
+ 0,
+ 1, //BIOS upgradable
+ 0, 0, 0,
+ 1, //Boot from CD
+ 1, //selectable boot
+ }, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics
+ { // BIOSCharacteristicsExtensionBytes[2]
+ 0x3,
+ 0xC,
+ },
+ 0, // UINT8 SystemBiosMajorRelease
+ 0, // UINT8 SystemBiosMinorRelease
+ 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease
+ 0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease
+ },
+ // Text strings (unformatted area)
+ TYPE0_STRINGS
+};
+
+// System information (section 7.2)
+STATIC CONST ARM_TYPE1 mArmDefaultType1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
+ sizeof(SMBIOS_TABLE_TYPE1),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, //Manufacturer
+ 2, //Product Name
+ 3, //Version
+ 4, //Serial
+ { 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }}, //UUID
+ 6, //Wakeup type
+ 0, //SKU
+ 0, //Family
+ },
+ // Text strings (unformatted)
+ TYPE1_STRINGS
+};
+
+// Baseboard (section 7.3)
+STATIC ARM_TYPE2 mArmDefaultType2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
+ SMBIOS_HANDLE_MOTHERBOARD,
+ },
+ 1, //Manufacturer
+ 2, //Product Name
+ 3, //Version
+ 4, //Serial
+ 0, //Asset tag
+ {1}, //motherboard, not replaceable
+ 5, //location of board
+ SMBIOS_HANDLE_CHASSIS,
+ BaseBoardTypeMotherBoard,
+ 1,
+ {SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY},
+ },
+ TYPE2_STRINGS
+};
+
+// Enclosure
+STATIC CONST ARM_TYPE3 mArmDefaultType3 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
+ SMBIOS_HANDLE_CHASSIS,
+ },
+ 1, //Manufacturer
+ 4, //enclosure type (low profile desktop)
+ 2, //version
+ 3, //serial
+ 0, //asset tag
+ ChassisStateUnknown, //boot chassis state
+ ChassisStateSafe, //power supply state
+ ChassisStateSafe, //thermal state
+ ChassisSecurityStatusNone, //security state
+ {0,0,0,0,}, //OEM defined
+ 1, //1U height
+ 1, //number of power cords
+ 0, //no contained elements
+ },
+ TYPE3_STRINGS
+};
+
+// Processor
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
+ SMBIOS_HANDLE_A72_CLUSTER,
+ },
+ 1, //socket type
+ 3, //processor type CPU
+ ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+ 2, //manufactuer
+ {{0,},{0.}}, //processor id
+ 5, //version
+ {0,0,0,0,0,1}, //voltage
+ 0, //external clock
+ 1200, //max speed
+ 1200, //current speed
+ 0x41, //status
+ ProcessorUpgradeOther,
+ SMBIOS_HANDLE_A57_L1I, //l1 cache handle
+ SMBIOS_HANDLE_A57_L2, //l2 cache handle
+ 0xFFFF, //l3 cache handle
+ 0, //serial not set
+ 0, //asset not set
+ 8, //part number
+ 2, //core count in socket
+ 2, //enabled core count in socket
+ 0, //threads per socket
+ 0xEC, // processor characteristics
+ ProcessorFamilyARM, //ARM core
+ },
+ TYPE4_STRINGS
+};
+
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
+ SMBIOS_HANDLE_A57_CLUSTER,
+ },
+ 1, //socket type
+ 3, //processor type CPU
+ ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+ 2, //manufactuer
+ {{0,},{0.}}, //processor id
+ 3, //version
+ {0,0,0,0,0,1}, //voltage
+ 0, //external clock
+ 1200, //max speed
+ 1200, //current speed
+ 0x41, //status
+ ProcessorUpgradeOther,
+ SMBIOS_HANDLE_A57_L1I, //l1 cache handle
+ SMBIOS_HANDLE_A57_L2, //l2 cache handle
+ 0xFFFF, //l3 cache handle
+ 0, //serial not set
+ 0, //asset not set
+ 7, //part number
+ 2, //core count in socket
+ 2, //enabled core count in socket
+ 0, //threads per socket
+ 0xEC, // processor characteristics
+ ProcessorFamilyARM, //ARM core
+ },
+ TYPE4_STRINGS
+};
+
+STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length
+ SMBIOS_HANDLE_A53_CLUSTER,
+ },
+ 1, //socket type
+ 3, //processor type CPU
+ ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2
+ 2, //manufactuer
+ {{0,},{0.}}, //processor id
+ 4, //version
+ {0,0,0,0,0,1}, //voltage
+ 0, //external clock
+ 650, //max speed
+ 650, //current speed
+ 0x41, //status
+ ProcessorUpgradeOther,
+ SMBIOS_HANDLE_A53_L1I, //l1 cache handle
+ SMBIOS_HANDLE_A53_L2, //l2 cache handle
+ 0xFFFF, //l3 cache handle
+ 0, //serial not set
+ 0, //asset not set
+ 6, //part number
+ 4, //core count in socket
+ 4, //enabled core count in socket
+ 0, //threads per socket
+ 0xEC, // processor characteristics
+ ProcessorFamilyARM, //ARM core
+ },
+ TYPE4_STRINGS
+};
+
+// Cache
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A57_L1I,
+ },
+ 1,
+ 0x380, //L1 enabled, unknown WB
+ 48, //48k i cache max
+ 48, //48k installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorParity, //parity checking
+ CacheTypeInstruction, //instruction cache
+ CacheAssociativityOther, //three way
+ },
+ TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A53_L1I,
+ },
+ 1,
+ 0x380, //L1 enabled, unknown WB
+ 32, //32k i cache max
+ 32, //32k installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorParity, //parity checking
+ CacheTypeInstruction, //instruction cache
+ CacheAssociativity2Way, //two way
+ },
+ TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A57_L1D,
+ },
+ 2,
+ 0x180, //L1 enabled, WB
+ 32, //32k d cache max
+ 32, //32k installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorSingleBit, //ECC checking
+ CacheTypeData, //instruction cache
+ CacheAssociativity2Way, //two way associative
+ },
+ TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A53_L1D,
+ },
+ 2,
+ 0x180, //L1 enabled, WB
+ 32, //32k d cache max
+ 32, //32k installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorSingleBit, //ECC checking
+ CacheTypeData, //instruction cache
+ CacheAssociativity4Way, //four way associative
+ },
+ TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A57_L2,
+ },
+ 3,
+ 0x181, //L2 enabled, WB
+ 2048, //2M d cache max
+ 2048, //2M installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorSingleBit, //ECC checking
+ CacheTypeUnified, //instruction cache
+ CacheAssociativity16Way, //16 way associative
+ },
+ TYPE7_STRINGS
+};
+
+STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length
+ SMBIOS_HANDLE_A53_L2,
+ },
+ 3,
+ 0x181, //L2 enabled, WB
+ 1024, //1M D cache max
+ 1024, //1M installed
+ {0,1}, //SRAM type
+ {0,1}, //SRAM type
+ 0, //unkown speed
+ CacheErrorSingleBit, //ECC checking
+ CacheTypeUnified, //instruction cache
+ CacheAssociativity16Way, //16 way associative
+ },
+ TYPE7_STRINGS
+};
+
+// Slots
+STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, //slot 0
+ SlotTypePciExpressGen2X4,
+ SlotDataBusWidth1X,
+ SlotUsageUnknown,
+ SlotLengthShort,
+ 0,
+ {1}, //unknown
+ {1,0,1}, //PME and SMBUS
+ 0,
+ 2,
+ 1,
+ },
+ TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, //slot 0
+ SlotTypePciExpressGen2X4,
+ SlotDataBusWidth1X,
+ SlotUsageUnknown,
+ SlotLengthShort,
+ 0,
+ {1},
+ {1,0,1}, //PME and SMBUS
+ 0,
+ 2,
+ 2,
+ },
+ TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, //slot 0
+ SlotTypePciExpressGen2X8,
+ SlotDataBusWidth4X,
+ SlotUsageUnknown,
+ SlotLengthShort,
+ 0,
+ {1},
+ {1,0,1}, //PME and SMBUS
+ 0,
+ 2,
+ 3,
+ },
+ TYPE9_STRINGS
+};
+
+STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1, //slot 0
+ SlotTypePciExpressGen2X16,
+ SlotDataBusWidth4X,
+ SlotUsageUnknown,
+ SlotLengthShort,
+ 0,
+ {1},
+ {1,0,1}, //PME and SMBUS
+ 0,
+ 2,
+ 0xc,
+ },
+ TYPE9_STRINGS
+};
+
+// Memory array
+STATIC CONST ARM_TYPE16 mArmDefaultType16 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
+ SMBIOS_HANDLE_MEMORY,
+ },
+ MemoryArrayLocationSystemBoard, //on motherboard
+ MemoryArrayUseSystemMemory, //system RAM
+ MemoryErrorCorrectionNone, //Juno doesn't have ECC RAM
+ 0x800000, //8GB
+ 0xFFFE, //No error information structure
+ 0x1, //soldered memory
+ },
+ TYPE16_STRINGS
+};
+
+// Memory device
+STATIC CONST ARM_TYPE17 mArmDefaultType17 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
+ SMBIOS_HANDLE_DIMM,
+ },
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+ 0xFFFE, //no errors
+ 64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+ 64, //data width of this device (64-bits)
+ 0x2000, //8GB
+ 0x0B, //row of chips
+ 0, //not part of a set
+ 1, //right side of board
+ 2, //bank 0
+// MemoryTypeLpddr3, //LP DDR3, isn't defined yet
+ MemoryTypeDdr3, //LP DDR3
+ {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered
+ 1600, //1600Mhz DDR
+ 0, //varies between diffrent production runs
+ 0, //serial
+ 0, //asset tag
+ 0, //part number
+ 0, //rank
+ },
+ TYPE17_STRINGS
+};
+
+// Memory array mapped address, this structure
+// is overridden by InstallMemoryStructure
+STATIC CONST ARM_TYPE19 mArmDefaultType19 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 0xFFFFFFFF, //invalid, look at extended addr field
+ 0xFFFFFFFF,
+ SMBIOS_HANDLE_DIMM, //handle
+ 1,
+ 0x080000000, //starting addr of first 2GB
+ 0x100000000, //ending addr of first 2GB
+ },
+ TYPE19_STRINGS
+};
+
+// System boot info
+STATIC CONST ARM_TYPE32 mArmDefaultType32 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ {0,0,0,0,0,0}, //reserved
+ BootInformationStatusNoError,
+ },
+ TYPE32_STRINGS
+};
+
+STATIC CONST VOID *DefaultCommonTables[]=
+{
+ &mArmDefaultType0,
+ &mArmDefaultType1,
+ &mArmDefaultType2,
+ &mArmDefaultType3,
+ &mArmDefaultType7_a53_l1i,
+ &mArmDefaultType7_a53_l1d,
+ &mArmDefaultType7_a53_l2,
+ &mArmDefaultType4_a53,
+ &mArmDefaultType9_0,
+ &mArmDefaultType9_1,
+ &mArmDefaultType9_2,
+ &mArmDefaultType9_3,
+ &mArmDefaultType16,
+ &mArmDefaultType17,
+// &mArmDefaultType19, //memory range type 19 dynamically generated
+ &mArmDefaultType32,
+ NULL
+};
+
+STATIC CONST VOID *DefaultTablesR0R1[]=
+{
+ &mArmDefaultType7_a57_l1i,
+ &mArmDefaultType7_a57_l1d,
+ &mArmDefaultType7_a57_l2,
+ &mArmDefaultType4_a57,
+ NULL
+};
+
+STATIC CONST VOID *DefaultTablesR2[]=
+{
+ &mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57
+ &mArmDefaultType7_a57_l1d,
+ &mArmDefaultType7_a57_l2,
+ &mArmDefaultType4_a72,
+ NULL
+};
+
+
+/**
+ Installs a memory descriptor (type19) for the given address range
+
+ @param Smbios SMBIOS protocol
+
+**/
+EFI_STATUS
+InstallMemoryStructure (
+ IN EFI_SMBIOS_PROTOCOL *Smbios,
+ IN UINT64 StartingAddress,
+ IN UINT64 RegionLength
+ )
+{
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ ARM_TYPE19 MemoryDescriptor;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19));
+
+ MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress;
+ MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength;
+ SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle;
+
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor
+ );
+ return Status;
+}
+
+/**
+ Install a whole table worth of structructures
+
+ @parm
+**/
+EFI_STATUS
+InstallStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios,
+ IN CONST VOID *DefaultTables[]
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+
+ int TableEntry;
+ for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++)
+ {
+ SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry]
+ );
+ if (EFI_ERROR(Status))
+ break;
+ }
+ return Status;
+}
+
+
+/**
+ Install all structures from the DefaultTables structure
+
+ @param Smbios SMBIOS protocol
+
+**/
+EFI_STATUS
+InstallAllStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 JunoRevision;
+ VOID *ExtraTables = DefaultTablesR0R1;
+
+ GetJunoRevision(JunoRevision);
+
+ // Fixup some table values
+ mArmDefaultType0.Base.SystemBiosMajorRelease = (PcdGet32 ( PcdFirmwareRevision ) >> 16) & 0xFF;
+ mArmDefaultType0.Base.SystemBiosMinorRelease = PcdGet32 ( PcdFirmwareRevision ) & 0xFF;
+ if ( JunoRevision == JUNO_REVISION_R1 )
+ {
+ mArmDefaultType2.Base.Version = 6;
+ }
+ else if ( JunoRevision == JUNO_REVISION_R2 )
+ {
+ mArmDefaultType2.Base.Version = 7;
+ ExtraTables=DefaultTablesR2;
+ }
+
+ //
+ // Add all Juno table entries
+ //
+ Status=InstallStructures (Smbios,DefaultCommonTables);
+ ASSERT_EFI_ERROR (Status);
+
+ Status=InstallStructures (Smbios,ExtraTables);
+ ASSERT_EFI_ERROR (Status);
+
+ // Generate memory descriptors for the two memory ranges we know about
+ Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize));
+ ASSERT_EFI_ERROR (Status);
+ Status = InstallMemoryStructure ( Smbios, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Installs SMBIOS information for ARM platforms
+
+ @param ImageHandle Module's image handle
+ @param SystemTable Pointer of EFI_SYSTEM_TABLE
+
+ @retval EFI_SUCCESS Smbios data successfully installed
+ @retval Other Smbios data was not installed
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosTablePublishEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ //
+ // Find the SMBIOS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID**)&Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = InstallAllStructures (Smbios);
+
+ return Status;
+}
diff --git a/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
new file mode 100644
index 0000000..457e1ff
--- /dev/null
+++ b/Platforms/ARM/Juno/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -0,0 +1,68 @@
+## @file
+# This driver installs SMBIOS information for ArmJuno
+#
+# Copyright (c) 2011, Bei Guan <gbtju85@...>
+# Copyright (c) 2011, Intel Corporation. All rights reserved.
+# Copyright (c) 2015, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SmbiosPlatformDxe
+ FILE_GUID = 4110465d-5ff3-4f4b-b580-24ed0d06747a
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = SmbiosTablePublishEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ SmbiosPlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gEfiGlobalVariableGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Guids]
+
+[Depex]
+ gEfiSmbiosProtocolGuid
--
2.5.5


Re: [Patch v3 00/40] MP Initialize Library

Laszlo Ersek
 

On 07/29/16 11:25, Laszlo Ersek wrote:
On 07/29/16 10:57, Fan, Jeff wrote:
Laszlo,

I sent one evaluate patch for you by adding back GDT table load in CpuDxe. Could you please help to verify if it could fix IA32 S3 issue?
Yes, I'll try to look into it shortly. I'll have to retest the other
cases as well.
Everything seems to work fine with your new patch added on top.

Thanks
Laszlo

Another solution is to remove hardcode from PiSmmCpuDxeSmm driver. But I do not prefer to do it this time. :-)

Thanks!
Jeff

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Laszlo Ersek
Sent: Thursday, July 28, 2016 11:21 PM
To: Fan, Jeff
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/28/16 15:55, Fan, Jeff wrote:
Laszlo,

Many thanks for your verification.

Your dump information and analysis result are very useful. I guess the issue happened at
UefiCpuPkg\PiSmmCpuDxeSmm\Ia32\MpFuncs.nasm:80 a32 jmp dword 0x20:0x0

The Proteted mode CS in current GDT table is not 0x20. But the PiSmmCpuDxeSmm hardcode it to 0x20.
Ah, good point; I recall:

commit 0d4c1db81aab86963536deb8253f35546c4398ea
Author: Michael Kinney <michael.d.kinney@...>
Date: Fri Oct 30 17:32:27 2015 +0000

UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim

as another related patch.

I will try it fix it tomorrow and feedback to you.
Thank you, I'll attempt to test it soon after.

Cheers
Laszlo

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Thursday, July 28, 2016 9:24 PM
To: Fan, Jeff; edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/25/16 04:52, Jeff Fan wrote:
We add MP Initialize Library defined in UefiCpuPkg/Include/Library/MpInitLib.h.
It will provide basic functionalities of MP services and could be
consumed by CPU MP PEI and CPU MP DXE to produce CPU MP PPI and CPU
MP Protocol. Then most of code could be shared between PEI and DXE modules.

PeiMpInitLib and DxeMpInitLib are added to make the CpuMpPei and
CpuDxe more simply.

I also updated the Ovmf Platform and Quark platform to consume MP
Initialize library. I have tested Ovmf platform and have not tested Quark yet.

v3:
1. Update Patch #2, #4 - #8, #28, #33, #36, #38 per Giri's comments to
a. Update SDM date to June, 2016
b. Mention BCD format in CPU_MICROCODE_DATE
c. Rename ProcessorChecksum to Checksum to match SDM.
d. Add whitespace after MpInitLibInitialize
e. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec.
f. Rename NumApsExecutingLoction to NumApsExecutingLocation
g. Add whitespace after ; in .nasm file
h. Rename *RellocateAp* to *RelocateAp*
2. Update Patch #16, #17, #29-#32 to
a. Use CamelCase for mStopCheckAllApsStatus and CheckAndUpdateApsStatus().
3. Update Patch #36 and #39 to
a. Add PeiMpInitLib instance in UefiCpuPkg.dsc
b. Add DxeMpInitLib instance in UefiCpuPkg.dsc
4. Update Patch #39 and #40 to
a. move the code of consuming MP Initialize library from patch #40 to
patch #39.
5. Update Patch #1, #3 - #8, #16 to
a. Add Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>

I fork the whole tree with the updated v3 patches at
https://github.com/vanjeff/edk2/tree/MpInitLibV3 for review.
I rebased your branch (originally at 09948b72fbb7) on top of current master (= 39dbc4d55347), and built it. It builds fine.

Scenarios that I tested, and seem to work:

* Q35, Ia32, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: FAIL (see details below)

* i440fx, X64, without -D SMM_REQUIRE, 8 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: pass

I re-verified the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86>, which requires CpuMpPei to actually *work* on both boot paths, and it works fine.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass

On the normal boot path, I also verified that the MTRR setup was consistent across the VCPUs (otherwise Linux would have complained), plus the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86> was working fine too. I also checked that the UEFI variable services worked, bound to the BSP, and then bound to the first AP as well. (Using the "taskset" Linux command, with "efibootmgr", to list the variables.) I quickly checked that Secure Boot was still recognized by the guest (Fedora) as enabled.

- S3 resume: pass

Repeated the BZ#86 check and the variable access checks from within the resumed guest, all pass.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Windows 8.1 guest:
- normal boot path: pass

On the normal boot path, I checked Secure Boot enablement with PowerShell.

- S3 resume: pass.

Now, about the one failure case. QEMU logs the following:

KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
extra data[0]: 80000b0d
extra data[0]: 80000b0d
extra data[1]: 31
extra data[1]: 31
extra data[0]: 80000b0d
extra data[1]: 31

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0 <66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66 8e
e8 66 8e d0 89 d6
I didn't try to analyze this in depth, but from the hex-encoded instruction stream, it looks like KVM dislikes the 0x66 prefix in front of a JMP instruction (EA, if I recall correctly). Given that this is logged all at once for three processors (out of 4 -- see the description of that test case above), I believe one of the far jumps in the AP mode switching code is incorrect, on the S3 resume path, for Ia32 + SMM.

Perhaps one of the "a32" or "o32" NASM prefixes should be tweaked. Similar examples: <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13258.html>, <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13259.html>.

Thanks!
Laszlo
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edk2-devel mailing list
edk2-devel@...
https://lists.01.org/mailman/listinfo/edk2-devel


Re: [Patch v3 00/40] MP Initialize Library

Fan, Jeff <jeff.fan@...>
 

Laszlo,

Thanks again for your verification on OVMF.

Jeff

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Laszlo Ersek
Sent: Friday, July 29, 2016 6:23 PM
To: Fan, Jeff
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/29/16 11:25, Laszlo Ersek wrote:
On 07/29/16 10:57, Fan, Jeff wrote:
Laszlo,

I sent one evaluate patch for you by adding back GDT table load in CpuDxe. Could you please help to verify if it could fix IA32 S3 issue?
Yes, I'll try to look into it shortly. I'll have to retest the other
cases as well.
Everything seems to work fine with your new patch added on top.

Thanks
Laszlo

Another solution is to remove hardcode from PiSmmCpuDxeSmm driver.
But I do not prefer to do it this time. :-)

Thanks!
Jeff

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf
Of Laszlo Ersek
Sent: Thursday, July 28, 2016 11:21 PM
To: Fan, Jeff
Cc: edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/28/16 15:55, Fan, Jeff wrote:
Laszlo,

Many thanks for your verification.

Your dump information and analysis result are very useful. I guess the issue happened at
UefiCpuPkg\PiSmmCpuDxeSmm\Ia32\MpFuncs.nasm:80 a32 jmp dword 0x20:0x0

The Proteted mode CS in current GDT table is not 0x20. But the PiSmmCpuDxeSmm hardcode it to 0x20.
Ah, good point; I recall:

commit 0d4c1db81aab86963536deb8253f35546c4398ea
Author: Michael Kinney <michael.d.kinney@...>
Date: Fri Oct 30 17:32:27 2015 +0000

UefiCpuPkg: CpuDxe: Update GDT to be consistent with DxeIplPeim

as another related patch.

I will try it fix it tomorrow and feedback to you.
Thank you, I'll attempt to test it soon after.

Cheers
Laszlo

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Thursday, July 28, 2016 9:24 PM
To: Fan, Jeff; edk2-devel@...
Subject: Re: [edk2] [Patch v3 00/40] MP Initialize Library

On 07/25/16 04:52, Jeff Fan wrote:
We add MP Initialize Library defined in UefiCpuPkg/Include/Library/MpInitLib.h.
It will provide basic functionalities of MP services and could be
consumed by CPU MP PEI and CPU MP DXE to produce CPU MP PPI and CPU
MP Protocol. Then most of code could be shared between PEI and DXE modules.

PeiMpInitLib and DxeMpInitLib are added to make the CpuMpPei and
CpuDxe more simply.

I also updated the Ovmf Platform and Quark platform to consume MP
Initialize library. I have tested Ovmf platform and have not tested Quark yet.

v3:
1. Update Patch #2, #4 - #8, #28, #33, #36, #38 per Giri's comments to
a. Update SDM date to June, 2016
b. Mention BCD format in CPU_MICROCODE_DATE
c. Rename ProcessorChecksum to Checksum to match SDM.
d. Add whitespace after MpInitLibInitialize
e. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec.
f. Rename NumApsExecutingLoction to NumApsExecutingLocation
g. Add whitespace after ; in .nasm file
h. Rename *RellocateAp* to *RelocateAp*
2. Update Patch #16, #17, #29-#32 to
a. Use CamelCase for mStopCheckAllApsStatus and CheckAndUpdateApsStatus().
3. Update Patch #36 and #39 to
a. Add PeiMpInitLib instance in UefiCpuPkg.dsc
b. Add DxeMpInitLib instance in UefiCpuPkg.dsc
4. Update Patch #39 and #40 to
a. move the code of consuming MP Initialize library from patch #40 to
patch #39.
5. Update Patch #1, #3 - #8, #16 to
a. Add Reviewed-by: Giri P Mudusuru
<giri.p.mudusuru@...>

I fork the whole tree with the updated v3 patches at
https://github.com/vanjeff/edk2/tree/MpInitLibV3 for review.
I rebased your branch (originally at 09948b72fbb7) on top of current master (= 39dbc4d55347), and built it. It builds fine.

Scenarios that I tested, and seem to work:

* Q35, Ia32, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: FAIL (see details below)

* i440fx, X64, without -D SMM_REQUIRE, 8 VCPUs, Fedora guest:
- normal boot path: pass
- S3 resume: pass

I re-verified the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86>, which requires CpuMpPei to actually *work* on both boot paths, and it works fine.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Fedora guest:
- normal boot path: pass

On the normal boot path, I also verified that the MTRR setup was consistent across the VCPUs (otherwise Linux would have complained), plus the fix for <https://tianocore.acgmultimedia.com/show_bug.cgi?id=86> was working fine too. I also checked that the UEFI variable services worked, bound to the BSP, and then bound to the first AP as well. (Using the "taskset" Linux command, with "efibootmgr", to list the variables.) I quickly checked that Secure Boot was still recognized by the guest (Fedora) as enabled.

- S3 resume: pass

Repeated the BZ#86 check and the variable access checks from within the resumed guest, all pass.

* Q35, Ia32X64, with -D SMM_REQUIRE, 4 VCPUs, Windows 8.1 guest:
- normal boot path: pass

On the normal boot path, I checked Secure Boot enablement with PowerShell.

- S3 resume: pass.

Now, about the one failure case. QEMU logs the following:

KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
KVM internal error. Suberror: 3
extra data[0]: 80000b0d
extra data[0]: 80000b0d
extra data[1]: 31
extra data[1]: 31
extra data[0]: 80000b0d
extra data[1]: 31

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16
[-WA] FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0
<66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66
8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16
[-WA] FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0
<66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66
8e
e8 66 8e d0 89 d6

EAX=60000011 EBX=00000000 ECX=00000000 EDX=0009f000
ESI=000000b5 EDI=00000000 EBP=00000000 ESP=00000000
EIP=00000032 EFL=00010006 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES
=9f00 0009f000 0000ffff 00009300 DPL=0 DS16 [-WA] CS =9f00 0009f000
0000ffff 00009b00 DPL=0 CS16 [-RA] SS =9f00 0009f000 0000ffff
00009300
DPL=0 DS16 [-WA] DS =0000 00000000 0000ffff 00009300 DPL=0 DS16
[-WA] FS =0000 00000000 0000ffff 00009300 DPL=0 DS16 [-WA] GS =0000
00000000 0000ffff 00009300 DPL=0 DS16 [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT TR =0000 00000000
0000ffff 00008b00 DPL=0 TSS32-busy
GDT= 7f2d8000 00000017
IDT= 7f2d8018 000007ff
CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000
DR6=ffff0ff0 DR7=00000400
EFER=0000000000000000
Code=00 2e 66 0f 01 1c 31 c0 8e d8 0f 20 c0 66 83 c8 01 0f 22 c0
<66>
67 ea 3b f0 09 00 20 00 66 b8 08 00 66 8e d8 66 8e c0 66 8e e0 66
8e
e8 66 8e d0 89 d6
I didn't try to analyze this in depth, but from the hex-encoded instruction stream, it looks like KVM dislikes the 0x66 prefix in front of a JMP instruction (EA, if I recall correctly). Given that this is logged all at once for three processors (out of 4 -- see the description of that test case above), I believe one of the far jumps in the AP mode switching code is incorrect, on the S3 resume path, for Ia32 + SMM.

Perhaps one of the "a32" or "o32" NASM prefixes should be tweaked. Similar examples: <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13258.html>, <https://www.mail-archive.com/edk2-devel@lists.01.org/msg13259.html>.

Thanks!
Laszlo
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Re: [PATCH v4 0/7] BaseTools: add support for GCC5 in LTO mode

Liming Gao
 

Ard:
My gcc version 5.3.0 20151204 (Ubuntu 5.3.0-3ubuntu1~14.04). I will try GCC54.

Besides, for new GCC5 tool chain, could you add one brief introduction in tools_def.txt like GCC49? And, highlight it enable LTO by default.

# GCC49 -Linux,Windows- Requires:
# GCC 4.9 targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
# Optional:
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads


Thanks
Liming
From: Ard Biesheuvel [mailto:ard.biesheuvel@...]
Sent: Friday, July 29, 2016 2:41 PM
To: Gao, Liming <liming.gao@...>
Cc: edk2-devel@...; lersek@...; Shi, Steven <steven.shi@...>; Zhu, Yonghong <yonghong.zhu@...>; Justen, Jordan L <jordan.l.justen@...>; leif.lindholm@...
Subject: Re: [PATCH v4 0/7] BaseTools: add support for GCC5 in LTO mode

On 29 July 2016 at 08:09, Ard Biesheuvel wrote:
On 29 July 2016 at 06:47, Gao, Liming wrote:
Ard:
Thanks for your update. I have some comments for them.
1) It uses GCC as Link for GCC44-GCC49. Have you done verification on them? I verify GCC49 in OVMFIa32X64 platform. It works.
Yes, I tested all of them.

2) After this change, how to append new link option in platform DSC? Use style -Wl, ?
It depends. Some options (like -z) don't need it, but others do.

3) I see GCC5 uses gcc-ar as its SLINK, and GCC49 uses ar as its SLINK. Is gcc-ar required only by LTO?
Yes

4) Before GCC49 optimization, GCC49 means GCC49 or later, GCC5 can work with GCC49 tool chain configuration. But now, I configure gcc to point to GCC5, and build OVMF with GCC49 tool chain, it reports GenFw failure. I expect GCC5 work with GCC49 and GCC5 tool chain both. GCC49 for no lto, GCC5 for lto. I know Steven has provided the patch to fix this GenFw issue.

GenFw: ERROR 3000: Invalid
/home/hwu/work/lgao4/AllPkg/Build/Ovmf3264/DEBUG_GCC49/X64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/DxeCore.dll unsupported ELF EM_X86_64 relocation 0x9.
GenFw: ERROR 3000: Invalid
/home/hwu/work/lgao4/AllPkg/Build/Ovmf3264/DEBUG_GCC49/X64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/DxeCore.dll unsupported ELF EM_X86_64 relocation 0x9.
GenFw: ERROR 3000: Invalid
Which GCC version are you using?
I cannot reproduce this with gcc version 5.4.0 20160609 (Ubuntu
5.4.0-6ubuntu1~16.04.1)

In any case, I think we should merge Steven's patch that adds handling
to the relocation types to GenFw. The issue is only that having a GOT
does not make a lot of sense for UEFI executables, since it forces a
symbol reference to be absolute, which uses more space in the code,
but also in the .reloc section. The visibility pragma I introduced for
GCC4x was intended to prevent GOT based relocations from being
emitted.


[RFC 0/2] Add EBC support for AArch64

Leif Lindholm <leif.lindholm@...>
 

Import the AArch64 EBC implementation from
https://source.codeaurora.org/external/server/edk2-blue/
1/2 does not contain a "Contributed-under:" due to my interpretation
of section 4 of the Tianocore Contribution license.

Tested with MdeModulePkg/Application/HelloWorld built for EBC.
Would appreciate some reviewing and testing.

Jeff Brasen (1):
MdeModulePkg/EbcDxe: Add AARCH64 EBC VM support

Leif Lindholm (1):
ArmVirtPkg: enable EBC interpreter for AArch64 QEMU

ArmVirtPkg/ArmVirtQemu.dsc | 1 +
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 5 +
.../Universal/EbcDxe/AArch64/EbcLowLevel.S | 135 +++++
MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c | 563 +++++++++++++++++++++
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf | 6 +-
5 files changed, 709 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Universal/EbcDxe/AArch64/EbcLowLevel.S
create mode 100644 MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c

--
2.1.4


[RFC 1/2] MdeModulePkg/EbcDxe: Add AARCH64 EBC VM support

Leif Lindholm <leif.lindholm@...>
 

From: Jeff Brasen <jbrasen@...>

Adds support for the EBC VM for AARCH64 platforms

Submitted on behalf of a third-party: The Linux Foundation
This contribution is licensed under the BSD license as found at
http://opensource.org/licenses/bsd-license.php

[Taken from https://source.codeaurora.org/external/server/edk2-blue/]
Signed-off-by: Leif Lindholm <leif.lindholm@...>
---
.../Universal/EbcDxe/AArch64/EbcLowLevel.S | 135 +++++
MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c | 563 +++++++++++++++++++++
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf | 6 +-
3 files changed, 703 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Universal/EbcDxe/AArch64/EbcLowLevel.S
create mode 100644 MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c

diff --git a/MdeModulePkg/Universal/EbcDxe/AArch64/EbcLowLevel.S b/MdeModulePkg/Universal/EbcDxe/AArch64/EbcLowLevel.S
new file mode 100644
index 0000000..e858227
--- /dev/null
+++ b/MdeModulePkg/Universal/EbcDxe/AArch64/EbcLowLevel.S
@@ -0,0 +1,135 @@
+#/** @file
+#
+# This code provides low level routines that support the Virtual Machine
+# for option ROMs.
+#
+# Copyright (c) 2015, The Linux Foundation. All rights reserved.
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#---------------------------------------------------------------------------
+# Equate files needed.
+#---------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(CopyMem);
+ASM_GLOBAL ASM_PFX(EbcInterpret);
+ASM_GLOBAL ASM_PFX(ExecuteEbcImageEntryPoint);
+
+#****************************************************************************
+# EbcLLCALLEX
+#
+# This function is called to execute an EBC CALLEX instruction.
+# This instruction requires that we thunk out to external native
+# code. For AArch64, we copy the VM stack into the main stack and then pop
+# the first 8 arguments off according to the AArch64 Procedure Call Standard
+# On return, we restore the stack pointer to its original location.
+#
+#****************************************************************************
+# UINTN EbcLLCALLEXNative(UINTN FuncAddr, UINTN NewStackPointer, VOID *FramePtr)
+ASM_GLOBAL ASM_PFX(EbcLLCALLEXNative);
+ASM_PFX(EbcLLCALLEXNative):
+ stp x19, x20, [sp, #-16]!
+ stp x29, x30, [sp, #-16]!
+
+ mov x19, x0
+ mov x20, sp
+ sub x2, x2, x1 // Length = NewStackPointer-FramePtr
+ sub sp, sp, x2
+ sub sp, sp, #64 // Make sure there is room for at least 8 args in the new stack
+ mov x0, sp
+
+ bl CopyMem // Sp, NewStackPointer, Length
+
+ ldp x0, x1, [sp], #16
+ ldp x2, x3, [sp], #16
+ ldp x4, x5, [sp], #16
+ ldp x6, x7, [sp], #16
+
+ blr x19
+
+ mov sp, x20
+ ldp x29, x30, [sp], #16
+ ldp x19, x20, [sp], #16
+
+ ret
+
+#****************************************************************************
+# EbcLLEbcInterpret
+#
+# This function is called by the thunk code to handle an Native to EBC call
+# This can handle up to 16 arguments (1-8 on in x0-x7, 9-16 are on the stack)
+# x9 contains the Entry point that will be the first argument when
+# EBCInterpret is called.
+#
+#****************************************************************************
+ASM_GLOBAL ASM_PFX(EbcLLEbcInterpret);
+ASM_PFX(EbcLLEbcInterpret):
+ stp x29, x30, [sp, #-16]!
+
+ // copy the current arguments 9-16 from old location and add arg 7 to stack
+ // keeping 16 byte stack alignment
+ sub sp, sp, #80
+ str x7, [sp]
+ ldr x11, [sp, #96]
+ str x11, [sp, #8]
+ ldr x11, [sp, #104]
+ str x11, [sp, #16]
+ ldr x11, [sp, #112]
+ str x11, [sp, #24]
+ ldr x11, [sp, #120]
+ str x11, [sp, #32]
+ ldr x11, [sp, #128]
+ str x11, [sp, #40]
+ ldr x11, [sp, #136]
+ str x11, [sp, #48]
+ ldr x11, [sp, #144]
+ str x11, [sp, #56]
+ ldr x11, [sp, #152]
+ str x11, [sp, #64]
+
+ // Shift arguments and add entry point and as argument 1
+ mov x7, x6
+ mov x6, x5
+ mov x5, x4
+ mov x4, x3
+ mov x3, x2
+ mov x2, x1
+ mov x1, x0
+ mov x0, x9
+
+ # call C-code
+ bl ASM_PFX(EbcInterpret)
+ add sp, sp, #80
+
+ ldp x29, x30, [sp], #16
+
+ ret
+
+#****************************************************************************
+# EbcLLExecuteEbcImageEntryPoint
+#
+# This function is called by the thunk code to handle the image entry point
+# x9 contains the Entry point that will be the first argument when
+# ExecuteEbcImageEntryPoint is called.
+#
+#****************************************************************************
+ASM_GLOBAL ASM_PFX(EbcLLExecuteEbcImageEntryPoint);
+ASM_PFX(EbcLLExecuteEbcImageEntryPoint):
+ stp x29, x30, [sp, #-16]!
+ # build new paramater calling convention
+ mov x2, x1
+ mov x1, x0
+ mov x0, x9
+
+ # call C-code
+ bl ASM_PFX(ExecuteEbcImageEntryPoint)
+ ldp x29, x30, [sp], #16
+ ret
diff --git a/MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c b/MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c
new file mode 100644
index 0000000..23261a0
--- /dev/null
+++ b/MdeModulePkg/Universal/EbcDxe/AArch64/EbcSupport.c
@@ -0,0 +1,563 @@
+/** @file
+ This module contains EBC support routines that are customized based on
+ the target AArch64 processor.
+
+Copyright (c) 2015, The Linux Foundation. All rights reserved.
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "EbcInt.h"
+#include "EbcExecute.h"
+
+//
+// Amount of space that is not used in the stack
+//
+#define STACK_REMAIN_SIZE (1024 * 4)
+
+//
+// This is instruction buffer used to create EBC thunk
+//
+#define EBC_MAGIC_SIGNATURE 0xCA112EBCCA112EBCull
+#define EBC_ENTRYPOINT_SIGNATURE 0xAFAFAFAFAFAFAFAFull
+#define EBC_LL_EBC_ENTRYPOINT_SIGNATURE 0xFAFAFAFAFAFAFAFAull
+UINT8 mInstructionBufferTemplate[] = {
+ 0x03, 0x00, 0x00, 0x14, //b pc+16
+ //
+ // Add a magic code here to help the VM recognize the thunk..
+ //
+ (UINT8)(EBC_MAGIC_SIGNATURE & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 8) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 16) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 24) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 32) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 40) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 48) & 0xFF),
+ (UINT8)((EBC_MAGIC_SIGNATURE >> 56) & 0xFF),
+ 0x69, 0x00, 0x00, 0x58, //ldr x9, #32
+ 0x8A, 0x00, 0x00, 0x58, //ldr x10, #40
+ 0x05, 0x00, 0x00, 0x14, //b pc+32
+ (UINT8)(EBC_ENTRYPOINT_SIGNATURE & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 8) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 16) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 24) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 32) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 40) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 48) & 0xFF),
+ (UINT8)((EBC_ENTRYPOINT_SIGNATURE >> 56) & 0xFF),
+ (UINT8)(EBC_LL_EBC_ENTRYPOINT_SIGNATURE & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 8) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 16) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 24) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 32) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 40) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 48) & 0xFF),
+ (UINT8)((EBC_LL_EBC_ENTRYPOINT_SIGNATURE >> 56) & 0xFF),
+ 0x40, 0x01, 0x1F, 0xD6 //br x10
+
+};
+
+/**
+ Begin executing an EBC image.
+ This is used for Ebc Thunk call.
+
+ @return The value returned by the EBC application we're going to run.
+
+**/
+UINT64
+EFIAPI
+EbcLLEbcInterpret (
+ VOID
+ );
+
+/**
+ Begin executing an EBC image.
+ This is used for Ebc image entrypoint.
+
+ @return The value returned by the EBC application we're going to run.
+
+**/
+UINT64
+EFIAPI
+EbcLLExecuteEbcImageEntryPoint (
+ VOID
+ );
+
+/**
+ Pushes a 64 bit unsigned value to the VM stack.
+
+ @param VmPtr The pointer to current VM context.
+ @param Arg The value to be pushed.
+
+**/
+VOID
+PushU64 (
+ IN VM_CONTEXT *VmPtr,
+ IN UINT64 Arg
+ )
+{
+ //
+ // Advance the VM stack down, and then copy the argument to the stack.
+ // Hope it's aligned.
+ //
+ VmPtr->Gpr[0] -= sizeof (UINT64);
+ *(UINT64 *) VmPtr->Gpr[0] = Arg;
+ return;
+}
+
+
+/**
+ Begin executing an EBC image.
+
+ This is a thunk function.
+
+ @param EntryPoint The entrypoint of EBC code.
+ @param Arg1 The 1st argument.
+ @param Arg2 The 2nd argument.
+ @param Arg3 The 3rd argument.
+ @param Arg4 The 4th argument.
+ @param Arg5 The 5th argument.
+ @param Arg6 The 6th argument.
+ @param Arg7 The 7th argument.
+ @param Arg8 The 8th argument.
+ @param Arg9 The 9th argument.
+ @param Arg10 The 10th argument.
+ @param Arg11 The 11th argument.
+ @param Arg12 The 12th argument.
+ @param Arg13 The 13th argument.
+ @param Arg14 The 14th argument.
+ @param Arg15 The 15th argument.
+ @param Arg16 The 16th argument.
+
+ @return The value returned by the EBC application we're going to run.
+
+**/
+UINT64
+EFIAPI
+EbcInterpret (
+ IN UINTN EntryPoint,
+ IN UINTN Arg1,
+ IN UINTN Arg2,
+ IN UINTN Arg3,
+ IN UINTN Arg4,
+ IN UINTN Arg5,
+ IN UINTN Arg6,
+ IN UINTN Arg7,
+ IN UINTN Arg8,
+ IN UINTN Arg9,
+ IN UINTN Arg10,
+ IN UINTN Arg11,
+ IN UINTN Arg12,
+ IN UINTN Arg13,
+ IN UINTN Arg14,
+ IN UINTN Arg15,
+ IN UINTN Arg16
+ )
+{
+ //
+ // Create a new VM context on the stack
+ //
+ VM_CONTEXT VmContext;
+ UINTN Addr;
+ EFI_STATUS Status;
+ UINTN StackIndex;
+
+ //
+ // Get the EBC entry point
+ //
+ Addr = EntryPoint;
+
+ //
+ // Now clear out our context
+ //
+ ZeroMem ((VOID *) &VmContext, sizeof (VM_CONTEXT));
+
+ //
+ // Set the VM instruction pointer to the correct location in memory.
+ //
+ VmContext.Ip = (VMIP) Addr;
+
+ //
+ // Initialize the stack pointer for the EBC. Get the current system stack
+ // pointer and adjust it down by the max needed for the interpreter.
+ //
+
+ //
+ // Adjust the VM's stack pointer down.
+ //
+
+ Status = GetEBCStack((EFI_HANDLE)(UINTN)-1, &VmContext.StackPool, &StackIndex);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];
+ VmContext.Gpr[0] -= sizeof (UINTN);
+
+ //
+ // Align the stack on a natural boundary.
+ //
+ VmContext.Gpr[0] &= ~(VM_REGISTER)(sizeof (UINTN) - 1);
+
+ //
+ // Put a magic value in the stack gap, then adjust down again.
+ //
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];
+
+ //
+ // The stack upper to LowStackTop is belong to the VM.
+ //
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];
+
+ //
+ // For the worst case, assume there are 4 arguments passed in registers, store
+ // them to VM's stack.
+ //
+ PushU64 (&VmContext, (UINT64) Arg16);
+ PushU64 (&VmContext, (UINT64) Arg15);
+ PushU64 (&VmContext, (UINT64) Arg14);
+ PushU64 (&VmContext, (UINT64) Arg13);
+ PushU64 (&VmContext, (UINT64) Arg12);
+ PushU64 (&VmContext, (UINT64) Arg11);
+ PushU64 (&VmContext, (UINT64) Arg10);
+ PushU64 (&VmContext, (UINT64) Arg9);
+ PushU64 (&VmContext, (UINT64) Arg8);
+ PushU64 (&VmContext, (UINT64) Arg7);
+ PushU64 (&VmContext, (UINT64) Arg6);
+ PushU64 (&VmContext, (UINT64) Arg5);
+ PushU64 (&VmContext, (UINT64) Arg4);
+ PushU64 (&VmContext, (UINT64) Arg3);
+ PushU64 (&VmContext, (UINT64) Arg2);
+ PushU64 (&VmContext, (UINT64) Arg1);
+
+ //
+ // Interpreter assumes 64-bit return address is pushed on the stack.
+ // AArch64 does not do this so pad the stack accordingly.
+ //
+ PushU64 (&VmContext, (UINT64) 0);
+ PushU64 (&VmContext, (UINT64) 0x1234567887654321ULL);
+
+ //
+ // For AArch64, this is where we say our return address is
+ //
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];
+
+ //
+ // We need to keep track of where the EBC stack starts. This way, if the EBC
+ // accesses any stack variables above its initial stack setting, then we know
+ // it's accessing variables passed into it, which means the data is on the
+ // VM's stack.
+ // When we're called, on the stack (high to low) we have the parameters, the
+ // return address, then the saved ebp. Save the pointer to the return address.
+ // EBC code knows that's there, so should look above it for function parameters.
+ // The offset is the size of locals (VMContext + Addr + saved ebp).
+ // Note that the interpreter assumes there is a 16 bytes of return address on
+ // the stack too, so adjust accordingly.
+ // VmContext.HighStackBottom = (UINTN)(Addr + sizeof (VmContext) + sizeof (Addr));
+ //
+
+ //
+ // Begin executing the EBC code
+ //
+ EbcExecute (&VmContext);
+
+ //
+ // Return the value in R[7] unless there was an error
+ //
+ ReturnEBCStack(StackIndex);
+ return (UINT64) VmContext.Gpr[7];
+}
+
+
+/**
+ Begin executing an EBC image.
+
+ @param EntryPoint The entrypoint of EBC code.
+ @param ImageHandle image handle for the EBC application we're executing
+ @param SystemTable standard system table passed into an driver's entry
+ point
+
+ @return The value returned by the EBC application we're going to run.
+
+**/
+UINT64
+EFIAPI
+ExecuteEbcImageEntryPoint (
+ IN UINTN EntryPoint,
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Create a new VM context on the stack
+ //
+ VM_CONTEXT VmContext;
+ UINTN Addr;
+ EFI_STATUS Status;
+ UINTN StackIndex;
+
+ //
+ // Get the EBC entry point
+ //
+ Addr = EntryPoint;
+
+ //
+ // Now clear out our context
+ //
+ ZeroMem ((VOID *) &VmContext, sizeof (VM_CONTEXT));
+
+ //
+ // Save the image handle so we can track the thunks created for this image
+ //
+ VmContext.ImageHandle = ImageHandle;
+ VmContext.SystemTable = SystemTable;
+
+ //
+ // Set the VM instruction pointer to the correct location in memory.
+ //
+ VmContext.Ip = (VMIP) Addr;
+
+ //
+ // Initialize the stack pointer for the EBC. Get the current system stack
+ // pointer and adjust it down by the max needed for the interpreter.
+ //
+
+ Status = GetEBCStack(ImageHandle, &VmContext.StackPool, &StackIndex);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ VmContext.StackTop = (UINT8*)VmContext.StackPool + (STACK_REMAIN_SIZE);
+ VmContext.Gpr[0] = (UINT64) ((UINT8*)VmContext.StackPool + STACK_POOL_SIZE);
+ VmContext.HighStackBottom = (UINTN) VmContext.Gpr[0];
+ VmContext.Gpr[0] -= sizeof (UINTN);
+
+
+ //
+ // Put a magic value in the stack gap, then adjust down again
+ //
+ *(UINTN *) (UINTN) (VmContext.Gpr[0]) = (UINTN) VM_STACK_KEY_VALUE;
+ VmContext.StackMagicPtr = (UINTN *) (UINTN) VmContext.Gpr[0];
+
+ //
+ // Align the stack on a natural boundary
+ VmContext.Gpr[0] &= ~(VM_REGISTER)(sizeof(UINTN) - 1);
+ //
+ VmContext.LowStackTop = (UINTN) VmContext.Gpr[0];
+
+ //
+ // Simply copy the image handle and system table onto the EBC stack.
+ // Greatly simplifies things by not having to spill the args.
+ //
+ PushU64 (&VmContext, (UINT64) SystemTable);
+ PushU64 (&VmContext, (UINT64) ImageHandle);
+
+ //
+ // VM pushes 16-bytes for return address. Simulate that here.
+ //
+ PushU64 (&VmContext, (UINT64) 0);
+ PushU64 (&VmContext, (UINT64) 0x1234567887654321ULL);
+
+ //
+ // For AArch64, this is where we say our return address is
+ //
+ VmContext.StackRetAddr = (UINT64) VmContext.Gpr[0];
+
+ //
+ // Entry function needn't access high stack context, simply
+ // put the stack pointer here.
+ //
+
+ //
+ // Begin executing the EBC code
+ //
+ EbcExecute (&VmContext);
+
+ //
+ // Return the value in R[7] unless there was an error
+ //
+ ReturnEBCStack(StackIndex);
+ return (UINT64) VmContext.Gpr[7];
+}
+
+
+/**
+ Create thunks for an EBC image entry point, or an EBC protocol service.
+
+ @param ImageHandle Image handle for the EBC image. If not null, then
+ we're creating a thunk for an image entry point.
+ @param EbcEntryPoint Address of the EBC code that the thunk is to call
+ @param Thunk Returned thunk we create here
+ @param Flags Flags indicating options for creating the thunk
+
+ @retval EFI_SUCCESS The thunk was created successfully.
+ @retval EFI_INVALID_PARAMETER The parameter of EbcEntryPoint is not 16-bit
+ aligned.
+ @retval EFI_OUT_OF_RESOURCES There is not enough memory to created the EBC
+ Thunk.
+ @retval EFI_BUFFER_TOO_SMALL EBC_THUNK_SIZE is not larger enough.
+
+**/
+EFI_STATUS
+EbcCreateThunks (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *EbcEntryPoint,
+ OUT VOID **Thunk,
+ IN UINT32 Flags
+ )
+{
+ UINT8 *Ptr;
+ UINT8 *ThunkBase;
+ UINT32 Index;
+ INT32 ThunkSize;
+
+ //
+ // Check alignment of pointer to EBC code
+ //
+ if ((UINT32) (UINTN) EbcEntryPoint & 0x01) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ThunkSize = sizeof(mInstructionBufferTemplate);
+
+ Ptr = AllocatePool (sizeof(mInstructionBufferTemplate));
+
+ if (Ptr == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ //
+ // Print(L"Allocate TH: 0x%X\n", (UINT32)Ptr);
+ //
+ // Save the start address so we can add a pointer to it to a list later.
+ //
+ ThunkBase = Ptr;
+
+ //
+ // Give them the address of our buffer we're going to fix up
+ //
+ *Thunk = (VOID *) Ptr;
+
+ //
+ // Copy whole thunk instruction buffer template
+ //
+ CopyMem (Ptr, mInstructionBufferTemplate, sizeof(mInstructionBufferTemplate));
+
+ //
+ // Patch EbcEntryPoint and EbcLLEbcInterpret
+ //
+ for (Index = 0; Index < sizeof(mInstructionBufferTemplate) - sizeof(UINTN); Index++) {
+ if (*(UINTN *)&Ptr[Index] == EBC_ENTRYPOINT_SIGNATURE) {
+ *(UINTN *)&Ptr[Index] = (UINTN)EbcEntryPoint;
+ }
+ if (*(UINTN *)&Ptr[Index] == EBC_LL_EBC_ENTRYPOINT_SIGNATURE) {
+ if ((Flags & FLAG_THUNK_ENTRY_POINT) != 0) {
+ *(UINTN *)&Ptr[Index] = (UINTN)EbcLLExecuteEbcImageEntryPoint;
+ } else {
+ *(UINTN *)&Ptr[Index] = (UINTN)EbcLLEbcInterpret;
+ }
+ }
+ }
+
+ //
+ // Add the thunk to the list for this image. Do this last since the add
+ // function flushes the cache for us.
+ //
+ EbcAddImageThunk (ImageHandle, (VOID *) ThunkBase, ThunkSize);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function is called to execute an EBC CALLEX instruction.
+ The function check the callee's content to see whether it is common native
+ code or a thunk to another piece of EBC code.
+ If the callee is common native code, use EbcLLCAllEXASM to manipulate,
+ otherwise, set the VM->IP to target EBC code directly to avoid another VM
+ be startup which cost time and stack space.
+
+ @param VmPtr Pointer to a VM context.
+ @param FuncAddr Callee's address
+ @param NewStackPointer New stack pointer after the call
+ @param FramePtr New frame pointer after the call
+ @param Size The size of call instruction
+
+**/
+VOID
+EbcLLCALLEX (
+ IN VM_CONTEXT *VmPtr,
+ IN UINTN FuncAddr,
+ IN UINTN NewStackPointer,
+ IN VOID *FramePtr,
+ IN UINT8 Size
+ )
+{
+ UINTN IsThunk;
+ UINTN TargetEbcAddr;
+ UINT8 InstructionBuffer[sizeof(mInstructionBufferTemplate)];
+ UINTN Index;
+ UINTN IndexOfEbcEntrypoint;
+
+ IsThunk = 1;
+ TargetEbcAddr = 0;
+ IndexOfEbcEntrypoint = 0;
+
+ //
+ // Processor specific code to check whether the callee is a thunk to EBC.
+ //
+ CopyMem (InstructionBuffer, (VOID *)FuncAddr, sizeof(InstructionBuffer));
+ //
+ // Fill the signature according to mInstructionBufferTemplate
+ //
+ for (Index = 0; Index < sizeof(mInstructionBufferTemplate) - sizeof(UINTN); Index++) {
+ if (*(UINTN *)&mInstructionBufferTemplate[Index] == EBC_ENTRYPOINT_SIGNATURE) {
+ *(UINTN *)&InstructionBuffer[Index] = EBC_ENTRYPOINT_SIGNATURE;
+ IndexOfEbcEntrypoint = Index;
+ }
+ if (*(UINTN *)&mInstructionBufferTemplate[Index] == EBC_LL_EBC_ENTRYPOINT_SIGNATURE) {
+ *(UINTN *)&InstructionBuffer[Index] = EBC_LL_EBC_ENTRYPOINT_SIGNATURE;
+ }
+ }
+ //
+ // Check if we need thunk to native
+ //
+ if (CompareMem (InstructionBuffer, mInstructionBufferTemplate, sizeof(mInstructionBufferTemplate)) != 0) {
+ IsThunk = 0;
+ }
+
+ if (IsThunk == 1){
+ //
+ // The callee is a thunk to EBC, adjust the stack pointer down 16 bytes and
+ // put our return address and frame pointer on the VM stack.
+ // Then set the VM's IP to new EBC code.
+ //
+ VmPtr->Gpr[0] -= 8;
+ VmWriteMemN (VmPtr, (UINTN) VmPtr->Gpr[0], (UINTN) FramePtr);
+ VmPtr->FramePtr = (VOID *) (UINTN) VmPtr->Gpr[0];
+ VmPtr->Gpr[0] -= 8;
+ VmWriteMem64 (VmPtr, (UINTN) VmPtr->Gpr[0], (UINT64) (UINTN) (VmPtr->Ip + Size));
+
+ CopyMem (&TargetEbcAddr, (UINT8 *)FuncAddr + IndexOfEbcEntrypoint, sizeof(UINTN));
+ VmPtr->Ip = (VMIP) (UINTN) TargetEbcAddr;
+ } else {
+ //
+ // The callee is not a thunk to EBC, call native code,
+ // and get return value.
+ //
+ VmPtr->Gpr[7] = EbcLLCALLEXNative (FuncAddr, NewStackPointer, FramePtr);
+
+ //
+ // Advance the IP.
+ //
+ VmPtr->Ip += Size;
+ }
+}
+
diff --git a/MdeModulePkg/Universal/EbcDxe/EbcDxe.inf b/MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
index 15dc01c..e9a0b28 100644
--- a/MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+++ b/MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
@@ -5,6 +5,7 @@
# platform and processor-independent mechanisms for loading and executing EFI
# device drivers.
#
+# Copyright (c) 2015, The Linux Foundation. All rights reserved.
# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -28,7 +29,7 @@ [Defines]
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF
+# VALID_ARCHITECTURES = IA32 X64 IPF AARCH64
#

[Sources]
@@ -54,6 +55,9 @@ [Sources.IPF]
Ipf/EbcSupport.c
Ipf/EbcLowLevel.s

+[Sources.AARCH64]
+ AArch64/EbcSupport.c
+ AArch64/EbcLowLevel.S

[Packages]
MdePkg/MdePkg.dec
--
2.1.4


[RFC 2/2] ArmVirtPkg: enable EBC interpreter for AArch64 QEMU

Leif Lindholm <leif.lindholm@...>
 

Since we now have EBC support for AArch64, enable it by default
on the QEMU platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@...>
---
ArmVirtPkg/ArmVirtQemu.dsc | 1 +
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 5 +++++
2 files changed, 6 insertions(+)

diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 9f88786..fb851e7 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -401,3 +401,4 @@ [Components.AARCH64]
<LibraryClasses>
NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
}
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index ad7037f..0a5b899 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -146,6 +146,11 @@ [FV.FvMain]
#
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpiPlatformDxe.inf
+
+ #
+ # EBC support
+ #
+ INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
!endif

#
--
2.1.4


Re: bugzilla whining

Michael D Kinney
 

Laszlo,

I have changed the global email setting for 'whinedays' to 0 to disable
that built-in Whine Event.

This means the only whine messages that should occur are Whine Events
added by individual users or administrators.

FYI...I had enabled that feature to make sure the cron jobs were
running correctly. Thanks for verifying :)

Best regards,

Mike

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Friday, July 29, 2016 12:40 AM
To: Kinney, Michael D <michael.d.kinney@...>
Cc: edk2-devel-01 <edk2-devel@...>
Subject: bugzilla whining

Hello Mike,

I got my first ever bugzilla whine today. It says "All of these bugs are
in the CONFIRMED state, and have not been touched in 7 days or more."

I'm not amused. :) I keep a very close eye on my BZs and I don't welcome
automated whines.

I checked the Bugzilla 5 documentation about whines:

http://bugzilla.readthedocs.io/en/5.0/administering/whining.html#whining
http://bugzilla.readthedocs.io/en/5.0/using/preferences.html?highlight=whine#permission
s
http://bugzilla.readthedocs.io/en/5.0/administering/parameters.html?highlight=whine#ema
il

I confirmed on my account (under Preferences | Permissions) that I have
the "bz_canusewhines" permission (--> "User can configure whine reports
for self"). However, when I go to Administration | Whining, it seems
that I can only create new whines -- I don't seem to have any personal
whines set up at the moment.

Which makes me think that this is a central default. Can we please make
it a personal setting instead?

Thank you,
Laszlo


Re: [PATCH] add top-level .gitattributes file, dealing with .depex

Leif Lindholm <leif.lindholm@...>
 

On Thu, Jul 07, 2016 at 05:03:13PM +0200, Laszlo Ersek wrote:
On 07/07/16 16:24, Leif Lindholm wrote:
Git tends to see .depex files as text, causing hideous patches being
generated (and breaking PatchCheck.py).

Add a .gitattributes file instructing git to treat them as binary.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@...>
---
.gitattributes | 1 +
1 file changed, 1 insertion(+)
create mode 100644 .gitattributes

diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..2d8a45b
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.depex binary
What generates .depex files? I've never seen any.

Also, unless you add .depex files with "git add" to the set of tracked files, no patches / diffs should cover them. What am I missing? :)

... Hm, after

$ find . -iname "*.depex"

I see .depex files in Build/ (which should be ignored altogether), and

./Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex

Why does that file exist in the tree? Let me see... git log says nothing relevant (the file dates back to commit 3cbfba02fef9, "Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to").

Grepping the tree for the filename itself leads to:

Vlv2TbltDevicePkg/PlatformPkg.fdf: DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex
Vlv2TbltDevicePkg/PlatformPkgGcc.fdf: DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex

Do these rules exist to override the DEPEX sections of binary-only modules? If so: that's horrible.

Anyway, given that edk2 contains at least one .depex file, and your patch is correct according to <https://git-scm.com/book/en/v2/Customizing-Git-Git-Attributes>:

Reviewed-by: Laszlo Ersek <lersek@...>
Thanks!

I had hoped for comments from someone else on cc, since we don't have
any Maintainers.txt entry for the top level directory :)

But if I don't hear anything before Monday, I'll push it then.

Regards,

Leif


Re: [PATCH] add top-level .gitattributes file, dealing with .depex

Tim Lewis
 

It appears that this file is not actually used. It is only referenced in the [Rule.Common.UEFI_DRIVER.NATIVE_BINARY] rule in PlatformPkg.fdf. A little further research shows that an alternate method was used for the actual GOP binary (see below). A grep of the entire tree shows that no one uses this rule NATIVE_BINARY. So it looks like it can just be cut out.

BTW, the downside of the method used for the binary version of the GOP driver, is that those drivers cannot use PCDs, since the PCD database is created based on references in the .inf. GOP works because it is pure UEFI and (therefore) doesn't use PCDs.

Tim

FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {
SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}
SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi
SECTION UI = "IntelGopDriver"
}

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@...] On Behalf Of Leif Lindholm
Sent: Friday, July 29, 2016 9:45 AM
To: Laszlo Ersek <lersek@...>
Cc: michael.d.kinney@...; Jordan Justen <jordan.l.justen@...>; edk2-devel@...; Andrew Fish <afish@...>
Subject: Re: [edk2] [PATCH] add top-level .gitattributes file, dealing with .depex

On Thu, Jul 07, 2016 at 05:03:13PM +0200, Laszlo Ersek wrote:
On 07/07/16 16:24, Leif Lindholm wrote:
Git tends to see .depex files as text, causing hideous patches being
generated (and breaking PatchCheck.py).

Add a .gitattributes file instructing git to treat them as binary.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@...>
---
.gitattributes | 1 +
1 file changed, 1 insertion(+)
create mode 100644 .gitattributes

diff --git a/.gitattributes b/.gitattributes new file mode 100644
index 0000000..2d8a45b
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.depex binary
What generates .depex files? I've never seen any.

Also, unless you add .depex files with "git add" to the set of tracked
files, no patches / diffs should cover them. What am I missing? :)

... Hm, after

$ find . -iname "*.depex"

I see .depex files in Build/ (which should be ignored altogether), and

./Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex

Why does that file exist in the tree? Let me see... git log says nothing relevant (the file dates back to commit 3cbfba02fef9, "Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to").

Grepping the tree for the filename itself leads to:

Vlv2TbltDevicePkg/PlatformPkg.fdf: DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex
Vlv2TbltDevicePkg/PlatformPkgGcc.fdf: DXE_DEPEX DXE_DEPEX Optional $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex

Do these rules exist to override the DEPEX sections of binary-only modules? If so: that's horrible.

Anyway, given that edk2 contains at least one .depex file, and your patch is correct according to <https://git-scm.com/book/en/v2/Customizing-Git-Git-Attributes>:

Reviewed-by: Laszlo Ersek <lersek@...>
Thanks!

I had hoped for comments from someone else on cc, since we don't have any Maintainers.txt entry for the top level directory :)

But if I don't hear anything before Monday, I'll push it then.

Regards,

Leif

_______________________________________________
edk2-devel mailing list
edk2-devel@...
https://lists.01.org/mailman/listinfo/edk2-devel


[Patch v4 00/46] MP Initialize Library

Jeff Fan <jeff.fan@...>
 

We add MP Initialize Library defined in UefiCpuPkg/Include/Library/MpInitLib.h.
It will provide basic functionalities of MP services and could be consumed by
CPU MP PEI and CPU MP DXE to produce CPU MP PPI and CPU MP Protocol. Then most
of code could be shared between PEI and DXE modules.

PeiMpInitLib and DxeMpInitLib are added to make the CpuMpPei and CpuDxe more
simply.

I also updated the Ovmf Platform and Quark platform to consume MP Initialize
library. I have tested Ovmf platform and have not tested Quark yet.

v4:
1. Update Patches #2 - #6, #10, #15, #28, #30, #31, #33, #34, #38, #41, #43.
2. Add Patches #7, #8, #42, #44 - #46.
3. Add Reviewed-by: Laszlo Ersek <lersek@...> on Patches #1, #2.
(Please see the patches commit log for more details)

v3:
1. Update Patch #2, #4 - #8, #28, #33, #36, #38 per Giri's comments to
a. Update SDM date to June, 2016
b. Mention BCD format in CPU_MICROCODE_DATE
c. Rename ProcessorChecksum to Checksum to match SDM.
d. Add whitespace after MpInitLibInitialize
e. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec.
f. Rename NumApsExecutingLoction to NumApsExecutingLocation
g. Add whitespace after ; in .nasm file
h. Rename *RellocateAp* to *RelocateAp*
2. Update Patch #16, #17, #29-#32 to
a. Use CamelCase for mStopCheckAllApsStatus and CheckAndUpdateApsStatus().
3. Update Patch #36 and #39 to
a. Add PeiMpInitLib instance in UefiCpuPkg.dsc
b. Add DxeMpInitLib instance in UefiCpuPkg.dsc
4. Update Patch #39 and #40 to
a. move the code of consuming MP Initialize library from patch #40 to
patch #39.
5. Update Patch #1, #3 - #8, #16 to
a. Add Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>

I fork the whole tree with the updated v3 patches
at https://github.com/vanjeff/edk2/tree/MpInitLibV4 for review.

Jeff Fan (46):
UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM
UefiCpuPkg/CpuS3DataDxe: Move StartupVector allocation to EndOfDxe()
UefiCpuPkg/MpInitLib: Add MP Initialize library class definition
UefiCpuPkg/MpInitLib: Add two instances PeiMpInitLib and DxeMpInitLib
UefiCpuPkg/MpInitLib: Add AP assembly code and MP_CPU_EXCHANGE_INFO
UefiCpuPkg/MpInitLib: Fix typo and clean up the code
UefiCpuPkg/MpInitLib: Add EnableExecuteDisable in MP_CPU_EXCHANGE_INFO
UefiCpuPkg/MpInitLib: Add AsmRelocateApLoop() assembly code
UefiCpuPkg/MpInitLib: Add MP_ASSEMBLY_ADDRESS_MAP
UefiCpuPkg/MpInitLib: Get ApLoopMode and MointorFilter size
UefiCpuPkg/MpInitLib: Allocate and initialize memory of MP Data buffer
UefiCpuPkg/MpInitLib: Initialize CPU_AP_DATA for CPU APs
UefiCpuPkg/MpInitLib: Add CPU_VOLATILE_REGISTERS & worker functions
UefiCpuPkg/MpInitLib: Add MicrocodeDetect() and load microcode on BSP
UefiCpuPkg/MpInitLib: Save CPU MP Data pointer
UefiCpuPkg/MpInitLib: Register one End of PEI callback function
UefiCpuPkg/MpInitLib: Register one period event to check APs status
UefiCpuPkg/MpInitLib: Allocate AP reset vector buffer under 1MB
UefiCpuPkg/MpInitLib: Add ApCFunction() executed by assembly code
UefiCpuPkg/MpInitLib: Fill MP_CPU_EXCHANGE_INFO fields
UefiCpuPkg/MpInitLib: Add WakeUpAP()
UefiCpuPkg/MpInitLib: Send INIT-SIPI-SIPI to get processor count
UefiCpuPkg/MpInitLib: Enable x2APIC mode on BSP/APs
UefiCpuPkg/MpInitLib: Sort processor by ascending order of APIC ID
UefiCpuPkg/MpInitLib: Skip collect processor count if GUIDed HOB exist
UefiCpuPkg/MpInitLib: Implementation of
MpInitLibGetNumberOfProcessors()
UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetProcessorInfo()
UefiCpuPkg/MpInitLib: Implementation of MpInitLibWhoAmI()
UefiCpuPkg/MpInitLib: Implementation of MpInitLibSwitchBSP()
UefiCpuPkg/MpInitLib: Implementation of MpInitLibEnableDisableAP()
UefiCpuPkg/MpInitLib: Check APs Status and update APs status
UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupThisAP()
UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupAllAPs()
UefiCpuPkg/MpInitLib: Place APs in safe loop before hand-off to OS
OvmfPkg: Add MpInitLib reference in DSC files.
QuarkPlatformPkg: Add MpInitLib reference in DSC files.
UefiCpuPkg/CpuMpPei: Consume MpInitLib to produce CPU MP PPI services
UefiCpuPkg/CpuMpPei: Remove unused files and codes
UefiCpuPkg/CpuMpPei: Delete PeiMpServices.c and PeiMpServices.h
UefiCpuPkg/CpuDxe: Consume MpInitLib to produce CPU MP Protocol
services
UefiCpuPkg/CpuDxe: Move SetMtrrsFromBuffer() location.
UefiCpuPkg/CpuDxe: Remove unused codes and files
MdePkg/MpService.h: Fixed typo in function header to match PI spec
MdePkg/MpService.h: Trim whitespace at end of line
UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI spec

MdePkg/Include/Protocol/MpService.h | 490 ++---
OvmfPkg/OvmfPkgIa32.dsc | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 2 +
OvmfPkg/OvmfPkgX64.dsc | 2 +
QuarkPlatformPkg/Quark.dsc | 1 +
QuarkPlatformPkg/QuarkMin.dsc | 3 +-
UefiCpuPkg/CpuDxe/ApStartup.c | 478 -----
UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +-
UefiCpuPkg/CpuDxe/CpuDxe.h | 13 +-
UefiCpuPkg/CpuDxe/CpuDxe.inf | 12 +-
UefiCpuPkg/CpuDxe/CpuDxe.uni | 10 +-
UefiCpuPkg/CpuDxe/CpuDxeExtra.uni | 4 +-
UefiCpuPkg/CpuDxe/CpuMp.c | 1302 +------------
UefiCpuPkg/CpuDxe/CpuMp.h | 186 +-
UefiCpuPkg/CpuDxe/Ia32/MpAsm.asm | 76 -
UefiCpuPkg/CpuDxe/Ia32/MpAsm.nasm | 68 -
UefiCpuPkg/CpuDxe/X64/MpAsm.asm | 76 -
UefiCpuPkg/CpuDxe/X64/MpAsm.nasm | 70 -
UefiCpuPkg/CpuMpPei/CpuBist.c | 53 +-
UefiCpuPkg/CpuMpPei/CpuMpPei.c | 1118 ++++-------
UefiCpuPkg/CpuMpPei/CpuMpPei.h | 515 ++---
UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 32 +-
UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm | 250 ---
UefiCpuPkg/CpuMpPei/Microcode.h | 58 -
UefiCpuPkg/CpuMpPei/PeiMpServices.c | 956 ----------
UefiCpuPkg/CpuMpPei/PeiMpServices.h | 377 ----
UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm | 290 ---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 42 +-
UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf | 2 +-
UefiCpuPkg/Include/Library/MpInitLib.h | 353 ++++
UefiCpuPkg/Include/Register/LocalApic.h | 20 +-
UefiCpuPkg/Include/Register/Microcode.h | 200 ++
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 29 +-
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 51 +-
.../MpInitLib/DxeMpInitLib.inf} | 68 +-
.../MpInitLib/DxeMpInitLib.uni} | 12 +-
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 646 +++++++
.../{CpuMpPei => Library/MpInitLib}/Ia32/MpEqu.inc | 4 +-
.../MpInitLib}/Ia32/MpFuncs.nasm | 66 +-
.../{CpuMpPei => Library/MpInitLib}/Microcode.c | 77 +-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 2018 ++++++++++++++++++++
UefiCpuPkg/Library/MpInitLib/MpLib.h | 529 +++++
.../MpInitLib/PeiMpInitLib.inf} | 60 +-
.../MpInitLib/PeiMpInitLib.uni} | 12 +-
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 640 +++++++
.../{CpuMpPei => Library/MpInitLib}/X64/MpEqu.inc | 6 +-
.../MpInitLib}/X64/MpFuncs.nasm | 84 +-
UefiCpuPkg/UefiCpuPkg.dec | 4 +
UefiCpuPkg/UefiCpuPkg.dsc | 5 +-
49 files changed, 5744 insertions(+), 5645 deletions(-)
delete mode 100644 UefiCpuPkg/CpuDxe/ApStartup.c
delete mode 100644 UefiCpuPkg/CpuDxe/Ia32/MpAsm.asm
delete mode 100644 UefiCpuPkg/CpuDxe/Ia32/MpAsm.nasm
delete mode 100644 UefiCpuPkg/CpuDxe/X64/MpAsm.asm
delete mode 100644 UefiCpuPkg/CpuDxe/X64/MpAsm.nasm
delete mode 100644 UefiCpuPkg/CpuMpPei/Ia32/MpFuncs.asm
delete mode 100644 UefiCpuPkg/CpuMpPei/Microcode.h
delete mode 100644 UefiCpuPkg/CpuMpPei/PeiMpServices.c
delete mode 100644 UefiCpuPkg/CpuMpPei/PeiMpServices.h
delete mode 100644 UefiCpuPkg/CpuMpPei/X64/MpFuncs.asm
create mode 100644 UefiCpuPkg/Include/Library/MpInitLib.h
create mode 100644 UefiCpuPkg/Include/Register/Microcode.h
copy UefiCpuPkg/{CpuMpPei/CpuMpPei.inf => Library/MpInitLib/DxeMpInitLib.inf} (52%)
copy UefiCpuPkg/{CpuDxe/CpuDxeExtra.uni => Library/MpInitLib/DxeMpInitLib.uni} (53%)
create mode 100644 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
rename UefiCpuPkg/{CpuMpPei => Library/MpInitLib}/Ia32/MpEqu.inc (88%)
rename UefiCpuPkg/{CpuMpPei => Library/MpInitLib}/Ia32/MpFuncs.nasm (77%)
rename UefiCpuPkg/{CpuMpPei => Library/MpInitLib}/Microcode.c (68%)
create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLib.c
create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLib.h
copy UefiCpuPkg/{CpuMpPei/CpuMpPei.inf => Library/MpInitLib/PeiMpInitLib.inf} (58%)
copy UefiCpuPkg/{CpuDxe/CpuDxeExtra.uni => Library/MpInitLib/PeiMpInitLib.uni} (53%)
create mode 100644 UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
rename UefiCpuPkg/{CpuMpPei => Library/MpInitLib}/X64/MpEqu.inc (88%)
rename UefiCpuPkg/{CpuMpPei => Library/MpInitLib}/X64/MpFuncs.nasm (73%)

--
2.7.4.windows.1


[Patch v4 01/46] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions

Jeff Fan <jeff.fan@...>
 

#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@...>
Cc: Feng Tian <feng.tian@...>
Cc: Giri P Mudusuru <giri.p.mudusuru@...>
Cc: Laszlo Ersek <lersek@...>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@...>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>
Reviewed-by: Laszlo Ersek <lersek@...>
---
UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 +
UefiCpuPkg/CpuMpPei/PeiMpServices.c | 20 ++++-----
UefiCpuPkg/Include/Register/LocalApic.h | 20 +--------
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 29 ++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 51 +++++++++++-----------
5 files changed, 53 insertions(+), 68 deletions(-)

diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
index b2e578b..0d1a14a 100644
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
@@ -25,6 +25,7 @@

#include <Register/Cpuid.h>
#include <Register/LocalApic.h>
+#include <Register/Msr.h>

#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
diff --git a/UefiCpuPkg/CpuMpPei/PeiMpServices.c b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
index e784377..e06fdf1 100644
--- a/UefiCpuPkg/CpuMpPei/PeiMpServices.c
+++ b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
@@ -1,7 +1,7 @@
/** @file
Implementation of Multiple Processor PPI services.

- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -729,9 +729,9 @@ PeiSwitchBSP (
IN BOOLEAN EnableOldBSP
)
{
- PEI_CPU_MP_DATA *PeiCpuMpData;
- UINTN CallerNumber;
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ PEI_CPU_MP_DATA *PeiCpuMpData;
+ UINTN CallerNumber;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

PeiCpuMpData = GetMpHobData ();
if (PeiCpuMpData == NULL) {
@@ -774,9 +774,9 @@ PeiSwitchBSP (
//
// Clear the BSP bit of MSR_IA32_APIC_BASE
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
- ApicBaseMsr.Bits.Bsp = 0;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Bits.BSP = 0;
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);

PeiCpuMpData->BSPInfo.State = CPU_SWITCH_STATE_IDLE;
PeiCpuMpData->APInfo.State = CPU_SWITCH_STATE_IDLE;
@@ -805,9 +805,9 @@ PeiSwitchBSP (
//
// Set the BSP bit of MSR_IA32_APIC_BASE on new BSP
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
- ApicBaseMsr.Bits.Bsp = 1;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Bits.BSP = 1;
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
//
// Set old BSP enable state
//
diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 346cce6..cfb6d76 100644
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -1,7 +1,7 @@
/** @file
IA32 Local APIC Definitions.

- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,11 +16,6 @@
#define __LOCAL_APIC_H__

//
-// Definitions for IA32 architectural MSRs
-//
-#define MSR_IA32_APIC_BASE_ADDRESS 0x1B
-
-//
// Definition for Local APIC registers and related values
//
#define XAPIC_ID_OFFSET 0x20
@@ -53,19 +48,6 @@
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3

-typedef union {
- struct {
- UINT32 Reserved0:8; ///< Reserved.
- UINT32 Bsp:1; ///< Processor is BSP.
- UINT32 Reserved1:1; ///< Reserved.
- UINT32 Extd:1; ///< Enable x2APIC mode.
- UINT32 En:1; ///< xAPIC global enable/disable.
- UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
- UINT32 ApicBaseHigh:32;
- } Bits;
- UINT64 Uint64;
-} MSR_IA32_APIC_BASE;
-
//
// Local APIC Version Register.
//
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 1fca66e..8d0fb02 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@

This local APIC library instance supports xAPIC mode only.

- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +15,7 @@
**/

#include <Register/Cpuid.h>
+#include <Register/Msr.h>
#include <Register/LocalApic.h>

#include <Library/BaseLib.h>
@@ -67,7 +68,7 @@ GetLocalApicBaseAddress (
VOID
)
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

if (!LocalApicBaseAddressMsrSupported ()) {
//
@@ -77,10 +78,10 @@ GetLocalApicBaseAddress (
return PcdGet32 (PcdCpuLocalApicBaseAddress);
}

- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);

- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
- (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}

/**
@@ -97,7 +98,7 @@ SetLocalApicBaseAddress (
IN UINTN BaseAddress
)
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);

@@ -108,12 +109,12 @@ SetLocalApicBaseAddress (
return;
}

- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);

- ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
- ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+ ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));

- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}

/**
@@ -246,18 +247,18 @@ GetApicMode (
{
DEBUG_CODE (
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

//
// Check to see if the CPU supports the APIC Base Address MSR
//
if (LocalApicBaseAddressMsrSupported ()) {
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
// Local APIC should have been enabled
//
- ASSERT (ApicBaseMsr.Bits.En != 0);
- ASSERT (ApicBaseMsr.Bits.Extd == 0);
+ ASSERT (ApicBaseMsr.Bits.EN != 0);
+ ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
}
);
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 38f5370..4c42696 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes.

- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +16,7 @@
**/

#include <Register/Cpuid.h>
+#include <Register/Msr.h>
#include <Register/LocalApic.h>

#include <Library/BaseLib.h>
@@ -68,7 +69,7 @@ GetLocalApicBaseAddress (
VOID
)
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

if (!LocalApicBaseAddressMsrSupported ()) {
//
@@ -78,10 +79,10 @@ GetLocalApicBaseAddress (
return PcdGet32 (PcdCpuLocalApicBaseAddress);
}

- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);

- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
- (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}

/**
@@ -98,7 +99,7 @@ SetLocalApicBaseAddress (
IN UINTN BaseAddress
)
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);

@@ -109,12 +110,12 @@ SetLocalApicBaseAddress (
return;
}

- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);

- ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
- ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+ ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));

- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}

/**
@@ -301,7 +302,7 @@ GetApicMode (
VOID
)
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

if (!LocalApicBaseAddressMsrSupported ()) {
//
@@ -310,12 +311,12 @@ GetApicMode (
return LOCAL_APIC_MODE_XAPIC;
}

- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
// Local APIC should have been enabled
//
- ASSERT (ApicBaseMsr.Bits.En != 0);
- if (ApicBaseMsr.Bits.Extd != 0) {
+ ASSERT (ApicBaseMsr.Bits.EN != 0);
+ if (ApicBaseMsr.Bits.EXTD != 0) {
return LOCAL_APIC_MODE_X2APIC;
} else {
return LOCAL_APIC_MODE_XAPIC;
@@ -339,8 +340,8 @@ SetApicMode (
IN UINTN ApicMode
)
{
- UINTN CurrentMode;
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ UINTN CurrentMode;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;

if (!LocalApicBaseAddressMsrSupported ()) {
//
@@ -355,9 +356,9 @@ SetApicMode (
case LOCAL_APIC_MODE_XAPIC:
break;
case LOCAL_APIC_MODE_X2APIC:
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
- ApicBaseMsr.Bits.Extd = 1;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Bits.EXTD = 1;
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
break;
default:
ASSERT (FALSE);
@@ -369,12 +370,12 @@ SetApicMode (
// Transition from x2APIC mode to xAPIC mode is a two-step process:
// x2APIC -> Local APIC disabled -> xAPIC
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
- ApicBaseMsr.Bits.Extd = 0;
- ApicBaseMsr.Bits.En = 0;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
- ApicBaseMsr.Bits.En = 1;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Bits.EXTD = 0;
+ ApicBaseMsr.Bits.EN = 0;
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+ ApicBaseMsr.Bits.EN = 1;
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
break;
case LOCAL_APIC_MODE_X2APIC:
break;
--
2.7.4.windows.1


[Patch v4 02/46] UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM

Jeff Fan <jeff.fan@...>
 

Add microcode definitions defined in Intel(R) 64 and IA-32 Architectures
Software Developer's Manual Volume 3A, Section 9.11.

v4:
1. ProcessorSignature type changed to CPU_MICROCODE_PROCESSOR_SIGNATURE
2. Add pack(1) for structure CPU_MICROCODE_HEADER and
CPU_MICROCODE_EXTENDED_TABLE.
v3:
1. Update SDM date to June, 2016
2. Mention BCD format in CPU_MICROCODE_DATE
3. Rename ProcessorChecksum to Checksum to match SDM.

Cc: Michael Kinney <michael.d.kinney@...>
Cc: Feng Tian <feng.tian@...>
Cc: Giri P Mudusuru <giri.p.mudusuru@...>
Cc: Laszlo Ersek <lersek@...>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@...>
Reviewed-by: Laszlo Ersek <lersek@...>
---
UefiCpuPkg/Include/Register/Microcode.h | 200 ++++++++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
create mode 100644 UefiCpuPkg/Include/Register/Microcode.h

diff --git a/UefiCpuPkg/Include/Register/Microcode.h b/UefiCpuPkg/Include/Register/Microcode.h
new file mode 100644
index 0000000..94529a1
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Microcode.h
@@ -0,0 +1,200 @@
+/** @file
+ Microcode Definitions.
+
+ Microcode Definitions based on contents of the
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ Volume 3A, Section 9.11 Microcode Definitions
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
+ June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
+
+**/
+
+#ifndef __MICROCODE_H__
+#define __MICROCODE_H__
+
+///
+/// CPU Microcode Date in BCD format
+///
+typedef union {
+ struct {
+ UINT32 Year:16;
+ UINT32 Day:8;
+ UINT32 Month:8;
+ } Bits;
+ UINT32 Uint32;
+} CPU_MICROCODE_DATE;
+
+///
+/// CPU Microcode Processor Signature format
+///
+typedef union {
+ struct {
+ UINT32 Stepping:4;
+ UINT32 Model:4;
+ UINT32 Family:4;
+ UINT32 Type:2;
+ UINT32 Reserved1:2;
+ UINT32 ExtendedModel:4;
+ UINT32 ExtendedFamily:8;
+ UINT32 Reserved2:4;
+ } Bits;
+ UINT32 Uint32;
+} CPU_MICROCODE_PROCESSOR_SIGNATURE;
+
+#pragma pack (1)
+
+///
+/// Microcode Update Format definition
+///
+typedef struct {
+ ///
+ /// Version number of the update header
+ ///
+ UINT32 HeaderVersion;
+ ///
+ /// Unique version number for the update, the basis for the update
+ /// signature provided by the processor to indicate the current update
+ /// functioning within the processor. Used by the BIOS to authenticate
+ /// the update and verify that the processor loads successfully. The
+ /// value in this field cannot be used for processor stepping identification
+ /// alone. This is a signed 32-bit number.
+ ///
+ UINT32 UpdateRevision;
+ ///
+ /// Date of the update creation in binary format: mmddyyyy (e.g.
+ /// 07/18/98 is 07181998H).
+ ///
+ CPU_MICROCODE_DATE Date;
+ ///
+ /// Extended family, extended model, type, family, model, and stepping
+ /// of processor that requires this particular update revision (e.g.,
+ /// 00000650H). Each microcode update is designed specifically for a
+ /// given extended family, extended model, type, family, model, and
+ /// stepping of the processor.
+ /// The BIOS uses the processor signature field in conjunction with the
+ /// CPUID instruction to determine whether or not an update is
+ /// appropriate to load on a processor. The information encoded within
+ /// this field exactly corresponds to the bit representations returned by
+ /// the CPUID instruction.
+ ///
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+ ///
+ /// Checksum of Update Data and Header. Used to verify the integrity of
+ /// the update header and data. Checksum is correct when the
+ /// summation of all the DWORDs (including the extended Processor
+ /// Signature Table) that comprise the microcode update result in
+ /// 00000000H.
+ ///
+ UINT32 Checksum;
+ ///
+ /// Version number of the loader program needed to correctly load this
+ /// update. The initial version is 00000001H
+ ///
+ UINT32 LoaderRevision;
+ ///
+ /// Platform type information is encoded in the lower 8 bits of this 4-
+ /// byte field. Each bit represents a particular platform type for a given
+ /// CPUID. The BIOS uses the processor flags field in conjunction with
+ /// the platform Id bits in MSR (17H) to determine whether or not an
+ /// update is appropriate to load on a processor. Multiple bits may be set
+ /// representing support for multiple platform IDs.
+ ///
+ UINT32 ProcessorFlags;
+ ///
+ /// Specifies the size of the encrypted data in bytes, and must be a
+ /// multiple of DWORDs. If this value is 00000000H, then the microcode
+ /// update encrypted data is 2000 bytes (or 500 DWORDs).
+ ///
+ UINT32 DataSize;
+ ///
+ /// Specifies the total size of the microcode update in bytes. It is the
+ /// summation of the header size, the encrypted data size and the size of
+ /// the optional extended signature table. This value is always a multiple
+ /// of 1024.
+ ///
+ UINT32 TotalSize;
+ ///
+ /// Reserved fields for future expansion.
+ ///
+ UINT8 Reserved[12];
+} CPU_MICROCODE_HEADER;
+
+///
+/// Extended Signature Table Header Field Definitions
+///
+typedef struct {
+ ///
+ /// Specifies the number of extended signature structures (Processor
+ /// Signature[n], processor flags[n] and checksum[n]) that exist in this
+ /// microcode update
+ ///
+ UINT32 ExtendedSignatureCount;
+ ///
+ /// Checksum of update extended processor signature table. Used to
+ /// verify the integrity of the extended processor signature table.
+ /// Checksum is correct when the summation of the DWORDs that
+ /// comprise the extended processor signature table results in
+ /// 00000000H.
+ ///
+ UINT32 ExtendedChecksum;
+ ///
+ /// Reserved fields.
+ ///
+ UINT8 Reserved[12];
+} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+///
+/// Extended Signature Table Field Definitions
+///
+typedef struct {
+ ///
+ /// Extended family, extended model, type, family, model, and stepping
+ /// of processor that requires this particular update revision (e.g.,
+ /// 00000650H). Each microcode update is designed specifically for a
+ /// given extended family, extended model, type, family, model, and
+ /// stepping of the processor.
+ /// The BIOS uses the processor signature field in conjunction with the
+ /// CPUID instruction to determine whether or not an update is
+ /// appropriate to load on a processor. The information encoded within
+ /// this field exactly corresponds to the bit representations returned by
+ /// the CPUID instruction.
+ ///
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+ ///
+ /// Platform type information is encoded in the lower 8 bits of this 4-
+ /// byte field. Each bit represents a particular platform type for a given
+ /// CPUID. The BIOS uses the processor flags field in conjunction with
+ /// the platform Id bits in MSR (17H) to determine whether or not an
+ /// update is appropriate to load on a processor. Multiple bits may be set
+ /// representing support for multiple platform IDs.
+ ///
+ UINT32 ProcessorFlag;
+ ///
+ /// Used by utility software to decompose a microcode update into
+ /// multiple microcode updates where each of the new updates is
+ /// constructed without the optional Extended Processor Signature
+ /// Table.
+ /// To calculate the Checksum, substitute the Primary Processor
+ /// Signature entry and the Processor Flags entry with the
+ /// corresponding Extended Patch entry. Delete the Extended Processor
+ /// Signature Table entries. The Checksum is correct when the
+ /// summation of all DWORDs that comprise the created Extended
+ /// Processor Patch results in 00000000H.
+ ///
+ UINT32 Checksum;
+} CPU_MICROCODE_EXTENDED_TABLE;
+
+#pragma pack ()
+
+#endif
--
2.7.4.windows.1


[Patch v4 03/46] UefiCpuPkg/CpuS3DataDxe: Move StartupVector allocation to EndOfDxe()

Jeff Fan <jeff.fan@...>
 

Currently, we will allocate StartupVector buffer under 1MB at entry point
function. But some modules may allocate some hard code address under 1MB.
For example, LegacyBiosDxe driver tries to manage some legacy range under
640KB.

To avoid the conflicts, we move StartupVector buffer allocation to End Of
DXE event callback function.

v4:
Update the Context parameter is used as a pointer to AcpiCpuDataEx, then
we needn't to add the global variable.

Cc: Michael Kinney <michael.d.kinney@...>
Cc: Feng Tian <feng.tian@...>
Cc: Giri P Mudusuru <giri.p.mudusuru@...>
Cc: Laszlo Ersek <lersek@...>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@...>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 42 +++++++++++++++++---------------
UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf | 2 +-
2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index 9fb47dc..7bd928f 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so this module does not
support hot plug CPUs. This module can be copied into a CPU specific package
and customized if these additional features are required.

-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2015, Red Hat, Inc.

This program and the accompanying materials
@@ -84,20 +84,36 @@ AllocateAcpiNvsMemoryBelow4G (
/**
Callback function executed when the EndOfDxe event group is signaled.

- We delay saving the MTRR settings until BDS signals EndOfDxe.
+ We delay allocating StartupVector and saving the MTRR settings until BDS signals EndOfDxe.

@param[in] Event Event whose notification function is being invoked.
@param[out] Context Pointer to the MTRR_SETTINGS buffer to fill in.
**/
VOID
EFIAPI
-SaveMtrrsOnEndOfDxe (
+CpuS3DataOnEndOfDxe (
IN EFI_EVENT Event,
OUT VOID *Context
)
{
+ EFI_STATUS Status;
+ ACPI_CPU_DATA_EX *AcpiCpuDataEx;
+
+ AcpiCpuDataEx = (ACPI_CPU_DATA_EX *) Context;
+ //
+ // Allocate a 4KB reserved page below 1MB
+ //
+ AcpiCpuDataEx->AcpiCpuData.StartupVector = BASE_1MB - 1;
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiReservedMemoryType,
+ 1,
+ &AcpiCpuDataEx->AcpiCpuData.StartupVector
+ );
+ ASSERT_EFI_ERROR (Status);
+
DEBUG ((EFI_D_VERBOSE, "%a\n", __FUNCTION__));
- MtrrGetAllMtrrs (Context);
+ MtrrGetAllMtrrs (&AcpiCpuDataEx->MtrrTable);

//
// Close event, so it will not be invoked again.
@@ -162,18 +178,6 @@ CpuS3DataInitialize (
ASSERT_EFI_ERROR (Status);

//
- // Allocate a 4KB reserved page below 1MB
- //
- AcpiCpuData->StartupVector = BASE_1MB - 1;
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiReservedMemoryType,
- 1,
- &AcpiCpuData->StartupVector
- );
- ASSERT_EFI_ERROR (Status);
-
- //
// Get the number of CPUs
//
Status = MpServices->GetNumberOfProcessors (
@@ -255,13 +259,13 @@ CpuS3DataInitialize (

//
// Register EFI_END_OF_DXE_EVENT_GROUP_GUID event.
- // The notification function saves MTRRs for ACPI_CPU_DATA
+ // The notification function allocates StartupVector and saves MTRRs for ACPI_CPU_DATA
//
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
- SaveMtrrsOnEndOfDxe,
- &AcpiCpuDataEx->MtrrTable,
+ CpuS3DataOnEndOfDxe,
+ AcpiCpuData,
&gEfiEndOfDxeEventGroupGuid,
&Event
);
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf b/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
index 857e12b..608e19f 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
@@ -9,7 +9,7 @@
# support hot plug CPUs. This module can be copied into a CPU specific package
# and customized if these additional features are required.
#
-# Copyright (c) 2013-2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2013-2016, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2015, Red Hat, Inc.
#
# This program and the accompanying materials
--
2.7.4.windows.1


[Patch v4 04/46] UefiCpuPkg/MpInitLib: Add MP Initialize library class definition

Jeff Fan <jeff.fan@...>
 

MP Initialize library provides basic functionalities to do APs initialization,
to manage MP information and to wakeup APs to execute AP task.

It could be consumed by CPU MP PEI or DXE drivers to provide CPU MP PPI/Protocol
services.

v4:
1. MpInitLibGetProcessorInfo():
Update HealthData type from UINT32 to EFI_HEALTH_FLAGS.
Add #include <Ppi/SecPlatformInformation.h>
2. MpInitLibSwitchBSP():
Return EFI_DEVICE_ERROR instead of EFI_SUCCESS if the calling processor is
an AP.
3. MpInitLibStartupThisAP():
Fix several incorrect references to "APs" to match PI spec.
4. MpInitLibSwitchBSP() and MpInitLibEnableDisableAP():
Fix incorrect description on ProcessorNumber.
5. Trim whitespace at end of line.

v3:
1. Add whitespace after MpInitLibInitialize
2. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@...>
Cc: Feng Tian <feng.tian@...>
Cc: Giri P Mudusuru <giri.p.mudusuru@...>
Cc: Laszlo Ersek <lersek@...>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@...>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>
---
UefiCpuPkg/Include/Library/MpInitLib.h | 353 +++++++++++++++++++++++++++++++++
UefiCpuPkg/UefiCpuPkg.dec | 4 +
2 files changed, 357 insertions(+)
create mode 100644 UefiCpuPkg/Include/Library/MpInitLib.h

diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h b/UefiCpuPkg/Include/Library/MpInitLib.h
new file mode 100644
index 0000000..3e19382
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/MpInitLib.h
@@ -0,0 +1,353 @@
+/** @file
+ Multiple-Processor initialization Library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __MP_INIT_LIB_H__
+#define __MP_INIT_LIB_H__
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Protocol/MpService.h>
+
+/**
+ MP Initialize Library initialization.
+
+ This service will allocate AP reset vector and wakeup all APs to do APs
+ initialization.
+
+ This service must be invoked before all other MP Initialize Library
+ service are invoked.
+
+ @retval EFI_SUCCESS MP initialization succeeds.
+ @retval Others MP initialization fails.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibInitialize (
+ VOID
+ );
+
+/**
+ Retrieves the number of logical processor in the platform and the number of
+ those logical processors that are enabled on this boot. This service may only
+ be called from the BSP.
+
+ @param[out] NumberOfProcessors Pointer to the total number of logical
+ processors in the system, including the BSP
+ and disabled APs.
+ @param[out] NumberOfEnabledProcessors Pointer to the number of enabled logical
+ processors that exist in system, including
+ the BSP.
+
+ @retval EFI_SUCCESS The number of logical processors and enabled
+ logical processors was retrieved.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfEnabledProcessors
+ is NULL.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibGetNumberOfProcessors (
+ OUT UINTN *NumberOfProcessors, OPTIONAL
+ OUT UINTN *NumberOfEnabledProcessors OPTIONAL
+ );
+
+/**
+ Gets detailed MP-related information on the requested processor at the
+ instant this call is made. This service may only be called from the BSP.
+
+ @param[in] ProcessorNumber The handle number of processor.
+ @param[out] ProcessorInfoBuffer A pointer to the buffer where information for
+ the requested processor is deposited.
+ @param[out] HealthData Return processor health data.
+
+ @retval EFI_SUCCESS Processor information was returned.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist in the platform.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibGetProcessorInfo (
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer,
+ OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL
+ );
+
+/**
+ This service executes a caller provided function on all enabled APs.
+
+ @param[in] Procedure A pointer to the function to be run on
+ enabled APs of the system. See type
+ EFI_AP_PROCEDURE.
+ @param[in] SingleThread If TRUE, then all the enabled APs execute
+ the function specified by Procedure one by
+ one, in ascending order of processor handle
+ number. If FALSE, then all the enabled APs
+ execute the function specified by Procedure
+ simultaneously.
+ @param[in] WaitEvent The event created by the caller with CreateEvent()
+ service. If it is NULL, then execute in
+ blocking mode. BSP waits until all APs finish
+ or TimeoutInMicroSeconds expires. If it's
+ not NULL, then execute in non-blocking mode.
+ BSP requests the function specified by
+ Procedure to be started on all the enabled
+ APs, and go on executing immediately. If
+ all return from Procedure, or TimeoutInMicroSeconds
+ expires, this event is signaled. The BSP
+ can use the CheckEvent() or WaitForEvent()
+ services to check the state of event. Type
+ EFI_EVENT is defined in CreateEvent() in
+ the Unified Extensible Firmware Interface
+ Specification.
+ @param[in] TimeoutInMicrosecsond Indicates the time limit in microseconds for
+ APs to return from Procedure, either for
+ blocking or non-blocking mode. Zero means
+ infinity. If the timeout expires before
+ all APs return from Procedure, then Procedure
+ on the failed APs is terminated. All enabled
+ APs are available for next function assigned
+ by MpInitLibStartupAllAPs() or
+ MPInitLibStartupThisAP().
+ If the timeout expires in blocking mode,
+ BSP returns EFI_TIMEOUT. If the timeout
+ expires in non-blocking mode, WaitEvent
+ is signaled with SignalEvent().
+ @param[in] ProcedureArgument The parameter passed into Procedure for
+ all APs.
+ @param[out] FailedCpuList If NULL, this parameter is ignored. Otherwise,
+ if all APs finish successfully, then its
+ content is set to NULL. If not all APs
+ finish before timeout expires, then its
+ content is set to address of the buffer
+ holding handle numbers of the failed APs.
+ The buffer is allocated by MP Initialization
+ library, and it's the caller's responsibility to
+ free the buffer with FreePool() service.
+ In blocking mode, it is ready for consumption
+ when the call returns. In non-blocking mode,
+ it is ready when WaitEvent is signaled. The
+ list of failed CPU is terminated by
+ END_OF_CPU_LIST.
+
+ @retval EFI_SUCCESS In blocking mode, all APs have finished before
+ the timeout expired.
+ @retval EFI_SUCCESS In non-blocking mode, function has been dispatched
+ to all enabled APs.
+ @retval EFI_UNSUPPORTED A non-blocking mode request was made after the
+ UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was
+ signaled.
+ @retval EFI_UNSUPPORTED WaitEvent is not NULL if non-blocking mode is not
+ supported.
+ @retval EFI_DEVICE_ERROR Caller processor is AP.
+ @retval EFI_NOT_STARTED No enabled APs exist in the system.
+ @retval EFI_NOT_READY Any enabled APs are busy.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+ @retval EFI_TIMEOUT In blocking mode, the timeout expired before
+ all enabled APs have finished.
+ @retval EFI_INVALID_PARAMETER Procedure is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibStartupAllAPs (
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
+ );
+
+/**
+ This service lets the caller get one enabled AP to execute a caller-provided
+ function.
+
+ @param[in] Procedure A pointer to the function to be run on the
+ designated AP of the system. See type
+ EFI_AP_PROCEDURE.
+ @param[in] ProcessorNumber The handle number of the AP. The range is
+ from 0 to the total number of logical
+ processors minus 1. The total number of
+ logical processors can be retrieved by
+ MpInitLibGetNumberOfProcessors().
+ @param[in] WaitEvent The event created by the caller with CreateEvent()
+ service. If it is NULL, then execute in
+ blocking mode. BSP waits until this AP finish
+ or TimeoutInMicroSeconds expires. If it's
+ not NULL, then execute in non-blocking mode.
+ BSP requests the function specified by
+ Procedure to be started on this AP,
+ and go on executing immediately. If this AP
+ return from Procedure or TimeoutInMicroSeconds
+ expires, this event is signaled. The BSP
+ can use the CheckEvent() or WaitForEvent()
+ services to check the state of event. Type
+ EFI_EVENT is defined in CreateEvent() in
+ the Unified Extensible Firmware Interface
+ Specification.
+ @param[in] TimeoutInMicrosecsond Indicates the time limit in microseconds for
+ this AP to finish this Procedure, either for
+ blocking or non-blocking mode. Zero means
+ infinity. If the timeout expires before
+ this AP returns from Procedure, then Procedure
+ on the AP is terminated. The
+ AP is available for next function assigned
+ by MpInitLibStartupAllAPs() or
+ MpInitLibStartupThisAP().
+ If the timeout expires in blocking mode,
+ BSP returns EFI_TIMEOUT. If the timeout
+ expires in non-blocking mode, WaitEvent
+ is signaled with SignalEvent().
+ @param[in] ProcedureArgument The parameter passed into Procedure on the
+ specified AP.
+ @param[out] Finished If NULL, this parameter is ignored. In
+ blocking mode, this parameter is ignored.
+ In non-blocking mode, if AP returns from
+ Procedure before the timeout expires, its
+ content is set to TRUE. Otherwise, the
+ value is set to FALSE. The caller can
+ determine if the AP returned from Procedure
+ by evaluating this value.
+
+ @retval EFI_SUCCESS In blocking mode, specified AP finished before
+ the timeout expires.
+ @retval EFI_SUCCESS In non-blocking mode, the function has been
+ dispatched to specified AP.
+ @retval EFI_UNSUPPORTED A non-blocking mode request was made after the
+ UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was
+ signaled.
+ @retval EFI_UNSUPPORTED WaitEvent is not NULL if non-blocking mode is not
+ supported.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_TIMEOUT In blocking mode, the timeout expired before
+ the specified AP has finished.
+ @retval EFI_NOT_READY The specified AP is busy.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP.
+ @retval EFI_INVALID_PARAMETER Procedure is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibStartupThisAP (
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
+ );
+
+/**
+ This service switches the requested AP to be the BSP from that point onward.
+ This service changes the BSP for all purposes. This call can only be performed
+ by the current BSP.
+
+ @param[in] ProcessorNumber The handle number of AP that is to become the new
+ BSP. The range is from 0 to the total number of
+ logical processors minus 1. The total number of
+ logical processors can be retrieved by
+ MpInitLibGetNumberOfProcessors().
+ @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an
+ enabled AP. Otherwise, it will be disabled.
+
+ @retval EFI_SUCCESS BSP successfully switched.
+ @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to
+ this service returning.
+ @retval EFI_UNSUPPORTED Switching the BSP is not supported.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or
+ a disabled AP.
+ @retval EFI_NOT_READY The specified AP is busy.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibSwitchBSP (
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
+ );
+
+/**
+ This service lets the caller enable or disable an AP from this point onward.
+ This service may only be called from the BSP.
+
+ @param[in] ProcessorNumber The handle number of AP.
+ The range is from 0 to the total number of
+ logical processors minus 1. The total number of
+ logical processors can be retrieved by
+ MpInitLibGetNumberOfProcessors().
+ @param[in] EnableAP Specifies the new state for the processor for
+ enabled, FALSE for disabled.
+ @param[in] HealthFlag If not NULL, a pointer to a value that specifies
+ the new health status of the AP. This flag
+ corresponds to StatusFlag defined in
+ EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only
+ the PROCESSOR_HEALTH_STATUS_BIT is used. All other
+ bits are ignored. If it is NULL, this parameter
+ is ignored.
+
+ @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.
+ @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed
+ prior to this service returning.
+ @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber
+ does not exist.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibEnableDisableAP (
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
+ );
+
+/**
+ This return the handle number for the calling processor. This service may be
+ called from the BSP and APs.
+
+ @param[out] ProcessorNumber Pointer to the handle number of AP.
+ The range is from 0 to the total number of
+ logical processors minus 1. The total number of
+ logical processors can be retrieved by
+ MpInitLibGetNumberOfProcessors().
+
+ @retval EFI_SUCCESS The current processor handle number was returned
+ in ProcessorNumber.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibWhoAmI (
+ OUT UINTN *ProcessorNumber
+ );
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index ef46318..8674533 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -50,6 +50,10 @@ [LibraryClasses.IA32, LibraryClasses.X64]
##
SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h

+ ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
+ ##
+ MpInitLib|Include/Library/MpInitLib.h
+
[Guids]
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}

--
2.7.4.windows.1


[Patch v4 05/46] UefiCpuPkg/MpInitLib: Add two instances PeiMpInitLib and DxeMpInitLib

Jeff Fan <jeff.fan@...>
 

Add two MP Initialize Library instances PeiMpInitLib.inf and DxeMpInitLib.inf
with NULL implementation.

One PeiMpInitLib.inf is consumed by PEI MP driver. Another DxeMpInitLib.inf is
consumed by DXE MP driver.

Place MpInitLibStartupAllAPs()/MpInitLibStartupThisAp()/MpInitLibSwitchBSP()/
MpInitLibEnableDisableAP() into PeiMpLib.c and DxeMpLib.c, because they have
the different implementations and will be updated in latter patches.

v4:
1. Return EFI_UNSUPPORTED instead of EFI_SUCCESS for NULL implementation of
all Functions.
2. Sync MpInitLibxxx functions header updating described in v4 part of Patch
#4.

v3:
1. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@...>
Cc: Feng Tian <feng.tian@...>
Cc: Giri P Mudusuru <giri.p.mudusuru@...>
Cc: Laszlo Ersek <lersek@...>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@...>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@...>
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 61 ++++++++++
.../Library/MpInitLib/DxeMpInitLib.uni | 12 +-
.../MpInitLib.h => Library/MpInitLib/DxeMpLib.c} | 123 +++------------------
UefiCpuPkg/Library/MpInitLib/MpLib.c | 119 ++++++++++++++++++++
UefiCpuPkg/Library/MpInitLib/MpLib.h | 40 +++++++
.../MpInitLib/PeiMpInitLib.inf} | 65 +++--------
.../Library/MpInitLib/PeiMpInitLib.uni | 12 +-
.../MpInitLib.h => Library/MpInitLib/PeiMpLib.c} | 123 ++++-----------------
UefiCpuPkg/UefiCpuPkg.dsc | 3 +-
9 files changed, 291 insertions(+), 267 deletions(-)
create mode 100644 UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
copy MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni => UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.uni (60%)
copy UefiCpuPkg/{Include/Library/MpInitLib.h => Library/MpInitLib/DxeMpLib.c} (78%)
create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLib.c
create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLib.h
copy UefiCpuPkg/{CpuMpPei/CpuMpPei.inf => Library/MpInitLib/PeiMpInitLib.inf} (54%)
copy MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni => UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.uni (60%)
copy UefiCpuPkg/{Include/Library/MpInitLib.h => Library/MpInitLib/PeiMpLib.c} (78%)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
new file mode 100644
index 0000000..1f131c0
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -0,0 +1,61 @@
+## @file
+# MP Initialize Library instance for DXE driver.
+#
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeMpInitLib
+ MODULE_UNI_FILE = DxeMpInitLib.uni
+ FILE_GUID = B88F7146-9834-4c55-BFAC-481CC0C33736
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = MpInitLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources.common]
+ DxeMpLib.c
+ MpLib.c
+ MpLib.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ LocalApicLib
+ MemoryAllocationLib
+ HobLib
+ MtrrLib
+ CpuLib
+ UefiCpuLib
+ UefiBootServicesTableLib
+ HobLib
+
+[Guids]
+ gEfiEventExitBootServicesGuid ## CONSUMES ## Event
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOMETIMES_CONSUMES
+
diff --git a/MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.uni
similarity index 60%
copy from MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni
copy to UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.uni
index 14b3a69..99d7997 100644
--- a/MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.uni
@@ -1,5 +1,7 @@
// /** @file
-// SmmCommunicationBuffer Localized Strings and Content
+// MP Initialize Library instance for DXE driver.
+//
+// MP Initialize Library instance for DXE driver.
//
// Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
//
@@ -13,6 +15,8 @@
//
// **/

-#string STR_PROPERTIES_MODULE_NAME
-#language en-US
-"SMM Communication Buffer DXE Driver"
+
+#string STR_MODULE_ABSTRACT #language en-US "MP Initialize Library instance for DXE driver."
+
+#string STR_MODULE_DESCRIPTION #language en-US "MP Initialize Library instance for DXE driver."
+
diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
similarity index 78%
copy from UefiCpuPkg/Include/Library/MpInitLib.h
copy to UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 3e19382..46a48a4 100644
--- a/UefiCpuPkg/Include/Library/MpInitLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -1,5 +1,5 @@
/** @file
- Multiple-Processor initialization Library.
+ MP initialize support functions for DXE phase.

Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
@@ -12,82 +12,7 @@

**/

-#ifndef __MP_INIT_LIB_H__
-#define __MP_INIT_LIB_H__
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Protocol/MpService.h>
-
-/**
- MP Initialize Library initialization.
-
- This service will allocate AP reset vector and wakeup all APs to do APs
- initialization.
-
- This service must be invoked before all other MP Initialize Library
- service are invoked.
-
- @retval EFI_SUCCESS MP initialization succeeds.
- @retval Others MP initialization fails.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibInitialize (
- VOID
- );
-
-/**
- Retrieves the number of logical processor in the platform and the number of
- those logical processors that are enabled on this boot. This service may only
- be called from the BSP.
-
- @param[out] NumberOfProcessors Pointer to the total number of logical
- processors in the system, including the BSP
- and disabled APs.
- @param[out] NumberOfEnabledProcessors Pointer to the number of enabled logical
- processors that exist in system, including
- the BSP.
-
- @retval EFI_SUCCESS The number of logical processors and enabled
- logical processors was retrieved.
- @retval EFI_DEVICE_ERROR The calling processor is an AP.
- @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfEnabledProcessors
- is NULL.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibGetNumberOfProcessors (
- OUT UINTN *NumberOfProcessors, OPTIONAL
- OUT UINTN *NumberOfEnabledProcessors OPTIONAL
- );
-
-/**
- Gets detailed MP-related information on the requested processor at the
- instant this call is made. This service may only be called from the BSP.
-
- @param[in] ProcessorNumber The handle number of processor.
- @param[out] ProcessorInfoBuffer A pointer to the buffer where information for
- the requested processor is deposited.
- @param[out] HealthData Return processor health data.
-
- @retval EFI_SUCCESS Processor information was returned.
- @retval EFI_DEVICE_ERROR The calling processor is an AP.
- @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
- @retval EFI_NOT_FOUND The processor with the handle specified by
- ProcessorNumber does not exist in the platform.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibGetProcessorInfo (
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer,
- OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL
- );
+#include "MpLib.h"

/**
This service executes a caller provided function on all enabled APs.
@@ -173,7 +98,10 @@ MpInitLibStartupAllAPs (
IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL
- );
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service lets the caller get one enabled AP to execute a caller-provided
@@ -255,7 +183,10 @@ MpInitLibStartupThisAP (
IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL
- );
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service switches the requested AP to be the BSP from that point onward.
@@ -288,7 +219,10 @@ EFIAPI
MpInitLibSwitchBSP (
IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP
- );
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service lets the caller enable or disable an AP from this point onward.
@@ -326,28 +260,7 @@ MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL
- );
-
-/**
- This return the handle number for the calling processor. This service may be
- called from the BSP and APs.
-
- @param[out] ProcessorNumber Pointer to the handle number of AP.
- The range is from 0 to the total number of
- logical processors minus 1. The total number of
- logical processors can be retrieved by
- MpInitLibGetNumberOfProcessors().
-
- @retval EFI_SUCCESS The current processor handle number was returned
- in ProcessorNumber.
- @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibWhoAmI (
- OUT UINTN *ProcessorNumber
- );
-
-#endif
+ )
+{
+ return EFI_UNSUPPORTED;
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
new file mode 100644
index 0000000..12bd04e
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -0,0 +1,119 @@
+/** @file
+ CPU MP Initialize Library common functions.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "MpLib.h"
+
+
+/**
+ MP Initialize Library initialization.
+
+ This service will allocate AP reset vector and wakeup all APs to do APs
+ initialization.
+
+ This service must be invoked before all other MP Initialize Library
+ service are invoked.
+
+ @retval EFI_SUCCESS MP initialization succeeds.
+ @retval Others MP initialization fails.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibInitialize (
+ VOID
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Gets detailed MP-related information on the requested processor at the
+ instant this call is made. This service may only be called from the BSP.
+
+ @param[in] ProcessorNumber The handle number of processor.
+ @param[out] ProcessorInfoBuffer A pointer to the buffer where information for
+ the requested processor is deposited.
+ @param[out] HealthData Return processor health data.
+
+ @retval EFI_SUCCESS Processor information was returned.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
+ @retval EFI_NOT_FOUND The processor with the handle specified by
+ ProcessorNumber does not exist in the platform.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibGetProcessorInfo (
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer,
+ OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+/**
+ This return the handle number for the calling processor. This service may be
+ called from the BSP and APs.
+
+ @param[out] ProcessorNumber Pointer to the handle number of AP.
+ The range is from 0 to the total number of
+ logical processors minus 1. The total number of
+ logical processors can be retrieved by
+ MpInitLibGetNumberOfProcessors().
+
+ @retval EFI_SUCCESS The current processor handle number was returned
+ in ProcessorNumber.
+ @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibWhoAmI (
+ OUT UINTN *ProcessorNumber
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+/**
+ Retrieves the number of logical processor in the platform and the number of
+ those logical processors that are enabled on this boot. This service may only
+ be called from the BSP.
+
+ @param[out] NumberOfProcessors Pointer to the total number of logical
+ processors in the system, including the BSP
+ and disabled APs.
+ @param[out] NumberOfEnabledProcessors Pointer to the number of enabled logical
+ processors that exist in system, including
+ the BSP.
+
+ @retval EFI_SUCCESS The number of logical processors and enabled
+ logical processors was retrieved.
+ @retval EFI_DEVICE_ERROR The calling processor is an AP.
+ @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfEnabledProcessors
+ is NULL.
+ @retval EFI_NOT_READY MP Initialize Library is not initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+MpInitLibGetNumberOfProcessors (
+ OUT UINTN *NumberOfProcessors, OPTIONAL
+ OUT UINTN *NumberOfEnabledProcessors OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
new file mode 100644
index 0000000..66425d3
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -0,0 +1,40 @@
+/** @file
+ Common header file for MP Initialize Library.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MP_LIB_H_
+#define _MP_LIB_H_
+
+#include <PiPei.h>
+
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Register/LocalApic.h>
+#include <Register/Microcode.h>
+
+#include <Library/MpInitLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/LocalApicLib.h>
+#include <Library/CpuLib.h>
+#include <Library/UefiCpuLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SynchronizationLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/HobLib.h>
+
+
+#endif
+
diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
similarity index 54%
copy from UefiCpuPkg/CpuMpPei/CpuMpPei.inf
copy to UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
index 5f45662..014a248 100644
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -1,7 +1,7 @@
## @file
-# CPU driver installs CPU PI Multi-processor PPI.
+# MP Initialize Library instance for PEI driver.
#
-# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -14,12 +14,12 @@

[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = CpuMpPei
- MODULE_UNI_FILE = CpuMpPei.uni
- FILE_GUID = EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
+ BASE_NAME = PeiMpInitLib
+ MODULE_UNI_FILE = PeiMpInitLib.uni
+ FILE_GUID = B00F6090-7739-4830-B906-E0032D388987
MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = CpuMpPeimInit
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = MpInitLib|PEIM

#
# The following information is for reference only and not required by the build tools.
@@ -27,55 +27,28 @@ [Defines]
# VALID_ARCHITECTURES = IA32 X64
#

-[Sources]
- CpuMpPei.h
- CpuMpPei.c
- CpuBist.c
- Microcode.h
- Microcode.c
- PeiMpServices.h
- PeiMpServices.c
-
-[Sources.IA32]
- Ia32/MpEqu.inc
- Ia32/MpFuncs.asm
- Ia32/MpFuncs.nasm
-
-[Sources.X64]
- X64/MpEqu.inc
- X64/MpFuncs.asm
- X64/MpFuncs.nasm
+[Sources.common]
+ PeiMpLib.c
+ MpLib.c
+ MpLib.h

[Packages]
MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec

[LibraryClasses]
BaseLib
- BaseMemoryLib
- DebugLib
- HobLib
LocalApicLib
- MtrrLib
- PcdLib
- PeimEntryPoint
+ MemoryAllocationLib
+ HobLib
PeiServicesLib
- ReportStatusCodeLib
- SynchronizationLib
- TimerLib
- UefiCpuLib
+ MtrrLib
CpuLib
- CpuExceptionHandlerLib
+ UefiCpuLib
+ SynchronizationLib

[Ppis]
- gEfiPeiMpServicesPpiGuid ## PRODUCES
gEfiEndOfPeiSignalPpiGuid ## NOTIFY
- gEfiSecPlatformInformationPpiGuid ## SOMETIMES_CONSUMES
- ## SOMETIMES_CONSUMES
- ## SOMETIMES_PRODUCES
- gEfiSecPlatformInformation2PpiGuid
- gEfiVectorHandoffInfoPpiGuid ## SOMETIMES_CONSUMES

[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
@@ -86,9 +59,3 @@ [Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOMETIMES_CONSUMES

-[Depex]
- gEfiPeiMemoryDiscoveredPpiGuid
-
-[UserExtensions.TianoCore."ExtraFiles"]
- CpuMpPeiExtra.uni
-
diff --git a/MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.uni
similarity index 60%
copy from MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni
copy to UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.uni
index 14b3a69..d16f306 100644
--- a/MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferExtraDxe.uni
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.uni
@@ -1,5 +1,7 @@
// /** @file
-// SmmCommunicationBuffer Localized Strings and Content
+// MP Initialize Library instance for PEI driver.
+//
+// MP Initialize Library instance for PEI driver.
//
// Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
//
@@ -13,6 +15,8 @@
//
// **/

-#string STR_PROPERTIES_MODULE_NAME
-#language en-US
-"SMM Communication Buffer DXE Driver"
+
+#string STR_MODULE_ABSTRACT #language en-US "MP Initialize Library instance for PEI driver."
+
+#string STR_MODULE_DESCRIPTION #language en-US "MP Initialize Library instance for PEI driver."
+
diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
similarity index 78%
copy from UefiCpuPkg/Include/Library/MpInitLib.h
copy to UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3e19382..a7e9fb8 100644
--- a/UefiCpuPkg/Include/Library/MpInitLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -1,5 +1,5 @@
/** @file
- Multiple-Processor initialization Library.
+ MP initialize support functions for PEI phase.

Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
@@ -12,82 +12,7 @@

**/

-#ifndef __MP_INIT_LIB_H__
-#define __MP_INIT_LIB_H__
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Protocol/MpService.h>
-
-/**
- MP Initialize Library initialization.
-
- This service will allocate AP reset vector and wakeup all APs to do APs
- initialization.
-
- This service must be invoked before all other MP Initialize Library
- service are invoked.
-
- @retval EFI_SUCCESS MP initialization succeeds.
- @retval Others MP initialization fails.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibInitialize (
- VOID
- );
-
-/**
- Retrieves the number of logical processor in the platform and the number of
- those logical processors that are enabled on this boot. This service may only
- be called from the BSP.
-
- @param[out] NumberOfProcessors Pointer to the total number of logical
- processors in the system, including the BSP
- and disabled APs.
- @param[out] NumberOfEnabledProcessors Pointer to the number of enabled logical
- processors that exist in system, including
- the BSP.
-
- @retval EFI_SUCCESS The number of logical processors and enabled
- logical processors was retrieved.
- @retval EFI_DEVICE_ERROR The calling processor is an AP.
- @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfEnabledProcessors
- is NULL.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibGetNumberOfProcessors (
- OUT UINTN *NumberOfProcessors, OPTIONAL
- OUT UINTN *NumberOfEnabledProcessors OPTIONAL
- );
-
-/**
- Gets detailed MP-related information on the requested processor at the
- instant this call is made. This service may only be called from the BSP.
-
- @param[in] ProcessorNumber The handle number of processor.
- @param[out] ProcessorInfoBuffer A pointer to the buffer where information for
- the requested processor is deposited.
- @param[out] HealthData Return processor health data.
-
- @retval EFI_SUCCESS Processor information was returned.
- @retval EFI_DEVICE_ERROR The calling processor is an AP.
- @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
- @retval EFI_NOT_FOUND The processor with the handle specified by
- ProcessorNumber does not exist in the platform.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibGetProcessorInfo (
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer,
- OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL
- );
+#include "MpLib.h"

/**
This service executes a caller provided function on all enabled APs.
@@ -173,7 +98,10 @@ MpInitLibStartupAllAPs (
IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL
- );
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service lets the caller get one enabled AP to execute a caller-provided
@@ -255,7 +183,10 @@ MpInitLibStartupThisAP (
IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL
- );
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service switches the requested AP to be the BSP from that point onward.
@@ -287,8 +218,11 @@ EFI_STATUS
EFIAPI
MpInitLibSwitchBSP (
IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
- );
+ IN BOOLEAN EnableOldBSP
+ )
+{
+ return EFI_UNSUPPORTED;
+}

/**
This service lets the caller enable or disable an AP from this point onward.
@@ -326,28 +260,9 @@ MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL
- );
-
-/**
- This return the handle number for the calling processor. This service may be
- called from the BSP and APs.
+ )
+{
+ return EFI_UNSUPPORTED;
+}

- @param[out] ProcessorNumber Pointer to the handle number of AP.
- The range is from 0 to the total number of
- logical processors minus 1. The total number of
- logical processors can be retrieved by
- MpInitLibGetNumberOfProcessors().
-
- @retval EFI_SUCCESS The current processor handle number was returned
- in ProcessorNumber.
- @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
- @retval EFI_NOT_READY MP Initialize Library is not initialized.
-
-**/
-EFI_STATUS
-EFIAPI
-MpInitLibWhoAmI (
- OUT UINTN *ProcessorNumber
- );

-#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index b35f41b..598c797 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -114,7 +114,8 @@ [Components.IA32, Components.X64]
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
- UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+ UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
--
2.7.4.windows.1