Microvm has no TPM support. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd Hoffmann <kraxel@...> Reviewed-by: Stefan Berger <stefanb@...> Acked-by:

Guests depending on BIOS will probably not work that well with microvm due to legacy hardware being not available. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd

Microvm has no SEV support. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd Hoffmann <kraxel@...> Acked-by: Jiewen Yao <Jiewen.yao@...> ---

Without SMM secure boot isn't actually secure, so drop it too. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd Hoffmann <kraxel@...> Acked-by: Jiewen Yao

Microvm has no SMM support. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599 Signed-off-by: Gerd Hoffmann <kraxel@...> Acked-by: Jiewen Yao <Jiewen.yao@...> ---

Create Microvm subdirectory. Copy OvmfPkgX64 .dsc and .fdf files unmodified as starting point for MicrovmX64. Changes come as separate patches, to simplify patch review and rebases. Ref:

Rename the firmware volume files (s/OVMF/MICROVM/). Fix includes so they work with microvm config being in a subdirectory. With this patch applied the build works. Ref:

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more

Reviewed-by: Leif Lindholm <leif@...>

I was not sure how TDX is approaching the validation in the SEC phase; i.e, will it go with validating the entire guest RAM at once or validate the selective portion then push everything to PEI or DXE

The SEC begins with a fixed GHCB page; During the PEI phase, we allocate and switch to new per-CPU GHCB page and thus need to registration for the new GHCB. Please see the

Sure, I will add comment. thanks

Yep, looking at the current TDX patches we see that GHCB is used for the mailbox,  to make integration easy its good idea that we define SEV_SECTION_TYPE_SEC_MEM and use it for those GHCB memory

Err, actually, no. You cannot give sign-off for Vu, but you need to sign off for yourself. So we will need a v4. If this patch in that set contains your Signed-off-by, and no-one elses, that can

Noted. thanks

Reviewed-by: Rebecca Cran <rebecca@...> -- Rebecca Cran

Reviewed-by: Leif Lindholm <leif@...>

Hi Nhi, + the added common functions in EmbeddedPkg AcpiLib. This feedback is a bit oversimplified. There is an entirely new Ac01PcieLib component - which I could quickly tell because the NOOPT

Hi, https://github.com/tianocore/edk2/pull/1979 detected errors. Can you check and update a new patch to fix? Thanks, Ray

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3621 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3631 Current CPU feature initialization design: During normal boot, CpuFeaturesPei