Can we define PAM register for CloudHv as well - DRAMC_REGISTER_Q35 (MCH_PAM0)? @@ -77,6 +77,8 @@ STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = { {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20}

Reviewed-by: Gerd Hoffmann <kraxel@...>

Hi Pierre, I have addressed all the suggested changes and posted v3 version of patches. I tried to do this, but unfortunately wasn't successful. We are reusing the standard version of PciExpressLib.c

On Tue, Nov 30, 2021 at 09:06 AM, PierreGondois wrote: Hi Pierre, Hi Khasim, On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: This patch enables CCIX root complex support by updating the root

This patch enables CCIX root complex support by updating the root complex node info in PciHostBridge library and enabling PciSegment library for N1Sdp. Change-Id:

The BasePCISegment Library in MdePkg doesn't allow configuring multiple segments required for PCIe and CCIX root port enumeration. Therefore, a custom PCI Segment library is adapted from

Update the PciExpressLib to enable CCIX port as PCIe root host by validating the PCIe addresses and introducing corresponding PCD entries. Change-Id:

The patch series enables CCIX port as PCIe root on N1SDP. V3: - The conditional logic in GetPciExpressAddress is made simple. - Removed few more PCD entries that were unused. - Removed hardcoded

From: Sebastien Boeuf <sebastien.boeuf@...> Adding support for retrieving the Cloud Hypervisor ACPI tables as a fallback mechanism if tables are not found through fw_cfg. Reviewed-by: Gerd

From: Sebastien Boeuf <sebastien.boeuf@...> Don't make the package Qemu centric so that we can introduce some alternative support for other VMMs not using the fw_cfg mechanism. This patch is

From: Sebastien Boeuf <sebastien.boeuf@...> Add a fallback on the SMBIOS code to find the SMBIOS table for Cloud Hypervisor if it couldn't be found for Qemu through fw_cfg. Reviewed-by: Gerd

From: Sebastien Boeuf <sebastien.boeuf@...> Move the generic entry point part out of Qemu.c to anticipate the addition of new ways of retrieving the SMBIOS table. Reviewed-by: Gerd Hoffmann

From: Sebastien Boeuf <sebastien.boeuf@...> Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Signed-off-by: Rob Bradford

From: Sebastien Boeuf <sebastien.boeuf@...> This series aims at adding the support for the Cloud Hypervisor platform to the OVMF firmware for x86 architecture. The goal is to allow the same

Christine: I add my comments below. This is the expected behavior. Edk2 implementation places AP reset vector into the first 16 bytes in SEC FV. GenFv tool has the logic to rebase PEIM on its

Mike: I have no comments for these changes. For MdePkg, MdeModulePkg, FmpDevicePkg, Reviewed-by: Liming Gao <gaoliming@...> Thanks Liming

Hi Liming, Need your helps on the first and third issues: 1. As the PI spec defined, for Fv Header "The first 16 bytes are reserved to allow for the reset vector of processors whose reset vector is

Reviewed-by: Gerd Hoffmann <kraxel@...>

Reviewed-by: Gerd Hoffmann <kraxel@...>

Reviewed-by: Gerd Hoffmann <kraxel@...>