Is below code right? + case CLOUDHV_DEVICE_ID: mRegisterValues = mRegisterValuesQ35; + case CLOUDHV_DEVICE_ID: mLegacyInterruptDevice = LEGACY_INT_DEV_Q35; I am not sure if it is

Reminder: TianoCore Design Meeting - APAC/NAMO When: 12/10/2021 9:30am to 10:30am (UTC+08:00) Asia/Shanghai Where: Microsoft Teams Organizer: Ray Ni ray.ni@... View

From: Sebastien Boeuf <sebastien.boeuf@...> Adding support for retrieving the Cloud Hypervisor ACPI tables as a fallback mechanism if tables are not found through fw_cfg. Signed-off-by: Rob

From: Sebastien Boeuf <sebastien.boeuf@...> Don't make the package Qemu centric so that we can introduce some alternative support for other VMMs not using the fw_cfg mechanism. This patch is

From: Sebastien Boeuf <sebastien.boeuf@...> Add a fallback on the SMBIOS code to find the SMBIOS table for Cloud Hypervisor if it couldn't be found for Qemu through fw_cfg. Signed-off-by: Rob

From: Sebastien Boeuf <sebastien.boeuf@...> Move the generic entry point part out of Qemu.c to anticipate the addition of new ways of retrieving the SMBIOS table. Signed-off-by: Sebastien

From: Sebastien Boeuf <sebastien.boeuf@...> Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Signed-off-by: Rob Bradford

From: Sebastien Boeuf <sebastien.boeuf@...> This series aims at adding the support for the Cloud Hypervisor platform to the OVMF firmware for x86 architecture. The goal is to allow the same

Make sure the base address and length of the Raspberry Pi miniuart set in the ACPI tables match those in the official device tree. This will be useful for adding ACPI support to the miniuart Linux

Morello SoC platform support has added and also boot flow modified to reflect the new boot flow for both Morello FVP and Morello SoC platforms Signed-off-by: Chandni Cherukuri

From: sah01 <sahil@...> Support has been added to parse NT_FW_CONFIG DTB to get the platform information. Signed-off-by: sahil <sahil@...> Signed-off-by: Chandni Cherukuri

From: Anurag Koul <anurag.koul@...> This commit adds: - SSDT, MCFG table for PCIe and CCIX RC nodes - IORT nodes bindings for PCIe/CCIX and the associated ITSs and SMMUs in the Configuration

From: Anurag Koul <anurag.koul@...> Add definitions for both PCIe and CCIX Root Complex in PciHostBridge Library. Also, use platform-specific PCI Segment Library and PCI Express Library to enable

From: Anurag Koul <anurag.koul@...> Morello platform requires a custom platform-specific PCI Express library because the native PCI Express Library only allows for a single ECAM config address to

From: Anurag Koul <anurag.koul@...> A custom PCI Segment library is required to handle multiple PCIe segments in Morello, as the base PCI Segment library doesn't allow supporting more than a

This patch adds initial support for Morello SoC platform. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...> --- Platform/ARM/Morello/MorelloPlatform.dsc.inc | 27 +-

This patch adds PlatformDxe support for Morello SoC platform. It includes the registration of ramdisk device. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...> ---

PlatformLibMem.c file is going to be different for Morello FVP and Morello SoC platforms since the virtual memory mapping is different so the file PlatformLibMem.c is renamed as PlatformLibMemFvp.c

This patch implements the configuration manager for Morello SoC platform. It enables support for generating the following ACPI tables for Morello SoC Platform: 1. FADT 2.

It includes virutal memory map for Morello SoC platform. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...> --- Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf | 44 +++++