Hi Eric, I added EFIAPI as the function is now intended to be called externally, as a member of "LocalApicLib". And to that end I added the function prototype in

From: Marc-André Lureau <marcandre.lureau@...> Matches TPM 2.0 commit 3103389043bd ("OvmfPkg: Add TCG2 Configuration menu to the Device Manager menu", 2019-02-11). Signed-off-by: Marc-André

From: Marc-André Lureau <marcandre.lureau@...> Mirrors TPM 2.0 commit d5a002aba0aa ("OvmfPkg: plug DxeTpm2MeasureBootLib into SecurityStubDxe", 2018-03-09) Signed-off-by: Marc-André Lureau

From: Marc-André Lureau <marcandre.lureau@...> A following patch is going to use the same configuration for TPM1.2 and TPM2.0, and it's simpler to support both than

From: Marc-André Lureau <marcandre.lureau@...> Hi, The following patches add basic TPM 1.2 support for Ovmf/QEMU. Tested successfully Win10 with TIS/TPM 1.2 & CRB/TPM 2.0 passthrough, and

Indeed I noticed that too. I figured this change -- moving the code around, beyond purely making it public -- was intentional. I assumed the new position of the function within the source code made

Cache maintenance on ARMv7 systems and up should be done by virtual address if the purpose is to manage the cached state of contents of memory. Set/way operations are only intended to maintain the

The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate

In the AARCH64 version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even

In the ARM version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if

Unlike the AArch64 implementation of ArmMmuLib, which combines the initial page table population code with the code that runs at later stages to manage permission attributes in the page tables, ARM

Make the CONSTRUCTOR define in the .INF AARCH64 only, so we can drop the empty stub that exists for ARM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...> ---

As it turns out, there were still some instances of set/way ops left in the core code, in ArmMmuLib to be precise. This series fixes ArmMmuLib to perform the appropriate cache invalidation when

Hi Andrew, With live migration, the running guest doesn't notice anything. This is a general requirement for live migration (regardless of UEFI or flash). You are very correct to ask about

Hi Prince, Please see my comments below inline.

Please add BZ in commit message, with this update: Reviewed-by: Chasel Chiu <chasel.chiu@...>

Leo: Now, we enter into Hard Feature Freeze phase until edk2-stable202002 tag is created at 2020-02-28. Only critical bug fix is still allowed. Do you request to catch this fix into this stable

Leo, You are saying that PlatformId MSR access is not performed by CPU in old code because of the zero size uCode. But now with Hao or Siyuan's change, the PlatformId MSR access is always performed

Acked-by: Siyuan Fu <siyuan.fu@...>

+ Hao Wu and Siyuan Fu for review.