Add a new device entry in the SSDT ACPI table to describe the serial port used as the debug port. On the Neoverse reference design platforms, the UART0 port of the SoC is used as the debug

Patch 433b5b1b0f7f ("Platform/Sgi: Route logs to different sets of consoles") assigns different address for the console UART and the debug UART. Correspondingly, update the SPCR and SSDT ACPI tables

Patch 433b5b1b0f7f ("Platform/Sgi: Route logs to different sets of consoles") setup the routing of console messages to a different set of UART ports. Following up with this change, this patch series

This problem has been fixed in edk2 20b292d0cdf7dce58d824fdf9ab1613c2a1ad2ec * BaseTools: Fix the issue caused by tostring() removal on Py39 REF:

The goal is to have a Drbg and its advantages: - Reproducibility - A Drbg is supposed to be faster than a Trng - Just have a Drbg when there is none Arm (resp. Intel) has specific instructions to get

Yes right, there would be indeed no dependency between the MdePkg and ArmPkg, the above case is perfectly correct. To continue the discussion on one thread, please see the answer

Depends on whenever the system has a serial console or not ... ConSplitterDxe uses the intersection of all outputs as final list of supported text modes. 80x50? take care, Gerd

Hi Would anyone have any suggestions on getting the Front Page to fill the screen? As far as I can see, configuring the below PCDs should allow it to fill the screen - which is being correctly

Hello Jeff, I think it would ideally be better to have the code adding/replacing the methods/objects you noted inside the edk2/edk2-platfoms repositories. The methods/objects that you want to replace

Hello Jeff, I understand that since the _UID value is generated, it is not possible for an external module to guess its value. However, the pcd (and the case you detailed) seem to be really

Hook up PCIE_BASE to PcdPciExpressBaseAddress Cc: Ray Ni <ray.ni@...> Cc: Maurice Ma <maurice.ma@...> Cc: Benjamin You <benjamin.you@...> Signed-off-by: Sean Rhodes

1. Is there a configuration that both GENERIC and NULL memory test is FALSE? If no, can we add a macro like "MEMORY_TEST" and its value could be "GENERIC" or "NULL"? 2. AtaAtapiPassThru also

Reviewed-by: Yuwei Chen<yuwei.chen@...>

Reviewed-by: Yuwei Chen<yuwei.chen@...>

Reviewed-by: Yuwei Chen<yuwei.chen@...>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3923 According to definition of PcdTpm2HashMask, the mask reflects the PCR banks which need to be extended. In the Tcg2Pei

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3923 According to definition of PcdTpm2HashMask, the mask reflects the PCR banks which need to be extended. In the Tcg2Pei

Thanks Ard, this was due to an actual failure that was a bit of a challenge to debug. A test in the ARM SBSA test suite installs the ISR first (which enables the interrupt) and then calls in to

The issue appears to have been introduced by: 41fb5d46 : ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3 The changes to ArmGicIsInterruptEnabled() introduced the error

Hello, I’ve encountered error during building Qualcomm deilivery with information to write an email to you. Please, see logs in attachment. Pozdrawiam/Kind Regards Fryderyk