From: Vu Nguyen <vunguyen@...> The DwGpioLib library provides basic functions to control the GPIO controller on Ampere Altra processor. Cc: Chuong Tran

From: Vu Nguyen <vunguyen@...> The DwI2cLib library provides basic functions to control the I2C controller on Ampere Altra processor. Cc: Chuong Tran

The FailSafeDxe is a driver for the FailSafe feature which reverts the system's configuration to known good values if the system fails to boot up multiple times. Also, this driver implements the

From: Vu Nguyen <vunguyen@...> This commit adds the support for Ampere’s Altra processor-based Mt. Jade platform that provides up to 160 processor cores in a dual

The Ampere Altra System Firmware provides a fail-safe feature to help recover the system if there are setting changes such as Core voltage, DRAM parameters that cause the UEFI failed to boot. The

From: Vu Nguyen <vunguyen@...> The MmCommunicationDxe module is derived from ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf. The MmCommunication PEI and DXE modules

This patch series adds the support for the Mt. Jade platform based on Ampere's Altra Family Processor. Notes: + The current patch series was tested with the edk2-stable202108 tag. + The IASL

Well that's a large number of conflicts. I find it unprofessional that I have been waiting over a month for a MinPlatformPkg maintainer to review and merge my patch while the patches that were merged

Should we consider this workaround? I’m having issues interpreting this part of PCIe spec. My understanding of this quote is that this capability can exist in but it shouldn’t be considered. I

According to SMBIOS 3.4, section 7.5.3.3 ARM64-class CPUs, if SMCCC_ARCH_SOC_ID is supported, the first DWORD is the JEP-106 code and the second DWORD is the SoC revision value. But in the

Extending PciBus to support such case is valid. But can you check if there is other pure software way to detect whether it’s an ECiEP?

Hi To avoid unnecessary change in DSC/FDF, can we change default size to be 4 in DEC? gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51 We shall also add comment on

Reviewed-by: Barton Gao <gaojie@...> Thanks Barton -----邮件原件----- 发件人: bounce+27952+68636+5325328+9289841@groups.io <bounce+27952+68636+5325328+9289841@groups.io> 代表

Reviewed-by: Ray Ni <ray.ni@...>

SEC phase will throw an assertion in IsSevGuest if PcdOvmfConfidentialComputingWorkAreaHeader doesn't match the sizeof CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER. Signed-off-by: Corvin Köhne

Hi Ray, There are only "UniversalPayloadEntry.inf" and "UefiPayloadEntry.inf" under [Components.IA32] in UefiPayloadPkg.dsc. The [Packages] sections in these two .inf file only contain MdePkg,

[edk2-devel] [PATCH V5] REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when

[edk2-devel] [PATCH V5] REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when

Hi, Liming TD Protocol is defined in below spec (Section 4.3.2) https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-guest-hypervisor-communication-interface.pdf This

Min: Which public spec defines this new protocol? Thanks Liming structure 0xae, logged. shall be the 1 1