From: Tom Lendacky <thomas.lendacky@...> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3275 Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled in the guest VM. See

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces advertisement of features that are supported by the hypervisor. See the GHCB spec section 2.2 for an additional

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of the GHCB spec introduces several new SNP-specific NAEs. Unfortunately, the names for those NAEs break the alignment. Add

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 An SEV-SNP guest is required to perform the GHCB GPA registration. See the GHCB specification for further details. Cc: Min Xu

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: Min Xu <min.m.xu@...> Cc: Tom Lendacky <thomas.lendacky@...> Cc: Ard Biesheuvel

This series is taken from the SNP RFC. This series defines the GHCBv2 macros and NAE events. Additionally, it also introduces a helper to clear the page encryption mask from the Mmio region. The

I am going to drop the Mmio hunk from this patch to make it sane. I was thinking ahead for the SEV-SNP support; For SEV and ES support, the SetMemoryEncDec() does not need to know whether its called

The changes are upstreamed by commit-id : https://github.com/tianocore/edk2-test/commit/2821093d6f2b3521c453834f0657cf07c0908155

Hi Grant, There is already a repo like this in tianocore: https://github.com/tianocore/edk2-edkrepo-manifest It is focused on manifests used by the edkrepo

As I said before, I am fine with this patch, but I would still like to understand why this causes a failure. The device limit is used by the DMA layer to decide whether bounce buffering is needed or

Would it be possible to get a new repo under the github.com/tianocore project? I've got a repo manifest that I've been using for building the SCT, and is now being used by quite a few people. However

Thanks Pete. I have pushed these 2 patches as e1efa61c33f7..09c5ab125b61 with the above suggestion applied.

Reviewed-by: Pete Batard <pete@...>

Two minor notes below: Even if the code makes it clear that we're testing the chip revision to decide what region to return, I would prefer if we had "for pre C0 revisions of the SoC" instead of "for

For anyone having this issue,the below patch detects the error in PciHostBridge aperture, from 9elements github repository:

Hi Etienn, Thank you for this patch. These changes look good to me. Reviewed-by: Sami Mujawar <sami.mujawar@...> Regards, Sami Mujawar IMPORTANT NOTICE: The contents of this email and any

Hi Etienn, Thank you for this patch. Please find my feedback inline marked [SAMI] . With those fixed. Reviewed-by: Sami Mujawar <sami.mujawar@...> Regards, Sami Mujawar [SAMI] I think

Hi Etienne, I have some minor suggestion marked inline as [SAMI]. With that addressed. Reviewed-by: Sami Mujawar <sami.mujawar@...> Regards, Sami Mujawar [SAMI] Is it possible to change the

Hi Etienne, Thank you for this patch. I would have prefered this patch split in 3 parts (for SgiPkg, Socionext and Platform/StandaloneMm). In either case the changes look good to me. Reviewed-by:

Hello Sami, Thanks for the comments. I'll address them in v2 if this series. Regards, Etienne I am using gcc 9.2 cross toolchain prebuilt by Arm (arm-linux-none-gnueabihf, 19dec2019)