REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 The security researcher found that we can get control after NEM disable. The reason is that the flash content reside in NEM at startup and

The TOCTOU vulnerability allow that the physical present person to replace the code with the normal BootGuard check and PCR0 value. The issue occur when BootGuard measure IBB and access flash code

Will fix this commit in v2. Thanks, Gary Lin

Will fix it. Oops. Will fix it. Ok, will add an assert for MaxLun. Will fix them in v2. Ok. Will remove DUAL_ADDRESS_CYCLE. Urghhh, it should be "jump to 7". LSI_INS_TC_RA stands for

From: Pankaj Bansal <pankaj.bansal@...> This patch adds the Support for printing the git commit information in linux build environment. Ideal place of retrieving this information should be

From: Pankaj Bansal <pankaj.bansal@...> Some NXP SOCs have some specialized IP blocks (like MC), which require DDR memory to operate. This DDR memory should not be managed by OS or

From: Pankaj Bansal <pankaj.bansal@...> For DXE_RUNTIME_DRIVER runtime safe version of DebugLib should be used. Otherwise, any DEBUG print in code can result in abort in OS. Signed-off-by:

From: Pankaj Bansal <pankaj.bansal@...> This patch series adds some useful features to NXP platforms. - runtime safe version of DebugLib - Add support for reserving a chunk from RAM - Add Support

From: Pankaj Bansal <pankaj.bansal@...> Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by: Pankaj Bansal <pankaj.bansal@...> Reviewed-by: Leif Lindholm

From: Pankaj Bansal <pankaj.bansal@...> LS1046A Freeway (FRWY) is a high-performance development platform that supports the QorIQ LS1046A Layerscape Architecture SOCs. Co-authored-by: Pramod

From: Pankaj Bansal <pankaj.bansal@...> LS1046A is QorIq Layerscape multicore communications processor with four Arm Cortex-A72 cores. This SOC is based on Layerscape Chassis v2. Co-authored-by:

From: Pankaj Bansal <pankaj.bansal@...> For LS1043A SOC the DCFG registers are read in big endian format. After Reading the registers in code we have the registers in Little Endian Bit format

From: Pankaj Bansal <pankaj.bansal@...> RCW bits parsing and their interpretation varies between various SOCs. Add the comments that explain this parsing scheme. Based on this explanation, fix

From: Pankaj Bansal <pankaj.bansal@...> The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance development platform that supports the QorIQ LS1046A architecture processor. The

Correct some typos. Cc: Ray Ni <ray.ni@...> Cc: Laszlo Ersek <lersek@...> Cc: Rahul Kumar <rahul1.kumar@...> Signed-off-by: Guomin Jiang <guomin.jiang@...> ---

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 To avoid the TOCTOU, enable paging and set Not Present flag so when access any code in the flash range, it will trigger #NP exception. Cc: Ray

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 When we allocate pool to save rebased the PEIMs, the address will change randomly, therefore the hash will change and result PCR0 change as

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 When we allocate pool to save the rebased PEIMs, the address will change randomly, therefore the hash will change and result PCR0 change as

From: Michael Kubacki <michael.a.kubacki@...> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 Adds a PEIM that republishes structures produced in SEC. This is done because SEC modules

From: Michael Kubacki <michael.a.kubacki@...> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 Moves the GDT and IDT to permanent memory in a memory discovered callback. This is done to