Date   

Event: TianoCore Community Meeting - EMEA / NAMO - 01/13/2022 #cal-reminder

devel@edk2.groups.io Calendar <noreply@...>
 

Reminder: TianoCore Community Meeting - EMEA / NAMO

When:
01/13/2022
9:00am to 10:00am
(UTC-08:00) America/Los Angeles

Where:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_N2UyMTVhZjUtOTk3Ni00MmI0LTg0NmItNzIwYTkyMGJhYzNh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%22b286b53a-1218-4db3-bfc9-3d4c5aa7669e%22%7d

Organizer: Soumya Guptha

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Description:

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Video Conference ID: 111 422 379 4

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Event: TianoCore Community Meeting - EMEA / NAMO - 01/13/2022 #cal-reminder

devel@edk2.groups.io Calendar <noreply@...>
 

Reminder: TianoCore Community Meeting - EMEA / NAMO

When:
01/13/2022
9:00am to 10:00am
(UTC-08:00) America/Los Angeles

Where:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_N2UyMTVhZjUtOTk3Ni00MmI0LTg0NmItNzIwYTkyMGJhYzNh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%22b286b53a-1218-4db3-bfc9-3d4c5aa7669e%22%7d

Organizer: Soumya Guptha

View Event

Description:

Microsoft Teams meeting

Join on your computer or mobile app

Click here to join the meeting

Join with a video conferencing device

teams@...

Video Conference ID: 111 422 379 4

Alternate VTC dialing instructions

Or call in (audio only)

+1 916-245-6934,,482062805#   United States, Sacramento

Phone Conference ID: 482 062 805#

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[PATCH v3 3/3] DynamicTablesPkg: Add AmlCodeGenMethodRetInteger function

Rebecca Cran
 

Add AmlCodeGenMethodRetInteger function to generate AML code for
a Method returning an Integer.

Signed-off-by: Rebecca Cran <quic_rcran@...>
Reviewed-by: Pierre Gondois <pierre.gondois@...>
---
DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h | 47 ++++++
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c | 156 ++++++++++++++++++++
2 files changed, 203 insertions(+)

diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
index 80d05f74ee69..6f214c0dfad2 100644
--- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
+++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
@@ -1118,6 +1118,53 @@ AmlCodeGenMethodRetNameString (
OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL
);

+/** AML code generation for a method returning an Integer.
+
+ AmlCodeGenMethodRetInteger (
+ "_CBA", 0, 1, TRUE, 3, ParentNode, NewObjectNode
+ );
+ is equivalent of the following ASL code:
+ Method(_CBA, 1, Serialized, 3) {
+ Return (0)
+ }
+
+ The ASL parameters "ReturnType" and "ParameterTypes" are not asked
+ in this function. They are optional parameters in ASL.
+
+ @param [in] MethodNameString The new Method's name.
+ Must be a NULL-terminated ASL NameString
+ e.g.: "MET0", "_SB.MET0", etc.
+ The input string is copied.
+ @param [in] ReturnedInteger The value of the integer returned by the
+ method.
+ @param [in] NumArgs Number of arguments.
+ Must be 0 <= NumArgs <= 6.
+ @param [in] IsSerialized TRUE is equivalent to Serialized.
+ FALSE is equivalent to NotSerialized.
+ Default is NotSerialized in ASL spec.
+ @param [in] SyncLevel Synchronization level for the method.
+ Must be 0 <= SyncLevel <= 15.
+ Default is 0 in ASL.
+ @param [in] ParentNode If provided, set ParentNode as the parent
+ of the node created.
+ @param [out] NewObjectNode If success, contains the created node.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenMethodRetInteger (
+ IN CONST CHAR8 *MethodNameString,
+ IN UINT64 ReturnedInteger,
+ IN UINT8 NumArgs,
+ IN BOOLEAN IsSerialized,
+ IN UINT8 SyncLevel,
+ IN AML_NODE_HANDLE ParentNode OPTIONAL,
+ OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL
+ );
+
/** Create a _LPI name.

AmlCreateLpiNode ("_LPI", 0, 1, ParentNode, &LpiNode) is
diff --git a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
index 838a892c6b58..07822ead5b70 100644
--- a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
+++ b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
@@ -1685,6 +1685,61 @@ exit_handler:
return Status;
}

+/** AML code generation for a Return object node,
+ returning an Integer.
+
+ AmlCodeGenReturn (0), ParentNode, NewObjectNode) is
+ equivalent of the following ASL code:
+ Return (0)
+
+ The ACPI 6.3 specification, 20.2.8 "Statement Opcodes Encoding" states:
+ DefReturn := ReturnOp ArgObject
+ ReturnOp := 0xA4
+ ArgObject := TermArg => DataRefObject
+
+ Thus, the ReturnNode must be evaluated as a DataRefObject.
+
+ The ReturnNode must be generated inside a Method body scope.
+
+ @param [in] Integer The integer is returned by the Return
+ ASL statement.
+ @param [in] ParentNode If provided, set ParentNode as the parent
+ of the node created.
+ Must be a MethodOp node.
+ @param [out] NewObjectNode If success, contains the created node.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+AmlCodeGenReturnInteger (
+ IN UINT64 Integer,
+ IN AML_NODE_HEADER *ParentNode OPTIONAL,
+ OUT AML_OBJECT_NODE **NewObjectNode OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ AML_OBJECT_NODE *IntNode;
+
+ IntNode = NULL;
+
+ Status = AmlCodeGenInteger (Integer, &IntNode);
+ ASSERT_EFI_ERROR (Status);
+
+ // AmlCodeGenReturn() deletes DataNode if error.
+ Status = AmlCodeGenReturn (
+ (AML_NODE_HEADER *)IntNode,
+ ParentNode,
+ NewObjectNode
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
/** AML code generation for a method returning a NameString.

AmlCodeGenMethodRetNameString (
@@ -1793,6 +1848,107 @@ error_handler:
return Status;
}

+/** AML code generation for a method returning an Integer.
+
+ AmlCodeGenMethodRetInteger (
+ "_CBA", 0, 1, TRUE, 3, ParentNode, NewObjectNode
+ );
+ is equivalent of the following ASL code:
+ Method(_CBA, 1, Serialized, 3) {
+ Return (0)
+ }
+
+ The ASL parameters "ReturnType" and "ParameterTypes" are not asked
+ in this function. They are optional parameters in ASL.
+
+ @param [in] MethodNameString The new Method's name.
+ Must be a NULL-terminated ASL NameString
+ e.g.: "MET0", "_SB.MET0", etc.
+ The input string is copied.
+ @param [in] ReturnedInteger The value of the integer returned by the
+ method.
+ @param [in] NumArgs Number of arguments.
+ Must be 0 <= NumArgs <= 6.
+ @param [in] IsSerialized TRUE is equivalent to Serialized.
+ FALSE is equivalent to NotSerialized.
+ Default is NotSerialized in ASL spec.
+ @param [in] SyncLevel Synchronization level for the method.
+ Must be 0 <= SyncLevel <= 15.
+ Default is 0 in ASL.
+ @param [in] ParentNode If provided, set ParentNode as the parent
+ of the node created.
+ @param [out] NewObjectNode If success, contains the created node.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenMethodRetInteger (
+ IN CONST CHAR8 *MethodNameString,
+ IN UINT64 ReturnedInteger,
+ IN UINT8 NumArgs,
+ IN BOOLEAN IsSerialized,
+ IN UINT8 SyncLevel,
+ IN AML_NODE_HANDLE ParentNode OPTIONAL,
+ OUT AML_OBJECT_NODE_HANDLE *NewObjectNode OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ AML_OBJECT_NODE_HANDLE MethodNode;
+
+ if ((MethodNameString == NULL) ||
+ ((ParentNode == NULL) && (NewObjectNode == NULL)))
+ {
+ ASSERT (0);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Create a Method named MethodNameString.
+ Status = AmlCodeGenMethod (
+ MethodNameString,
+ NumArgs,
+ IsSerialized,
+ SyncLevel,
+ NULL,
+ &MethodNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenReturnInteger (
+ ReturnedInteger,
+ (AML_NODE_HANDLE)MethodNode,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ goto error_handler;
+ }
+
+ Status = LinkNode (
+ MethodNode,
+ ParentNode,
+ NewObjectNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ goto error_handler;
+ }
+
+ return Status;
+
+error_handler:
+ if (MethodNode != NULL) {
+ AmlDeleteTree ((AML_NODE_HANDLE)MethodNode);
+ }
+
+ return Status;
+}
+
/** Create a _LPI name.

AmlCreateLpiNode ("_LPI", 0, 1, ParentNode, &LpiNode) is
--
2.31.1


[PATCH v3 2/3] DynamicTablesPkg: Remove redundant cast in AmlCodeGenReturn

Rebecca Cran
 

In AmlCodeGenReturn, the cast to AML_NODE_HEADER* in the call to
AmlSetFixedArgument is redundant because ReturnNode is already a
AML_NODE_HEADER* .

Signed-off-by: Rebecca Cran <quic_rcran@...>
Reviewed-by: Pierre Gondois <pierre.gondois@...>
---
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
index d245848ce3fa..838a892c6b58 100644
--- a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
+++ b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c
@@ -1564,7 +1564,7 @@ AmlCodeGenReturn (
Status = AmlSetFixedArgument (
ObjectNode,
EAmlParseIndexTerm0,
- (AML_NODE_HEADER *)ReturnNode
+ ReturnNode
);
if (EFI_ERROR (Status)) {
ASSERT (0);
--
2.31.1


[PATCH v3 1/3] DynamicTablesPkg: Add Memory32Fixed function

Rebecca Cran
 

Add a Memory32Fixed function to generate code for the corresponding
Memory32Fixed macro in AML.

Signed-off-by: Rebecca Cran <quic_rcran@...>
Reviewed-by: Pierre Gondois <pierre.gondois@...>
---
DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h | 33 ++++++++++++
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c | 57 ++++++++++++++++++++
2 files changed, 90 insertions(+)

diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
index af18bf8e4871..80d05f74ee69 100644
--- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
+++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
@@ -592,6 +592,39 @@ AmlCodeGenRdDWordMemory (
OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL
);

+/** Code generation for the "Memory32Fixed ()" ASL macro.
+
+ The Resource Data effectively created is a 32-bit Memory Resource
+ Data. Cf ACPI 6.4:
+ - s19.6.83 "Memory Resource Descriptor Macro".
+ - s19.2.8 "Memory32FixedTerm".
+
+ See ACPI 6.4 spec, s19.2.8 for more.
+
+ @param [in] IsReadWrite ReadAndWrite parameter.
+ @param [in] Address AddressBase parameter.
+ @param [in] RangeLength Range length.
+ @param [in] NameOpNode NameOp object node defining a named object.
+ If provided, append the new resource data
+ node to the list of resource data elements
+ of this node.
+ @param [out] NewMemNode If provided and success,
+ contain the created node.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenRdMemory32Fixed (
+ BOOLEAN IsReadWrite,
+ UINT32 Address,
+ UINT32 RangeLength,
+ AML_OBJECT_NODE_HANDLE NameOpNode,
+ AML_DATA_NODE_HANDLE *NewMemNode
+ );
+
/** Code generation for the "WordBusNumber ()" ASL function.

The Resource Data effectively created is a Word Address Space Resource
diff --git a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
index 40d8c2b07ae3..fb18c5a77e2f 100644
--- a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
+++ b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
@@ -609,6 +609,63 @@ AmlCodeGenRdDWordMemory (
);
}

+/** Code generation for the "Memory32Fixed ()" ASL macro.
+
+ The Resource Data effectively created is a 32-bit Memory Resource
+ Data. Cf ACPI 6.4:
+ - s19.6.83 "Memory Resource Descriptor Macro".
+ - s19.2.8 "Memory32FixedTerm".
+
+ See ACPI 6.4 spec, s19.2.8 for more.
+
+ @param [in] IsReadWrite ReadAndWrite parameter.
+ @param [in] Addres AddressBase parameter.
+ @param [in] RangeLength Range length.
+ @param [in] NameOpNode NameOp object node defining a named object.
+ If provided, append the new resource data
+ node to the list of resource data elements
+ of this node.
+ @param [out] NewMemNode If provided and success,
+ contain the created node.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenRdMemory32Fixed (
+ BOOLEAN IsReadWrite,
+ UINT32 Address,
+ UINT32 RangeLength,
+ AML_OBJECT_NODE_HANDLE NameOpNode,
+ AML_DATA_NODE_HANDLE *NewMemNode
+ )
+{
+ EFI_STATUS Status;
+ AML_DATA_NODE *MemNode;
+ EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR RangeDesc;
+
+ RangeDesc.Header.Header.Byte = ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR;
+ RangeDesc.Header.Length = 0x09;
+ RangeDesc.Information = IsReadWrite ? BIT0 : 0;
+ RangeDesc.BaseAddress = Address;
+ RangeDesc.Length = RangeLength;
+
+ Status = AmlCreateDataNode (
+ EAmlNodeDataTypeResourceData,
+ (UINT8 *)&RangeDesc,
+ sizeof (RangeDesc),
+ &MemNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ return LinkRdNode (MemNode, NameOpNode, NewMemNode);
+}
+
/** Code generation for the "WordSpace ()" ASL function.

The Resource Data effectively created is a Word Address Space Resource
--
2.31.1


[PATCH v3 0/3] Add Memory32Fixed and AmlCodeGenMethodRetInteger functions

Rebecca Cran
 

Add functions to generate code for the Memory32Fixed ASL macro and a
method returning an Integer.

Remove a redundant cast from AmlCodeGenReturn.


Changes from v2 to v3:

o Rename function to AmlCodeGenRdMemory32Fixed.
o Use define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR.

Rebecca Cran (3):
DynamicTablesPkg: Add Memory32Fixed function
DynamicTablesPkg: Remove redundant cast in AmlCodeGenReturn
DynamicTablesPkg: Add AmlCodeGenMethodRetInteger function

DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h | 80 ++++++++++
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlCodeGen.c | 158 +++++++++++++++++++-
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c | 57 +++++++
3 files changed, 294 insertions(+), 1 deletion(-)

--
2.31.1


Re: [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package

Michael D Kinney
 

Hi Abner,

General recommendations included below. Of course each lib/modules/include needs to be reviewed and the
best location selected. I am aware that there are components in edk2 that do not follow these general
recommendations. This is due to content that was added before these recommendations were established
and we have work to do to get everything aligned.

Mike

-----Original Message-----
From: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>
Sent: Wednesday, January 12, 2022 9:34 PM
To: Kinney, Michael D <michael.d.kinney@...>; Leif Lindholm <leif@...>; devel@edk2.groups.io; Ni, Ray
<ray.ni@...>
Cc: Andrew Fish <afish@...>; Sami Mujawar <Sami.Mujawar@...>
Subject: RE: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package

HI Mike,
It is no problem to meet there. However, I am not available to join the design meeting in the next two weeks. Before we can get
together to discuss the best locations, do you have information regarding the rationale of driver/library location?

What is the best location for,
- Processor ARCH dependent modules
MdePkg for libs
UefiCpuPkg for modules

- Common modules for all processor ARCHs
Feature Packages based on the common feature. Add to existing if it fits. Create new for completely new feature area.

- Platform module that is specific to processor ARCH?
edk2-platform repository

The only exception so far are platform modules used to support OvmfPkg/QEMU to support CI.
In this case the modules are added to OvmfPkg.

- Platform module that is common to processor ARCHs?
edk2-platform repository

The only exception so far are platform modules used to support OvmfPkg/QEMU to support CI.
In this case the modules are added to OvmfPkg.


Thanks
Abner

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@...>
Sent: Monday, January 10, 2022 11:58 PM
To: Leif Lindholm <leif@...>; devel@edk2.groups.io; Chang, Abner
(HPS SW/FW Technologist) <abner.chang@...>; Kinney, Michael D
<michael.d.kinney@...>; Ni, Ray <ray.ni@...>
Cc: Andrew Fish <afish@...>; Sami Mujawar
<Sami.Mujawar@...>
Subject: RE: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add header
files of RISC-V processor package

Hi Abner,

I see comments from Leif as well.

Do you think a discussion in the design meeting Ray Ni runs would be
valuable
to review all the modules/libs/includes and discuss options for the best
location for them to reside in the edk2 repos?

Thanks,

Mike

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@...>
Sent: Monday, January 10, 2022 7:55 AM
To: Leif Lindholm <leif@...>; devel@edk2.groups.io; Chang,
Abner <abner.chang@...>; Kinney, Michael D
<michael.d.kinney@...>
Cc: Andrew Fish <afish@...>; Sami Mujawar
<Sami.Mujawar@...>
Subject: RE: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add
header files of RISC-V processor package

Hi Abner,

I would also like to see some proposals on adding the RiscV CPU scoped
content
to the existing MdePkg/UefiCpuPkg instead of adding a new top level CPU
package.

There is already some work started to move some of the ARM specific
content
from ARM CPU packages into MdePkg.

Thanks,

Mike

-----Original Message-----
From: Leif Lindholm <leif@...>
Sent: Monday, January 10, 2022 5:11 AM
To: devel@edk2.groups.io; Chang, Abner <abner.chang@...>
Cc: Andrew Fish <afish@...>; Kinney, Michael D
<michael.d.kinney@...>; Sami Mujawar <Sami.Mujawar@...>
Subject: Re: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add
header files of RISC-V processor package

On Sat, Jan 08, 2022 at 12:07:53 +0800, Abner Chang wrote:
(This is migrated from edk2-platforms:Silicon/RISC-V)

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@...>
Co-authored-by: Daniel Schaefer <daniel.schaefer@...>
Co-authored-by: Gilbert Chen <gilbert.chen@...>
Reviewed-by: Leif Lindholm <leif.lindholm@...>
Hmm, no.
I gave a reviewed-by for that patch to be merged into edk2-platforms
once upon a time. This is not relevant for migration to edk2.

My proposal for migrating this code would be as follows:
- Announce a hold on merging new code to RiscV portions of
edk2-platforms.
- Apply any and all bugfixes and CI/uncrustify fixes in place in
edk2-platforms.
- Get some level of agreement for what to do instead of
RiscVPlatformPkg - i.e. slot into MdeModulePkg instead.
- If that cannot be reached within a few days, create a new
top-level directory called "CommonPlatformPkg" or something,
with you, Daniel(/Gilbert?), Sami, me as maintainers.
- Move all of the RiscVPlatformPkg code under there instead.
- I'll follow with ArmPlatformPkg.
- PC/AT code should move across too over time.
- Move the rest of the code across unmodified as massive single
patches per package (potentially more patches than that for
RiscVPlatformPkg).
- Drop all existing Reviewed-by/Acked-by.
- After each "move" patch, insert a "fixup" patch to address the
things that need fixing due to path/name changes.

/
Leif

Cc: Leif Lindholm <leif.lindholm@...>
Cc: Gilbert Chen <gilbert.chen@...>
---
.../Include/IndustryStandard/RiscV.h | 156 ++++++++++++++++++
.../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 87 ++++++++++
2 files changed, 243 insertions(+)
create mode 100644 Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h

diff --git a/Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000000..2a992394ed
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,156 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001
<< 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 <<
2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION
(0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION
(0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION
(0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 <<
8)
+#define
RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION
(0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 <<
11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001
<< 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED
(0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 <<
15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION
(0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED
(0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION
(0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001
<< 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001
<< 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+ #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+ #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
+ #define SSTATUS_SIE_BIT_POSITION 1
+ #define SSTATUS_SPP_BIT_POSITION 8
+#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
+#define RISCV_CSR_SUPERVISOR_SEPC 0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
+ #define SCAUSE_USER_SOFTWARE_INT 0
+ #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
+ #define SCAUSE_USER_TIMER_INT 4
+ #define SCAUSE_SUPERVISOR_TIMER_INT 5
+ #define SCAUSE_USER_EXTERNAL_INT 8
+ #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
+#define RISCV_CSR_SUPERVISOR_STVAL 0x143
+#define RISCV_CSR_SUPERVISOR_SIP 0x144
+#define RISCV_CSR_SUPERVISOR_SATP 0x180
+
+#if defined (MDE_CPU_RISCV64)
+ #define RISCV_SATP_MODE_MASK 0xF000000000000000
+ #define RISCV_SATP_MODE_BIT_POSITION 60
+#endif
+ #define RISCV_SATP_MODE_OFF 0
+ #define RISCV_SATP_MODE_SV32 1
+ #define RISCV_SATP_MODE_SV39 8
+ #define RISCV_SATP_MODE_SV48 9
+ #define RISCV_SATP_MODE_SV57 10
+ #define RISCV_SATP_MODE_SV64 11
+
+ #define SATP64_ASID_MASK 0x0FFFF00000000000
+ #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
+
+#define RISCV_CAUSE_MISALIGNED_FETCH 0x0
+#define RISCV_CAUSE_FETCH_ACCESS 0x1
+#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define RISCV_CAUSE_BREAKPOINT 0x3
+#define RISCV_CAUSE_MISALIGNED_LOAD 0x4
+#define RISCV_CAUSE_LOAD_ACCESS 0x5
+#define RISCV_CAUSE_MISALIGNED_STORE 0x6
+#define RISCV_CAUSE_STORE_ACCESS 0x7
+#define RISCV_CAUSE_USER_ECALL 0x8
+#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9
+#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa
+#define RISCV_CAUSE_MACHINE_ECALL 0xb
+#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc
+#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd
+#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf
+#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
+#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
+#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
new file mode 100644
index 0000000000..14092df174
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
@@ -0,0 +1,87 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscV.h>
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ##
Name)
+
+#if defined (MDE_CPU_RISCV64)
+typedef UINT64 RISC_V_REGS_PROTOTYPE;
+#else
+#endif
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT
RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine
mode trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode
trap handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for
machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
--
2.31.1






Re: [PATCH] OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check

Peter Gonda
 

On Mon, Jan 10, 2022 at 11:18 AM Tom Lendacky <thomas.lendacky@...> wrote:

On 1/10/22 9:29 AM, Peter Gonda wrote:
On Fri, Jan 7, 2022 at 3:54 PM Tom Lendacky <thomas.lendacky@...> wrote:

On 1/7/22 11:04 AM, Peter Gonda wrote:
The SEV-ES bit of Fn800-001F[EAX] - Bit 3 is used for a host to
determine support for running SEV-ES guests. It should not be checked by
a guest to determine if it is running under SEV-ES. The guest should use
the SEV_STATUS MSR Bit 1 to determine if SEV-ES is enabled.
Worth mentioning in the commit message that this check wasn't part of the
original SEV-ES support (Fixes: a91b700e385e7484ab7286b3ba7ea2efbd59480e
tag?), so this is really a compatibility thing, and that this makes the
check consistent with the Linux kernel.
Sure I update the commit message in the V2 with this info and add the
Fixes tag. Do I need a (Fixes:
b461d67639f2deced77e9bb967d014b7cfcd75f8) tag too? Since the Check was
moved between files in that commit?
I don't think so, but that's just my opinion.
Thanks. Sent V2 with updates to commit and fixes tag.


Thanks,
Tom


[PATCH v2] OvmfPkg/ResetVector: Removing SEV-ES CPUID bit check

Peter Gonda
 

The SEV-ES bit of Fn800-001F[EAX] - Bit 3 is used for a host to
determine support for running SEV-ES guests. It should not be checked by
a guest to determine if it is running under SEV-ES. The guest should use
the SEV_STATUS MSR Bit 1 to determine if SEV-ES is enabled. This check
was not part of the original SEV-ES support and was added in
a91b700e38. Removing the check makes this code consistent with the
Linux kernel

Fixes: a91b700e38 (Ovmf/ResetVector: Simplify and consolidate the SEV features checks)
Cc: James Bottomley <jejb@...>
Cc: Min Xu <min.m.xu@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Erdem Aktas <erdemaktas@...>
Cc: Brijesh Singh <brijesh.singh@...>
Cc: Erdem Aktas <erdemaktas@...>
Cc: Marc Orr <marcorr@...>
Signed-off-by: Peter Gonda <pgonda@...>
---
OvmfPkg/ResetVector/Ia32/AmdSev.asm | 8 --------
1 file changed, 8 deletions(-)

diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
index 1f827da3b9..77692db27e 100644
--- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
+++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
@@ -265,14 +265,6 @@ CheckSevFeatures:
; Set the work area header to indicate that the SEV is enabled
mov byte[WORK_AREA_GUEST_TYPE], 1

- ; Check for SEV-ES memory encryption feature:
- ; CPUID Fn8000_001F[EAX] - Bit 3
- ; CPUID raises a #VC exception if running as an SEV-ES guest
- mov eax, 0x8000001f
- cpuid
- bt eax, 3
- jnc GetSevEncBit
-
; Check if SEV-ES is enabled
; MSR_0xC0010131 - Bit 1 (SEV-ES enabled)
mov ecx, SEV_STATUS_MSR
--
2.34.1.575.g55b058a8bb-goog


[PATCH v1 1/1] UefiCpuPackage: Add APIs for CPU physical address mask calculation

Yu Pu <yu.pu@...>
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3394

Firmware contains lots of code that deals with page table.These
code need the information of cpu physical address mask which
can be calculated from CPUID result.Today all these code implements
directly calls CPUID and calculates the address mask.
This bugzilla requests to add a new API as below so that all the
duplicated code can be removed.

Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>

Signed-off-by: Yu Pu <yu.pu@...>
---
UefiCpuPkg/CpuDxe/CpuDxe.c | 16 +------
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 47 ++++++++++++++++++=
++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 9 +---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +---
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +---
UefiCpuPkg/Include/Library/UefiCpuLib.h | 17 +++++++
6 files changed, 70 insertions(+), 37 deletions(-)

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 00f3cb09572c..8aca1bf72b4c 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -503,21 +503,7 @@ InitializeMtrrMask (
VOID=0D
)=0D
{=0D
- UINT32 RegEax;=0D
- UINT8 PhysicalAddressBits;=0D
-=0D
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D
-=0D
- if (RegEax >=3D 0x80000008) {=0D
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D
-=0D
- PhysicalAddressBits =3D (UINT8)RegEax;=0D
- } else {=0D
- PhysicalAddressBits =3D 36;=0D
- }=0D
-=0D
- mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1;=0D
- mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL;=0D
+ GetPhysicalAddressBits(&mValidMtrrBitsMask, &mValidMtrrAddressMask);=0D
}=0D
=0D
/**=0D
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPk=
g/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
index 5d925bc273f8..bb1343f3cd21 100644
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
@@ -79,3 +79,50 @@ GetCpuSteppingId (
=0D
return (UINT8)Eax.Bits.SteppingId;=0D
}=0D
+=0D
+/**=0D
+ Get the physical address width supported by the processor.=0D
+ @param[out] ValidAddressMask Bitmask with valid address bits se=
t to=0D
+ one; other bits are clear. Optiona=
l=0D
+ parameter.=0D
+ @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre=
ss=0D
+ bits set to one; other bits are cl=
ear.=0D
+ Optional parameter.=0D
+ @return The physical address width supported by the processor.=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+GetPhysicalAddressBits (=0D
+ OUT UINT64 *ValidAddressMask OPTIONAL,=0D
+ OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D
+ )=0D
+{=0D
+ UINT32 MaxExtendedFunction;=0D
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0D
+ UINT64 AddressMask;=0D
+ UINT64 PageBaseAddressMask;=0D
+=0D
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NUL=
L);=0D
+ if (MaxExtendedFunction >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0D
+ AsmCpuid (=0D
+ CPUID_VIR_PHY_ADDRESS_SIZE,=0D
+ &VirPhyAddressSize.Uint32,=0D
+ NULL,=0D
+ NULL,=0D
+ NULL=0D
+ );=0D
+ } else {=0D
+ VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0D
+ }=0D
+=0D
+ AddressMask =3D LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits=
) - 1;=0D
+ PageBaseAddressMask =3D AddressMask & ~(UINT64)0xFFF;=0D
+=0D
+ if (ValidAddressMask !=3D NULL) {=0D
+ *ValidAddressMask =3D AddressMask;=0D
+ }=0D
+ if (ValidPageBaseAddressMask !=3D NULL) {=0D
+ *ValidPageBaseAddressMask =3D PageBaseAddressMask;=0D
+ }=0D
+ return (UINT8)VirPhyAddressSize.Bits.PhysicalAddressBits;=0D
+}=0D
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib=
rary/SmmCpuFeaturesLib/SmmStm.c
index 4e8f897f5e9c..ec7cd4013132 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -15,6 +15,7 @@
#include <Library/UefiBootServicesTableLib.h>=0D
#include <Library/SmmServicesTableLib.h>=0D
#include <Library/TpmMeasurementLib.h>=0D
+#include <Library/UefiCpuLib.h>=0D
#include <Register/Intel/Cpuid.h>=0D
#include <Register/Intel/ArchitecturalMsr.h>=0D
#include <Register/Intel/SmramSaveStateMap.h>=0D
@@ -330,13 +331,7 @@ SmmCpuFeaturesInstallSmiHandler (
if (Hob !=3D NULL) {=0D
Psd->PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=
=0D
} else {=0D
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D
- if (RegEax >=3D 0x80000008) {=0D
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D
- Psd->PhysicalAddressBits =3D (UINT8)RegEax;=0D
- } else {=0D
- Psd->PhysicalAddressBits =3D 36;=0D
- }=0D
+ Psd->PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D
}=0D
=0D
if (!mStmConfigurationTableInitialized) {=0D
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD=
xeSmm/X64/PageTbl.c
index 538394f23910..de1385a86948 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -194,7 +194,6 @@ CalculateMaximumSupportAddress (
VOID=0D
)=0D
{=0D
- UINT32 RegEax;=0D
UINT8 PhysicalAddressBits;=0D
VOID *Hob;=0D
=0D
@@ -205,13 +204,7 @@ CalculateMaximumSupportAddress (
if (Hob !=3D NULL) {=0D
PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D
} else {=0D
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D
- if (RegEax >=3D 0x80000008) {=0D
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D
- PhysicalAddressBits =3D (UINT8)RegEax;=0D
- } else {=0D
- PhysicalAddressBits =3D 36;=0D
- }=0D
+ PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D
}=0D
=0D
return PhysicalAddressBits;=0D
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg=
/Universal/Acpi/S3Resume2Pei/S3Resume.c
index 8419a4e32acb..1017f0316093 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -42,6 +42,7 @@
#include <Library/HobLib.h>=0D
#include <Library/LockBoxLib.h>=0D
#include <IndustryStandard/Acpi.h>=0D
+#include <Library/UefiCpuLib.h>=0D
=0D
/**=0D
This macro aligns the address of a variable with auto storage=0D
@@ -646,13 +647,7 @@ RestoreS3PageTables (
if (Hob !=3D NULL) {=0D
PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;=0D
} else {=0D
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D
- if (RegEax >=3D 0x80000008) {=0D
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D
- PhysicalAddressBits =3D (UINT8)RegEax;=0D
- } else {=0D
- PhysicalAddressBits =3D 36;=0D
- }=0D
+ PhysicalAddressBits =3D GetPhysicalAddressBits (NULL, NULL);=0D
}=0D
=0D
//=0D
diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/L=
ibrary/UefiCpuLib.h
index 0ff4a35774c1..dabed95ab38a 100644
--- a/UefiCpuPkg/Include/Library/UefiCpuLib.h
+++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h
@@ -62,4 +62,21 @@ GetCpuSteppingId (
VOID=0D
);=0D
=0D
+/**=0D
+ Get the physical address width supported by the processor.=0D
+ @param[out] ValidAddressMask Bitmask with valid address bits se=
t to=0D
+ one; other bits are clear. Optiona=
l=0D
+ parameter.=0D
+ @param[out] ValidPageBaseAddressMask Bitmask with valid page base addre=
ss=0D
+ bits set to one; other bits are cl=
ear.=0D
+ Optional parameter.=0D
+ @return The physical address width supported by the processor.=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+GetPhysicalAddressBits (=0D
+ OUT UINT64 *ValidAddressMask OPTIONAL,=0D
+ OUT UINT64 *ValidPageBaseAddressMask OPTIONAL=0D
+ );=0D
+=0D
#endif=0D
--=20
2.30.0.windows.2


MOM // RE: TianoCore edk2-test Bug Triage Meeting 13.01.2022

G Edhaya Chandran
 

Hello All,

 

    Thank you attending the meeting.

Next meeting is on: 3rd February 2022

 

MOM:

Three issues were closed today. The updated status of other issues are as below:

 

 

ID

Product

Comp

Assignee

Status

Resolution

Summary

Changed

3736

EDK2 Tes

UEFI-SCT

Joseph.Hemann@...

UNCO

---

UEFI-SCT: TCG2 Protocol Test

09:34:51

3145

EDK2 Tes

UEFI-SCT

Sunny.Wang@...

CONF

---

UEFI-SCT: handling of unsupported EFI_SIMPLE_NETWORK_PROTOCOL functions

09:24:30

3738

EDK2 Tes

UEFI-SCT

Sunny.Wang@...

CONF

---

EFI_SIMPLE_TEXT_OUT_PROTOCOL tests should allow SetMode to return EFI_UNSUPPORTED

09:23:00

3601

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

QemuVideoDxe SCT inconsistent test failures and logging issue

09:16:58

3759

EDK2 Tes

UEFI-SCT

unassigned@...

CONF

---

SCT test fails when RouteConfig returns EFI_ACCESS_DENIED

09:13:54

2126

EDK2 Tes

UEFI-SCT

Carolyn.Gjertsen@...

CONF

---

SCT does not build for X64 using GCC - missing EFIAPI

09:10:24

2238

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

NULL dereference in BBTestQueryFunctionAutoTest()

08:17:16

1860

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

Verify that loading images with <4k section alignment either succeeds or fails gracefully

2021-12-03

2774

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

BS.GetNextMonotonicCount - high 32 bit increase by 1 FAILURE.

2021-12-02

2650

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

SCT2.7 "BootServicesTest\ImageServicesTest" Test Fail

2021-12-02

2386

EDK2 Tes

UEFI-SCT

gaojie@...

CONF

---

BBTestReadKeyStrokeExFunctionAutoTestCheckpoint1() can't identify the problem of wrong implementation of ReadKeyStrokeEx

2021-11-23

2239

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

UpdateInfoFileName() returns random bytes from stack

2021-11-11

2230

EDK2 Tes

UEFI-SCT

stuart.yoder@...

CONF

---

Feature request: image authentication test

2021-11-11

1839

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

Feature request for location of tests for vendor/edk2 specific protocols

2021-11-11

3270

EDK2 Tes

UEFI-SCT

edhaya.chandran@...

CONF

---

uefi-sct: DevicePathFromText test for Uart() is too strict

2021-11-11

3595

EDK2 Tes

UEFI-SCT

Carolyn.Gjertsen@...

CONF

---

SctPkg does not build for a variety of architectures/toolchains

2021-09-07

 

 

With Warm Regards,

Edhay

 

 

-----Original Appointment-----

From: G Edhaya Chandran
Sent: 19 August 2021 17:33
To: G Edhaya Chandran; Samer El-Haj-Mahmoud; Barton Gao; Heinrich Schuchardt; Venkatesh, Supreeth; Gjertsen, Carolyn; Sunny Wang; Mark Woods; Grant Likely; Joseph Hemann; Stuart Yoder; Jeremy Linton; Paul Yang; Vincent Stehle; Rob Herring; devel@edk2.groups.io
Cc: gaoliming; 'Hsiung, Harry L'; 'Guptha, Soumya K'; 'Kinney, Michael D'; heinrich.schuchardt@...; Dong Wei; Wang, Nickle (HPS SW); Michael Chiu; Venu Busireddy; Karl Heubaum; Doran, Mark; Bret Barkelew; Bodke, Kishore K; Fang, Peter; Spottswood, Jason; Tsao, Ethan; Roger Pau Monne; Velusamy, Sudhakar; Jeff Ragucci; Lohr, Paul A; Jared McNeill; Jonathan Cameron; Eugene Khoruzhenko; Girish Pathak; Demeter, Miki; Ryan Harkin; Andrei Warkentin
Subject: TianoCore edk2-test Bug Triage Meeting
When: 13 January 2022 19:30-20:30 (UTC+05:30) Chennai, Kolkata, Mumbai, New Delhi.
Where: https://armltd.zoom.us/j/93809865843?pwd=dU1hSzk4NHM2RGhaRDRyWWZxUzY5dz09&from=addon

 

Please Note: Postponing only the January 2022 instance of the meeting by 1 week to 13th January in view of the holiday season.

Wishing you a Merry Christmas and a Happy New Year!

 

TianoCore edk2-test Bug Triage meeting

Hosted by: G Edhaya Chandran, Barton Gao, Carolyn Gjersten

 

Changed the medium to Zoom

 

 

Agenda:

                       Discussion on the progress of the BZ tickets dispositioned in the previous meeting

                          Bug List (tianocore.org)

                       Dispositioning the new BZ tickets

                       Specific agenda items from the community members

 

 

 

 

 Edhaya Chandran G is inviting you to a scheduled Zoom meeting.

Join Zoom Meeting
https://armltd.zoom.us/j/93809865843?pwd=dU1hSzk4NHM2RGhaRDRyWWZxUzY5dz09&from=addon

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IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH v4 00/11] Create new target for Cloud Hypervisor

Yao, Jiewen
 

-----Original Message-----
From: Boeuf, Sebastien <sebastien.boeuf@...>
Sent: Tuesday, January 11, 2022 8:31 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@...>; Justen, Jordan L
<jordan.l.justen@...>; kraxel@...; Boeuf, Sebastien
<sebastien.boeuf@...>
Subject: [PATCH v4 00/11] Create new target for Cloud Hypervisor

From: Sebastien Boeuf <sebastien.boeuf@...>

Since Cloud Hypervisor and QEMU pc/q35 are quite different, it makes
more sense to create a dedicated OVMF target for Cloud Hypervisor rather
than trying to support both VMMs from the same OvmfPkgX64 target.

That's the reason why this series introduces a new target called
CloudHvX64, meant to be used with the Cloud Hypervisor VMM only.

The new target is initially copied over from the OvmfPkgX64, then it is
trimmed down by removing what is not needed from a Cloud Hypervisor
perspective.

Sebastien Boeuf (11):
OvmfPkg/CloudHv: Add new target for Cloud Hypervisor
OvmfPkg/CloudHv: Replace legacy 8254 PIT with local APIC timer
OvmfPkg/CloudHv: Connect serial console
OvmfPkg/CloudHv: Remove legacy 8259 PIC support
OvmfPkg/CloudHv: Remove Q35 specifics
OvmfPkg/CloudHv: Reduce dependency on QemuFwCfg
OvmfPkg/CloudHv: Remove video support
OvmfPkg/CloudHv: Remove USB support
OvmfPkg/CloudHv: Remove CSM support
OvmfPkg/CloudHv: add Maintainers.txt entry
OvmfPkg: Add CloudHvX64 to the CI

Maintainers.txt | 5 +
OvmfPkg/CloudHv/CloudHvX64.dsc | 938 ++++++++++++++++++
OvmfPkg/CloudHv/CloudHvX64.fdf | 503 ++++++++++
.../PlatformBootManagerLib/BdsPlatform.c | 8 +-
.../.azurepipelines/Ubuntu-GCC5.yml | 9 +
OvmfPkg/PlatformCI/CloudHvBuild.py | 37 +
6 files changed, 1499 insertions(+), 1 deletion(-)
create mode 100644 OvmfPkg/CloudHv/CloudHvX64.dsc
create mode 100644 OvmfPkg/CloudHv/CloudHvX64.fdf
create mode 100644 OvmfPkg/PlatformCI/CloudHvBuild.py

--
2.30.2


Re: [PATCH] uefi-sct/SctPkg:Enhance BBTestReadKeyStrokeExFunctionAutoTestCheckpoint1()

G Edhaya Chandran
 

Reviewed-by: G Edhaya Chandran <edhaya.chandran@...>


Re: [PATCH edk2-test 1/1] uefi-sct/SctPkg: invalid values for SetWakeupTime()

G Edhaya Chandran
 

Upstreamed as commit - id:
https://github.com/tianocore/edk2-test/commit/01d9d24efdedb30ff6b0e1f1c47c6c3b0c5a7093


A question about ELF conversion in BaseTools

Chao Li
 

Hi devel:

I have a question about ELF convert to PE format:

In the function WriteSections64, after the section is copied, it will apply the relocation. I found that the address that needs to be modified in the PE file is the same as the ELF file, because the address is determined in the linking step, so I don't know why the code is fixing the address in the PE file? Maybe an ELF file have multiple .text or .data sections, while a PE file should merge sections with the same name? Or some other reason?

I tried use the GenFw with -v option, the log like:


All of the Addend and Relocation are the same.

Hope someone can answer me. :)

Thanks,

Chao Li


Re: [PATCH v3] MdePkg: Add registers of boot partition feature

Gerd Hoffmann
 

On Wed, Jan 05, 2022 at 06:35:06PM +0800, Maggie Chu wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3757

Add registers of boot partition feature which defined in NVM Express 1.4 Spec
nvme boot in qemu broke, and git bisect landed at this commit.

Error message:

NvmeControllerInit: the controller doesn't support NVMe command set

// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
@@ -51,11 +55,14 @@ typedef struct {
UINT8 To; // Timeout
UINT16 Dstrd : 4;
UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
- UINT16 Css : 4; // Command Sets Supported - Bit 37
- UINT16 Rsvd3 : 7;
+ UINT16 Css : 8; // Command Sets Supported - Bit 37
+ UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
+ UINT16 Rsvd3 : 2;
This looks very suspicious ...

take care,
Gerd


Re: [PATCH v2 1/3] DynamicTablesPkg: Add Memory32Fixed function

PierreGondois
 

Hello Rebecca,

Just 2 minor comments. With that changed:

Reviewed-by: Pierre Gondois <pierre.gondois@...>


On 1/11/22 6:54 PM, Rebecca Cran wrote:
Add a Memory32Fixed function to generate code for the corresponding
Memory32Fixed macro in AML.

Signed-off-by: Rebecca Cran <quic_rcran@...>
---
DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h | 33 ++++++++++++
DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c | 57 ++++++++++++++++++++
2 files changed, 90 insertions(+)

diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
index af18bf8e4871..2491ade397c6 100644
--- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
+++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
@@ -592,6 +592,39 @@ AmlCodeGenRdDWordMemory (
OUT AML_DATA_NODE_HANDLE *NewRdNode OPTIONAL
);

+/** Code generation for the "Memory32Fixed ()" ASL macro.
+
+ The Resource Data effectively created is a 32-bit Memory Resource
+ Data. Cf ACPI 6.4:
+ - s19.6.83 "Memory Resource Descriptor Macro".
+ - s19.2.8 "Memory32FixedTerm".
+
+ See ACPI 6.4 spec, s19.2.8 for more.
+
+ @param [in] IsReadWrite ReadAndWrite parameter.
+ @param [in] Address AddressBase parameter.
+ @param [in] RangeLength Range length.
+ @param [in] NameOpNode NameOp object node defining a named object.
+ If provided, append the new resource data
+ node to the list of resource data elements
+ of this node.
+ @param [out] NewMemNode If provided and success,
+ contain the created node.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenMemory32Fixed (
+ BOOLEAN IsReadWrite,
+ UINT32 Address,
+ UINT32 RangeLength,
+ AML_OBJECT_NODE_HANDLE NameOpNode,
+ AML_DATA_NODE_HANDLE *NewMemNode
+ );
+
/** Code generation for the "WordBusNumber ()" ASL function.

The Resource Data effectively created is a Word Address Space Resource
diff --git a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
index 40d8c2b07ae3..19fb76dc5b45 100644
--- a/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
+++ b/DynamicTablesPkg/Library/Common/AmlLib/CodeGen/AmlResourceDataCodeGen.c
@@ -609,6 +609,63 @@ AmlCodeGenRdDWordMemory (
);
}

+/** Code generation for the "Memory32Fixed ()" ASL macro.
+
+ The Resource Data effectively created is a 32-bit Memory Resource
+ Data. Cf ACPI 6.4:
+ - s19.6.83 "Memory Resource Descriptor Macro".
+ - s19.2.8 "Memory32FixedTerm".
+
+ See ACPI 6.4 spec, s19.2.8 for more.
+
+ @param [in] IsReadWrite ReadAndWrite parameter.
+ @param [in] Addres AddressBase parameter.
+ @param [in] RangeLength Range length.
+ @param [in] NameOpNode NameOp object node defining a named object.
+ If provided, append the new resource data
+ node to the list of resource data elements
+ of this node.
+ @param [out] NewMemNode If provided and success,
+ contain the created node.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+**/
+EFI_STATUS
+EFIAPI
+AmlCodeGenMemory32Fixed (
I missed it in the v1, but other similar functions have an 'Rd' for Resource Data
in their name, so I think it should be AmlCodeGenRdMemory32Fixed() instead.


+ BOOLEAN IsReadWrite,
+ UINT32 Address,
+ UINT32 RangeLength,
+ AML_OBJECT_NODE_HANDLE NameOpNode,
+ AML_DATA_NODE_HANDLE *NewMemNode
+ )
+{
+ EFI_STATUS Status;
+ AML_DATA_NODE *MemNode;
+ EFI_ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR RangeDesc;
+
+ RangeDesc.Header.Header.Byte = 0x86;
+ RangeDesc.Header.Length = 0x09;
Is it possible to use the macros available instead of hard-coded values ?
Cf the AmlCodeRdGenRegister() function and the macro:
ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME

+ RangeDesc.Information = IsReadWrite ? BIT0 : 0;
+ RangeDesc.BaseAddress = Address;
+ RangeDesc.Length = RangeLength;
+
+ Status = AmlCreateDataNode (
+ EAmlNodeDataTypeResourceData,
+ (UINT8 *)&RangeDesc,
+ sizeof (RangeDesc),
+ &MemNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ return LinkRdNode (MemNode, NameOpNode, NewMemNode);
+}
+
/** Code generation for the "WordSpace ()" ASL function.

The Resource Data effectively created is a Word Address Space Resource


Re: [PATCH] MdeModulePkg/HiiDatabaseDxe: Add Support for authenticated variable

Dandan Bi
 

The change is ok to me. Reviewed-by: Dandan Bi <dandan.bi@...>

Hi Liming,

Could you also help review it?


Thanks,
Dandan

-----Original Message-----
From: Huang, Long1 <long1.huang@...>
Sent: Thursday, January 13, 2022 1:06 AM
To: devel@edk2.groups.io
Cc: Huang, Long1 <long1.huang@...>; Feng, Bob C
<bob.c.feng@...>; Gao, Liming <gaoliming@...>; Bi,
Dandan <dandan.bi@...>; Chen, Lin Z <lin.z.chen@...>; Li,
Zhuangzhi <zhuangzhi.li@...>
Subject: [PATCH] MdeModulePkg/HiiDatabaseDxe: Add Support for
authenticated variable

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3796

Database.c:
1. Replace PcdGetExPtr with PcdGetExPtr.
2. Add FindAuthVariableData function to parse authenticated
variable type for getting a correct default value in
PcdNvStoreDefaultValueBuffer.

Signed-off-by: Huang Long <long1.huang@...>

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Dandan Bi <dandan.bi@...>
Cc: Lin Z Chen <lin.z.chen@...>
Cc: Zhuangzhi Li <zhuangzhi.li@...>
---
.../Universal/HiiDatabaseDxe/Database.c | 130 ++++++++++++++----
.../HiiDatabaseDxe/HiiDatabaseDxe.inf | 3 +
2 files changed, 105 insertions(+), 28 deletions(-)

diff --git a/MdeModulePkg/Universal/HiiDatabaseDxe/Database.c
b/MdeModulePkg/Universal/HiiDatabaseDxe/Database.c
index 0b09c24d52..c7a92d6aed 100644
--- a/MdeModulePkg/Universal/HiiDatabaseDxe/Database.c
+++ b/MdeModulePkg/Universal/HiiDatabaseDxe/Database.c
@@ -603,6 +603,45 @@ FindVariableData (
return NULL;

}



+/**

+ Find the matched authenticated variable from the input variable storage.

+

+ @param[in] VariableStorage Point to the variable storage header.

+ @param[in] VarGuid A unique identifier for the variable.

+ @param[in] VarAttribute The attributes bitmask for the variable.

+ @param[in] VarName A Null-terminated ascii string that is the name of
the variable.

+

+ @return Pointer to the matched variable header or NULL if not found.

+**/

+AUTHENTICATED_VARIABLE_HEADER *

+FindAuthVariableData (

+ IN VARIABLE_STORE_HEADER *VariableStorage,

+ IN EFI_GUID *VarGuid,

+ IN UINT32 VarAttribute,

+ IN CHAR16 *VarName

+ )

+{

+ AUTHENTICATED_VARIABLE_HEADER *AuthVariableHeader;

+ AUTHENTICATED_VARIABLE_HEADER *AuthVariableEnd;

+

+ AuthVariableEnd = (AUTHENTICATED_VARIABLE_HEADER *)((UINT8
*)VariableStorage + VariableStorage->Size);

+ AuthVariableHeader = (AUTHENTICATED_VARIABLE_HEADER
*)(VariableStorage + 1);

+ AuthVariableHeader = (AUTHENTICATED_VARIABLE_HEADER
*)HEADER_ALIGN (AuthVariableHeader);

+ while (AuthVariableHeader < AuthVariableEnd) {

+ if (CompareGuid (&AuthVariableHeader->VendorGuid, VarGuid) &&

+ (AuthVariableHeader->Attributes == VarAttribute) &&

+ (StrCmp (VarName, (CHAR16 *)(AuthVariableHeader + 1)) == 0))

+ {

+ return AuthVariableHeader;

+ }

+

+ AuthVariableHeader = (AUTHENTICATED_VARIABLE_HEADER *)((UINT8
*)AuthVariableHeader + sizeof (AUTHENTICATED_VARIABLE_HEADER) +
AuthVariableHeader->NameSize + AuthVariableHeader->DataSize);

+ AuthVariableHeader = (AUTHENTICATED_VARIABLE_HEADER
*)HEADER_ALIGN (AuthVariableHeader);

+ }

+

+ return NULL;

+}

+

/**

Find question default value from PcdNvStoreDefaultValueBuffer



@@ -626,25 +665,29 @@ FindQuestionDefaultSetting (
IN BOOLEAN BitFieldQuestion

)

{

- VARIABLE_HEADER *VariableHeader;

- VARIABLE_STORE_HEADER *VariableStorage;

- LIST_ENTRY *Link;

- VARSTORAGE_DEFAULT_DATA *Entry;

- VARIABLE_STORE_HEADER *NvStoreBuffer;

- UINT8 *DataBuffer;

- UINT8 *BufferEnd;

- BOOLEAN IsFound;

- UINTN Index;

- UINT32 BufferValue;

- UINT32 BitFieldVal;

- UINTN BitOffset;

- UINTN ByteOffset;

- UINTN BitWidth;

- UINTN StartBit;

- UINTN EndBit;

- PCD_DEFAULT_DATA *DataHeader;

- PCD_DEFAULT_INFO *DefaultInfo;

- PCD_DATA_DELTA *DeltaData;

+ VARIABLE_HEADER *VariableHeader;

+ AUTHENTICATED_VARIABLE_HEADER *AuthVariableHeader;

+ VARIABLE_STORE_HEADER *VariableStorage;

+ LIST_ENTRY *Link;

+ VARSTORAGE_DEFAULT_DATA *Entry;

+ VARIABLE_STORE_HEADER *NvStoreBuffer;

+ VOID *ValueSource;

+ VOID *BitValueSource;

+ UINT8 *DataBuffer;

+ UINT8 *BufferEnd;

+ BOOLEAN AuthFormat;

+ BOOLEAN IsFound;

+ UINTN Index;

+ UINT32 BufferValue;

+ UINT32 BitFieldVal;

+ UINTN BitOffset;

+ UINTN ByteOffset;

+ UINTN BitWidth;

+ UINTN StartBit;

+ UINTN EndBit;

+ PCD_DEFAULT_DATA *DataHeader;

+ PCD_DEFAULT_INFO *DefaultInfo;

+ PCD_DATA_DELTA *DeltaData;



if (gSkuId == 0xFFFFFFFFFFFFFFFF) {

gSkuId = LibPcdGetSku ();

@@ -666,7 +709,7 @@ FindQuestionDefaultSetting (
}



if (Link == &gVarStorageList) {

- DataBuffer = (UINT8 *)PcdGetPtr (PcdNvStoreDefaultValueBuffer);

+ DataBuffer = (UINT8 *)PcdGetExPtr
(&gEfiMdeModulePkgTokenSpaceGuid, PcdNvStoreDefaultValueBuffer);

gNvDefaultStoreSize = ((PCD_NV_STORE_DEFAULT_BUFFER_HEADER
*)DataBuffer)->Length;

//

// The first section data includes NV storage default setting.

@@ -750,12 +793,27 @@ FindQuestionDefaultSetting (
return EFI_NOT_FOUND;

}



+ //

+ // Judge if the variable type is authenticated, default is false

+ //

+ AuthFormat = FALSE;

+ if (CompareGuid (&VariableStorage->Signature,
&gEfiAuthenticatedVariableGuid)) {

+ AuthFormat = TRUE;

+ }

+

//

// Find the question default value from the variable storage

//

- VariableHeader = FindVariableData (VariableStorage, &EfiVarStore->Guid,
EfiVarStore->Attributes, (CHAR16 *)EfiVarStore->Name);

- if (VariableHeader == NULL) {

- return EFI_NOT_FOUND;

+ if(AuthFormat) {

+ AuthVariableHeader = FindAuthVariableData (VariableStorage,
&EfiVarStore->Guid, EfiVarStore->Attributes, (CHAR16 *)EfiVarStore-
Name);
+ if (AuthVariableHeader == NULL) {

+ return EFI_NOT_FOUND;

+ }

+ } else {

+ VariableHeader = FindVariableData (VariableStorage, &EfiVarStore->Guid,
EfiVarStore->Attributes, (CHAR16 *)EfiVarStore->Name);

+ if (VariableHeader == NULL) {

+ return EFI_NOT_FOUND;

+ }

}



StartBit = 0;

@@ -770,8 +828,24 @@ FindQuestionDefaultSetting (
Width = EndBit / 8 + 1;

}



- if (VariableHeader->DataSize < ByteOffset + Width) {

- return EFI_INVALID_PARAMETER;

+ if (AuthFormat) {

+ if (AuthVariableHeader->DataSize < ByteOffset + Width) {

+ return EFI_INVALID_PARAMETER;

+ }

+

+ ValueSource = (UINT8 *)AuthVariableHeader + sizeof
(AUTHENTICATED_VARIABLE_HEADER) + AuthVariableHeader->NameSize +
IfrQuestionHdr->VarStoreInfo.VarOffset;

+ if (BitFieldQuestion) {

+ BitValueSource = (UINT8 *)AuthVariableHeader + sizeof
(AUTHENTICATED_VARIABLE_HEADER) + AuthVariableHeader->NameSize +
ByteOffset;

+ }

+ } else {

+ if (VariableHeader->DataSize < ByteOffset + Width) {

+ return EFI_INVALID_PARAMETER;

+ }

+

+ ValueSource = (UINT8 *)VariableHeader + sizeof (VARIABLE_HEADER) +
VariableHeader->NameSize + IfrQuestionHdr->VarStoreInfo.VarOffset;

+ if (BitFieldQuestion) {

+ BitValueSource = (UINT8 *)VariableHeader + sizeof (VARIABLE_HEADER)
+ VariableHeader->NameSize + ByteOffset;

+ }

}



//

@@ -779,11 +853,11 @@ FindQuestionDefaultSetting (
//

if (ValueBuffer != NULL) {

if (BitFieldQuestion) {

- CopyMem (&BufferValue, (UINT8 *)VariableHeader + sizeof
(VARIABLE_HEADER) + VariableHeader->NameSize + ByteOffset, Width);

+ CopyMem (&BufferValue, BitValueSource, Width);

BitFieldVal = BitFieldRead32 (BufferValue, StartBit, EndBit);

CopyMem (ValueBuffer, &BitFieldVal, Width);

} else {

- CopyMem (ValueBuffer, (UINT8 *)VariableHeader + sizeof
(VARIABLE_HEADER) + VariableHeader->NameSize + IfrQuestionHdr-
VarStoreInfo.VarOffset, Width);
+ CopyMem (ValueBuffer, ValueSource, Width);

}

}



@@ -832,7 +906,7 @@ UpdateDefaultSettingInFormPackage (
// If no default setting, do nothing

//

if (gNvDefaultStoreSize == 0) {

- gNvDefaultStoreSize = PcdGetSize (PcdNvStoreDefaultValueBuffer);

+ gNvDefaultStoreSize = PcdGetExSize
(&gEfiMdeModulePkgTokenSpaceGuid, PcdNvStoreDefaultValueBuffer);

}



if (gNvDefaultStoreSize < sizeof
(PCD_NV_STORE_DEFAULT_BUFFER_HEADER)) {

diff --git a/MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
b/MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
index 0116fb6ecb..dac4d614a8 100644
--- a/MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+++ b/MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
@@ -86,6 +86,9 @@
gEfiHiiImageDecoderNameJpegGuid
|gEfiMdeModulePkgTokenSpaceGuid.PcdSupportHiiImageProtocol ##
SOMETIMES_CONSUMES ## GUID

gEfiHiiImageDecoderNamePngGuid
|gEfiMdeModulePkgTokenSpaceGuid.PcdSupportHiiImageProtocol ##
SOMETIMES_CONSUMES ## GUID

gEdkiiIfrBitVarstoreGuid ##
SOMETIMES_CONSUMES ## GUID

+ gEfiAuthenticatedVariableGuid

+ gEfiVariableGuid

+ gEfiMdeModulePkgTokenSpaceGuid



[Depex]

TRUE

--
2.25.1


Re: [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package

Abner Chang
 

HI Mike,
It is no problem to meet there. However, I am not available to join the design meeting in the next two weeks. Before we can get together to discuss the best locations, do you have information regarding the rationale of driver/library location?

What is the best location for,
- Processor ARCH dependent modules
- Common modules for all processor ARCHs
- Platform module that is specific to processor ARCH?
- Platform module that is common to processor ARCHs?

Thanks
Abner

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@...>
Sent: Monday, January 10, 2022 11:58 PM
To: Leif Lindholm <leif@...>; devel@edk2.groups.io; Chang, Abner
(HPS SW/FW Technologist) <abner.chang@...>; Kinney, Michael D
<michael.d.kinney@...>; Ni, Ray <ray.ni@...>
Cc: Andrew Fish <afish@...>; Sami Mujawar
<Sami.Mujawar@...>
Subject: RE: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add header
files of RISC-V processor package

Hi Abner,

I see comments from Leif as well.

Do you think a discussion in the design meeting Ray Ni runs would be
valuable
to review all the modules/libs/includes and discuss options for the best
location for them to reside in the edk2 repos?

Thanks,

Mike

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@...>
Sent: Monday, January 10, 2022 7:55 AM
To: Leif Lindholm <leif@...>; devel@edk2.groups.io; Chang,
Abner <abner.chang@...>; Kinney, Michael D
<michael.d.kinney@...>
Cc: Andrew Fish <afish@...>; Sami Mujawar
<Sami.Mujawar@...>
Subject: RE: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add
header files of RISC-V processor package

Hi Abner,

I would also like to see some proposals on adding the RiscV CPU scoped
content
to the existing MdePkg/UefiCpuPkg instead of adding a new top level CPU
package.

There is already some work started to move some of the ARM specific
content
from ARM CPU packages into MdePkg.

Thanks,

Mike

-----Original Message-----
From: Leif Lindholm <leif@...>
Sent: Monday, January 10, 2022 5:11 AM
To: devel@edk2.groups.io; Chang, Abner <abner.chang@...>
Cc: Andrew Fish <afish@...>; Kinney, Michael D
<michael.d.kinney@...>; Sami Mujawar <Sami.Mujawar@...>
Subject: Re: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add
header files of RISC-V processor package

On Sat, Jan 08, 2022 at 12:07:53 +0800, Abner Chang wrote:
(This is migrated from edk2-platforms:Silicon/RISC-V)

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@...>
Co-authored-by: Daniel Schaefer <daniel.schaefer@...>
Co-authored-by: Gilbert Chen <gilbert.chen@...>
Reviewed-by: Leif Lindholm <leif.lindholm@...>
Hmm, no.
I gave a reviewed-by for that patch to be merged into edk2-platforms
once upon a time. This is not relevant for migration to edk2.

My proposal for migrating this code would be as follows:
- Announce a hold on merging new code to RiscV portions of
edk2-platforms.
- Apply any and all bugfixes and CI/uncrustify fixes in place in
edk2-platforms.
- Get some level of agreement for what to do instead of
RiscVPlatformPkg - i.e. slot into MdeModulePkg instead.
- If that cannot be reached within a few days, create a new
top-level directory called "CommonPlatformPkg" or something,
with you, Daniel(/Gilbert?), Sami, me as maintainers.
- Move all of the RiscVPlatformPkg code under there instead.
- I'll follow with ArmPlatformPkg.
- PC/AT code should move across too over time.
- Move the rest of the code across unmodified as massive single
patches per package (potentially more patches than that for
RiscVPlatformPkg).
- Drop all existing Reviewed-by/Acked-by.
- After each "move" patch, insert a "fixup" patch to address the
things that need fixing due to path/name changes.

/
Leif

Cc: Leif Lindholm <leif.lindholm@...>
Cc: Gilbert Chen <gilbert.chen@...>
---
.../Include/IndustryStandard/RiscV.h | 156 ++++++++++++++++++
.../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 87 ++++++++++
2 files changed, 243 insertions(+)
create mode 100644 Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h

diff --git a/Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000000..2a992394ed
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,156 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001
<< 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 <<
2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION
(0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION
(0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION
(0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 <<
8)
+#define
RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION
(0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 <<
11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001
<< 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED
(0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 <<
15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION
(0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED
(0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION
(0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001
<< 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001
<< 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+ #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+ #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
+ #define SSTATUS_SIE_BIT_POSITION 1
+ #define SSTATUS_SPP_BIT_POSITION 8
+#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
+#define RISCV_CSR_SUPERVISOR_SEPC 0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
+ #define SCAUSE_USER_SOFTWARE_INT 0
+ #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
+ #define SCAUSE_USER_TIMER_INT 4
+ #define SCAUSE_SUPERVISOR_TIMER_INT 5
+ #define SCAUSE_USER_EXTERNAL_INT 8
+ #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
+#define RISCV_CSR_SUPERVISOR_STVAL 0x143
+#define RISCV_CSR_SUPERVISOR_SIP 0x144
+#define RISCV_CSR_SUPERVISOR_SATP 0x180
+
+#if defined (MDE_CPU_RISCV64)
+ #define RISCV_SATP_MODE_MASK 0xF000000000000000
+ #define RISCV_SATP_MODE_BIT_POSITION 60
+#endif
+ #define RISCV_SATP_MODE_OFF 0
+ #define RISCV_SATP_MODE_SV32 1
+ #define RISCV_SATP_MODE_SV39 8
+ #define RISCV_SATP_MODE_SV48 9
+ #define RISCV_SATP_MODE_SV57 10
+ #define RISCV_SATP_MODE_SV64 11
+
+ #define SATP64_ASID_MASK 0x0FFFF00000000000
+ #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
+
+#define RISCV_CAUSE_MISALIGNED_FETCH 0x0
+#define RISCV_CAUSE_FETCH_ACCESS 0x1
+#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define RISCV_CAUSE_BREAKPOINT 0x3
+#define RISCV_CAUSE_MISALIGNED_LOAD 0x4
+#define RISCV_CAUSE_LOAD_ACCESS 0x5
+#define RISCV_CAUSE_MISALIGNED_STORE 0x6
+#define RISCV_CAUSE_STORE_ACCESS 0x7
+#define RISCV_CAUSE_USER_ECALL 0x8
+#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9
+#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa
+#define RISCV_CAUSE_MACHINE_ECALL 0xb
+#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc
+#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd
+#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf
+#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
+#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
+#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
new file mode 100644
index 0000000000..14092df174
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
@@ -0,0 +1,87 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development
LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscV.h>
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ##
Name)
+
+#if defined (MDE_CPU_RISCV64)
+typedef UINT64 RISC_V_REGS_PROTOTYPE;
+#else
+#endif
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT
RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine
mode trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode
trap handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for
machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
--
2.31.1






Re: [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package

Abner Chang
 

Hi Leif,

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Leif
Lindholm
Sent: Monday, January 10, 2022 9:11 PM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
<abner.chang@...>
Cc: Andrew Fish <afish@...>; Michael D Kinney
<michael.d.kinney@...>; Sami Mujawar <Sami.Mujawar@...>
Subject: Re: [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add header
files of RISC-V processor package

On Sat, Jan 08, 2022 at 12:07:53 +0800, Abner Chang wrote:
(This is migrated from edk2-platforms:Silicon/RISC-V)

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@...>
Co-authored-by: Daniel Schaefer <daniel.schaefer@...>
Co-authored-by: Gilbert Chen <gilbert.chen@...>
Reviewed-by: Leif Lindholm <leif.lindholm@...>
Hmm, no.
I gave a reviewed-by for that patch to be merged into edk2-platforms
once upon a time. This is not relevant for migration to edk2.

My proposal for migrating this code would be as follows:
- Announce a hold on merging new code to RiscV portions of
edk2-platforms.
- Apply any and all bugfixes and CI/uncrustify fixes in place in
edk2-platforms.
- Get some level of agreement for what to do instead of
RiscVPlatformPkg - i.e. slot into MdeModulePkg instead.
Is this the idea from edk2 community? To have the platform modules under MdeModulePkg?

- If that cannot be reached within a few days, create a new
top-level directory called "CommonPlatformPkg" or something,
This seems makes more sense than having platform modules in MdeModulePkg, while I don't know the reasons for MdeModulePkg.

with you, Daniel(/Gilbert?), Sami, me as maintainers.
Gilbert moved to ARM. 😊

- Move all of the RiscVPlatformPkg code under there instead.
- I'll follow with ArmPlatformPkg.
- PC/AT code should move across too over time.
I believe you mean to share the same common platform drivers (if this is the case) with the separate libraries for different ARCHs under CommonPlatformPkg?
So what do you imagine the locations of drivers those are specifically to ARM, RISC-V, or X86 under CommonPlatformPkg? Have the second level folders for processor architectures?

Abner

- Move the rest of the code across unmodified as massive single
patches per package (potentially more patches than that for
RiscVPlatformPkg).
- Drop all existing Reviewed-by/Acked-by.
- After each "move" patch, insert a "fixup" patch to address the
things that need fixing due to path/name changes.

/
Leif

Cc: Leif Lindholm <leif.lindholm@...>
Cc: Gilbert Chen <gilbert.chen@...>
---
.../Include/IndustryStandard/RiscV.h | 156 ++++++++++++++++++
.../RISC-V/ProcessorPkg/Include/RiscVImpl.h | 87 ++++++++++
2 files changed, 243 insertions(+)
create mode 100644 Silicon/RISC-
V/ProcessorPkg/Include/IndustryStandard/RiscV.h
create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h

diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000000..2a992394ed
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,156 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001
<< 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001
<< 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001
<< 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
+#define
RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION
(0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 <<
12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001
<< 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001
<< 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001
<< 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION
(0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 <<
20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 <<
23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+ #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+ #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
+ #define SSTATUS_SIE_BIT_POSITION 1
+ #define SSTATUS_SPP_BIT_POSITION 8
+#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
+#define RISCV_CSR_SUPERVISOR_SEPC 0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
+ #define SCAUSE_USER_SOFTWARE_INT 0
+ #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
+ #define SCAUSE_USER_TIMER_INT 4
+ #define SCAUSE_SUPERVISOR_TIMER_INT 5
+ #define SCAUSE_USER_EXTERNAL_INT 8
+ #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
+#define RISCV_CSR_SUPERVISOR_STVAL 0x143
+#define RISCV_CSR_SUPERVISOR_SIP 0x144
+#define RISCV_CSR_SUPERVISOR_SATP 0x180
+
+#if defined (MDE_CPU_RISCV64)
+ #define RISCV_SATP_MODE_MASK 0xF000000000000000
+ #define RISCV_SATP_MODE_BIT_POSITION 60
+#endif
+ #define RISCV_SATP_MODE_OFF 0
+ #define RISCV_SATP_MODE_SV32 1
+ #define RISCV_SATP_MODE_SV39 8
+ #define RISCV_SATP_MODE_SV48 9
+ #define RISCV_SATP_MODE_SV57 10
+ #define RISCV_SATP_MODE_SV64 11
+
+ #define SATP64_ASID_MASK 0x0FFFF00000000000
+ #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
+
+#define RISCV_CAUSE_MISALIGNED_FETCH 0x0
+#define RISCV_CAUSE_FETCH_ACCESS 0x1
+#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define RISCV_CAUSE_BREAKPOINT 0x3
+#define RISCV_CAUSE_MISALIGNED_LOAD 0x4
+#define RISCV_CAUSE_LOAD_ACCESS 0x5
+#define RISCV_CAUSE_MISALIGNED_STORE 0x6
+#define RISCV_CAUSE_STORE_ACCESS 0x7
+#define RISCV_CAUSE_USER_ECALL 0x8
+#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9
+#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa
+#define RISCV_CAUSE_MACHINE_ECALL 0xb
+#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc
+#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd
+#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf
+#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
+#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
+#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/Silicon/RISC-
V/ProcessorPkg/Include/RiscVImpl.h
new file mode 100644
index 0000000000..14092df174
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
@@ -0,0 +1,87 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.
All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscV.h>
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ##
Name)
+
+#if defined (MDE_CPU_RISCV64)
+typedef UINT64 RISC_V_REGS_PROTOTYPE;
+#else
+#endif
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT
RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode
trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor
mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap
handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for
machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
--
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