Date   

Re: 回复: [edk2-devel] [PATCH] MdeModulePkg\CoreDxe: Allow DXE Drivers to use untested memory

Sean
 

if this is auto promotion is happening in the core then what is the value of memory testing and tracking that state. Is memory testing state a necessary feature of the Dxe Core?


I think it makes more sense that if you platform wants to use a given range your platform should either test it and/or mark it as tested.

OR

The dxe core should do away with the memory testing tracking.


On most platforms i have seen in the past few years all memory is marked as tested without doing any testing. The only value in the flag is keep the initial memory allocations in a given low range (below 4gb).

On 1/10/2022 5:59 PM, gaoliming wrote:
Stacy:
This fix covers the case with AllocateAddress allocation type. I agree
this fix. Reviewed-by: Liming Gao <gaoliming@...>
Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Stacy Howell
发送时间: 2022年1月8日 3:36
收件人: devel@edk2.groups.io
抄送: Stacy Howell <stacy.howell@...>; Dandan Bi
<dandan.bi@...>; Liming Gao <gaoliming@...>
主题: [edk2-devel] [PATCH] MdeModulePkg\CoreDxe: Allow DXE Drivers to
use untested memory

REF: https://https://bugzilla.tianocore.org/show_bug.cgi?id=3795
CC: Dandan Bi <dandan.bi@...>
CC: Liming Gao <gaoliming@...>

Updated CoreInternalAllocatePages() to call PromoteMemoryResource() and
re-attempt the allocation if unable to convert the specified memory range

Signed-off-by: Stacy Howell <stacy.howell@...>
---
MdeModulePkg/Core/Dxe/Mem/Page.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c
b/MdeModulePkg/Core/Dxe/Mem/Page.c
index 47d4c5d92e..cc0b90ac0d 100644
--- a/MdeModulePkg/Core/Dxe/Mem/Page.c
+++ b/MdeModulePkg/Core/Dxe/Mem/Page.c
@@ -1417,6 +1417,20 @@ CoreInternalAllocatePages (
Status = CoreConvertPages (Start, NumberOfPages, MemoryType);
}

+ if (EFI_ERROR (Status)) {
+ //
+ // If requested memory region is unavailable it may be untested
memory
+ // Attempt to promote memory resources, then re-attempt the
allocation
+ //
+ if (PromoteMemoryResource ()) {
+ if (NeedGuard) {
+ Status = CoreConvertPagesWithGuard (Start, NumberOfPages,
MemoryType);
+ } else {
+ Status = CoreConvertPages (Start, NumberOfPages, MemoryType);
+ }
+ }
+ }
+
Done:
CoreReleaseMemoryLock ();

--
2.32.0.windows.2





Re: [PATCH] IntelSiliconPkg/IntelVTdDxe: Reduce Debug Level

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: Sheng, W <w.sheng@...>
Sent: Tuesday, January 11, 2022 9:27 AM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...>; Huang, Jenny
<jenny.huang@...>; Kowalewski, Robert <robert.kowalewski@...>
Subject: [PATCH] IntelSiliconPkg/IntelVTdDxe: Reduce Debug Level

Reduce the debug level from DEBUG_INFO to DEBUG_VERBOSE in
function SubmitQueuedInvalidationDescriptor ().

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3801

Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Jenny Huang <jenny.huang@...>
Cc: Robert Kowalewski <robert.kowalewski@...>
Signed-off-by: Sheng Wei <w.sheng@...>
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index 1ce9c1c0..c88f462b 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -238,7 +238,7 @@ SubmitQueuedInvalidationDescriptor (
QiDescLength = mVtdUnitInformation[VtdIndex].QiDescLength;
BaseDesc = mVtdUnitInformation[VtdIndex].QiDesc;

- DEBUG((DEBUG_INFO, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High,
mVtdUnitInformation[VtdIndex].QiFreeHead));
+ DEBUG((DEBUG_VERBOSE, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc-
High, mVtdUnitInformation[VtdIndex].QiFreeHead));
BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].Low = Desc->Low;
BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].High = Desc->High;
--
2.16.2.windows.1


Re: [PATCH] UefiPayloadPkg: Change the user interface name of the Uiapp

Ni, Ray
 

+[Rule.Common.UEFI_APPLICATION.UI]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="Enter Setup"
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
\ No newline at end of file
All looks good to me. But, can you please put a "newline" at end of file?


Event: TianoCore Bug Triage - APAC / NAMO - 01/11/2022 #cal-reminder

devel@edk2.groups.io Calendar <noreply@...>
 

Reminder: TianoCore Bug Triage - APAC / NAMO

When:
01/11/2022
6:30pm to 7:30pm
(UTC-08:00) America/Los Angeles

Where:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTUyZTg2NjgtNDhlNS00ODVlLTllYTUtYzg1OTNjNjdiZjFh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%22b286b53a-1218-4db3-bfc9-3d4c5aa7669e%22%7d

Organizer: Liming Gao gaoliming@...

View Event

Description:

TianoCore Bug Triage - APAC / NAMO

Hosted by Liming Gao

 

________________________________________________________________________________

Microsoft Teams meeting

Join on your computer or mobile app

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Re: [PATCH 08/10] OvmfPkg: Update Sec to support Tdvf Config-B

Min Xu
 

On January 10, 2022 3:56 PM, Gerd Hoffmann wrote:
On Fri, Jan 07, 2022 at 06:13:37AM +0000, Xu, Min M wrote:
On January 3, 2022 4:02 PM, Gerd Hoffmann wrote:

PCDs cannot be set in SEC phase, so the values should be saved in
a Hob (for example, PLATFORM_INFO_HOB). In early DXE phase these
values are set to the PCDs. This is how TdxDxe does today.

Other tasks can be done in SEC phase. I think there should be a
lib (for example, PlatformPeiLib) to wrap these functions so that
they can be re-used by OvmfPkg/PlatformPei.
Yes, I think we need a PlatformLib for the platform initialization
code. With PEI we would simply link the lib into PlatformPei,
without PEI we would link parts of the lib into SEC and parts of the lib into
DXE.

After carefully study the PlatformPei code and a quick PoC
(PlatformInitLib which wraps the basic functions in PlatformPei), I
found it's not a easy task for such a lib which can be used in both
PlatformPei and Pei-less boot.
1. PlatformInitLib should work both in SEC and PEI. So it cannot use
global variables between different functions. mHostBridgeDevId and
mPhysMemAddressWidth are the examples. So these variables must be
provided by the caller thru the input function parameters.
2. PlatformInitLib cannot set PCDs in the code. So a Guid hob should
be created to store the PCDs and pass them to DXE phase. Then these
PCDs will be set at the very beginning of DXE phase.
Yes. Your patches add a PlatformInitHob because of that. I think right now it
only has some tdx-specific variables, but we can move more variables into the
hob to allow platform init code run in both SEC and PEI phase. I think it makes
sense to have the hob in both PEI and PEI-less mode to minimize the code
differences.
Yes, we can use EFI_HOB_PLATFORM_INFO.

4. In PlatformPei there are many if-else to check if it is
SMM/S3/Microvm/Cloud-Hypervisor/SEV/TDX. There are also Bhyve and
Xen
PlatformPei variants. In the current PlatformPei those if-else check
depends on the PCDs and global variables. Because of (1) it needs
input parameters for all these if-else check. Maybe a big environment
variable data structure is needed.
Use PlatformInitHob?
Yes, we can use this data structure.

But anyway a complete functional PlatformInitLib is a big task. My
suggestion is that in TDVF-Config-B we first propose a basic
functional PlatformInitLib. This lib can boot up Tdx guest and legacy
OVMF guest in TDVF-Config-B. OvmfPkg/PlatformPei is not refactored by
this basic PlatformInitLib this time.
Well. The whole point of adding PlatformInitLib is to move over (and refactor if
needed) existing code in PlatformPei so we can avoid code duplication. Now
you want add PlatformInitLib without touching PlatformPei, probably by
copying code. That doesn't make sense at all.

This is because PlatformPei serves
SMM/S3/Microvm/Cloud-Hypervisor/SEV/TDX. It is a big risk for such
refactor. We can revisit PlatformPei in the future.
Well, if you want avoid the refactoring because of the risk there is still the
option to have tdx config-b use the normal PEI boot flow.
Then revisit refactoring and adding support for PEI-less boot later.
I think it still makes sense (Adding a basic PlatformInitLib which brings up tdx guest and legacy guest in Pei-less boot, but not touch PlatformPei).
1. The goal of TDVF-Config-B is to bring up tdx guest and legacy guest without PEI. So that attack surface can be reduced.
2. There are common functions when bring up tdx guest and legacy guest in Config-B. So PlatformInitLib is necessary.
3. As I explained there are many if-else checks in PlatformPei and the logics are rather complicated (because PlatformPei serves S3/SMM/SEV/TDX/Legacy/Microvm/CloudHypervisor, etc). To be honest I have not so much confidence to abstract PlatformPei's common function to PlatformInitLib.
4. But a basic version of PlatformInitLib is a good start. During the development and community review, we can understand better what functions should be wrapped into PlatformInitLib. After that PlatformInitLib can be evolved for OvmfPkg/PlatformPei, Bhyve/PlatformPei, XenPlatformPei.

Thanks
Min


Re: [edk2platforms][PATCH v4 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol

Chaganty, Rangasai V
 

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@...>

-----Original Message-----
From: Czajkowski, Maciej <maciej.czajkowski@...>
Sent: Tuesday, December 07, 2021 7:21 AM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...>
Subject: [edk2platforms][PATCH v4 1/1] IntelSiliconPkg: Add IntelDieInfoProtocol

Added IntelDieInfo header into IntelSiliconPkg tree.
The purpose is to have generic and unified interface for getting information about dies installed in the system.
It will be implemented by silicon code.

Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Signed-off-by: Maciej Czajkowski <maciej.czajkowski@...>
---

Notes:
v4:
- removed Signature field

v3:
- added EDKII_ prefix to interface
- removed GUID definitons from .h file
- corrected descriptions
- made PPI/protocol GUIDs unique

v2:
- added interface description
- added die specific GUIDs into .dec file

Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h | 94 ++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 9 ++
2 files changed, 103 insertions(+)

diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h
new file mode 100644
index 000000000000..bba2908bf598
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/IntelDieInfo.h
@@ -0,0 +1,94 @@
+/** @file+ IntelDieInfo definition++ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef _DIE_INFO_PROTOCOL_H_+#define _DIE_INFO_PROTOCOL_H_++typedef struct _EDKII_INTEL_DIE_INFO_PROTOCOL EDKII_INTEL_DIE_INFO_PROTOCOL;+typedef EDKII_INTEL_DIE_INFO_PROTOCOL EDKII_INTEL_DIE_INFO_PPI;++extern EFI_GUID gIntelDieInfoProtocolGuid;+extern EFI_GUID gIntelDieInfoPpiGuid;++extern EFI_GUID gIntelDieInfoPchGuid;+extern EFI_GUID gIntelDieInfoSocGuid;+extern EFI_GUID gIntelDieInfoIoGuid;+extern EFI_GUID gIntelDieInfoCpuGuid;+extern EFI_GUID gIntelDieInfoGfxGuid;++#define DIE_INFO_PROTOCOL_REVISION 1++/**+ Returns pointer to constant string representing die name.+ Name is specific to die type.++ @param[in] This Pointer to the DieInfoProtocol context structure+ @retval Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_DIE_NAME_STR) (+ IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to constant string representing stepping of the die.++ @param[in] This Pointer to the DieInfoProtocol context structure+ @retval Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_STEPPING_STR) (+ IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Returns pointer to constant string representing SKU of the die.++ @param[in] This Pointer to the DieInfoProtocol context structure+ @retval Pointer to the const string+**/+typedef+CONST CHAR8*+(EFIAPI *EDKII_INTEL_DIE_INFO_GET_SKU_STR) (+ IN EDKII_INTEL_DIE_INFO_PROTOCOL *This+ );++/**+ Protocol/PPI definition.+ The purpose of this interface is to serve die-specific informations in a unified, generic way.+ It will be produced by silicon code per die, and can be consumed by any module that needs contained information.++ <b>Revision 1</b>:+ - Initial version.+**/+struct _EDKII_INTEL_DIE_INFO_PROTOCOL {+ UINT32 Revision; ///< Current protocol revision+ /**+ Type of the die that particular instance is reffering to.+ **/+ EFI_GUID Type;+ /**+ Index of the die in the package.+ **/+ UINT32 DieIndex;+ /**+ Unique ID specific to the die and the associated generation.+ **/+ UINT64 DieId;+ /**+ Generation and die specific stepping ID.+ **/+ UINT32 SteppingId;++ EDKII_INTEL_DIE_INFO_GET_DIE_NAME_STR GetNameStr;+ EDKII_INTEL_DIE_INFO_GET_STEPPING_STR GetSteppingStr;+ EDKII_INTEL_DIE_INFO_GET_SKU_STR GetSkuStr;+};++#endif // _DIE_INFO_PROTOCOL_H_diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index f950c3d1c72b..e5b785ae6204 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -92,12 +92,20 @@ [Guids]
gFlashRegionAllGuid = { 0xbabe60dc, 0xf88d, 0x4584, {0x9e, 0x54, 0x57, 0x44, 0x4b, 0xe2, 0x6e, 0xf3 } } gFlashRegionMaxGuid = { 0x74c2e3c1, 0x8faa, 0x4659, {0xa7, 0xbb, 0x87, 0x1f, 0xbb, 0x61, 0xd3, 0xb4 } } + ## Include/Protocol/IntelDieInfo.h+ gIntelDieInfoPchGuid = { 0x62CB6D68, 0x4771, 0x4569, { 0x81, 0xFA, 0x1E, 0x99, 0x6E, 0xA9, 0x91, 0xC5 }}+ gIntelDieInfoSocGuid = { 0x63287105, 0x578E, 0x4799, { 0xBE, 0x55, 0x5D, 0xDA, 0xCA, 0x03, 0x74, 0xD0 }}+ gIntelDieInfoIoGuid = { 0x23DA4C74, 0x54A0, 0x4E01, { 0x83, 0xB1, 0x8C, 0xA7, 0x43, 0x43, 0x1F, 0xF0 }}+ gIntelDieInfoCpuGuid = { 0x6E5AF2E3, 0x5D84, 0x48F2, { 0x84, 0x28, 0x99, 0xE4, 0x93, 0x4F, 0x51, 0xE4 }}+ gIntelDieInfoGfxGuid = { 0x1D3D2599, 0x7A1C, 0x4B1E, { 0x8C, 0xC5, 0x0F, 0x88, 0x27, 0xA0, 0x2E, 0xEC }}+ [Ppis] ## Include/Ppi/Spi2.h gPchSpi2PpiGuid = { 0x63c40580, 0x10c4, 0x4a8e, { 0xb4, 0x16, 0x86, 0x85, 0x25, 0x7e, 0xce, 0x04 } } gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } }+ gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }} [Protocols] ## Protocols that provide services for the Intel(R) PCH SPI Host Controller Compatibility Interface@@ -107,6 +115,7 @@ [Protocols]
gPchSmmSpi2ProtocolGuid = { 0x2d1c0c43, 0x20d3, 0x40ae, { 0x99, 0x07, 0x2d, 0xf0, 0xe7, 0x91, 0x21, 0xa5 } } gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}+ gIntelDieInfoProtocolGuid = { 0xAED8A0A1, 0xFDE6, 0x4CF2, { 0xA3, 0x85, 0x08, 0xF1, 0x25, 0xF2, 0x40, 0x37 }} ## Protocol for device security policy. # Include/Protocol/PlatformDeviceSecurityPolicy.h--
2.27.0.windows.1


回复: [edk2-devel] [PATCH] MdeModulePkg\CoreDxe: Allow DXE Drivers to use untested memory

gaoliming
 

Stacy:
This fix covers the case with AllocateAddress allocation type. I agree
this fix. Reviewed-by: Liming Gao <gaoliming@...>

Thanks
Liming

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Stacy Howell
发送时间: 2022年1月8日 3:36
收件人: devel@edk2.groups.io
抄送: Stacy Howell <stacy.howell@...>; Dandan Bi
<dandan.bi@...>; Liming Gao <gaoliming@...>
主题: [edk2-devel] [PATCH] MdeModulePkg\CoreDxe: Allow DXE Drivers to
use untested memory

REF: https://https://bugzilla.tianocore.org/show_bug.cgi?id=3795
CC: Dandan Bi <dandan.bi@...>
CC: Liming Gao <gaoliming@...>

Updated CoreInternalAllocatePages() to call PromoteMemoryResource() and
re-attempt the allocation if unable to convert the specified memory range

Signed-off-by: Stacy Howell <stacy.howell@...>
---
MdeModulePkg/Core/Dxe/Mem/Page.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c
b/MdeModulePkg/Core/Dxe/Mem/Page.c
index 47d4c5d92e..cc0b90ac0d 100644
--- a/MdeModulePkg/Core/Dxe/Mem/Page.c
+++ b/MdeModulePkg/Core/Dxe/Mem/Page.c
@@ -1417,6 +1417,20 @@ CoreInternalAllocatePages (
Status = CoreConvertPages (Start, NumberOfPages, MemoryType);
}

+ if (EFI_ERROR (Status)) {
+ //
+ // If requested memory region is unavailable it may be untested
memory
+ // Attempt to promote memory resources, then re-attempt the
allocation
+ //
+ if (PromoteMemoryResource ()) {
+ if (NeedGuard) {
+ Status = CoreConvertPagesWithGuard (Start, NumberOfPages,
MemoryType);
+ } else {
+ Status = CoreConvertPages (Start, NumberOfPages, MemoryType);
+ }
+ }
+ }
+
Done:
CoreReleaseMemoryLock ();

--
2.32.0.windows.2





Issues with CLANGDWARF tool specification and X64 -- am I nuts or what?

Bill Paul <wpaul@...>
 

Hello all:

Recently I discovered that you can enable CSM compatibility mode in OVMF and
decided to build some images with this feature Because Of Reasons (tm). My
platform is:

FreeBSD/amd64 12.2-RELEASE
Clang/LLVM 10.0.1
QEMU 6.2.0

These days FreeBSD uses Clang as its native compiler. 12.2-RELEASE comes with
version 10.0.1, but you also have the option of installing more recent Clang/
LLVM versions up to 12.0.1 as supplemental packages. I noticed that CLANGDWARF
is a supported tool spec for the X64 and IA32 build targets so I decided to
try that.

Unfortunately I ran into a couple of problems:

1) Compilation of OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c fails due to
uninitialized local variable.

/mnt/home/wpaul/edk2/edk2/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c:
1875:9: error: variable 'Compacted' is used uninitialized whenever 'if'
condition is false [-Werror,-Wsometimes-uninitialized]
if (EcxIn == 1) {
^~~~~~~~~~
/mnt/home/wpaul/edk2/edk2/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c:
1895:12: note: uninitialized use occurs here
Compacted
^~~~~~~~~
/mnt/home/wpaul/edk2/edk2/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c:
1875:5: note: remove the 'if' if its condition is always true
if (EcxIn == 1) {
^~~~~~~~~~~~~~~~
/mnt/home/wpaul/edk2/edk2/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c:
1871:37: note: initialize the variable 'Compacted' to silence this warning
BOOLEAN Compacted;
^
= '\0'

I changed line 1871 to:

BOOLEAN Compacted = FALSE;

and that fixed it. I suspect this may be a case where Clang is being a bit
more strict than GCC about uninitialized variables.

2) Linking fails with numerous errors of the following kind:

ld.lld: error: can't create dynamic relocation R_X86_64_64 against local
symbol in readonly segment; recompile object files with -fPIC or pass '-Wl,-
z,notext' to allow text relocations in the output
defined in /mnt/home/wpaul/edk2/edk2/Build/OvmfX64/RELEASE_CLANGDWARF/X64/
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib/OUTPUT/
SecPeiCpuExceptionHandlerLib.lib(ExceptionHandlerAsm.obj)

If I edit tools_def.txt and change RELEASE_CLANGDWARF_X64_DLINK_FLAGS so that
it includes -Wl,-z,notext as the error suggests, then everything links as
expected. (The same thing is needed for DEBUG_CLANGDWARF_X64_DLINK_FLAGS and
probably NOOPT_CLANGDWARF_X64_DLINK_FLAGS.)

This problem only occurs when building for X64. IA32 seems ok.

Is there any particular reason why these flags aren't there already?

3) Although fixing the above two problems allows me to produce a complete
OVMF.fd image, it crashes at start-up with the runtime error:

!!!! X64 Exception Type - 06(#UD - Invalid Opcode) CPU Apic ID - 00000000
!!!!
RIP - 000000007EC8A7DB, CS - 0000000000000038, RFLAGS - 0000000000010206
RAX - 0000000000000000, RCX - 000000007F5A0880, RDX - 000000007FF2BAE0
RBX - 000000007FF2BBF0, RSP - 000000007FF2BB20, RBP - 000000005A1C5000
RSI - 000000007FF2BB48, RDI - 0000000000000000
R8 - 0000000000000008, R9 - 0000000000000000, R10 - 0000000000000000
R11 - 000000007FF41C90, R12 - 0000000000058080, R13 - 000000007FF2BC20
R14 - 00000000000F6DB0, R15 - 0000000000000000
DS - 0000000000000030, ES - 0000000000000030, FS - 0000000000000030
GS - 0000000000000030, SS - 0000000000000030
CR0 - 0000000080010033, CR2 - 0000000000000000, CR3 - 000000007FC01000
CR4 - 0000000000000668, CR8 - 0000000000000000
DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000
DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400
GDTR - 000000007F9EC000 0000000000000047, LDTR - 0000000000000000
IDTR - 000000007F5A4018 0000000000000FFF, TR - 0000000000000000
FXSAVE_STATE - 000000007FF2B780
!!!! Find image based on IP(0x7EC8A7DB) (No PDB) (ImageBase=000000007EC87000,
EntryPoint=000000007EC8D7A6) !!!!

The same thing occurs for IA32:

!!!! IA32 Exception Type - 06(#UD - Invalid Opcode) CPU Apic ID - 00000000
!!!!
EIP - 7ECF72D4, CS - 00000010, EFLAGS - 00010206
EAX - 00000008, ECX - 00000000, EDX - 7F8EEE10, EBX - 5000A19D
ESP - 7FF33D44, EBP - 7FF33E4C, ESI - 7FF33D4C, EDI - 7ECFB04C
DS - 00000008, ES - 00000008, FS - 00000008, GS - 00000008, SS - 00000008
CR0 - 80010033, CR2 - 00000000, CR3 - 7FC01000, CR4 - 00000660
DR0 - 00000000, DR1 - 00000000, DR2 - 00000000, DR3 - 00000000
DR6 - FFFF0FF0, DR7 - 00000400
GDTR - 7F9EC000 00000047, IDTR - 7F5E5010 000007FF
LDTR - 00000000, TR - 00000000
FXSAVE_STATE - 7FF33A80
!!!! Find image based on IP(0x7ECF72D4) (No PDB) (ImageBase=000000007ECF4000,
EntryPoint=000000007ECF9FBD) !!!!

This one had me going for a while, but I eventually traced it down to
LegacyBiosInt86() in OvmfPkg/Csm/LegacyBiosDxe/Thunk.c.

In that function, there is this code:

UINT16 Segment;
UINT16 Offset;
[...]
//
// The base address of legacy interrupt vector table is 0.
// We use this base address to get the legacy interrupt handler.
//
ACCESS_PAGE0_CODE (
Segment = (UINT16)(((UINT32 *)0)[BiosInt] >> 16);
Offset = (UINT16)((UINT32 *)0)[BiosInt];
);

As the comment notes, here, we're trying to directly read from address 0 using
BiosInt as an offset. This seems to trigger a problem with the Clang
optimizer. The disassembled output looks like this:

0000000000003786 <LegacyBiosInt86>:
3786: 56 push %rsi
3787: 48 83 ec 60 sub $0x60,%rsp
378b: 41 0f b7 40 18 movzwl 0x18(%r8),%eax
3790: 25 d4 0c 00 00 and $0xcd4,%eax
3795: 0d 02 30 00 00 or $0x3002,%eax
379a: 66 41 89 40 18 mov %ax,0x18(%r8)
379f: 48 8d 74 24 28 lea 0x28(%rsp),%rsi
37a4: 48 83 66 18 00 andq $0x0,0x18(%rsi)
37a9: 48 8b 05 a8 59 00 00 mov 0x59a8(%rip),%rax # 9158
<gDS>
37b0: 31 c9 xor %ecx,%ecx
37b2: 48 89 f2 mov %rsi,%rdx
37b5: ff 50 38 call *0x38(%rax)
37b8: 4c 8b 46 18 mov 0x18(%rsi),%r8
37bc: 41 0f ba e0 0d bt $0xd,%r8d
37c1: 73 18 jae 37db <LegacyBiosInt86+0x55>
37c3: 48 8b 05 8e 59 00 00 mov 0x598e(%rip),%rax # 9158
<gDS>
37ca: 49 81 e0 ff df ff ff and $0xffffffffffffdfff,%r8
37d1: ba 00 10 00 00 mov $0x1000,%edx
37d6: 31 c9 xor %ecx,%ecx
37d8: ff 50 40 call *0x40(%rax)
37db: 0f 0b ud2 <--- er... what?

Note the "ud2" instruction. I have no idea what that's supposed to be, but it
looks like Clang just gives up generating any further instructions once it
hits this code.

I reduced this to a very simple sample C program that also reproduces the
problem:

#include <stdint.h>

extern int somefunc (uint16_t s, uint16_t o);

int
foo (uint8_t BiosInt)
{
uint16_t Segment;
uint16_t Offset;

Segment = (uint16_t)(((uint32_t *)0)[BiosInt] >> 16);
Offset = (uint16_t)((uint32_t *)0)[BiosInt];

return somefunc (Segment, Offset);
}

If I compile this with:

% clang -O2 -c edk.c

then I get this:

0000000000000000 <foo>:
0: 55 push %rbp
1: 48 89 e5 mov %rsp,%rbp
4: 0f 0b ud2

If I compile with GCC instead:

% gcc10 -O2 -c edk.c

then I get this:

0000000000000000 <foo>:
0: 40 0f b6 ff movzbl %dil,%edi
4: 8b 3c bd 00 00 00 00 mov 0x0(,%rdi,4),%edi
b: 0f b7 f7 movzwl %di,%esi
e: c1 ef 10 shr $0x10,%edi
11: e9 00 00 00 00 jmp 16 <foo+0x16>

If I compile with Clang using -O0 to disable optimization, then it produces
code:

0000000000000000 <foo>:
0: 55 push %rbp
1: 48 89 e5 mov %rsp,%rbp
4: 48 83 ec 10 sub $0x10,%rsp
8: 31 c0 xor %eax,%eax
a: 89 c1 mov %eax,%ecx
c: 40 88 7d ff mov %dil,-0x1(%rbp)
10: 0f b6 45 ff movzbl -0x1(%rbp),%eax
14: 89 c2 mov %eax,%edx
16: 8b 04 91 mov (%rcx,%rdx,4),%eax
19: c1 e8 10 shr $0x10,%eax
1c: 66 89 45 fc mov %ax,-0x4(%rbp)
20: 0f b6 75 ff movzbl -0x1(%rbp),%esi
24: 89 f2 mov %esi,%edx
26: 8b 34 91 mov (%rcx,%rdx,4),%esi
29: 66 89 75 fa mov %si,-0x6(%rbp)
2d: 66 8b 45 fc mov -0x4(%rbp),%ax
31: 0f b7 f8 movzwl %ax,%edi
34: 0f b7 75 fa movzwl -0x6(%rbp),%esi
38: e8 00 00 00 00 call 3d <foo+0x3d>
3d: 48 83 c4 10 add $0x10,%rsp
41: 5d pop %rbp
42: c3 ret

Note that this is with Clang 10.0.1, however I observe exactly the same
results with Clang 12.0.1.

I was able to fix this locally (for both X64 and IA32 targets) this by doing
this:

UINT16 Segment;
UINT16 Offset;
volatile UINT32 * Page0 = NULL;
[...]
ACCESS_PAGE0_CODE (
Segment = (UINT16)(Page0[BiosInt] >> 16);
Offset = (UINT16)Page0[BiosInt];
);

Note that the addition of the volatile keyword seems to be the key. If you
wanted to make the change simpler, you could also just do this:

ACCESS_PAGE0_CODE (
Segment = (UINT16)(((volatile UINT32 *)0)[BiosInt] >> 16);
Offset = (UINT16)((volatile UINT32 *)0)[BiosInt];
);

(To my eyes, the other way is more readable, but others may disagree.)

With these three issues fixed, I'm able to boot and run my OVMF.fd images for
both X64 and IA32, and they're able to also boot and run the loaders and OS
images that I'm testing.

I'm not sure how much testing the CLANGDWARF toolspec is getting these days,
but maybe it should get a little more. Is there any chance these issues could
be addressed?

-Bill

--
=============================================================================
-Bill Paul (510) 749-2329 | VxWorks Software Architect,
wpaul@... | Master of Unix-Fu - Wind River Systems
=============================================================================
"I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================


[PATCH] IntelSiliconPkg/IntelVTdDxe: Reduce Debug Level

Sheng Wei
 

Reduce the debug level from DEBUG_INFO to DEBUG_VERBOSE in
function SubmitQueuedInvalidationDescriptor ().

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3801

Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Jenny Huang <jenny.huang@...>
Cc: Robert Kowalewski <robert.kowalewski@...>
Signed-off-by: Sheng Wei <w.sheng@...>
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index 1ce9c1c0..c88f462b 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -238,7 +238,7 @@ SubmitQueuedInvalidationDescriptor (
QiDescLength = mVtdUnitInformation[VtdIndex].QiDescLength;
BaseDesc = mVtdUnitInformation[VtdIndex].QiDesc;

- DEBUG((DEBUG_INFO, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High, mVtdUnitInformation[VtdIndex].QiFreeHead));
+ DEBUG((DEBUG_VERBOSE, "[%d] Submit QI Descriptor [0x%08x, 0x%08x] Free Head (%d)\n", VtdIndex, Desc->Low, Desc->High, mVtdUnitInformation[VtdIndex].QiFreeHead));

BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].Low = Desc->Low;
BaseDesc[mVtdUnitInformation[VtdIndex].QiFreeHead].High = Desc->High;
--
2.16.2.windows.1


Re: [PATCH] Wiki: Add optional steps for developer to run CI test before sending

Guomin Jiang
 

Reviewed-by: Guomin Jiang <guomin.jiang@...>

Guomin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Zhiguang Liu
Sent: Monday, January 10, 2022 11:26 AM
To: devel@edk2.groups.io
Cc: Gao, Liming <gaoliming@...>
Subject: [edk2-devel] [PATCH] Wiki: Add optional steps for developer to run
CI test before sending

Cc: Liming Gao <gaoliming@...>
Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---
EDK-II-Development-Process.md | 60
+++++++++++++++++++++++++++++++++++++++++++++---------------
1 file changed, 45 insertions(+), 15 deletions(-)

diff --git a/EDK-II-Development-Process.md b/EDK-II-Development-
Process.md
index 469a979..747c6e1 100644
--- a/EDK-II-Development-Process.md
+++ b/EDK-II-Development-Process.md
@@ -59,20 +59,50 @@ The developer process for the EDK II project

`$ git rebase origin/master`

-9. Run the automated code formatting tool (Uncrustify) against your
changes

-

- - [EDK-II-Code-Formatting](EDK-II-Code-Formatting "wikilink")

-

- - The changes must pass local CI which includes a code formatting check

- in order to be merged into the code base.

-

- - It is strongly recommended that you format the code after each commit.

- The code can then be easily amended with the formatted output. Some

- developers might also prefer to format frequently while writing the

- code using the plugin instructions described in the code formatting

- wiki page.

-

-10. Create patch (serial) to the [[edk2-devel]] mailing list

+9. Run the automated code formatting tool (Uncrustify) against your
changes
+
+ - [EDK-II-Code-Formatting](EDK-II-Code-Formatting "wikilink")
+
+ - The changes must pass local CI which includes a code formatting check
+ in order to be merged into the code base.
+
+ - It is strongly recommended that you format the code after each commit.
+ The code can then be easily amended with the formatted output. Some
+ developers might also prefer to format frequently while writing the
+ code using the plugin instructions described in the code formatting
+ wiki page.
+
+10. (Optional) Push changes to the developer's fork of the EDK II project
+ repository.
+
+ - How to create a [GitHub
fork](https://help.github.com/en/github/getting-started-with-github/fork-
a-repo)
+ - **NOTE:** A GitHub fork can also be created using the command line
+ utility called [`hub`](https://github.com/github/hub/releases). The
+ `hub` usage information can be found
[here](https://hub.github.com/hub.1.html).
+
+ - Add remote to the developer's fork of the EDK II project
+
+ `$ git remote add <developer-id> https://github.com/<developer-
id>/edk2.git`
+
+ - Push the integration branch.
+
+ `$ git push <developer-id> <new-integration-branch>`
+
+11. (Optional) Create a GitHub pull request from the developer's
+ <new-integration-branch> to edk2/master to run CI check.
+
+ - How to create a [GitHub pull
request](https://help.github.com/en/github/collaborating-with-issues-and-
pull-requests/creating-a-pull-request)
+ - **NOTE:** A GitHub pull request can also be created using the
command
+ line utility called [`hub`](https://github.com/github/hub/releases).
+ The `hub` usage information can be found
[here](https://hub.github.com/hub.1.html).
+
+ - Declare that it is for CI check test in the pull request title and
+ description.
+
+ - Resolve GitHub pull request issues if it fails. Please refrence step 8
+ in the below **The maintainer process for the EDK II project**
+
+12. Create patch (serial) to the [[edk2-devel]] mailing list

- Clean out any old patches: `$ rm *.patch`

@@ -86,7 +116,7 @@ The developer process for the EDK II project

- `$ git send-email *.patch`

-11. Modify local commits based on the review feedbacks and repeat steps

+13. Modify local commits based on the review feedbacks and repeat steps
3 to 9

- For the latest commit, you can use `$ git commit --amend`
--
2.32.0.windows.2



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回复: [edk2-devel] [PATCH] Wiki: Add optional steps for developer to run CI test before sending

gaoliming
 

Zhiguang:
Thanks for your update. Reviewed-by: Liming Gao <gaoliming@...>

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Zhiguang Liu
发送时间: 2022年1月10日 11:26
收件人: devel@edk2.groups.io
抄送: Liming Gao <gaoliming@...>
主题: [edk2-devel] [PATCH] Wiki: Add optional steps for developer to run
CI
test before sending

Cc: Liming Gao <gaoliming@...>
Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---
EDK-II-Development-Process.md | 60
+++++++++++++++++++++++++++++++++++++++++++++---------------
1 file changed, 45 insertions(+), 15 deletions(-)

diff --git a/EDK-II-Development-Process.md
b/EDK-II-Development-Process.md
index 469a979..747c6e1 100644
--- a/EDK-II-Development-Process.md
+++ b/EDK-II-Development-Process.md
@@ -59,20 +59,50 @@ The developer process for the EDK II project

`$ git rebase origin/master`

-9. Run the automated code formatting tool (Uncrustify) against your
changes

-

- - [EDK-II-Code-Formatting](EDK-II-Code-Formatting "wikilink")

-

- - The changes must pass local CI which includes a code formatting
check

- in order to be merged into the code base.

-

- - It is strongly recommended that you format the code after each
commit.

- The code can then be easily amended with the formatted output.
Some

- developers might also prefer to format frequently while writing the

- code using the plugin instructions described in the code formatting

- wiki page.

-

-10. Create patch (serial) to the [[edk2-devel]] mailing list

+9. Run the automated code formatting tool (Uncrustify) against your
changes
+
+ - [EDK-II-Code-Formatting](EDK-II-Code-Formatting "wikilink")
+
+ - The changes must pass local CI which includes a code formatting
check
+ in order to be merged into the code base.
+
+ - It is strongly recommended that you format the code after each
commit.
+ The code can then be easily amended with the formatted output.
Some
+ developers might also prefer to format frequently while writing the
+ code using the plugin instructions described in the code formatting
+ wiki page.
+
+10. (Optional) Push changes to the developer's fork of the EDK II project
+ repository.
+
+ - How to create a [GitHub
fork](https://help.github.com/en/github/getting-started-with-github/fork-a-r
epo)
+ - **NOTE:** A GitHub fork can also be created using the command
line
+ utility called [`hub`](https://github.com/github/hub/releases).
The
+ `hub` usage information can be found
[here](https://hub.github.com/hub.1.html).
+
+ - Add remote to the developer's fork of the EDK II project
+
+ `$ git remote add <developer-id>
https://github.com/<developer-id>/edk2.git`
+
+ - Push the integration branch.
+
+ `$ git push <developer-id> <new-integration-branch>`
+
+11. (Optional) Create a GitHub pull request from the developer's
+ <new-integration-branch> to edk2/master to run CI check.
+
+ - How to create a [GitHub pull
request](https://help.github.com/en/github/collaborating-with-issues-and-pu
ll-requests/creating-a-pull-request)
+ - **NOTE:** A GitHub pull request can also be created using the
command
+ line utility called
[`hub`](https://github.com/github/hub/releases).
+ The `hub` usage information can be found
[here](https://hub.github.com/hub.1.html).
+
+ - Declare that it is for CI check test in the pull request title and
+ description.
+
+ - Resolve GitHub pull request issues if it fails. Please refrence
step 8
+ in the below **The maintainer process for the EDK II project**
+
+12. Create patch (serial) to the [[edk2-devel]] mailing list

- Clean out any old patches: `$ rm *.patch`

@@ -86,7 +116,7 @@ The developer process for the EDK II project

- `$ git send-email *.patch`

-11. Modify local commits based on the review feedbacks and repeat steps

+13. Modify local commits based on the review feedbacks and repeat steps
3 to 9

- For the latest commit, you can use `$ git commit --amend`
--
2.32.0.windows.2



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回复: [edk2-devel] [PATCH v2 1/6] MdeModulePkg: VariableSmmRuntimeDxe: Fix Variable Policy Message Length

gaoliming
 

Reviewed-by: Liming Gao <gaoliming@...>

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Kun Qin
发送时间: 2021年12月21日 9:33
收件人: devel@edk2.groups.io
抄送: Jian J Wang <jian.j.wang@...>; Liming Gao
<gaoliming@...>; Hao A Wu <hao.a.wu@...>; Bret
Barkelew <Bret.Barkelew@...>; Michael Kubacki
<michael.kubacki@...>
主题: [edk2-devel] [PATCH v2 1/6] MdeModulePkg: VariableSmmRuntimeDxe:
Fix Variable Policy Message Length

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3709

In EDKII implementation of variable policy, the DXE runtime agent would
communicate to MM to disable, register or query policies. However, these
operations populate the value of MessageLength that includes communicate
header to include MM communicate header, which mismatches with the
description of PI specification.

This fix will correct the MessageLength field calculation to exclude
the size of MM_COMMUNICATE_HEADER.

Cc: Jian J Wang <jian.j.wang@...>
Cc: Liming Gao <gaoliming@...>
Cc: Hao A Wu <hao.a.wu@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Michael Kubacki <michael.kubacki@...>

Signed-off-by: Kun Qin <kuqin12@...>
---

Notes:
v2:
- No review, no updates

MdeModulePkg/Universal/Variable/RuntimeDxe/VariablePolicySmmDxe.c |
10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git
a/MdeModulePkg/Universal/Variable/RuntimeDxe/VariablePolicySmmDxe.c
b/MdeModulePkg/Universal/Variable/RuntimeDxe/VariablePolicySmmDxe.c
index 672a2293bcb1..b2094fbcd6ea 100644
---
a/MdeModulePkg/Universal/Variable/RuntimeDxe/VariablePolicySmmDxe.c
+++
b/MdeModulePkg/Universal/Variable/RuntimeDxe/VariablePolicySmmDxe.c
@@ -89,7 +89,7 @@ ProtocolDisableVariablePolicy (
CommHeader = mMmCommunicationBuffer;
PolicyHeader = (VAR_CHECK_POLICY_COMM_HEADER
*)&CommHeader->Data;
CopyGuid (&CommHeader->HeaderGuid,
&gVarCheckPolicyLibMmiHandlerGuid);
- CommHeader->MessageLength = BufferSize;
+ CommHeader->MessageLength = BufferSize - OFFSET_OF
(EFI_MM_COMMUNICATE_HEADER, Data);
PolicyHeader->Signature = VAR_CHECK_POLICY_COMM_SIG;
PolicyHeader->Revision = VAR_CHECK_POLICY_COMM_REVISION;
PolicyHeader->Command =
VAR_CHECK_POLICY_COMMAND_DISABLE;
@@ -138,7 +138,7 @@ ProtocolIsVariablePolicyEnabled (
PolicyHeader = (VAR_CHECK_POLICY_COMM_HEADER
*)&CommHeader->Data;
CommandParams = (VAR_CHECK_POLICY_COMM_IS_ENABLED_PARAMS
*)(PolicyHeader + 1);
CopyGuid (&CommHeader->HeaderGuid,
&gVarCheckPolicyLibMmiHandlerGuid);
- CommHeader->MessageLength = BufferSize;
+ CommHeader->MessageLength = BufferSize - OFFSET_OF
(EFI_MM_COMMUNICATE_HEADER, Data);
PolicyHeader->Signature = VAR_CHECK_POLICY_COMM_SIG;
PolicyHeader->Revision = VAR_CHECK_POLICY_COMM_REVISION;
PolicyHeader->Command =
VAR_CHECK_POLICY_COMMAND_IS_ENABLED;
@@ -213,7 +213,7 @@ ProtocolRegisterVariablePolicy (
PolicyHeader = (VAR_CHECK_POLICY_COMM_HEADER
*)&CommHeader->Data;
PolicyBuffer = (VOID *)(PolicyHeader + 1);
CopyGuid (&CommHeader->HeaderGuid,
&gVarCheckPolicyLibMmiHandlerGuid);
- CommHeader->MessageLength = BufferSize;
+ CommHeader->MessageLength = BufferSize - OFFSET_OF
(EFI_MM_COMMUNICATE_HEADER, Data);
PolicyHeader->Signature = VAR_CHECK_POLICY_COMM_SIG;
PolicyHeader->Revision = VAR_CHECK_POLICY_COMM_REVISION;
PolicyHeader->Command =
VAR_CHECK_POLICY_COMMAND_REGISTER;
@@ -270,7 +270,7 @@ DumpVariablePolicyHelper (
PolicyHeader = (VAR_CHECK_POLICY_COMM_HEADER
*)&CommHeader->Data;
CommandParams = (VAR_CHECK_POLICY_COMM_DUMP_PARAMS
*)(PolicyHeader + 1);
CopyGuid (&CommHeader->HeaderGuid,
&gVarCheckPolicyLibMmiHandlerGuid);
- CommHeader->MessageLength = BufferSize;
+ CommHeader->MessageLength = BufferSize - OFFSET_OF
(EFI_MM_COMMUNICATE_HEADER, Data);
PolicyHeader->Signature = VAR_CHECK_POLICY_COMM_SIG;
PolicyHeader->Revision = VAR_CHECK_POLICY_COMM_REVISION;
PolicyHeader->Command =
VAR_CHECK_POLICY_COMMAND_DUMP;
@@ -397,7 +397,7 @@ ProtocolLockVariablePolicy (
CommHeader = mMmCommunicationBuffer;
PolicyHeader = (VAR_CHECK_POLICY_COMM_HEADER
*)&CommHeader->Data;
CopyGuid (&CommHeader->HeaderGuid,
&gVarCheckPolicyLibMmiHandlerGuid);
- CommHeader->MessageLength = BufferSize;
+ CommHeader->MessageLength = BufferSize - OFFSET_OF
(EFI_MM_COMMUNICATE_HEADER, Data);
PolicyHeader->Signature = VAR_CHECK_POLICY_COMM_SIG;
PolicyHeader->Revision = VAR_CHECK_POLICY_COMM_REVISION;
PolicyHeader->Command =
VAR_CHECK_POLICY_COMMAND_LOCK;
--
2.32.0.windows.1





Re: [PATCH 00/79] Migration of RiscV*Pkg

Abner Chang
 

I forget this again. I am going to create one for this.
Thanks
Abner

-----Original Message-----
From: gaoliming <gaoliming@...>
Sent: Tuesday, January 11, 2022 9:01 AM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
<abner.chang@...>
Cc: 'Sean Brogan' <sean.brogan@...>; 'Bret Barkelew'
<Bret.Barkelew@...>; 'Michael D Kinney'
<michael.d.kinney@...>; 'Leif Lindholm' <leif@...>;
Schaefer, Daniel (ROM Janitor) <daniel.schaefer@...>; 'Sunil V L'
<sunilvl@...>
Subject: 回复: [edk2-devel] [PATCH 00/79] Migration of RiscV*Pkg

Abner:
Is there one BZ for this migration?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Abner
Chang
发送时间: 2022年1月8日 10:26
收件人: devel@edk2.groups.io
抄送: abner.chang@...; Sean Brogan <sean.brogan@...>;
Bret Barkelew <Bret.Barkelew@...>; Michael D Kinney
<michael.d.kinney@...>; Leif Lindholm <leif@...>; Liming
Gao <gaoliming@...>; Daniel Schaefer
<daniel.schaefer@...>; Sunil V L <sunilvl@...>
主题: [edk2-devel] [PATCH 00/79] Migration of RiscV*Pkg

This is the migration of RISC-V related packages from edk2-platforms repo
to
edk2 repo, as the RISC-V edk2 port is getting mature and the demands of
RISC-V
edk2 port is increasing. RiscVVirtPKg is the next RISC-V edk2 package to
upstream to edk2 repo, which is built base on edk2 RiscVPkg and
RiscVPlatformPkg
for RISC-V QEMU port. The edk2 port drivers for RISC-V processor,
peripherals,
and the implemetation of industry standards (such as UEFI/ACPI/RISC-V
related specs) are also emulated base on RisVVirtPkg.

* Patches you can ignore:
Commit/Patch ca3c581e(1/79)-d3f147c4(61/79) are originally located in
edk2-platforms repo. Those patches had been reviewed and the commit
message
are all preserved for the migration.

*- Patches require review:
1. Commit/Patch 9aad8c35(62/79) and b284fa42(63/79) are the changes
to rename
RISC-V PlatformPkg and ProcessorPkg to RiscVPlatformPkg and
RiscVPkg.
2. Commit/Patch 6955062e(64/79) and a786bc26(65/79) are build error
fixes.
3. Commit/Patch c1fe0fe9(66/79) addes a git submodule for RISC-V
OpenSBI.
4. The rest of patches are the fixes for edk2 Core CI.
The patches for edk2 core CI fixes are created base on the CI test
items
but not base on the package owner or module, because those changes
are all
belong to RiscV*Pkg for CI issues and have no functional changes.

Signed-off-by: Abner Chang <abner.chang@...>
Cc: Sean Brogan <sean.brogan@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Leif Lindholm <leif@...>
Cc: Liming Gao <gaoliming@...>
Cc: Daniel Schaefer <daniel.schaefer@...>
Cc: Sunil V L <sunilvl@...>

Abner Chang (65):
ProcessorPkg/Include: Add header files of RISC-V processor package
ProcessorPkg/Library: RISC-V CPU library
ProcessorPkg/Library: Add RISC-V exception library
ProcessorPkg/Library: Add RISC-V timer library
ProcessorPkg/RiscVOpensbLib: Add opensbi submodule
ProcessorPkg/Library: Add RiscVOpensbiLib
ProcessorPkg/Library: RISC-V PEI Service Table Pointer library
ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver.
ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
platforms.
ProcesorPkg/Library: NULL instance of RISC-V platform timer library.
RISC-V/ProcessorPkg: RISC-V package.
PlatformPkg/Library: RISC-V Platform Temporary Memory library
PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module
PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib
PlatformPkg/Library: NULL instance of PlatformMemoryTestLib
PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib
PlatformPkg/Library: Platform Boot Manager library.
PlatformPkg/SecMain: RISC-V SecMain module.
PlatformPkg: Add RiscVPlatformPkg
RISC-V/PlatformPkg: Revise Readme.md
Silicon/SiFive: Handle case of NULL FirmwareContext
Silicon/RISC-V: Update old SMBIOS struct filed name
U5SeriesPkg: Deduplicate PlatformPei
RISC-V: Split SMBIOS out of PlatformPei
RISC-V: Use U5 SMBIOS library only for those platforms
Silicon/RISC-V: Introduce FirmwareContext library
Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib
RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB
RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table
RISC-V: Switch to latest OpenSBI
RISC-V: Implement ResetSystem RT call
Move OpenSbiPlatformLib to RISC-V/PlatformPkg
RISC-V/PlatformPkg: Update document
RISC-V: Add RISC-V PeiCoreEntryPoint library
RISC-V: Create opensbi firmware domains
RISC-V: Use RISC-V PeiCoreEntryPoint library
Platform/RISC-V: Add library to get PPI descriptor
Platform/RISC-V: Use PlatformSecPpiLib
Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
Platform/RISC-V: Remove platform dependency from common platform
lib
Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull
RiscVPlatformPkg/Sec: Initial hart_index2Id array
RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
RiscVPkg: Update opensbi library
RiscVPlatformPkg/Sec: Check Cold/Warm hart
RiscVPlatformPkg/Sec: Add more comments to Secmain.c
RiscV/ProcessorPkg: Create read mtime CSR library instances
RiscV/ProcessorPkg: Use mtime CSR library
RISC-V/PlatformPkg: Updates for the latest OpenSBI
PlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
RISC-V/PlatformPkg: Determine hart number from DTB
Silicon/RISC-V: Add PciCpuIoDxe driver
Platform/RISC-V: Add debug message to SecMain.c
Platform/RISC-V: Initialize variable to zero
RiscVPlatformPkg: Rename PlatformPkg to RiscVPlatformPkg
RiscVPkg: Rename ProcessorPkg to RiscVPkg
RiscVPkg: Fix build fail on RiscVPkg package
RiscVPkg/PlatformPei: Fix the build error
edk2:.gitmodules
RiscVPlatformPkg: Address Core CI ECC errors.
RiscVPkg: Address Core CI ECC errors.
edk2: RiscVPlatformPkg Core CI YAML file
edk2: RiscVPkg Core CI YAML file
edk2: Enable Core CI on RiscV*Pkg

Dandan Bi (2):
Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib
Silicon/RISC_V: Consume MdeLibs.dsc.inc for RegisterFilterLib

Daniel Schaefer (4):
ProcessorPkg/Library: Add RiscVEdk2SbiLib
RISC-V/CpuDxe: Ignore set memory attributes failure
Signal EndOfDxe in boot manager
RISC-V/PlatformPkg: Build DeviceTree and use that in SEC

changab (8):
RiscVPlatformVPkg: Address Core CI Spelling errors.
RiscVPlatformVPkg: Address Core CI package dependency check errors
RiscVPlatformVPkg: Address Core CI license check errors.
RiscVPlatformVPkg: Address Core CI library header check errors
RiscVPlatformVPkg: Address Core CI Uncrustify errors
RiscVPkg: Address Core CI library header check errors
RiscVPkg: Address Core CI Spelling errors.
RiscVPkg: Address Core CI Uncrustify errors

RiscVPkg/RiscVPkg.dec | 50 +
RiscVPlatformPkg/RiscVPlatformPkg.dec | 94 +
RiscVPkg/RiscVPkg.dsc | 109 +
RiscVPlatformPkg/RiscVPlatformPkg.dsc | 95 +
.../PeiServicesTablePointerLibOpenSbi.inf | 39 +
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 +
.../RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 28 +
.../CpuExceptionHandlerDxeLib.inf | 43 +
.../RiscVFirmwareContextSbiLib.inf | 34 +
.../RiscVFirmwareContextSscratchLib.inf | 33 +
.../RiscVFirmwareContextStvecLib.inf | 34 +
.../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +
.../RiscVPlatformTimerLib.inf | 35 +
.../EmulatedMachineModeTimerLib.inf | 34 +
.../MachineModeTimerLib.inf | 38 +
.../RiscVTimerLib/BaseRiscVTimerLib.inf | 35 +
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 49 +
RiscVPkg/Universal/FdtDxe/FdtDxe.inf | 53 +
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 +
.../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 +
.../Edk2OpensbiPlatformWrapperLib.inf | 44 +
.../FirmwareContextProcessorSpecificLib.inf | 31 +
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 50 +
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +
.../PeiCoreInfoHobLib.inf | 43 +
.../PlatformBootManagerLib.inf | 55 +
.../PlatformMemoryTestLibNull.inf | 27 +
.../PlatformSecPpiLibNull.inf | 32 +
.../PlatformUpdateProgressLibNull.inf | 28 +
.../Library/ResetSystemLib/ResetSystemLib.inf | 32 +
.../RiscVPlatformTempMemoryInitLibNull.inf | 38 +
.../RiscVSpecialPlatformLibNull.inf | 36 +
.../Universal/FdtPeim/FdtPeim.inf | 46 +
.../Universal/Pei/PlatformPei/PlatformPei.inf | 66 +
RiscVPlatformPkg/Universal/Sec/SecMain.inf | 79 +
RiscVPkg/Include/IndustryStandard/RiscV.h | 162 ++
.../Include/IndustryStandard/RiscVOpensbi.h | 62 +
.../Include/Library/MachineModeTimerLib.h | 17 +
RiscVPkg/Include/Library/RiscVCpuLib.h | 118 +
RiscVPkg/Include/Library/RiscVEdk2SbiLib.h | 596 +++++
.../Include/Library/RiscVFirmwareContextLib.h | 43 +
.../Include/Library/RiscVPlatformTimerLib.h | 25 +
RiscVPkg/Include/OpensbiTypes.h | 82 +
RiscVPkg/Include/ProcessorSpecificHobData.h | 97 +
RiscVPkg/Include/RiscVImpl.h | 87 +
.../Include/SmbiosProcessorSpecificData.h | 57 +
.../CpuExceptionHandlerLib.h | 110 +
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 198 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 22 +
.../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
.../FirmwareContextProcessorSpecificLib.h | 54 +
.../Include/Library/PlatformSecPpiLib.h | 24 +
.../Library/RiscVPlatformTempMemoryInitLib.h | 29 +
.../Include/Library/RiscVSpecialPlatformLib.h | 20 +
.../PlatformBootManager.h | 109 +
.../Universal/Pei/PlatformPei/Platform.h | 97 +
RiscVPlatformPkg/Universal/Sec/SecMain.h | 64 +
.../PeiServicesTablePointerOpenSbi.c | 119 +
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 1016 +++++++++
.../CpuExceptionHandlerLib.c | 194 ++
.../RiscVFirmwareContextSbiLib.c | 51 +
.../RiscVFirmwareContextSscratchLib.c | 48 +
.../RiscVFirmwareContextStvecLib.c | 48 +
.../Library/RiscVTimerLib/RiscVTimerLib.c | 199 ++
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 310 +++
RiscVPkg/Universal/FdtDxe/FdtDxe.c | 134 ++
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 +++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 350 +++
.../Edk2OpensbiPlatformWrapperLib.c | 554 +++++
.../FirmwareContextProcessorSpecificLib.c | 123 ++
.../OpensbiPlatformLib/OpensbiPlatform.c | 270 +++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 106 +
.../PeiCoreInfoHobLibNull/CoreInfoHob.c | 36 +
.../PlatformBootManager.c | 257 +++
.../PlatformBootManagerLib/PlatformData.c | 53 +
.../PlatformMemoryTestLibNull.c | 29 +
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 27 +
.../PlatformUpdateProgressLibNull.c | 53 +
.../Library/ResetSystemLib/ResetSystemLib.c | 128 ++
.../RiscVSpecialPlatformLib.c | 19 +
RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c | 73 +
.../Universal/Pei/PlatformPei/Fv.c | 54 +
.../Universal/Pei/PlatformPei/MemDetect.c | 80 +
.../Universal/Pei/PlatformPei/Platform.c | 365 ++++
RiscVPlatformPkg/Universal/Sec/SecMain.c | 733 +++++++
RiscVPlatformPkg/Readme.md | 224 ++
.../templates/pr-gate-build-job.yml | 3 +
.gitmodules | 3 +
.pytool/CISettings.py | 6 +-
.../PeiServicesTablePointerLibOpenSbi.uni | 16 +
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 143 ++
.../CpuExceptionHandlerLib.uni | 13 +
.../RiscVExceptionLib/SupervisorTrapHandler.S | 112 +
RiscVPkg/Library/RiscVOpensbiLib/opensbi | 1 +
.../RiscVPlatformTimerLibNull.S | 40 +
.../EmulatedMachineModeTimerLib.S | 24 +
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 +
RiscVPkg/RiscVPkg.ci.yaml | 151 ++
RiscVPkg/RiscVPkg.uni | 29 +
RiscVPkg/RiscVPkgExtra.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
.../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
.../SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
.../Documents/Media/RiscVEdk2BootProcess.svg | 1928
+++++++++++++++++
.../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +
.../PlatformBootManagerLib/Strings.uni | 28 +
.../Riscv64/TempMemInit.S | 26 +
RiscVPlatformPkg/RiscVPlatformPkg.ci.yaml | 122 ++
RiscVPlatformPkg/RiscVPlatformPkg.uni | 84 +
RiscVPlatformPkg/RiscVPlatformPkgExtra.uni | 12 +
.../Universal/Sec/Riscv64/SecEntry.S | 579 +++++
113 files changed, 14683 insertions(+), 1 deletion(-)
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.dsc
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dsc
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoint
er
LibOpenSbi.inf
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.i
nf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextS
scratchLib.inf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStve
cLib.inf
create mode 100644
RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644
RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTi
m
erLib/EmulatedMachineModeTimerLib.inf
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma
chineModeTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/FdtDxe/FdtDxe.inf
create mode 100644 RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644
RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPla
t
formWrapperLib.inf
create mode 100644
RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareCo
ntextProcessorSpecificLib.inf
create mode 100644
RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
create mode 100644
RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLi
b
.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTes
tLi
bNull.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateP
ro
gressLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
create mode 100644
RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatfo
r
mTempMemoryInitLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLi
bNull.inf
create mode 100644 RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.inf
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h
create mode 100644 RiscVPkg/Include/Library/MachineModeTimerLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVFirmwareContextLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
create mode 100644 RiscVPkg/Include/OpensbiTypes.h
create mode 100644 RiscVPkg/Include/ProcessorSpecificHobData.h
create mode 100644 RiscVPkg/Include/RiscVImpl.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644
RiscVPlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/PlatformSecPpiLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.h
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoint
er
OpenSbi.c
create mode 100644 RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.
c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextS
scratchLib.c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStve
cLib.c
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 RiscVPkg/Universal/FdtDxe/FdtDxe.c
create mode 100644 RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644
RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPla
t
formWrapperLib.c
create mode 100644
RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareCo
ntextProcessorSpecificLib.c
create mode 100644
RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
create mode 100644
RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644
RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTes
tLi
bNull.c
create mode 100644
RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
create mode 100644
RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateP
ro
gressLibNull.c
create mode 100644
RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
create mode 100644
RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLi
b.c
create mode 100644 RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c
create mode 100644 RiscVPlatformPkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.c
create mode 100644 RiscVPlatformPkg/Readme.md
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePoint
er
LibOpenSbi.uni
create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
create mode 160000 RiscVPkg/Library/RiscVOpensbiLib/opensbi
create mode 100644
RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTi
m
erLib/EmulatedMachineModeTimerLib.S
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma
chineModeTimerLib.S
create mode 100644 RiscVPkg/RiscVPkg.ci.yaml
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
create mode 100644
RiscVPlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
create mode 100644
RiscVPlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
create mode 100644
RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/Te
mpMemInit.S
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.ci.yaml
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.uni
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
create mode 100644 RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S

--
2.31.1





Re: [PATCH v2 3/6] SourceLevelDebugPkg: Replace Opcode with the corresponding instructions.

Wu, Hao A
 

Reviewed-by: Hao A Wu <hao.a.wu@...>

Best Regards,
Hao Wu

-----Original Message-----
From: Lou, Yun <yun.lou@...>
Sent: Monday, January 10, 2022 11:13 PM
To: devel@edk2.groups.io
Cc: Lou, Yun <yun.lou@...>; Wu, Hao A <hao.a.wu@...>
Subject: [PATCH v2 3/6] SourceLevelDebugPkg: Replace Opcode with the
corresponding instructions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)

Signed-off-by: Jason Lou <yun.lou@...>
Cc: Hao A Wu <hao.a.wu@...>
---

SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/Asm
Funcs.nasm | 6 +++---

SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/Asm
Funcs.nasm | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)

diff --git
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/As
mFuncs.nasm
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/A
smFuncs.nasm
index 912256ba45..b5e5a96e34 100644
---
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/As
mFuncs.nasm
+++
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/A
smFuncs.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------

;

-; Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -321,7 +321,7 @@ NoExtrPush:
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.

; edx still contains result from CPUID above

jz .2

- db 0xf, 0xae, 00000111y ;fxsave [edi]

+ fxsave [edi]

.2:



;; save the exception data

@@ -342,7 +342,7 @@ NoExtrPush:
cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported

test edx, BIT24 ; Test for FXSAVE/FXRESTOR support

jz .3

- db 0xf, 0xae, 00001110y ; fxrstor [esi]

+ fxrstor [esi]

.3:

add esp, 512



diff --git
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As
mFuncs.nasm
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As
mFuncs.nasm
index ccee120ca1..b1019e017b 100644
---
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As
mFuncs.nasm
+++
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/As
mFuncs.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------

;

-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -293,7 +293,7 @@ NoExtrPush:
rep stosq

pop rcx

mov rdi, rsp

- db 0xf, 0xae, 00000111y ;fxsave [rdi]

+ fxsave [rdi]



;; save the exception data

push qword [rbp + 16]

@@ -314,7 +314,7 @@ NoExtrPush:
add rsp, 8



mov rsi, rsp

- db 0xf, 0xae, 00001110y ; fxrstor [rsi]

+ fxrstor [rsi]

add rsp, 512



;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;

--
2.28.0.windows.1


回复: [edk2-devel] [PATCH 00/79] Migration of RiscV*Pkg

gaoliming
 

Abner:
Is there one BZ for this migration?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Abner Chang
发送时间: 2022年1月8日 10:26
收件人: devel@edk2.groups.io
抄送: abner.chang@...; Sean Brogan <sean.brogan@...>;
Bret Barkelew <Bret.Barkelew@...>; Michael D Kinney
<michael.d.kinney@...>; Leif Lindholm <leif@...>; Liming
Gao <gaoliming@...>; Daniel Schaefer
<daniel.schaefer@...>; Sunil V L <sunilvl@...>
主题: [edk2-devel] [PATCH 00/79] Migration of RiscV*Pkg

This is the migration of RISC-V related packages from edk2-platforms repo
to
edk2 repo, as the RISC-V edk2 port is getting mature and the demands of
RISC-V
edk2 port is increasing. RiscVVirtPKg is the next RISC-V edk2 package to
upstream to edk2 repo, which is built base on edk2 RiscVPkg and
RiscVPlatformPkg
for RISC-V QEMU port. The edk2 port drivers for RISC-V processor,
peripherals,
and the implemetation of industry standards (such as UEFI/ACPI/RISC-V
related specs) are also emulated base on RisVVirtPkg.

* Patches you can ignore:
Commit/Patch ca3c581e(1/79)-d3f147c4(61/79) are originally located in
edk2-platforms repo. Those patches had been reviewed and the commit
message
are all preserved for the migration.

*- Patches require review:
1. Commit/Patch 9aad8c35(62/79) and b284fa42(63/79) are the changes
to rename
RISC-V PlatformPkg and ProcessorPkg to RiscVPlatformPkg and
RiscVPkg.
2. Commit/Patch 6955062e(64/79) and a786bc26(65/79) are build error
fixes.
3. Commit/Patch c1fe0fe9(66/79) addes a git submodule for RISC-V
OpenSBI.
4. The rest of patches are the fixes for edk2 Core CI.
The patches for edk2 core CI fixes are created base on the CI test
items
but not base on the package owner or module, because those changes
are all
belong to RiscV*Pkg for CI issues and have no functional changes.

Signed-off-by: Abner Chang <abner.chang@...>
Cc: Sean Brogan <sean.brogan@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Leif Lindholm <leif@...>
Cc: Liming Gao <gaoliming@...>
Cc: Daniel Schaefer <daniel.schaefer@...>
Cc: Sunil V L <sunilvl@...>

Abner Chang (65):
ProcessorPkg/Include: Add header files of RISC-V processor package
ProcessorPkg/Library: RISC-V CPU library
ProcessorPkg/Library: Add RISC-V exception library
ProcessorPkg/Library: Add RISC-V timer library
ProcessorPkg/RiscVOpensbLib: Add opensbi submodule
ProcessorPkg/Library: Add RiscVOpensbiLib
ProcessorPkg/Library: RISC-V PEI Service Table Pointer library
ProcessorPkg/CpuDxe: Add RISC-V CPU DXE driver.
ProcessorPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
platforms.
ProcesorPkg/Library: NULL instance of RISC-V platform timer library.
RISC-V/ProcessorPkg: RISC-V package.
PlatformPkg/Library: RISC-V Platform Temporary Memory library
PlatformPkg/Library: Add FirmwareContextProcessorSpecificLib module
PlatformPkg/Library: NULL instance of RiscVOpensbiPlatformLib
PlatformPkg/Library: NULL instance of PlatformMemoryTestLib
PlatformPkg/Library: NULL instance of PlatformUpdateProgressLib
PlatformPkg/Library: Platform Boot Manager library.
PlatformPkg/SecMain: RISC-V SecMain module.
PlatformPkg: Add RiscVPlatformPkg
RISC-V/PlatformPkg: Revise Readme.md
Silicon/SiFive: Handle case of NULL FirmwareContext
Silicon/RISC-V: Update old SMBIOS struct filed name
U5SeriesPkg: Deduplicate PlatformPei
RISC-V: Split SMBIOS out of PlatformPei
RISC-V: Use U5 SMBIOS library only for those platforms
Silicon/RISC-V: Introduce FirmwareContext library
Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib
RISC-V/PlatformPkg: Add FdtPeim to pass DTB from PEI to DXE via HOB
RISC-V/PlatformPkg: Fixup FDT from HOB and install into config table
RISC-V: Switch to latest OpenSBI
RISC-V: Implement ResetSystem RT call
Move OpenSbiPlatformLib to RISC-V/PlatformPkg
RISC-V/PlatformPkg: Update document
RISC-V: Add RISC-V PeiCoreEntryPoint library
RISC-V: Create opensbi firmware domains
RISC-V: Use RISC-V PeiCoreEntryPoint library
Platform/RISC-V: Add library to get PPI descriptor
Platform/RISC-V: Use PlatformSecPpiLib
Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
Platform/RISC-V: Remove platform dependency from common platform lib
Platform/RISC-V: Remove Null instance of OpensbiPlatformLibNull
RiscVPlatformPkg/Sec: Initial hart_index2Id array
RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
RiscVPkg: Update opensbi library
RiscVPlatformPkg/Sec: Check Cold/Warm hart
RiscVPlatformPkg/Sec: Add more comments to Secmain.c
RiscV/ProcessorPkg: Create read mtime CSR library instances
RiscV/ProcessorPkg: Use mtime CSR library
RISC-V/PlatformPkg: Updates for the latest OpenSBI
PlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
RISC-V/PlatformPkg: Determine hart number from DTB
Silicon/RISC-V: Add PciCpuIoDxe driver
Platform/RISC-V: Add debug message to SecMain.c
Platform/RISC-V: Initialize variable to zero
RiscVPlatformPkg: Rename PlatformPkg to RiscVPlatformPkg
RiscVPkg: Rename ProcessorPkg to RiscVPkg
RiscVPkg: Fix build fail on RiscVPkg package
RiscVPkg/PlatformPei: Fix the build error
edk2:.gitmodules
RiscVPlatformPkg: Address Core CI ECC errors.
RiscVPkg: Address Core CI ECC errors.
edk2: RiscVPlatformPkg Core CI YAML file
edk2: RiscVPkg Core CI YAML file
edk2: Enable Core CI on RiscV*Pkg

Dandan Bi (2):
Platform/RISC-V: Consume MdeLibs.dsc.inc for RegisterFilterLib
Silicon/RISC_V: Consume MdeLibs.dsc.inc for RegisterFilterLib

Daniel Schaefer (4):
ProcessorPkg/Library: Add RiscVEdk2SbiLib
RISC-V/CpuDxe: Ignore set memory attributes failure
Signal EndOfDxe in boot manager
RISC-V/PlatformPkg: Build DeviceTree and use that in SEC

changab (8):
RiscVPlatformVPkg: Address Core CI Spelling errors.
RiscVPlatformVPkg: Address Core CI package dependency check errors
RiscVPlatformVPkg: Address Core CI license check errors.
RiscVPlatformVPkg: Address Core CI library header check errors
RiscVPlatformVPkg: Address Core CI Uncrustify errors
RiscVPkg: Address Core CI library header check errors
RiscVPkg: Address Core CI Spelling errors.
RiscVPkg: Address Core CI Uncrustify errors

RiscVPkg/RiscVPkg.dec | 50 +
RiscVPlatformPkg/RiscVPlatformPkg.dec | 94 +
RiscVPkg/RiscVPkg.dsc | 109 +
RiscVPlatformPkg/RiscVPlatformPkg.dsc | 95 +
.../PeiServicesTablePointerLibOpenSbi.inf | 39 +
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 +
.../RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf | 28 +
.../CpuExceptionHandlerDxeLib.inf | 43 +
.../RiscVFirmwareContextSbiLib.inf | 34 +
.../RiscVFirmwareContextSscratchLib.inf | 33 +
.../RiscVFirmwareContextStvecLib.inf | 34 +
.../RiscVOpensbiLib/RiscVOpensbiLib.inf | 89 +
.../RiscVPlatformTimerLib.inf | 35 +
.../EmulatedMachineModeTimerLib.inf | 34 +
.../MachineModeTimerLib.inf | 38 +
.../RiscVTimerLib/BaseRiscVTimerLib.inf | 35 +
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 49 +
RiscVPkg/Universal/FdtDxe/FdtDxe.inf | 53 +
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 +
.../Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 +
.../Edk2OpensbiPlatformWrapperLib.inf | 44 +
.../FirmwareContextProcessorSpecificLib.inf | 31 +
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 50 +
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +
.../PeiCoreInfoHobLib.inf | 43 +
.../PlatformBootManagerLib.inf | 55 +
.../PlatformMemoryTestLibNull.inf | 27 +
.../PlatformSecPpiLibNull.inf | 32 +
.../PlatformUpdateProgressLibNull.inf | 28 +
.../Library/ResetSystemLib/ResetSystemLib.inf | 32 +
.../RiscVPlatformTempMemoryInitLibNull.inf | 38 +
.../RiscVSpecialPlatformLibNull.inf | 36 +
.../Universal/FdtPeim/FdtPeim.inf | 46 +
.../Universal/Pei/PlatformPei/PlatformPei.inf | 66 +
RiscVPlatformPkg/Universal/Sec/SecMain.inf | 79 +
RiscVPkg/Include/IndustryStandard/RiscV.h | 162 ++
.../Include/IndustryStandard/RiscVOpensbi.h | 62 +
.../Include/Library/MachineModeTimerLib.h | 17 +
RiscVPkg/Include/Library/RiscVCpuLib.h | 118 +
RiscVPkg/Include/Library/RiscVEdk2SbiLib.h | 596 +++++
.../Include/Library/RiscVFirmwareContextLib.h | 43 +
.../Include/Library/RiscVPlatformTimerLib.h | 25 +
RiscVPkg/Include/OpensbiTypes.h | 82 +
RiscVPkg/Include/ProcessorSpecificHobData.h | 97 +
RiscVPkg/Include/RiscVImpl.h | 87 +
.../Include/SmbiosProcessorSpecificData.h | 57 +
.../CpuExceptionHandlerLib.h | 110 +
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 198 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 22 +
.../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
.../FirmwareContextProcessorSpecificLib.h | 54 +
.../Include/Library/PlatformSecPpiLib.h | 24 +
.../Library/RiscVPlatformTempMemoryInitLib.h | 29 +
.../Include/Library/RiscVSpecialPlatformLib.h | 20 +
.../PlatformBootManager.h | 109 +
.../Universal/Pei/PlatformPei/Platform.h | 97 +
RiscVPlatformPkg/Universal/Sec/SecMain.h | 64 +
.../PeiServicesTablePointerOpenSbi.c | 119 +
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 1016 +++++++++
.../CpuExceptionHandlerLib.c | 194 ++
.../RiscVFirmwareContextSbiLib.c | 51 +
.../RiscVFirmwareContextSscratchLib.c | 48 +
.../RiscVFirmwareContextStvecLib.c | 48 +
.../Library/RiscVTimerLib/RiscVTimerLib.c | 199 ++
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 310 +++
RiscVPkg/Universal/FdtDxe/FdtDxe.c | 134 ++
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 +++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 350 +++
.../Edk2OpensbiPlatformWrapperLib.c | 554 +++++
.../FirmwareContextProcessorSpecificLib.c | 123 ++
.../OpensbiPlatformLib/OpensbiPlatform.c | 270 +++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 106 +
.../PeiCoreInfoHobLibNull/CoreInfoHob.c | 36 +
.../PlatformBootManager.c | 257 +++
.../PlatformBootManagerLib/PlatformData.c | 53 +
.../PlatformMemoryTestLibNull.c | 29 +
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 27 +
.../PlatformUpdateProgressLibNull.c | 53 +
.../Library/ResetSystemLib/ResetSystemLib.c | 128 ++
.../RiscVSpecialPlatformLib.c | 19 +
RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c | 73 +
.../Universal/Pei/PlatformPei/Fv.c | 54 +
.../Universal/Pei/PlatformPei/MemDetect.c | 80 +
.../Universal/Pei/PlatformPei/Platform.c | 365 ++++
RiscVPlatformPkg/Universal/Sec/SecMain.c | 733 +++++++
RiscVPlatformPkg/Readme.md | 224 ++
.../templates/pr-gate-build-job.yml | 3 +
.gitmodules | 3 +
.pytool/CISettings.py | 6 +-
.../PeiServicesTablePointerLibOpenSbi.uni | 16 +
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 143 ++
.../CpuExceptionHandlerLib.uni | 13 +
.../RiscVExceptionLib/SupervisorTrapHandler.S | 112 +
RiscVPkg/Library/RiscVOpensbiLib/opensbi | 1 +
.../RiscVPlatformTimerLibNull.S | 40 +
.../EmulatedMachineModeTimerLib.S | 24 +
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 +
RiscVPkg/RiscVPkg.ci.yaml | 151 ++
RiscVPkg/RiscVPkg.uni | 29 +
RiscVPkg/RiscVPkgExtra.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
.../Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
.../SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
.../Documents/Media/RiscVEdk2BootProcess.svg | 1928
+++++++++++++++++
.../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +
.../PlatformBootManagerLib/Strings.uni | 28 +
.../Riscv64/TempMemInit.S | 26 +
RiscVPlatformPkg/RiscVPlatformPkg.ci.yaml | 122 ++
RiscVPlatformPkg/RiscVPlatformPkg.uni | 84 +
RiscVPlatformPkg/RiscVPlatformPkgExtra.uni | 12 +
.../Universal/Sec/Riscv64/SecEntry.S | 579 +++++
113 files changed, 14683 insertions(+), 1 deletion(-)
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.dsc
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dsc
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointer
LibOpenSbi.inf
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.i
nf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextS
scratchLib.inf
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStve
cLib.inf
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644
RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTim
erLib/EmulatedMachineModeTimerLib.inf
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma
chineModeTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/FdtDxe/FdtDxe.inf
create mode 100644 RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644
RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlat
formWrapperLib.inf
create mode 100644
RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareCo
ntextProcessorSpecificLib.inf
create mode 100644
RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
create mode 100644
RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib
.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLi
bNull.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdatePro
gressLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
create mode 100644
RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatfor
mTempMemoryInitLibNull.inf
create mode 100644
RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLi
bNull.inf
create mode 100644 RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.inf
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.inf
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscVOpensbi.h
create mode 100644 RiscVPkg/Include/Library/MachineModeTimerLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVEdk2SbiLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVFirmwareContextLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTimerLib.h
create mode 100644 RiscVPkg/Include/OpensbiTypes.h
create mode 100644 RiscVPkg/Include/ProcessorSpecificHobData.h
create mode 100644 RiscVPkg/Include/RiscVImpl.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644
RiscVPlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
create mode 100644 RiscVPlatformPkg/Include/Library/PlatformSecPpiLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644
RiscVPlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.h
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.h
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointer
OpenSbi.c
create mode 100644 RiscVPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.
c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextS
scratchLib.c
create mode 100644
RiscVPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStve
cLib.c
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 RiscVPkg/Universal/FdtDxe/FdtDxe.c
create mode 100644 RiscVPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644
RiscVPlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlat
formWrapperLib.c
create mode 100644
RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareCo
ntextProcessorSpecificLib.c
create mode 100644
RiscVPlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatform.c
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
create mode 100644
RiscVPlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644
RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLi
bNull.c
create mode 100644
RiscVPlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
create mode 100644
RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdatePro
gressLibNull.c
create mode 100644
RiscVPlatformPkg/Library/ResetSystemLib/ResetSystemLib.c
create mode 100644
RiscVPlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLi
b.c
create mode 100644 RiscVPlatformPkg/Universal/FdtPeim/FdtPeim.c
create mode 100644 RiscVPlatformPkg/Universal/Pei/PlatformPei/Fv.c
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644
RiscVPlatformPkg/Universal/Pei/PlatformPei/Platform.c
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.c
create mode 100644 RiscVPlatformPkg/Readme.md
create mode 100644
RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointer
LibOpenSbi.uni
create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
create mode 100644
RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
create mode 160000 RiscVPkg/Library/RiscVOpensbiLib/opensbi
create mode 100644
RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTim
erLib/EmulatedMachineModeTimerLib.S
create mode 100644
RiscVPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/Ma
chineModeTimerLib.S
create mode 100644 RiscVPkg/RiscVPkg.ci.yaml
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
create mode 100644
RiscVPlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
create mode 100644
RiscVPlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
create mode 100644
RiscVPlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
create mode 100644
RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
create mode 100644
RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/Te
mpMemInit.S
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.ci.yaml
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.uni
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
create mode 100644 RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S

--
2.31.1





回复: [edk2-devel] [PATCH v2 2/6] MdePkg: Replace Opcode with the corresponding instructions.

gaoliming
 

Jason:
Thanks for your update. Reviewed-by: Liming Gao <gaoliming@...>
for this patch set.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Jason Lou
发送时间: 2022年1月10日 23:13
收件人: devel@edk2.groups.io
抄送: Jason <yun.lou@...>; Michael D Kinney
<michael.d.kinney@...>; Liming Gao <gaoliming@...>;
Zhiguang Liu <zhiguang.liu@...>
主题: [edk2-devel] [PATCH v2 2/6] MdePkg: Replace Opcode with the
corresponding instructions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)

Signed-off-by: Jason Lou <yun.lou@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
---
MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm | 20
++++++++------------
MdePkg/Library/BaseLib/Ia32/LongJump.nasm | 6 +++---
MdePkg/Library/BaseLib/Ia32/Monitor.nasm | 4 ++--
MdePkg/Library/BaseLib/Ia32/Mwait.nasm | 4 ++--
MdePkg/Library/BaseLib/Ia32/RdRand.nasm | 13 +++++--------
MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm | 6 +++---
MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm | 6 +++---
MdePkg/Library/BaseLib/Ia32/SetJump.nasm | 6 +++---
MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm | 6 +++---
MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm | 6 +++---
MdePkg/Library/BaseLib/X64/DisablePaging64.nasm | 5 ++---
MdePkg/Library/BaseLib/X64/LongJump.nasm | 6 +++---
MdePkg/Library/BaseLib/X64/Monitor.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/Mwait.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/RdRand.nasm | 11 ++++-------
MdePkg/Library/BaseLib/X64/ReadDr4.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/ReadDr5.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/ReadMm0.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm1.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm2.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm3.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm4.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm5.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm6.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/ReadMm7.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/SetJump.nasm | 6 +++---
MdePkg/Library/BaseLib/X64/WriteDr4.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/WriteDr5.nasm | 4 ++--
MdePkg/Library/BaseLib/X64/WriteMm0.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm1.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm2.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm3.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm4.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm5.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm6.nasm | 7 ++-----
MdePkg/Library/BaseLib/X64/WriteMm7.nasm | 7 ++-----
MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm | 10
+++++-----
MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm | 8 ++++----
MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm | 8 ++++----
MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm | 10
+++++-----
MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm | 6 +++---
MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm | 8 ++++----
42 files changed, 116 insertions(+), 175 deletions(-)

diff --git a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
index 544e3c3892..ef11458077 100644
--- a/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/EnablePaging64.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -44,16 +44,12 @@ ASM_PFX(InternalX86EnablePaging64):
mov cr0, eax ; enable paging

retf ; topmost 2 dwords hold the
address

.0:

- DB 0x67, 0x48 ; 32-bit address size,
64-bit operand size

- mov ebx, [esp] ; mov rbx, [esp]

- DB 0x67, 0x48

- mov ecx, [esp + 8] ; mov rcx, [esp + 8]

- DB 0x67, 0x48

- mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]

- DB 0x67, 0x48

- mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]

- DB 0x48

- add esp, -0x20 ; add rsp, -20h

- call ebx ; call rbx

+BITS 64

+ mov rbx, [esp]

+ mov rcx, [esp + 8]

+ mov rdx, [esp + 0x10]

+ mov rsp, [esp + 0x18]

+ add rsp, -0x20

+ call rbx

hlt ; no one should get here



diff --git a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
index f94d10f806..6c13dfe307 100644
--- a/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/LongJump.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -39,12 +39,12 @@ ASM_PFX(InternalLongJump):


mov edx, [esp + 4] ; edx = JumpBuffer

mov edx, [edx + 24] ; edx = target SSP

- READSSP_EAX

+ rdsspd eax

sub edx, eax ; edx = delta

mov eax, edx ; eax = delta



shr eax, 2 ; eax = delta/sizeof(UINT32)

- INCSSP_EAX

+ incsspd eax



CetDone:



diff --git a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
index 28dc0ba70a..70dbe66e27 100644
--- a/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/Monitor.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,6 +31,6 @@ ASM_PFX(AsmMonitor):
mov eax, [esp + 4]

mov ecx, [esp + 8]

mov edx, [esp + 12]

- DB 0xf, 1, 0xc8 ; monitor

+ monitor

ret



diff --git a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
index 3956940cab..2d36a97df6 100644
--- a/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/Mwait.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -29,6 +29,6 @@ global ASM_PFX(AsmMwait)
ASM_PFX(AsmMwait):

mov eax, [esp + 4]

mov ecx, [esp + 8]

- DB 0xf, 1, 0xc9 ; mwait

+ mwait

ret



diff --git a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
index e12b8e9611..d818b6ef55 100644
--- a/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/RdRand.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -25,9 +25,8 @@ SECTION .text
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand16)

ASM_PFX(InternalX86RdRand16):

- ; rdrand ax ; generate a 16 bit RN into ax

+ rdrand eax ; generate a 16 bit RN into ax

; CF=1 if RN generated ok,
otherwise CF=0

- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6
ModRM:r/m(w)"

jc rn16_ok ; jmp if CF=1

xor eax, eax ; reg=0 if CF=0

ret ; return with failure status

@@ -45,9 +44,8 @@ rn16_ok:
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand32)

ASM_PFX(InternalX86RdRand32):

- ; rdrand eax ; generate a 32 bit RN into eax

+ rdrand eax ; generate a 32 bit RN into eax

; CF=1 if RN generated ok,
otherwise CF=0

- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6
ModRM:r/m(w)"

jc rn32_ok ; jmp if CF=1

xor eax, eax ; reg=0 if CF=0

ret ; return with failure status

@@ -65,14 +63,13 @@ rn32_ok:
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand64)

ASM_PFX(InternalX86RdRand64):

- ; rdrand eax ; generate a 32 bit RN into eax

+ rdrand eax ; generate a 32 bit RN into eax

; CF=1 if RN generated ok,
otherwise CF=0

- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6
ModRM:r/m(w)"

jnc rn64_ret ; jmp if CF=0

mov edx, dword [esp + 4]

mov [edx], eax



- db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN

+ rdrand eax ; generate another 32 bit RN

jnc rn64_ret ; jmp if CF=0

mov [edx + 4], eax



diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
index 81c681de34..1c312b670d 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr4):
; this register will cause a #UD exception.

;

; MS assembler doesn't support this instruction since no one would
use
it

- ; under normal circustances. Here opcode is used.

+ ; under normal circustances.

;

- DB 0xf, 0x21, 0xe0

+ mov eax, dr4

ret



diff --git a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
index e2deacb832..07a1b44a00 100644
--- a/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/ReadDr5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,8 +31,8 @@ ASM_PFX(AsmReadDr5):
; this register will cause a #UD exception.

;

; MS assembler doesn't support this instruction since no one would
use
it

- ; under normal circustances. Here opcode is used.

+ ; under normal circustances.

;

- DB 0xf, 0x21, 0xe8

+ mov eax, dr5

ret



diff --git a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
index 364613b5f9..2577373241 100644
--- a/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/SetJump.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -46,8 +46,8 @@ ASM_PFX(SetJump):
jnc CetDone



mov eax, 1

- INCSSP_EAX ; to read original SSP

- READSSP_EAX

+ incsspd eax ; to read original SSP

+ rdsspd eax

mov [edx + 0x24], eax ; save SSP



CetDone:

diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
index 0d23fca111..b8479b39f7 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr4):
; this register will cause a #UD exception.

;

; MS assembler doesn't support this instruction since no one would
use
it

- ; under normal circustances. Here opcode is used.

+ ; under normal circustances.

;

- DB 0xf, 0x23, 0xe0

+ mov dr4, eax

ret



diff --git a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
index bc5f424b8d..3545561025 100644
--- a/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
+++ b/MdePkg/Library/BaseLib/Ia32/WriteDr5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -32,8 +32,8 @@ ASM_PFX(AsmWriteDr5):
; this register will cause a #UD exception.

;

; MS assembler doesn't support this instruction since no one would
use
it

- ; under normal circustances. Here opcode is used.

+ ; under normal circustances.

;

- DB 0xf, 0x23, 0xe8

+ mov dr5, eax

ret



diff --git a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
index c76ed1a76c..200c408d9a 100644
--- a/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
+++ b/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -51,8 +51,7 @@ ASM_PFX(InternalX86DisablePaging64):
sub eax, 4 ; eax <- One slot below
transition code on the stack

push rcx ; push Cs to stack

push r10 ; push address of tansition
code on stack

- DB 0x48 ; prefix to composite
"retq" with next "retf"

- retf ; Use far return to load CS
register from stack

+ retfq



; Start of transition code

.0:

diff --git a/MdePkg/Library/BaseLib/X64/LongJump.nasm
b/MdePkg/Library/BaseLib/X64/LongJump.nasm
index 59f7092169..2002f65cba 100644
--- a/MdePkg/Library/BaseLib/X64/LongJump.nasm
+++ b/MdePkg/Library/BaseLib/X64/LongJump.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -41,12 +41,12 @@ ASM_PFX(InternalLongJump):
push rdx ; save rdx



mov rdx, [rcx + 0xF8] ; rdx = target SSP

- READSSP_RAX

+ rdsspq rax

sub rdx, rax ; rdx = delta

mov rax, rdx ; rax = delta



shr rax, 3 ; rax = delta/sizeof(UINT64)

- INCSSP_RAX

+ incsspq rax



pop rdx ; restore rdx

CetDone:

diff --git a/MdePkg/Library/BaseLib/X64/Monitor.nasm
b/MdePkg/Library/BaseLib/X64/Monitor.nasm
index e1ccb83a85..210037d402 100644
--- a/MdePkg/Library/BaseLib/X64/Monitor.nasm
+++ b/MdePkg/Library/BaseLib/X64/Monitor.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -32,6 +32,6 @@ ASM_PFX(AsmMonitor):
mov eax, ecx

mov ecx, edx

mov edx, r8d

- DB 0xf, 1, 0xc8 ; monitor

+ monitor

ret



diff --git a/MdePkg/Library/BaseLib/X64/Mwait.nasm
b/MdePkg/Library/BaseLib/X64/Mwait.nasm
index 83fc895491..c8ad59588b 100644
--- a/MdePkg/Library/BaseLib/X64/Mwait.nasm
+++ b/MdePkg/Library/BaseLib/X64/Mwait.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -30,6 +30,6 @@ global ASM_PFX(AsmMwait)
ASM_PFX(AsmMwait):

mov eax, ecx

mov ecx, edx

- DB 0xf, 1, 0xc9 ; mwait

+ mwait

ret



diff --git a/MdePkg/Library/BaseLib/X64/RdRand.nasm
b/MdePkg/Library/BaseLib/X64/RdRand.nasm
index 7e7fe99670..73479be8d3 100644
--- a/MdePkg/Library/BaseLib/X64/RdRand.nasm
+++ b/MdePkg/Library/BaseLib/X64/RdRand.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -26,9 +26,8 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand16)

ASM_PFX(InternalX86RdRand16):

- ; rdrand ax ; generate a 16 bit RN into eax,

+ rdrand eax ; generate a 16 bit RN into eax,

; CF=1 if RN generated ok,
otherwise CF=0

- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6
ModRM:r/m(w)"

jc rn16_ok ; jmp if CF=1

xor rax, rax ; reg=0 if CF=0

ret ; return with failure status

@@ -45,9 +44,8 @@ rn16_ok:
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand32)

ASM_PFX(InternalX86RdRand32):

- ; rdrand eax ; generate a 32 bit RN into eax,

+ rdrand eax ; generate a 32 bit RN into eax,

; CF=1 if RN generated ok,
otherwise CF=0

- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6
ModRM:r/m(w)"

jc rn32_ok ; jmp if CF=1

xor rax, rax ; reg=0 if CF=0

ret ; return with failure status

@@ -64,9 +62,8 @@ rn32_ok:
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalX86RdRand64)

ASM_PFX(InternalX86RdRand64):

- ; rdrand rax ; generate a 64 bit RN into rax,

+ rdrand rax ; generate a 64 bit RN into rax,

; CF=1 if RN generated ok,
otherwise CF=0

- db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6
ModRM:r/m(w)"

jc rn64_ok ; jmp if CF=1

xor rax, rax ; reg=0 if CF=0

ret ; return with failure status

diff --git a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
index 82c0a9a588..90b2172cee 100644
--- a/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadDr4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr4):
; There's no obvious reason to access this register, since it's
aliased to

; DR7 when DE=0 or an exception generated when DE=1

;

- DB 0xf, 0x21, 0xe0

+ mov rax, dr4

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
index c309c66dfe..c1143f4498 100644
--- a/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadDr5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,6 +31,6 @@ ASM_PFX(AsmReadDr5):
; There's no obvious reason to access this register, since it's
aliased to

; DR7 when DE=0 or an exception generated when DE=1

;

- DB 0xf, 0x21, 0xe8

+ mov rax, dr5

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
index 615721b6aa..e64b2c7882 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm0.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm0)

ASM_PFX(AsmReadMm0):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xc0

+ movq rax, mm0

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
index 7b27393490..bec3c71207 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm1.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm1)

ASM_PFX(AsmReadMm1):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xc8

+ movq rax, mm1

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
index c654b91a7a..4c880697cb 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm2.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm2)

ASM_PFX(AsmReadMm2):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xd0

+ movq rax, mm2

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
index 88d51c0781..cf81e5a7ab 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm3.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm3)

ASM_PFX(AsmReadMm3):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xd8

+ movq rax, mm3

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
index 4252d20bb1..17ba364e32 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm4)

ASM_PFX(AsmReadMm4):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xe0

+ movq rax, mm4

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
index d8f530dec8..f1354dd68c 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm5)

ASM_PFX(AsmReadMm5):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xe8

+ movq rax, mm5

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
index 6f6883c2b6..9d5a287218 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm6.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm6)

ASM_PFX(AsmReadMm6):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xf0

+ movq rax, mm6

ret



diff --git a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
index 573f15dfc8..ae15f24d8b 100644
--- a/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
+++ b/MdePkg/Library/BaseLib/X64/ReadMm7.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmReadMm7)

ASM_PFX(AsmReadMm7):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x7e, 0xf8

+ movq rax, mm7

ret



diff --git a/MdePkg/Library/BaseLib/X64/SetJump.nasm
b/MdePkg/Library/BaseLib/X64/SetJump.nasm
index 5a68396eec..5943a5ebe5 100644
--- a/MdePkg/Library/BaseLib/X64/SetJump.nasm
+++ b/MdePkg/Library/BaseLib/X64/SetJump.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -48,8 +48,8 @@ ASM_PFX(SetJump):
jnc CetDone



mov rax, 1

- INCSSP_RAX ; to read original SSP

- READSSP_RAX

+ incsspq rax ; to read original SSP

+ rdsspq rax

mov [rcx + 0xF8], rax ; save SSP



CetDone:

diff --git a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
index c4b12c9e92..5e4d96015e 100644
--- a/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteDr4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr4):
; There's no obvious reason to access this register, since it's
aliased to

; DR6 when DE=0 or an exception generated when DE=1

;

- DB 0xf, 0x23, 0xe1

+ mov dr4, rcx

mov rax, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
index 986a4a95d9..d5d4e2f324 100644
--- a/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteDr5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,7 +31,7 @@ ASM_PFX(AsmWriteDr5):
; There's no obvious reason to access this register, since it's
aliased to

; DR7 when DE=0 or an exception generated when DE=1

;

- DB 0xf, 0x23, 0xe9

+ mov dr5, rcx

mov rax, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
index 3f03529edf..e6b5a0fc33 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm0.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm0)

ASM_PFX(AsmWriteMm0):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xc1

+ movq mm0, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
index f552d40716..414c6af6da 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm1.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm1)

ASM_PFX(AsmWriteMm1):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xc9

+ movq mm1, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
index 1bd176ced9..525740342a 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm2.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm2)

ASM_PFX(AsmWriteMm2):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xd1

+ movq mm2, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
index 403f140736..abf11bfb17 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm3.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm3)

ASM_PFX(AsmWriteMm3):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xd9

+ movq mm3, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
index d99709d495..7cbd25e70a 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm4.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm4)

ASM_PFX(AsmWriteMm4):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xe1

+ movq mm4, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
index 0467ac4220..9edfd0db83 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm5.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm5)

ASM_PFX(AsmWriteMm5):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xe9

+ movq mm5, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
index 6d2e5eb8fb..4555563a55 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm6.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm6)

ASM_PFX(AsmWriteMm6):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xf1

+ movq mm6, rcx

ret



diff --git a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
index de72adf685..4ef0eb5271 100644
--- a/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
+++ b/MdePkg/Library/BaseLib/X64/WriteMm7.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -27,9 +27,6 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(AsmWriteMm7)

ASM_PFX(AsmWriteMm7):

- ;

- ; 64-bit MASM doesn't support MMX instructions, so use opcode here

- ;

- DB 0x48, 0xf, 0x6e, 0xf9

+ movq mm7, rcx

ret



diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm
index 5769c00bf9..3b336c6bdf 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/CopyMem.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -44,15 +44,15 @@ ASM_PFX(InternalMemCopyMem):
and r8, 7

shr rcx, 3 ; rcx <- # of Qwords to copy

jz @CopyBytes

- DB 0x49, 0xf, 0x7e, 0xc2 ; movd r10, mm0 (Save mm0
in r10)

+ movq r10, mm0

.1:

- DB 0xf, 0x6f, 0x6 ; movd mm0, [rsi]

- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0

+ movq mm0, [rsi]

+ movntq [rdi], mm0

add rsi, 8

add rdi, 8

loop .1

mfence

- DB 0x49, 0xf, 0x6e, 0xc2 ; movd mm0, r10 (Restore
mm0)

+ movq mm0, r10

jmp @CopyBytes

@CopyBackward:

mov rsi, r9 ; rsi <- End of Source

diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm
index 450113ba84..af584e3d34 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -32,16 +32,16 @@ ASM_PFX(InternalMemSetMem):
push rdi

mov rax, r8

mov ah, al

- DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax

+ movq mm0, rax

mov r8, rcx

mov rdi, r8 ; rdi <- Buffer

mov rcx, rdx

and edx, 7

shr rcx, 3

jz @SetBytes

- DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h

+ pshufw mm0, mm0, 0

.0:

- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0

+ movntq [rdi], mm0

add rdi, 8

loop .0

mfence

diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm
index 4e1f4be2b4..7a63a1c50b 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem16.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -31,16 +31,16 @@ global ASM_PFX(InternalMemSetMem16)
ASM_PFX(InternalMemSetMem16):

push rdi

mov rax, r8

- DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax

+ movq mm0, rax

mov r8, rcx

mov rdi, r8

mov rcx, rdx

and edx, 3

shr rcx, 2

jz @SetWords

- DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h

+ pshufw mm0, mm0, 0

.0:

- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0

+ movntq [rdi], mm0

add rdi, 8

loop .0

mfence

diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm
index b3a7385897..ab5f954826 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem32.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -28,20 +28,20 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalMemSetMem32)

ASM_PFX(InternalMemSetMem32):

- DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value)

+ movq mm0, r8

mov rax, rcx ; rax <- Buffer

xchg rcx, rdx ; rcx <- Count rdx <- Buffer

shr rcx, 1 ; rcx <- # of qwords to set

jz @SetDwords

- DB 0xf, 0x70, 0xC0, 0x44 ; pshufw mm0, mm0, 44h

+ pshufw mm0, mm0, 44h

.0:

- DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0

+ movntq [rdx], mm0

lea rdx, [rdx + 8] ; use "lea" to avoid flag changes

loop .0

mfence

@SetDwords:

jnc .1

- DB 0xf, 0x7e, 0x2 ; movd [rdx], mm0

+ movd [rdx], mm0

.1:

ret



diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm
index f517e1d23a..fcc44294a8 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/SetMem64.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -28,11 +28,11 @@
;---------------------------------------------------------------------------
---

global ASM_PFX(InternalMemSetMem64)

ASM_PFX(InternalMemSetMem64):

- DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value)

+ movq mm0, r8

mov rax, rcx ; rax <- Buffer

xchg rcx, rdx ; rcx <- Count

.0:

- DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0

+ movntq [rdx], mm0

add rdx, 8

loop .0

mfence

diff --git a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm
b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm
index 2a85f15b55..8b02eeb732 100644
--- a/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibMmx/X64/ZeroMem.nasm
@@ -1,6 +1,6 @@
;---------------------------------------------------------------------------
---

;

-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>

; SPDX-License-Identifier: BSD-2-Clause-Patent

;

; Module Name:

@@ -34,12 +34,12 @@ ASM_PFX(InternalMemZeroMem):
and edx, 7

shr rcx, 3

jz @ZeroBytes

- DB 0xf, 0xef, 0xc0 ; pxor mm0, mm0

+ pxor mm0, mm0

.0:

- DB 0xf, 0xe7, 7 ; movntq [rdi], mm0

+ movntq [rdi], mm0

add rdi, 8

loop .0

- DB 0xf, 0xae, 0xf0 ; mfence

+ mfence

@ZeroBytes:

xor eax, eax

mov ecx, edx

--
2.28.0.windows.1



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回复: [edk2-devel] [PATCH v2 00/10] Create new target for Cloud Hypervisor

gaoliming
 

Can you submit one BZ (https://bugzilla.tianocore.org/ ) to track this
feature?

Thanks
Liming

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Boeuf,
Sebastien
发送时间: 2022年1月11日 1:47
收件人: devel@edk2.groups.io
抄送: jiewen.yao@...; jordan.l.justen@...; kraxel@...;
sebastien.boeuf@...
主题: [edk2-devel] [PATCH v2 00/10] Create new target for Cloud Hypervisor

From: Sebastien Boeuf <sebastien.boeuf@...>

Since Cloud Hypervisor and QEMU pc/q35 are quite different, it makes
more sense to create a dedicated OVMF target for Cloud Hypervisor rather
than trying to support both VMMs from the same OvmfPkgX64 target.

That's the reason why this series introduces a new target called
CloudHvX64, meant to be used with the Cloud Hypervisor VMM only.

The new target is initially copied over from the OvmfPkgX64, then it is
trimmed down by removing what is not needed from a Cloud Hypervisor
perspective.

Sebastien Boeuf (10):
OvmfPkg/CloudHv: Add new target for Cloud Hypervisor
OvmfPkg/CloudHv: Replace legacy 8254 PIT with local APIC timer
OvmfPkg/CloudHv: Connect serial console
OvmfPkg/CloudHv: Remove legacy 8259 PIC support
OvmfPkg/CloudHv: Remove Q35 specifics
OvmfPkg/CloudHv: Reduce dependency on QemuFwCfg
OvmfPkg/CloudHv: Remove video support
OvmfPkg/CloudHv: Remove USB support
OvmfPkg/CloudHv: Remove CSM support
OvmfPkg/CloudHv: add Maintainers.txt entry

Maintainers.txt | 5 +
OvmfPkg/CloudHv/CloudHvX64.dsc | 937
++++++++++++++++++
OvmfPkg/CloudHv/CloudHvX64.fdf | 503 ++++++++++
.../PlatformBootManagerLib/BdsPlatform.c | 8 +-
4 files changed, 1452 insertions(+), 1 deletion(-)
create mode 100644 OvmfPkg/CloudHv/CloudHvX64.dsc
create mode 100644 OvmfPkg/CloudHv/CloudHvX64.fdf

--
2.30.2

---------------------------------------------------------------------
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Registered headquarters: "Les Montalets"- 2, rue de Paris,
92196 Meudon Cedex, France
Registration Number: 302 456 199 R.C.S. NANTERRE
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[edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Include: Remove duplicate file

Oram, Isaac W
 

Switch to using the IntelSiliconPkg version of the file as both were
identical.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>

Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SpiFlashCommonLib.h | 98 --------------------
Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf | 1 +
2 files changed, 1 insertion(+), 98 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SpiFlashCommonLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SpiFlashCommonLib.h
deleted file mode 100644
index ef62ba238d..0000000000
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/SpiFlashCommonLib.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/** @file
- The header file includes the common header files, defines
- internal structure and functions used by SpiFlashCommonLib.
-
- Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __SPI_FLASH_COMMON_LIB_H__
-#define __SPI_FLASH_COMMON_LIB_H__
-
-#include <Uefi.h>
-#include <Library/BaseLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
-/**
- Enable block protection on the Serial Flash device.
-
- @retval EFI_SUCCESS Opertion is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashLock (
- VOID
- );
-
-/**
- Read NumBytes bytes of data from the address specified by
- PAddress into Buffer.
-
- @param[in] Address The starting physical address of the read.
- @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
- of bytes actually read.
- @param[out] Buffer The destination data buffer for the read.
-
- @retval EFI_SUCCESS Opertion is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashRead (
- IN UINTN Address,
- IN OUT UINT32 *NumBytes,
- OUT UINT8 *Buffer
- );
-
-/**
- Write NumBytes bytes of data from Buffer to the address specified by
- PAddresss.
-
- @param[in] Address The starting physical address of the write.
- @param[in,out] NumBytes On input, the number of bytes to write. On output,
- the actual number of bytes written.
- @param[in] Buffer The source data buffer for the write.
-
- @retval EFI_SUCCESS Opertion is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashWrite (
- IN UINTN Address,
- IN OUT UINT32 *NumBytes,
- IN UINT8 *Buffer
- );
-
-/**
- Erase the block starting at Address.
-
- @param[in] Address The starting physical address of the block to be erased.
- This library assume that caller garantee that the PAddress
- is at the starting address of this block.
- @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
- On output, the actual number of bytes erased.
-
- @retval EFI_SUCCESS. Opertion is successful.
- @retval EFI_DEVICE_ERROR If there is any device errors.
-
-**/
-EFI_STATUS
-EFIAPI
-SpiFlashBlockErase (
- IN UINTN Address,
- IN UINTN *NumBytes
- );
-
-#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
index a5bcb5e2f2..b1e0896c7c 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -33,6 +33,7 @@

[Packages]
MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
WhitleySiliconPkg/WhitleySiliconPkg.dec
WhitleySiliconPkg/CpRcPkg.dec
WhitleyOpenBoardPkg/PlatformPkg.dec
--
2.27.0.windows.1


Re: [edk2-platforms PATCH 0/8] Update Arm platforms following addition of EFI_MP_SERVICES_PROTOCOL support in edk2

Rebecca Cran
 

Thanks! It looks like the existing changes covered Platform/Marvell/Cn913xDb/Cn913xDbA.dsc and Armada7k8kCapsule isn't something that would be broken by my changes.


--

Rebecca Cran


On 12/19/21 03:32, Marcin Wojtas wrote:
Hi,

czw., 16 gru 2021 o 23:09 Rebecca Cran <rebecca@...> napisał(a):
On 12/16/21 6:16 AM, Ard Biesheuvel wrote:
There were some changes a while ago to support standalone MM in 32-bit
mode, but I don't think any of the Platform/ARM platforms implement
that. So the best fix here is to simply stop lying about ARM support.

As for RdkQemu - I think it is time we just remove that.
During the work I found that the following list of platforms didn't build:


o Drivers/OptionRomPkg/OptionRomPkg.dsc for AARCH64 and ARM: due to OptionRomPkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf.

o Features/Ext4Pkg/Ext4Pkg.dsc for ARM: edk2-platforms/Features/Ext4Pkg/Ext4Dxe/Inode.c:341: undefined reference to `__aeabi_uidivmod')

o Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc for ARM

o Platform/Hisilicon/{D03,D05,D06} for AARCH64: Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c:50:18: error: ‘EmHilink0Hccs1X8Width16’ undeclared here (not in a function))

o Silicon/Marvell/Armada7k8k/Armada7k8kCapsule.dsc for AARCH64 and ARM: error C0DE: Unknown fatal error when processing [Silicon/Marvell/Armada7k8k/Armada7k8kCapsule.dsc]

It is expected behavior. In order to succeed, proper -D FIRMWARE_IMAGE
and -D PLATFORM_NAME must be passed.

o Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc for ARM.

o Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc for ARM.

o Platform/ARM/SgiPkg/RdN2/RdN2.dsc for ARM.

o Platform/ARM/SgiPkg/RdV1/RdV1.dsc for ARM.

o Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc for ARM.

o Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc for ARM.

o Platform/Comcast/RDKQemu/RDKQemu.dsc for AARCH64 and ARM due to ACPI
issue.

o Platform/Marvell/Cn913xDb/Cn913xDbA.dsc for AARCH64 and ARM: tries to
use literal $(PLATFORM_NAME).

The build is expected to fail - the user must explicitly pick the SoC
variant with -D flag, see the .dsc excerpt:
[Defines]
!if $(CN9130)
  PLATFORM_NAME                  = Cn9130DbA
!elseif $(CN9131)
  PLATFORM_NAME                  = Cn9131DbA
!elseif $(CN9132)
  PLATFORM_NAME                  = Cn9132DbA
!endif

Thanks,
Marcin

o Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc for AARCH64
and ARM: VariablePolicyHelperLib issue.

o Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc for AARCH64 and ARM:
T91 not found.

--
Rebecca Cran


Re: [PATCH v2 0/6] MM communicate functionality in variable policy

Kun Qin
 

Hi MdeModulePkg and ArmPkg maintainers,

It has been another week since this v2 patch series has been sent out for review. Could you please take a look and provide feedback? Any input is appreciated.

Regards,
Kun

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