Date   

[edk2-platforms PATCH 1/8] Platform/ARM: Add MpInitLib instance

Rebecca Cran <rebecca@...>
 

MpInitLib is now required for all users of ArmPkg/Drivers/CpuDxe. Add
ArmPkg/Library/MpInitLib/DxeMpInitLib.inf .

Signed-off-by: Rebecca Cran <rebecca@...>
---
Platform/ARM/JunoPkg/ArmJuno.dsc | 1 +
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 1 +
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 1 +
Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 1 +
5 files changed, 5 insertions(+)

diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJuno.dsc
index 3b7a63b6437a..61f5f2673d7a 100644
--- a/Platform/ARM/JunoPkg/ArmJuno.dsc
+++ b/Platform/ARM/JunoPkg/ArmJuno.dsc
@@ -76,6 +76,7 @@
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ MpInitLib|ArmPkg/Library/MpInitLib/DxeMpInitLib.inf

[BuildOptions]
GCC:*_*_ARM_PLATFORM_FLAGS = -march=armv8-a
diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
index dccd22248318..3d29153c8281 100644
--- a/Platform/ARM/Morello/MorelloPlatform.dsc.inc
+++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
@@ -50,6 +50,7 @@
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ MpInitLib|ArmPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc03609..4b8a990d1211 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -78,6 +78,7 @@
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
+ MpInitLib|ArmPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 4fe3ccf9a530..ca4eaa101b4d 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -83,6 +83,7 @@
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ MpInitLib|ArmPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
index d6f31ecda42f..207cf75a5671 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
@@ -211,6 +211,7 @@
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ MpInitLib|ArmPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.UEFI_APPLICATION]
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
--
2.31.1


[edk2-platforms PATCH 0/8] Update Arm platforms following addition of EFI_MP_SERVICES_PROTOCOL support in edk2

Rebecca Cran <rebecca@...>
 

This patch series depends on the "Add EFI_MP_SERVICES_PROTOCOL support
for AARCH64" series which is in the process of being reviewed (I'm
sending a v2 soon).

With the addition of EFI_MP_SERVICES_PROTOCOL support for Arm, consumers
of ArmPkg/Drivers/CpuDxe now need an instance of MpInitLib. This series
adds ArmPkg/Library/MpInitLib/DxeMpInitLib.inf.

Also, the ARM_CORE_INFO struct has changed so there's now an MPIDR field
where there were previously separate cluster and core fields. This
series updates the initializers for the various instances.


Rebecca Cran (8):
Platform/ARM: Add MpInitLib instance
Platform/Socionext: Add instance of MpInitLib
Silicon/Marvell: Add instance of MpInitLib
Platform/Qemu: Add instance of MpInitLib
Platform/ARM: Update ARM_CORE_INFO initializer for MPIDR field change
Silicon/Marvell: Update ARM_CORE_INFO initializer for MPIDR field
change
Silicon/Socionext: Update ARM_CORE_INFO initializer for MPIDR field
change
Silicon/Qemu: Update ARM_CORE_INFO initializer for MPIDR field change

Platform/ARM/JunoPkg/ArmJuno.dsc | 1 +
Platform/ARM/JunoPkg/Library/ArmJunoLib/ArmJuno.c | 12 ++---
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 1 +
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 1 +
Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 1 +
Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c | 16 +++----
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c | 16 +++----
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 +
Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 +
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 1 +
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.c | 8 ++--
Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c | 8 ++--
Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c | 48 ++++++++++----------
15 files changed, 63 insertions(+), 54 deletions(-)

--
2.31.1


Re: [edk2-platforms PATCH] Platform/RaspberryPi: Fix miniuart base address and length

Adrien Thierry
 

The Raspberry Pi support in edk2-platforms, including ACPI, is a direct ancestor of the original ms-iot tree (https://github.com/ms-iot/RPi-UEFI, by way of https://github.com/andreiw/RaspberryPiPkg).
The way the miniUART is described in ACPI came from Microsoft. Microsoft introduced DBG2/SPCR type 0x10 (https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table) and the BCM2836 _HID to describe the miniUART, and the contract is that the base address includes all those crazy registers.

To the best of my knowledge, today there isn't any other way to correctly describe the miniUART in a DBG2, SPCR or DSDT. Moreover, because there's code out there in at least two operating systems coded against these specific definitions, you don't get to change how a _HID == BCM2836 device or SPCR/DBG2 type 0x10 is described.
Thanks for your feedback!
I only had Linux in mind and didn't think about the other implementations
that would break. Thank you for stating the historical reasons why things
are set that way, I better understand now and see why this patch wouldn't
be such a great idea.

I guess I wasn't clear, I wasn't suggesting we change the existing
mechanism, so yes, I agree we either need another mechanism, or linux is
going to have to deal with it as is. The latter is IMHO the best option
(and as I mentioned I have patches to make it work), but sort of moves
us away from the standard uart/etc mechanisms we want for systemready.
So in that regard its not ideal.
I'm very interested to play with your patches if you could send them :)
I've been trying to add ACPI support to the miniuart Linux driver, and
stumbled across two issues:
- the miniuart base address "off by 0x40" in the DSDT (the subject of
this thread)
- how to properly get the clock rate with ACPI

Ideally, the end goal would be to have both the serial console and BT
working with the miniuart.

Adrien


[edk2-platforms][PATCH V1 1/1] Platform/Intel/Readme : Fix platform list

Oram, Isaac W
 

From: "manickavasakam karpagavinayagam via groups.io" <manickavasakamk@...>

The list of WhiskeyLake and Whitley boards got confused at some
earlier merge. Also untabified.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/Readme.md | 35 ++++++++++----------
1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 6fe8e076f3..b92d8a0c24 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -273,7 +273,7 @@ return back to the minimum platform caller.
| | | |---build_config.cfg: BoardTiogaPass specific
| | | | build settings, environment variables.
| | | |---build_board.py: Optional board-specific pre-build,
- | | | build, post-build and clean functions.
+ | | | build, post-build and clean functions.
| | |
| | |------SimicsOpenBoardPkg
| | | |------BoardX58Ich10
@@ -281,24 +281,23 @@ return back to the minimum platform caller.
| | | build settings, environment variables.
| | |
| | |------WhiskeylakeOpenBoardPkg
+ | | | |------UpXtreme
+ | | | |---build_config.cfg: UpXtreme specific build
+ | | | | settings environment variables.
+ | | | |------WhiskeylakeURvp
+ | | | |---build_config.cfg: WhiskeylakeURvp specific build
+ | | | settings environment variables.
+ | | |
+ | | |------WhitleyOpenBoardPkg
| | | |------CooperCityRvp
| | | | |---build_config.cfg: CooperCityRvp specific build
| | | | settings environment variables.
| | | |------WilsonCityRvp
- | | | |---build_config.cfg: WilsonCityRvp specific build
- | | | settings environment variables.
- | | |
- | | |------WhitleyOpenBoardPkg
- | | | |------UpXtreme
- | | | |---build_config.cfg: UpXtreme specific build
- | | | settings environment variables.
- | | |------WhitleyOpenBoardPkg
+ | | | | |---build_config.cfg: WilsonCityRvp specific build
+ | | | | settings environment variables.
| | | |------JunctionCity
| | | |---build_config.cfg: JunctionCity specific build
| | | settings environment variables.
- | | | |------WhiskeylakeURvp
- | | | |---build_config.cfg: WhiskeylakeURvp specific build
- | | | settings environment variables.
| | |
| | |------CometlakeOpenBoardPkg
| | | |------CometlakeURvp
@@ -335,10 +334,10 @@ For PurleyOpenBoardPkg (TiogaPass)
4. Type "bld" to build Purley BoardTiogaPass board UEFI firmware image, "bld release" for release build, "bld clean" to
remove intermediate files."bld cache-produce" Generate a cache of binary files in the specified directory,
"bld cache-consume" Consume a cache of binary files from the specified directory, BINARY_CACHE_PATH is empty,
- used "BinCache" as default path.
-5. Final BIOS image will be Build\PurleyOpenBoardPkg\BoardTiagoPass\DEBUG_VS2015x86\FV\PLATFORM.fd or
+ used "BinCache" as default path.
+5. Final BIOS image will be Build\PurleyOpenBoardPkg\BoardTiagoPass\DEBUG_VS2015x86\FV\PLATFORM.fd or
Build\PurleyOpenBoardPkg\BoardTiagoPass\RELEASE_VS2015x86\FV\PLATFORM.fd, depending on bld batch script input.
-6. This BIOS image needs to be merged with SPS FW
+6. This BIOS image needs to be merged with SPS FW

### **Known limitations**

@@ -367,9 +366,9 @@ For PurleyOpenBoardPkg (TiogaPass)
9. Verified Mellanox card detection during POST and OS
10. LINUX Boot Support (PcdLinuxBootEnable needs to be enabled)

-1. Follow directions on http://osresearch.net/Building/ to compile the heads kernel and initrd for qemu-system_x86_64
-2. Copy the following built files
-(1) initrd.cpio.xz to LinuxBootPkg/LinuxBinaries/initrd.cpio.xz
+1. Follow directions on http://osresearch.net/Building/ to compile the heads kernel and initrd for qemu-system_x86_64
+2. Copy the following built files
+(1) initrd.cpio.xz to LinuxBootPkg/LinuxBinaries/initrd.cpio.xz
(2) bzimage to LinuxBootPkg/LinuxBinaries/linux.efi


--
2.27.0.windows.1


Re: [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform

Oram, Isaac W
 

Pushed as: 871ce778eb..c14a67ee2a

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Oram, Isaac W
Sent: Wednesday, December 8, 2021 5:52 PM
To: devel@edk2.groups.io; KARPAGAVINAYAGAM, MANICKAVASAKAM <manickavasakamk@...>
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@...>; Jha, Manish <manishj@...>; sureshkumarp@...; Bobroff, Zachary <zacharyb@...>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform

Reviewed-by: Isaac Oram <isaac.w.oram@...>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of manickavasakam karpagavinayagam via groups.io
Sent: Wednesday, December 8, 2021 4:37 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@...>; Jha, Manish <manishj@...>; sureshkumarp@...; KARPAGAVINAYAGAM, MANICKAVASAKAM <manickavasakamk@...>; Bobroff, Zachary <zacharyb@...>
Subject: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform

Support for JunctionCity Platform
- Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all
other files in UBA folder are just name replacement (replaced TypeWilsonCity with TypeJunctionCity)
- Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time
- Modified GetPlatformInfo() to check build time PcdBoardId and decide the board detection logic

Notes :
V2 :
- Moved Junction UBA folder from WhitleyOpenBoardPkg\Uba\UbaMain
to WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity
- Modified WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c GetPlatformInfo()
to check build time PcdBoardId and decide the board detection logic
which avoid maintaining the JunctionCity PEIM Copy
- Include WhitleyOpenBoardPkg\PlatformPkg.dsc in JunctionCity PlatformPkg.dsc to avoid a lot of duplicate code
- Fix typo errors and unwanted statements in ReadMe.md
- Fix coding style errors.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Isaac Oram <isaac.w.oram@...>
Cc: Harikrishna Doppalapudi <harikrishnad@...>
Cc: Manish Jha <manishj@...>
Cc: Sureshkumar Ponnusamy <sureshkumarp@...>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@...>
Cc: Zachary Bobroff <zacharyb@...>

Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@...>
---
Platform/Intel/Readme.md | 14 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc | 276 +--
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c | 47 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf | 32 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c | 95 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf | 35 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc | 83 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf | 824 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 100 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 119 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 116 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 58 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 128 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 45 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/AcpiTablePcds.c | 54 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/GpioTable.c | 296 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/IioBifurInit.c | 242 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/KtiEparam.c | 69 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PcdData.c | 275 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PchEarlyUpdate.c | 93 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInit.h | 78 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.c | 157 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf | 167 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SlotTable.c | 172 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SoftStrapFixup.c | 121 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/UsbOC.c | 127 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py | 127 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg | 37 +
Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c | 1535 ++++++++--------
Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf | 129 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 1793 +++++++++---------
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 1924 ++++++++++----------
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c | 205 ++-
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf | 142 +-
Platform/Intel/build.cfg | 139 +-
Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h | 214 +--
39 files changed, 7042 insertions(+), 3149 deletions(-)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 965009ce21..6fe8e076f3 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -101,6 +101,8 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
| Machine Name | Supported Chipsets | BoardPkg | Board Name |

----------------------------------------|--------------------------------------------|------------------------------|--------------------|

| TiogaPass | Purley | PurleyOpenBoardPkg | BoardTiogaPass |

+----------------------------------------|--------------------------------------------|------------------------------|--------------------|

+| JunctionCity | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | JunctionCity |





#### Simics

@@ -289,6 +291,10 @@ return back to the minimum platform caller.
| | |------WhitleyOpenBoardPkg

| | | |------UpXtreme

| | | |---build_config.cfg: UpXtreme specific build

+ | | | settings environment variables.

+ | | |------WhitleyOpenBoardPkg

+ | | | |------JunctionCity

+ | | | |---build_config.cfg: JunctionCity specific build

| | | settings environment variables.

| | | |------WhiskeylakeURvp

| | | |---build_config.cfg: WhiskeylakeURvp specific build

@@ -392,6 +398,14 @@ For PurleyOpenBoardPkg (TiogaPass)
**WhitleyOpenBoardPkg**

1. This firmware project has been tested booting to UEFI shell with headless serial console



+**JunctionCity**

+1. This firmware project has been tested booting to UEFI shell

+2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk

+3. Booted to Windows 2019 using M2 SSD Disk

+4. Booted to Ubuntu 18.04,Windows 2019, RHEL 8.3 using SATA HDD

+5. Connected PCIE Network card and made sure PCIE card detected in POST and in OS

+6. Verified TPM offboard chip detection

+

### **Package Builds**



In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
index 99ab0961ca..6256922386 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -1,137 +1,139 @@
-## @file

-# Platform description.

-#

-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>

-#

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-#

-##

-

-

- #

- # Generic EDKII Driver

- #

- MdeModulePkg/Core/Dxe/DxeMain.inf {

- <LibraryClasses>

- NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf

- }

- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {

- <LibraryClasses>

- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

- }

-

- MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf

- MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf

-

- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf

- MdeModulePkg/Universal/Metronome/Metronome.inf

- MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf

- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf

- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

-

- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf

- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf

- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {

- <LibraryClasses>

- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf

- NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf

- NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf

- }

-

-

- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf

-

- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

- MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf

- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {

- <LibraryClasses>

-!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE

- NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf

-!endif

-!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

- NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.inf

-!endif

- }

-

- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf

-

- #UefiCpuPkg/CpuDxe/CpuDxe.inf

-

- MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf

- PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf

-

- #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

-

- #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

- #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf

- #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

- MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf

- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf

- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf

-

- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf

- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf

- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

- FatPkg/EnhancedFatDxe/Fat.inf

-

- #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf

- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

-

- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf

-

- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

-

- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf

-

- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

-

- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

-

- MdeModulePkg/Application/UiApp/UiApp.inf {

- <LibraryClasses>

- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

- NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf

- NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf

- NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf

- }

- MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf {

- <LibraryClasses>

- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

- }

-

- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf

- MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf

-

- MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf

- MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf

-

- #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf

-

- UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf

- MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf

-

- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf

- MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf

-

-!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE

- SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf

-!endif

-

-!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

- SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf

- SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {

- <LibraryClasses>

- Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf

- NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf

- NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf

- }

- SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf

- SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf

-!endif

-

+## @file
+# Platform description.
+#
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+ #
+ # Generic EDKII Driver
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ MdeModulePkg/Universal/Metronome/Metronome.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf
+ NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf
+ }
+
+
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+!endif
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.inf
+!endif
+ }
+
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ #UefiCpuPkg/CpuDxe/CpuDxe.inf
+
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+
+ MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+ #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+
+ UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+ MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
+ SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {
+ <LibraryClasses>
+ Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.inf
+ NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
+ NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
+ }
+ SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf
+ SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf
+ SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf
+!endif
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
new file mode 100644
index 0000000000..91ae2d376f
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file implements the IPMI Platform hook functions
+
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#define KCS_BASE_ADDRESS_MASK 0xFFF0
+#define NUMBER_OF_BYTES_TO_DECODE 0x10
+
+/**
+ This function sets IO Decode Range in LPC registers
+
+ @param[in] IpmiIoBase - IPMI Base IO address
+
+ @retval EFI_SUCCESS - Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformIpmiIoRangeSet (
+ UINT16 IpmiIoBase
+)
+{
+
+ EFI_STATUS Status;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((DEBUG_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n", IpmiIoBase));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGuid failed. Status %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE);
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
new file mode 100644
index 0000000000..699d89b24a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for IPMI platform hook Library.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiPlatformHookLib
+ FILE_GUID = A770BDB8-331A-4110-8B60-81FC17480B36
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IpmiPlatformHookLib
+
+[sources]
+ IpmiPlatformHookLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Ppis]
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..6a88df37d1
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
@@ -0,0 +1,95 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <Library/PeiPlatformHooklib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+/**
+ Configure GPIO
+
+ @param[in] None
+
+ @retval None
+**/
+VOID
+GpioInit (
+ VOID
+)
+{
+ PlatformInitGpios ();
+}
+
+/**
+ Disables ME PCI devices like IDE-R , KT
+
+ @param[in] None
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+DisableMEDevices (
+ VOID
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((DEBUG_INFO, "DisableMEDevices\n"));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ //Disable IDE-R
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+
+ //
+ //Disable KT
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+ return EFI_SUCCESS;
+
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ )
+{
+
+ GpioInit();
+ DisableMEDevices ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..fb3985c4e0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
@@ -0,0 +1,35 @@
+## @file
+#
+# @copyright
+# Copyright 1999 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPlatformHookLib
+ FILE_GUID = 6E9351C3-A17A-4ADF-8602-55B07962718F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiPlatformHooklib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ UbaGpioInitLib
+
+[Pcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
new file mode 100644
index 0000000000..93e031a06c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
@@ -0,0 +1,83 @@
+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+
+[PcdsFixedAtBuild]
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |TRUE
+!else
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE
+!endif
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+ !include WhitleyOpenBoardPkg/PlatformPkg.dsc
+
+[Defines]
+ BOARD_NAME = JunctionCity
+ PLATFORM_NAME = $(BOARD_NAME)
+ PLATFORM_GUID = F5798629-30B2-42EC-A1CA-825FEAA8A22A
+ FLASH_DEFINITION = $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf
+
+[PcdsFixedAtBuild]
+
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+ gPlatformTokenSpaceGuid.PcdBoardId|0x25
+
+[PcdsFixedAtBuild.X64]
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999
+
+[PcdsDynamicExHii]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+
+!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE
+ IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
+!endif
+
+[Components.IA32]
+ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
+ <LibraryClasses>
+ NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf
+ NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf
+ }
+
+[Components.X64]
+ $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+ $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+ $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
new file mode 100644
index 0000000000..b1058c9baa
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
@@ -0,0 +1,824 @@
+## @file
+# FDF file of platform with 64-bit DXE
+# This package provides platform specific modules and flash layout information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+ DEFINE FSP_BIN_DIR = Api
+!else
+ DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
+
+################################################################################
+#
+# FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+# FvBsp for board specific components
+# FvPostMemory for compressed post memory MinPlatform spec required components
+# FvFspS for compressed post memory silicon initialization components
+# FvPostMemorySilicon for silicon components
+# FvFspM for pre memory silicon initialization components
+# FvPreMemorySilicon for silicon components
+# FvFspT for temp RAM silicon initilization components
+# FvBspPreMemory for board specific components required to intialize memory
+# FvAdvancedPreMemory FV for advanced features components
+# FvPreMemory for components required by MinPlatform spec and to initialize memory
+# FvPreMemorySecurity FV for stage 6 required components
+# Contains reset vector
+#
+################################################################################
+
+[FD.SecPei]
+ BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
+ Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x360
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
+ # This will be corrected in the future.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00009000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ FV = FvBsp
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ FV = FvPostMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+ #
+ # Shared FV layout
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+ FV = FvBspPreMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ FV = FvPreMemory
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Set duplicate PCD
+ # These should not need to be changed
+ #
+
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+ #
+ # For API mode, wrappers have some duplicate PCD as well
+ #
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+
+################################################################################
+#
+# FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+# FvAdvanced for advanced feature components
+# Assorted advanced feature FV
+# FvSecurity for MinPlatform spec required components needed to boot securely
+# FvOsBoot for MinPlatform spec required components needed to boot OS
+# FvLateSilicon for silicon specific components
+# FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
+#
+################################################################################
+[FD.Main]
+ BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
+ Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x9C0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # These are out of flash layout order because FvAdvanced gets any remaining space
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00040000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ FV = FvAdvanced
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ FV = FvSecurity
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+ FV = FvOsBoot
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+ FV = FvUefiBoot
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+################################################################################
+#
+# FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+# FvOpRom containing pre-built components
+# FvAcmRegion containing ACM related content
+# FV Header + Blank Space (1K)
+# Policy block (3K)
+# Blank space to align ACM on 64K boundary (60K)
+# ACM binary
+# FvMicrocode containing microcode update patches
+# Unformatted region for PCI Gen 3 Data
+# FvVpd containing PCD VPD data
+# FvWhea for WHEA data recording
+# FvNvStorageVariable for UEFI Variable storage
+# FvNvStorageEventLog for NV Store management
+# FvNvStorageFtwWorking for Fault Tolerant Write solution
+# FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+################################################################################
+[FD.Binary]
+ BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+ Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2E0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
+ #
+ # These four items are tightly coupled.
+ # The spare area size must be >= the first three areas.
+ #
+ # There isn't really a benefit to a larger spare area unless the FLASH device
+ # block size is larger than the size specified.
+ #
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Calculate Offsets Once (You should not need to modify this section)
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
+ #
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+
+ #
+ # FV Layout (You should not need to modify this section)
+ #
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ FV = FvOprom
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ FV = FvAcm
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ FV = FvMicrocode
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ FV = FvVPD
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ FV = FvWhea
+
+ #
+ # Do not modify.
+ # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+
+ #
+ # Calculate base addresses (You should not need to modify this section)
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # ACM details
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
+
+ #
+ # Other duplicate PCD
+ #
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+################################################################################
+#
+# FD FPGA
+#
+# Contains the FPGA modules
+#
+################################################################################
+
+[FD.Fpga]
+ BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
+ Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2000
+
+ 0x00000000|0x02000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+ FV = FvFpga
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvSecurityPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ INF UefiCpuPkg/SecCore/SecCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
+ INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+ INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+ INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+
+ FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
+ SECTION UI = "DynamicSiLibraryPei"
+ }
+
+ INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
+
+ #
+ # UBA common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+ INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+ FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
+ SECTION UI = "SiliconPolicyInitPreAndPostMem"
+ }
+
+ INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
+
+ INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ !if $(FSP_MODE) == 0
+ FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
+ SECTION UI = "CsrPseudoOffsetInitPeim"
+ }
+ FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
+ SECTION UI = "RegAccessPeim"
+ }
+ FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
+ SECTION UI = "SiliconDataInitPeim"
+ }
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+ !endif
+
+ FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+[FV.FvAdvancedPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+ !include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvBspPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+ FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+ SECTION FV_IMAGE = FvAdvancedPreMemory
+ }
+
+#
+# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+ FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompressed
+ }
+ }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+ FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvBspUncompressed
+ }
+ }
+
+[FV.FvUefiBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ #ATA for IDE/AHCI/RAID support
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+ FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
+ SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
+ }
+
+
+[FV.FvUefiBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+ FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompressed
+ }
+ }
+
+[FV.FvOsBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ #
+ # DXE Phase modules
+ #
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+ SECTION UI = "FvLateSilicon"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+ }
+
+ INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
+
+ #
+ # UBA DXE common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+ INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+ INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+ INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+ INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ !if ($(FSP_MODE) == 1)
+ INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+ !else
+ INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ !endif
+
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+ SECTION UI = "FvLateOpenBoard"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+ }
+
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+ INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+
+ INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ # UEFI USB stack
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
+ INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+
+[FV.FvOsBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
+
+ FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompressed
+ }
+ }
+
+[FV.FvSecuritySilicon]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+
+[FV.FvSecurityUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
+
+ FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecuritySilicon
+ }
+ }
+
+[FV.FvSecurity]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
+
+ FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityUncompressed
+ }
+ }
+
+[FV.FvAdvancedUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
+
+ !include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+[FV.FvAdvanced]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
+
+ FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompressed
+ }
+ }
+
+#
+# FV for all Microcode Updates.
+#
+[FV.FvMicrocode]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
+
+!if $(CPUTARGET) == "CPX"
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+!else
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+!endif
+
+
+[FV.FvVPD]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
+ FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+ }
+
+#
+# Various Vendor UEFI Drivers (OROMs).
+#
+[FV.FvOpromUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
+
+[FV.FvOprom]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
+
+ FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOpromUncompressed
+ }
+ }
+
+[FV.FvWhea]
+ BlockSize = 0x1000
+ NumBlocks = 0x30
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
+
+#
+# FV For ACM Binary.
+#
+[FV.FvAcm]
+ BlockSize = 0x1000
+ NumBlocks = 0x50
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
+
+[FV.FvFpga]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
new file mode 100644
index 0000000000..b6b81f188c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
@@ -0,0 +1,100 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "IioCfgUpdateDxe.h"
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+IioCfgUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_1,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_2,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_3,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
new file mode 100644
index 0000000000..53d3a49f9a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
@@ -0,0 +1,119 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOCFG_UPDATE_DXE_H_
+#define _IIOCFG_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/UbaCfgDb.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+#define NO_SLT_IMP 0xFF
+#define SLT_IMP 1
+#define HIDE 1
+#define NOT_HIDE 0
+#define VPP_PORT_0 0
+#define VPP_PORT_1 1
+#define VPP_PORT_MAX 0xFF
+#define VPP_ADDR_MAX 0xFF
+#define PWR_VAL_MAX 0xFF
+#define PWR_SCL_MAX 0xFF
+
+static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
+{
+ // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6)
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
+ { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
+ // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
+ // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
+ { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink
+ { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink
+ { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
+ { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
+ { SOCKET_1_INDEX +
+ PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
+};
+
+#endif //_IIOCFG_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
new file mode 100644
index 0000000000..13d88a3748
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IioCfgUpdateDxeJunctionCity
+ FILE_GUID = 9E1DECF5-C606-44A2-B99D-5BF4222A174C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IioCfgUpdateEntry
+
+[sources]
+ IioCfgUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
new file mode 100644
index 0000000000..37e9c6a9e6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
@@ -0,0 +1,116 @@
+/** @file
+ Slot Data Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SlotDataUpdateDxe.h"
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+SlotDataUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
new file mode 100644
index 0000000000..e59e70c9ee
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
@@ -0,0 +1,58 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLOT_DATA_UPDATE_DXE_H_
+#define _SLOT_DATA_UPDATE_DXE_H_
+
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+#endif //_SLOT_DATA_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
new file mode 100644
index 0000000000..8f107b9c42
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SlotDataUpdateDxeJunctionCity
+ FILE_GUID = 98750E94-CCCB-45AA-9259-3CF7F8C43C33
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SlotDataUpdateEntry
+
+[sources]
+ SlotDataUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
new file mode 100644
index 0000000000..7522d7b6e2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
@@ -0,0 +1,128 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UsbOcUpdateDxe.h"
+
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPinSkip, //Port00: BMC
+ UsbOverCurrentPinSkip, //Port01: BMC
+ UsbOverCurrentPin0, //Port02: Rear Panel
+ UsbOverCurrentPin1, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPinSkip, //Port05: NC
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPin4, //Port07: Type A internal
+ UsbOverCurrentPinSkip, //Port08: NC
+ UsbOverCurrentPinSkip, //Port09: NC
+ UsbOverCurrentPin6, //Port10: Front Panel
+ UsbOverCurrentPinSkip, //Port11: NC
+ UsbOverCurrentPin6, //Port12: Front Panel
+ UsbOverCurrentPinSkip, //Port13: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin6, //Port01: Front Panel
+ UsbOverCurrentPin6, //Port02: Front Panel
+ UsbOverCurrentPin0, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPin1, //Port05: Rear Panel
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+UsbOcUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gDxePlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
new file mode 100644
index 0000000000..2ba90c7598
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
@@ -0,0 +1,27 @@
+/** @file
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _USBOC_UPDATE_DXE_H_
+#define _USBOC_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+
+
+#endif //_USBOC_UPDATE_DXE_H_
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
new file mode 100644
index 0000000000..0f8e953e2b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
@@ -0,0 +1,45 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UsbOcUpdateDxeJunctionCity
+ FILE_GUID = 5149EA77-8FCC-41B4-A8D0-CE652E817FD0
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = UsbOcUpdateEntry
+
+[sources]
+ UsbOcUpdateDxe.c
+ UsbOcUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/AcpiTablePcds.c
new file mode 100644
index 0000000000..f4eedccd77
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/AcpiTablePcds.c
@@ -0,0 +1,54 @@
+/** @file
+ ACPI table pcds update.
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <UncoreCommonIncludes.h>
+#include <Cpu/CpuIds.h>
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+ )
+{
+ CHAR8 AcpiName10nm[] = "EPRP10NM"; // USED for identify ACPI table for 10nm in systmeboard dxe driver
+ CHAR8 OemTableIdXhci[] = "xh_nccrb";
+
+ UINTN Size;
+ EFI_STATUS Status;
+
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ DEBUG ((DEBUG_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n"));
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+ //#
+ //#ACPI items
+ //#
+ Size = AsciiStrSize (AcpiName10nm);
+ Status = PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm);
+ DEBUG ((DEBUG_INFO, "%a TypeJunctionCity ICX\n", __FUNCTION__));
+ ASSERT_EFI_ERROR (Status);
+
+ Size = AsciiStrSize (OemTableIdXhci);
+ Status = PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/GpioTable.c
new file mode 100644
index 0000000000..2d1e46b143
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/GpioTable.c
@@ -0,0 +1,296 @@
+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaGpioUpdateLib.h>
+
+#include <Library/GpioLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/PcdLib.h>
+
+//
+// Board : Wilson City RP
+//
+static GPIO_INIT_CONFIG mGpioTableJunctionCity [] =
+ {
+ {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N //IRQ_ESPI_FPGA_PCH_ALERT1_N PU not used
+ {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0
+ {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1
+ {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2
+ {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3
+ {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+ {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+ {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+ {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N //PU_LPC_CLKRUN_N PU not used
+ {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI
+ {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10
+ {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N //PU_LPC_PME_N PU not used
+ {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N //PU_IRQ_PCH_SCI_WHEA_N PU not used
+ {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N //TP_PCH_GPP_A_13
+ {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
+ {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N //TP_PCH_GPP_A_15
+ {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 //FM_PCHIE_BMC_N
+ {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 //FM_BMC_PCHIE_N
+ {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS //IRQ_BMC_PCH_SMI_LPC_N
+// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS //ME Recovery Jumper FM_ME_RCVR_N
+ {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 //FM_BMC_READY_N
+ {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21
+ {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22
+ {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23
+ {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0
+ {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1
+ {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
+ {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //PU_SATA_EN
+// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS //ME SMB Alert MGPIO IRQ_SML1_PMBUS_ALERT
+ {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 //TP_PCH_GPP_B_5
+ {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 //TP_PCH_GPP_B_6
+ {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7
+ {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8
+ {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 //TP_PCH_GPP_B_9
+ {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N
+// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS //ME SMB Alert_EN MGPIO FM_PMBUS_ALERT_BUF_EN_N
+ {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N //FM_GLOBAL_RST_WARN_N
+ {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
+ {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+ {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
+ {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
+ {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
+ {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT //PU_NO_REBOOT Spare
+ {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 //TP_PCH_GPP_B19
+ {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+ {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21
+ {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE //FM_USB_PWR_EN
+ {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N
+// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS //ME SMBCLK
+// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS //ME SMBDATA
+ {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP //IRQ_SMB_ALERT_N_TLS_EN_STRP
+// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS //ME SML0CLK
+// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS //ME SML0DATA
+ {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
+// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS //ME SML1CLK
+// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS //ME SML1DATA
+ {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
+ {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
+ {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
+ {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N //FM_BOARD_REV_ID0
+ {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 //FM_BOARD_REV_ID1
+ {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 //FM_BOARD_REV_ID2
+ {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N //TP_PCH_GPP_C_14
+ {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 //TP_PCH_GPP_C_15
+ {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 //TP_PCH_GPP_C_16
+ {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 //TP_PCH_GPP_C_17
+ {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 //TP_PCH_GPP_C_18
+// GPIO_SKL_H_GPP_C19 - Not Owned by BIOS //SMBus Smbus Mux GPIO reset GPP_C_19_RST_SMB_HOST_PCH_MUX_N
+// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS //ME PROCHOT MGPIO GPP_C_20_FM_THROTTLE_N
+ {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N //TP_PCH_GPP_C_21
+ {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N //FM_BMC_PCH_SCI_LPC_N
+ {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
+ {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N
+ {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR //TP_PCH_GPP_D_2
+ {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT //TP_PCH_GPP_D_3
+ {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
+ {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 //FM_OCP_MOD1_PRSNT_N
+ {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6
+ {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7
+ {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL //TP_PCH_GPP_D_8
+ {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9
+ {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_D_10
+ {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11
+ {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 //TP_PCH_GPP_D_12
+ {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL //TP_PCH_GPP_D_13
+ {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA //TP_PCH_GPP_D_14
+ {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0
+ {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 //FM_SLOT1_PRSNT
+ {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 //FM_SLOT2_PRSNT
+ {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N //TP_PCH_GPP_D_18
+ {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
+ {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20
+ {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21
+ {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22
+ {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23
+ {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N //TP_PCH_GPP_E_0
+ {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N //TP_PCH_GPP_E_1
+ {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N //TP_PCH_GPP_E_2
+ {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N
+ {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 //FM_CPU0_SSD0_PRSNT_N
+ {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 //FM_CPU0_SSD1_PRSNT_N
+ {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 //FM_CPU0_SSD2_PRSNT_N
+ {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
+ {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N //FM_CPU0_SSD3_PRSNT_N
+ {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N
+ {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N
+ {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N
+ {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N
+ {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N //FM_OCP_MOD2_PRSNT_N
+ {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N //TP_PCH_GPP_F_1
+ {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT0_N
+ {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT1_N
+ {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N //FM_BIOS_USB_RECOVERY
+ {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+ {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK //FM_EDSFF1_PRSNT0_N
+ {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI //FM_EDSFF1_PRSNT1_N
+ {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS //FM_EDSFF2_PRSNT0_N
+ {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO //FM_EDSFF2_PRSNT1_N
+ {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK
+ {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD
+ {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1
+ {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0
+ {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N //TP_PCH_GPP_F14
+ {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N //FM_EDSFF3_PRSNT0_N
+ {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N //FM_EDSFF3_PRSNT1_N
+ {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N //FM_EDSFF4_PRSNT0_N
+ {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N //FM_EDSFF4_PRSNT1_N
+ {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL //FM_EDSFF5_PRSNT0_N
+ {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA //FM_EDSFF5_PRSNT1_N
+ {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21
+ {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK
+ {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD
+ {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 //FM_BOARD_SKU_ID0
+ {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 //FM_BOARD_SKU_ID1
+ {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 //FM_BOARD_SKU_ID2
+ {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 //FM_BOARD_SKU_ID3
+ {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 //FM_BOARD_SKU_ID4
+ {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 //FM_BOARD_SKU_ID5
+ {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 //FM_MIDPLANE_PCH_ID0
+ {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 //FM_MIDPLANE_PCH_ID1
+ {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 //FM_PCH_GPP_G8
+ {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 //FM_PCH_GPP_G9
+ {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 //FM_PCH_GPP_G10
+ {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 //FM_PCH_GPP_G11
+ {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_GSXDOUT //IRQ_FORCE_NM_THROTTLE_N
+ {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 //TP_PCH_GPP_G_13
+ {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 //TP_PCH_GPP_G_14
+ {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 //TP_PCH_GPP_G_15
+ {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 //TP_PCH_GPP_G_16
+ {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
+ {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
+ {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
+ {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //TP_PCH_GPP_G_20
+ {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N //TP_PCH_GPP_G_21
+ {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_G_22
+ {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23
+ {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 //FM_CLKREQ_M2_SSD_A_N
+ {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N //FM_CLKREQ_M2_SSD_B_N
+ {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 //FM_ROWOL_ENABLE
+ {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 //FM_ROWOL_LATCH
+ {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 //TP_PCH_GPP_H_4
+ {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_5_FM_CLKREQ_M2_1_N //TP_PCH_GPP_H_5
+ {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N //TP_PCH_GPP_H_6
+ {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 //TP_PCH_GPP_H_7
+ {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N //TP_PCH_GPP_H_8
+ {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 //TP_PCH_GPP_H_9
+// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS //ME SML2CLK
+// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS //ME SML2DATA
+ {GPIO_SKL_H_GPP_H12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE //IRQ_SML2_ALERT_N
+ {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
+ {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
+ {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N //TP_PCH_GPP_H_19
+ {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL //TP_PCH_GPP_H_20
+ {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N //TP_PCH_GPP_H_21
+ {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL //TP_PCH_GPP_H_22
+ {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23
+ {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0
+ {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1
+ {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2
+ {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3
+ {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4
+ {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5
+ {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6
+ {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7
+ {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N
+ {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N
+ {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 //FM_BIOS_MRC_DEBUG_MSG_DIS_N
+// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS
+// GPIO_SKL_H_GPD0 - Not Owned by BIOS //ME FIVRBREAK
+ {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT
+ {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N //RST_BMC_SRST_N
+ {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
+ {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
+ {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
+ {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N
+ {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
+ {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK
+ {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP
+ {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N
+ {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N
+ {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0
+ {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1
+ {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2
+ {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3
+ {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4
+ {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5
+ {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6
+ {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7
+ {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8
+ {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9
+ {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10
+ {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11
+ {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12
+ {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13
+ {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14
+ {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15
+ {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16
+ {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17
+ {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18
+ {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19
+ {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20
+ {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21
+ {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22
+ {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23
+ {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH
+ {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0
+ {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1
+ {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN
+ {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV
+ {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0
+ {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1
+ {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER
+ {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN
+ {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT
+ {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
+// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS
+ {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0
+ {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1
+ {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2
+ {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3
+ {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4
+ {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5
+ {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6
+ {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7
+ {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK
+ {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0
+ {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1
+ {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2
+ {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3
+ {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4
+ {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5
+ {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6
+ {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7
+ {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK
+};
+
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformGpioInitDataGuid,
+ &mGpioTableJunctionCity,
+ sizeof(mGpioTableJunctionCity)
+ );
+ Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableJunctionCity));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/IioBifurInit.c
new file mode 100644
index 0000000000..4c376964e2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/IioBifurInit.c
@@ -0,0 +1,242 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 = 0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+
+static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =
+{
+
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_x4x4xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxx8x4x4, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }
+};
+//[-start-210223-Enhance_Dynamic_Type9-modify]//
+static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = {
+ // Port Index | Slot |Interlock |power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard |ExtnCard |ExtnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer|
+ // | | |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port |Vpp Address | |
+ {SOCKET_0_INDEX +
+ PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1C_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1D_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2C_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+
+ {SOCKET_1_INDEX +
+ PORT_1A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2A_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4A_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4B_INDEX, 12 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4C_INDEX, 13 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5A_INDEX, 14 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }
+};
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr;
+ UINTN PlatformIioInfoSize;
+
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ //
+ // This is config for ICX
+ //
+ PlatformIioInfoPtr = &TypeJunctionCityIioConfigTable;
+ PlatformIioInfoSize = sizeof(TypeJunctionCityIioConfigTable);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_1,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_2,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_3,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/KtiEparam.c
new file mode 100644
index 0000000000..1ec1424d23
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/KtiEparam.c
@@ -0,0 +1,69 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <KtiSetupDefinitions.h>
+#include <UbaKti.h>
+
+extern EFI_GUID gPlatformKtiEparamUpdateDataGuid;
+
+ALL_LANES_EPARAM_LINK_INFO KtiJunctionCityIcxAllLanesEparamTable[] = {
+ //
+ // SocketID, Freq, Link, TXEQL, CTLEPEAK
+ // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA KtiEparam tables
+ //
+ //
+ // Socket 0
+ //
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE},
+ //
+ // Socket 1
+ //
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE}
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeJunctionCityIcxKtiEparamUpdate = {
+ PLATFORM_KTIEP_UPDATE_SIGNATURE,
+ PLATFORM_KTIEP_UPDATE_VERSION,
+ KtiJunctionCityIcxAllLanesEparamTable,
+ sizeof (KtiJunctionCityIcxAllLanesEparamTable),
+ NULL,
+ 0
+};
+
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformKtiEparamUpdateDataGuid,
+ &TypeJunctionCityIcxKtiEparamUpdate,
+ sizeof(TypeJunctionCityIcxKtiEparamUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PcdData.c
new file mode 100644
index 0000000000..f833775a73
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PcdData.c
@@ -0,0 +1,275 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <ImonVrSvid.h>
+#include <Library/MemVrSvidMapLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UbaPcdUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <CpuAndRevisionDefines.h>
+
+#define GPIO_SKL_H_GPP_B20 0x01010014
+
+VOID TypeJunctionCityPlatformUpdateVrIdAddress (VOID);
+
+/**
+ Update JunctionCity IMON SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateImonAddress (
+ VOID
+ )
+{
+ VCC_IMON *VccImon = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (VCC_IMON);
+ VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
+ if (VccImon == NULL) {
+ DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
+ return;
+ }
+
+ VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
+ VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
+ VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
+
+ PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
+}
+
+/**
+ Update WilsonCity VR ID SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateVrIdAddress (
+ VOID
+ )
+{
+ MEM_SVID_MAP *MemSvidMap = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (MEM_SVID_MAP);
+ MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
+ if (MemSvidMap == NULL) {
+ DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
+ return;
+ }
+ /*
+ Map VR ID Address to Memory controller
+ The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
+ Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
+ Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
+ and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
+ BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
+ BIT 0:3 => SVID ADDRESS
+ */
+
+ MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+
+ PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
+}
+
+EFI_STATUS
+TypeJunctionCityPlatformPcdUpdateCallback (
+ VOID
+)
+{
+ CHAR8 FamilyName[] = "Whitley";
+
+ CHAR8 BoardName[] = "EPRP";
+ UINT32 Data32;
+ UINTN Size;
+ UINTN PlatformFeatureFlag = 0;
+
+ CHAR16 PlatformName[] = L"TypeJunctionCity";
+ UINTN PlatformNameSize = 0;
+ EFI_STATUS Status;
+
+ //#Integer for BoardID, must match the SKU number and be unique.
+ Status = PcdSet16S (PcdOemSkuBoardID , TypeJunctionCity);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Number of Sockets on Board.
+ Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Max channel and max DIMM
+ Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Update Onboard Video Controller PCI Ven_id, Dev_id
+ Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //#
+ //# Misc.
+ //#
+ //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
+ Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //SDP Active Flag
+ Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to ID family
+ Size = AsciiStrSize (FamilyName);
+ Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to Board Name
+ Size = AsciiStrSize (BoardName);
+ Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ PlatformNameSize = sizeof (PlatformName);
+ Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# FeaturesBasedOnPlatform
+ Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Assert GPIO
+ Data32 = 0;
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# UplinkPortIndex
+ Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
+ Status = TypeJunctionCityPlatformUpdateAcpiTablePcds ();
+ //# BMC Pcie Port Number
+ PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
+ ASSERT_EFI_ERROR(Status);
+
+ //# Board Type Bit Mask
+ PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
+ ASSERT_EFI_ERROR(Status);
+
+ //Update IMON Address
+ TypeJunctionCityPlatformUpdateImonAddress ();
+
+ return Status;
+}
+
+PLATFORM_PCD_UPDATE_TABLE TypeJunctionCityPcdUpdateTable =
+{
+ PLATFORM_PCD_UPDATE_SIGNATURE,
+ PLATFORM_PCD_UPDATE_VERSION,
+ TypeJunctionCityPlatformPcdUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPcdConfigDataGuid,
+ &TypeJunctionCityPcdUpdateTable,
+ sizeof(TypeJunctionCityPcdUpdateTable)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PchEarlyUpdate.c
new file mode 100644
index 0000000000..e8cc05155a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PchEarlyUpdate.c
@@ -0,0 +1,93 @@
+/** @file
+ Pch Early update.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/UbaPchEarlyUpdateLib.h>
+
+#include <PchAccess.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+TypeJunctionCityPchLanConfig (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
+ DynamicSiLibraryPpi->PchDisableGbe ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+TypeJunctionCityOemInitLateHook (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ return EFI_SUCCESS;
+}
+
+
+PLATFORM_PCH_EARLY_UPDATE_TABLE TypeJunctionCityPchEarlyUpdateTable =
+{
+ PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
+ PLATFORM_PCH_EARLY_UPDATE_VERSION,
+ TypeJunctionCityPchLanConfig,
+ TypeJunctionCityOemInitLateHook
+};
+
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPchEarlyUpdate(
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchEarlyConfigDataGuid,
+ &TypeJunctionCityPchEarlyUpdateTable,
+ sizeof(TypeJunctionCityPchEarlyUpdateTable)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInit.h
new file mode 100644
index 0000000000..1c596a30c4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInit.h
@@ -0,0 +1,78 @@
+/** @file
+ PeiBoardInit.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_PEIM_H_
+#define _PEI_BOARD_INIT_PEIM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/UbaCfgDb.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+);
+
+EFI_STATUS
+TypeJunctionCityInstallClockgenData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPchEarlyUpdate (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+) ;
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+#endif // _PEI_BOARD_INIT_PEIM_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.c
new file mode 100644
index 0000000000..8cc76a5db3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.c
@@ -0,0 +1,157 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+/**
+ The constructor function for Board Init Libray.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Table initialization successfully.
+ @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table.
+**/
+
+#include "PeiBoardInit.h"
+#include <UncoreCommonIncludes.h>
+#include <Library/PchMultiPchBase.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPeiBoardInitLibConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UBA_CONFIG_DATABASE_PPI *UbaConfigPpi;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ UINT8 SocketIndex;
+ UINT8 ChannelIndex;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+
+ if (PlatformInfo->BoardId == TypeJunctionCity) {
+
+ DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: JunctionCity\n", PlatformInfo->BoardId));
+
+ // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+ for (ChannelIndex = 0; ChannelIndex < MAX_CH; ChannelIndex++) {
+ switch (SocketIndex) {
+ case 0:
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorSmt;
+ break;
+ case 1:
+ // Fall through since socket 1 is PTH type
+ default:
+ // Use the more restrictive type as the default case
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorPth;
+ break;
+ }
+ }
+ }
+
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfo),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->InitSku (
+ UbaConfigPpi,
+ PlatformInfo->BoardId,
+ NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = TypeJunctionCityInstallGpioData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallPcdData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSoftStrapData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPchEarlyUpdate (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPlatformUpdateUsbOcMappings (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSlotTableData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallKtiEparamData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+
+ //
+ // Set default memory type connector.
+ // Socket 0: DimmConnectorSmt
+ // Socket 1: DimmConnectorPth
+ //
+ if (SocketIndex % 2 == 0) {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorSmt);
+ } else {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorPth);
+ }
+ }
+
+ //
+ // Initialize InterposerType to InterposerUnknown
+ //
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
+ PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown;
+ }
+
+ //
+ // TypeJunctionCityIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO.
+ //
+ Status = TypeJunctionCityIioPortBifurcationInit (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+ return Status;
+}
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf
new file mode 100644
index 0000000000..ee6fdb95ff
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf
@@ -0,0 +1,167 @@
+## @file
+# Component information file for BoardInitLib in PEI post memory phase.
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TypeJunctionCityPeiBoardInitLib
+ FILE_GUID = F92478AE-058E-4E2A-939C-B806D461398E
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+ CONSTRUCTOR = TypeJunctionCityPeiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PeiServicesLib
+ HobLib
+ PeiServicesTablePointerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[Sources]
+ PeiBoardInitLib.c
+ GpioTable.c
+ PcdData.c
+ UsbOC.c
+ AcpiTablePcds.c
+ IioBifurInit.c
+ SlotTable.c
+ KtiEparam.c
+ PchEarlyUpdate.c
+ SoftStrapFixup.c
+ PeiBoardInit.h
+
+[FixedPcd]
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
+ gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
+
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
+
+[Ppis]
+ gUbaConfigDatabasePpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Guids]
+ gPlatformGpioInitDataGuid
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SlotTable.c
new file mode 100644
index 0000000000..963515ea41
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SlotTable.c
@@ -0,0 +1,172 @@
+/** @file
+ Slot Table Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+#define PCI_DEVICE_ON_BOARD_TRUE 0
+#define PCI_DEVICE_ON_BOARD_FALSE 1
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+static UINT8 TypeJunctionCityPchPciSlotImpementedTableData[] = {
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18
+ PCI_DEVICE_ON_BOARD_FALSE // Root Port 19
+};
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeJunctionCityPchPciSlotImplementedTable = {
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ TypeJunctionCityPchPciSlotImpementedTableData
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid2,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPciSlotImplementedGuid,
+ &TypeJunctionCityPchPciSlotImplementedTable,
+ sizeof(TypeJunctionCityPchPciSlotImplementedTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SoftStrapFixup.c
new file mode 100644
index 0000000000..541961b020
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/SoftStrapFixup.c
@@ -0,0 +1,121 @@
+/** @file
+ Soft Strap update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSoftStrapUpdateLib.h>
+
+PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeJunctionCitySoftStrapTable[] =
+{
+// SoftStrapNumber, LowBit, BitLength, Value
+ {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select
+ {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control
+ {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2)
+ {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3)
+ {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8)
+ {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2)
+ {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3)
+ {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled
+ {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2
+ {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3
+ {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0
+ {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1
+ {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2
+ {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3
+ {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4
+ {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2
+ {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5
+ {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6
+ {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7
+ {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS)
+ {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address
+ {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address
+ {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable
+ {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect
+ {88, 8, 2, 0x3 }, // Root Port Configuration 0
+ {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12
+ {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13
+ {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14
+ {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15
+ {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16
+ {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17
+ {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18
+ {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19
+ {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12
+ {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13
+ {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14
+ {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15
+ {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16
+ {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17
+ {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18
+ {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19
+ {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection
+ {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled
+ {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled
+// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled
+// {133, 2, 1, 0x1 }, // Quad Output Read Enabled
+// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled
+// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode
+// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable
+// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency
+// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode
+
+//
+// END OF LIST
+//
+ {0, 0, 0, 0}
+};
+
+UINT32
+TypeJunctionCitySystemBoardRevIdValue (VOID)
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT(GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return 0xFF;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+ return PlatformInfo->TypeRevisionId;
+}
+
+VOID
+TypeJunctionCityPlatformSpecificUpdate (
+ IN OUT UINT8 *FlashDescriptorCopy
+ )
+{
+}
+
+PLATFORM_PCH_SOFTSTRAP_UPDATE TypeJunctionCitySoftStrapUpdate =
+{
+ PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
+ PLATFORM_SOFT_STRAP_UPDATE_VERSION,
+ TypeJunctionCitySoftStrapTable,
+ TypeJunctionCityPlatformSpecificUpdate
+};
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchSoftStrapConfigDataGuid,
+ &TypeJunctionCitySoftStrapUpdate,
+ sizeof(TypeJunctionCitySoftStrapUpdate)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/UsbOC.c
new file mode 100644
index 0000000000..eaf59de869
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/UsbOC.c
@@ -0,0 +1,127 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+
+#include <Library/PcdLib.h>
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin5,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ //#
+ //# USB, see PG 104 in GZP SCH
+ //#
+
+// USB2 USB3 Port OC
+//
+//Port00: PORT5 Back Panel ,OC0#
+//Port01: PORT2 Back Panel ,OC0#
+//Port02: PORT3 Back Panel ,OC1#
+//Port03: PORT0 NOT USED ,NA
+//Port04: BMC1.0 ,NA
+//Port05: INTERNAL_2X5_A ,OC2#
+//Port06: INTERNAL_2X5_A ,OC2#
+//Port07: NOT USED ,NA
+//Port08: EUSB (AKA SSD) ,NA
+//Port09: INTERNAL_TYPEA ,OC6#
+//Port10: PORT1 Front Panel ,OC5#
+//Port11: NOT USED ,NA
+//Port12: BMC2.0 ,NA
+//Port13: PORT4 Front Panel ,OC5#
+
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPeiPlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
new file mode 100644
index 0000000000..4125ece197
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
@@ -0,0 +1,127 @@
+# @ build_board.py
+# Extensions for building JunctionCity using build_bios.py
+#
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("pre_build_ex")
+ config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+ 'Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ # set BUILD_DIR path
+ config["BUILD_DIR"] = os.path.join('Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+ config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+ if not os.path.isdir(config["BUILD_DIR_PATH"]):
+ try:
+ os.makedirs(config["BUILD_DIR_PATH"])
+ except OSError:
+ print("Error while creating Build folder")
+ sys.exit(1)
+
+ #@todo: Replace this with PcdFspModeSelection
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+ else:
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable")
+ return None
+
+def _merge_files(files, ofile):
+ with open(ofile, 'wb') as of:
+ for x in files:
+ if not os.path.exists(x):
+ return
+
+ with open(x, 'rb') as f:
+ of.write(f.read())
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ binary_fd = os.path.join(fv_path, "BINARY.fd")
+ main_fd = os.path.join(fv_path, "MAIN.fd")
+ secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ final_ifwi = os.path.join(fv_path, "{}.bin".format(board_fd))
+
+ ifwi_ingredients_path = os.path.join(config["WORKSPACE_PLATFORM_BIN"], "Ifwi", config["BOARD"])
+ flash_descriptor = os.path.join(ifwi_ingredients_path, "FlashDescriptor.bin")
+ intel_me = os.path.join(ifwi_ingredients_path, "Me.bin")
+ _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi)
+ if os.path.isfile(final_fd):
+ print("IFWI image can be found at {}".format(final_ifwi))
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
new file mode 100644
index 0000000000..602987b922
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
@@ -0,0 +1,37 @@
+# @ build_config.cfg
+# This is the JunctionCity board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/WhitleyOpenBoardBinPkg
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/JunctionCity
+BOARD = JunctionCity
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/JunctionCity/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 4
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = WhitleyFspBinPkg
+FSP_PKG_NAME = WhitleyFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c
index 3652695fba..e638e6f941 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c
@@ -1,761 +1,774 @@
-/** @file

- Platform Info PEIM.

-

- @copyright

- Copyright 1999 - 2021 Intel Corporation.

-

- SPDX-License-Identifier: BSD-2-Clause-Patent

-**/

-

-#include "PlatformInfo.h"

-#include <GpioPinsSklH.h>

-#include <Library/GpioLib.h>

-#include <Library/PchInfoLib.h>

-

-#include <Ppi/DynamicSiLibraryPpi.h>

-

-#include <Library/UbaGpioPlatformConfig.h>

-#include <UncoreCommonIncludes.h>

-#include <PlatformInfoTypes.h>

-

-#include <Library/PeiServicesLib.h>

-

-#define TEMP_BUS_NUMBER (0x3F)

-

-

-STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi = {

- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,

- &gEfiPlatformInfoGuid,

- NULL

- };

-

-#define BOARD_ID_GPIO_PADS_NUMBER 6

-#define BOARD_REV_ID_GPIO_PADS_NUMBER 3

-

-//

-// These pads shall not be board specific as these are used for Board ID and Rev ID detection

-// Therefore can not be moved to UBA and are common for all Purley boards

-//

-GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] = {

- // BoardId pads - PADCFG register for GPIO G12

- // WARNING: The pad number must be obtained from board schematics

- GPIO_SKL_H_GPP_G12,

- GPIO_SKL_H_GPP_G13,

- GPIO_SKL_H_GPP_G14,

- GPIO_SKL_H_GPP_G15,

- GPIO_SKL_H_GPP_G16,

- GPIO_SKL_H_GPP_B19

-};

-

-GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] = {

- // Board RevId pads - Start from pad C12

- // WARNING: This should be obtained from board schematics

- GPIO_SKL_H_GPP_C12,

- GPIO_SKL_H_GPP_C13,

- GPIO_SKL_H_GPP_B9

-};

-

-GPIO_CONFIG mBoardAndRevIdConfig = {

- // Board and Revision ID pads configuration required for proper reading the values

- GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,

- GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default

-};

-

-

-VOID

-GpioConfigForBoardId (

- VOID

- )

-{

- UINT8 i;

- EFI_STATUS Status;

- GPIO_CONFIG PadConfig;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;

- PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;

- PadConfig.Direction = mBoardAndRevIdConfig.Direction;

- PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;

- PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;

- PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;

- PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;

- PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;

- PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return;

- }

-

- for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {

- Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadConfig);

- ASSERT_EFI_ERROR (Status);

- }

-}

-

-

-VOID

-GpioConfigForBoardRevId (

- VOID

- )

-{

- UINT8 i;

- EFI_STATUS Status;

- GPIO_CONFIG PadConfig;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;

- PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;

- PadConfig.Direction = mBoardAndRevIdConfig.Direction;

- PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;

- PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;

- PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;

- PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;

- PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;

- PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return;

- }

-

- for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) {

- Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &PadConfig);

- ASSERT_EFI_ERROR (Status);

- }

-}

-

-/**

-

- Reads GPIO pins to get Board ID value

-

- @retval Status - Success if GPIO's are read properly

-

-**/

-EFI_STATUS

-GpioGetBoardId (

- OUT UINT32 *BoardId

- )

-{

- EFI_STATUS Status = EFI_DEVICE_ERROR;

- UINT32 Data32;

- UINT8 i;

- UINT32 BdId;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- if (BoardId == NULL) {

- return EFI_UNSUPPORTED;

- }

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return Status;

- }

-

- BdId = 0;

-

- GpioConfigForBoardId ();

-

- for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {

- Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data32);

- if (EFI_ERROR(Status)) {

- break;

- }

- if (Data32) {

- BdId = BdId | (1 << i);

- }

- }

- if (Status != EFI_SUCCESS) {

- return Status;

- }

- *BoardId = BdId;

- return EFI_SUCCESS;

-}

-

-/**

-

- Reads GPIO pins to get Board Revision ID value

-

- @retval Status - Success if GPIO's are read properly

-

-**/

-EFI_STATUS

-GpioGetBoardRevId (

- OUT UINT32 *BoardRevId

- )

-{

- EFI_STATUS Status = EFI_DEVICE_ERROR;

- UINT32 Data32;

- UINT8 i;

- UINT32 RevId;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- if (BoardRevId == NULL) {

- return EFI_UNSUPPORTED;

- }

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return Status;

- }

-

- RevId = 0;

-

- GpioConfigForBoardRevId ();

-

- for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){

- Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &Data32);

- if (EFI_ERROR(Status)) {

- break;

- }

- if (Data32) {

- RevId = RevId | (1 << i);

- }

- }

- if (Status != EFI_SUCCESS) {

- return Status;

- }

- *BoardRevId = RevId;

- return EFI_SUCCESS;

-

-}

-

-/**

-

- Returns the Model ID of the CPU.

- Model ID = EAX[7:4]

-

-**/

-VOID

-GetCpuInfo (

- UINT32 *CpuType,

- UINT8 *CpuStepping

- )

-

-{

- UINT32 RegEax=0;

-

- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);

-

- *CpuStepping = (UINT8) (RegEax & 0x0F);

- *CpuType = (UINT32) (RegEax >> 4);

-}

-

-

-/**

-

- GC_TODO: add routine description

-

- @param BAR - GC_TODO: add arg description

- @param PeiServices - GC_TODO: add arg description

-

- @retval None

-

-**/

-VOID

-InitGSX(

- UINT32 *BAR,

- IN EFI_PEI_SERVICES **PeiServices

-)

-{

-}

-

-/**

-

- GC_TODO: add routine description

-

- @param Data - GC_TODO: add arg description

- @param PeiServices - GC_TODO: add arg description

-

- @retval EFI_SUCCESS - GC_TODO: add retval description

- @retval EFI_UNSUPPORTED - GC_TODO: add retval description

-

-**/

-EFI_STATUS

-GsxRead(

- UINT32 *Data,

- IN EFI_PEI_SERVICES **PeiServices

-)

-{

- return EFI_UNSUPPORTED;

-}

-

-/**

-

- GC_TODO: add routine description

-

- @param Data - GC_TODO: add arg description

- @param PeiServices - GC_TODO: add arg description

-

- @retval None

-

-**/

-VOID

-GetGsxBoardID(

- BOARD_ID *Data,

- IN EFI_PEI_SERVICES **PeiServices

-)

-{

-

- EFI_STATUS Status;

- UINT32 GSXIN[2];

- UINT32 RetryCount;

-

- RetryCount = 0;

- GSXIN[0] = 0;

- GSXIN[1] = 0;

-

- do {

- Status = GsxRead(GSXIN, PeiServices);

-

- if(Status){

- // if EFI_SUCCESS != Success then retry one more time

- RetryCount ++;

- }else{

- // if EFI_SUCCESS read Board ID and exit

- RetryCount = 0xFFFFFFFF;

- }

-

- if (GSXIN[0] & BIT0) {

- Data->BoardID.BoardID0 = 1;

- }

-

- if (GSXIN[0] & BIT1) {

- Data->BoardID.BoardID1 = 1;

- }

-

- if (GSXIN[0] & BIT2) {

- Data->BoardID.BoardID2 = 1;

- }

-

- if (GSXIN[0] & BIT3) {

- Data->BoardID.BoardID3 = 1;

- }

-

- if (GSXIN[0] & BIT4) {

- Data->BoardID.BoardID4 = 1;

- }

-

- if (GSXIN[0] & BIT5) {

- Data->BoardID.BoardRev0 = 1;

- }

-

- if (GSXIN[0] & BIT6) {

- Data->BoardID.BoardRev1 = 1;

- }

-

- } while(RetryCount < 1);

-

- if(Status){

- //

- // Unhable to read GSX HW error Hang the system

- //

- DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n"));

- CpuDeadLoop ();

- }

-}

-

-/**

- Get Platform Type by read Platform Data Region in SPI flash.

- SPI Descriptor Mode Routines for Accessing Platform Info from Platform Data Region (PDR)

-

- @param PeiServices - General purpose services available to every PEIM.

- @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob->BoardId

-

- @retval Status EFI_SUCCESS - PDR read success

- @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid Platform Type

-

-**/

-EFI_STATUS

-PdrGetPlatformInfo (

- IN CONST EFI_PEI_SERVICES **PeiServices,

- OUT EFI_PLATFORM_INFO *PlatformInfoHob

- )

-{

- EFI_STATUS Status;

- PCH_SPI_PROTOCOL *SpiPpi;

- UINTN Size;

-

- //

- // Locate the SPI PPI Interface

- //

- Status = (*PeiServices)->LocatePpi (

- PeiServices,

- &gPchSpiPpiGuid,

- 0,

- NULL,

- &SpiPpi

- );

-

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return Status;

- }

-

- //

- // Read the PIT (Platform Info Table) from the SPI Flash Platform Data Region

- //

- Size = sizeof (EFI_PLATFORM_INFO);

- Status = SpiPpi->FlashRead (

- SpiPpi,

- FlashRegionPlatformData,

- PDR_REGION_START_OFFSET,

- (UINT32) Size,

- (UINT8 *) PlatformInfoHob

- );

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return Status;

- }

-

- if ((PlatformInfoHob->BoardId >= TypePlatformMin) && (PlatformInfoHob->BoardId <= TypePlatformMax)) {

- //

- // Valid Platform Identified

- //

- DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type = %x\n",PlatformInfoHob->BoardId));

- } else {

- //

- // Reading PIT from SPI PDR Failed or a unknown platform identified

- //

- DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId));

- PlatformInfoHob->BoardId = TypePlatformUnknown;

- Status = EFI_INCOMPATIBLE_VERSION;

- }

- return Status;

-}

-

-VOID

-GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob)

-/**

-

- GC_TODO: add routine description

-

- @param None

-

- @ret None

-**/

-{

- EFI_STATUS Status;

- GPIO_CONFIG PadConfig;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- // Gpio programming to QAT board detection

- PadConfig.PadMode = GpioPadModeGpio;

- PadConfig.HostSoftPadOwn = GpioHostOwnDefault;

- PadConfig.Direction = GpioDirIn;

- PadConfig.OutputState = GpioOutLow;

- PadConfig.InterruptConfig = GpioIntDis;

- PadConfig.PowerConfig = GpioResetPwrGood;

- PadConfig.ElectricalConfig = GpioTermNone;

- PadConfig.LockConfig = GpioPadConfigLock;

- PadConfig.OtherSettings = 00;

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return;

- }

-

- Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &PadConfig);

- Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &PlatformInfoHob->QATDis);

- Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &PadConfig);

- Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &PlatformInfoHob->QATSel);

-}

-

-EFI_STATUS

-GetPlatformInfo (

- IN CONST EFI_PEI_SERVICES **PeiServices,

- OUT EFI_PLATFORM_INFO *PlatformInfoHob

- )

-/**

-

- GC_TODO: add routine description

-

- @param PeiServices - GC_TODO: add arg description

- @param PlatformInfoHob - GC_TODO: add arg description

-

- @retval EFI_UNSUPPORTED - GC_TODO: add retval description

- @retval EFI_SUCCESS - GC_TODO: add retval description

-

-**/

-{

-

-

- UINT32 BoardId;

- UINT32 BoardRev;

- EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;

- EFI_STATUS Status;

-

- PciCfgPpi = (**PeiServices).PciCfg;

- ASSERT (PciCfgPpi != NULL);

-

- PlatformInfoHob->BoardId = TypeNeonCityEPRP;

- DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n"));

-

- Status = GpioGetBoardId (&BoardId);

- if (EFI_ERROR (Status)) {

- DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));

- return Status;

- }

- Status = GpioGetBoardRevId (&BoardRev);

- if (EFI_ERROR(Status)) {

- DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));

- return Status;

- }

- PlatformInfoHob->TypeRevisionId = BoardRev;

-

- switch (BoardId) {

- case 0x00: // for Simics

- PlatformInfoHob->BoardId = TypeWilsonCityRP;

- break;

- case 0x01:

- PlatformInfoHob->BoardId = TypeWilsonCityRP;

- DEBUG ((DEBUG_INFO, "Board ID = TypeWilsonCityRP\n"));

- break;

- case 0x12:

- PlatformInfoHob->BoardId = TypeWilsonCityRP;

- DEBUG((DEBUG_INFO, "Board ID = TypeWilsonCityRP\n"));

- break;

- case 0x15:

- PlatformInfoHob->BoardId = TypeWilsonCitySMT;

- DEBUG((DEBUG_INFO, "Board ID = TypeWilsonCitySMT\n"));

- break;

- case 0x17:

- case 0x18:

- PlatformInfoHob->BoardId = TypeCooperCityRP;

- DEBUG((DEBUG_INFO, "Board ID = TypeCooperCityRP\n"));

- break;

- default:

- PlatformInfoHob->BoardId = TypePlatformDefault;

- DEBUG ((DEBUG_INFO, "Board ID = %2X Default set to TypePlatformDefault\n",BoardId));

- break;

- }

-

- GatherQATInfo(PlatformInfoHob);

-

- DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev));

- return EFI_SUCCESS;

-}

-

-/**

-

- This function initializes the board related flag to indicates if

- PCH and Lan-On-Motherboard (LOM) devices is supported.

-

-**/

-VOID

-GetPchLanSupportInfo(

- IN EFI_PLATFORM_INFO *PlatformInfoHob

- )

-{

- PlatformInfoHob->PchData.LomLanSupported = 0;

-}

-

-/**

-

- GC_TODO: add routine description

-

- @param PeiVariable - GC_TODO: add arg description

- @param PlatformInfoHob - GC_TODO: add arg description

-

- @retval EFI_SUCCESS - GC_TODO: add retval description

-

-**/

-EFI_STATUS

-EFIAPI

-GetIioCommonRcPlatformSetupPolicy(

- OUT EFI_PLATFORM_INFO *PlatformInfoHob

- )

- {

- UINT8 IsocEn;

-

- CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_OF(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8));

-

- PlatformInfoHob->SysData.IsocEn = IsocEn; // ISOC enabled

-

- return EFI_SUCCESS;

-}

-/**

-

- GC_TODO: add routine description

-

- @param PeiVariable - GC_TODO: add arg description

- @param PlatformInfoHob - GC_TODO: add arg description

-

- @retval EFI_SUCCESS - GC_TODO: add retval description

-

-**/

-EFI_STATUS

-EFIAPI

-GetIioPlatformSetupPolicy(

- OUT EFI_PLATFORM_INFO *PlatformInfoHob

- )

-{

- return EFI_SUCCESS;

-}

-

-

-/**

- Platform Type detection. Because the PEI globle variable

- is in the flash, it could not change directly.So use

- 2 PPIs to distinguish the platform type.

-

- @param FfsHeader - Pointer to Firmware File System file header.

- @param PeiServices - General purpose services available to every PEIM.

-

- @retval EFI_SUCCESS - Memory initialization completed successfully.

- @retval Others - All other error conditions encountered result in an ASSERT.

-

-**/

-EFI_STATUS

-EFIAPI

-PlatformInfoInit (

- IN EFI_PEI_FILE_HANDLE FileHandle,

- IN CONST EFI_PEI_SERVICES **PeiServices

- )

-{

- EFI_STATUS Status;

- EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;

- EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;

- EFI_PLATFORM_INFO PlatformInfoHob;

- EFI_PLATFORM_INFO tempPlatformInfoHob;

- UINT8 ChipId;

- UINT32 Delay;

- UINT32 CpuType;

- UINT8 CpuStepping;

- DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;

-

- PciCfgPpi = (**PeiServices).PciCfg;

- if (PciCfgPpi == NULL) {

- DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a NULL Pointer!!!\n"));

- ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);

- return EFI_INVALID_PARAMETER;

- }

-

- //

- // Locate Variable PPI

- //

- Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &PeiVariable);

-

- (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0);

-

- Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);

- if (EFI_ERROR (Status)) {

- ASSERT_EFI_ERROR (Status);

- return Status;

- }

-

- //

- // --------------------------------------------------

- //

- // Detect the iBMC SIO for CV/CRB Platforms

- // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM.

- //

- IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK);

- for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);

- IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG);

- for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);

- ChipId = IoRead8 (PILOTIV_SIO_DATA_PORT);

- for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);

- IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK);

- for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);

-

- if (EFI_ERROR (Status))

- {

- DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n"));

- }

-

- Status = GetIioPlatformSetupPolicy (&PlatformInfoHob);

- ASSERT_EFI_ERROR (Status);

- Status = GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob);

- ASSERT_EFI_ERROR (Status);

-

- //

- // Update PCH Type

- //

- PlatformInfoHob.PchType = DynamicSiLibraryPpi->GetPchSeries ();

- PlatformInfoHob.PchSku = DynamicSiLibraryPpi->GetPchLpcDeviceId ();

- PlatformInfoHob.PchRevision = (UINT8) DynamicSiLibraryPpi->PchStepping ();

- PlatformInfoHob.MaxNumOfPchs = 1;

- Status = EFI_SUCCESS;

-

- if(!EFI_ERROR(Status)) {

- Status = GetPlatformInfo (PeiServices, &PlatformInfoHob);

- if(EFI_ERROR (Status)) {

- Status = PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob);

- PlatformInfoHob.BoardId = tempPlatformInfoHob.BoardId;

- PlatformInfoHob.TypeRevisionId = tempPlatformInfoHob.TypeRevisionId;

- if (EFI_ERROR(Status)) {

- PlatformInfoHob.BoardId = TypePlatformUnknown;

- }

- }

- } else {

- PlatformInfoHob.BoardId = TypePlatformUnknown;

- }

-

- //

- // Update IIO Type

- //

- PlatformInfoHob.IioRevision = 0;

-

-

- //

- // Get Subtractive decode enable bit from descriptor

- //

-

- if (DynamicSiLibraryPpi->PchIsGbeRegionValid () == FALSE) {

- PlatformInfoHob.PchData.GbeRegionInvalid = 1;

- } else {

- PlatformInfoHob.PchData.GbeRegionInvalid = 0;

- }

- GetPchLanSupportInfo (&PlatformInfoHob);

- PlatformInfoHob.PchData.GbePciePortNum = 0xFF;

- PlatformInfoHob.PchData.GbePciePortNum = (UINT8) DynamicSiLibraryPpi->PchGetGbePortNumber ();

- PlatformInfoHob.PchData.GbeEnabled = DynamicSiLibraryPpi->PchIsGbePresent ();

- PlatformInfoHob.PchData.PchStepping = (UINT8) DynamicSiLibraryPpi->PchStepping ();

-

- PlatformInfoHob.SysData.SysSioExist = (UINT8)IsSioExist();

-

- GetCpuInfo (&CpuType, &CpuStepping);

- PlatformInfoHob.CpuType = CpuType;

- PlatformInfoHob.CpuStepping = CpuStepping;

-

- //

- // Set default memory topology to DaisyChainTopology. This should be modified in UBA board

- // specific file.

- //

- (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (PlatformInfoHob.MemoryTopology), DaisyChainTopology);

-

- //

- // Set default memory type connector to DimmConnectorPth. This should be modified in UBA board

- // specific file.

- //

- (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (PlatformInfoHob.MemoryConnectorType), DimmConnectorPth);

-

- //

- // Build HOB for setup memory information

- //

- BuildGuidDataHob (

- &gEfiPlatformInfoGuid,

- &(PlatformInfoHob),

- sizeof (EFI_PLATFORM_INFO)

- );

-

- Status = (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi);

- ASSERT_EFI_ERROR (Status);

-

- //

- // Save PlatformInfoHob.BoardId in CMOS

- //

- IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO);

- IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId);

-

- IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI);

- IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2Type << 4) + (PlatformInfoHob.PcieRiser1Type)));

-

- return EFI_SUCCESS;

-}

+/** @file
+ Platform Info PEIM.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInfo.h"
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Library/PchInfoLib.h>
+
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+#include <Library/UbaGpioPlatformConfig.h>
+#include <UncoreCommonIncludes.h>
+#include <PlatformInfoTypes.h>
+
+#include <Library/PeiServicesLib.h>
+
+#define TEMP_BUS_NUMBER (0x3F)
+
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPlatformInfoGuid,
+ NULL
+ };
+
+#define BOARD_ID_GPIO_PADS_NUMBER 6
+#define BOARD_REV_ID_GPIO_PADS_NUMBER 3
+
+//
+// These pads shall not be board specific as these are used for Board ID and Rev ID detection
+// Therefore can not be moved to UBA and are common for all Purley boards
+//
+GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] = {
+ // BoardId pads - PADCFG register for GPIO G12
+ // WARNING: The pad number must be obtained from board schematics
+ GPIO_SKL_H_GPP_G12,
+ GPIO_SKL_H_GPP_G13,
+ GPIO_SKL_H_GPP_G14,
+ GPIO_SKL_H_GPP_G15,
+ GPIO_SKL_H_GPP_G16,
+ GPIO_SKL_H_GPP_B19
+};
+
+GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] = {
+ // Board RevId pads - Start from pad C12
+ // WARNING: This should be obtained from board schematics
+ GPIO_SKL_H_GPP_C12,
+ GPIO_SKL_H_GPP_C13,
+ GPIO_SKL_H_GPP_B9
+};
+
+GPIO_CONFIG mBoardAndRevIdConfig = {
+ // Board and Revision ID pads configuration required for proper reading the values
+ GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
+ GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default
+};
+
+
+VOID
+GpioConfigForBoardId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+
+VOID
+GpioConfigForBoardRevId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+
+ Reads GPIO pins to get Board ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardId (
+ OUT UINT32 *BoardId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 BdId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ BdId = 0;
+
+ GpioConfigForBoardId ();
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ BdId = BdId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardId = BdId;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Reads GPIO pins to get Board Revision ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardRevId (
+ OUT UINT32 *BoardRevId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 RevId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardRevId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ RevId = 0;
+
+ GpioConfigForBoardRevId ();
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ RevId = RevId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardRevId = RevId;
+ return EFI_SUCCESS;
+
+}
+
+/**
+
+ Returns the Model ID of the CPU.
+ Model ID = EAX[7:4]
+
+**/
+VOID
+GetCpuInfo (
+ UINT32 *CpuType,
+ UINT8 *CpuStepping
+ )
+
+{
+ UINT32 RegEax=0;
+
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
+
+ *CpuStepping = (UINT8) (RegEax & 0x0F);
+ *CpuType = (UINT32) (RegEax >> 4);
+}
+
+
+/**
+
+ GC_TODO: add routine description
+
+ @param BAR - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+InitGSX(
+ UINT32 *BAR,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+GsxRead(
+ UINT32 *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+GetGsxBoardID(
+ BOARD_ID *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+
+ EFI_STATUS Status;
+ UINT32 GSXIN[2];
+ UINT32 RetryCount;
+
+ RetryCount = 0;
+ GSXIN[0] = 0;
+ GSXIN[1] = 0;
+
+ do {
+ Status = GsxRead(GSXIN, PeiServices);
+
+ if(Status){
+ // if EFI_SUCCESS != Success then retry one more time
+ RetryCount ++;
+ }else{
+ // if EFI_SUCCESS read Board ID and exit
+ RetryCount = 0xFFFFFFFF;
+ }
+
+ if (GSXIN[0] & BIT0) {
+ Data->BoardID.BoardID0 = 1;
+ }
+
+ if (GSXIN[0] & BIT1) {
+ Data->BoardID.BoardID1 = 1;
+ }
+
+ if (GSXIN[0] & BIT2) {
+ Data->BoardID.BoardID2 = 1;
+ }
+
+ if (GSXIN[0] & BIT3) {
+ Data->BoardID.BoardID3 = 1;
+ }
+
+ if (GSXIN[0] & BIT4) {
+ Data->BoardID.BoardID4 = 1;
+ }
+
+ if (GSXIN[0] & BIT5) {
+ Data->BoardID.BoardRev0 = 1;
+ }
+
+ if (GSXIN[0] & BIT6) {
+ Data->BoardID.BoardRev1 = 1;
+ }
+
+ } while(RetryCount < 1);
+
+ if(Status){
+ //
+ // Unhable to read GSX HW error Hang the system
+ //
+ DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n"));
+ CpuDeadLoop ();
+ }
+}
+
+/**
+ Get Platform Type by read Platform Data Region in SPI flash.
+ SPI Descriptor Mode Routines for Accessing Platform Info from Platform Data Region (PDR)
+
+ @param PeiServices - General purpose services available to every PEIM.
+ @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob->BoardId
+
+ @retval Status EFI_SUCCESS - PDR read success
+ @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid Platform Type
+
+**/
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ EFI_STATUS Status;
+ PCH_SPI_PROTOCOL *SpiPpi;
+ UINTN Size;
+
+ //
+ // Locate the SPI PPI Interface
+ //
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ &SpiPpi
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // Read the PIT (Platform Info Table) from the SPI Flash Platform Data Region
+ //
+ Size = sizeof (EFI_PLATFORM_INFO);
+ Status = SpiPpi->FlashRead (
+ SpiPpi,
+ FlashRegionPlatformData,
+ PDR_REGION_START_OFFSET,
+ (UINT32) Size,
+ (UINT8 *) PlatformInfoHob
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if ((PlatformInfoHob->BoardId >= TypePlatformMin) && (PlatformInfoHob->BoardId <= TypePlatformMax)) {
+ //
+ // Valid Platform Identified
+ //
+ DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type = %x\n",PlatformInfoHob->BoardId));
+ } else {
+ //
+ // Reading PIT from SPI PDR Failed or a unknown platform identified
+ //
+ DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId));
+ PlatformInfoHob->BoardId = TypePlatformUnknown;
+ Status = EFI_INCOMPATIBLE_VERSION;
+ }
+ return Status;
+}
+
+VOID
+GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob)
+/**
+
+ GC_TODO: add routine description
+
+ @param None
+
+ @ret None
+**/
+{
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ // Gpio programming to QAT board detection
+ PadConfig.PadMode = GpioPadModeGpio;
+ PadConfig.HostSoftPadOwn = GpioHostOwnDefault;
+ PadConfig.Direction = GpioDirIn;
+ PadConfig.OutputState = GpioOutLow;
+ PadConfig.InterruptConfig = GpioIntDis;
+ PadConfig.PowerConfig = GpioResetPwrGood;
+ PadConfig.ElectricalConfig = GpioTermNone;
+ PadConfig.LockConfig = GpioPadConfigLock;
+ PadConfig.OtherSettings = 00;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &PlatformInfoHob->QATDis);
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &PlatformInfoHob->QATSel);
+}
+
+EFI_STATUS
+GetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiServices - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+{
+
+
+ UINT32 BoardId;
+ UINT32 BoardRev;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_STATUS Status;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ ASSERT (PciCfgPpi != NULL);
+
+ PlatformInfoHob->BoardId = TypeNeonCityEPRP;
+
+ //
+ //Check if BoardId is fixed during build time.
+ //
+ BoardId = FixedPcdGet8 (PcdBoardId);
+ if (BoardId != 0) {
+ PlatformInfoHob->BoardId = (UINT8)BoardId;
+ PlatformInfoHob->TypeRevisionId = FixedPcdGet8 (PcdBoardRevId);
+ DEBUG((DEBUG_INFO, "Board ID = %2x Board Rev = %x \n", PlatformInfoHob->BoardId, PlatformInfoHob->TypeRevisionId));
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n"));
+
+ Status = GpioGetBoardId (&BoardId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ Status = GpioGetBoardRevId (&BoardRev);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ PlatformInfoHob->TypeRevisionId = BoardRev;
+
+ switch (BoardId) {
+ case 0x00: // for Simics
+ PlatformInfoHob->BoardId = TypeWilsonCityRP;
+ break;
+ case 0x01:
+ PlatformInfoHob->BoardId = TypeWilsonCityRP;
+ DEBUG ((DEBUG_INFO, "Board ID = TypeWilsonCityRP\n"));
+ break;
+ case 0x12:
+ PlatformInfoHob->BoardId = TypeWilsonCityRP;
+ DEBUG((DEBUG_INFO, "Board ID = TypeWilsonCityRP\n"));
+ break;
+ case 0x15:
+ PlatformInfoHob->BoardId = TypeWilsonCitySMT;
+ DEBUG((DEBUG_INFO, "Board ID = TypeWilsonCitySMT\n"));
+ break;
+ case 0x17:
+ case 0x18:
+ PlatformInfoHob->BoardId = TypeCooperCityRP;
+ DEBUG((DEBUG_INFO, "Board ID = TypeCooperCityRP\n"));
+ break;
+ default:
+ PlatformInfoHob->BoardId = TypePlatformDefault;
+ DEBUG ((DEBUG_INFO, "Board ID = %2X Default set to TypePlatformDefault\n",BoardId));
+ break;
+ }
+
+ GatherQATInfo(PlatformInfoHob);
+
+ DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev));
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function initializes the board related flag to indicates if
+ PCH and Lan-On-Motherboard (LOM) devices is supported.
+
+**/
+VOID
+GetPchLanSupportInfo(
+ IN EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ PlatformInfoHob->PchData.LomLanSupported = 0;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioCommonRcPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+ {
+ UINT8 IsocEn;
+
+ CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_OF(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8));
+
+ PlatformInfoHob->SysData.IsocEn = IsocEn; // ISOC enabled
+
+ return EFI_SUCCESS;
+}
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Type detection. Because the PEI globle variable
+ is in the flash, it could not change directly.So use
+ 2 PPIs to distinguish the platform type.
+
+ @param FfsHeader - Pointer to Firmware File System file header.
+ @param PeiServices - General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS - Memory initialization completed successfully.
+ @retval Others - All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformInfoInit (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ EFI_PLATFORM_INFO PlatformInfoHob;
+ EFI_PLATFORM_INFO tempPlatformInfoHob;
+ UINT8 ChipId;
+ UINT32 Delay;
+ UINT32 CpuType;
+ UINT8 CpuStepping;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ if (PciCfgPpi == NULL) {
+ DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a NULL Pointer!!!\n"));
+ ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Locate Variable PPI
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &PeiVariable);
+
+ (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0);
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // --------------------------------------------------
+ //
+ // Detect the iBMC SIO for CV/CRB Platforms
+ // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM.
+ //
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ ChipId = IoRead8 (PILOTIV_SIO_DATA_PORT);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n"));
+ }
+
+ Status = GetIioPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update PCH Type
+ //
+ PlatformInfoHob.PchType = DynamicSiLibraryPpi->GetPchSeries ();
+ PlatformInfoHob.PchSku = DynamicSiLibraryPpi->GetPchLpcDeviceId ();
+ PlatformInfoHob.PchRevision = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+ PlatformInfoHob.MaxNumOfPchs = 1;
+ Status = EFI_SUCCESS;
+
+ if(!EFI_ERROR(Status)) {
+ Status = GetPlatformInfo (PeiServices, &PlatformInfoHob);
+ if(EFI_ERROR (Status)) {
+ Status = PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob);
+ PlatformInfoHob.BoardId = tempPlatformInfoHob.BoardId;
+ PlatformInfoHob.TypeRevisionId = tempPlatformInfoHob.TypeRevisionId;
+ if (EFI_ERROR(Status)) {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+ }
+ } else {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+
+ //
+ // Update IIO Type
+ //
+ PlatformInfoHob.IioRevision = 0;
+
+
+ //
+ // Get Subtractive decode enable bit from descriptor
+ //
+
+ if (DynamicSiLibraryPpi->PchIsGbeRegionValid () == FALSE) {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 1;
+ } else {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 0;
+ }
+ GetPchLanSupportInfo (&PlatformInfoHob);
+ PlatformInfoHob.PchData.GbePciePortNum = 0xFF;
+ PlatformInfoHob.PchData.GbePciePortNum = (UINT8) DynamicSiLibraryPpi->PchGetGbePortNumber ();
+ PlatformInfoHob.PchData.GbeEnabled = DynamicSiLibraryPpi->PchIsGbePresent ();
+ PlatformInfoHob.PchData.PchStepping = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+
+ PlatformInfoHob.SysData.SysSioExist = (UINT8)IsSioExist();
+
+ GetCpuInfo (&CpuType, &CpuStepping);
+ PlatformInfoHob.CpuType = CpuType;
+ PlatformInfoHob.CpuStepping = CpuStepping;
+
+ //
+ // Set default memory topology to DaisyChainTopology. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (PlatformInfoHob.MemoryTopology), DaisyChainTopology);
+
+ //
+ // Set default memory type connector to DimmConnectorPth. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (PlatformInfoHob.MemoryConnectorType), DimmConnectorPth);
+
+ //
+ // Build HOB for setup memory information
+ //
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfoHob),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Save PlatformInfoHob.BoardId in CMOS
+ //
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId);
+
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2Type << 4) + (PlatformInfoHob.PcieRiser1Type)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
index 69d926004d..2eb2d5ab0e 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
@@ -1,63 +1,66 @@
-## @file

-# PlatformInfo PEIM

-#

-# @copyright

-# Copyright 2009 - 2021 Intel Corporation. <BR>

-#

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-##

-

-[Defines]

- INF_VERSION = 0x00010005

- BASE_NAME = PlatformInfo

- FILE_GUID = 34CC6167-7AE7-403e-8AB2-23837F398A30

- MODULE_TYPE = PEIM

- VERSION_STRING = 1.0

- ENTRY_POINT = PlatformInfoInit

-

-#

-# The following information is for reference only and not required by the build tools.

-#

-# VALID_ARCHITECTURES = IA32

-#

-

-[Sources]

- PlatformInfo.c

- PlatformInfo.h

-

-[Packages]

- MdePkg/MdePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- UefiCpuPkg/UefiCpuPkg.dec

-

-[LibraryClasses]

- PeimEntryPoint

- PcdLib

- DebugLib

- HobLib

- IoLib

- PlatformHooksLib

- PeiServicesLib

-

-[Pcd]

- gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig

-

-[Guids]

- gEfiPlatformInfoGuid

- gEfiSetupVariableGuid

-

-[Ppis]

- gPchSpiPpiGuid

- gEfiPeiReadOnlyVariable2PpiGuid

- gDynamicSiLibraryPpiGuid ## CONSUMES

-

-[Depex]

- gPchSpiPpiGuid AND

- gEfiPeiReadOnlyVariable2PpiGuid AND

- gDynamicSiLibraryPpiGuid

-

-

-

+## @file
+# PlatformInfo PEIM
+#
+# @copyright
+# Copyright 2009 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformInfo
+ FILE_GUID = 34CC6167-7AE7-403e-8AB2-23837F398A30
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformInfoInit
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformInfo.c
+ PlatformInfo.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ HobLib
+ IoLib
+ PlatformHooksLib
+ PeiServicesLib
+
+[Pcd]
+ gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig
+ gPlatformTokenSpaceGuid.PcdBoardId
+ gPlatformTokenSpaceGuid.PcdBoardRevId
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gEfiSetupVariableGuid
+
+[Ppis]
+ gPchSpiPpiGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gPchSpiPpiGuid AND
+ gEfiPeiReadOnlyVariable2PpiGuid AND
+ gDynamicSiLibraryPpiGuid
+
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
index 363d4e4059..303baa07cb 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -1,892 +1,901 @@
-## @file

-# Platform Package

-# Cross Platform Modules for Tiano

-#

-# @copyright

-# Copyright 2008 - 2021 Intel Corporation. <BR>

-#

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-##

-

-[Defines]

- DEC_SPECIFICATION = 0x00010005

- PACKAGE_NAME = PlatformPkg

- PACKAGE_GUID = 9A29FD32-8C72-4b25-A7C4-767F7A2838EB

- PACKAGE_VERSION = 0.91

-

-[Includes]

- Include

- Include/Protocol

-

-#TODO: Move these generated temp files into include.

- Uba/BoardInit/Dxe

-

-[Guids]

- gBiosInfoGuid = { 0x1b453c67, 0xcb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } }

- gClvBootTimeTestExecution = { 0x3ff7d152, 0xef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } }

- gUbaCurrentConfigHobGuid = { 0xe4b2025b, 0xc7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } }

-

- gCommonSystemConfigurationGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } }

- gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }

- gEfiSetupVariableDefaultGuid = { 0x8d247131, 0x385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } }

- gEfiGlobalVariableControlGuid = { 0x99a96812, 0x4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } }

- gMainPkgListGuid = { 0x6205c3a4, 0x1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } }

- gAdvancedPkgListGuid = { 0xc09c81cb, 0x31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } }

- gTpmPkgListGuid = { 0x7da45aa9, 0x6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } }

- gSecurityPkgListGuid = { 0x3a885aae, 0x3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } }

- gBootOptionsPkgListGuid = { 0x62197ef0, 0x7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } }

- gEfiOcDataGuid = { 0x4af92599, 0x8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } }

- gEfiDprRegsProgrammedGuid = { 0x4b844201, 0x6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } }

- gPlatformModuleTokenSpaceGuid = { 0x69d13bf0, 0xaf91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } }

- gCpPlatFlashTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }

- gPchSetupVariableGuid = { 0x4570b7f1, 0xade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } }

-

-#

-# UBA_START

-#

- #OEM SKU

- gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } }

- gPlatformKtiEparamUpdateDataGuid = { 0x7bc065cf, 0xafe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } }

- gSmbiosTablesTokenSpaceGuid = { 0x5e80ad48, 0xf240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } }

- gPlatformGpioInitDataGuid = { 0x9282563e, 0xae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } }

-#

-# UBA_END

-#

- gReserveMemFlagVariableGuid = { 0xb87aa73f, 0xdcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } }

- gEfiOpaSocketMapHobGuid = { 0x829d41d2, 0x6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } }

- gEfiPlatformTxtPolicyDataGuid = { 0xa353290b, 0x867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } }

- gEfiSmmPeiSmramMemoryReserveGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } }

- gSystemBoardInfoConfigDataGuid = { 0x68B046F7, 0x15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } }

-

- # Fce multi mode support

- gPlatformVariableHobGuid = { 0x71e6d4bc, 0x4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } }

- gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } }

-

- gCpPlatIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }

- gEfiIpmiFormatFruGuid = { 0x3531fdc6, 0xeae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } }

- gServerCommonIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }

-

- gServerMgmtPkgListGuid = { 0x35dcfcd1, 0xc14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } }

-

-

- ## Include/Guid/CpPlatPkgTokenSpace.h

- gCpPlatTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }

- gEfiSetupEnterGuid = { 0x71202EEE, 0x5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } }

- gEfiSetupExitGuid = { 0xD6E335EC, 0x0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }}

-

- gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } }

-

-[Ppis]

-#

-# UBA_START

-#

- gEfiPeiPlatformTypeWolfPassPpiGuid = { 0xd2a92001, 0x22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } }

- gEfiPeiPlatformTypeNeonCityEPRPPpiGuid = { 0xa2e5609e, 0x8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } }

- gEfiPeiPlatformTypeTennesseePassPpiGuid = { 0xf7b87a79, 0xa640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } }

- gEfiPeiPlatformTypeNeonCityEPECBPpiGuid = { 0x21877e2f, 0xf86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } }

- gEfiPeiPlatformTypeOpalCitySTHIPpiGuid = { 0xa07b3bdf, 0xb78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } }

- gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid = { 0x3c234470, 0x69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } }

- gEfiPeiPlatformTypeCrescentCityPpiGuid = { 0x4ad920ef, 0x4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } }

- gEfiPeiPlatformTypeHedtEVPpiGuid = { 0x41781f4f, 0xa3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } }

- gEfiPeiPlatformTypeHedtCRBPpiGuid = { 0x9bb6e29a, 0x2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } }

- gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid = { 0xaf2417f4, 0x7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } }

- gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid = { 0xf70a4116, 0xfdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } }

- gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid = { 0x0c04b0ff, 0x227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } }

- gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid = { 0x94c0203b, 0x54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } }

- gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid = { 0x4284a11c, 0x18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } }

- gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid = { 0x4f51c243, 0x7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } }

- gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid = { 0x5d9516d3, 0xbc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } }

- gEfiPeiPlatformTypeKyanitePpiGuid = { 0xb23ce2c1, 0x16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } }

- gEfiPeiPlatformTypeNeonCityFPGAPpiGuid = { 0x48e796bd, 0x4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } }

- gEfiPeiPlatformTypeOpalCityFPGAPpiGuid = { 0xe5434b26, 0xaedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } }

- gEfiPeiPlatformTypeWilsonCityRPPpiGuid = { 0x0629aff2, 0x4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } }

- gEfiPeiPlatformTypeWilsonCityModularPpiGuid = { 0x3170ea7b, 0x6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } }

- gEfiPlatformTypeIsoscelesPeakPpiGuid = { 0xfc7b089f, 0x5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } }

-

- gPeiIpmiTransportPpiGuid = { 0x7bf5fecc, 0xc5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } }

-

-#

-# UBA_END

-#

-

- gBoardInitGuid = { 0xecc07551, 0xd64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } }

- gUbaConfigDatabasePpiGuid = { 0xc1176733, 0x159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } }

-

- gPeiSpiSoftStrapsPpiGuid = { 0x7F19E716, 0x419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } }

- gUpdatePcdGuid = { 0xa08e4c6b, 0xff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } }

- gPlatformVariableInitPpiGuid = { 0x9b1b911b, 0x4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } }

- gUpdateBootModePpiGuid = { 0x927186a0, 0xa13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } }

-

- gEfiPeiExStatusCodeHandlerPpiGuid = { 0x4e942617, 0xbbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } }

-

-

-[Protocols]

- gEfiPlatformTypeProtocolGuid = { 0x171e9398, 0x269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } }

- gUbaConfigDatabaseProtocolGuid = { 0xe03e0d46, 0x5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } }

-#

-# UBA_START

-#

- gEfiPlatformTypeNeonCityEPRPProtocolGuid = { 0xc0cd2d36, 0xa81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } }

- gEfiPlatformTypeHedtCRBProtocolGuid = { 0x2c824f87, 0x0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } }

- gEfiPlatformTypeLightningRidgeEXRPProtocolGuid = { 0x1b4ae0f8, 0xed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } }

- gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid = { 0x45b59855, 0x500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } }

- gEfiPlatformTypeWilsonCityRPProtocolGuid = { 0x8430776f, 0xbd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } }

- gEfiPlatformTypeIsoscelesPeakProtocolGuid = { 0xcff3f211, 0x5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } }

- gEfiPlatformTypeWilsonCityModularProtocolGuid = { 0x28e862f4, 0xa4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } }

-

- gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }

- gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }

-

-#

-# UBA_END

-#

-

- gEfiPciIovPlatformProtocolGuid = { 0xf3a4b484, 0x9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } }

- gEfiWindowsInt10Workaround = { 0x387f555, 0x20a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } }

- gEfiVMDDriverProtocolGuid = { 0x5a676ae9, 0xdb23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } }

- gEfiHfiPcieGen3ProtocolGuid = { 0x7b59316e, 0xe9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } }

- gEfiLegacyBiosProtocolGuid = { 0xdb9a1e3d, 0x45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } }

-

- gEfiIpmiSolStatusProtocolGuid = { 0xe790848e, 0xb6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } }

- gEfiIpmiTransportProtocolGuid = { 0x6bb945e8, 0x3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } }

- gSmmIpmiTransportProtocolGuid = { 0x8bb070f1, 0xa8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } }

- gEfiIpmiBootGuid = { 0x5c9b75ec, 0x8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } }

- gEfiGenericIpmiDriverInstalledGuid = { 0x7cdad61a, 0x3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } }

-

- gDmaRemapProtocolGuid = { 0x4e873773, 0x8391, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } }

-

-[PcdsFixedAtBuild]

-

-#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used here to it, or move these values to the SocketPkg where the GUID is defined

-# Using a GUID defined in another .DEC file is a violation of the UEFI packaging standards.

-

- gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E

- gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F

- gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x3000001A

- gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x3000001B

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x3000001C

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x3000001D

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000001E

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000001F

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000020

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000021

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x30000027

-

- gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000001

- gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x30000004

- gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x0000000|UINT32|0x30000006

- gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0x30000008

-

- gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030

- gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031

-

- gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032

-

- # Choose the default serial debug message level when CMOS is bad; in the later BIOS phase, the setup default is applied

- # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max

- gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033

- gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 #BIT4 => SVID BUS 0, BIT3-BIT0 => VR ADDRESS

- gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002

- gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003

-

- # PCD for failsafe variable ffs in other FV rather than bb1

- # by default, FCE will insert into SECPEI, and you don't need to set these two PCD if bb1(secpei)is used

- gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034

- gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035

-

- gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4, 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30000036

-

- #

- # These need to move to MinPlatformPkg.dec

- #

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF00000A9

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF00000AA

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF00000AB

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE

-

- #IIO configuration data for socket 3 will be used for sockets 4..7

- gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF

-

- gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00000B0

- gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00000B1

-

- #If True, extend PCR7 when VT-d disabled.

- gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000045

-

-[PcdsFixedAtBuild, PcdsPatchableInModule]

- gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004

- ## Specify memory size with page number for a pre-allocated reserved memory to be used

- # by PEI in S3 phase. The default size 32K. When changing the value make sure the memory size

- # is large enough to meet PEI requirement in the S3 phase.

- # @Prompt Reserved S3 Boot ACPI Memory Size

- gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|0x90010039

- gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012

- gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013

- gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015

- gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016

- gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x90000017

- gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000018

-

-

- gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021

- gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022

- gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023

- gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90000024

-

- gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025

- gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026

- gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027

- gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000000B

- gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000D

- gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014

- gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006

-

-[PcdsDynamicEx]

-

-#

-# PAL

-#

- gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000008

-

-#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use local GUID...

- gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x00000048

-

- ## This value is used to save memory address of MRC data structure.

- gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041

- gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042

-

-#

-# IMR0 programming values

-#

- gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000

- gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001

- gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002

- gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003

- gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004

-

-#

-# IMR3 programming values

-#

- gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022

-

-#

-# Server common Hot Key binding

-#

- # EFI Scan codes

- # SCAN_F2 0x000C

- # SCAN_F6 0x0010

- # SCAN_F7 0x0011

- gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009

- gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A

-

-

- gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x0000000B

-

-#Indicate whether to perform LT Config lock

-# The PCD can be set to false when there is the debug request

-# TRUE - Force the LT config lock

-# FALSE - Allow the LT config unlock for debug

- gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x3000000e

-

-#Indicate whether LTSX enabled

-# TRUE - Intel (R) TXT feature enabled on the platform

-# FALSE - Disable Intel(R) TXT feature on the platform

- gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x3000000f

-

- #

- # SMBIOS Type 0 - BIOS Information

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B000000

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B000001

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0x5B000002

-

- #

- # SMBIOS Type 1 - System Information

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID*|0x5B010000

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*|0x5B010001

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5B010002

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID*|0x5B010003

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0x5B010004

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B010005

-

- #

- # SMBIOS Type 2 - Base Board (or Module) Information

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|VOID*|0x5B020000

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VOID*|0x5B020001

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|0x5B020002

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|VOID*|0x5B020003

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*|0x5B020004

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"TBD"|VOID*|0x5B020005

-

- #

- # SMBIOS Type 3 - System Enclosure or Chassis Information

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOID*|0x5B030000

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x5B030001

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOID*|0x5B030002

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0x5B030003

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|0x5B030004

-

- #

- # SMBIOS Type 11 - OEM Strings

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B0001

-

- #

- # SMBIOS Type 12 - System Configuration Options

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|0x5B0C0001

-

- #

- # SMBIOS Type 14 - Group Associations

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001

-

- #

- # SMBIOS Type 17 - Memory Device

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00|UINT8|0x5B110000

-

- #

- # SMBIOS Type 27 - Cooling Device

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD"|VOID*|0x5B1B0000

-

- #

- # SMBIOS Type 28 - Temperature Probe

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"TBD"|VOID*|0x5B1C0000

-

- #

- # SMBIOS Type 34 - Management Device

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"TBD"|VOID*|0x5B220000

-

- #

- # SMBIOS Type 35 - Management Device Component

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDescription|"TBD"|VOID*|0x5B230000

-

- #

- # SMBIOS Type 39 - System Power Supply

- #

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TBD"|VOID*|0x5B270000

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"TBD"|VOID*|0x5B270001

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer|"TBD"|VOID*|0x5B270002

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber|"TBD"|VOID*|0x5B270003

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumber|"TBD"|VOID*|0x5B270004

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNumber|"TBD"|VOID*|0x5B270005

- gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLevel|"TBD"|VOID*|0x5B270006

-

-[PcdsFeatureFlag]

- gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00000020

-

- ##

- ## High Speed UART

- ##

- gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x0000002C

-

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]

- ## MemoryCheck value for checking memory before boot OS.

- # To save the boot performance, the default MemoryCheck is set to 0.

- gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005

-

-

- ## following PCDs should remove if CORE accept the fix

- gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4

-

- ## Vendor ID and Device ID of device producing onboard video

- gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013

- gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014

- gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x30000009

- ## This PCD is to control which device is the potential trusted console input device.<BR><BR>

- # For example:<BR>

- # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)<BR>

- # //Header VendorId ProductId Class SubClass Protocol<BR>

- # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01,<BR>

- # //Header<BR>

- # 0x7F, 0xFF, 0x04, 0x00}<BR>

- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000A

-

- ## This PCD is to control which device is the potential trusted console output device.<BR><BR>

- # For example:<BR>

- # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)<BR>

- # //Header HID UID<BR>

- # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00,<BR>

- # //Header Func Dev<BR>

- # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02,

- # //Header<BR>

- # 0x7F, 0xFF, 0x04, 0x00}<BR>

- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C

-

-

- gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16|0x00010035

- gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16|0x00010036

- gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT16|0x0001037

- gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT16|0x00010038

- gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT16|0x00010039

- gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0x0001003A

- gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x0001003B

- gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x0001003C

-

-#

-# UBA_START

-#

-[PcdsDynamicEx]

-

-#

-#Board Definitions

-#

-#Integer for BoardID, must match the SKU number and be unique.

- gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000

-#Integer for BoardFamily, must be unique

- gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001

-# Zero terminated unicode string to ID family

- gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT "|VOID*|0x0000002

-# Zero terminated unicode string to Board Name

- gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT "|VOID*|0x00000003

-# Number of Sockets on Board.

- gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004

-

-# Number of DIMM slots per channel for each Socket

- gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005

- gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006

- gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007

- gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008

-

- gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009

-# Form factor is MemoryFormFactorDimm by default

-# MemoryFormFactorOther = 0x01

-# MemoryFormFactorUnknown = 0x02

-# MemoryFormFactorSimm = 0x03

-# MemoryFormFactorSip = 0x04

-# MemoryFormFactorChip = 0x05

-# MemoryFormFactorDip = 0x06

-# MemoryFormFactorZip = 0x07

-# MemoryFormFactorProprietaryCard = 0x08

-# MemoryFormFactorDimm = 0x09

-# MemoryFormFactorTsop = 0x0A

-# MemoryFormFactorRowOfChips = 0x0B

-# MemoryFormFactorRimm = 0x0C

-# MemoryFormFactorSodimm = 0x0D

-# MemoryFormFactorSrimm = 0x0E

-# MemoryFormFactorFbDimm = 0x0F

-# MemoryFormFactorDie = 0x10

- gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010

-

-#

-# USB

-#

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x00000010

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x00000011

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x00000012

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x00000013

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x00000014

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x00000015

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x00000016

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x00000017

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x00000018

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x00000019

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x0000001A

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x0000001B

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x0000001C

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x0000001D

-

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x00000020

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x00000021

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x00000022

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x00000023

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x00000024

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x00000025

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x00000026

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x00000027

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x00000028

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x00000029

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002A

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002B

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002C

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002D

-

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000100

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000101

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000102

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000103

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000104

-gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000105

-

-#

-# ACPI items

-#

-# Acpi Name, MUST be 8 chars long

- gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x00000030

- gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x00000031

-#

-# Misc.

-#

-

- gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039

- gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040

-

-#

-# GPIO

-#

-

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x00000050

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00000051

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00000052

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x00000053

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x00000054

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x00000055

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x00000056

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x00000057

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x00000058

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x00000059

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x0000005a

- gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000005c

-

-#

-# SATA registers

-#

-

- gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b

-

-#

-# Clock generator settings

-#

-

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b

- gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x0000006c

-

- gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT "|VOID*|0x00000201

- gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202

- gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203

-

-#

-# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't set related GPIO.

-#

- gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x00000204

- gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205

-

- gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206

- gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207

-#

-# UBA_END

-#

-

- gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022

- gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x10000023

- gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x10000021

- gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030

- gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208

-

-

-## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState

- gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC

- gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208

-

-[PcdsDynamicEx]

- gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026

- gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024

-

-[PcdsFixedAtBuild]

-#

-# Flash map related PCD.

-#

-# Note: most values here are overridden in the .fdf file

-#

-#

-# Note: FlashNv PCD naming conventions are as follows:

-#

-# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec

-# PcdFlash*Size is a hex count of the length of the FD or FV

-# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'

-#

-# Also all values will have a PCD assigned so that they can be used in the system, and

-# the FlashMap edit tool can be used to change the values here, without effecting the code.

-# This requires all code to only use the PCD tokens to recover the values.

-#

-

-

-

-# PCD's that are for the whole SPI part

-

-

-#Block size of SPI

-gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010000 |UINT32|0x50000102

-

-

-#AJW rename this to be more in keeping with the function

-gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00000 |UINT32|0x50000105

-

-

-

-# for PeiSec FD

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100000 |UINT32|0x50000221

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000000 |UINT32|0x50000222

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000000 |UINT32|0x50000260

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040000 |UINT32|0x50000261

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000000 |UINT32|0x50000211

-gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100000 |UINT32|0x50000212

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x00100000 |UINT32|0x50000233

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x00000000 |UINT32|0x50000234

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x00000000 |UINT32|0x50000235

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100000 |UINT32|0x50000241

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000000 |UINT32|0x50000242

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100000 |UINT32|0x50000251

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000000 |UINT32|0x50000252

-

-

-# for Main FD

-

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff00000 |UINT32|0x50000300

-gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x00400000 |UINT32|0x50000301

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x00200000 |UINT32|0x50000311

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF820000 |UINT32|0x50000312

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x00200000 |UINT32|0x50000341

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF820000 |UINT32|0x50000342

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF820000 |UINT32|0x50000343

-

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x00200000 |UINT32|0x50000351

-gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF820000 |UINT32|0x50000352

-

-## This PCD specifies the size of the physical device containing the BIOS, SMBIOS will use it.

-

-gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF800000 |UINT32|0x50000001

-gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x00000000 |UINT32|0x50000002

-

-[PcdsFeatureFlag.common]

-

-##

-## Those PCDs are used to control build process.

-##

-

- #

- # SV Tools

- #

- gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000

- gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E

- #

- #

- #

-

-[PcdsDynamicEx]

- ### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###

- gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x80000015 {

- <HeaderFiles>

- Guid/PlatformInfo.h

- <Packages>

- WhitleyOpenBoardPkg/PlatformPkg.dec

- }

- # Interposer A MC 0 mapped to original MC1

- # Enum values for Interposer

- # Interposer A => 1

- # Interposer B => 2

- # Interposer Unknown => 0

- gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] |1

-

-### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###

-

-[Guids]

- gStructPcdTokenSpaceGuid = {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x74, 0x29, 0x1b, 0x36, 0x16, 0xf4}}

-

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]

-gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURATION|0XFCD0000C{

- <HeaderFiles>

- Include/Guid/EmulationDfxVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION|0XFCD00010{

- <HeaderFiles>

- Include/Guid/FpgaSocketVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFCD00004{

- <HeaderFiles>

- Include/Guid/IeRcVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFCD0000B{

- <HeaderFiles>

- Include/Guid/MeRcVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG|0XFCD00002{

- <HeaderFiles>

- Include/Guid/MemBootHealthGuid.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{

- <HeaderFiles>

- Include/PchSetupVariableLbg.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{

- <HeaderFiles>

- Include/Guid/SetupVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFIGURATION|0XFCD00001{

- <HeaderFiles>

- Include/Guid/SocketCommonRcVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0XFCD00006{

- <HeaderFiles>

- Include/Guid/SocketIioVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURATION|0XFCD0000D{

- <HeaderFiles>

- Include/Guid/SocketMemoryVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGURATION|0XFCD00008{

- <HeaderFiles>

- Include/Guid/SocketMpLinkVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMANAGEMENT_CONFIGURATION|0XFCD00005{

- <HeaderFiles>

- Include/Guid/SocketPowermanagementVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSORCORE_CONFIGURATION|0XFCD00003{

- <HeaderFiles>

- Include/Guid/SocketProcessorCoreVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD00009{

- <HeaderFiles>

- Include/Guid/SetupVariable.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFCD0000A{

- <HeaderFiles>

- Include/Tcg2ConfigNvData.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- SecurityPkg/SecurityPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

-}

-gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{

- <HeaderFiles>

- Include/Tcg2ConfigNvData.h

- <Packages>

- MdePkg/MdePkg.dec

- MdeModulePkg/MdeModulePkg.dec

- SecurityPkg/SecurityPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

-}

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]

- gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209

- gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A

-

-[LibraryClasses]

- ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLib.inf

+## @file
+# Platform Package
+# Cross Platform Modules for Tiano
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PlatformPkg
+ PACKAGE_GUID = 9A29FD32-8C72-4b25-A7C4-767F7A2838EB
+ PACKAGE_VERSION = 0.91
+
+[Includes]
+ Include
+ Include/Protocol
+
+#TODO: Move these generated temp files into include.
+ Uba/BoardInit/Dxe
+
+[Guids]
+ gBiosInfoGuid = { 0x1b453c67, 0xcb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } }
+ gClvBootTimeTestExecution = { 0x3ff7d152, 0xef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } }
+ gUbaCurrentConfigHobGuid = { 0xe4b2025b, 0xc7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } }
+
+ gCommonSystemConfigurationGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } }
+ gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }
+ gEfiSetupVariableDefaultGuid = { 0x8d247131, 0x385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } }
+ gEfiGlobalVariableControlGuid = { 0x99a96812, 0x4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } }
+ gMainPkgListGuid = { 0x6205c3a4, 0x1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } }
+ gAdvancedPkgListGuid = { 0xc09c81cb, 0x31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } }
+ gTpmPkgListGuid = { 0x7da45aa9, 0x6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } }
+ gSecurityPkgListGuid = { 0x3a885aae, 0x3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } }
+ gBootOptionsPkgListGuid = { 0x62197ef0, 0x7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } }
+ gEfiOcDataGuid = { 0x4af92599, 0x8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } }
+ gEfiDprRegsProgrammedGuid = { 0x4b844201, 0x6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } }
+ gPlatformModuleTokenSpaceGuid = { 0x69d13bf0, 0xaf91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } }
+ gCpPlatFlashTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }
+ gPchSetupVariableGuid = { 0x4570b7f1, 0xade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } }
+
+#
+# UBA_START
+#
+ #OEM SKU
+ gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } }
+ gPlatformKtiEparamUpdateDataGuid = { 0x7bc065cf, 0xafe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } }
+ gSmbiosTablesTokenSpaceGuid = { 0x5e80ad48, 0xf240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } }
+ gPlatformGpioInitDataGuid = { 0x9282563e, 0xae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } }
+#
+# UBA_END
+#
+ gReserveMemFlagVariableGuid = { 0xb87aa73f, 0xdcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } }
+ gEfiOpaSocketMapHobGuid = { 0x829d41d2, 0x6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } }
+ gEfiPlatformTxtPolicyDataGuid = { 0xa353290b, 0x867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } }
+ gEfiSmmPeiSmramMemoryReserveGuid = { 0x6dadf1d1, 0xd4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } }
+ gSystemBoardInfoConfigDataGuid = { 0x68B046F7, 0x15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } }
+
+ # Fce multi mode support
+ gPlatformVariableHobGuid = { 0x71e6d4bc, 0x4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } }
+ gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } }
+
+ gCpPlatIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }
+ gEfiIpmiFormatFruGuid = { 0x3531fdc6, 0xeae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } }
+ gServerCommonIpmiTokenSpaceGuid = { 0xd1112ebf, 0xd82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } }
+
+ gServerMgmtPkgListGuid = { 0x35dcfcd1, 0xc14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } }
+
+
+ ## Include/Guid/CpPlatPkgTokenSpace.h
+ gCpPlatTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } }
+ gEfiSetupEnterGuid = { 0x71202EEE, 0x5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } }
+ gEfiSetupExitGuid = { 0xD6E335EC, 0x0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }}
+
+ gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } }
+
+[Ppis]
+#
+# UBA_START
+#
+ gEfiPeiPlatformTypeWolfPassPpiGuid = { 0xd2a92001, 0x22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } }
+ gEfiPeiPlatformTypeNeonCityEPRPPpiGuid = { 0xa2e5609e, 0x8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } }
+ gEfiPeiPlatformTypeTennesseePassPpiGuid = { 0xf7b87a79, 0xa640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } }
+ gEfiPeiPlatformTypeNeonCityEPECBPpiGuid = { 0x21877e2f, 0xf86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } }
+ gEfiPeiPlatformTypeOpalCitySTHIPpiGuid = { 0xa07b3bdf, 0xb78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } }
+ gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid = { 0x3c234470, 0x69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } }
+ gEfiPeiPlatformTypeCrescentCityPpiGuid = { 0x4ad920ef, 0x4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } }
+ gEfiPeiPlatformTypeHedtEVPpiGuid = { 0x41781f4f, 0xa3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } }
+ gEfiPeiPlatformTypeHedtCRBPpiGuid = { 0x9bb6e29a, 0x2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } }
+ gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid = { 0xaf2417f4, 0x7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid = { 0xf70a4116, 0xfdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid = { 0x0c04b0ff, 0x227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid = { 0x94c0203b, 0x54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } }
+ gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid = { 0x4284a11c, 0x18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } }
+ gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid = { 0x4f51c243, 0x7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } }
+ gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid = { 0x5d9516d3, 0xbc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } }
+ gEfiPeiPlatformTypeKyanitePpiGuid = { 0xb23ce2c1, 0x16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } }
+ gEfiPeiPlatformTypeNeonCityFPGAPpiGuid = { 0x48e796bd, 0x4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } }
+ gEfiPeiPlatformTypeOpalCityFPGAPpiGuid = { 0xe5434b26, 0xaedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } }
+ gEfiPeiPlatformTypeWilsonCityRPPpiGuid = { 0x0629aff2, 0x4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } }
+ gEfiPeiPlatformTypeWilsonCityModularPpiGuid = { 0x3170ea7b, 0x6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } }
+ gEfiPlatformTypeIsoscelesPeakPpiGuid = { 0xfc7b089f, 0x5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } }
+
+ gPeiIpmiTransportPpiGuid = { 0x7bf5fecc, 0xc5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } }
+
+#
+# UBA_END
+#
+
+ gBoardInitGuid = { 0xecc07551, 0xd64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } }
+ gUbaConfigDatabasePpiGuid = { 0xc1176733, 0x159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } }
+
+ gPeiSpiSoftStrapsPpiGuid = { 0x7F19E716, 0x419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } }
+ gUpdatePcdGuid = { 0xa08e4c6b, 0xff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } }
+ gPlatformVariableInitPpiGuid = { 0x9b1b911b, 0x4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } }
+ gUpdateBootModePpiGuid = { 0x927186a0, 0xa13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } }
+
+ gEfiPeiExStatusCodeHandlerPpiGuid = { 0x4e942617, 0xbbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } }
+
+
+[Protocols]
+ gEfiPlatformTypeProtocolGuid = { 0x171e9398, 0x269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } }
+ gUbaConfigDatabaseProtocolGuid = { 0xe03e0d46, 0x5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } }
+#
+# UBA_START
+#
+ gEfiPlatformTypeNeonCityEPRPProtocolGuid = { 0xc0cd2d36, 0xa81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } }
+ gEfiPlatformTypeHedtCRBProtocolGuid = { 0x2c824f87, 0x0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } }
+ gEfiPlatformTypeLightningRidgeEXRPProtocolGuid = { 0x1b4ae0f8, 0xed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } }
+ gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid = { 0x45b59855, 0x500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } }
+ gEfiPlatformTypeWilsonCityRPProtocolGuid = { 0x8430776f, 0xbd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } }
+ gEfiPlatformTypeIsoscelesPeakProtocolGuid = { 0xcff3f211, 0x5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } }
+ gEfiPlatformTypeWilsonCityModularProtocolGuid = { 0x28e862f4, 0xa4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } }
+
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }
+ gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }
+ gEfiPlatformTypeJunctionCityProtocolGuid = { 0xB1C2B1C9, 0xB606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } }
+
+#
+# UBA_END
+#
+
+ gEfiPciIovPlatformProtocolGuid = { 0xf3a4b484, 0x9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } }
+ gEfiWindowsInt10Workaround = { 0x387f555, 0x20a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } }
+ gEfiVMDDriverProtocolGuid = { 0x5a676ae9, 0xdb23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } }
+ gEfiHfiPcieGen3ProtocolGuid = { 0x7b59316e, 0xe9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } }
+ gEfiLegacyBiosProtocolGuid = { 0xdb9a1e3d, 0x45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } }
+
+ gEfiIpmiSolStatusProtocolGuid = { 0xe790848e, 0xb6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } }
+ gEfiIpmiTransportProtocolGuid = { 0x6bb945e8, 0x3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } }
+ gSmmIpmiTransportProtocolGuid = { 0x8bb070f1, 0xa8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } }
+ gEfiIpmiBootGuid = { 0x5c9b75ec, 0x8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } }
+ gEfiGenericIpmiDriverInstalledGuid = { 0x7cdad61a, 0x3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } }
+
+ gDmaRemapProtocolGuid = { 0x4e873773, 0x8391, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } }
+
+[PcdsFixedAtBuild]
+
+#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used here to it, or move these values to the SocketPkg where the GUID is defined
+# Using a GUID defined in another .DEC file is a violation of the UEFI packaging standards.
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E
+ gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x3000001A
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x3000001B
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x3000001C
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x3000001D
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000001E
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000001F
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000020
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000021
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x30000027
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000001
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x30000004
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x0000000|UINT32|0x30000006
+ gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0x30000008
+
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030
+ gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031
+
+ gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032
+
+ # Choose the default serial debug message level when CMOS is bad; in the later BIOS phase, the setup default is applied
+ # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max
+ gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033
+ gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 #BIT4 => SVID BUS 0, BIT3-BIT0 => VR ADDRESS
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003
+
+ # PCD for failsafe variable ffs in other FV rather than bb1
+ # by default, FCE will insert into SECPEI, and you don't need to set these two PCD if bb1(secpei)is used
+ gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034
+ gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035
+
+ gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4, 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30000036
+
+ #
+ # These need to move to MinPlatformPkg.dec
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF00000A9
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF00000AA
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF00000AB
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE
+
+ #IIO configuration data for socket 3 will be used for sockets 4..7
+ gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00000B0
+ gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00000B1
+
+ #If True, extend PCR7 when VT-d disabled.
+ gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000045
+
+ #If 0 BoardId detection is done using GPIO. Otherwise Board id will be forced to value set by this PCD
+ #Non zero value should match the values defined in PlatformInfoTypes.h
+ gPlatformTokenSpaceGuid.PcdBoardId|0|UINT8|0xE0000046
+
+ # BoardRevion Id value. Valid only if PcdBoardId is not equal to 0
+ gPlatformTokenSpaceGuid.PcdBoardRevId|0|UINT8|0xE0000047
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+ gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004
+ ## Specify memory size with page number for a pre-allocated reserved memory to be used
+ # by PEI in S3 phase. The default size 32K. When changing the value make sure the memory size
+ # is large enough to meet PEI requirement in the S3 phase.
+ # @Prompt Reserved S3 Boot ACPI Memory Size
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|0x90010039
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x90000017
+ gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000018
+
+
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022
+ gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023
+ gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90000024
+
+ gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
+ gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
+ gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
+ gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000000B
+ gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000D
+ gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
+ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006
+
+[PcdsDynamicEx]
+
+#
+# PAL
+#
+ gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000008
+
+#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use local GUID...
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x00000048
+
+ ## This value is used to save memory address of MRC data structure.
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041
+ gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042
+
+#
+# IMR0 programming values
+#
+ gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000
+ gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001
+ gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002
+ gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003
+ gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004
+
+#
+# IMR3 programming values
+#
+ gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022
+
+#
+# Server common Hot Key binding
+#
+ # EFI Scan codes
+ # SCAN_F2 0x000C
+ # SCAN_F6 0x0010
+ # SCAN_F7 0x0011
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A
+
+
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x0000000B
+
+#Indicate whether to perform LT Config lock
+# The PCD can be set to false when there is the debug request
+# TRUE - Force the LT config lock
+# FALSE - Allow the LT config unlock for debug
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x3000000e
+
+#Indicate whether LTSX enabled
+# TRUE - Intel (R) TXT feature enabled on the platform
+# FALSE - Disable Intel(R) TXT feature on the platform
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x3000000f
+
+ #
+ # SMBIOS Type 0 - BIOS Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B000000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B000001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0x5B000002
+
+ #
+ # SMBIOS Type 1 - System Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID*|0x5B010000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*|0x5B010001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5B010002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID*|0x5B010003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0x5B010004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B010005
+
+ #
+ # SMBIOS Type 2 - Base Board (or Module) Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|VOID*|0x5B020000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VOID*|0x5B020001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|0x5B020002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|VOID*|0x5B020003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*|0x5B020004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"TBD"|VOID*|0x5B020005
+
+ #
+ # SMBIOS Type 3 - System Enclosure or Chassis Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOID*|0x5B030000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x5B030001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOID*|0x5B030002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0x5B030003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|0x5B030004
+
+ #
+ # SMBIOS Type 11 - OEM Strings
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B0001
+
+ #
+ # SMBIOS Type 12 - System Configuration Options
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|0x5B0C0001
+
+ #
+ # SMBIOS Type 14 - Group Associations
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001
+
+ #
+ # SMBIOS Type 17 - Memory Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00|UINT8|0x5B110000
+
+ #
+ # SMBIOS Type 27 - Cooling Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD"|VOID*|0x5B1B0000
+
+ #
+ # SMBIOS Type 28 - Temperature Probe
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"TBD"|VOID*|0x5B1C0000
+
+ #
+ # SMBIOS Type 34 - Management Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"TBD"|VOID*|0x5B220000
+
+ #
+ # SMBIOS Type 35 - Management Device Component
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDescription|"TBD"|VOID*|0x5B230000
+
+ #
+ # SMBIOS Type 39 - System Power Supply
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TBD"|VOID*|0x5B270000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"TBD"|VOID*|0x5B270001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer|"TBD"|VOID*|0x5B270002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber|"TBD"|VOID*|0x5B270003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumber|"TBD"|VOID*|0x5B270004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNumber|"TBD"|VOID*|0x5B270005
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLevel|"TBD"|VOID*|0x5B270006
+
+[PcdsFeatureFlag]
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00000020
+
+ ##
+ ## High Speed UART
+ ##
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x0000002C
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+ ## MemoryCheck value for checking memory before boot OS.
+ # To save the boot performance, the default MemoryCheck is set to 0.
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005
+
+
+ ## following PCDs should remove if CORE accept the fix
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4
+
+ ## Vendor ID and Device ID of device producing onboard video
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014
+ gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x30000009
+ ## This PCD is to control which device is the potential trusted console input device.<BR><BR>
+ # For example:<BR>
+ # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)<BR>
+ # //Header VendorId ProductId Class SubClass Protocol<BR>
+ # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01,<BR>
+ # //Header<BR>
+ # 0x7F, 0xFF, 0x04, 0x00}<BR>
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000A
+
+ ## This PCD is to control which device is the potential trusted console output device.<BR><BR>
+ # For example:<BR>
+ # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)<BR>
+ # //Header HID UID<BR>
+ # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00,<BR>
+ # //Header Func Dev<BR>
+ # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02,
+ # //Header<BR>
+ # 0x7F, 0xFF, 0x04, 0x00}<BR>
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C
+
+
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16|0x00010035
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16|0x00010036
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT16|0x0001037
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT16|0x00010038
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT16|0x00010039
+ gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0x0001003A
+ gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x0001003B
+ gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x0001003C
+
+#
+# UBA_START
+#
+[PcdsDynamicEx]
+
+#
+#Board Definitions
+#
+#Integer for BoardID, must match the SKU number and be unique.
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000
+#Integer for BoardFamily, must be unique
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001
+# Zero terminated unicode string to ID family
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT "|VOID*|0x0000002
+# Zero terminated unicode string to Board Name
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT "|VOID*|0x00000003
+# Number of Sockets on Board.
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004
+
+# Number of DIMM slots per channel for each Socket
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009
+# Form factor is MemoryFormFactorDimm by default
+# MemoryFormFactorOther = 0x01
+# MemoryFormFactorUnknown = 0x02
+# MemoryFormFactorSimm = 0x03
+# MemoryFormFactorSip = 0x04
+# MemoryFormFactorChip = 0x05
+# MemoryFormFactorDip = 0x06
+# MemoryFormFactorZip = 0x07
+# MemoryFormFactorProprietaryCard = 0x08
+# MemoryFormFactorDimm = 0x09
+# MemoryFormFactorTsop = 0x0A
+# MemoryFormFactorRowOfChips = 0x0B
+# MemoryFormFactorRimm = 0x0C
+# MemoryFormFactorSodimm = 0x0D
+# MemoryFormFactorSrimm = 0x0E
+# MemoryFormFactorFbDimm = 0x0F
+# MemoryFormFactorDie = 0x10
+ gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010
+
+#
+# USB
+#
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x00000010
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x00000011
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x00000012
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x00000013
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x00000014
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x00000015
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x00000016
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x00000017
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x00000018
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x00000019
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x0000001A
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x0000001B
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x0000001C
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x0000001D
+
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x00000020
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x00000021
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x00000022
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x00000023
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x00000024
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x00000025
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x00000026
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x00000027
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x00000028
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x00000029
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002A
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002B
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002C
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002D
+
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000100
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000101
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000102
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000103
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000104
+gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000105
+
+#
+# ACPI items
+#
+# Acpi Name, MUST be 8 chars long
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x00000030
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x00000031
+#
+# Misc.
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040
+
+#
+# GPIO
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x00000050
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00000051
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00000052
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x00000053
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x00000054
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x00000055
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x00000056
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x00000057
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x00000058
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x00000059
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x0000005a
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000005c
+
+#
+# SATA registers
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b
+
+#
+# Clock generator settings
+#
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x0000006c
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT "|VOID*|0x00000201
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203
+
+#
+# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't set related GPIO.
+#
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x00000204
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207
+#
+# UBA_END
+#
+
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x10000023
+ gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x10000021
+ gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030
+ gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208
+
+
+## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState
+ gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC
+ gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208
+
+[PcdsDynamicEx]
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024
+
+[PcdsFixedAtBuild]
+#
+# Flash map related PCD.
+#
+# Note: most values here are overridden in the .fdf file
+#
+#
+# Note: FlashNv PCD naming conventions are as follows:
+#
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+#
+
+
+
+# PCD's that are for the whole SPI part
+
+
+#Block size of SPI
+gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010000 |UINT32|0x50000102
+
+
+#AJW rename this to be more in keeping with the function
+gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00000 |UINT32|0x50000105
+
+
+
+# for PeiSec FD
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100000 |UINT32|0x50000221
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000000 |UINT32|0x50000222
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000000 |UINT32|0x50000260
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040000 |UINT32|0x50000261
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000000 |UINT32|0x50000211
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100000 |UINT32|0x50000212
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x00100000 |UINT32|0x50000233
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x00000000 |UINT32|0x50000234
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x00000000 |UINT32|0x50000235
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100000 |UINT32|0x50000241
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000000 |UINT32|0x50000242
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100000 |UINT32|0x50000251
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000000 |UINT32|0x50000252
+
+
+# for Main FD
+
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff00000 |UINT32|0x50000300
+gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x00400000 |UINT32|0x50000301
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x00200000 |UINT32|0x50000311
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF820000 |UINT32|0x50000312
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x00200000 |UINT32|0x50000341
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF820000 |UINT32|0x50000342
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF820000 |UINT32|0x50000343
+
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x00200000 |UINT32|0x50000351
+gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF820000 |UINT32|0x50000352
+
+## This PCD specifies the size of the physical device containing the BIOS, SMBIOS will use it.
+
+gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF800000 |UINT32|0x50000001
+gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x00000000 |UINT32|0x50000002
+
+[PcdsFeatureFlag.common]
+
+##
+## Those PCDs are used to control build process.
+##
+
+ #
+ # SV Tools
+ #
+ gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000
+ gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E
+ #
+ #
+ #
+
+[PcdsDynamicEx]
+ ### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x80000015 {
+ <HeaderFiles>
+ Guid/PlatformInfo.h
+ <Packages>
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ }
+ # Interposer A MC 0 mapped to original MC1
+ # Enum values for Interposer
+ # Interposer A => 1
+ # Interposer B => 2
+ # Interposer Unknown => 0
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] |1
+
+### Sample implementation...No real data. Use this PCD to override a platform with Interposer ###
+
+[Guids]
+ gStructPcdTokenSpaceGuid = {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x74, 0x29, 0x1b, 0x36, 0x16, 0xf4}}
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURATION|0XFCD0000C{
+ <HeaderFiles>
+ Include/Guid/EmulationDfxVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION|0XFCD00010{
+ <HeaderFiles>
+ Include/Guid/FpgaSocketVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFCD00004{
+ <HeaderFiles>
+ Include/Guid/IeRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFCD0000B{
+ <HeaderFiles>
+ Include/Guid/MeRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG|0XFCD00002{
+ <HeaderFiles>
+ Include/Guid/MemBootHealthGuid.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{
+ <HeaderFiles>
+ Include/PchSetupVariableLbg.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{
+ <HeaderFiles>
+ Include/Guid/SetupVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFIGURATION|0XFCD00001{
+ <HeaderFiles>
+ Include/Guid/SocketCommonRcVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0XFCD00006{
+ <HeaderFiles>
+ Include/Guid/SocketIioVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURATION|0XFCD0000D{
+ <HeaderFiles>
+ Include/Guid/SocketMemoryVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGURATION|0XFCD00008{
+ <HeaderFiles>
+ Include/Guid/SocketMpLinkVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMANAGEMENT_CONFIGURATION|0XFCD00005{
+ <HeaderFiles>
+ Include/Guid/SocketPowermanagementVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSORCORE_CONFIGURATION|0XFCD00003{
+ <HeaderFiles>
+ Include/Guid/SocketProcessorCoreVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD00009{
+ <HeaderFiles>
+ Include/Guid/SetupVariable.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFCD0000A{
+ <HeaderFiles>
+ Include/Tcg2ConfigNvData.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{
+ <HeaderFiles>
+ Include/Tcg2ConfigNvData.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+}
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
+ gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209
+ gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A
+
+[LibraryClasses]
+ ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLib.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index ae3646df7a..5507a044a4 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -1,954 +1,970 @@
-## @file

-# X64 Platform with 64-bit DXE.

-#

-# @copyright

-# Copyright 2008 - 2021 Intel Corporation. <BR>

-#

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-##

-

-################################################################################

-#

-# Defines Section - statements that will be processed to create a Makefile.

-#

-################################################################################

-[Defines]

- PLATFORM_NAME = $(RP_PKG)

- PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61

- PLATFORM_VERSION = 0.1

- DSC_SPECIFICATION = 0x00010005

- OUTPUT_DIRECTORY = Build/$(RP_PKG)

- SUPPORTED_ARCHITECTURES = IA32|X64

- BUILD_TARGETS = DEBUG|RELEASE

- SKUID_IDENTIFIER = DEFAULT

- VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08

- FLASH_DEFINITION = $(RP_PKG)/PlatformPkg.fdf

- PLATFORM_SI_PACKAGE = ClientOneSiliconPkg

- DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg

- PEI_ARCH = IA32

- DXE_ARCH = X64

-

-!if $(CPUTARGET) == "CPX"

- DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg

- DEFINE IIO_INSTANCE = Skx

-!elseif $(CPUTARGET) == "ICX"

- DEFINE FSP_BIN_PKG = WhitleyFspBinPkg

- DEFINE IIO_INSTANCE = Icx

-!else

- DEFINE IIO_INSTANCE = UnknownCpu

-!endif

-

- #

- # Platform On/Off features are defined here

- #

- !include $(RP_PKG)/PlatformPkgConfig.dsc

-

- #

- # MRC common configuration options defined here

- #

- !include $(SILICON_PKG)/MrcCommonConfig.dsc

-

-[Packages]

- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec

-

- !include $(FSP_BIN_PKG)/DynamicExPcd.dsc

- !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc

- !include $(RP_PKG)/DynamicExPcd.dsc

-

- !include $(RP_PKG)/Uba/UbaCommon.dsc

- !include $(RP_PKG)/Uba/UbaRpBoards.dsc

-

- !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc

-

-################################################################################

-#

-# SKU Identification section - list of all SKU IDs supported by this

-# Platform.

-#

-################################################################################

-[SkuIds]

- 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.

-

-[DefaultStores]

- 0|STANDARD

- 1|MANUFACTURING

-

-

-################################################################################

-#

-# Pcd Section - list of all EDK II PCD Entries defined by this Platform

-#

-################################################################################

-[PcdsFeatureFlag]

- #

- # MinPlatform control flags

- #

- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE

- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE

- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE

- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE

- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE

- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE

- gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE

-

- # don't degrade 64bit MMIO space to 32-bit

- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE

-

- # Server doesn't support capsule update on Reset.

- gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE

- gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE

- gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE

-

- gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE

-

-!if ($(CPUTARGET) == "ICX")

- gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE

-!endif # $(CPUTARGET) == "ICX"

-

- gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE

- gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE

-

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE

- gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE

-

- ## Uncomment for better boot performance

-# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE

-# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE

-

- gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE

-

- ## This PCD specified whether ACPI SDT protocol is installed.

- gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

-

- ## This PCD specifies whether FPGA routine will be active

- gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE

-

-!if $(CPU_SKX_ONLY_SUPPORT) == TRUE

- gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE

- gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE

-!endif

-

- ## This PCD specifies whether or not to enable the High Speed UART

- gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE

-

-[PcdsFixedAtBuild]

- gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2

-

- ## MinPlatform Boot Stage Selector

- # Stage 1 - enable debug (system deadloop after debug init)

- # Stage 2 - mem init (system deadloop after mem init)

- # Stage 3 - boot to shell only

- # Stage 4 - boot to OS

- # Stage 5 - boot to OS with security boot enabled

- # Stage 6 - boot with advanced features enabled

- #

- gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6

-

- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.

- gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init

-!if $(TARGET) == "DEBUG"

- gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging

-!endif

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0

- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000

- gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0

- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0

- gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "

- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E49 # "INTEL ID"

- gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000

- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000

- gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302

- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140

-

- gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000

- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512

- gCpuPkgTokenSpaceGuid.PcdPlatformType|2

- gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000

-

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000

-

- #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize - (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))

- gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70

-

- #

- # This controls the NEM code region cached during SEC

- # It usually isn't necessary to match exactly the FV layout in the FDF file.

- # It is a performance optimization to have it match the flash region exactly

- # as then no extra reads are done to load unused flash into cache.

- #

- gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000

- gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000

-

- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000

- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000

-

- #

- # Mode | FSP_MODE | PcdFspModeSelection

- # ------------------|----------|--------------------

- # FSP Dispatch Mode | 1 | 0

- # FSP API Mode | 0 | 1

- #

-!if ($(FSP_MODE) == 0)

- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1

- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000

-!else

- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0

-!endif

- gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000

-

- #

- # These will be initialized during build

- #

-

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000

-

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000

-

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000

-

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000

- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000

- gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000

-

- ## Specifies delay value in microseconds after sending out an INIT IPI.

- # @Prompt Configure delay value after send an INIT IPI

- gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10

- ## Specifies max supported number of Logical Processors.

- # @Prompt Configure max supported number of Logical Processorss

- gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000

-

- gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2

-

- gPlatformTokenSpaceGuid.PcdUboDev|0x08

- gPlatformTokenSpaceGuid.PcdUboFunc|0x02

- gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC

-

- gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE

- gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE

-

- ## Defines the ACPI register set base address.

- # The invalid 0xFFFF is as its default value. It must be configured to the real value.

- # @Prompt ACPI Timer IO Port Address

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500

-

- ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.

- # @Prompt ACPI Hardware PCI Bus Number

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00

-

- ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.

- # The invalid 0xFF is as its default value. It must be configured to the real value.

- # @Prompt ACPI Hardware PCI Device Number

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F

-

- ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.

- # The invalid 0xFF is as its default value. It must be configured to the real value.

- # @Prompt ACPI Hardware PCI Function Number

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02

-

- ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.

- # The invalid 0xFFFF is as its default value. It must be configured to the real value.

- # @Prompt ACPI Hardware PCI Register Offset

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044

-

- ## Defines the bit mask that must be set to enable the APIC hardware register BAR.

- # @Prompt ACPI Hardware PCI Bar Enable BitMask

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80

-

- ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.

- # The invalid 0xFFFF is as its default value. It must be configured to the real value.

- # @Prompt ACPI Hardware PCI Bar Register Offset

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040

-

- ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.

- # @Prompt Offset to 32-bit Timer register in ACPI BAR

- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008

-

-!if $(CPUTARGET) == "ICX"

- #

- # ACPI PCD custom override

- #

- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49

- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013

-!endif

-

- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28

- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)

- gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07

-

- # Enable DDRT scheduler debug features for power on

- gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE

-

- # Disable Fast Warm Boot for Whitley Openboard Package

- gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE

-

-!if $(CPU_SKX_ONLY_SUPPORT) == FALSE

- gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE

- gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE

-!endif

-

- gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74

- gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75

-

- #

- # PlatformInitPreMem

- #

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100

-

- gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0

-

- !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc

-

-[PcdsFixedAtBuild.IA32]

- #

- # FSP Base address PCD will be updated in FDF basing on flash map.

- #

- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0

- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0

-

-!if ($(FSP_MODE) == 0)

- gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE

- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000

- gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0

-!endif

-

-[PcdsFixedAtBuild.X64]

- # Change PcdBootManagerMenuFile to UiApp

- ##

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }

-

- gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000

-

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE

-

- #

- # AcpiPlatform

- #

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1

- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32

- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09

- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000

- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24

-

- gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04

- gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000

- gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5

- gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000

- gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000

- gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08

-

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580

- gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0

-

- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE

-

- gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}

- gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}

- gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x1F, 0x0}

- gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01

-

-[PcdsPatchableInModule]

- #

- # These debug options are patcheable so that they can be manipulated during debug (if memory is updateable)

- #

-

- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors

- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn

-

- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000

- gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

-

-!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE

- gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000

-!endif

-

-[PcdsDynamicExDefault.IA32]

-!if ($(FSP_MODE) == 0)

- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000

-!endif

-

-

-[PcdsDynamicExHii]

- gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGenericVariableGuid|0x0|TRUE

- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout"

- gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformTokenSpaceGuid|0x0|0

- gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatTokenSpaceGuid|0x0|TRUE

- gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVariableGuid|0x0|TRUE

- gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"

- gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScratchPad"|gEfiGenericVariableGuid|0x0|FALSE

-

-[PcdsDynamicExDefault]

- gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000

- gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE

- gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE

- gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE

- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE

- gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE

- gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE

-

- gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE

- gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE

- gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE

-

- gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE

- gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0

- gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0

- gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0

-

- #Platform should change it to by code

- gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000

- gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22

-

- gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE

-

- #

- # CPU features related PCDs.

- #

- gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy

- gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle

- gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset

-

- gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE

- gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE

- gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE

- gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01

-

- ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }

- ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }

- ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }

-

- #TPM2.0#

- gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}

-

- gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0

- gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1

- gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0

-

- gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE

- gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE

-

- gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b

- gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522

-

- gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C

- gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011

- gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }

- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0

-

-[PcdsDynamicExDefault.X64]

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1

- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0

-

- #

- # Set video to 1024x768 resolution

- #

- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024

- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768

-

-[PcdsDynamicExDefault]

-

-!if $(CPUTARGET) == "CPX"

- !include $(RP_PKG)/StructurePcdCpx.dsc

-!else

- !include $(RP_PKG)/StructurePcd.dsc

-!endif

-

-################################################################################

-#

-# Library Class section - list of all Library Classes needed by this Platform.

-#

-################################################################################

-

-!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc

-!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc

-!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc

-

-[LibraryClasses]

-

- #

- # Simics source level debugging requires the non-null version of PeCoffExtraActionLib

- #

-!if $(TARGET) == "DEBUG"

- PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf

-!else

- PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf

-!endif

-

- #

- # Basic

- #

-

- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf

- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf

-

- #

- # Framework

- #

- S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf

- FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf

-

- SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf

-!if ($(FSP_MODE) == 0)

- SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf

-!else

- SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf

-!endif

-

- SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf

-

- #

- # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?

- #

- TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf

-

- MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSupportLib.inf

- ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf

- PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf

- PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf

-

- PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf

- SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf

- PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf

-

- CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf

- PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCmosAccessLib.inf

- SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf

- TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf

-

- #

- # MinPlatform uses port 80, we don't want to assume HW

- #

- PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf

-

- TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf

- Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf

- AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf

- PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf

- PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf

- VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf

-

-[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]

- FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf

- FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf

- FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf

- FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf

-

- FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf

- FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf

- FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf

-

-[LibraryClasses.Common.SEC]

- #

- # SEC phase

- #

- TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf

-

- PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf

- SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf

- VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf

-

-[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]

- #

- # ToDo: Can we remove

- #

- CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf

-

- MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf

-

-

- PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf

- PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocksLib.inf

-

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf

- TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf

-

- ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf

-

-[LibraryClasses.Common.PEIM]

- #

- # Library instance consumed by MinPlatformPkg PlatformInit modules.

- #

- ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

- SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf

-

-[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]

- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf

-

- Tcg2PhysicalPresenceLib|$(RP_PKG)/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.inf

- TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf

-

- BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf

- MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf

-

- TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf

-

- Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf

-

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf

- TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf

- BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf

- BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf

-

- CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf

-

-[LibraryClasses.Common.DXE_SMM_DRIVER]

- SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf

- TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf

- MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf

- BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf

-

-[LibraryClasses.Common.SMM_CORE]

- S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf

-

-[LibraryClasses.Common]

- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

- PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf

-

-[Components.IA32]

- UefiCpuPkg/SecCore/SecCore.inf

-

- !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc

-

- MdeModulePkg/Universal/PCD/Pei/Pcd.inf {

- <LibraryClasses>

- #

- # Beware of circular dependencies on PCD if you want to use another DebugLib instance.

- #

- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

- NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD

- NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD

- NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD

- }

- $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf

- $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf

- $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf

-

- $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf

-

- $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf

- $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {

- <LibraryClasses>

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf

- BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf

- }

- $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf

-

- $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{

- <LibraryClasses>

- SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf

- }

- $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf

- $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {

- <LibraryClasses>

- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf

- BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf

- }

-

- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf

-!if ($(FSP_MODE) == 0)

- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf

- $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf

-!endif

-

- $(RP_PKG)/BiosInfo/BiosInfo.inf

-

- WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf

- UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf

-

- UefiCpuPkg/CpuMpPei/CpuMpPei.inf

-

- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {

- <LibraryClasses>

- !if $(PERFORMANCE_ENABLE) == TRUE

- TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf

- !endif

- }

-

-[Components.X64]

- !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc

-

- $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf

-

- MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf

-

- MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf

- MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf

- MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf

-

- MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf

- UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf

-

- ShellPkg/Application/Shell/Shell.inf {

- <LibraryClasses>

- ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf

- NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf

- NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf

- HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf

- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf

- BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf

- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf

-

- <PcdsFixedAtBuild>

- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF

- gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE

- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000

- }

-

- $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf

- UefiCpuPkg/CpuDxe/CpuDxe.inf

- UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf

-

- $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf

- IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf

-

- $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf

-

- $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf

-

- $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf

-

- $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {

- <LibraryClasses>

- BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf

- }

- $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {

-!if ($(FSP_MODE) == 0)

- <BuildOptions>

- *_*_*_CC_FLAGS = -D FSP_API_MODE

-!endif

- }

-

- $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf

-

- $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf

- $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf

-

- MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf

- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

- BoardModulePkg/LegacySioDxe/LegacySioDxe.inf

- BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf

-

- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

-

- MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf

-

- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf

- MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf

- MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf

- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

-

- #

- # SiliconPkg code for Platform Integration are defined here

- #

-!if $(CPUTARGET) == "CPX"

- DEFINE CPU_CPX_SUPPORT = TRUE

-!else

- DEFINE CPU_CPX_SUPPORT = FALSE

-!endif

-[PcdsFixedAtBuild]

-!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)

- gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE

-!endif

-[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]

- ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf

-[LibraryClasses.common.DXE_RUNTIME_DRIVER]

- ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf

-

-

-###################################################################################################

-#

-# BuildOptions Section - Define the module specific tool chain flags that should be used as

-# the default flags for a module. These flags are appended to any

-# standard flags that are defined by the build process. They can be

-# applied for any modules or only those modules with the specific

-# module style (EDK or EDKII) specified in [Components] section.

-#

-###################################################################################################

-[BuildOptions.Common.EDKII]

-# Append build options for EDK and EDKII drivers (= is Append, == is Replace)

-!if $(CRB_FLAG_ENABLE) == TRUE

- DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG

-!else

- DEFINE CRB_EDKII_BUILD_OPTIONS =

-!endif

-

-!if $(DEBUG_FLAGS_ENABLE) == TRUE

- DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3

-!else

- DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3

-!endif

-

-!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE

- DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT

-!else

- DEFINE SPARING_SCRATCHPAD_OPTIONS =

-!endif

-

-!if $(SCRATCHPAD_DEBUG) == TRUE

- DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG

-!else

- DEFINE SCRATCHPAD_DEBUG_OPTION =

-!endif

-

-!if $(PCH_SERVER_BIOS_ENABLE) == TRUE

- DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1

-!else

- DEFINE PCH_BUILD_OPTION =

-!endif

-

-!if $(SERVER_BIOS_ENABLE) == TRUE

- DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1

-!else

- DEFINE SERVER_BUILD_OPTION =

-!endif

-

-DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"

-

-DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"

-

-DEFINE IE_PATH = -D IE_PATH="Ie/v1"

-

-DEFINE NVDIMM_OPTIONS =

-

-!if $(CPUTARGET) == "ICX"

- DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST

-!elseif $(CPUTARGET) == "CPX"

- DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST

-!endif

-

-DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)

-

-DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT

-

-!if $(CPU_SKX_ONLY_SUPPORT) == FALSE

- DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2

-!else

- DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3

-!endif

-

-DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1

-

-DEFINE LT_BUILD_OPTIONS = -D LT_FLAG

-

-DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1

-

-#

-# MAX_KTI_PORTS needs to be updated based on the silicon type

-#

-!if $(CPUTARGET) == "CPX"

- DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6

-!else

- DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3

-!endif

-

-DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8

-

-DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)

-

-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)

-

-DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0

-

-!if $(LINUX_GCC_BUILD) == TRUE

- DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD

-!else

- DEFINE EDK2_LINUX_BUILD_OPTIONS =

-!endif

-

-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)

-

-DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)

-

-DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE

-

-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)

-

- MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819

- GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

- *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

- *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

- *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

- *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

- *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)

-

-

-#

-# Enable source level debugging for RELEASE build

-#

-!if $(TARGET) == "RELEASE"

- DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =

- DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =

- DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =

-

- MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi

- MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7

- MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG

- GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)

- GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)

- GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)

-!endif

-

-#

-# Override ASL Compiler parameters in tools_def.template.

-#

- MSFT:*_*_*_ASL_PATH == $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/iasl.exe

- GCC:*_*_*_ASL_PATH == $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/iasl

- *_*_*_ASL_FLAGS == -vr -we -oi

-#

-# Override the VFR compile flags to speed the build time

-#

-

-*_*_*_VFR_FLAGS == -n

-

-#

-# add to the build options for DXE/SMM drivers to remove the log message:

-# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!

-#

-[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]

- MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096

-

-[BuildOptions]

- GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms

- GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs

- GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs

- MSFT:*_*_*_CC_FLAGS = /FAsc

+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = $(RP_PKG)
+ PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FLASH_DEFINITION = $(RP_PKG)/PlatformPkg.fdf
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+ #
+ # MRC common configuration options defined here
+ #
+ !include $(SILICON_PKG)/MrcCommonConfig.dsc
+
+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
+ !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
+ !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
+ !include $(RP_PKG)/DynamicExPcd.dsc
+
+ !include $(RP_PKG)/Uba/UbaCommon.dsc
+ !include $(RP_PKG)/Uba/UbaRpBoards.dsc
+
+ !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD
+ 1|MANUFACTURING
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag]
+ #
+ # MinPlatform control flags
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE
+
+ # don't degrade 64bit MMIO space to 32-bit
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
+
+ # Server doesn't support capsule update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+ gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE
+
+!if ($(CPUTARGET) == "ICX")
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE
+!endif # $(CPUTARGET) == "ICX"
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+
+ ## Uncomment for better boot performance
+# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE
+# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE
+
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ## This PCD specifies whether FPGA routine will be active
+ gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == TRUE
+ gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE
+!endif
+
+ ## This PCD specifies whether or not to enable the High Speed UART
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2
+
+ ## MinPlatform Boot Stage Selector
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init
+!if $(TARGET) == "DEBUG"
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E49 # "INTEL ID"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gCpuPkgTokenSpaceGuid.PcdPlatformType|2
+ gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize - (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70
+
+ #
+ # This controls the NEM code region cached during SEC
+ # It usually isn't necessary to match exactly the FV layout in the FDF file.
+ # It is a performance optimization to have it match the flash region exactly
+ # as then no extra reads are done to load unused flash into cache.
+ #
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
+
+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ #
+ # These will be initialized during build
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2
+
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+!if $(CPUTARGET) == "ICX"
+ #
+ # ACPI PCD custom override
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ # Enable DDRT scheduler debug features for power on
+ gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE
+
+ # Disable Fast Warm Boot for Whitley Openboard Package
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75
+
+ #
+ # PlatformInitPreMem
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0
+
+ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
+
+[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+!if ($(FSP_MODE) == 0)
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0
+!endif
+
+[PcdsFixedAtBuild.X64]
+ # Change PcdBootManagerMenuFile to UiApp
+ ##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ #
+ # AcpiPlatform
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x1F, 0x0}
+ gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01
+
+[PcdsPatchableInModule]
+ #
+ # These debug options are patcheable so that they can be manipulated during debug (if memory is updateable)
+ #
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
+
+!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000
+!endif
+
+[PcdsDynamicExDefault.IA32]
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+!endif
+
+
+[PcdsDynamicExHii]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0 # Variable: L"Timeout"
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformTokenSpaceGuid|0x0|0
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatTokenSpaceGuid|0x0|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScratchPad"|gEfiGenericVariableGuid|0x0|FALSE
+
+[PcdsDynamicExDefault]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE
+
+ gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ #Platform should change it to by code
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
+
+ #
+ # CPU features related PCDs.
+ #
+ gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01
+
+ ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+ ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+ ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+
+ #TPM2.0#
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|4
+ gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x600C0
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522
+
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+
+[PcdsDynamicExDefault.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ #
+ # Set video to 1024x768 resolution
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
+[PcdsDynamicExDefault]
+
+!if $(CPUTARGET) == "CPX"
+ !include $(RP_PKG)/StructurePcdCpx.dsc
+!else
+ !include $(RP_PKG)/StructurePcd.dsc
+!endif
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+!endif
+
+[Defines]
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ DEFINE SECURE_BOOT_ENABLE = TRUE
+!endif
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses]
+
+ #
+ # Simics source level debugging requires the non-null version of PeCoffExtraActionLib
+ #
+!if $(TARGET) == "DEBUG"
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+!endif
+
+ #
+ # Basic
+ #
+
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Framework
+ #
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
+
+ SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
+!if ($(FSP_MODE) == 0)
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf
+!else
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
+!endif
+
+ SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
+
+ #
+ # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?
+ #
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+
+ MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSupportLib.inf
+ ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf
+ PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf
+ PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf
+
+ PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf
+ PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf
+
+ CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf
+ PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCmosAccessLib.inf
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+ TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+
+ #
+ # MinPlatform uses port 80, we don't want to assume HW
+ #
+ PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
+
+ TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf
+ Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
+ AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+ PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+
+[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+ FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
+ FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+
+ FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+ FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+
+[LibraryClasses.Common.SEC]
+ #
+ # SEC phase
+ #
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+ PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ #
+ # ToDo: Can we remove
+ #
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+
+ PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocksLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+[LibraryClasses.Common.PEIM]
+ #
+ # Library instance consumed by MinPlatformPkg PlatformInit modules.
+ #
+ ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
+ ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf
+
+[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.inf
+ TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+
+ BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+
+ Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf
+ BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
+ BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf
+
+ CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+ SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf
+ MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
+ BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf
+
+[LibraryClasses.Common.SMM_CORE]
+ S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+
+[LibraryClasses.Common]
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf
+
+[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ #
+ # Beware of circular dependencies on PCD if you want to use another DebugLib instance.
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD
+ }
+ $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+ $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{
+ <LibraryClasses>
+ SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
+ }
+ $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ }
+
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+!endif
+
+ $(RP_PKG)/BiosInfo/BiosInfo.inf
+
+ WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+ !if $(PERFORMANCE_ENABLE) == TRUE
+ TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
+ !endif
+ }
+
+[Components.X64]
+ !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+
+ $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf
+
+ MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+ $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+
+ $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
+
+ $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf
+
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+ <LibraryClasses>
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf
+ }
+ $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {
+!if ($(FSP_MODE) == 0)
+ <BuildOptions>
+ *_*_*_CC_FLAGS = -D FSP_API_MODE
+!endif
+ }
+
+ $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+ $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # SiliconPkg code for Platform Integration are defined here
+ #
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+[PcdsFixedAtBuild]
+!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)
+ gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE
+!endif
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf
+
+
+###################################################################################################
+#
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process. They can be
+# applied for any modules or only those modules with the specific
+# module style (EDK or EDKII) specified in [Components] section.
+#
+###################################################################################################
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override ASL Compiler parameters in tools_def.template.
+#
+ *_*_*_ASL_FLAGS == -vr -we -oi
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
index 212103f483..498526c856 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
@@ -1,97 +1,108 @@
-/** @file

- BOARD INIT DXE Driver.

-

- @copyright

- Copyright 2014 - 2021 Intel Corporation.

-

- SPDX-License-Identifier: BSD-2-Clause-Patent

-**/

-

-#include "BoardInitDxe.h"

-#include <PlatformInfoTypes.h>

-

-/**

- The Driver Entry Point.

-

- The function is the driver Entry point.

-

- @param ImageHandle A handle for the image that is initializing this driver

- @param SystemTable A pointer to the EFI system table

-

- @retval EFI_SUCCESS: Driver initialized successfully

- @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded

- @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources

-

-**/

-EFI_STATUS

-EFIAPI

-BoardInitDxeDriverEntry (

- IN EFI_HANDLE ImageHandle,

- IN EFI_SYSTEM_TABLE *SystemTable

-)

-{

- EFI_STATUS Status = EFI_SUCCESS;

- UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;

- UINT32 PlatformType = 0;

- EFI_HANDLE Handle = NULL;

-

- Status = gBS->LocateProtocol (

- &gUbaConfigDatabaseProtocolGuid,

- NULL,

- &UbaConfigProtocol

- );

- if (EFI_ERROR(Status)) {

- return Status;

- }

-

- Status = UbaConfigProtocol->GetSku(

- UbaConfigProtocol,

- &PlatformType,

- NULL,

- NULL

- );

- ASSERT_EFI_ERROR (Status);

-

- DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=%d\n", PlatformType));

-

- //according to the platform type to install different dummy maker.

- //later, the PEIM will be loaded by the dependency.

- switch(PlatformType)

- {

- case TypeWilsonCityRP:

- Status = gBS->InstallProtocolInterface (

- &Handle,

- &gEfiPlatformTypeWilsonCityRPProtocolGuid,

- EFI_NATIVE_INTERFACE,

- NULL

- );

- ASSERT_EFI_ERROR (Status);

- break;

-

- case TypeWilsonCitySMT:

- Status = gBS->InstallProtocolInterface(

- &Handle,

- &gEfiPlatformTypeWilsonCitySMTProtocolGuid,

- EFI_NATIVE_INTERFACE,

- NULL

- );

- ASSERT_EFI_ERROR(Status);

- break;

-

- case TypeCooperCityRP:

- Status = gBS->InstallProtocolInterface (

- &Handle,

- &gEfiPlatformTypeCooperCityRPProtocolGuid,

- EFI_NATIVE_INTERFACE,

- NULL

- );

- ASSERT_EFI_ERROR (Status);

- break;

-

- default:

- // CAN'T GO TO HERE.

- ASSERT (FALSE);

- }

-

- return Status;

-}

+/** @file
+ BOARD INIT DXE Driver.
+
+ @copyright
+ Copyright 2014 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardInitDxe.h"
+#include <PlatformInfoTypes.h>
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+BoardInitDxeDriverEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+ UINT32 PlatformType = 0;
+ EFI_HANDLE Handle = NULL;
+
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->GetSku(
+ UbaConfigProtocol,
+ &PlatformType,
+ NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=%d\n", PlatformType));
+
+ //according to the platform type to install different dummy maker.
+ //later, the PEIM will be loaded by the dependency.
+ switch(PlatformType)
+ {
+ case TypeWilsonCityRP:
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiPlatformTypeWilsonCityRPProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ break;
+
+ case TypeWilsonCitySMT:
+ Status = gBS->InstallProtocolInterface(
+ &Handle,
+ &gEfiPlatformTypeWilsonCitySMTProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+ break;
+
+ case TypeCooperCityRP:
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiPlatformTypeCooperCityRPProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ break;
+
+ case TypeJunctionCity:
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiPlatformTypeJunctionCityProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ break;
+
+ default:
+ // CAN'T GO TO HERE.
+ ASSERT (FALSE);
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
index 206d95658a..01dc8a9697 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
@@ -1,70 +1,72 @@
-## @file

-# Uba init for multi-boards support in DXE phase.

-#

-# @copyright

-# Copyright 2014 - 2021 Intel Corporation.

-#

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-##

-

-[Defines]

- INF_VERSION = 0x00010005

- BASE_NAME = BoardInitDxe

- FILE_GUID = 69E6DD6D-F09E-485f-9627-EB70E9CFC82A

- MODULE_TYPE = DXE_DRIVER

- VERSION_STRING = 1.0

-

- ENTRY_POINT = BoardInitDxeDriverEntry

-

-#

-# The following information is for reference only and not required by the build tools.

-#

-# VALID_ARCHITECTURES = IA32

-#

-

-[Sources]

- BoardInitDxe.c

- BoardInitDxe.h

-

-[Packages]

- MdeModulePkg/MdeModulePkg.dec

- MdePkg/MdePkg.dec

- WhitleySiliconPkg/WhitleySiliconPkg.dec

- WhitleySiliconPkg/CpRcPkg.dec

- WhitleySiliconPkg/SiliconPkg.dec

- WhitleyOpenBoardPkg/PlatformPkg.dec

-

-

-[LibraryClasses]

- DebugLib

- IoLib

- HobLib

- UefiLib

- BaseLib

- BaseMemoryLib

- MemoryAllocationLib

- DebugLib

- UefiBootServicesTableLib

- UefiRuntimeServicesTableLib

- UefiDriverEntryPoint

- PrintLib

-

-[Guids]

-

-[Protocols]

- gUbaConfigDatabaseProtocolGuid #CONSUMER

- gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER

- gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER

- gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER

- gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER

- gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER

- gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER

- gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER

- gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER

- gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER

-

-[FixedPcd]

- gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount

-

-[Depex]

- gUbaConfigDatabaseProtocolGuid

+## @file
+# Uba init for multi-boards support in DXE phase.
+#
+# @copyright
+# Copyright 2014 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BoardInitDxe
+ FILE_GUID = 69E6DD6D-F09E-485f-9627-EB70E9CFC82A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = BoardInitDxeDriverEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ BoardInitDxe.c
+ BoardInitDxe.h
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ HobLib
+ UefiLib
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiDriverEntryPoint
+ PrintLib
+
+[Guids]
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid #CONSUMER
+ gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER
+ gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER
+ gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER
+ gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER
+ gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER
+ gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER
+ gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER
+ gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER
+ gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Depex]
+ gUbaConfigDatabaseProtocolGuid
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 2827334797..9a811fa3d0 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -1,69 +1,70 @@
-# @ build.cfg

-# This is the main/default build configuration file

-#

-# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>

-# Copyright (c) 2021, American Megatrends International LLC.<BR>

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-#

-

-

-[DEFAULT_CONFIG]

-WORKSPACE =

-WORKSPACE_FSP_BIN = FSP

-EDK_TOOLS_BIN = edk2-BaseTools-win32

-EDK_BASETOOLS = BaseTools

-WORKSPACE_DRIVERS = edk2-platforms/Drivers

-WORKSPACE_FEATURES = edk2-platforms/Features/Intel

-WORKSPACE_PLATFORM = edk2-platforms/Platform/Intel

-WORKSPACE_SILICON = edk2-platforms/Silicon/Intel

-WORKSPACE_PLATFORM_BIN =

-WORKSPACE_SILICON_BIN = edk2-non-osi/Silicon/Intel

-MIN_PACKAGE_TOOLS = edk2-platforms/Platform/Intel/MinPlatformPkg/Tools

-PACKAGES_PATH =

-EDK_SETUP_OPTION =

-BASE_TOOLS_PATH = edk2/BaseTools

-EDK_TOOLS_PATH = edk2/BaseTools

-openssl_path =

-PLATFORM_BOARD_PACKAGE =

-BIOS_SIZE_OPTION = -DBIOS_SIZE_OPTION=SIZE_70

-WORKSPACE_CORE = edk2

-EFI_SOURCE = edk2

-PATHEXT = .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC

-PROMPT = $P$G

-PLATFORM_PACKAGE = MinPlatformPkg

-BOARD =

-PrepRELEASE = DEBUG

-SILENT_MODE = FALSE

-EXT_CONFIG_CLEAR =

-CapsuleBuild = FALSE

-EXT_BUILD_FLAGS =

-CAPSULE_BUILD = 0

-TARGET = DEBUG

-TARGET_SHORT = D

-PERFORMANCE_BUILD = FALSE

-FSP_WRAPPER_BUILD = FALSE

-FSP_BIN_PKG =

-FSP_PKG_NAME =

-FSP_BINARY_BUILD = FALSE

-FSP_TEST_RELEASE = FALSE

-SECURE_BOOT_ENABLE = FALSE

-REBUILD_MODE =

-BUILD_ROM_ONLY =

-NUMBER_OF_PROCESSORS = 0

-BIOS_INFO_GUID =

-

-

-[PLATFORMS]

-# board_name = path_to_board_build_config.cfg

-BoardMtOlympus = PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg

-BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg

-AspireVn7Dash572G = KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg

-GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg

-KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg

-UpXtreme = WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg

-WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg

-CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg

-TigerlakeURvp = TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg

-CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg

-WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg

-BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg

+# @ build.cfg
+# This is the main/default build configuration file
+#
+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[DEFAULT_CONFIG]
+WORKSPACE =
+WORKSPACE_FSP_BIN = FSP
+EDK_TOOLS_BIN = edk2-BaseTools-win32
+EDK_BASETOOLS = BaseTools
+WORKSPACE_DRIVERS = edk2-platforms/Drivers
+WORKSPACE_FEATURES = edk2-platforms/Features/Intel
+WORKSPACE_PLATFORM = edk2-platforms/Platform/Intel
+WORKSPACE_SILICON = edk2-platforms/Silicon/Intel
+WORKSPACE_PLATFORM_BIN =
+WORKSPACE_SILICON_BIN = edk2-non-osi/Silicon/Intel
+MIN_PACKAGE_TOOLS = edk2-platforms/Platform/Intel/MinPlatformPkg/Tools
+PACKAGES_PATH =
+EDK_SETUP_OPTION =
+BASE_TOOLS_PATH = edk2/BaseTools
+EDK_TOOLS_PATH = edk2/BaseTools
+openssl_path =
+PLATFORM_BOARD_PACKAGE =
+BIOS_SIZE_OPTION = -DBIOS_SIZE_OPTION=SIZE_70
+WORKSPACE_CORE = edk2
+EFI_SOURCE = edk2
+PATHEXT = .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC
+PROMPT = $P$G
+PLATFORM_PACKAGE = MinPlatformPkg
+BOARD =
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS =
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = FALSE
+FSP_BIN_PKG =
+FSP_PKG_NAME =
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+REBUILD_MODE =
+BUILD_ROM_ONLY =
+NUMBER_OF_PROCESSORS = 0
+BIOS_INFO_GUID =
+
+
+[PLATFORMS]
+# board_name = path_to_board_build_config.cfg
+BoardMtOlympus = PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
+BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
+AspireVn7Dash572G = KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg
+GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
+KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
+UpXtreme = WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg
+WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
+CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
+TigerlakeURvp = TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
+CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
+WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
+BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg
+JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
index ca91434663..8a8a5c8bc0 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -1,106 +1,108 @@
-/** @file

-

- @copyright

- Copyright 2020 - 2021 Intel Corporation. <BR>

-

- SPDX-License-Identifier: BSD-2-Clause-Patent

-**/

-

-#ifndef _PLATFORM_INFO_TYPES_H_

-#define _PLATFORM_INFO_TYPES_H_

-

-//

-// DIMM Connector type

-//

-typedef enum {

- DimmConnectorPth = 0x00, // Through hole connector

- DimmConnectorSmt, // Surface mount connector

- DimmConnectorMemoryDown, // Platform soldered DRAMs

- DimmConnectorIgnore, // Ignore connector type

- DimmConnectorMax

-} EFI_MEMORY_DIMM_CONNECTOR_TYPE;

-

-//

-// Platform types - used with EFI_PLATFORM_INFO BoardId

-//

-typedef enum {

- StartOfEfiPlatformTypeEnum = 0x00,

- //For PPO

- TypeNeonCityEPRP,

- TypeWolfPass,

- TypeTennesseePass,

- TypeHedtCRB,

- TypeLightningRidgeEXRP,

- TypeLightningRidgeEX8S1N,

- TypeBarkPeak,

- TypeYubaCityRP,

- TypeRidgeport,

- //End PPO

- TypeWilsonCityRP,

- TypeWilsonCityModular,

- TypeCoyotePass,

- TypeIdaville,

- TypeMoroCityRP,

- TypeBrightonCityRp,

- TypeJacobsville,

- TypeSnrSvp,

- TypeSnrSvpSodimm,

- TypeJacobsvilleMDV,

- TypeFrostCreekRP,

- TypeVictoriaCanyonRP,

- TypeArcherCityRP,

- TypeNeonCityEPECB,

- TypeIsoscelesPeak,

- TypeWilsonPointRP,

- TypeWilsonPointModular,

- TypeBretonSound,

- TypeWilsonCityPPV,

- TypeCooperCityRP,

- TypeWilsonCitySMT,

- TypeSnrSvpSodimmB,

- TypeArcherCityModular,

- TypeArcherCityEVB,

- TypeArcherCityXPV,

- TypeBigPineKey,

- TypeExperWorkStationRP,

- EndOfEfiPlatformTypeEnum

-} EFI_PLATFORM_TYPE;

-

-#define TypePlatformUnknown 0xFF

-#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1

-#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1

-#define TypePlatformDefault TypeWilsonPointRP

-

-//

-// CPU type: Standard (no MCP), -F, etc

-//

-typedef enum {

- CPU_TYPE_STD,

- CPU_TYPE_F,

- CPU_TYPE_P,

- CPU_TYPE_MAX

-} CPU_TYPE;

-

-#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD)

-#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F)

-#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P)

-

-typedef enum {

- DaisyChainTopology = 0x00,

- InvSlotsDaisyChainTopology,

- TTopology

-} EFI_MEMORY_TOPOLOGY_TYPE;

-

-//

-// Values for SocketConfig

-//

-

-#define SOCKET_UNDEFINED 0

-#define SOCKET_4S 1

-#define SOCKET_HEDT 2

-#define SOCKET_1S 3

-#define SOCKET_1SWS 4

-#define SOCKET_8S 5

-#define SOCKET_2S 6

-

-#endif // #ifndef _PLATFORM_INFO_TYPES_H_

+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_TYPES_H_
+#define _PLATFORM_INFO_TYPES_H_
+
+//
+// DIMM Connector type
+//
+typedef enum {
+ DimmConnectorPth = 0x00, // Through hole connector
+ DimmConnectorSmt, // Surface mount connector
+ DimmConnectorMemoryDown, // Platform soldered DRAMs
+ DimmConnectorIgnore, // Ignore connector type
+ DimmConnectorMax
+} EFI_MEMORY_DIMM_CONNECTOR_TYPE;
+
+//
+// Platform types - used with EFI_PLATFORM_INFO BoardId
+//
+typedef enum {
+ StartOfEfiPlatformTypeEnum = 0x00,
+ //For PPO
+ TypeNeonCityEPRP,
+ TypeWolfPass,
+ TypeTennesseePass,
+ TypeHedtCRB,
+ TypeLightningRidgeEXRP,
+ TypeLightningRidgeEX8S1N,
+ TypeBarkPeak,
+ TypeYubaCityRP,
+ TypeRidgeport,
+ //End PPO
+ TypeWilsonCityRP,
+ TypeWilsonCityModular,
+ TypeCoyotePass,
+ TypeIdaville,
+ TypeMoroCityRP,
+ TypeBrightonCityRp,
+ TypeJacobsville,
+ TypeSnrSvp,
+ TypeSnrSvpSodimm,
+ TypeJacobsvilleMDV,
+ TypeFrostCreekRP,
+ TypeVictoriaCanyonRP,
+ TypeArcherCityRP,
+ TypeNeonCityEPECB,
+ TypeIsoscelesPeak,
+ TypeWilsonPointRP,
+ TypeWilsonPointModular,
+ TypeBretonSound,
+ TypeWilsonCityPPV,
+ TypeCooperCityRP,
+ TypeWilsonCitySMT,
+ TypeSnrSvpSodimmB,
+ TypeArcherCityModular,
+ TypeArcherCityEVB,
+ TypeArcherCityXPV,
+ TypeBigPineKey,
+ TypeExperWorkStationRP,
+ TypeJunctionCity,
+ EndOfEfiPlatformTypeEnum
+} EFI_PLATFORM_TYPE;
+
+#define TypePlatformUnknown 0xFF
+#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1
+#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1
+#define TypePlatformDefault TypeWilsonPointRP
+
+//
+// CPU type: Standard (no MCP), -F, etc
+//
+typedef enum {
+ CPU_TYPE_STD,
+ CPU_TYPE_F,
+ CPU_TYPE_P,
+ CPU_TYPE_MAX
+} CPU_TYPE;
+
+#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD)
+#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F)
+#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P)
+
+typedef enum {
+ DaisyChainTopology = 0x00,
+ InvSlotsDaisyChainTopology,
+ TTopology
+} EFI_MEMORY_TOPOLOGY_TYPE;
+
+//
+// Values for SocketConfig
+//
+
+#define SOCKET_UNDEFINED 0
+#define SOCKET_4S 1
+#define SOCKET_HEDT 2
+#define SOCKET_1S 3
+#define SOCKET_1SWS 4
+#define SOCKET_8S 5
+#define SOCKET_2S 6
+
+#endif // #ifndef _PLATFORM_INFO_TYPES_H_
--
2.25.0.windows.1


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[PATCH v4 3/3] Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib instead

Khasim Mohammed
 

The patch removes PciExpressLib implementation for N1Sdp as:

a) The PciSegmentLib implementation for N1Sdp makes MmioRead() calls
instead of PciRead() which makes the PciExpressLib redundant.

b) Since N1Sdp requires multiple segments to be supported, PciExpressLib
and PciLib cannot be used, PciSegmentLib should be used instead as it
supports multiple segments.

Change-Id: I0d1167b86e53a3781f59c4d68a3b2e61add4317e
Signed-off-by: Deepak Pandey <Deepak.Pandey@...>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 4 +-
.../PciExpressLib.c | 1589 -----------------
.../PciExpressLib.inf | 56 -
3 files changed, 1 insertion(+), 1648 deletions(-)
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf

diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index cb2049966c..8dac1bc54c 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -75,9 +75,7 @@
[LibraryClasses.common.DXE_DRIVER]
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
- PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
- PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
+ PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
deleted file mode 100644
index bb0246b4a9..0000000000
--- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
+++ /dev/null
@@ -1,1589 +0,0 @@
-/** @file
- Functions in this library instance make use of MMIO functions in IoLib to
- access memory mapped PCI configuration space.
-
- All assertions for I/O operations are handled in MMIO functions in the IoLib
- Library.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
-
- On the NeoverseN1Soc, a slave error is generated when host accesses the
- configuration space of non-available device or unimplemented function on a
- given bus. So this library introduces a workaround using IsBdfValid(),
- to return 0xFFFFFFFF for all such access.
-
- In addition to this, the hardware has two other limitations which affect
- access to the PCIe root port:
- 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
- from rest of the downstream hierarchy ECAM space.
- 2. Root port ECAM space is not capable of 8bit/16bit writes.
- The description of the workarounds included for these limitations can
- be found in the comments below.
-
- Copyright (c) 2020, ARM Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <Base.h>
-
-#include <Library/BaseLib.h>
-#include <Library/PciExpressLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <NeoverseN1Soc.h>
-
-/**
- Assert the validity of a PCI address. A valid PCI address should contain 1's
- only in the low 28 bits.
-
- @param A The address to validate.
-
-**/
-#define ASSERT_INVALID_PCI_ADDRESS(A) \
- ASSERT (((A) & ~0xfffffff) == 0)
-
-/* Root port Entry, BDF Entries Count */
-#define BDF_TABLE_ENTRY_SIZE 4
-#define BDF_TABLE_HEADER_COUNT 2
-#define BDF_TABLE_HEADER_SIZE 8
-
-/* BDF table offsets for PCIe */
-#define PCIE_BDF_TABLE_OFFSET 0
-
-#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
-#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
-#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
-#define GET_REG_NUM(Address) ((Address) & 0xFFF)
-
-/**
- BDF Table structure : (Header + BDF Entries)
- --------------------------------------------
- [Offset 0x00] ROOT PORT ADDRESS
- [Offset 0x04] BDF ENTRIES COUNT
- [Offset 0x08] BDF ENTRY 0
- [Offset 0x0C] BDF ENTRY 1
- [Offset 0x10] BDF ENTRY 2
- [Offset 0x14] BDF ENTRY 3
- [Offset 0x18] BDF ENTRY 4
- ...
- [Offset 0x--] BDF ENTRY N
- --------------------------------------------
-**/
-
-/**
- Value returned for reads on configuration space of unimplemented
- device functions.
-**/
-STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
-
-/**
- Registers a PCI device so PCI configuration registers may be accessed after
- SetVirtualAddressMap().
-
- Registers the PCI device specified by Address so all the PCI configuration
- registers associated with that PCI device may be accessed after SetVirtualAddressMap()
- is called.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @retval RETURN_SUCCESS The PCI device was registered for runtime access.
- @retval RETURN_UNSUPPORTED An attempt was made to call this function
- after ExitBootServices().
- @retval RETURN_UNSUPPORTED The resources required to access the PCI device
- at runtime could not be mapped.
- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
- complete the registration.
-
-**/
-RETURN_STATUS
-EFIAPI
-PciExpressRegisterForRuntimeAccess (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return RETURN_UNSUPPORTED;
-}
-
-/**
- Check if the requested PCI address can be safely accessed.
-
- SCP performs the initial bus scan, prepares a table of valid BDF addresses
- and shares them through non-trusted SRAM. This function validates if the
- requested PCI address belongs to a valid BDF by checking the table of valid
- entries. If not, this function will return false. This is a workaround to
- avoid bus fault that occurs when accessing unavailable PCI device due to
- hardware bug.
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return TRUE BDF can be accessed, valid.
- @return FALSE BDF should not be accessed, invalid.
-
-**/
-STATIC
-BOOLEAN
-IsBdfValid (
- IN UINTN Address
- )
-{
- UINTN BdfCount;
- UINTN BdfValue;
- UINTN BdfEntry;
- UINTN Count;
- UINTN TableBase;
- UINTN ConfigBase;
-
- ConfigBase = Address & ~0xFFF;
- TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
- BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
- BdfEntry = TableBase + BDF_TABLE_HEADER_SIZE;
-
- /* Skip the header & check remaining entry */
- for (Count = 0; Count < BdfCount; Count++, BdfEntry += BDF_TABLE_ENTRY_SIZE) {
- BdfValue = MmioRead32 (BdfEntry);
- if (BdfValue == ConfigBase) {
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/**
- Get the physical address of a configuration space register.
-
- Implement a workaround to avoid generation of slave errors from the bus. That
- is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
- address with that base address and check whether this converted address
- points to a accessible BDF. If it is not accessible, return the address
- of a dummy location so that a read from it does not cause a slave error.
-
- In addition to this, implement a workaround for accessing the root port's
- configuration space. The root port configuration space is not contiguous
- with the rest of the downstream hierarchy configuration space. So determine
- whether the specified address is for the root port and use a different base
- address for it.
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return Physical address of the configuration register that corresponds to the
- PCI configuration register specified by input parameter 'Address'.
-
-**/
-STATIC
-VOID*
-GetPciExpressAddress (
- IN UINTN Address
- )
-{
- UINT8 Bus, Device, Function;
- UINTN ConfigAddress;
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- ConfigAddress = PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Address;
- } else {
- ConfigAddress = PcdGet64 (PcdPciExpressBaseAddress) + Address;
- if (!IsBdfValid(Address)) {
- ConfigAddress = (UINTN)&mDummyConfigData;
- }
- }
-
- return (VOID *)ConfigAddress;
-}
-
-/**
- Reads an 8-bit PCI configuration register.
-
- Reads and returns the 8-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressRead8 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes an 8-bit PCI configuration register.
-
- Writes the 8-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- UINT8 Bus, Device, Function;
- UINT8 Offset;
- UINT32 Data;
-
- ASSERT_INVALID_PCI_ADDRESS (Address);
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- //
- // 8-bit and 16-bit writes to root port config space is not supported due to
- // a hardware limitation. As a workaround, perform a read-update-write
- // sequence on the whole 32-bit word of the root port config register such
- // that only the specified 8-bits of that word are updated.
- //
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- Offset = Address & 0x3;
- Address &= 0xFFFFFFFC;
- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
- Data &= ~(0xFF << (8 * Offset));
- Data |= (Value << (8 * Offset));
- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
- return Value;
- }
-
- return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of an 8-bit PCI configuration register with
- an 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressOr8 (
- IN UINTN Address,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value, followed a bitwise OR with another 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr8 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in an 8-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 8-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 8-bit register.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciExpressBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr8 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a 16-bit PCI configuration register.
-
- Reads and returns the 16-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressRead16 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes a 16-bit PCI configuration register.
-
- Writes the 16-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- UINT8 Bus, Device, Function;
- UINT8 Offset;
- UINT32 Data;
-
- ASSERT_INVALID_PCI_ADDRESS (Address);
-
- Bus = GET_BUS_NUM (Address);
- Device = GET_DEV_NUM (Address);
- Function = GET_FUNC_NUM (Address);
-
- //
- // 8-bit and 16-bit writes to root port config space is not supported due to
- // a hardware limitation. As a workaround, perform a read-update-write
- // sequence on the whole 32-bit word of the root port config register such
- // that only the specified 16-bits of that word are updated.
- //
- if ((Bus == 0) && (Device == 0) && (Function == 0)) {
- Offset = Address & 0x3;
- Address &= 0xFFFFFFFC;
- Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address));
- Data &= ~(0xFFFF << (8 * Offset));
- Data |= (Value << (8 * Offset));
- MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data);
- return Value;
- }
-
- return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of a 16-bit PCI configuration register with
- a 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressOr16 (
- IN UINTN Address,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value, followed a bitwise OR with another 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr16 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 16-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 16-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 16-bit register.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciExpressBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr16 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a 32-bit PCI configuration register.
-
- Reads and returns the 32-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The read value from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressRead32 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
-}
-
-/**
- Writes a 32-bit PCI configuration register.
-
- Writes the 32-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param Value The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
-}
-
-/**
- Performs a bitwise OR of a 32-bit PCI configuration register with
- a 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value, followed a bitwise OR with another 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioAndThenOr32 (
- (UINTN)GetPciExpressAddress (Address),
- AndData,
- OrData
- );
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 32-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address The PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldRead32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit
- );
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 32-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value The new value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldWrite32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- Value
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldOr32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- OrData
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 32-bit register.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAnd32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address The PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciExpressBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address);
- return MmioBitFieldAndThenOr32 (
- (UINTN)GetPciExpressAddress (Address),
- StartBit,
- EndBit,
- AndData,
- OrData
- );
-}
-
-/**
- Reads a range of PCI configuration registers into a caller supplied buffer.
-
- Reads the range of PCI configuration registers specified by StartAddress and
- Size into the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be read. Size is
- returned. When possible 32-bit PCI configuration read cycles are used to read
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
- and 16-bit PCI configuration read cycles may be used at the beginning and the
- end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress The starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer receiving the data read.
-
- @return Size read data from StartAddress.
-
-**/
-UINTN
-EFIAPI
-PciExpressReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return Size;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Read a byte if StartAddress is byte aligned
- //
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Read a word if StartAddress is word aligned
- //
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
-
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Read as many double words as possible
- //
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));
-
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Read the last remaining word if exist
- //
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Read the last remaining byte if exist
- //
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
- }
-
- return ReturnValue;
-}
-
-/**
- Copies the data in a caller supplied buffer to a specified range of PCI
- configuration space.
-
- Writes the range of PCI configuration registers specified by StartAddress and
- Size from the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be written. Size is
- returned. When possible 32-bit PCI configuration write cycles are used to
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
- and the end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress The starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size The size in bytes of the transfer.
- @param Buffer The pointer to a buffer containing the data to write.
-
- @return Size written to StartAddress.
-
-**/
-UINTN
-EFIAPI
-PciExpressWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return 0;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Write a byte if StartAddress is byte aligned
- //
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Write a word if StartAddress is word aligned
- //
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Write as many double words as possible
- //
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Write the last remaining word if exist
- //
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Write the last remaining byte if exist
- //
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
- }
-
- return ReturnValue;
-}
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
deleted file mode 100644
index acb6fb6219..0000000000
--- a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
+++ /dev/null
@@ -1,56 +0,0 @@
-## @file
-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
-#
-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
-# PCI Configuration cycles. Layers on top of an I/O Library instance.
-#
-# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
-#
-# This library is inherited from MdePkg/Library/BasePciExpressLib. On
-# NeoverseN1 SoC, with the unmodified version of this library, a slave error is
-# generated when host accesses the config space of a non-available device or
-# unimplemented function on a given bus. In order to resolve this for
-# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpressLib
-# library is used. The modification includes a check to determine whether the
-# incoming PCI address can be safely accessed.
-#
-# In addition to this, the NeoverseN1 SoC has two other limitations which
-# affect the access to the PCIe root port:
-# 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
-# from rest of the downstream hierarchy ECAM space.
-# 2. Root port ECAM space is not capable of 8bit/16bit writes.
-# This library includes workaround for these limitations as well.
-#
-# Copyright (c) 2020, ARM Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = BasePciExpressLib
- FILE_GUID = b378dd06-de7f-4e8c-8fb0-5126adfb34bf
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PciExpressLib
-
-[Sources]
- PciExpressLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
-
-[FixedPcd]
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
-
-[LibraryClasses]
- BaseLib
- DebugLib
- IoLib
- PcdLib
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
--
2.17.1


[PATCH v4 2/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support

Khasim Mohammed
 

This patch enables CCIX root complex support by updating
the root complex node info in PciHostBridge library.
The corresponding PCDs are updated.

Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../ConfigurationManager.c | 6 +-
.../ConfigurationManagerDxe.inf | 4 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 10 ++-
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 -
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 10 +--
9 files changed, 91 insertions(+), 27 deletions(-)

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 9c91372c11..1998c44e63 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -1047,21 +1047,21 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
{
// PCIe ECAM
{
- 0x70000000, // Base Address
+ FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address
0x0, // Segment Group Number
0x0, // Start Bus Number
17 // End Bus Number
},
// CCIX ECAM
{
- 0x68000000, // Base Address
+ FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address
0x1, // Segment Group Number
0x0, // Start Bus Number
17 // End Bus Number
},
//Remote Chip PCIe ECAM
{
- 0x40070000000, // Base Address
+ FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address
0x2, // Segment Group Number
0x0, // Start Bus Number
17 // End Bus Number
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 027a4202ff..84543e2f95 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -76,8 +76,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate

- gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
-
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base

@@ -91,6 +89,7 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
@@ -158,6 +157,7 @@
gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase

# Remote PCIe
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress
gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
index 2ab6c20dcc..ed7ea44d0d 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -34,9 +34,6 @@
gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002

- # PCIe
- gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
-
# External memory
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029

@@ -94,6 +91,7 @@
gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049

# Remote Chip PCIe
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
- gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT64|0x0000004A
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004B
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004C
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004D
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc036..cb2049966c 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -127,7 +127,6 @@
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000

# PCIe
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 9332939f63..c3a14a6c17 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -1,7 +1,7 @@
/** @file
* PCI Host Bridge Library instance for ARM Neoverse N1 platform
*
-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,6 +16,8 @@
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>

+#define ROOT_COMPLEX_NUM 2
+
GLOBAL_REMOVE_IF_UNREFERENCED
STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
@@ -28,7 +30,7 @@ typedef struct {
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
#pragma pack ()

-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
// PCIe
{
{
@@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
0
}
}
- }
+ },
+ //CCIX
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A09), // CCIX
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
};

-STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
{
0, // Segment
0, // Supports
@@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
0
},
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
- }
+ },
+ {
+ 1, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdCcixBusMin),
+ FixedPcdGet32 (PcdCcixBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdCcixIoBase),
+ FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdCcixMmio32Base),
+ FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdCcixMmio64Base),
+ FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+ },
};

/**
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 3ff1c592f2..3356c3ad35 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -1,7 +1,7 @@
## @file
# PCI Host Bridge Library instance for ARM Neoverse N1 platform.
#
-# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,15 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size

+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+
[Protocols]
gEfiCpuIo2ProtocolGuid

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 8e2154aadf..96e590cdd8 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -43,6 +43,7 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 1c4a445c5e..339fa07b32 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe ECAM Configuration Space
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciExpressBaseAddress);
- VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieExpressBaseAddress);
VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
FixedPcdGet32 (PcdPcieBusMin) + 1) *
SIZE_1MB;
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index eea2d58402..9d7e2e3130 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -46,6 +46,7 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT64|0x00000013

# CCIX
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
@@ -53,8 +54,8 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
- gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0x0000001B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x0000001C
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
@@ -68,8 +69,3 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027

gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
-
- # Remote Chip PCIe
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
- gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
--
2.17.1


[PATCH v4 1/3] Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library

Khasim Mohammed
 

The BasePCISegment Library in MdePkg doesn't allow configuring
multiple segments required for PCIe and CCIX root port
enumeration. Therefore, a custom PCI Segment library is adapted
from SynQuacerPciSegmentLib and ported for N1Sdp.

In addition to this, the hardware has few other limitations which affects
the access to the PCIe root port:
1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
from rest of the downstream hierarchy ECAM space.
2. Root port ECAM space is not capable of 8bit/16bit writes.
3. A slave error is generated when host accesses the configuration
space of non-available device or unimplemented function on a
given bus.

The description of the workarounds included for these limitations can
be found in the corresponding files of this patch.

Change-Id: I0a124b0ea2fb7a8ee652de2d66b977d848c509b4
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../Library/PciSegmentLib/PciSegmentLib.c | 1643 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
2 files changed, 1681 insertions(+)
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000000..3a3cf3008a
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1643 @@
+/** @file
+ PCI Segment Library for N1SDP SoC with multiple RCs
+
+ Having two distinct root complexes is not supported by the standard
+ set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib
+ reimplements the functionality to support multiple root ports on
+ different segment numbers.
+
+ On the NeoverseN1Soc, a slave error is generated when host accesses the
+ configuration space of non-available device or unimplemented function on a
+ given bus. So this library introduces a workaround using IsBdfValid(),
+ to return 0xFFFFFFFF for all such access.
+
+ In addition to this, the hardware has two other limitations which affect
+ access to the PCIe root port:
+ 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated
+ from rest of the downstream hierarchy ECAM space.
+ 2. Root port ECAM space is not capable of 8bit/16bit writes.
+ The description of the workarounds included for these limitations can
+ be found in the comments below.
+
+ Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PciSegmentLib.h>
+#include <NeoverseN1Soc.h>
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+#define BUS_OFFSET 20
+#define DEV_OFFSET 15
+#define FUNC_OFFSET 12
+#define REG_OFFSET 4096
+
+/**
+ Assert the validity of a PCI address. A valid PCI address should contain 1's.
+
+ @param A The address to validate.
+
+**/
+#define ASSERT_INVALID_PCI_ADDRESS(A) \
+ ASSERT (((A) & ~0xffffffff) == 0)
+
+#define EFI_PCIE_ADDRESS(bus, dev, func, reg) \
+ (UINT64) ( \
+ (((UINTN) bus) << BUS_OFFSET) | \
+ (((UINTN) dev) << DEV_OFFSET) | \
+ (((UINTN) func) << FUNC_OFFSET) | \
+ (((UINTN) (reg)) < REG_OFFSET ? \
+ ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
+
+#define GET_PCIE_BASE_ADDRESS(Address) (Address & 0xF8000000)
+
+/* Root port Entry, BDF Entries Count */
+#define BDF_TABLE_ENTRY_SIZE 4
+#define BDF_TABLE_HEADER_COUNT 2
+#define BDF_TABLE_HEADER_SIZE 8
+
+/* BDF table offsets for PCIe */
+#define PCIE_BDF_TABLE_OFFSET 0
+#define CCIX_BDF_TABLE_OFFSET (16 * 1024)
+
+#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
+#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
+#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
+#define GET_REG_NUM(Address) ((Address) & 0xFFF)
+
+CONST STATIC UINTN mDummyConfigData = 0xFFFFFFFF;
+
+/**
+ Check if the requested PCI address is a valid BDF address.
+
+ SCP performs the initial bus scan and prepares a table of valid BDF addresses
+ and shares them through non-trusted SRAM. This function validates if the PCI
+ address from any PCI request falls within the table of valid entries. If not,
+ this function will return 0xFFFFFFFF. This is a workaround to avoid bus fault
+ that happens when accessing unavailable PCI device due to RTL bug.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The base address of PCI Express.
+
+**/
+STATIC
+UINTN
+IsBdfValid (
+ IN UINTN Address
+ )
+{
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINTN BdfCount;
+ UINTN BdfValue;
+ UINTN Count;
+ UINTN TableBase;
+ UINTN PciAddress;
+
+ Bus = GET_BUS_NUM (Address);
+ Device = GET_DEV_NUM (Address);
+ Function = GET_FUNC_NUM (Address);
+
+ PciAddress = EFI_PCIE_ADDRESS (Bus, Device, Function, 0);
+
+ if (GET_PCIE_BASE_ADDRESS (Address) ==
+ FixedPcdGet64 (PcdPcieExpressBaseAddress)) {
+ TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFSET;
+ } else {
+ TableBase = NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + CCIX_BDF_TABLE_OFFSET;
+ }
+
+ BdfCount = MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE);
+
+ /* Start from the second entry */
+ for (Count = BDF_TABLE_HEADER_COUNT;
+ Count < (BdfCount + BDF_TABLE_HEADER_COUNT);
+ Count++) {
+ BdfValue = MmioRead32 (TableBase + (Count * BDF_TABLE_ENTRY_SIZE));
+ if (BdfValue == PciAddress)
+ break;
+ }
+
+ if (Count == (BdfCount + BDF_TABLE_HEADER_COUNT)) {
+ return mDummyConfigData;
+ } else {
+ return PciAddress;
+ }
+}
+
+/**
+ Get the physical address of a configuration space register.
+
+ Implement a workaround to avoid generation of slave errors from the bus. That
+ is, retrieve the PCI Express Base Address via a PCD entry, add the incomming
+ address with that base address and check whether this converted address
+ points to a accessible BDF. If it is not accessible, return the address
+ of a dummy location so that a read from it does not cause a slave error.
+
+ In addition to this, implement a workaround for accessing the root port's
+ configuration space. The root port configuration space is not contiguous
+ with the rest of the downstream hierarchy configuration space. So determine
+ whether the specified address is for the root port and use a different base
+ address for it.
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return Physical address of the configuration register that corresponds to the
+ PCI configuration register specified by input parameter 'Address'.
+
+**/
+STATIC
+VOID*
+GetPciExpressAddress (
+ IN UINTN Address
+ )
+{
+ BOOLEAN CheckRootPort;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINT16 Register;
+ UINTN ConfigAddress;
+
+ Bus = GET_BUS_NUM (Address);
+ Device = GET_DEV_NUM (Address);
+ Function = GET_FUNC_NUM (Address);
+ Register = GET_REG_NUM (Address);
+
+ CheckRootPort = (BOOLEAN) (Bus == 0) && (Device == 0) && (Function == 0);
+
+ if (GET_PCIE_BASE_ADDRESS (Address) ==
+ FixedPcdGet64 (PcdPcieExpressBaseAddress)) {
+ if (CheckRootPort == TRUE) {
+ ConfigAddress = (UINTN) (PcdGet32 (PcdPcieRootPortConfigBaseAddress) +
+ EFI_PCIE_ADDRESS (Bus, Device, Function, Register));
+ } else {
+ ConfigAddress = (UINTN) (PcdGet64 (PcdPcieExpressBaseAddress) +
+ EFI_PCIE_ADDRESS (Bus, Device, Function, Register));
+ }
+ } else {
+ if (CheckRootPort == TRUE) {
+ ConfigAddress = (UINTN) (PcdGet32 (PcdCcixRootPortConfigBaseAddress) +
+ EFI_PCIE_ADDRESS (Bus, Device, Function, Register));
+ } else {
+ ConfigAddress = (UINTN) PcdGet32 (PcdCcixExpressBaseAddress +
+ EFI_PCIE_ADDRESS (Bus, Device, Function, Register));
+ }
+ }
+
+ if (CheckRootPort == FALSE) {
+ if (IsBdfValid (Address) == mDummyConfigData) {
+ ConfigAddress = (UINTN) &mDummyConfigData;
+ }
+ }
+
+ return (VOID *)ConfigAddress;
+}
+
+/**
+ Function to return PCIe Physical Address for different RCs.
+ If address is invalid, then ASSERT().
+
+ @param Address Address passed from bus layer.
+
+ @return Return PCIe base address.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+ switch ((UINT16)(Address >> 32)) {
+ case 0:
+ return FixedPcdGet32 (PcdPcieExpressBaseAddress);
+ case 1:
+ return FixedPcdGet32 (PcdCcixExpressBaseAddress);
+ default:
+ ASSERT (FALSE);
+ }
+ return 0;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function
+ and Register.
+ @param Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Addr;
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ Addr = (UINT64)GetPciExpressAddress ((UINT32) Address + Base);
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Addr);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Addr);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Addr);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+/**
+ Internal worker function to write to a PCI configuration register.
+
+ @param Address The address that encodes the PCI Bus, Device, Function
+ and Register.
+ @param Width The width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT8 Bus, Device, Function;
+ UINT8 Offset;
+ UINT32 WData;
+ UINT64 Addr;
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ Addr = (UINTN) Address + Base;
+
+ Bus = GET_BUS_NUM (Addr);
+ Device = GET_DEV_NUM (Addr);
+ Function = GET_FUNC_NUM (Addr);
+
+ // 8-bit and 16-bit writes to root port config space is not supported due to
+ // a hardware limitation. As a workaround, perform a read-update-write
+ // sequence on the whole 32-bit word of the root port config register such
+ // that only the specified 8-bits of that word are updated.
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ if ((Bus == 0) && (Device == 0) && (Function == 0)) {
+ Offset = Addr & 0x3;
+ Addr &= 0xFFFFFFFC;
+ WData = MmioRead32 ((UINTN) GetPciExpressAddress (Addr));
+ WData &= ~(0xFF << (8 * Offset));
+ WData |= (Data << (8 * Offset));
+ MmioWrite32 ((UINTN) GetPciExpressAddress (Addr), WData);
+ return Data;
+ }
+ MmioWrite8 ((UINTN) GetPciExpressAddress (Addr), Data);
+ break;
+ case PciCfgWidthUint16:
+ if ((Bus == 0) && (Device == 0) && (Function == 0)) {
+ Offset = Addr & 0x3;
+ Addr &= 0xFFFFFFFC;
+ WData = MmioRead32 ((UINTN) GetPciExpressAddress (Addr));
+ WData &= ~(0xFFFF << (8 * Offset));
+ WData |= (Data << (8 * Offset));
+ MmioWrite32 ((UINTN) GetPciExpressAddress (Addr), WData);
+ return Data;
+ }
+ MmioWrite16 ((UINTN) GetPciExpressAddress (Addr), Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 ((UINTN) GetPciExpressAddress (Addr), Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+
+ @return The 8-bit PCI configuration register specified by the Address.
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit Value in the PCI configuration register specified by the
+ Address. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by
+ AndData, and writes the result to the 8-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized. If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with
+ an 8-bit value, followed by a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, performs a bitwise OR between the result of the AND operation
+ and the value specified by OrData, and writes the result to the 8-bit
+ PCI configuration register specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ (UINT8) ((PciSegmentRead8 (Address) & AndData)
+ | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldOr8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The Value written is returned.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by
+ AndData, performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ (UINT16) ((PciSegmentRead16 (Address) & AndData)
+ | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified
+ by OrData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldOr16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by the Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is
+ bit 0.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param AndData The value to AND with the read value from the PCI
+ configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a
+ 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified
+ by OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 32-bit PCI configuration register
+ specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with
+ a 32-bit value, followed by a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, performs a bitwise OR between the result of the AND operation
+ and the value specified by OrData, and writes the result to the 32-bit
+ PCI configuration register specified by Address.
+
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address The PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ Value));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldOr32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ OrData));
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified
+ by AndData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register
+ is returned. This function must guarantee that all PCI read and write
+ operations are serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ AndData));
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit
+ and EndBit, then ASSERT().
+
+ @param Address The PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData));
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ // Read a byte if StartAddress is byte aligned
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ // Read a word if StartAddress is word aligned
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Read as many double words as possible
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Read the last remaining word if exist
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Read the last remaining byte if exist
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ // Write a byte if StartAddress is byte aligned
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ // Write a word if StartAddress is word aligned
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Write as many double words as possible
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Write the last remaining word if exist
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Write the last remaining byte if exist
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000000..1d15f74faf
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PCI Segment Library for N1Sdp SoC with multiple RCs
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = b5ecc9c3-6b30-4f72-8a06-889b4ea8427e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+
+[FixedPcd]
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
--
2.17.1


[PATCH v4 0/3] Enable CCIX port as PCIe root host on N1SDP

Khasim Mohammed
 

The patch series removes PciExpressLib and enables CCIX port
as PCIe root on N1SDP.

V4:
- Remove PciExpressLib and use PciSegmentLib instead. More detailed explanation
is included in the patch.

V3:
- The conditional logic in GetPciExpressAddress is made simple.
- Removed few more PCD entries that were unused.
- Removed hardcoded entries.

V2:
- Removed few PCDs entries that were not used.
- Migrated to latest version edk2-platform and validated the patches.

V1:
- The PciExpressLib is updated to validate the PCIe addresses
and introducing corresponding PCD entries.
- A custom PCI Segment library is adapted from SynQuacerPciSegmentLib
and ported for N1Sdp.
- The root complex node info in PciHostBridge library is updated to
include the CCIX port information.

The changes can be seen at:
https://github.com/khasim/edk2-platforms-n1sdp/tree/n1sdp-ccix-root

Khasim Syed Mohammed (3):
Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Silicon/ARM/NeoverseN1Soc: Remove PciExpressLib use PciSegmentLib
instead

.../ConfigurationManager.c | 6 +-
.../ConfigurationManagerDxe.inf | 4 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 10 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +-
.../PciExpressLib.c | 1589 ----------------
.../PciExpressLib.inf | 56 -
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 +-
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 +-
.../Library/PciSegmentLib/PciSegmentLib.c | 1643 +++++++++++++++++
.../Library/PciSegmentLib/PciSegmentLib.inf | 38 +
.../Library/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/PlatformLibMem.c | 4 +-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 10 +-
13 files changed, 1773 insertions(+), 1675 deletions(-)
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c
delete mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf

--
2.17.1


Re: [PATCH v3 0/5] Add DynamicPlatRepoLib

Sami Mujawar
 

Pushed as 9006967c8d24..38f6d78c3b62

Regards,

Sami Mujawar


On 09/12/2021 09:32 AM, Pierre.Gondois@... wrote:
From: Pierre Gondois <Pierre.Gondois@...>

v3:
- Run uncrustify and apply the required formatting. [Pierre]
- No other change with v2. [Pierre]
v2:
- Various small fixes (change status returned, reset values when
freeing memory, ...). [Sami]

Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=3743

The DynamicPlatRepoLib is library allowing to receive and then
give Configuration Manager (CM) objects.
After being initialized, a dynamic platform repository can receive
CMObjects. The library generates a token to uniquely identify the
CMObject in the repository. The dynamic platform repository must
then be 'finalized' before receiving CMObject queries.

This library is complementary to the 'static' definition of
CMObjects (i.e. as C structs). It is particularly useful when
using a HwInfoParserLib that dynamically creates CMObjects
(from a device tree for instance).

The changes can be seen at: https://github.com/PierreARM/edk2/tree/1788_Add_Dynamic_Plarform_Repository_Lib_v3

Pierre Gondois (5):
DynamicTablesPkg: Definition for DynamicPlatRepoLib interface
DynamicTablesPkg: DynamicPlatRepo: Add TokenGenerator
DynamicTablesPkg: DynamicPlatRepo: Add TokenFixer
DynamicTablesPkg: DynamicPlatRepo: Add TokenMapper
DynamicTablesPkg: Add DynamicPlatRepo library

DynamicTablesPkg/DynamicTablesPkg.dec | 3 +
DynamicTablesPkg/DynamicTablesPkg.dsc | 1 +
.../Include/Library/DynamicPlatRepoLib.h | 114 ++++
.../DynamicPlatRepoLib/CmObjectTokenFixer.c | 165 ++++++
.../DynamicPlatRepoLib/CmObjectTokenFixer.h | 52 ++
.../DynamicPlatRepoLib/DynamicPlatRepo.c | 521 ++++++++++++++++++
.../DynamicPlatRepoInternal.h | 78 +++
.../DynamicPlatRepoLib/DynamicPlatRepoLib.inf | 33 ++
.../DynamicPlatRepoLib/TokenGenerator.c | 29 +
.../DynamicPlatRepoLib/TokenGenerator.h | 26 +
.../Common/DynamicPlatRepoLib/TokenMapper.c | 224 ++++++++
.../Common/DynamicPlatRepoLib/TokenMapper.h | 123 +++++
12 files changed, 1369 insertions(+)
create mode 100644 DynamicTablesPkg/Include/Library/DynamicPlatRepoLib.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/CmObjectTokenFixer.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/CmObjectTokenFixer.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepo.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepoInternal.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepoLib.inf
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenGenerator.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenGenerator.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenMapper.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenMapper.h

--
2.25.1
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH v3 0/5] Add DynamicPlatRepoLib

Sami Mujawar
 

Hi Pierre,

Thank you for this patch series.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 09/12/2021 09:32 AM, Pierre.Gondois@... wrote:
From: Pierre Gondois <Pierre.Gondois@...>

v3:
- Run uncrustify and apply the required formatting. [Pierre]
- No other change with v2. [Pierre]
v2:
- Various small fixes (change status returned, reset values when
freeing memory, ...). [Sami]

Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=3743

The DynamicPlatRepoLib is library allowing to receive and then
give Configuration Manager (CM) objects.
After being initialized, a dynamic platform repository can receive
CMObjects. The library generates a token to uniquely identify the
CMObject in the repository. The dynamic platform repository must
then be 'finalized' before receiving CMObject queries.

This library is complementary to the 'static' definition of
CMObjects (i.e. as C structs). It is particularly useful when
using a HwInfoParserLib that dynamically creates CMObjects
(from a device tree for instance).

The changes can be seen at: https://github.com/PierreARM/edk2/tree/1788_Add_Dynamic_Plarform_Repository_Lib_v3

Pierre Gondois (5):
DynamicTablesPkg: Definition for DynamicPlatRepoLib interface
DynamicTablesPkg: DynamicPlatRepo: Add TokenGenerator
DynamicTablesPkg: DynamicPlatRepo: Add TokenFixer
DynamicTablesPkg: DynamicPlatRepo: Add TokenMapper
DynamicTablesPkg: Add DynamicPlatRepo library

DynamicTablesPkg/DynamicTablesPkg.dec | 3 +
DynamicTablesPkg/DynamicTablesPkg.dsc | 1 +
.../Include/Library/DynamicPlatRepoLib.h | 114 ++++
.../DynamicPlatRepoLib/CmObjectTokenFixer.c | 165 ++++++
.../DynamicPlatRepoLib/CmObjectTokenFixer.h | 52 ++
.../DynamicPlatRepoLib/DynamicPlatRepo.c | 521 ++++++++++++++++++
.../DynamicPlatRepoInternal.h | 78 +++
.../DynamicPlatRepoLib/DynamicPlatRepoLib.inf | 33 ++
.../DynamicPlatRepoLib/TokenGenerator.c | 29 +
.../DynamicPlatRepoLib/TokenGenerator.h | 26 +
.../Common/DynamicPlatRepoLib/TokenMapper.c | 224 ++++++++
.../Common/DynamicPlatRepoLib/TokenMapper.h | 123 +++++
12 files changed, 1369 insertions(+)
create mode 100644 DynamicTablesPkg/Include/Library/DynamicPlatRepoLib.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/CmObjectTokenFixer.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/CmObjectTokenFixer.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepo.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepoInternal.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/DynamicPlatRepoLib.inf
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenGenerator.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenGenerator.h
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenMapper.c
create mode 100644 DynamicTablesPkg/Library/Common/DynamicPlatRepoLib/TokenMapper.h

--
2.25.1


[PATCH] MdeModulePkg/ScsiDisk: Change TPL to NOTIFY

Jeff Brasen
 

Increase TPL to TPL_NOTIFY to allow for use if caller is > TPL_CALLBACK.
This allows services like variable services that run at TPL_NOTIFY to
be hosted on ScsiDisks (i.e. UFS)

Aligns with the eMMC driver that also uses a higher TPL.
This change was made in 3b1d8241d0dac25c5e678c364fa2754ac1731060

Signed-off-by: Jeff Brasen <jbrasen@...>
---
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c | 22 ++++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c b/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c
index 98e84b4ea8..b6e5848e77 100644
--- a/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c
+++ b/MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDisk.c
@@ -514,7 +514,7 @@ ScsiDiskReset (
SCSI_DISK_DEV *ScsiDiskDevice;
EFI_STATUS Status;

- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);

ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO (This);

@@ -581,7 +581,7 @@ ScsiDiskReadBlocks (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -733,7 +733,7 @@ ScsiDiskWriteBlocks (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -898,7 +898,7 @@ ScsiDiskResetEx (
SCSI_DISK_DEV *ScsiDiskDevice;
EFI_STATUS Status;

- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);

ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO2 (This);

@@ -975,7 +975,7 @@ ScsiDiskReadBlocksEx (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO2 (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -1154,7 +1154,7 @@ ScsiDiskWriteBlocksEx (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO2 (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -1323,7 +1323,7 @@ ScsiDiskFlushBlocksEx (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_BLKIO2 (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -1717,7 +1717,7 @@ ScsiDiskEraseBlocks (
EFI_TPL OldTpl;

MediaChange = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_ERASEBLK (This);

if (!IS_DEVICE_FIXED (ScsiDiskDevice)) {
@@ -1907,7 +1907,7 @@ ScsiDiskReceiveData (
AlignedBuffer = NULL;
MediaChange = FALSE;
AlignedBufferAllocated = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_STORSEC (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -2122,7 +2122,7 @@ ScsiDiskSendData (
AlignedBuffer = NULL;
MediaChange = FALSE;
AlignedBufferAllocated = FALSE;
- OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
ScsiDiskDevice = SCSI_DISK_DEV_FROM_STORSEC (This);
Media = ScsiDiskDevice->BlkIo.Media;

@@ -2294,7 +2294,7 @@ ScsiDiskDetectMedia (

Status = gBS->CreateEvent (
EVT_TIMER,
- TPL_CALLBACK,
+ TPL_NOTIFY,
NULL,
NULL,
&TimeoutEvt
--
2.17.1


Re: [edk2-platforms PATCH] Platform/RaspberryPi: Fix miniuart base address and length

Jeremy Linton
 

Hi,

On 12/14/21 00:21, Andrei Warkentin wrote:
The Raspberry Pi support in edk2-platforms, including ACPI, is a direct ancestor of the original ms-iot tree (https://github.com/ms-iot/RPi-UEFI, by way of https://github.com/andreiw/RaspberryPiPkg).
The way the miniUART is described in ACPI came from Microsoft. Microsoft introduced DBG2/SPCR type 0x10 (https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table) and the BCM2836 _HID to describe the miniUART, and the contract is that the base address includes all those crazy registers.
To the best of my knowledge, today there isn't any other way to correctly describe the miniUART in a DBG2, SPCR or DSDT. Moreover, because there's code out there in at least two operating systems coded against these specific definitions, you don't get to change how a _HID == BCM2836 device or SPCR/DBG2 type 0x10 is described.
If you wanted to introduce an alternate mechanism to describe the miniUART - great. You'd have to pick a new _HID. And re-use one of the generic DBG2/SPCR types or cajole for a new one (I'm guessing in the ASWG but I really don't know). But you surely can't haphazardly change an existing firmware<->OS contract. Moreover, you can't deprecate the existing contract overnight as well, so you'd have to add an option to expose the miniUART using a presumably more-Linux friendly option.
I guess I wasn't clear, I wasn't suggesting we change the existing mechanism, so yes, I agree we either need another mechanism, or linux is going to have to deal with it as is. The latter is IMHO the best option (and as I mentioned I have patches to make it work), but sort of moves us away from the standard uart/etc mechanisms we want for systemready. So in that regard its not ideal.

If you do introduce a new mechanism to describe the miniUART in ACPI, I'm happy to add support for it in ESXi, paving the way for eventual deprecation of the current mechanism (assuming you get all the other OSes to play ball too...)
Still a NAK. It's not a fix because it's not broken. And it's not considered broken just because you don't like the definitions. I don't like the definitions either, but that's all we got.
Yes, I tend to agree WRT to changing the base address for the existing HID. So I wasn't disagreeing with your intent, just trying to point out a way forward without changing the base addr. Although, I'm going to continue thinking its broken :)


Thanks,


A
________________________________
From: Jeremy Linton <jeremy.linton@...>
Sent: Monday, December 13, 2021 11:39 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; Andrei Warkentin <awarkentin@...>; Ard Biesheuvel <ardb@...>; Adrien Thierry <athierry@...>; Pete Batard <pete@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>; Leif Lindholm <leif@...>
Subject: Re: [edk2-devel] [edk2-platforms PATCH] Platform/RaspberryPi: Fix miniuart base address and length
Hi,
On 12/13/21 13:17, Andrei Warkentin via groups.io wrote:
If I understand correctly, you want to describe the UART at 0x00215000 to be at 0x00215040.

This will break SPCR and DBG2 - so that's a regression for Windows, ESXi and possibly the NetBSDs.

I guess that's a NAK unless I misunderstood something.
Presumably the end goal is to get BT working, or are we trying to get
the console working too?
Either way, the historical SPCR definition is less than ideal because it
covers those AUX_IRQ/AUX_ENABLE registers which include information for
the SPI which isn't included in the "uart" definition here. So, IMHO it
is wrong, but its stuck that way unless we define another uart. Which if
all we wanted it for was BT then we could just create another device
under BCM2836 which is only the 8250 like registers. That is sorta ugly,
but not having a standard uart is ugly too. The other ugly thing is to
just use the address as is, and offset it by 0x40 in linux as part of
the clock and ACPI bindings linux patch. (i've got a patch to make it
work someone wants to bite into it. Lol).
For linux the base clock-rate is going to have to be added as a _DSD
too. Which I assume is a large part of why it has a custom SPCR id? Put
another way, is anyone using the extra AUX_ registers, and what else are
people (windows/etc) "quirking" with the SPCR id?
For linux I've not particularly felt the need to fix this because I had
BT working (although unreliably) this time last year when I was working
on the SD/SDIO drivers, and my answer at the time was that one either
gets a serial console using the pl011 or one gets BT with the pl011. But
it looks like at a minimum the linux-firmware project and the brcmfmac
firmware loader have been tweaked over the past year and getting BT
working isn't as simple as just taking the miniuart-bt line out of
config.txt as I have in my not particularly good notes from that time
period.
So, while its behaving like it did when it had bad firmware, it could be
something in the lower level firmware since attempting to roll back to
an older firmware/kernel I had on another disk didn't immediately fix it.

________________________________
From: Ard Biesheuvel <ardb@...>
Sent: Monday, December 13, 2021 9:14 AM
To: Adrien Thierry <athierry@...>; Andrei Warkentin <awarkentin@...>; Pete Batard <pete@...>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>; Ard Biesheuvel <ardb+tianocore@...>; Leif Lindholm <leif@...>
Subject: Re: [edk2-platforms PATCH] Platform/RaspberryPi: Fix miniuart base address and length

On Mon, 13 Dec 2021 at 15:54, Adrien Thierry <athierry@...> wrote:

Hi Ard, Leif, Pete

Do you have any feedback on this patch ?
No objections from me but I'd like an ack from someone else as well.





Re: [PATCH v1 1/1] ShellPkg: Fix incorrect PPTT FlagName dereference

Sami Mujawar
 

Hi Chris,

 

Thanks for fixing this issue.

 

Reviewed-by: Sami Mujawar <sami.mujawar@...>

 

Regards,

 

Sami Mujawar

 

From: Chris Jones <christopher.jones@...>
Date: Tuesday, 14 December 2021 at 12:38
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: ray.ni@... <ray.ni@...>, zhichao.gao@... <zhichao.gao@...>, rebecca@... <rebecca@...>, Sami Mujawar <Sami.Mujawar@...>, nd <nd@...>
Subject: [PATCH v1 1/1] ShellPkg: Fix incorrect PPTT FlagName dereference

Bugzilla: 3770 (https://bugzilla.tianocore.org/show_bug.cgi?id=3770)

The PPTT parser in AcpiView incorrectly dereferences a pointer to
FlagName when trying to log an error with the PPTT cache flags, which
can lead to random crashes and other errors.

Also fix some spacing in the error message to ensure the message is
printed cleanly.

Signed-off-by: Chris Jones <christopher.jones@...>
---
 ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
index 8d52bb5e4811298ddc45cdaef41150f6ee7819af..53777644580e779adab4e8047ea279e1c0de14a3 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
@@ -40,9 +40,9 @@ LogCacheFlagError (
   IncrementErrorCount ();
   Print (
     L"\nERROR: On Arm based systems, all cache properties must be"
-    L"provided in the cache type structure."
-    L"Missing '%s' flag.",
-    *FlagName
+    L" provided in the cache type structure."
+    L" Missing '%s' flag.",
+    FlagName
     );
 }
 
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


Re: [PATCH v4 00/15] Implement a FdtHwInfoParserLib

Sami Mujawar
 

Hi Pierre,

Thank you for this patch series.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 09/12/2021 09:31 AM, Pierre.Gondois@... wrote:
From: Pierre Gondois <Pierre.Gondois@...>

v4:
- Run uncrustify and apply the required formatting. [Pierre]
- No other change with v3. [Pierre]
v3:
- Populate the 64 bits of the MPIDR field of the GicC CmObj.
[Sami]
- Fix typos. [Sami]
v2:
- Handle absence of Pci legacy interrupts in Pci parser. [Pierre]
- Handle Affinity3 field in GicC parser. [Sami]
- Add pl011 compatible string in serial port parser. [Sami]
- Use 16550_with_GAS ID when 16550 is detected in serial
port parser. [Sami]
- Use ASSERT_EFI_ERROR when possible. [Sami]
- Fix typos and add comments. [Pierre]

Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=3741

The generic HwInfoParserLib provides an interface to parse hardware
information stored in certain a data type (e.g.: xml, device tree,
...) and generate objects that can be used by the DynamicTablesPkg
framework to generate another hardware description (e.g.:
SMBIOS tables, ACPI tables, ...).

This patch-set also implements a FdtHwInfoParserLib, parsing
hardware information stored in a device tree. The objects
generated by the library have been used ACPI tables.

The changes can be seen at: https://github.com/PierreARM/edk2/tree/1787_Implement_FdtHwInfoParser_v4

Pierre Gondois (15):
DynamicTablesPkg: Definition for HwInfoParser interface
DynamicTablesPkg: FdtHwInfoParser: CM Object descriptor helper
DynamicTablesPkg: FdtHwInfoParser: Add FDT utility functions
DynamicTablesPkg: FdtHwInfoParser: Add Boot Arch parser
DynamicTablesPkg: FdtHwInfoParser: Generic Timer Parser
DynamicTablesPkg: FdtHwInfoParser: Add Serial port parser
DynamicTablesPkg: FdtHwInfoParser: Add GICC parser
DynamicTablesPkg: FdtHwInfoParser: Add GICD parser
DynamicTablesPkg: FdtHwInfoParser: Add MSI Frame parser
DynamicTablesPkg: FdtHwInfoParser: Add ITS parser
DynamicTablesPkg: FdtHwInfoParser: Add GICR parser
DynamicTablesPkg: FdtHwInfoParser: Add GIC dispatcher
DynamicTablesPkg: FdtHwInfoParser: Add PCI config parser
DynamicTablesPkg: Add FdtHwInfoParser library
DynamicTablesPkg: Handle 16550_WITH_GAS id

DynamicTablesPkg/DynamicTablesPkg.dec | 3 +
DynamicTablesPkg/DynamicTablesPkg.dsc | 3 +-
.../Include/Library/HwInfoParserLib.h | 99 ++
.../SsdtSerialPortFixupLib.c | 5 +-
.../BootArch/ArmBootArchParser.c | 159 +++
.../BootArch/ArmBootArchParser.h | 45 +
.../FdtHwInfoParserLib/CmObjectDescUtility.c | 306 ++++++
.../FdtHwInfoParserLib/CmObjectDescUtility.h | 131 +++
.../FdtHwInfoParserLib/FdtHwInfoParser.c | 192 ++++
.../FdtHwInfoParserLib/FdtHwInfoParser.h | 63 ++
.../FdtHwInfoParserInclude.h | 17 +
.../FdtHwInfoParserLib/FdtHwInfoParserLib.inf | 56 ++
.../Library/FdtHwInfoParserLib/FdtUtility.c | 923 ++++++++++++++++++
.../Library/FdtHwInfoParserLib/FdtUtility.h | 458 +++++++++
.../GenericTimer/ArmGenericTimerParser.c | 258 +++++
.../GenericTimer/ArmGenericTimerParser.h | 66 ++
.../FdtHwInfoParserLib/Gic/ArmGicCParser.c | 777 +++++++++++++++
.../FdtHwInfoParserLib/Gic/ArmGicCParser.h | 67 ++
.../FdtHwInfoParserLib/Gic/ArmGicDParser.c | 171 ++++
.../FdtHwInfoParserLib/Gic/ArmGicDParser.h | 50 +
.../FdtHwInfoParserLib/Gic/ArmGicDispatcher.c | 218 +++++
.../FdtHwInfoParserLib/Gic/ArmGicDispatcher.h | 72 ++
.../FdtHwInfoParserLib/Gic/ArmGicItsParser.c | 218 +++++
.../FdtHwInfoParserLib/Gic/ArmGicItsParser.h | 48 +
.../Gic/ArmGicMsiFrameParser.c | 217 ++++
.../Gic/ArmGicMsiFrameParser.h | 50 +
.../FdtHwInfoParserLib/Gic/ArmGicRParser.c | 238 +++++
.../FdtHwInfoParserLib/Gic/ArmGicRParser.h | 47 +
.../Pci/ArmPciConfigSpaceParser.c | 813 +++++++++++++++
.../Pci/ArmPciConfigSpaceParser.h | 143 +++
.../Serial/ArmSerialPortParser.c | 633 ++++++++++++
.../Serial/ArmSerialPortParser.h | 47 +
32 files changed, 6591 insertions(+), 2 deletions(-)
create mode 100644 DynamicTablesPkg/Include/Library/HwInfoParserLib.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/BootArch/ArmBootArchParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/BootArch/ArmBootArchParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/CmObjectDescUtility.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/CmObjectDescUtility.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParserInclude.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtHwInfoParserLib.inf
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtUtility.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/FdtUtility.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/GenericTimer/ArmGenericTimerParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/GenericTimer/ArmGenericTimerParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicCParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicDParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicDParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicDispatcher.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicDispatcher.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicItsParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicItsParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicMsiFrameParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicMsiFrameParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicRParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Gic/ArmGicRParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser.h
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Serial/ArmSerialPortParser.c
create mode 100644 DynamicTablesPkg/Library/FdtHwInfoParserLib/Serial/ArmSerialPortParser.h

--
2.25.1


[edk2-wiki][PATCH v1 1/1] Add code formatting to development process instructions

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@...>

Adds a step to the development process instructions to account for
code formatting since it is now a required part of the contribution
process.

Cc: Andrew Fish <afish@...>
Cc: Leif Lindholm <leif@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Signed-off-by: Michael Kubacki <michael.kubacki@...>
---

Notes:
Rendered diff:
https://github.com/makubacki/tianocore.github.io/commit/42ca5959541393070cc9be380edcea6f341427a0?short_path=17579ba#diff-17579ba0854da983120baa5c2060294e6701dac24ecf1c75c9d94d08b869b02b

EDK-II-Development-Process.md | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/EDK-II-Development-Process.md b/EDK-II-Development-Process.md
index 4fd202c40c63..6e2c00fccff9 100644
--- a/EDK-II-Development-Process.md
+++ b/EDK-II-Development-Process.md
@@ -59,7 +59,20 @@ The developer process for the EDK II project

`$ git rebase origin/master`

-9. Create patch (serial) to the [[edk2-devel]] mailing list
+9. Run the automated code formatting tool (Uncrustify) against your changes
+
+ - [EDK-II-Code-Formatting](EDK-II-Code-Formatting "wikilink")
+
+ - The changes must pass local CI which includes a code formatting check
+ in order to be merged into the code base.
+
+ - It is strongly recommended that you format the code after each commit.
+ The code can then be easily amended with the formatted output. Some
+ developers might also prefer to format frequently while writing the
+ code using the plugin instructions described in the code formatting
+ wiki page.
+
+10. Create patch (serial) to the [[edk2-devel]] mailing list

- Clean out any old patches: `$ rm *.patch`

@@ -73,7 +86,7 @@ The developer process for the EDK II project

- `$ git send-email *.patch`

-10. Modify local commits based on the review feedbacks and repeat steps
+11. Modify local commits based on the review feedbacks and repeat steps
3 to 9

- For the latest commit, you can use `$ git commit --amend`
--
2.28.0.windows.1


Re: [PATCH v1] SecurityPkg: Improve initialization of default key variables.

Sunny Wang
 

Looks good to me.
Reviewed-by: Sunny Wang <sunny.wang@...>

Hi Patrick,
This patch is to address your comment below. Could you give this patch a try on your side?
https://edk2.groups.io/g/devel/message/79766?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2CSecurityPkg%3A+Create+library+for+enrolling+Secure+Boot+variables.%2C20%2C2%2C0%2C84608356

Best Regards,
Sunny

-----Original Message-----
From: Grzegorz Bernacki <gjb@...>
Sent: 06 October 2021 13:25
To: devel@edk2.groups.io
Cc: jiewen.yao@...; jian.j.wang@...; Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; Sunny Wang <Sunny.Wang@...>; mw@...; upstream@...; Grzegorz Bernacki <gjb@...>
Subject: [PATCH v1] SecurityPkg: Improve initialization of default key variables.

This commit allows to use data in EFI_VARIABLE_AUTHENTICATION_2
structure format to initialize default secure boot variables.
It allows to use revocation list published by UEFI.

Signed-off-by: Grzegorz Bernacki <gjb@...>
---
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c | 90 ++++++++++++--------
1 file changed, 56 insertions(+), 34 deletions(-)

diff --git a/SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c b/SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c
index ff65184713..1f8869b1d2 100644
--- a/SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c
+++ b/SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c
@@ -73,20 +73,19 @@ CreateSigList (

/** Adds new signature list to signature database.

- @param[in] SigLists A pointer to signature database.
- @param[in] SigListAppend A signature list to be added.
- @param[out] *SigListOut Created signature database.
+ @param[in,out] SigLists A pointer to signature database.
+ @param[in] SigListAppend A signature list to be added.
@param[in, out] SigListsSize A size of created signature database.

@retval EFI_SUCCESS Signature List was added successfully.
@retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+ @retval EFI_INVALID_PARAMETER Invalid parameters.
**/
STATIC
EFI_STATUS
ConcatenateSigList (
- IN EFI_SIGNATURE_LIST *SigLists,
+ IN EFI_SIGNATURE_LIST **SigLists,
IN EFI_SIGNATURE_LIST *SigListAppend,
- OUT EFI_SIGNATURE_LIST **SigListOut,
IN OUT UINTN *SigListsSize
)
{
@@ -94,6 +93,10 @@ ConcatenateSigList (
UINT8 *Offset;
UINTN NewSigListsSize;

+ if ((SigLists == NULL) || (SigListsSize == NULL) || (SigListAppend == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
NewSigListsSize = *SigListsSize + SigListAppend->SignatureListSize;

TmpSigList = (EFI_SIGNATURE_LIST *) AllocateZeroPool (NewSigListsSize);
@@ -101,14 +104,17 @@ ConcatenateSigList (
return EFI_OUT_OF_RESOURCES;
}

- CopyMem (TmpSigList, SigLists, *SigListsSize);
+ if (*SigLists != NULL) {
+ CopyMem (TmpSigList, *SigLists, *SigListsSize);
+ FreePool(*SigLists);
+ }

Offset = (UINT8 *)TmpSigList;
Offset += *SigListsSize;
CopyMem ((VOID *)Offset, SigListAppend, SigListAppend->SignatureListSize);

*SigListsSize = NewSigListsSize;
- *SigListOut = TmpSigList;
+ *SigLists = TmpSigList;
return EFI_SUCCESS;
}

@@ -133,14 +139,15 @@ SecureBootFetchData (
OUT EFI_SIGNATURE_LIST **SigListOut
)
{
+ EFI_VARIABLE_AUTHENTICATION_2 *Auth2;
EFI_SIGNATURE_LIST *EfiSig;
EFI_SIGNATURE_LIST *TmpEfiSig;
- EFI_SIGNATURE_LIST *TmpEfiSig2;
EFI_STATUS Status;
VOID *Buffer;
VOID *RsaPubKey;
UINTN Size;
UINTN KeyIndex;
+ UINTN SigListOffset;


KeyIndex = 0;
@@ -154,42 +161,57 @@ SecureBootFetchData (
&Buffer,
&Size
);
+ if (Status == EFI_NOT_FOUND && KeyIndex > 0) {
+ break;
+ } else if (EFI_ERROR(Status)) {
+ if (EfiSig != NULL) {
+ FreePool(EfiSig);
+ }
+ return EFI_INVALID_PARAMETER;
+ }

- if (Status == EFI_SUCCESS) {
- RsaPubKey = NULL;
- if (RsaGetPublicKeyFromX509 (Buffer, Size, &RsaPubKey) == FALSE) {
- DEBUG ((DEBUG_ERROR, "%a: Invalid key format: %d\n", __FUNCTION__, KeyIndex));
+ RsaPubKey = NULL;
+ Auth2 = (EFI_VARIABLE_AUTHENTICATION_2 *)Buffer;
+ if ((Auth2->AuthInfo.Hdr.wCertificateType == WIN_CERT_TYPE_EFI_GUID) &&
+ (CompareGuid (&gEfiCertPkcs7Guid, &Auth2->AuthInfo.CertType) == TRUE)) {
+
+ SigListOffset = Auth2->AuthInfo.Hdr.dwLength - (UINT32) (OFFSET_OF (WIN_CERTIFICATE_UEFI_GUID, CertData));
+ TmpEfiSig = (EFI_SIGNATURE_LIST *) &Auth2->AuthInfo.CertData[SigListOffset];
+ Size -= OFFSET_OF (EFI_VARIABLE_AUTHENTICATION_2, AuthInfo);
+ Size -= OFFSET_OF (WIN_CERTIFICATE_UEFI_GUID, CertData);
+ Size -= SigListOffset;
+
+ while (Size > 0) {
+ ConcatenateSigList (&EfiSig, TmpEfiSig, SigListsSize);
+ Size -= TmpEfiSig->SignatureListSize;
+ TmpEfiSig = (EFI_SIGNATURE_LIST *)((UINT8 *)TmpEfiSig + TmpEfiSig->SignatureListSize);
+ }
+ } else if (RsaGetPublicKeyFromX509 (Buffer, Size, &RsaPubKey) == TRUE) {
+ Status = CreateSigList (Buffer, Size, &TmpEfiSig);
+
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Cannot create a sig list\n", __FUNCTION__));
if (EfiSig != NULL) {
FreePool(EfiSig);
}
FreePool(Buffer);
- return EFI_INVALID_PARAMETER;
- }

- Status = CreateSigList (Buffer, Size, &TmpEfiSig);
-
- //
- // Concatenate lists if more than one section found
- //
- if (KeyIndex == 0) {
- EfiSig = TmpEfiSig;
- *SigListsSize = TmpEfiSig->SignatureListSize;
- } else {
- ConcatenateSigList (EfiSig, TmpEfiSig, &TmpEfiSig2, SigListsSize);
- FreePool (EfiSig);
- FreePool (TmpEfiSig);
- EfiSig = TmpEfiSig2;
+ return Status;
}

- KeyIndex++;
- FreePool (Buffer);
- } if (Status == EFI_NOT_FOUND) {
- break;
+ ConcatenateSigList (&EfiSig, TmpEfiSig, SigListsSize);
+ FreePool (TmpEfiSig);
+ } else {
+ DEBUG ((DEBUG_ERROR, "%a: Invalid key format: %d\n", __FUNCTION__, KeyIndex));
+ if (EfiSig != NULL) {
+ FreePool(EfiSig);
+ }
+ FreePool(Buffer);
+ return EFI_INVALID_PARAMETER;
}
- };

- if (KeyIndex == 0) {
- return EFI_NOT_FOUND;
+ KeyIndex++;
+ FreePool (Buffer);
}

*SigListOut = EfiSig;
--
2.25.1

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH v4 01/15] DynamicTablesPkg: Definition for HwInfoParser interface

Joey Gouly
 

Hi Pierre,

From: Pierre Gondois <Pierre.Gondois@...>

Hardware information parser is an optional module defined
by the Dynamic Tables Framework. It can either parse an
XML, a Device Tree or a Json file containing the platform
hardware information to populate the platform information
repository.

The Configuration Manager can then utilise this information
to generate ACPI tables for the platform.

Therefore, define an interface for the HwInfoParser library
class.
Reviewed-by: Joey Gouly <joey.gouly@...>

Thanks,
Joey


Re: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.

manickavasakam karpagavinayagam
 

Nate :

Seems you forgot to see [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform changes. Patch V2 has all the required changes and it was reviewed by Isaac.

Thank you

-Manic

-----Original Message-----
From: Desimone, Nathaniel L <nathaniel.l.desimone@...>
Sent: Monday, December 13, 2021 7:11 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@...>; devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@...>; Harikrishna Doppalapudi <Harikrishnad@...>; Manish Jha <manishj@...>; Zachary Bobroff <zacharyb@...>; Manickavasakam Karpagavinayagam <manickavasakamk@...>
Subject: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.


**CAUTION: The e-mail below is from an external source. Please exercise caution before opening attachments, clicking links, or following guidance.**

Hi Manic,

I have a few code review comments for you.

Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\build_board.py - Misspelling... "JunctioCity" should be "JunctionCity"

Readme.md - Revert this change, we only refer to SoC/chipset generations in this file. Since Junction City is a new board added to an existing chipset we don't need to reference it here.

Platform\Intel\Readme.md - I've attached my recommended fixes for this file. There is a summary:

1. This is not needed: * The `WhitleyOpenBoardPkg` contains board implementations for JunctionCity systems.
2. Manufacturer for Junction City should be Intel/Wiwynn instead of just Intel Corporation
3. Board name should be OCP Junction City
4. **JunctionCity** should be **WhitleyOpenBoardPkg/JunctionCity**
5. Don't need second "known limitations" section
6. Need to fix WhitleyOpenBoardPkg directory tree

WhitleyOpenBoardPkg\JunctionCity\Library\IpmiPlatformHookLib\IpmiPlatformHookLib.c

1. Please fix the function documentation format for PlatformIpmiIoRangeSet()

WhitleyOpenBoardPkg\JunctionCity\Library\PeiPlatformHookLib\PeiPlatformHooklib.c

1. Trailing Whitespace

WhitleyOpenBoardPkg\JunctionCity\Platform\Pei\PlatformInfo\PlatformInfo.c

1. Trailing Whitespace

WhitleyOpenBoardPkg\JunctionCity\PlatformPkg.dsc

1. Should merge the following items back to Wilson City:
a. AdvancedFeaturesPkg enabling
b. DxeTcg2PhysicalPresenceLib override removal
c. Isal compiler override removal

WhitleyOpenBoardPkg\JunctionCity\PlatformPkg.fdf

1. Should merge the following items back to Wilson City:
a. !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
b. !include AdvancedFeaturePkg/Include/PreMemory.fdf
c. ASpeedAst2500Gop.efi
d. !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
e. !include AdvancedFeaturePkg/Include/PostMemory.fdf

WhitleyOpenBoardPkg\Uba\UbaDxeRpBoards.fdf

1. TypeJunctioCity should be TypeJunctionCity

Thanks,
Nate

-----Original Message-----
From: manickavasakam karpagavinayagam <manickavasakamk@...>
Sent: Monday, November 29, 2021 3:15 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Oram, Isaac W
<isaac.w.oram@...>; DOPPALAPUDI, HARIKRISHNA
<harikrishnad@...>; Jha, Manish <manishj@...>; Bobroff,
Zachary <zacharyb@...>; KARPAGAVINAYAGAM, MANICKAVASAKAM
<manickavasakamk@...>
Subject: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for
Junction City Platform.

Support for JunctionCity Platform
- Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all
other files in UBA folder are just name replacement (replaced
TypeWilsonCity with TypeJunctionCity)
- Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time
- JunctionCity has different SKU's. Apart from reading the GPIO's
always forcing
board id to JunctionCity in GetPlatformInfo()

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Isaac Oram <isaac.w.oram@...>
Cc: Harikrishna Doppalapudi <harikrishnad@...>
Cc: Manish Jha <manishj@...>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@...>
Cc: Zachary Bobroff <zacharyb@...>

Signed-off-by: Manickavasakam Karpagavinayagam
<manickavasakamk@...>
---
Platform/Intel/Readme.md | 12 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
| 2 +

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHoo
kLib/IpmiPlatformHookLib.c | 60 ++

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHoo
kLib/IpmiPlatformHookLib.inf | 32 +

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHook
Lib/PeiPlatformHooklib.c | 92 ++

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHook
Lib/PeiPlatformHooklib.inf | 35 +

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformIn
fo/PlatformInfo.c | 741 +++++++++++++++

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformIn
fo/PlatformInfo.h | 90 ++

Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformIn
fo/PlatformInfo.inf | 64 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
| 996 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
| 821 ++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
| 127 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
| 37 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
| 1 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
| 11 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
| 2 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
| 8 +

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 100 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 119 +++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 116 +++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 58 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 128 +++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe
/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 45 +

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
AcpiTablePcds.c | 54 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
GpioTable.c | 296 ++++++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/I
ioBifurInit.c | 242 +++++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
KtiEparam.c | 69 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
PcdData.c | 275 ++++++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
PchEarlyUpdate.c | 93 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
PeiBoardInit.h | 78 ++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
PeiBoardInitLib.c | 157 +++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
PeiBoardInitLib.inf | 167 ++++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
SlotTable.c | 172 ++++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
SoftStrapFixup.c | 121 +++

Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/
UsbOC.c | 127 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
| 9 +
Platform/Intel/build.cfg | 1 +
Readme.md | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
| 2 +
42 files changed, 5684 insertions(+)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 965009ce21..dd02d1526d 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -60,6 +60,7 @@ A UEFI firmware implementation using MinPlatformPkg
is constructed using the fol
* The `CometlakeOpenBoardPkg` contains board implementations for
CometLake systems.

* The `TigerlakeOpenBoardPkg` contains board implementations for
TigerLake systems.

* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-
SP and Cooper Lake systems.

+* The `WhitleyOpenBoardPkg` contains board implementations for
JunctionCity systems.



### **Supported Hardware**



@@ -89,6 +90,7 @@ A UEFI firmware implementation using MinPlatformPkg
is constructed using the fol
| TGL-U DDR4 RVP | TigerLake |
TigerlakeOpenBoardPkg | TigerlakeURvp |

| Wilson City RVP | IceLake-SP (Xeon Scalable) |
WhitleyOpenBoardPkg | WilsonCityRvp |

| Cooper City RVP | Copper Lake |
WhitleyOpenBoardPkg | CooperCityRvp |

+| JunctionCity | IceLake-SP (Xeon Scalable) |
WhitleyOpenBoardPkg | JunctionCity |



*Note: RVP = Reference and Validation Platform*



@@ -392,6 +394,16 @@ For PurleyOpenBoardPkg (TiogaPass)
**WhitleyOpenBoardPkg**

1. This firmware project has been tested booting to UEFI shell with headless
serial console



+**JunctionCity**

+1. This firmware project has been tested booting to UEFI shell

+2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk

+3. Booted to Windows 2019 using M2 SSD Disk

+4. Connected PCIE Network card and made sure PCIE card detected in POST
and in OS

+5. Verified TPM offboard chip detection

+

+### **Known limitations**

+1. System boots very slow when booting to RHEL 8.2 OS using SATA drive

+

### **Package Builds**



In some cases, such as BoardModulePkg, a package may provide a set of
functionality that is included in other

diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
index 99ab0961ca..05d140898f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -2,6 +2,7 @@
# Platform description.

#

# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2021, American Megatrends International LLC. <BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

@@ -133,5 +134,6 @@
}

SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf

SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf

+ SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf

!endif



diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.c
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.c
new file mode 100644
index 0000000000..680b0ac6b7
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.c
@@ -0,0 +1,60 @@
+/** @file
+ This file implements the IPMI Platform hook functions
+
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#define KCS_BASE_ADDRESS_MASK 0xFFF0
+#define NUMBER_OF_BYTES_TO_DECODE 0x10
+
+//
+// Prototype definitions for IPMI Platform Update Library
+//
+
+EFI_STATUS
+EFIAPI
+PlatformIpmiIoRangeSet(
+ UINT16 IpmiIoBase
+)
+/*++
+
+ Routine Description:
+
+ This function sets IPMI Io range
+
+ Arguments:
+
+ IpmiIoBase
+
+ Returns:
+
+ Status
+
+--*/
+{
+
+ EFI_STATUS Status;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((EFI_D_INFO, "PlatformIpmiIoRangeSet IpmiIoBase
%x\n",IpmiIoBase));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PeiServicesLocatePpi for
gDynamicSiLibraryPpiGuid failed. Status %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase &
KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE);
+
+ return EFI_SUCCESS;
+
+}
\ No newline at end of file
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.inf
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.inf
new file mode 100644
index 0000000000..699d89b24a
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH
ookLib/IpmiPlatformHookLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for IPMI platform hook Library.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiPlatformHookLib
+ FILE_GUID = A770BDB8-331A-4110-8B60-81FC17480B36
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IpmiPlatformHookLib
+
+[sources]
+ IpmiPlatformHookLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Ppis]
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.c
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..d2ccfebc43
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.c
@@ -0,0 +1,92 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <Library/PeiPlatformHooklib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+/**
+ Configure GPIO
+
+ @param[in] PlatformInfo
+**/
+VOID
+GpioInit (
+)
+{
+ EFI_STATUS Status;
+ Status = PlatformInitGpios();
+}
+
+/**
+ Disables ME PCI devices like IDE-R , KT
+
+ @param[in] None
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+DisableMEDevices (
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((DEBUG_INFO, "DisableMEDevices\n"));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ //Disable IDE-R
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE +
R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+
+ //
+ //Disable KT
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE +
R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+ return EFI_SUCCESS;
+
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ )
+{
+
+ GpioInit();
+ DisableMEDevices ();
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.inf
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..fb3985c4e0
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo
okLib/PeiPlatformHooklib.inf
@@ -0,0 +1,35 @@
+## @file
+#
+# @copyright
+# Copyright 1999 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPlatformHookLib
+ FILE_GUID = 6E9351C3-A17A-4ADF-8602-55B07962718F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiPlatformHooklib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ UbaGpioInitLib
+
+[Pcd]
+
+[Ppis]
+
+[Guids]
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.c
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.c
new file mode 100644
index 0000000000..acc9605df2
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.c
@@ -0,0 +1,741 @@
+/** @file
+ Platform Info PEIM.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInfo.h"
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Library/PchInfoLib.h>
+
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+#include <Library/UbaGpioPlatformConfig.h>
+#include <UncoreCommonIncludes.h>
+#include <PlatformInfoTypes.h>
+
+#include <Library/PeiServicesLib.h>
+
+#define TEMP_BUS_NUMBER (0x3F)
+
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI |
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPlatformInfoGuid,
+ NULL
+ };
+
+#define BOARD_ID_GPIO_PADS_NUMBER 6
+#define BOARD_REV_ID_GPIO_PADS_NUMBER 3
+
+//
+// These pads shall not be board specific as these are used for Board ID and
Rev ID detection
+// Therefore can not be moved to UBA and are common for all Purley
boards
+//
+GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] = {
+ // BoardId pads - PADCFG register for GPIO G12
+ // WARNING: The pad number must be obtained from board schematics
+ GPIO_SKL_H_GPP_G12,
+ GPIO_SKL_H_GPP_G13,
+ GPIO_SKL_H_GPP_G14,
+ GPIO_SKL_H_GPP_G15,
+ GPIO_SKL_H_GPP_G16,
+ GPIO_SKL_H_GPP_B19
+};
+
+GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER]
= {
+ // Board RevId pads - Start from pad C12
+ // WARNING: This should be obtained from board schematics
+ GPIO_SKL_H_GPP_C12,
+ GPIO_SKL_H_GPP_C13,
+ GPIO_SKL_H_GPP_B9
+};
+
+GPIO_CONFIG mBoardAndRevIdConfig = {
+ // Board and Revision ID pads configuration required for proper reading
the values
+ GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault,
GpioIntDefault,
+ GpioPlatformReset, GpioTermDefault, GpioLockDefault,
GpioRxRaw1Default
+};
+
+
+VOID
+GpioConfigForBoardId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i],
&PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+
+VOID
+GpioConfigForBoardRevId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i],
&PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+
+ Reads GPIO pins to get Board ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardId (
+ OUT UINT32 *BoardId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 BdId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ BdId = 0;
+
+ GpioConfigForBoardId ();
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i],
&Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ BdId = BdId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardId = BdId;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Reads GPIO pins to get Board Revision ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardRevId (
+ OUT UINT32 *BoardRevId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 RevId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardRevId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ RevId = 0;
+
+ GpioConfigForBoardRevId ();
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i],
&Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ RevId = RevId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardRevId = RevId;
+ return EFI_SUCCESS;
+
+}
+
+/**
+
+ Returns the Model ID of the CPU.
+ Model ID = EAX[7:4]
+
+**/
+VOID
+GetCpuInfo (
+ UINT32 *CpuType,
+ UINT8 *CpuStepping
+ )
+
+{
+ UINT32 RegEax=0;
+
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
+
+ *CpuStepping = (UINT8) (RegEax & 0x0F);
+ *CpuType = (UINT32) (RegEax >> 4);
+}
+
+
+/**
+
+ GC_TODO: add routine description
+
+ @param BAR - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+InitGSX(
+ UINT32 *BAR,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+GsxRead(
+ UINT32 *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+GetGsxBoardID(
+ BOARD_ID *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+
+ EFI_STATUS Status;
+ UINT32 GSXIN[2];
+ UINT32 RetryCount;
+
+ RetryCount = 0;
+ GSXIN[0] = 0;
+ GSXIN[1] = 0;
+
+ do {
+ Status = GsxRead(GSXIN, PeiServices);
+
+ if(Status){
+ // if EFI_SUCCESS != Success then retry one more time
+ RetryCount ++;
+ }else{
+ // if EFI_SUCCESS read Board ID and exit
+ RetryCount = 0xFFFFFFFF;
+ }
+
+ if (GSXIN[0] & BIT0) {
+ Data->BoardID.BoardID0 = 1;
+ }
+
+ if (GSXIN[0] & BIT1) {
+ Data->BoardID.BoardID1 = 1;
+ }
+
+ if (GSXIN[0] & BIT2) {
+ Data->BoardID.BoardID2 = 1;
+ }
+
+ if (GSXIN[0] & BIT3) {
+ Data->BoardID.BoardID3 = 1;
+ }
+
+ if (GSXIN[0] & BIT4) {
+ Data->BoardID.BoardID4 = 1;
+ }
+
+ if (GSXIN[0] & BIT5) {
+ Data->BoardID.BoardRev0 = 1;
+ }
+
+ if (GSXIN[0] & BIT6) {
+ Data->BoardID.BoardRev1 = 1;
+ }
+
+ } while(RetryCount < 1);
+
+ if(Status){
+ //
+ // Unhable to read GSX HW error Hang the system
+ //
+ DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM
HANG\n"));
+ CpuDeadLoop ();
+ }
+}
+
+/**
+ Get Platform Type by read Platform Data Region in SPI flash.
+ SPI Descriptor Mode Routines for Accessing Platform Info from Platform
Data Region (PDR)
+
+ @param PeiServices - General purpose services available to every PEIM.
+ @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob-
BoardId
+
+ @retval Status EFI_SUCCESS - PDR read success
+ @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid
Platform Type
+
+**/
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ EFI_STATUS Status;
+ PCH_SPI_PROTOCOL *SpiPpi;
+ UINTN Size;
+
+ //
+ // Locate the SPI PPI Interface
+ //
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ &SpiPpi
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // Read the PIT (Platform Info Table) from the SPI Flash Platform Data
Region
+ //
+ Size = sizeof (EFI_PLATFORM_INFO);
+ Status = SpiPpi->FlashRead (
+ SpiPpi,
+ FlashRegionPlatformData,
+ PDR_REGION_START_OFFSET,
+ (UINT32) Size,
+ (UINT8 *) PlatformInfoHob
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if ((PlatformInfoHob->BoardId >= TypePlatformMin) &&
(PlatformInfoHob->BoardId <= TypePlatformMax)) {
+ //
+ // Valid Platform Identified
+ //
+ DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type =
%x\n",PlatformInfoHob->BoardId));
+ } else {
+ //
+ // Reading PIT from SPI PDR Failed or a unknown platform identified
+ //
+ DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This
is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob-
BoardId));
+ PlatformInfoHob->BoardId = TypePlatformUnknown;
+ Status = EFI_INCOMPATIBLE_VERSION;
+ }
+ return Status;
+}
+
+VOID
+GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob)
+/**
+
+ GC_TODO: add routine description
+
+ @param None
+
+ @ret None
+**/
+{
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ // Gpio programming to QAT board detection
+ PadConfig.PadMode = GpioPadModeGpio;
+ PadConfig.HostSoftPadOwn = GpioHostOwnDefault;
+ PadConfig.Direction = GpioDirIn;
+ PadConfig.OutputState = GpioOutLow;
+ PadConfig.InterruptConfig = GpioIntDis;
+ PadConfig.PowerConfig = GpioResetPwrGood;
+ PadConfig.ElectricalConfig = GpioTermNone;
+ PadConfig.LockConfig = GpioPadConfigLock;
+ PadConfig.OtherSettings = 00;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3,
&PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3,
&PlatformInfoHob->QATDis);
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4,
&PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4,
&PlatformInfoHob->QATSel);
+}
+
+EFI_STATUS
+GetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiServices - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+{
+
+
+ UINT32 BoardId;
+ UINT32 BoardRev;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_STATUS Status;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ ASSERT (PciCfgPpi != NULL);
+
+ PlatformInfoHob->BoardId = TypeNeonCityEPRP;
+ DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n"));
+
+ Status = GpioGetBoardId (&BoardId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ Status = GpioGetBoardRevId (&BoardRev);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ PlatformInfoHob->TypeRevisionId = BoardRev;
+
+ //
+ //Forcing the Board id to JunctionCity
+ //
+ PlatformInfoHob->BoardId = TypeJunctionCity;
+ DEBUG ((DEBUG_INFO, "Board ID = TypeJunctionCity\n"));
+
+ GatherQATInfo(PlatformInfoHob);
+
+ DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev));
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function initializes the board related flag to indicates if
+ PCH and Lan-On-Motherboard (LOM) devices is supported.
+
+**/
+VOID
+GetPchLanSupportInfo(
+ IN EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ PlatformInfoHob->PchData.LomLanSupported = 0;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioCommonRcPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+ {
+ UINT8 IsocEn;
+
+ CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) +
OFFSET_OF(SOCKET_COMMONRC_CONFIGURATION, IsocEn),
sizeof(UINT8));
+
+ PlatformInfoHob->SysData.IsocEn = IsocEn; // ISOC enabled
+
+ return EFI_SUCCESS;
+}
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Type detection. Because the PEI globle variable
+ is in the flash, it could not change directly.So use
+ 2 PPIs to distinguish the platform type.
+
+ @param FfsHeader - Pointer to Firmware File System file header.
+ @param PeiServices - General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS - Memory initialization completed successfully.
+ @retval Others - All other error conditions encountered result in an
ASSERT.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformInfoInit (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ EFI_PLATFORM_INFO PlatformInfoHob;
+ EFI_PLATFORM_INFO tempPlatformInfoHob;
+ UINT8 ChipId;
+ UINT32 Delay;
+ UINT32 CpuType;
+ UINT8 CpuStepping;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ if (PciCfgPpi == NULL) {
+ DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a
NULL Pointer!!!\n"));
+ ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Locate Variable PPI
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0,
NULL, &PeiVariable);
+
+ (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0);
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
&DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // --------------------------------------------------
+ //
+ // Detect the iBMC SIO for CV/CRB Platforms
+ // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM.
+ //
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ ChipId = IoRead8 (PILOTIV_SIO_DATA_PORT);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n"));
+ }
+
+ Status = GetIioPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update PCH Type
+ //
+ PlatformInfoHob.PchType = DynamicSiLibraryPpi->GetPchSeries ();
+ PlatformInfoHob.PchSku = DynamicSiLibraryPpi->GetPchLpcDeviceId ();
+ PlatformInfoHob.PchRevision = (UINT8) DynamicSiLibraryPpi->PchStepping
();
+ PlatformInfoHob.MaxNumOfPchs = 1;
+ Status = EFI_SUCCESS;
+
+ if(!EFI_ERROR(Status)) {
+ Status = GetPlatformInfo (PeiServices, &PlatformInfoHob);
+ if(EFI_ERROR (Status)) {
+ Status = PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob);
+ PlatformInfoHob.BoardId = tempPlatformInfoHob.BoardId;
+ PlatformInfoHob.TypeRevisionId =
tempPlatformInfoHob.TypeRevisionId;
+ if (EFI_ERROR(Status)) {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+ }
+ } else {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+
+ //
+ // Update IIO Type
+ //
+ PlatformInfoHob.IioRevision = 0;
+
+
+ //
+ // Get Subtractive decode enable bit from descriptor
+ //
+
+ if (DynamicSiLibraryPpi->PchIsGbeRegionValid () == FALSE) {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 1;
+ } else {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 0;
+ }
+ GetPchLanSupportInfo (&PlatformInfoHob);
+ PlatformInfoHob.PchData.GbePciePortNum = 0xFF;
+ PlatformInfoHob.PchData.GbePciePortNum = (UINT8)
DynamicSiLibraryPpi->PchGetGbePortNumber ();
+ PlatformInfoHob.PchData.GbeEnabled = DynamicSiLibraryPpi-
PchIsGbePresent ();
+ PlatformInfoHob.PchData.PchStepping = (UINT8) DynamicSiLibraryPpi-
PchStepping ();
+
+ PlatformInfoHob.SysData.SysSioExist = (UINT8)IsSioExist();
+
+ GetCpuInfo (&CpuType, &CpuStepping);
+ PlatformInfoHob.CpuType = CpuType;
+ PlatformInfoHob.CpuStepping = CpuStepping;
+
+ //
+ // Set default memory topology to DaisyChainTopology. This should be
modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof
(PlatformInfoHob.MemoryTopology), DaisyChainTopology);
+
+ //
+ // Set default memory type connector to DimmConnectorPth. This should
be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType,
sizeof (PlatformInfoHob.MemoryConnectorType), DimmConnectorPth);
+
+ //
+ // Build HOB for setup memory information
+ //
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfoHob),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Save PlatformInfoHob.BoardId in CMOS
+ //
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA,
(UINT8)PlatformInfoHob.BoardId);
+
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA,
(UINT8)((PlatformInfoHob.PcieRiser2Type << 4) +
(PlatformInfoHob.PcieRiser1Type)));
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.h
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.h
new file mode 100644
index 0000000000..bb00b2cc75
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.h
@@ -0,0 +1,90 @@
+/** @file
+ Platform Info Driver.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_INTERNAL_H_
+#define _PLATFORM_INFO_INTERNAL_H_
+
+#include <PiPei.h>
+#include <Ppi/CpuIo.h>
+#include <Ppi/Spi.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PlatformHooksLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Guid/SocketVariable.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PlatformInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Platform.h>
+#include "SioRegs.h"
+#include <Register/PchRegsSpi.h>
+#include <PchAccess.h>
+#include <Register/PchRegsLpc.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Register/Cpuid.h>
+
+#define EFI_PLATFORMINFO_DRIVER_PRIVATE_SIGNATURE
SIGNATURE_32 ('P', 'I', 'N', 'F')
+
+//
+// CPU Model
+//
+#define INVALID_MODEL 0x0
+
+#define R_SB_SPI_FDOC 0xB0
+#define R_SB_SPI_FDOD 0xB4
+#define SPI_OPCODE_READ_INDEX 4
+#define PDR_REGION_START_OFFSET 0x0
+
+typedef union BOARD_ID
+{
+ struct{
+ UINT8 BoardID0 :1;
+ UINT8 BoardID1 :1;
+ UINT8 BoardID2 :1;
+ UINT8 BoardID3 :1;
+ UINT8 BoardID4 :1;
+ UINT8 BoardRev0 :1;
+ UINT8 BoardRev1 :1;
+ UINT8 Rsvd :1;
+ }BoardID;
+}BOARD_ID;
+
+typedef union RISER_ID
+{
+ struct{
+ UINT8 RiserID0 :1;
+ UINT8 RiserID1 :1;
+ UINT8 RiserID2 :1;
+ UINT8 RiserID3 :1;
+ UINT8 Rsvd :4;
+ }RiserID;
+}RISER_ID;
+
+
+
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ );
+
+EFI_STATUS
+GPIOGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+);
+
+#endif
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.inf
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.inf
new file mode 100644
index 0000000000..41c072e29e
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/Platform
Info/PlatformInfo.inf
@@ -0,0 +1,64 @@
+## @file
+# PlatformInfo PEIM
+#
+# @copyright
+# Copyright 2009 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformInfo
+ FILE_GUID = 0CEBAC0F-9349-44EC-A2DC-E07F34D412B3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformInfoInit
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformInfo.c
+ PlatformInfo.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ HobLib
+ IoLib
+ PlatformHooksLib
+ PeiServicesLib
+
+[Pcd]
+ gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gEfiSetupVariableGuid
+
+[Ppis]
+ gPchSpiPpiGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gPchSpiPpiGuid AND
+ gEfiPeiReadOnlyVariable2PpiGuid AND
+ gDynamicSiLibraryPpiGuid
+
+
+
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
new file mode 100644
index 0000000000..62d4ea68b0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
@@ -0,0 +1,996 @@
+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#########################################################
#######################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+#########################################################
#######################
+[Defines]
+ BOARD_NAME = JunctionCity
+ PLATFORM_NAME = $(BOARD_NAME)
+ PLATFORM_GUID = F5798629-30B2-42EC-A1CA-825FEAA8A22A
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FLASH_DEFINITION =
$(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+ #
+ # MRC common configuration options defined here
+ #
+ !include $(SILICON_PKG)/MrcCommonConfig.dsc
+
+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
+ !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
+ !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
+ !include $(RP_PKG)/DynamicExPcd.dsc
+
+ !include $(RP_PKG)/Uba/UbaCommon.dsc
+ !include $(RP_PKG)/Uba/UbaRpBoards.dsc
+
+ !include
$(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+
+#########################################################
#######################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+#########################################################
#######################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always
required.
+
+[DefaultStores]
+ 0|STANDARD
+ 1|MANUFACTURING
+
+
+#########################################################
#######################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+#########################################################
#######################
+[PcdsFeatureFlag]
+ #
+ # MinPlatform control flags
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE
+
+ # don't degrade 64bit MMIO space to 32-bit
+
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom
|FALSE
+
+ # Server doesn't support capsule update on Reset.
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALS
E
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+
gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+ gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE
+
+!if ($(CPUTARGET) == "ICX")
+
gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE
+!endif # $(CPUTARGET) == "ICX"
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+
+ ## Uncomment for better boot performance
+# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE
+# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE
+
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ## This PCD specifies whether FPGA routine will be active
+ gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == TRUE
+ gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE
+!endif
+
+ ## This PCD specifies whether or not to enable the High Speed UART
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2
+
+ ## MinPlatform Boot Stage Selector
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F #
Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047
# Built in messages: Error, MTRR, info, load, warn, init
+
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x
2 # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+
+
gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204
C45544E49 # "INTEL ID"
+
gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x21
00000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302
+
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gCpuPkgTokenSpaceGuid.PcdPlatformType|2
+ gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize -
(EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof
(EFI_FFS_FILE_HEADER))
+
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70
+
+ #
+ # This controls the NEM code region cached during SEC
+ # It usually isn't necessary to match exactly the FV layout in the FDF file.
+ # It is a performance optimization to have it match the flash region exactly
+ # as then no extra reads are done to load unused flash into cache.
+ #
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
+
+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ #
+ # These will be initialized during build
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2
+
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |
0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR
and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR
and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the
BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the
Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset
|0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware
register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR
for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset
|0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within
the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+!if $(CPUTARGET) == "ICX"
+ #
+ # ACPI PCD custom override
+ #
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x0100
0013
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET
)
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ # Enable DDRT scheduler debug features for power on
+ gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE
+
+ # Disable Fast Warm Boot for Whitley Openboard Package
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE
+
gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALS
E
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75
+
+ #
+ # PlatformInitPreMem
+ #
+
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0
x100
+
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA3
0
+
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1
00
+
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
+
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0
+
+ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
+
+[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+!if ($(FSP_MODE) == 0)
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0
+!endif
+
+[PcdsFixedAtBuild.X64]
+ # Change PcdBootManagerMenuFile to UiApp
+ ##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21,
0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66,
0x23, 0x31 }
+
+
gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC0000
0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ #
+ # AcpiPlatform
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+
gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+
gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{
0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01,
0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01,
0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03,
0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c,
0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F,
0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,
0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{
0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01,
0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01,
0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03,
0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c,
0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01,
0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0,
0x0, 0x1F, 0x0}
+ gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999
+
+[PcdsPatchableInModule]
+ #
+ # These debug options are patcheable so that they can be manipulated
during debug (if memory is updateable)
+ #
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
# Enable status codes for debug, progress, and errors
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 #
Displayed messages: Error, Info, warn
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
+
+!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000
+!endif
+
+[PcdsDynamicExDefault.IA32]
+!if ($(FSP_MODE) == 0)
+
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+!endif
+
+
+[PcdsDynamicExHii]
+
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|
gEfiGenericVariableGuid|0x0|TRUE
+
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo
balVariableGuid|0x0|5 # Variable: L"Timeout"
+
gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gP
latformTokenSpaceGuid|0x0|0
+
gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCp
PlatTokenSpaceGuid|0x0|TRUE
+
gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericV
ariableGuid|0x0|TRUE
+
gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup
port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+
gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDevic
eScratchPad"|gEfiGenericVariableGuid|0x0|FALSE
+
+[PcdsDynamicExDefault]
+
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationC
hange|FALSE
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE
+
+ gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ #Platform should change it to by code
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
+
+ #
+ # CPU features related PCDs.
+ #
+ gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01
+
+ ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29,
0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+ ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67,
0x1b, 0x90, 0xcc } }
+ ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6,
0x75, 0x8b, 0x73, 0x17 } }
+
+ #TPM2.0#
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b,
0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522
+
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee,
0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|4
+ gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x600C0
+
+[PcdsDynamicExDefault.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ #
+ # Set video to 1024x768 resolution
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
+[PcdsDynamicExDefault]
+
+!if $(CPUTARGET) == "CPX"
+ !include $(RP_PKG)/StructurePcdCpx.dsc
+!else
+ !include $(RP_PKG)/StructurePcd.dsc
+!endif
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |TRUE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|FALSE
+!endif
+
+[Defines]
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ DEFINE SECURE_BOOT_ENABLE = TRUE
+!endif
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+#########################################################
#######################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+#########################################################
#######################
+
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses]
+
+ #
+ # Simics source level debugging requires the non-null version of
PeCoffExtraActionLib
+ #
+!if $(TARGET) == "DEBUG"
+
PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibD
ebug/PeCoffExtraActionLibDebug.inf
+!else
+
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BaseP
eCoffExtraActionLibNull.inf
+!endif
+
+ #
+ # Basic
+ #
+
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Framework
+ #
+
S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootSc
riptLib.inf
+
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBuffer
BltLib.inf
+
+
SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconP
olicyInitLibShim.inf
+!if ($(FSP_MODE) == 0)
+
SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPoli
cyUpdateLibFsp.inf
+!else
+
SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPoli
cyUpdateLib.inf
+!endif
+
+ SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
+
+ #
+ # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?
+ #
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+
+
MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSuppo
rtLib.inf
+ ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf
+
PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSy
ncLibNull/PlatformSetupVariableSyncLibNull.inf
+ PlatformVariableHookLib
|$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLib
Null.inf
+
+
PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBoot
ManagerLib/DxePlatformBootManagerLib.inf
+ SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf
+
PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.i
nf
+
+
CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf
+
PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/Platfor
mCmosAccessLib.inf
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+ TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+
+ #
+ # MinPlatform uses port 80, we don't want to assume HW
+ #
+
PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDeb
ug.inf
+
+
TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibN
ull.inf
+
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorL
ibNull.inf
+
AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUp
dateLib.inf
+
PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimpl
e/PciSegmentInfoLibSimple.inf
+
PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/Pl
atformOpromPolicyLibNull.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+
+[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE,
LibraryClasses.Common.PEIM]
+
FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Ba
seFspWrapperApiLib.inf
+
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTest
Lib/PeiFspWrapperApiTestLib.inf
+
FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/F
spWrapperPlatformLib.inf
+
FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperH
obProcessLib/PeiFspWrapperHobProcessLib.inf
+
+
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit
chStackLib.inf
+
FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommon
Lib.inf
+
FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi
b.inf
+
+[LibraryClasses.Common.SEC]
+ #
+ # SEC phase
+ #
+
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTem
plate.inf
+
+
PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspW
rapperPlatformSecLib.inf
+
SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/S
ecBoardInitLibNull.inf
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTest
PointCheckLib.inf
+
VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVari
ableReadLibNull.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ #
+ # ToDo: Can we remove
+ #
+
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiC
puExceptionHandlerLib.inf
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+
+
PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHook
Lib/PeiPlatformHooklib.inf
+
PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocks
Lib.inf
+
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTest
PointCheckLib.inf
+
TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+[LibraryClasses.Common.PEIM]
+ #
+ # Library instance consumed by MinPlatformPkg PlatformInit modules.
+ #
+
ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/R
eportCpuHobLib.inf
+
SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSyste
mLib.inf
+
+!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE
+ IpmiPlatformHookLib|
$(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHo
okLib.inf
+!endif
+
+
+[LibraryClasses.common.DXE_CORE,
LibraryClasses.common.DXE_SMM_DRIVER,
LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER,
LibraryClasses.common.DXE_RUNTIME_DRIVER,
LibraryClasses.common.UEFI_DRIVER,
LibraryClasses.common.UEFI_APPLICATION]
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+
Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/D
xeTcg2PhysicalPresenceLib.inf
+
TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe
TcgPhysicalPresenceLib.inf
+
+ BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+
+
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTp
mMeasurementLib.inf
+
+
Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLib
DTpm.inf
+
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Tes
tPointCheckLibNull.inf
+
TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf
+
BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHoo
kLib.inf
+
BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLib
Null/BoardBootManagerLibNull.inf
+
+ CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+
SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFl
ashCommonLib.inf
+
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTe
stPointCheckLib.inf
+
TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.in
f
+
MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTabl
eLib.inf
+
Tcg2PhysicalPresenceLib|SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/
SmmTcg2PhysicalPresenceLib.inf
+
+[LibraryClasses.Common.SMM_CORE]
+
S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL
ibNull.inf
+
+[LibraryClasses.Common]
+
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.
inf
+ PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf
+
+[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ #
+ # Beware of circular dependencies on PCD if you want to use another
DebugLib instance.
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf
# Include FSP DynamicEx PCD
+
NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSili
con.inf # Include FvLateSilicon DynamicEx PCD
+
NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOp
enBoard.inf # Include FvLateBoard DynamicEx PCD
+ }
+
$(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterP
ei.inf
+
$(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
$(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+
$(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.
inf
+
+ $(RP_PKG)/$(BOARD_NAME)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
{
+ <LibraryClasses>
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Tes
tPointCheckLibNull.inf
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf
+
+
$(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
{
+ <LibraryClasses>
+
SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/S
iliconWorkaroundLibNull.inf
+ }
+ $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
{
+ <LibraryClasses>
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Tes
tPointCheckLibNull.inf
+
BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/Board
InitLibNull.inf
+ }
+
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+!endif
+
+ $(RP_PKG)/BiosInfo/BiosInfo.inf
+
+ WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+ !if $(PERFORMANCE_ENABLE) == TRUE
+
TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLi
bUefiCpu.inf
+ !endif
+ }
+
+[Components.X64]
+ !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+
+ $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf
+
+ MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor
Dxe.inf
+
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
ndLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
ndsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
ndsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
ndsLib.inf
+
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com
mandsLib.inf
+
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
mandsLib.inf
+
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com
mandsLib.inf
+
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1
CommandsLib.inf
+
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL
ib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg
CommandLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+ $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+
+ $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
+
+ $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+
BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnable
Lib.inf
+ }
+
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+ <LibraryClasses>
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf
+ }
+ $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {
+!if ($(FSP_MODE) == 0)
+ <BuildOptions>
+ *_*_*_CC_FLAGS = -D FSP_API_MODE
+!endif
+ }
+
+
$(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.in
f
+
+ $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+
MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe
.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurement
Dxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # SiliconPkg code for Platform Integration are defined here
+ #
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+[PcdsFixedAtBuild]
+!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)
+ gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE
+!endif
+[LibraryClasses.common.DXE_DRIVER,
LibraryClasses.common.UEFI_DRIVER,
LibraryClasses.common.UEFI_APPLICATION]
+
ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSyst
emLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+
ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/Runtime
ResetSystemLib.inf
+
+
+#########################################################
##########################################
+#
+# BuildOptions Section - Define the module specific tool chain flags that
should be used as
+# the default flags for a module. These flags are appended to
any
+# standard flags that are defined by the build process. They can
be
+# applied for any modules or only those modules with the
specific
+# module style (EDK or EDKII) specified in [Components] section.
+#
+#########################################################
##########################################
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is
Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D
PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D
PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D
SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -
D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D
MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D
MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D
MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D
MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH)
$(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS)
$(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS)
$(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS)
$(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS)
$(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS)
$(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION)
$(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT
$(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D
DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS)
$(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS)
$(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D
ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS)
$(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
/wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS =
$(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS =
$(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS =
$(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS =
$(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS =
$(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS =
$(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override ASL Compiler parameters in tools_def.template.
+#
+ *_*_*_ASL_FLAGS == -vr -we -oi
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER,
BuildOptions.common.EDKII.DXE_SMM_DRIVER,
BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -
Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-
pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
new file mode 100644
index 0000000000..deaac1bd7a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
@@ -0,0 +1,821 @@
+## @file
+# FDF file of platform with 64-bit DXE
+# This package provides platform specific modules and flash layout
information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof
(EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =
0x90 # FV Header plus FFS header
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+ DEFINE FSP_BIN_DIR = Api
+!else
+ DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the
gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this
guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note
change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form
'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the
system, and
+# the FlashMap edit tool can be used to change the values here, without
effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
+
+#########################################################
#######################
+#
+# FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+# FvBsp for board specific components
+# FvPostMemory for compressed post memory MinPlatform spec
required components
+# FvFspS for compressed post memory silicon initialization components
+# FvPostMemorySilicon for silicon components
+# FvFspM for pre memory silicon initialization components
+# FvPreMemorySilicon for silicon components
+# FvFspT for temp RAM silicon initilization components
+# FvBspPreMemory for board specific components required to intialize
memory
+# FvAdvancedPreMemory FV for advanced features components
+# FvPreMemory for components required by MinPlatform spec and to
initialize memory
+# FvPreMemorySecurity FV for stage 6 required components
+# Contains reset vector
+#
+#########################################################
#######################
+
+[FD.SecPei]
+ BaseAddress = 0xFFCA0000
|gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base
address of the FLASH Device
+ Size = 0x00360000
|gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in
bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x360
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually
calculate the offsets.
+ # At this time, the FSP FV must be aligned at the same address they were
built to, 0xFFD00000
+ # This will be corrected in the future.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =
0x00010000 # BaseAddress + PcdFlashFvBspSize +
PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =
0x00010000 # BaseAddress + PcdFlashFvBspSize +
PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =
0x00040000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =
0x00221000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =
0x00006000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =
0x00009000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =
gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =
0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ #
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTo
kenSpaceGuid.PcdFlashFvBspSize
+ FV = FvBsp
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatf
ormPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ FV = FvPostMemory
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgT
okenSpaceGuid.PcdFlashFvFspSSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkg
TokenSpaceGuid.PcdFlashFvFspMSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgT
okenSpaceGuid.PcdFlashFvFspTSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+ #
+ # Shared FV layout
+ #
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPl
atformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+ FV = FvBspPreMemory
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatfo
rmPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ FV = FvPreMemory
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Set duplicate PCD
+ # These should not need to be changed
+ #
+
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+ #
+ # For API mode, wrappers have some duplicate PCD as well
+ #
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+
+#########################################################
#######################
+#
+# FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+# FvAdvanced for advanced feature components
+# Assorted advanced feature FV
+# FvSecurity for MinPlatform spec required components needed to boot
securely
+# FvOsBoot for MinPlatform spec required components needed to boot
OS
+# FvLateSilicon for silicon specific components
+# FvUefiBoot for MinPlatform spec required components needed to boot
to UEFI shell
+#
+#########################################################
#######################
+[FD.Main]
+ BaseAddress = 0xFF2E0000 |
gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of
the FLASH Device
+ Size = 0x009C0000 |
gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of
the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x9C0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually
calculate the offsets.
+ # These are out of flash layout order because FvAdvanced gets any
remaining space
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =
0x00040000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =
0x00230000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =
0x0004C000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =
gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize -
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =
0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ #
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatfor
mPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ FV = FvAdvanced
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformP
kgTokenSpaceGuid.PcdFlashFvSecuritySize
+ FV = FvSecurity
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPk
gTokenSpaceGuid.PcdFlashFvOsBootSize
+ FV = FvOsBoot
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatform
PkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+ FV = FvUefiBoot
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture
specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+#########################################################
#######################
+#
+# FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+# FvOpRom containing pre-built components
+# FvAcmRegion containing ACM related content
+# FV Header + Blank Space (1K)
+# Policy block (3K)
+# Blank space to align ACM on 64K boundary (60K)
+# ACM binary
+# FvMicrocode containing microcode update patches
+# Unformatted region for PCI Gen 3 Data
+# FvVpd containing PCD VPD data
+# FvWhea for WHEA data recording
+# FvNvStorageVariable for UEFI Variable storage
+# FvNvStorageEventLog for NV Store management
+# FvNvStorageFtwWorking for Fault Tolerant Write solution
+# FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+#########################################################
#######################
+[FD.Binary]
+ BaseAddress = 0xFF000000
|gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+ Size = 0x002E0000
|gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2E0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually
calculate the offsets.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize =
0x00100000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize =
0x00050000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =
0x000D0000
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize =
0x00010000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize =
0x00030000
+ #
+ # These four items are tightly coupled.
+ # The spare area size must be >= the first three areas.
+ #
+ # There isn't really a benefit to a larger spare area unless the FLASH device
+ # block size is larger than the size specified.
+ #
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
= 0x0003C000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize =
0x00002000
+ SET
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Calculate Offsets Once (You should not need to modify this section)
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset =
0x00000000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset =
gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset +
gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset
= gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET
gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset =
gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET
gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =
gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset
= gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
dynamically
+ #
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
= gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize -
gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+
+ #
+ # FV Layout (You should not need to modify this section)
+ #
+
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSp
aceGuid.PcdFlashFvOpromSize
+ FV = FvOprom
+
+
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTok
enSpaceGuid.PcdFlashFvAcmRegionSize
+ FV = FvAcm
+
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatfor
mPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ FV = FvMicrocode
+
+
gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleT
okenSpaceGuid.PcdFlashFvVpdSize
+ FV = FvVPD
+
+
gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpa
ceGuid.PcdFlashFvWheaSize
+ FV = FvWhea
+
+ #
+ # Do not modify.
+ # See comments in size discussion above. These four areas are tightly
coupled and should be modified with utmost care.
+ #
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMd
eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+
gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gC
pPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as
Base/Size to be written
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEf
iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ !include
WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+
gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiM
deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as
Base/Size to be written
+
+ #
+ # Calculate base addresses (You should not need to modify this section)
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize +
$(VPD_HEADER_SIZE)
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase =
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress +
gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize -
$(VPD_HEADER_SIZE)
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
= gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase =
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # ACM details
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
+
+ #
+ # Other duplicate PCD
+ #
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize +
gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+#########################################################
#######################
+#
+# FD FPGA
+#
+# Contains the FPGA modules
+#
+#########################################################
#######################
+
+[FD.Fpga]
+ BaseAddress = 0xFD000000
|gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base
address of the FPGA Device ( 4G - 48M )
+ Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize
#The size in bytes of the FPGA Device ( 32M )
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2000
+
+ 0x00000000|0x02000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase |
gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+ FV = FvFpga
+
+#########################################################
#######################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed
within a flash
+# device file. This section also defines order the components and modules
are positioned
+# within the image. The [FV] section consists of define statements, set
statements and
+# module statements.
+#
+#########################################################
#######################
+
+[FV.FvSecurityPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ INF UefiCpuPkg/SecCore/SecCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF
WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCo
deRouterPei.inf
+ INF
WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHa
ndlerPei.inf
+
+ INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF
MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+ INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+ INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+
+ FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+ SECTION PEI_DEPEX =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-
1137493c0f38DynamicSiLibrary.depex
+ SECTION Align = 32 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-
1137493c0f38DynamicSiLibrary.efi
+ SECTION UI = "DynamicSiLibraryPei"
+ }
+
+ INF
WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVar
iableInitPei.inf
+
+ INF
WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatfo
rmInit.inf
+
+ INF
WhitleyOpenBoardPkg/$(BOARD_NAME)/Platform/Pei/PlatformInfo/Platfor
mInfo.inf
+
+ #
+ # UBA common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+ INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+ FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+ SECTION PEI_DEPEX =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-
9fb373649161SiliconPolicyInitPreAndPostMem.depex
+ SECTION Align = 32 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-
9fb373649161SiliconPolicyInitPreAndPostMem.efi
+ SECTION UI = "SiliconPolicyInitPreAndPostMem"
+ }
+
+ INF
MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+ !include
WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastruc
turePreMemory.fdf
+
+ INF
WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerTo
SvidMap.inf
+
+ INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ !if $(FSP_MODE) == 0
+ FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+ SECTION PEI_DEPEX =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-
53DAC93EF407CsrPseudoOffsetInitPeim.depex
+ SECTION Align = 32 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-
53DAC93EF407CsrPseudoOffsetInitPeim.efi
+ SECTION UI = "CsrPseudoOffsetInitPeim"
+ }
+ FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+ SECTION PEI_DEPEX =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-
384DAE2B0352RegAccessPeim.depex
+ SECTION Align = 32 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-
384DAE2B0352RegAccessPeim.efi
+ SECTION UI = "RegAccessPeim"
+ }
+ FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+ SECTION PEI_DEPEX =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-
7500EAA7B67FSiliconDataInitPeim.depex
+ SECTION Align = 32 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-
7500EAA7B67FSiliconDataInitPeim.efi
+ SECTION UI = "SiliconDataInitPeim"
+ }
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF
WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+ !endif
+
+ FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+[FV.FvAdvancedPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+ !include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvBspPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+ FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+ SECTION FV_IMAGE = FvAdvancedPreMemory
+ }
+
+#
+# FvPostMemory includes common hardware, common core variable
services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+ FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompressed
+ }
+ }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+ FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvBspUncompressed
+ }
+ }
+
+[FV.FvUefiBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ INF
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF
MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe
.inf
+
+ INF
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleD
xe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF
MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurement
Dxe.inf
+ #ATA for IDE/AHCI/RAID support
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryT
estDxe.inf
+ INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
+ SECTION PE32 = edk2-non-
osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
+ }
+
+
+[FV.FvUefiBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+ FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompressed
+ }
+ }
+
+[FV.FvOsBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ #
+ # DXE Phase modules
+ #
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportSt
atusCodeRouterRuntimeDxe.inf
+ INF
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHan
dlerRuntimeDxe.inf
+
+ FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+ SECTION UI = "FvLateSilicon"
+ SECTION FV_IMAGE =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+ }
+
+ INF
MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+ !include
WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastruc
turePostMemory.fdf
+
+ #
+ # UBA DXE common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+ INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ !if ($(FSP_MODE) == 1)
+ INF
WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+ !else
+ INF
MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ !endif
+
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF
WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+ SECTION UI = "FvLateOpenBoard"
+ SECTION FV_IMAGE =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+ }
+
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF
PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime
Dxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF
WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ INF
MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+ INF
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun
terRuntimeDxe.inf
+ INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+ INF
MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuAp
p.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ #TPM when TPM enable, SecurityStubDxe needs to be removed from this
FV.
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ INF
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCod
eRouterSmm.inf
+ INF
MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSm
m.inf
+
+ INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/