Date   

Re: Soft Feature Freeze will start on 2021-11-08 for edk2-stable202111

PierreGondois
 

Hi Liming,

The "Add SSDT PCI generator in DynamicTablesPkg" feature at
https://bugzilla.tianocore.org/show_bug.cgi?id=3682 won't be merged
before hard feature freeze, so I think it should be removed from the
list of proposed features,

Regards,

Pierre

On 11/5/21 05:53, gaoliming via groups.io wrote:

Hi, all

We will enter into Soft Feature Freeze phase on 2021-11-08. In this
phase, the feature under review will not be allowed to be pushed. The
feature passed review can still be merged.

 

The patch review can continue without break in edk2 community. If the
patch is sent before Soft Feature Freeze, and plans to catch this
stable tag, the patch contributor need reply to his patch and notify
edk2 community. If the patch is sent after Soft Feature Freeze, and
plans to catch this stable tag, please add edk2-stable202111 key words
in the patch title and BZ, so the community know this patch target and
give the feedback.

 

Below is edk2-stable202111 tag planning
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Release-Planning
Proposed Schedule

Date (00:00:00 UTC-8) Description

2021-08-30  Beginning of development

2021-11-08  Soft Feature Freeze

2021-11-12  Hard Feature Freeze

2021-11-26  Release

 

Thanks

Liming


Re: [PATCH v2 3/4] OvmfPkg: Enable physical presence interface for TPM 1.2

Yao, Jiewen
 

The PPFlag variable MUST to be locked to prevent malicious modification.
Otherwise, anyone can change the PP configuration without confirmation from end user.

Thank you
Yao Jiewen

-----Original Message-----
From: Gerd Hoffmann <kraxel@...>
Sent: Monday, November 8, 2021 7:58 PM
To: Stefan Berger <stefanb@...>
Cc: devel@edk2.groups.io; marcandre.lureau@...; Yao, Jiewen
<jiewen.yao@...>; Wang, Jian J <jian.j.wang@...>; Ard Biesheuvel
<ardb+tianocore@...>; Justen, Jordan L <jordan.l.justen@...>
Subject: Re: [edk2-devel] [PATCH v2 3/4] OvmfPkg: Enable physical presence
interface for TPM 1.2

On Sat, Nov 06, 2021 at 09:19:33PM -0400, Stefan Berger wrote:

On 11/5/21 08:17, Gerd Hoffmann wrote:
On Tue, Nov 02, 2021 at 11:49:09AM -0400, Stefan Berger wrote:
Enable the physical presence interface for TPM 1.2. It is required for the
TPM 1.2 menu to work.

The changes to DxeTcgPhysicalPresenceLib.c are due to the device we are
using
in QEMU for presenting the supported PPI commands and results to the OS
via
ACPI as well as to store the PPI opcode to execute.
Fails to build for microvm.

+
TcgPhysicalPresenceLib|OvmfPkg/Library/TcgPhysicalPresenceLibNull/DxeTcgPh
ysicalPresenceLib.inf
I guess this line is needed just next to Tcg2PhysicalPresenceLibNull
line?
(same problem on OvmfXen.dsc)
Fixed in v3 for microvm and Xen and Bhyve also.

You happen to know about the variable lock issue? Why does the variable need
to be locked?
No clue, sorry. That's a topic I have to learn about myself. Noticed
the variable locking deprecation warning in the ovmf boot log too, but
havn't found the time yet to look into that.

take care,
Gerd


Re: [PATCH v2 3/4] OvmfPkg: Enable physical presence interface for TPM 1.2

Gerd Hoffmann
 

On Sat, Nov 06, 2021 at 09:19:33PM -0400, Stefan Berger wrote:

On 11/5/21 08:17, Gerd Hoffmann wrote:
On Tue, Nov 02, 2021 at 11:49:09AM -0400, Stefan Berger wrote:
Enable the physical presence interface for TPM 1.2. It is required for the
TPM 1.2 menu to work.

The changes to DxeTcgPhysicalPresenceLib.c are due to the device we are using
in QEMU for presenting the supported PPI commands and results to the OS via
ACPI as well as to store the PPI opcode to execute.
Fails to build for microvm.

+ TcgPhysicalPresenceLib|OvmfPkg/Library/TcgPhysicalPresenceLibNull/DxeTcgPhysicalPresenceLib.inf
I guess this line is needed just next to Tcg2PhysicalPresenceLibNull
line?
(same problem on OvmfXen.dsc)
Fixed in v3 for microvm and Xen and Bhyve also.

You happen to know about the variable lock issue? Why does the variable need
to be locked?
No clue, sorry. That's a topic I have to learn about myself. Noticed
the variable locking deprecation warning in the ovmf boot log too, but
havn't found the time yet to look into that.

take care,
Gerd


Re: The arm virtual machine displays problems in QXL during the UEFI phase

Gerd Hoffmann
 

Hi,

From the above point of view, your speculation is right. excellent!
In this way, if a QXL device wants to work on ARM, the io window of the bridge it is mounted on must be allocated as 00000000-00000fff [size=4K].
That doesn't solve the cache attribute issues though ...

In my work, by modifying the qemu code, the io window of the bridge
mounted with the qxl device is fixed to 00000000-00000fff to solve
this problem. what do you think?
It's not qemu but tianocore who assigns bridge windows, should be
in pci scan order, i.e. lowest slot.func goes first and gets the
0000-0fff range.

take care,
Gerd


Re: [PATCH v1 1/1] MdePkg: Fix ACPI memory aggregator/device type mismatch

Chris Jones
 

Hi,
It looks like this patch has received the relevant approvals and is ready for merge. Could this patch please be merged in time for the edk2-stable202111 release.


Thanks,
Chris

From: gaoliming <gaoliming@...>
Sent: Friday, October 8, 2021 3:09 AM
To: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; devel@edk2.groups.io <devel@edk2.groups.io>; Christopher Jones <Christopher.Jones@...>
Cc: michael.d.kinney@... <michael.d.kinney@...>; zhiguang.liu@... <zhiguang.liu@...>; Sami Mujawar <Sami.Mujawar@...>; Ben Adderson <Ben.Adderson@...>; Akanksha Jain <Akanksha.Jain2@...>; Matteo Carlini <Matteo.Carlini@...>; nd <nd@...>
Subject: 回复: [edk2-devel] [PATCH v1 1/1] MdePkg: Fix ACPI memory aggregator/device type mismatch
 
Samer:
  Thanks for your information. I agree this change. Reviewed-by: Liming Gao <gaoliming@...>

Thanks
Liming
> -----邮件原件-----
> 发件人: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
> 发送时间: 2021年10月8日 9:45
> 收件人: devel@edk2.groups.io; gaoliming@...; Christopher
> Jones <Christopher.Jones@...>
> 抄送: michael.d.kinney@...; zhiguang.liu@...; Sami Mujawar
> <Sami.Mujawar@...>; Ben Adderson <Ben.Adderson@...>;
> Akanksha Jain <Akanksha.Jain2@...>; Matteo Carlini
> <Matteo.Carlini@...>; nd <nd@...>; Samer El-Haj-Mahmoud
> <Samer.El-Haj-Mahmoud@...>
> 主题: RE: [edk2-devel] [PATCH v1 1/1] MdePkg: Fix ACPI memory
> aggregator/device type mismatch
>
> We did investigate this in the BZ, and the conclusion was it is safer to update
> the code to match the spec. The only OS implementation we have seen so far
> is in Linux, and it uses the spec defined values (although for limited usage).
> See https://bugzilla.tianocore.org/show_bug.cgi?id=3579
>
>
>
>

> > -----Original Message-----
> > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
> > gaoliming via groups.io
> > Sent: Thursday, October 7, 2021 9:26 PM
> > To: devel@edk2.groups.io; Christopher Jones
> > <Christopher.Jones@...>
> > Cc: michael.d.kinney@...; zhiguang.liu@...; Sami Mujawar
> > <Sami.Mujawar@...>; Ben Adderson <Ben.Adderson@...>;
> > Akanksha Jain <Akanksha.Jain2@...>; Matteo Carlini
> > <Matteo.Carlini@...>; nd <nd@...>
> > Subject: 回复: [edk2-devel] [PATCH v1 1/1] MdePkg: Fix ACPI memory
> > aggregator/device type mismatch
> >
> > Jones:
> >   Do you know what impact will be introduced by this change?
> >
> > Thanks
> > Liming
> > > -----邮件原件-----
> > > 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Chris
> Jones
> > > 发送时间: 2021年10月6日 18:12
> > > 收件人: devel@edk2.groups.io
> > > 抄送: michael.d.kinney@...; gaoliming@...;
> > > zhiguang.liu@...; Sami.Mujawar@...;
> > Ben.Adderson@...;
> > > Akanksha.Jain2@...; Matteo.Carlini@...; nd@...
> > > 主题: [edk2-devel] [PATCH v1 1/1] MdePkg: Fix ACPI memory
> > > aggregator/device type mismatch
> > >
> > > Bugzilla: 3578 (https://bugzilla.tianocore.org/show_bug.cgi?id=3579)
> > >
> > > Since the Common Memory Device (formerly Memory Aggregator Device)
> > > was
> > > introduced in ACPI 5.0, the edk2 type values have not matched the
> > > values defined in the ACPI specification.
> > >
> > > Fix this discrepancy by aligning the code to match the specification.
> > >
> > > Signed-off-by: Chris Jones <christopher.jones@...>
> > > ---
> > >  MdePkg/Include/IndustryStandard/Acpi50.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi51.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi60.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi61.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi62.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi63.h | 6 +++---
> > >  MdePkg/Include/IndustryStandard/Acpi64.h | 6 +++---
> > >  7 files changed, 21 insertions(+), 21 deletions(-)
> > >
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi50.h
> > > b/MdePkg/Include/IndustryStandard/Acpi50.h
> > > index
> > >
> 31a47e6a2c4276d5b1ad7b834af84844090b64c5..83d787c7650cf649fe3d2e1
> > > 2e7983bae86a2a114 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi50.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi50.h
> > > @@ -996,9 +996,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h
> > > b/MdePkg/Include/IndustryStandard/Acpi51.h
> > > index
> > >
> fc28ffa18fc6a22e52fda88fade6ad80b2817cc3..5fbf7c99f1f7d6ca9109f198bd
> > > 3f25f12bd47961 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi51.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi51.h
> > > @@ -951,9 +951,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h
> > > b/MdePkg/Include/IndustryStandard/Acpi60.h
> > > index
> > >
> 5dcd73b6f1ec4bccc7fdae7d56c2963ab58764f9..eba4248e1d5733d21973f0d
> > > ac2286e02238a0aae 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi60.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi60.h
> > > @@ -966,9 +966,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h
> > > b/MdePkg/Include/IndustryStandard/Acpi61.h
> > > index
> > >
> 8626833a794dfb4a6f19d459d5214c6caefdbbee..7a776020baa8f3ee7b6f05fe
> > > e336225ab6589ce0 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi61.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi61.h
> > > @@ -966,9 +966,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h
> > > b/MdePkg/Include/IndustryStandard/Acpi62.h
> > > index
> > >
> 1b2704e98e3703a4405075247432ec842e45021b..33a0a0f21959df8b64803e
> > > 972ab19f0c0ab1619e 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi62.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi62.h
> > > @@ -1078,9 +1078,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h
> > > b/MdePkg/Include/IndustryStandard/Acpi63.h
> > > index
> > >
> b281b30155e90eba5169dc39bde9a3379e3b7005..3b1426af27ea4ebada1a1
> > > 2e99ce958bb288ad931 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi63.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi63.h
> > > @@ -1040,9 +1040,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Aggregator Device Type
> > >  ///
> > > -#define
> > > EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > >
> >
> EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x2
> > > -#define
> > > EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define
> > > EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > >
> >
> EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_C
> > > ONTROLLER 0x1
> > > +#define
> > > EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM
> > > 0x2
> > >
> > >  ///
> > >  /// Socket Memory Aggregator Device Structure.
> > > diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h
> > > b/MdePkg/Include/IndustryStandard/Acpi64.h
> > > index
> > >
> 3a91302f8c0e71d4951d27aac35322073219c836..8346d83f1249045497b602
> > > 907b94fbb2b495cd56 100644
> > > --- a/MdePkg/Include/IndustryStandard/Acpi64.h
> > > +++ b/MdePkg/Include/IndustryStandard/Acpi64.h
> > > @@ -1075,9 +1075,9 @@ typedef struct {
> > >  ///
> > >  /// Memory Device Type.
> > >  ///
> > > -#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET
> > > 0x1
> > > -#define
> > > EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER
> > > 0x2
> > > -#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM
> > > 0x3
> > > +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET
> > > 0x0
> > > +#define
> > > EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER
> > > 0x1
> > > +#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM
> > > 0x2
> > >  #define
> > > EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE
> > > 0xFF
> > >
> > >  ///
> > > --
> > > Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")
> > >
> > >
> > >
> > >
> > >
> >
> >
> >
> >
> >
> >
> >




Re: [PATCH v1 1/1] ShellPkg: Add comment that ItemPtr is set after validation

Chris Jones
 

Hi,
It looks like this patch has recieved the relevant approvals and is ready for merge. Could this patch please be merged in time for the edk2-stable202111 release.


Thanks,
Chris

From: Gao, Zhichao <zhichao.gao@...>
Sent: Thursday, October 28, 2021 4:15 AM
To: Sami Mujawar <Sami.Mujawar@...>; Christopher Jones <Christopher.Jones@...>; devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@...>; nd <nd@...>
Subject: RE: [PATCH v1 1/1] ShellPkg: Add comment that ItemPtr is set after validation
 
Reviewed-by: Zhichao Gao <zhichao.gao@...>

Thanks,
Zhichao

> -----Original Message-----
> From: Sami Mujawar <Sami.Mujawar@...>
> Sent: Wednesday, October 20, 2021 6:54 PM
> To: Christopher Jones <Christopher.Jones@...>;
> devel@edk2.groups.io
> Cc: Ni, Ray <ray.ni@...>; Gao, Zhichao <zhichao.gao@...>; nd
> <nd@...>
> Subject: Re: [PATCH v1 1/1] ShellPkg: Add comment that ItemPtr is set after
> validation
>
> Hi Chris,
>
> Thanks for adding the comment that clarifies the usage.
>
> Reviewed-by: Sami Mujawar <sami.mujawar@...>
>
> Regards,
>
> Sami Mujawar
>
> On 20/10/2021, 11:47, "Chris Jones" <christopher.jones@...> wrote:
>
>     Add a comment to clarify that in Acpiview the ItemPtr is not set until
>     after the FieldValidator has been called.
>
>     Signed-off-by: Chris Jones <christopher.jones@...>
>     ---
>      ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h | 4 +++-
>      1 file changed, 3 insertions(+), 1 deletion(-)
>
>     diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
> b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
>     index
> 0b7726b9d5807ad2f5c5447408c4c5451718938b..5e34a70c8baeaaa05ecd797d4
> 05f1fc62a44a305 100644
>     --- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
>     +++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
>     @@ -283,7 +283,9 @@ typedef struct AcpiParser {
>        FNPTR_PRINT_FORMATTER PrintFormatter;
>
>        /// Optional pointer which may be set to request the parser to update
>     -  /// a pointer to the field data. If unused this must be set to NULL.
>     +  /// a pointer to the field data. This value is set after the FieldValidator
>     +  /// has been called and therefore should not be used by the
> FieldValidator.
>     +  /// If unused this must be set to NULL.
>        VOID**                ItemPtr;
>
>        /// Optional pointer to a field validator function.
>     --
>     Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")
>


Re: [PATCH v4 1/7] Silicon/ARM/NeoverseN1Soc: Fix missing function documentation

Khasim Mohammed
 

On Wed, Oct 27, 2021 at 08:28 AM, PierreGondois wrote:
Hi Khasim,

+ Sami

Thanks for the new patch-set, everything looks good to me:

Reviewed-by: Pierre Gondois <pierre.gondois@...>
Hi all,

As we have entered the soft freeze phase, I would like to provide additional info to the edk2 community about the following series (7 Patches version 5) of the patches for N1SDP. These patches were already reviewed a few weeks ago, with reviewed-by as shown above, these patches are important for N1SDP platform as they provide all the functionality required to get the N1SDP platform booting various OS distributions like busybox, poky and ubuntu with ACPI tables.

These patches are independent of any other platform and specific to only N1SDP hardware thereby it would not break any other platform or existing features in the edk2 software. 

I request you to consider these patches and the merge request and merge the patches to appropriate repository.

Thanks.

Regards,
Khasim

Just a reminder for Sami about the _OSC method:
https://edk2.groups.io/g/devel/message/82724

Regards,

Pierre


On 10/26/21 18:39, Khasim Mohammed via groups.io wrote:
This patch adds missing documentation for few of the functions
and fixes few formatting changes.

Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../Library/PlatformLib/PlatformLib.c | 46 +++++++++++++++++--
1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
index f722080e56..c0effd37f3 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/

#include <Library/ArmPlatformLib.h>
@@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] = {
{ 0x1, 0x1 } // Cluster 1, Core 1
};

+/**
+ Return the current Boot Mode.
+
+ @return The boot reason on the platform.
+
+**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
@@ -25,6 +31,16 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}

+/**
+ Initialize controllers that must be setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or
+ ArmPlatformPkg/Pei/PlatformPeim in the PEI phase.
+
+ @param[in] MpId Processor ID
+ @retval RETURN_SUCCESS
+
+**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
@@ -33,6 +49,17 @@ ArmPlatformInitialize (
return RETURN_SUCCESS;
}

+/**
+ Populate the Platform core information.
+
+ This function populates the ARM_MP_CORE_INFO_PPI with information
+ about the cores.
+
+ @param[out] CoreCount Number of cores
+ @param[out] ArmCoreTable Table containing information about the cores
+ @retval EFI_SUCCESS
+
+**/
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
@@ -56,6 +83,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
}
};

+/**
+ Return the Platform specific PPIs
+
+ This function exposes the N1Sdp Specific PPIs.
+
+ @param[out] PpiListSize Size in Bytes of the Platform PPI List
+ @param[out] PpiList Platform PPI List
+
+**/
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,


Re: [PATCH v5 4/7] Platform/ARM/N1Sdp: Enable N1Sdp platform specific configurations

Sami Mujawar
 

Hi Khasim,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 05/11/2021 02:21 PM, Khasim Mohammed via groups.io wrote:
This patch adds PCDs and updates the fdf file for N1Sdp
platform specific configurations.

Signed-off-by: Deepak Pandey <Deepak.Pandey@...>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 98 ++++++++++++++++++++++++++++
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 33 +++++++++-
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 13 +++-
3 files changed, 140 insertions(+), 4 deletions(-)
create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dec

diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
new file mode 100644
index 0000000000..d56891b985
--- /dev/null
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -0,0 +1,98 @@
+## @file
+# Describes the N1Sdp configuration.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = N1SdpPlatform
+ PACKAGE_GUID = 29aacb23-61e8-4fe2-8a06-793537cd26e9
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+
+[LibraryClasses]
+ ArmPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+
+[Guids.common]
+ gArmN1SdpTokenSpaceGuid = { 0xd8f1624a, 0x98c1, 0x4f64, { 0xa6, 0x41, 0x19, 0x5e, 0xb5, 0x3b, 0x26, 0x0f } }
+
+[PcdsFixedAtBuild]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
+
+ # PCIe
+ gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
+
+ # External memory
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
+
+[PcdsFeatureFlag.common]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000003
+
+[PcdsFixedAtBuild.common]
+ # CoreSight Debug and Trace components
+ # CoreSight ETMs
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0Base|0x402040000|UINT64|0x0000002D
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0MaxBase|0x402040FFF|UINT64|0x0000002E
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1Base|0x402140000|UINT64|0x0000002F
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1MaxBase|0x402140FFF|UINT64|0x00000030
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2Base|0x403040000|UINT64|0x00000031
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2MaxBase|0x403040FFF|UINT64|0x00000032
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3Base|0x403140000|UINT64|0x00000033
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3MaxBase|0x403140FFF|UINT64|0x00000034
+
+ # CoreSight TMC (ETRs/ETFs/ETBs)
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0Base|0x400410000|UINT64|0x00000035
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0MaxBase|0x400410FFF|UINT64|0x00000036
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1Base|0x400420000|UINT64|0x00000037
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1MaxBase|0x400420FFF|UINT64|0x00000038
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2Base|0x400010000|UINT64|0x00000039
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2MaxBase|0x400010FFF|UINT64|0x0000003A
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrBase|0x400120000|UINT64|0x00000043
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrMaxBase|0x400120FFF|UINT64|0x00000044
+
+ # CoreSight Dynamic Funnel(s)
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0Base|0x4000B0000|UINT64|0x0000003B
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0MaxBase|0x4000B0FFF|UINT64|0x0000003C
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1Base|0x4000A0000|UINT64|0x0000003D
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1MaxBase|0x4000A0FFF|UINT64|0x0000003E
+
+ # CoreSight Dynamic Replicator(s)
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorBase|0x400110000|UINT64|0x0000003F
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorMaxBase|0x400110FFF|UINT64|0x00000040
+
+ # CoreSight TPIU
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuBase|0x400130000|UINT64|0x00000041
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase|0x400130FFF|UINT64|0x00000042
+
+ # CoreSight STM and STM Stimulus
+ gArmN1SdpTokenSpaceGuid.PcdCsStmBase|0x400800000|UINT64|0x00000045
+ gArmN1SdpTokenSpaceGuid.PcdCsStmMaxBase|0x400800FFF|UINT64|0x00000046
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusBase|0x4D000000|UINT32|0x00000047
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusSize|0x1000000|UINT32|0x00000048
+
+ # CoreSight Components' Size
+ #
+ # Newton TRMs specify the size for these coresight components as 64K.
+ # The actual size is just 4K though 64K is reserved. Access to the
+ # unmapped reserved region results in a DECERR response.
+ #
+ gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
+
+ # Remote Chip PCIe
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 61e7a909f8..f76b9eb0ce 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -1,8 +1,14 @@
+## @file
+# Component Description File for N1Sdp
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# This provides platform specific component descriptions and libraries that
+# conform to EFI/Framework standards.
#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
################################################################################
#
@@ -33,6 +39,9 @@
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ # file explorer library support
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
[LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -71,6 +80,9 @@
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+!endif
[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -82,11 +94,16 @@
################################################################################
[PcdsFeatureFlag.common]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdVFPEnabled|1
+ # RAM Disk
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000
+
# Stacks for MPCores in Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
@@ -99,6 +116,9 @@
# Secondary DDR memory
gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0x8080000000
+ # External memory
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000
+
# GIC Base Addresses
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
@@ -198,6 +218,9 @@
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}
+ # Platform driver
+ Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
+
# Human Interface Support
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
@@ -236,6 +259,9 @@
# SATA Controller
MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ # NVMe boot devices
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
# Usb Support
MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
@@ -244,3 +270,6 @@
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ # RAM Disk
+ MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
index c4e1f7b4b8..6b097438ad 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
@@ -1,8 +1,10 @@
+## @file
+# FDF file of N1Sdp
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+##
################################################################################
#
@@ -109,6 +111,9 @@ READ_LOCK_STATUS = TRUE
# SATA Controller
INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ # NVMe boot devices
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
# Usb Support
INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
@@ -137,10 +142,14 @@ READ_LOCK_STATUS = TRUE
# FV FileSystem
INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+ INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
# UEFI applications
INF ShellPkg/Application/Shell/Shell.inf
+ # Platform driver
+ INF Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
+
# Bds
INF MdeModulePkg/Application/UiApp/UiApp.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf


Re: [PATCH v5 3/7] Platform/ARM/N1Sdp: Introduce platform DXE driver

Sami Mujawar
 

Hi Khasim,

Other than a few minor code alignment issues (which I will fix before pushing), this patch looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 05/11/2021 02:21 PM, Khasim Mohammed via groups.io wrote:
Add an initial platform DXE driver and support for ramdisk devices.

Signed-off-by: Deepak Pandey <Deepak.Pandey@...>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../N1Sdp/Drivers/PlatformDxe/PlatformDxe.c | 59 +++++++++++++++++++
.../N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf | 47 +++++++++++++++
2 files changed, 106 insertions(+)
create mode 100644 Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf

diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 0000000000..3f975fa5ac
--- /dev/null
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,59 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/RamDisk.h>
+
+/**
+ Entrypoint of Platform Dxe Driver
+
+ @param ImageHandle[in] The firmware allocated handle for the EFI image.
+ @param SystemTable[in] A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The RAM disk has been registered.
+ @retval EFI_NOT_FOUND No RAM disk protocol instances were found.
+ @retval EFI_UNSUPPORTED The ImageType is not supported.
+ @retval Others Unexpected error happened.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmN1SdpEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_RAM_DISK_PROTOCOL *RamDisk;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = EFI_UNSUPPORTED;
+ if (FeaturePcdGet (PcdRamDiskSupported)) {
+ Status = gBS->LocateProtocol (&gEfiRamDiskProtocolGuid, NULL,
+ (VOID**) &RamDisk);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Couldn't find the RAM Disk protocol - %r\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ Status = RamDisk->Register (
+ (UINTN)PcdGet32 (PcdRamDiskBase),
+ (UINTN)PcdGet32 (PcdRamDiskSize),
+ &gEfiVirtualCdGuid,
+ NULL,
+ &DevicePath
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n",
+ __FUNCTION__, Status));
+ }
+ }
+ return Status;
+}
diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 0000000000..d74f09b46c
--- /dev/null
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,47 @@
+## @file
+# Platform DXE driver for N1Sdp
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 116dcefb-aa53-46aa-81cd-49581684db55
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmN1SdpEntryPoint
+
+[Sources.common]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
+
+[LibraryClasses]
+ HobLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiRamDiskProtocolGuid
+
+[Guids]
+ gEfiVirtualCdGuid ## SOMETIMES_CONSUMES ## GUID
+
+[FeaturePcd]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported
+
+[FixedPcd]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize
+
+[Depex]
+ gEfiRamDiskProtocolGuid


Re: [PATCH v5 2/7] Silicon/ARM/NeoverseN1Soc: Define new PCDs and configure memory map

Sami Mujawar
 

Hi Khasim,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 05/11/2021 02:21 PM, Khasim Mohammed via groups.io wrote:
This patch introduces new PCDs required to enable
chip to chip interface and corresponding memory map is updated.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@...>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../Library/PlatformLib/PlatformLib.inf | 28 +++++--
.../Library/PlatformLib/PlatformLibMem.c | 84 ++++++++++++++++---
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 35 +++++++-
3 files changed, 125 insertions(+), 22 deletions(-)

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 166c9e0444..8e2154aadf 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -1,6 +1,7 @@
## @file
+# Platform Library for N1Sdp.
#
-# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -29,13 +30,17 @@
AArch64/Helper.S | GCC
[FixedPcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
@@ -45,7 +50,12 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
- gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
[Guids]
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index f9b3d03753..1c4a445c5e 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/
#include <Library/ArmPlatformLib.h>
@@ -13,7 +13,7 @@
#include <NeoverseN1Soc.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
/**
Returns the Virtual Memory Map of the platform.
@@ -21,21 +21,23 @@
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
on your platform.
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
- a Physical-to-Virtual Memory mapping. This array
- must be ended by a zero-filled entry.
+ @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
+ a Physical-to-Virtual Memory mapping. This array
+ must be ended by a zero-filled entry.
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
)
{
- UINTN Index = 0;
+ UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT64 DramBlock2Size;
+ UINT64 RemoteDdrSize;
+ Index = 0;
PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
@@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap (
FixedPcdGet64 (PcdDramBlock2Base),
DramBlock2Size);
+ if (PlatInfo->MultichipMode == 1) {
+ RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBase),
+ PcdGet64 (PcdSystemMemorySize)
+ );
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base),
+ RemoteDdrSize
+ );
+ }
+
ASSERT (VirtualMemoryMap != NULL);
Index = 0;
@@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // CCIX RC Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixRootPortConfigBaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX ECAM Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdCcixBusMax) -
+ FixedPcdGet32 (PcdCcixBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX MMIO32 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixMmio32Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX MMIO64 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdCcixMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// SubSystem Pheripherals - UART0
VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE;
VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE;
@@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ if (PlatInfo->MultichipMode == 1) {
+ //Remote DDR (2GB)
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
+
+ //Remote DDR
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].Length = RemoteDdrSize;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
+ }
+
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index 54b793a937..eea2d58402 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -1,5 +1,7 @@
+## @file
+# Describes the entire platform configuration.
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -33,8 +35,8 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000008
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000009
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000A
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000B
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000C
@@ -44,3 +46,30 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
+
+ # CCIX
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
+
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
+
+ # Remote Chip PCIe
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C


Re: [PATCH v5 1/7] Silicon/ARM/NeoverseN1Soc: Fix missing function documentation

Sami Mujawar
 

Hi Khasim,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar

On 05/11/2021 02:21 PM, Khasim Mohammed via groups.io wrote:
This patch adds missing documentation for few of the functions
and fixes few formatting changes.

Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@...>
---
.../Library/PlatformLib/PlatformLib.c | 46 +++++++++++++++++--
1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
index f722080e56..c0effd37f3 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/
#include <Library/ArmPlatformLib.h>
@@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] = {
{ 0x1, 0x1 } // Cluster 1, Core 1
};
+/**
+ Return the current Boot Mode.
+
+ @return The boot reason on the platform.
+
+**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
@@ -25,6 +31,16 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}
+/**
+ Initialize controllers that must be setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or
+ ArmPlatformPkg/Pei/PlatformPeim in the PEI phase.
+
+ @param[in] MpId Processor ID
+ @retval RETURN_SUCCESS
+
+**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
@@ -33,6 +49,17 @@ ArmPlatformInitialize (
return RETURN_SUCCESS;
}
+/**
+ Populate the Platform core information.
+
+ This function populates the ARM_MP_CORE_INFO_PPI with information
+ about the cores.
+
+ @param[out] CoreCount Number of cores
+ @param[out] ArmCoreTable Table containing information about the cores
+ @retval EFI_SUCCESS
+
+**/
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
@@ -56,6 +83,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
}
};
+/**
+ Return the Platform specific PPIs
+
+ This function exposes the N1Sdp Specific PPIs.
+
+ @param[out] PpiListSize Size in Bytes of the Platform PPI List
+ @param[out] PpiList Platform PPI List
+
+**/
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,


Re: The arm virtual machine displays problems in QXL during the UEFI phase

Lange Tang
 

Hi Gerd:
Thanks for your reply.
>1. I wonder why the device display be normal when it hung on bus=pci.8,addr=0x0, but it is abnormal when bus=pci.9,addr=0x1 or bus=pci.7,addr=0x0.

> Placing qxl behind a pci bridge is problematic too (even on x86).
> I'm surprised it works at all.  qxl needs io ports 0x01ce + 0x1cf for
> programming video modes in vga compatibility mode, and pci bridges
> typically don't pass that though.
>
> Maybe the working bridge got the 0x0000 -> 0x0fff io window assigned.
> Wouldn't happen on x86 because of the legacy hardware in the 0x000 ->
> 0x3ff range, but maybe it is used for pci-pci bridges on arm.
qxl device msg as follow,when it behind bus=pci.8,addr=0x0:
```
VGA compatible controller [0300]: Red Hat, Inc. QXL paravirtual graphic card [1b36:0100] (rev 05) (prog-if 00 [VGA controller])
        Subsystem: Red Hat, Inc. QEMU Virtual Machine [1af4:1100]
        Physical Slot: 0-8
        Flags: bus master, fast devsel, latency 0, IRQ 39
        Memory at 14000000 (32-bit, non-prefetchable) [size=64M]
        Memory at 10000000 (32-bit, non-prefetchable) [size=64M]
        Memory at 18000000 (32-bit, non-prefetchable) [size=8K]
        I/O ports at 0000 [virtual] [size=32]
        Expansion ROM at 18010000 [disabled] [size=64K]
        Kernel driver in use: qxl
        Kernel modules: qxl
```
his working bridge io window as follow:
```
PCI bridge [0604]: Red Hat, Inc. QEMU PCIe Root port [1b36:000c] (prog-if 00 [Normal decode])
        Flags: bus master, fast devsel, latency 0, IRQ 39
        Memory at 19440000 (32-bit, non-prefetchable) [size=4K]
        Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=0
        I/O behind bridge: 00000000-00000fff [size=4K]
        Memory behind bridge: 10000000-180fffff [size=129M]
        Prefetchable memory behind bridge: 0000008000b00000-0000008000cfffff [size=2M]
        Capabilities: [54] Express Root Port (Slot+), MSI 00
        Capabilities: [48] MSI-X: Enable+ Count=1 Masked-
        Capabilities: [40] Subsystem: Red Hat, Inc. Device [1b36:0000]
        Capabilities: [100] Advanced Error Reporting
        Capabilities: [148] Access Control Services
        Kernel driver in use: pcieport
```

qxl device msg as follow,when it behind bus=pci.9,addr=0x1:
```
VGA compatible controller [0300]: Red Hat, Inc. QXL paravirtual graphic card [1b36:0100] (rev 05) (prog-if 00 [VGA controller])
        Subsystem: Red Hat, Inc. QEMU Virtual Machine [1af4:1100]
        Physical Slot: 1
        Flags: fast devsel, IRQ 39
        Memory at 14000000 (32-bit, non-prefetchable) [size=64M]
        Memory at 10000000 (32-bit, non-prefetchable) [size=64M]
        Memory at 18000000 (32-bit, non-prefetchable) [size=8K]
        I/O ports at 2000 [size=32]
        Expansion ROM at 18010000 [disabled] [size=64K]
        Kernel driver in use: qxl
        Kernel modules: qxl
```
his working bridge io window as follow:
``` PCI bridge [0604]: Red Hat, Inc. Device [1b36:000e] (prog-if 00 [Normal decode]) Physical Slot: 0-6 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 52 Memory at 18100000 (64-bit, non-prefetchable) [size=256] Bus: primary=07, secondary=08, subordinate=08, sec-latency=0 I/O behind bridge: 00002000-00002fff [size=4K] Memory behind bridge: 10000000-180fffff [size=129M] Prefetchable memory behind bridge: [disabled] Capabilities: [8c] MSI: Enable+ Count=1/1 Maskable+ 64bit+ Capabilities: [84] Power Management version 3 Capabilities: [48] Express PCI-Express to PCI/PCI-X Bridge, MSI 00 Capabilities: [40] Hot-plug capable Capabilities: [100] Advanced Error Reporting Kernel driver in use: shpchp ```
From the above point of view, your speculation is right. excellent!
In this way, if a QXL device wants to work on ARM, the io window of the bridge it is mounted on must be allocated as 00000000-00000fff [size=4K].
In my work, by modifying the qemu code, the io window of the bridge mounted with the qxl device is fixed to 00000000-00000fff to solve this problem. what do you think?
take care
Lange








At 2021-11-03 14:03:22, "Gerd Hoffmann" <kraxel@...> wrote: >On Wed, Nov 03, 2021 at 09:46:01AM +0800, Lange Tang wrote: >> Hi Gerd: >> Thanks for your reply. In fact, I have no choice, only QXL in my work. >> 1. I wonder why the device display be normal when it hung on bus=pci.8,addr=0x0, but it is abnormal when bus=pci.9,addr=0x1 or bus=pci.7,addr=0x0. > >Placing qxl behind a pci bridge is problematic too (even on x86). >I'm surprised it works at all. qxl needs io ports 0x01ce + 0x1cf for >programming video modes in vga compatibility mode, and pci bridges >typically don't pass that though. > >Maybe the working bridge got the 0x0000 -> 0x0fff io window assigned. >Wouldn't happen on x86 because of the legacy hardware in the 0x000 -> >0x3ff range, but maybe it is used for pci-pci bridges on arm. > >> 2. Why cache properties are going to cause QXL display abnormal on >> ARM. Are there any links or materials? Thanks. > >The fundamental issue is that the pci memory br for vram is virtual. >The guest maps it as io memory, but it actually is normal ram, so guest >and host map the same memory with different attributes. That just >doesn't work on arm and results in display corruption when actually >running on arm hardware (when running in emulation, for example using >qemu on a x86 machine, this doesn't happen). > >This is the reason why QemuVideoDxe is not compiled into ArmVirt. > >take care, > Gerd > > > > >


 


Re: [PATCH v2] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bits

Wu, Hao A
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
ian.chiu@...
Sent: Friday, November 5, 2021 5:46 PM
To: devel@edk2.groups.io
Cc: Chiu, Ian <Ian.chiu@...>; Chiu, Ian <Ian.chiu@...>; Chu,
Maggie <maggie.chu@...>; Ni, Ray <ray.ni@...>; Wu, Hao A
<hao.a.wu@...>
Subject: [edk2-devel] [PATCH v2] MdeModulePkg\UfsBlockIoPei: UFS MMIO
address size support both 32/64 bits

From: Ian Chiu <Ian.chiu@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3703

MMIO base address size will overflow while finding two or more Host
controller in the system. Correct it and support 32 and 64 bits address
space.

Reviewed-by: Hao A Wu <hao.a.wu@...>

Best Regards,
Hao Wu



Signed-off-by: Ian Chiu <ian.chiu@...>
Cc: Maggie Chu <maggie.chu@...>
Cc: Ray Ni <ray.ni@...>
Cc: Hao A Wu <hao.a.wu@...>
---
MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 47
+++++++++++++++++++-
1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
index 447a05b5b2..86f1529eec 100644
--- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
+++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
@@ -76,6 +76,8 @@ InitializeUfsHcPeim (
UINT16 Device;

UINT16 Function;

UINT32 Size;

+ UINT64 MmioSize;

+ UINT32 BarAddr;

UINT8 SubClass;

UINT8 BaseClass;

UFS_HC_PEI_PRIVATE_DATA *Private;

@@ -106,6 +108,7 @@ InitializeUfsHcPeim (
Private->PpiList = mPpiList;

Private->PpiList.Ppi = &Private->UfsHostControllerPpi;



+ BarAddr = PcdGet32 (PcdUfsPciHostControllerMmioBase);

for (Bus = 0; Bus < 256; Bus++) {

for (Device = 0; Device < 32; Device++) {

for (Function = 0; Function < 8; Function++) {

@@ -119,17 +122,57 @@ InitializeUfsHcPeim (
PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER |
EFI_PCI_COMMAND_MEMORY_SPACE));

PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);

Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET));

+

+ switch (Size & 0x07) {

+ case 0x0:

+ //

+ // Memory space: anywhere in 32 bit address space

+ //

+ MmioSize = (~(Size & 0xFFFFFFF0)) + 1;

+ break;

+ case 0x4:

+ //

+ // Memory space: anywhere in 64 bit address space

+ //

+ MmioSize = Size & 0xFFFFFFF0;

+ PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);

+ Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET + 4));

+

+ //

+ // Fix the length to support some specific 64 bit BAR

+ //

+ Size |= ((UINT32)(-1) << HighBitSet32 (Size));

+

+ //

+ // Calculate the size of 64bit bar

+ //

+ MmioSize |= LShiftU64 ((UINT64) Size, 32);

+ MmioSize = (~(MmioSize)) + 1;

+

+ //

+ // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit
BAR.

+ //

+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET + 4), 0);

+ break;

+ default:

+ //

+ // Unknown BAR type

+ //

+ ASSERT (FALSE);

+ continue;

+ };

//

// Assign resource to the Ufs Pci host controller's MMIO BAR.

// Enable the Ufs Pci host controller by setting BME and MSE bits of
PCI_CMD register.

//

- PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32
(PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));

+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_BASE_ADDRESSREG_OFFSET), BarAddr);

PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function,
PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER |
EFI_PCI_COMMAND_MEMORY_SPACE));

//

// Record the allocated Mmio base address.

//

- Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32
(PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs;

+ Private->UfsHcPciAddr[Private->TotalUfsHcs] = BarAddr;

Private->TotalUfsHcs++;

+ BarAddr += (UINT32)MmioSize;

ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);

}

}

--
2.16.2.windows.1



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[PATCH V3 3/3] OvmfPkg: Move LocalApicTimerDxe to UefiCpuPkg

Min Xu
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711

OvmfPkg.dec is removed from [Packages] because it doesn't depend
on OvmfPkg. LocalApicTimerDxe is moved to UefiCpuPkg.

Cc: Jiewen Yao <jiewen.yao@...>
Cc: Gerd Hoffmann <kraxel@...>
Cc: Anthony Perard <anthony.perard@...>
Cc: Julien Grall <julien@...>
Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Signed-off-by: Min Xu <min.m.xu@...>
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +-
OvmfPkg/AmdSev/AmdSevX64.fdf | 2 +-
OvmfPkg/Microvm/MicrovmX64.dsc | 2 +-
OvmfPkg/Microvm/MicrovmX64.fdf | 2 +-
OvmfPkg/OvmfPkgIa32.dsc | 2 +-
OvmfPkg/OvmfPkgIa32.fdf | 2 +-
OvmfPkg/OvmfPkgIa32X64.dsc | 2 +-
OvmfPkg/OvmfPkgIa32X64.fdf | 2 +-
OvmfPkg/OvmfPkgX64.dsc | 2 +-
OvmfPkg/OvmfPkgX64.fdf | 2 +-
OvmfPkg/OvmfXen.dsc | 2 +-
OvmfPkg/OvmfXen.fdf | 2 +-
.../LocalApicTimerDxe/LocalApicTimerDxe.c | 0
.../LocalApicTimerDxe/LocalApicTimerDxe.h | 0
.../LocalApicTimerDxe/LocalApicTimerDxe.inf | 6 ++++--
15 files changed, 16 insertions(+), 14 deletions(-)
rename {OvmfPkg => UefiCpuPkg}/LocalApicTimerDxe/LocalApicTimerDxe.c (100%)
rename {OvmfPkg => UefiCpuPkg}/LocalApicTimerDxe/LocalApicTimerDxe.h (100%)
rename {OvmfPkg => UefiCpuPkg}/LocalApicTimerDxe/LocalApicTimerDxe.inf (79%)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index 88c51dfe8337..888fc24f1b58 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -674,7 +674,7 @@
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
diff --git a/OvmfPkg/AmdSev/AmdSevX64.fdf b/OvmfPkg/AmdSev/AmdSevX64.fdf
index 7489b04198fe..659810f96bec 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.fdf
+++ b/OvmfPkg/AmdSev/AmdSevX64.fdf
@@ -208,7 +208,7 @@ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc
index 1a0e848f8356..fcb8b571a041 100644
--- a/OvmfPkg/Microvm/MicrovmX64.dsc
+++ b/OvmfPkg/Microvm/MicrovmX64.dsc
@@ -656,7 +656,7 @@

MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
diff --git a/OvmfPkg/Microvm/MicrovmX64.fdf b/OvmfPkg/Microvm/MicrovmX64.fdf
index ac9efba26811..d02e88e2a48e 100644
--- a/OvmfPkg/Microvm/MicrovmX64.fdf
+++ b/OvmfPkg/Microvm/MicrovmX64.fdf
@@ -215,7 +215,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index d0e9f3ca05f6..f8c8ef1e58be 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -763,7 +763,7 @@
OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index b7b35a3a490a..321d4a871afa 100644
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -218,7 +218,7 @@ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index d3531d388e24..4de4ed21a5ca 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -777,7 +777,7 @@
OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index 986228a44c78..10e97c35001f 100644
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -222,7 +222,7 @@ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index c6ee624fc738..57b0c3c10826 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -775,7 +775,7 @@
OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index 99339e73bb51..b52c43127845 100644
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -238,7 +238,7 @@ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF OvmfPkg/8254TimerDxe/8254Timer.inf
!else
- INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc
index 7c4c5412d102..d4a9e8f87def 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -551,7 +551,7 @@
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+ UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf
index 196853740753..76934d354fa6 100644
--- a/OvmfPkg/OvmfXen.fdf
+++ b/OvmfPkg/OvmfXen.fdf
@@ -298,7 +298,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+INF UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c b/UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
similarity index 100%
rename from OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
rename to UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h b/UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
similarity index 100%
rename from OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
rename to UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf b/UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
similarity index 79%
rename from OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
rename to UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
index 3ad28a148c5b..4f2b4db9e5dc 100644
--- a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+++ b/UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
@@ -1,6 +1,9 @@
## @file
# Local APIC timer driver that provides Timer Arch protocol.
-# PcdFSBClock is defined in MdePkg and it should be set by the consumer.
+#
+# This driver is to support fixed frequency. If a real platform happens
+# to have fixed frequency, then it can be used. In this case the consumer
+# should set PcdFSBClock which is defined in MdePkg.
#
# Copyright (c) 2005 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2019, Citrix Systems, Inc.
@@ -21,7 +24,6 @@
[Packages]
MdePkg/MdePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
- OvmfPkg/OvmfPkg.dec

[LibraryClasses]
UefiBootServicesTableLib
--
2.29.2.windows.2


[PATCH V3 2/3] OvmfPkg: Switch timer in build time for OvmfPkg

Min Xu
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711

Discussion in https://bugzilla.tianocore.org/show_bug.cgi?id=1496 shows
that 8254TimerDxe was not written for OVMF. It was moved over from
PcAtChipsetPkg to OvmfPkg in 2019. Probably because OVMF was the only
user left.

Most likely the reason OVMF used 8254TimerDxe initially was that it could
just use the existing driver in PcAtChipsetPkg. And it simply hasn't
been changed ever.

CSM support was moved in 2019 too. (CSM support depends on 8254/8259
drivers). So 8254TimerDxe will be used when CSM_ENABLE=TRUE.

There are 4 .dsc which include the 8254Timer.
- OvmfPkg/AmdSev/AmdSevX64.dsc
- OvmfPkg/OvmfPkgIa32.dsc
- OvmfPkg/OvmfPkgIa32X64.dsc
- OvmfPkg/OvmfPkgX64.dsc

For the three OvmfPkg* configs using 8254TimerDxe with CSM_ENABLE=TRUE
and LapicTimerDxe otherwise.

For the AmdSev config it doesn't make sense to support a CSM. So use
the lapic timer unconditionally.

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Brijesh Singh <brijesh.singh@...>
Cc: Erdem Aktas <erdemaktas@...>
Cc: James Bottomley <jejb@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Gerd Hoffmann <kraxel@...>
Suggested-by: Gerd Hoffmann <kraxel@...>
Signed-off-by: Min Xu <min.m.xu@...>
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 5 +++--
OvmfPkg/AmdSev/AmdSevX64.fdf | 3 +--
OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c | 4 ++--
OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgIa32.fdf | 8 ++++++--
OvmfPkg/OvmfPkgIa32X64.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgIa32X64.fdf | 8 ++++++--
OvmfPkg/OvmfPkgX64.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgX64.fdf | 8 ++++++--
10 files changed, 52 insertions(+), 15 deletions(-)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index 5ee54451169b..88c51dfe8337 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -579,6 +579,8 @@
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
!endif

+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
[PcdsDynamicHii]
!if $(TPM_ENABLE) == TRUE && $(TPM_CONFIG_ENABLE) == TRUE
gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
@@ -670,10 +672,9 @@
}

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/8259InterruptControllerDxe/8259.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
- OvmfPkg/8254TimerDxe/8254Timer.inf
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
diff --git a/OvmfPkg/AmdSev/AmdSevX64.fdf b/OvmfPkg/AmdSev/AmdSevX64.fdf
index 56626098862c..7489b04198fe 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.fdf
+++ b/OvmfPkg/AmdSev/AmdSevX64.fdf
@@ -206,10 +206,9 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF OvmfPkg/8254TimerDxe/8254Timer.inf
+INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
index 5f57fd69d4fb..fa91a4b2ad90 100644
--- a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
+++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
@@ -173,7 +173,7 @@ TimerDriverSetTimerPeriod (
//
DisableApicTimerInterrupt();
} else {
- TimerFrequency = PcdGet32(PcdFSBClock) / DivideValue;
+ TimerFrequency = PcdGet32(PcdFSBClock) / (UINT32)DivideValue;

//
// Convert TimerPeriod into local APIC counts
@@ -193,7 +193,7 @@ TimerDriverSetTimerPeriod (
//
// Program the timer with the new count value
//
- InitializeApicTimer(DivideValue, TimerCount, TRUE, LOCAL_APIC_TIMER_VECTOR);
+ InitializeApicTimer(DivideValue, (UINT32)TimerCount, TRUE, LOCAL_APIC_TIMER_VECTOR);

//
// Enable timer interrupt
diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
index 63b75b75c921..3ad28a148c5b 100644
--- a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
@@ -1,5 +1,6 @@
## @file
# Local APIC timer driver that provides Timer Arch protocol.
+# PcdFSBClock is defined in MdePkg and it should be set by the consumer.
#
# Copyright (c) 2005 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2019, Citrix Systems, Inc.
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 6a5be97c059d..d0e9f3ca05f6 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -650,6 +650,10 @@
gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01
gEfiNetworkPkgTokenSpaceGuid.PcdIPv6PXESupport|0x01

+!if $(CSM_ENABLE) == FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+!endif
+
[PcdsDynamicHii]
!if $(TPM_ENABLE) == TRUE && $(TPM_CONFIG_ENABLE) == TRUE
gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
@@ -753,10 +757,14 @@
}

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/8259InterruptControllerDxe/8259.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
+!ifdef $(CSM_ENABLE)
+ OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index 775ea2d71098..b7b35a3a490a 100644
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -212,10 +212,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!ifdef $(CSM_ENABLE)
+ INF OvmfPkg/8259InterruptControllerDxe/8259.inf
+ INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 71227d1b709a..d3531d388e24 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -658,6 +658,10 @@
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
!endif

+!if $(CSM_ENABLE) == FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+!endif
+
[PcdsDynamicDefault.X64]
# IPv4 and IPv6 PXE Boot support.
gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01
@@ -767,10 +771,14 @@
}

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/8259InterruptControllerDxe/8259.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
+!ifdef $(CSM_ENABLE)
+ OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index 9d8695922f97..986228a44c78 100644
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -216,10 +216,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!ifdef $(CSM_ENABLE)
+ INF OvmfPkg/8259InterruptControllerDxe/8259.inf
+ INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 52f7598cf1c7..c6ee624fc738 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -662,6 +662,10 @@
gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01
gEfiNetworkPkgTokenSpaceGuid.PcdIPv6PXESupport|0x01

+!if $(CSM_ENABLE) == FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+!endif
+
[PcdsDynamicHii]
!if $(TPM_ENABLE) == TRUE && $(TPM_CONFIG_ENABLE) == TRUE
gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
@@ -765,10 +769,14 @@
}

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/8259InterruptControllerDxe/8259.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
+!ifdef $(CSM_ENABLE)
+ OvmfPkg/8259InterruptControllerDxe/8259.inf
OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index b6cc3cabdd69..99339e73bb51 100644
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -232,10 +232,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/8259InterruptControllerDxe/8259.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
-INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!ifdef $(CSM_ENABLE)
+ INF OvmfPkg/8259InterruptControllerDxe/8259.inf
+ INF OvmfPkg/8254TimerDxe/8254Timer.inf
+!else
+ INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
+!endif
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
--
2.29.2.windows.2


[PATCH V3 1/3] OvmfPkg: Rename XenTimerDxe to LocalApicTimerDxe

Min Xu
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711

XenTimerDxe is a local Apic timer driver and it has nothing to do
with Xen. So rename it to LocalApicTimerDxe.

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Brijesh Singh <brijesh.singh@...>
Cc: Erdem Aktas <erdemaktas@...>
Cc: James Bottomley <jejb@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Gerd Hoffmann <kraxel@...>
Cc: Anthony Perard <anthony.perard@...>
Cc: Julien Grall <julien@...>
Signed-off-by: Min Xu <min.m.xu@...>
---
.../XenTimerDxe.c => LocalApicTimerDxe/LocalApicTimerDxe.c} | 3 +--
.../XenTimerDxe.h => LocalApicTimerDxe/LocalApicTimerDxe.h} | 4 ++--
.../LocalApicTimerDxe.inf} | 6 +++---
OvmfPkg/Microvm/MicrovmX64.dsc | 2 +-
OvmfPkg/Microvm/MicrovmX64.fdf | 2 +-
OvmfPkg/OvmfXen.dsc | 2 +-
OvmfPkg/OvmfXen.fdf | 2 +-
7 files changed, 10 insertions(+), 11 deletions(-)
rename OvmfPkg/{XenTimerDxe/XenTimerDxe.c => LocalApicTimerDxe/LocalApicTimerDxe.c} (96%)
rename OvmfPkg/{XenTimerDxe/XenTimerDxe.h => LocalApicTimerDxe/LocalApicTimerDxe.h} (96%)
rename OvmfPkg/{XenTimerDxe/XenTimerDxe.inf => LocalApicTimerDxe/LocalApicTimerDxe.inf} (86%)

diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.c b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
similarity index 96%
rename from OvmfPkg/XenTimerDxe/XenTimerDxe.c
rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
index 0bec59382b0a..5f57fd69d4fb 100644
--- a/OvmfPkg/XenTimerDxe/XenTimerDxe.c
+++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c
@@ -8,7 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

**/

-#include "XenTimerDxe.h"
+#include "LocalApicTimerDxe.h"

//
// The handle onto which the Timer Architectural Protocol will be installed
@@ -353,4 +353,3 @@ TimerDriverInitialize (

return Status;
}
-
diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.h b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
similarity index 96%
rename from OvmfPkg/XenTimerDxe/XenTimerDxe.h
rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
index e0a3d95fd063..7d4802f8050f 100644
--- a/OvmfPkg/XenTimerDxe/XenTimerDxe.h
+++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h
@@ -7,8 +7,8 @@ Copyright (c) 2019, Citrix Systems, Inc.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

-#ifndef _TIMER_H_
-#define _TIMER_H_
+#ifndef LOCAL_APIC_TIMER_H_
+#define LOCAL_APIC_TIMER_H_

#include <PiDxe.h>

diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.inf b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
similarity index 86%
rename from OvmfPkg/XenTimerDxe/XenTimerDxe.inf
rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
index add1d01bbf9c..63b75b75c921 100644
--- a/OvmfPkg/XenTimerDxe/XenTimerDxe.inf
+++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
@@ -10,7 +10,7 @@

[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = XenTimerDxe
+ BASE_NAME = LocalApicTimerDxe
FILE_GUID = 52fe8196-f9de-4d07-b22f-51f77a0e7c41
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
@@ -30,8 +30,8 @@
LocalApicLib

[Sources]
- XenTimerDxe.h
- XenTimerDxe.c
+ LocalApicTimerDxe.h
+ LocalApicTimerDxe.c

[Protocols]
gEfiCpuArchProtocolGuid ## CONSUMES
diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc
index 617f92539518..1a0e848f8356 100644
--- a/OvmfPkg/Microvm/MicrovmX64.dsc
+++ b/OvmfPkg/Microvm/MicrovmX64.dsc
@@ -656,7 +656,7 @@

MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/XenTimerDxe/XenTimerDxe.inf
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
diff --git a/OvmfPkg/Microvm/MicrovmX64.fdf b/OvmfPkg/Microvm/MicrovmX64.fdf
index 6314014f3de7..ac9efba26811 100644
--- a/OvmfPkg/Microvm/MicrovmX64.fdf
+++ b/OvmfPkg/Microvm/MicrovmX64.fdf
@@ -215,7 +215,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/XenTimerDxe/XenTimerDxe.inf
+INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf
diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc
index a31519e356b7..7c4c5412d102 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -551,7 +551,7 @@
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf

MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
- OvmfPkg/XenTimerDxe/XenTimerDxe.inf
+ OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf
index 8b5823555937..196853740753 100644
--- a/OvmfPkg/OvmfXen.fdf
+++ b/OvmfPkg/OvmfXen.fdf
@@ -298,7 +298,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF OvmfPkg/XenTimerDxe/XenTimerDxe.inf
+INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
--
2.29.2.windows.2


[PATCH V3 0/3] Rename XenTimerDxe to LocalApicTimerDxe

Min Xu
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711

XenTimerDxe is a local Apic timer driver and it has nothing to do
with Xen. So rename it to LocalApicTimerDxe.

After renaming, LocalApicTimerDxe is used in OvmfPkg if CSM_ENABLE=FALSE.
Otherwise 8254 timer is used.

Since LocalApicTimerDxe doesn't depend on OvmfPkg, so it is moved to
UefiCpuPkg.

Patch #1:
Rename XenTimerDxe to LocalApicTimerDxe

Patch #2:
Switch timer in build time for OvmfPkg. If CSM_ENABLE=TRUE, 8254 timer
is used, otherwise the timer is LocalApicTimerDxe.

Patch #3:
Move LocalApicTimerDxe from OvmfPkg to UefiCpuPkg.

Code at: https://github.com/mxu9/edk2/tree/ovmf_lapic_timer.v3

v3 changes:
- Move LocalApicTimerDxe to UefiCpuPkg
- Fix the errors in v2 patch-1 that OvmfXen.dsc / .fdf and
MicrovmX64.dsc / .fdf are not updated for new name.
- Add XenTimerDxe reviewers.

v2 changes:
- Add gEfiMdePkgTokenSpaceGuid.PcdFSBClock in *.dsc

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Brijesh Singh <brijesh.singh@...>
Cc: Erdem Aktas <erdemaktas@...>
Cc: James Bottomley <jejb@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Gerd Hoffmann <kraxel@...>
Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Signed-off-by: Min Xu <min.m.xu@...>

Min Xu (3):
OvmfPkg: Rename XenTimerDxe to LocalApicTimerDxe
OvmfPkg: Switch timer in build time for OvmfPkg
OvmfPkg: Move LocalApicTimerDxe to UefiCpuPkg

OvmfPkg/AmdSev/AmdSevX64.dsc | 5 +++--
OvmfPkg/AmdSev/AmdSevX64.fdf | 3 +--
OvmfPkg/Microvm/MicrovmX64.dsc | 2 +-
OvmfPkg/Microvm/MicrovmX64.fdf | 2 +-
OvmfPkg/OvmfPkgIa32.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgIa32.fdf | 8 ++++++--
OvmfPkg/OvmfPkgIa32X64.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgIa32X64.fdf | 8 ++++++--
OvmfPkg/OvmfPkgX64.dsc | 10 +++++++++-
OvmfPkg/OvmfPkgX64.fdf | 8 ++++++--
OvmfPkg/OvmfXen.dsc | 2 +-
OvmfPkg/OvmfXen.fdf | 2 +-
.../LocalApicTimerDxe/LocalApicTimerDxe.c | 7 +++----
.../LocalApicTimerDxe/LocalApicTimerDxe.h | 4 ++--
.../LocalApicTimerDxe/LocalApicTimerDxe.inf | 11 +++++++----
15 files changed, 65 insertions(+), 27 deletions(-)
rename OvmfPkg/XenTimerDxe/XenTimerDxe.c => UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.c (95%)
rename OvmfPkg/XenTimerDxe/XenTimerDxe.h => UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.h (96%)
rename OvmfPkg/XenTimerDxe/XenTimerDxe.inf => UefiCpuPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf (72%)

--
2.29.2.windows.2


Re: 回复: [PATCH v1 1/1] MdeModulePkg/XhciSched: Fix missing DEBUG arguments

Wu, Hao A
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Thursday, November 4, 2021 2:00 PM
To: mikuback@...; devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>;
Ni, Ray <ray.ni@...>
Subject: [edk2-devel] 回复: [PATCH v1 1/1] MdeModulePkg/XhciSched: Fix
missing DEBUG arguments

Reviewed-by: Liming Gao <gaoliming@...>

-----邮件原件-----
发件人: mikuback@... <mikuback@...>
发送时间: 2021年11月3日 23:16
收件人: devel@edk2.groups.io
抄送: Jian J Wang <jian.j.wang@...>; Liming Gao
<gaoliming@...>; Hao A Wu <hao.a.wu@...>; Ray Ni
<ray.ni@...>
主题: [PATCH v1 1/1] MdeModulePkg/XhciSched: Fix missing DEBUG
arguments

From: Michael Kubacki <michael.kubacki@...>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3662

Two DEBUG macros in XhciDxe/XhciSched.c are missing the argument that
should be passed for the print specifier.

In addition, this change updates the print level to "DEBUG_ERROR"
and prints the status as well.

Cc: Jian J Wang <jian.j.wang@...>
Cc: Liming Gao <gaoliming@...>
Cc: Hao A Wu <hao.a.wu@...>
Cc: Ray Ni <ray.ni@...>
Signed-off-by: Michael Kubacki <michael.kubacki@...>
---
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 7cbc9a8502ea..6fcd2be6277c 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2299,7 +2299,7 @@ XhcInitializeDeviceSlot (
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n",
DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
- DEBUG ((DEBUG_INFO, " Address %d assigned unsuccessfully\n"));
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned
successfully. Status = %r\n", SlotId, Status));
XhcDisableSlotCmd (Xhc, SlotId);
}

@@ -2512,7 +2512,7 @@ XhcInitializeDeviceSlot64 (
DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n",
DeviceAddress));
Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
} else {
- DEBUG ((DEBUG_INFO, " Address %d assigned unsuccessfully\n"));
+ DEBUG ((DEBUG_ERROR, " Slot %d address not assigned
successfully. Status = %r\n", SlotId, Status));
XhcDisableSlotCmd64 (Xhc, SlotId);
}

--
2.28.0.windows.1






回复: [edk2-devel][PATCH] BaseTools: Increase the DevicePath length for support more PCD value.

gaoliming
 

Xiaolu:
Can you calculate the required memory, then allocate it instead of use hard code memory length?

Thanks
Liming

-----邮件原件-----
发件人: Jiang, Xiaolu <xiaolu.jiang@...>
发送时间: 2021年11月8日 10:26
收件人: gaoliming <gaoliming@...>; devel@edk2.groups.io
抄送: Feng, Bob C <bob.c.feng@...>; Chen, Christine
<yuwei.chen@...>; Fu, Siyuan <siyuan.fu@...>
主题: RE: [edk2-devel][PATCH] BaseTools: Increase the DevicePath length for
support more PCD value.

Hi Liming,

I have checked with Team member , Totally We need support 50+ Driver GUID
in DevicePath PCD value ,So the length need to increase again, I will change
the Patch and re-send again.

Thanks!

-----Original Message-----
From: Jiang, Xiaolu
Sent: Monday, November 8, 2021 9:24 AM
To: gaoliming <gaoliming@...>; devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@...>; Chen, Christine
<Yuwei.Chen@...>
Subject: RE: [edk2-devel][PATCH] BaseTools: Increase the DevicePath length
for support more PCD value.

1. Currently the PCD value length is More than 1024, less than 2048, 2. Now
we have 14 members, Also need to add 4~6 part to the PCD.
So we Increase the length to 4096.

-----Original Message-----
From: gaoliming <gaoliming@...>
Sent: Monday, November 8, 2021 9:15 AM
To: Jiang, Xiaolu <xiaolu.jiang@...>; devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@...>; Chen, Christine
<yuwei.chen@...>
Subject: 回复: [edk2-devel][PATCH] BaseTools: Increase the DevicePath
length for support more PCD value.

Xiaolu:
Why choose 4096? Is it enough?

Thanks
Liming
-----邮件原件-----
发件人: Xiaolu.Jiang <xiaolu.jiang@...>
发送时间: 2021年11月6日 11:51
收件人: devel@edk2.groups.io
抄送: Xiaolu.Jiang <xiaolu.jiang@...>; Bob Feng
<bob.c.feng@...>; Liming Gao <gaoliming@...>; Yuwei
Chen <yuwei.chen@...>
主题: [edk2-devel][PATCH] BaseTools: Increase the DevicePath length for
support more PCD value.

Currently the PCD Value only support 13 Guid,When use more 13 pcd will
cause the build tool fail, Need increase the DevicePath length to
support more value.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3718

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>

Signed-off-by: Xiaolu Jiang <xiaolu.jiang@...>
---
BaseTools/Source/C/DevicePath/DevicePath.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/C/DevicePath/DevicePath.c
b/BaseTools/Source/C/DevicePath/DevicePath.c
index c4d224ed61..ef493f5506 100644
--- a/BaseTools/Source/C/DevicePath/DevicePath.c
+++ b/BaseTools/Source/C/DevicePath/DevicePath.c
@@ -170,7 +170,7 @@ int main(int argc, CHAR8 *argv[])
fprintf(stderr, "Invalid option value, Device Path can't be
NULL");

return STATUS_ERROR;

}

- Str16 = (CHAR16 *)malloc(1024);

+ Str16 = (CHAR16 *)malloc(4096);

if (Str16 == NULL) {

fprintf(stderr, "Resource, memory cannot be allocated");

return STATUS_ERROR;

--
2.30.2.windows.1


Re: [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP) support

Yao, Jiewen
 

Ok, then we have to wait.

Please aware that we are in the code freeze state. We may have to check in after WW50.

 

I would prefer to submit small patch set if possible. It is easy to get it reviewed and merged.

A large patch set is hard to review. Usually it takes longer time (not linear).

 

Thank you

Yao Jiewen

 

From: Singh, Brijesh <brijesh.singh@...>
Sent: Monday, November 8, 2021 10:50 AM
To: Yao, Jiewen <jiewen.yao@...>; devel@edk2.groups.io
Cc: James Bottomley <jejb@...>; Xu, Min M <min.m.xu@...>; Lendacky, Thomas <Thomas.Lendacky@...>; Justen, Jordan L <jordan.l.justen@...>; Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>; Roth, Michael <Michael.Roth@...>; Gerd Hoffmann <kraxel@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>
Subject: Re: [edk2-devel] [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP) support

 

[AMD Official Use Only]

 

Without UefiCpuPkg we will have a broken SNP support and I would prefer not to commit a broken SEV-SNP support. The UefiCpuPkg is required for the multiple CPU boot and based all the feedback we have added a new ConfidentialCompting PCD that is set and used for OVMF. Splitting all that support is much more work for no reason. 

 

I will wait couple of more days to see if UefiCpuPkg maintainer reply otherwise I will go ahead and send v12 with the rebased.

 

thanks,

Brijesh


From: Yao, Jiewen <jiewen.yao@...>
Sent: Sunday, November 7, 2021 8:14 PM
To: Singh, Brijesh <
brijesh.singh@...>; devel@edk2.groups.io <devel@edk2.groups.io>
Cc: James Bottomley <
jejb@...>; Xu, Min M <min.m.xu@...>; Lendacky, Thomas <Thomas.Lendacky@...>; Justen, Jordan L <jordan.l.justen@...>; Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>; Roth, Michael <Michael.Roth@...>; Gerd Hoffmann <kraxel@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; Yao, Jiewen <jiewen.yao@...>
Subject: RE: [edk2-devel] [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP) support

 

[AMD Official Use Only]

 

I recommend you split the patch set to OvmfPkg update and UefiPkg update, unless there is strong reason that you have to mix them together.

 

With that, I can merge the OvmfPkg at first and we can move forward there, while waiting UefiPkg review.

 

If you agree, please rebase and resubmit.

 

Thank you

Yao Jiewen

 

From: Singh, Brijesh <brijesh.singh@...>
Sent: Monday, November 8, 2021 10:11 AM
To: Yao, Jiewen <jiewen.yao@...>; devel@edk2.groups.io; Singh, Brijesh <brijesh.singh@...>
Cc: James Bottomley <jejb@...>; Xu, Min M <min.m.xu@...>; Lendacky, Thomas <Thomas.Lendacky@...>; Justen, Jordan L <jordan.l.justen@...>; Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>; Roth, Michael <Michael.Roth@...>; Gerd Hoffmann <kraxel@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>
Subject: Re: [edk2-devel] [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP) support

 

[AMD Official Use Only]

 

Hi,

 

I am not getting any response from the UefiCpuPkg maintainers,  I am not sure if the Ray/Rahul are on vacation or need more information.

 

Jiewen and Gerd,

 

Any recommendations how we proceed further ? I can send the rebased version and we can go ahead and commit it. If UefiCpuPkg maintainer does not like something, then I am always happy to rework the stuff after the commit. I would like to send some cleanup patches post SNP series that will simplify some of the MemEncryptIs{Sev,Es,Snp}Enabled() based on our recent workarea patches. It will also help/align with the TDX series.

 

-Brijesh


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Brijesh Singh via groups.io <brijesh.singh@...>
Sent: Sunday, October 31, 2021 4:40 PM
To: Yao, Jiewen <
jiewen.yao@...>; devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Singh, Brijesh <
brijesh.singh@...>; James Bottomley <jejb@...>; Xu, Min M <min.m.xu@...>; Lendacky, Thomas <Thomas.Lendacky@...>; Justen, Jordan L <jordan.l.justen@...>; Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>; Roth, Michael <Michael.Roth@...>; Gerd Hoffmann <kraxel@...>; Ray Ni <ray.ni@...>; Rahul Kumar <rahul1.kumar@...>
Subject: Re: [edk2-devel] [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP) support

 

Hi Ray and Rahul,

Gentle ping. Could you please Ack or R-b the files touched in UefiCpuPkg?

-Brijesh

On 10/29/21 9:52 AM, Brijesh Singh wrote:
> Hi Jiewen,
>
> I have not heard anything back from UefiCpuPkg maintainer yet, I will
> send another gentle ping on Monday again and hope maintainer get to it.
>
> -Brijesh
>
> On 10/29/21 7:26 AM, Yao, Jiewen wrote:
>> Hi Brijesh
>> Have you got R-B from UefiCpuPkg maintainer?
>>
>>
>>

>>> -----Original Message-----
>>> From: Brijesh Singh <brijesh.singh@...>
>>> Sent: Monday, October 25, 2021 7:54 AM
>>> To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@...>
>>> Cc: brijesh.singh@...; James Bottomley <jejb@...>; Xu, Min M
>>> <min.m.xu@...>; Tom Lendacky <thomas.lendacky@...>; Justen,
>>> Jordan L <jordan.l.justen@...>; Ard Biesheuvel
>>> <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>;
>>> Michael Roth <Michael.Roth@...>; Gerd Hoffmann <kraxel@...>
>>> Subject: Re: [edk2-devel] [PATCH v11 00/32] Add AMD Secure Nested Paging
>>> (SEV-SNP) support
>>>
>>> Thank Jiewen,
>>>
>>> I have ping'ed UefiCpuPkg maintainer (Ray and Rahul) on every patch
>>> which touches the UefiCpuPkg. If maintainer wants me to rework on
>>> something then I will work accordingly. If they are okay with v11 then
>>> now the merge will create a conflict (due to the TDX patches merge
>>> commit). I have rebased my series to the recent master and have pushed
>>> it here: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FAMDESE%2Fovmf%2Ftree%2Fsnp-v12&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7C400c84b654c6423f739e08d99cb72382%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637713132658929026%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=loCp%2FptHiWgvAtdp6zjDH5jDeq9mKLYBwedNU%2FT0IzM%3D&amp;reserved=0. I can post the
>>> series if you prefer it.
>>>
>>> thanks
>>>
>>> On 10/23/21 8:46 PM, Yao, Jiewen via groups.io wrote:
>>>> Yes. I will try my best to merge.
>>>>
>>>> I checked the patch set but I did not find the "R-B" from UefiCpuPkg
>>> maintainer. Neither from email nor from you v11.
>>>> Did I miss something?
>>>>
>>>> Thank you
>>>> Yao Jiewen
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: Brijesh Singh <brijesh.singh@...>
>>>>> Sent: Saturday, October 23, 2021 12:13 PM
>>>>> To: devel@edk2.groups.io
>>>>> Cc: James Bottomley <jejb@...>; Xu, Min M
>>> <min.m.xu@...>;
>>>>> Yao, Jiewen <jiewen.yao@...>; Tom Lendacky
>>>>> <thomas.lendacky@...>; Justen, Jordan L <jordan.l.justen@...>;
>>>>> Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas
>>>>> <erdemaktas@...>; Michael Roth <Michael.Roth@...>; Gerd
>>>>> Hoffmann <kraxel@...>; Brijesh Singh <brijesh.singh@...>
>>>>> Subject: [PATCH v11 00/32] Add AMD Secure Nested Paging (SEV-SNP)
>>> support
>>>>> Hi Gerd and Jiewen,
>>>>>
>>>>> CI was a bit unstable during my v10 submission, so, I was not able to
>>>>> run it to the completion. Finally, I managed to get the CI going,
>>>>> and it reported few Windows 32-bit build errors. The v11 fixes those build
>>>>> errors. Please consider this for the merge.
>>>>>
>>>>> Thank you so much for all your support in reviewing the series.
>>>>>
>>>>> -----------------------------------------------------------------------------
>>>>> BZ:
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.
>>> tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&amp;data=04%7C01%7Cbrijesh.
>>> singh%40amd.com%7Cddc5570780ff4a91d0da08d9969026e2%7C3dd8961fe488
>>> 4e608e11a82d994e183d%7C0%7C0%7C637706369230826414%7CUnknown%7
>>> CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ
>>> XVCI6Mn0%3D%7C3000&amp;sdata=L41krO6G221HaIsG92FloIzgCDqMLAAsU26
>>> jaEMF7yw%3D&amp;reserved=0
>>>>> SEV-SNP builds upon existing SEV and SEV-ES functionality while adding
>>>>> new hardware-based memory protections. SEV-SNP adds strong memory
>>>>> integrity
>>>>> protection to help prevent malicious hypervisor-based attacks like data
>>>>> replay, memory re-mapping and more in order to create an isolated memory
>>>>> encryption environment.
>>>>>
>>>>> This series provides the basic building blocks to support booting the SEV-SNP
>>>>> VMs, it does not cover all the security enhancement introduced by the SEV-
>>> SNP
>>>>> such as interrupt protection.
>>>>>
>>>>> Many of the integrity guarantees of SEV-SNP are enforced through a new
>>>>> structure called the Reverse Map Table (RMP). Adding a new page to SEV-SNP
>>>>> VM requires a 2-step process. First, the hypervisor assigns a page to the
>>>>> guest using the new RMPUPDATE instruction. This transitions the page to
>>>>> guest-invalid. Second, the guest validates the page using the new PVALIDATE
>>>>> instruction. The SEV-SNP VMs can use the new "Page State Change Request
>>>>> NAE"
>>>>> defined in the GHCB specification to ask hypervisor to add or remove page
>>>>> from the RMP table.
>>>>>
>>>>> Each page assigned to the SEV-SNP VM can either be validated or unvalidated,
>>>>> as indicated by the Validated flag in the page's RMP entry. There are two
>>>>> approaches that can be taken for the page validation: Pre-validation and
>>>>> Lazy Validation.
>>>>>
>>>>> Under pre-validation, the pages are validated prior to first use. And under
>>>>> lazy validation, pages are validated when first accessed. An access to a
>>>>> unvalidated page results in a #VC exception, at which time the exception
>>>>> handler may validate the page. Lazy validation requires careful tracking of
>>>>> the validated pages to avoid validating the same GPA more than once. The
>>>>> recently introduced "Unaccepted" memory type can be used to communicate
>>>>> the
>>>>> unvalidated memory ranges to the Guest OS.
>>>>>
>>>>> At this time we only support the pre-validation. OVMF detects all the
>>> available
>>>>> system RAM in the PEI phase. When SEV-SNP is enabled, the memory is
>>> validated
>>>>> before it is made available to the EDK2 core.
>>>>>
>>>>> Now that series contains all the basic support required to launch SEV-SNP
>>>>> guest. We are still missing the Interrupt security feature provided by the
>>>>> SNP. The feature will be added after the base support is accepted.
>>>>>
>>>>> Additional resources
>>>>> ---------------------
>>>>> SEV-SNP whitepaper
>>>>>
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.a%2F&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7C400c84b654c6423f739e08d99cb72382%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637713132658929026%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=WznkScyKwwPKfde08y%2Fb1KTmUgVt2al9%2Bupz%2FATGOHE%3D&amp;reserved=0
>>> md.com%2Fsystem%2Ffiles%2FTechDocs%2FSEV-SNP-strengthening-vm-
>>> &amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7Cddc5570780ff4a91d0da
>>> 08d9969026e2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63770
>>> 6369230826414%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQ
>>> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=nVMSG%
>>> 2FvSS2Wa21lu1lGrHr9OYX8hL7FoAcQXBBiCztc%3D&amp;reserved=0
>>>>> isolation-with-integrity-protection-and-more.pdf
>>>>>
>>>>> APM 2:
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.a%2F&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7C400c84b654c6423f739e08d99cb72382%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637713132658929026%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=WznkScyKwwPKfde08y%2Fb1KTmUgVt2al9%2Bupz%2FATGOHE%3D&amp;reserved=0
>>> md.com%2Fsystem%2Ffiles%2FTechDocs%2F24593.pdf&amp;data=04%7C01%7
>>> Cbrijesh.singh%40amd.com%7Cddc5570780ff4a91d0da08d9969026e2%7C3dd8
>>> 961fe4884e608e11a82d994e183d%7C0%7C0%7C637706369230826414%7CUnk
>>> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
>>> aWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=G8Xg2glOGY2EjHpeQ3WM4gZCh
>>> uI0k8QcLDTbpJiTplg%3D&amp;reserved=0 (section 15.36)
>>>>> The complete source is available at
>>>>>
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c%2F&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7C400c84b654c6423f739e08d99cb72382%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637713132658929026%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Wx6h8FQ0289ZBQJa3iTk3Sb7zkmQO6D6VZFvRX5lEeM%3D&amp;reserved=0
>>> om%2FAMDESE%2Fovmf%2Ftree%2Fsnp-
>>> v11&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7Cddc5570780ff4a91d
>>> 0da08d9969026e2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63
>>> 7706369230826414%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiL
>>> CJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=HMH
>>> Fq8G%2FPqdhzNW3Ashmc4%2Bmv1RcDULD4vniofhiS54%3D&amp;reserved=0
>>>>> GHCB spec:
>>>>>
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdevelop
>>> er.amd.com%2Fwp-
>>> content%2Fresources%2F56421.pdf&amp;data=04%7C01%7Cbrijesh.singh%40a
>>> md.com%7Cddc5570780ff4a91d0da08d9969026e2%7C3dd8961fe4884e608e11
>>> a82d994e183d%7C0%7C0%7C637706369230826414%7CUnknown%7CTWFpbGZ
>>> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
>>> %3D%7C3000&amp;sdata=YiPgZU87fdnl5rJpD0E2ue9aTKbqUwizuBrKxom0FiU%
>>> 3D&amp;reserved=0
>>>>> SEV-SNP firmware specification:
>>>>>
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.a%2F&amp;data=04%7C01%7Cbrijesh.singh%40amd.com%7C400c84b654c6423f739e08d99cb72382%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637713132658939021%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Hs%2BB9e%2FrZ0aYV3XPtJ9ZegaaIAMURuH1Dc9C1CeBauU%3D&amp;reserved=0
>>> md.com%2Fsystem%2Ffiles%2FTechDocs%2F56860.pdf&amp;data=04%7C01%7
>>> Cbrijesh.singh%40amd.com%7Cddc5570780ff4a91d0da08d9969026e2%7C3dd8
>>> 961fe4884e608e11a82d994e183d%7C0%7C0%7C637706369230826414%7CUnk
>>> nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
>>> aWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=bfQsY4%2BRnlFGuD3Bg%2BFPb3l
>>> RgSGgpomNocXswHqkm%2F4%3D&amp;reserved=0
>>>>> Change since v10:
>>>>>  * fix 'unresolved external symbol __allshl' link error when building I32 for
>>>>> VS2017.
>>>>>
>>>>> Changes since v9:
>>>>>  * Move CCAttrs Pcd define in MdePkg
>>>>>  * Add comment to indicate that allocating the identity map PT is temporary
>>> until
>>>>> we get lazy validation
>>>>>
>>>>> Changes since v8:
>>>>>  * drop the generic metadata and make it specific to SEV.
>>>>>
>>>>> Changes since v7:
>>>>>  * Move SEV specific changes in MpLib in AmdSev file
>>>>>  * Update the GHCB register function to not restore the GHCB MSR because
>>>>>    we were already in the MSR protocol mode.
>>>>>  * Drop the SNP name from PcdSnpSecPreValidate.
>>>>>  * Add new section for GHCB memory in the OVMF metadata.
>>>>>
>>>>> Change since v6:
>>>>>  * Drop the SNP boot block GUID and switch to using the Metadata guided
>>>>> structure
>>>>>    proposed by Min in TDX series.
>>>>>  * Exclude the GHCB page from the pre-validated region. It simplifies the
>>> reset
>>>>>    vector code where we do not need to unvalidate the GHCB page.
>>>>>  * Now that GHCB page is not validated so move the VMPL check from reset
>>>>> vector
>>>>>    code to the MemEncryptSevLib on the first page validation.
>>>>>  * Introduce the ConfidentialComputingGuestAttr PCD to communicate which
>>>>>    memory encryption is active so that MpInitLib can make use of it.
>>>>>  * Drop the SEVES specific PCD as the information can be communicated via
>>>>>    the ConfidentialComputingGuestAttr.
>>>>>  * Move the SNP specific AP creation function in AmdSev.c.
>>>>>  * Define the SNP Blob GUID in a new file.
>>>>>
>>>>> Change since v5:
>>>>>  * When possible use the CPUID value from CPUID page
>>>>>  * Move the SEV specific functions from SecMain.c in AmdSev.c
>>>>>  * Rebase to the latest code
>>>>>  * Add the review feedback from Yao.
>>>>>
>>>>> Change since v4:
>>>>>  * Use the correct MSR for the SEV_STATUS
>>>>>  * Add VMPL-0 check
>>>>>
>>>>> Change since v3:
>>>>>  * ResetVector: move all SEV specific code in AmdSev.asm and add macros to
>>>>> keep
>>>>>    the code readable.
>>>>>  * Drop extending the EsWorkArea to contain SNP specific state.
>>>>>  * Drop the GhcbGpa library and call the VmgExit directly to register GHCB
>>> GPA.
>>>>>  * Install the CC blob config table from AmdSevDxe instead of extending the
>>>>>    AmdSev/SecretsDxe for it.
>>>>>  * Add the separate PCDs for the SNP Secrets.
>>>>>
>>>>> Changes since v2:
>>>>>  * Add support for the AP creation.
>>>>>  * Use the module-scoping override to make AmdSevDxe use the IO port for
>>> PCI
>>>>> reads.
>>>>>  * Use the reserved memory type for CPUID and Secrets page.
>>>>>  *
>>>>> Changes since v1:
>>>>>  * Drop the interval tree support to detect the pre-validated overlap region.
>>>>>  * Use an array to keep track of pre-validated regions.
>>>>>  * Add support to query the Hypervisor feature and verify that SNP feature is
>>>>> supported.
>>>>>  * Introduce MemEncryptSevClearMmioPageEncMask() to clear the C-bit
>>> from
>>>>> MMIO ranges.
>>>>>  * Pull the SevSecretDxe and SevSecretPei into OVMF package build.
>>>>>  * Extend the SevSecretDxe to expose confidential computing blob location
>>>>> through
>>>>>    EFI configuration table.
>>>>>
>>>>> Brijesh Singh (28):
>>>>>   OvmfPkg/SecMain: move SEV specific routines in AmdSev.c
>>>>>   UefiCpuPkg/MpInitLib: move SEV specific routines in AmdSev.c
>>>>>   OvmfPkg/ResetVector: move clearing GHCB in SecMain
>>>>>   OvmfPkg/ResetVector: introduce SEV metadata descriptor for VMM use
>>>>>   OvmfPkg: reserve SNP secrets page
>>>>>   OvmfPkg: reserve CPUID page
>>>>>   OvmfPkg/ResetVector: pre-validate the data pages used in SEC phase
>>>>>   OvmfPkg/MemEncryptSevLib: add MemEncryptSevSnpEnabled()
>>>>>   OvmfPkg/SecMain: register GHCB gpa for the SEV-SNP guest
>>>>>   OvmfPkg/PlatformPei: register GHCB gpa for the SEV-SNP guest
>>>>>   OvmfPkg/AmdSevDxe: do not use extended PCI config space
>>>>>   OvmfPkg/MemEncryptSevLib: add support to validate system RAM
>>>>>   OvmfPkg/MemEncryptSevLib: add function to check the VMPL0
>>>>>   OvmfPkg/BaseMemEncryptSevLib: skip the pre-validated system RAM
>>>>>   OvmfPkg/MemEncryptSevLib: add support to validate > 4GB memory in PEI
>>>>>     phase
>>>>>   OvmfPkg/SecMain: validate the memory used for decompressing Fv
>>>>>   OvmfPkg/PlatformPei: validate the system RAM when SNP is active
>>>>>   UefiCpuPkg: Define ConfidentialComputingGuestAttr
>>>>>   OvmfPkg/PlatformPei: set PcdConfidentialComputingAttr when SEV is
>>>>>     active
>>>>>   UefiCpuPkg/MpInitLib: use PcdConfidentialComputingAttr to check SEV
>>>>>     status
>>>>>   UefiCpuPkg: add PcdGhcbHypervisorFeatures
>>>>>   OvmfPkg/PlatformPei: set the Hypervisor Features PCD
>>>>>   MdePkg/GHCB: increase the GHCB protocol max version
>>>>>   UefiCpuPkg/MpLib: add support to register GHCB GPA when SEV-SNP is
>>>>>     enabled
>>>>>   OvmfPkg/MemEncryptSevLib: change the page state in the RMP table
>>>>>   OvmfPkg/MemEncryptSevLib: skip page state change for Mmio address
>>>>>   OvmfPkg/PlatformPei: mark cpuid and secrets memory reserved in EFI map
>>>>>   OvmfPkg/AmdSev: expose the SNP reserved pages through configuration
>>>>>     table
>>>>>
>>>>> Michael Roth (3):
>>>>>   OvmfPkg/ResetVector: use SEV-SNP-validated CPUID values
>>>>>   OvmfPkg/VmgExitLib: use SEV-SNP-validated CPUID values
>>>>>   UefiCpuPkg/MpInitLib: use BSP to do extended topology check
>>>>>
>>>>> Tom Lendacky (1):
>>>>>   UefiCpuPkg/MpInitLib: Use SEV-SNP AP Creation NAE event to launch APs
>>>>>
>>>>>  MdePkg/MdePkg.dec                             |   4 +
>>>>>  OvmfPkg/OvmfPkg.dec                           |  18 +
>>>>>  UefiCpuPkg/UefiCpuPkg.dec                     |   5 +
>>>>>  OvmfPkg/AmdSev/AmdSevX64.dsc                  |   8 +-
>>>>>  OvmfPkg/Bhyve/BhyveX64.dsc                    |   5 +-
>>>>>  OvmfPkg/OvmfPkgIa32.dsc                       |   4 +
>>>>>  OvmfPkg/OvmfPkgIa32X64.dsc                    |   9 +-
>>>>>  OvmfPkg/OvmfPkgX64.dsc                        |   8 +-
>>>>>  OvmfPkg/OvmfXen.dsc                           |   5 +-
>>>>>  OvmfPkg/OvmfPkgX64.fdf                        |   6 +
>>>>>  OvmfPkg/AmdSevDxe/AmdSevDxe.inf               |   7 +
>>>>>  .../DxeMemEncryptSevLib.inf                   |   3 +
>>>>>  .../PeiMemEncryptSevLib.inf                   |   7 +
>>>>>  .../SecMemEncryptSevLib.inf                   |   3 +
>>>>>  OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf  |   2 +
>>>>>  OvmfPkg/Library/VmgExitLib/VmgExitLib.inf     |   3 +
>>>>>  OvmfPkg/PlatformPei/PlatformPei.inf           |   7 +
>>>>>  OvmfPkg/ResetVector/ResetVector.inf           |   5 +
>>>>>  OvmfPkg/Sec/SecMain.inf                       |   4 +
>>>>>  UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |   6 +-
>>>>>  UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf |   6 +-
>>>>>  .../Include/ConfidentialComputingGuestAttr.h  |  25 +
>>>>>  MdePkg/Include/Register/Amd/Ghcb.h            |   2 +-
>>>>>  .../Guid/ConfidentialComputingSevSnpBlob.h    |  33 ++
>>>>>  OvmfPkg/Include/Library/MemEncryptSevLib.h    |  26 +
>>>>>  .../X64/SnpPageStateChange.h                  |  36 ++
>>>>>  .../BaseMemEncryptSevLib/X64/VirtualMemory.h  |  24 +
>>>>>  OvmfPkg/PlatformPei/Platform.h                |   5 +
>>>>>  OvmfPkg/Sec/AmdSev.h                          |  95 ++++
>>>>>  UefiCpuPkg/Library/MpInitLib/MpLib.h          |  93 ++++
>>>>>  OvmfPkg/AmdSevDxe/AmdSevDxe.c                 |  23 +
>>>>>  .../DxeMemEncryptSevLibInternal.c             |  27 ++
>>>>>  .../Ia32/MemEncryptSevLib.c                   |  17 +
>>>>>  .../PeiMemEncryptSevLibInternal.c             |  27 ++
>>>>>  .../SecMemEncryptSevLibInternal.c             |  19 +
>>>>>  .../X64/DxeSnpSystemRamValidate.c             |  40 ++
>>>>>  .../X64/PeiDxeVirtualMemory.c                 | 167 ++++++-
>>>>>  .../X64/PeiSnpSystemRamValidate.c             | 127 +++++
>>>>>  .../X64/SecSnpSystemRamValidate.c             |  82 ++++
>>>>>  .../X64/SnpPageStateChangeInternal.c          | 294 ++++++++++++
>>>>>  OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 444
>>> ++++++++++++++++--
>>>>>  OvmfPkg/PlatformPei/AmdSev.c                  | 231 +++++++++
>>>>>  OvmfPkg/PlatformPei/MemDetect.c               |   2 +
>>>>>  OvmfPkg/Sec/AmdSev.c                          | 298 ++++++++++++
>>>>>  OvmfPkg/Sec/SecMain.c                         | 158 +------
>>>>>  UefiCpuPkg/Library/MpInitLib/AmdSev.c         | 239 ++++++++++
>>>>>  UefiCpuPkg/Library/MpInitLib/DxeMpLib.c       |  16 +-
>>>>>  UefiCpuPkg/Library/MpInitLib/Ia32/AmdSev.c    |  70 +++
>>>>>  UefiCpuPkg/Library/MpInitLib/MpLib.c          | 345 +++++---------
>>>>>  UefiCpuPkg/Library/MpInitLib/PeiMpLib.c       |   4 +-
>>>>>  UefiCpuPkg/Library/MpInitLib/X64/AmdSev.c     | 261 ++++++++++
>>>>>  OvmfPkg/FvmainCompactScratchEnd.fdf.inc       |   5 +
>>>>>  OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm  |  17 +
>>>>>  OvmfPkg/ResetVector/Ia32/AmdSev.asm           |  86 +++-
>>>>>  OvmfPkg/ResetVector/ResetVector.nasmb         |  18 +
>>>>>  OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm   |  74 +++
>>>>>  UefiCpuPkg/Library/MpInitLib/MpEqu.inc        |   2 +
>>>>>  UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm  | 200 ++++++++
>>>>>  UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 100 +---
>>>>>  59 files changed, 3329 insertions(+), 528 deletions(-)
>>>>>  create mode 100644 MdePkg/Include/ConfidentialComputingGuestAttr.h
>>>>>  create mode 100644
>>>>> OvmfPkg/Include/Guid/ConfidentialComputingSevSnpBlob.h
>>>>>  create mode 100644
>>>>> OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChange.h
>>>>>  create mode 100644 OvmfPkg/Sec/AmdSev.h
>>>>>  create mode 100644
>>>>> OvmfPkg/Library/BaseMemEncryptSevLib/X64/DxeSnpSystemRamValidate.c
>>>>>  create mode 100644
>>>>> OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiSnpSystemRamValidate.c
>>>>>  create mode 100644
>>>>> OvmfPkg/Library/BaseMemEncryptSevLib/X64/SecSnpSystemRamValidate.c
>>>>>  create mode 100644
>>>>>
>>> OvmfPkg/Library/BaseMemEncryptSevLib/X64/SnpPageStateChangeInternal.c
>>>>>  create mode 100644 OvmfPkg/Sec/AmdSev.c
>>>>>  create mode 100644 UefiCpuPkg/Library/MpInitLib/AmdSev.c
>>>>>  create mode 100644 UefiCpuPkg/Library/MpInitLib/Ia32/AmdSev.c
>>>>>  create mode 100644 UefiCpuPkg/Library/MpInitLib/X64/AmdSev.c
>>>>>  create mode 100644 OvmfPkg/ResetVector/X64/OvmfSevMetadata.asm
>>>>>  create mode 100644 UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
>>>>>
>>>>> --
>>>>> 2.25.1
>>>>
>>>>
>>>>


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