Date   

Re: [PATCH] OvmfPkg/BhyveBhfPkg: install bhyve's ACPI tables

Yao, Jiewen
 

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Peter
Grehan
Sent: Thursday, October 14, 2021 1:42 PM
To: Köhne, Corvin <c.koehne@beckhoff.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen
<jiewen.yao@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; Gerd
Hoffmann <kraxel@redhat.com>; Rebecca Cran <rebecca@bsdio.com>;
devel@edk2.groups.io; Kinney, Michael D <michael.d.kinney@intel.com>;
Liming Gao <gaoliming@byosoft.com.cn>; Liu, Zhiguang
<zhiguang.liu@intel.com>
Subject: Re: [edk2-devel] [PATCH] OvmfPkg/BhyveBhfPkg: install bhyve's ACPI
tables

It's much easier to create configuration dependend ACPI tables for > bhyve
than for OVMF. For this reason, don't use the statically>
created ACPI tables provided by OVMF. Instead use the dynamically>
created ACPI tables of bhyve. If bhyve provides no ACPI tables or> we
are unable to detect those, fall back to OVMF tables.
This looks fine though bhyve will need to generate MCFG to get to full
parity.

I've requested in the past that you do this so I'll request again:
please discuss these changes on the freebsd-virtualization list before
sending patches outside of the project.

Acked-by: Peter Grehan <grehan@freebsd.org>

later,

Peter.




[edk2-platforms: PATCH v5 9/9] WhitleySiliconPkg: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl=
atformLib.c | 35 +++++++++--------------------------
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl=
atformLib.inf | 3 ++-
2 files changed, 11 insertions(+), 27 deletions(-)

diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/=
FspWrapperPlatformLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrappe=
rPlatformLib/FspWrapperPlatformLib.c
index a6196a78b0..95a1f2a33c 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap=
perPlatformLib.c
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap=
perPlatformLib.c
@@ -13,7 +13,7 @@
#include <Library/HobLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
#include <Library/LargeVariableReadLib.h>=0D
-=0D
+#include <Library/PeiLib.h>=0D
#include <FspmUpd.h>=0D
#include <Guid/PlatformInfo.h>=0D
#include <Ppi/UpiPolicyPpi.h>=0D
@@ -24,39 +24,22 @@ GetFspNvsBuffer (
)=0D
{=0D
EFI_STATUS Status;=0D
- UINTN FspNvsBufferSize;=0D
- VOID *FspNvsBufferPtr;=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
=0D
FspNvsBufferPtr =3D NULL;=0D
FspNvsBufferSize =3D 0;=0D
- Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHob=
Guid, &FspNvsBufferSize, NULL);=0D
- if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
- DEBUG ((DEBUG_INFO, "FspNvsBuffer Size =3D %d\n", FspNvsBufferSize));=
=0D
- FspNvsBufferPtr =3D AllocateZeroPool (FspNvsBufferSize);=0D
- if (FspNvsBufferPtr =3D=3D NULL) {=0D
- DEBUG ((DEBUG_ERROR, "Error: Cannot create FspNvsBuffer, out of memo=
ry!\n"));=0D
- ASSERT (FALSE);=0D
- return NULL;=0D
- }=0D
- Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageH=
obGuid, &FspNvsBufferSize, FspNvsBufferPtr);=0D
- if (EFI_ERROR (Status)) {=0D
- DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variab=
le Status: %r\n", Status));=0D
- ASSERT_EFI_ERROR (Status);=0D
- return NULL;=0D
- }=0D
-=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
return FspNvsBufferPtr;=0D
-=0D
- } else if (Status =3D=3D EFI_NOT_FOUND) {=0D
- DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does =
not exist (this is likely a first boot)\n"));=0D
} else {=0D
- DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable=
Status: %r\n", Status));=0D
- ASSERT_EFI_ERROR (Status);=0D
- }=0D
-=0D
+ DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does =
not exist (this is likely a first boot)\n"));=0D
return NULL;=0D
}=0D
=0D
+=0D
+}=0D
+=0D
VOID=0D
EFIAPI=0D
UpdateFspmUpdData (=0D
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/=
FspWrapperPlatformLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrap=
perPlatformLib/FspWrapperPlatformLib.inf
index 3e80ea670c..6ee15ea55f 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap=
perPlatformLib.inf
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap=
perPlatformLib.inf
@@ -58,11 +58,12 @@
=0D
[Guids]=0D
gEfiPlatformInfoGuid=0D
- gFspNonVolatileStorageHobGuid=0D
+ gFspNvsBufferVariableGuid # CONSUMES=0D
=0D
[LibraryClasses]=0D
PeiServicesLib=0D
LargeVariableReadLib=0D
+ PeiLib=0D
=0D
[Pcd]=0D
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 8/9] WhitleyOpenBoardPkg: Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

Implementation should search FSP_NON_VOLATILE_STORAGE_HOB2 firstly
and only search FSP_NON_VOLATILE_STORAGE_HOB when former one is not found.

Also added PeiGetLargeVariable () to support the scenarios where the
variable data size is bigger than a single variable size limit.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.c =
| 29 +++++++++++++++++++++++------
Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.in=
f | 4 +++-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc =
| 1 +
3 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3=
NvramSave.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S=
3NvramSave.c
index 709c7ad479..01e36cda27 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa=
ve.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa=
ve.c
@@ -7,6 +7,7 @@
**/=0D
=0D
#include "S3NvramSave.h"=0D
+#include <Guid/FspNonVolatileStorageHob2.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
#include <Library/LargeVariableReadLib.h>=0D
#include <Library/LargeVariableWriteLib.h>=0D
@@ -80,21 +81,37 @@ SaveFspNonVolatileStorageHob (
Status =3D EFI_SUCCESS;=0D
=0D
DEBUG ((DEBUG_INFO, "Saving FSP / MRC Training Data\n"));=0D
- GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHobGuid);=0D
+ //=0D
+ // Firstly check version2 FspNvsHob.=0D
+ //=0D
+ GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHob2Guid);=0D
if (GuidHob !=3D NULL) {=0D
- HobData =3D GET_GUID_HOB_DATA (GuidHob);=0D
- DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob);=0D
+ HobData =3D (VOID *) (UINTN) ((FSP_NON_VOLATILE_STORAGE_HOB2 *) (UINTN=
) GuidHob)->NvsDataPtr;=0D
+ DataSize =3D (UINTN) ((FSP_NON_VOLATILE_STORAGE_HOB2 *) (UINTN) GuidHo=
b)->NvsDataLength;=0D
+ } else {=0D
+ //=0D
+ // Fall back to version1 FspNvsHob=0D
+ //=0D
+ GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHobGuid);=0D
+ if (GuidHob !=3D NULL) {=0D
+ HobData =3D GET_GUID_HOB_DATA (GuidHob);=0D
+ DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob);=0D
+ }=0D
+ }=0D
+ if (HobData !=3D NULL) {=0D
+ DEBUG ((DEBUG_INFO, "FspNvsHob.Size: %d\n", DataSize));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsHob.NvsDataPtr: 0x%x\n", HobData));=0D
if (DataSize > 0) {=0D
=0D
//=0D
// Check if the presently saved data is identical to the data given =
by MRC/FSP=0D
//=0D
- Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorag=
eHobGuid, &FspNvsBufferSize, NULL);=0D
+ Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariable=
Guid, &FspNvsBufferSize, NULL);=0D
if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
if (FspNvsBufferSize =3D=3D DataSize) {=0D
VariableData =3D AllocatePool (FspNvsBufferSize);=0D
if (VariableData !=3D NULL) {=0D
- Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatile=
StorageHobGuid, &FspNvsBufferSize, VariableData);=0D
+ Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVa=
riableGuid, &FspNvsBufferSize, VariableData);=0D
if (!EFI_ERROR (Status) && (FspNvsBufferSize =3D=3D DataSize) =
&& (0 =3D=3D CompareMem (HobData, VariableData, DataSize))) {=0D
DataIsIdentical =3D TRUE;=0D
}=0D
@@ -105,7 +122,7 @@ SaveFspNonVolatileStorageHob (
Status =3D EFI_SUCCESS;=0D
=0D
if (!DataIsIdentical) {=0D
- Status =3D SetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStor=
ageHobGuid, TRUE, DataSize, HobData);=0D
+ Status =3D SetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariab=
leGuid, TRUE, DataSize, HobData);=0D
ASSERT_EFI_ERROR (Status);=0D
DEBUG ((DEBUG_INFO, "Saved size of FSP / MRC Training Data: 0x%x\n=
", DataSize));=0D
} else {=0D
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3=
NvramSave.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave=
/S3NvramSave.inf
index e62baa24c4..a77125cf44 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa=
ve.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSa=
ve.inf
@@ -43,7 +43,9 @@
LargeVariableWriteLib=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid # CONSUMES=0D
+ gFspNonVolatileStorageHobGuid # CONSUMES=0D
+ gFspNonVolatileStorageHob2Guid # CONSUMES=0D
+ gFspNvsBufferVariableGuid # PRODUCES=0D
=0D
[Pcd]=0D
gEfiCpRcPkgTokenSpaceGuid.PcdPeiSyshostMemorySize=0D
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/=
Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index dc3dd0e026..87165103bf 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -637,6 +637,7 @@
=0D
[LibraryClasses.Common]=0D
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in=
f=0D
+ PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf=0D
=0D
[Components.IA32]=0D
UefiCpuPkg/SecCore/SecCore.inf=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 7/9] WhiskeylakeOpenBoardPkg: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy=
UpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++---=
------------------------------------------------
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSili=
conPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++---=
------------------------------------------------
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy=
UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSili=
conPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 4 ++--
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclud=
e.fdf | 18 +++++++++------=
---
5 files changed, 37 insertions(+), 116 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS=
iliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/Whiskeyl=
akeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscU=
pdUpdateLib.c
index a341a58930..ab35bc3f8f 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP=
olicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP=
olicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -2,7 +2,7 @@
Implementation of Fsp Misc UPD Initialization.=0D
=0D
=0D
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
=0D
@@ -17,11 +17,9 @@
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
=0D
-#include <Library/MemoryAllocationLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DebugPrintErrorLevelLib.h>=0D
#include <Library/PciLib.h>=0D
-#include <Ppi/ReadOnlyVariable2.h>=0D
#include <Guid/MemoryOverwriteControl.h>=0D
#include <PchAccess.h>=0D
=0D
@@ -44,55 +42,18 @@ PeiFspMiscUpdUpdatePreMem (
)=0D
{=0D
EFI_STATUS Status;=0D
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;=0D
- UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
-=0D
- Status =3D PeiServicesLocatePpi (=0D
- &gEfiPeiReadOnlyVariable2PpiGuid,=0D
- 0,=0D
- NULL,=0D
- (VOID **) &VariableServices=0D
- );=0D
- if (EFI_ERROR (Status)) {=0D
- ASSERT_EFI_ERROR (Status);=0D
- return Status;=0D
- }=0D
-=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
- MemorySavedData =3D AllocatePool (VariableSize);=0D
- if (MemorySavedData =3D=3D NULL) {=0D
- ASSERT (MemorySavedData !=3D NULL);=0D
- return EFI_OUT_OF_RESOURCES;=0D
- }=0D
-=0D
- DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_SUCCESS) {=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
- } else {=0D
- DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe=
moryConfigVariableGuid, Status =3D %r\n", Status));=0D
- ASSERT_EFI_ERROR (Status);=0D
- }=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
+=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
+ } else {=0D
+ DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does =
not exist (this is likely a first boot)\n"));=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D NULL;=0D
}=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
=0D
return EFI_SUCCESS;=0D
}=0D
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib=
rary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel=
/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdate=
LibFsp/PeiFspMiscUpdUpdateLib.c
index 145deb5de3..381ef232ea 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pe=
iSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pe=
iSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -2,7 +2,7 @@
Implementation of Fsp Misc UPD Initialization.=0D
=0D
=0D
- Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
=0D
@@ -18,11 +18,9 @@
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
=0D
-#include <Library/MemoryAllocationLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DebugPrintErrorLevelLib.h>=0D
#include <Library/PciLib.h>=0D
-#include <Ppi/ReadOnlyVariable2.h>=0D
#include <Guid/MemoryOverwriteControl.h>=0D
#include <PchAccess.h>=0D
#include <Platform.h>=0D
@@ -46,54 +44,17 @@ PeiFspMiscUpdUpdatePreMem (
)=0D
{=0D
EFI_STATUS Status;=0D
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;=0D
- UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
-=0D
- Status =3D PeiServicesLocatePpi (=0D
- &gEfiPeiReadOnlyVariable2PpiGuid,=0D
- 0,=0D
- NULL,=0D
- (VOID **) &VariableServices=0D
- );=0D
- if (EFI_ERROR (Status)) {=0D
- ASSERT_EFI_ERROR (Status);=0D
- return Status;=0D
- }=0D
-=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
- MemorySavedData =3D AllocatePool (VariableSize);=0D
- if (MemorySavedData =3D=3D NULL) {=0D
- ASSERT (MemorySavedData !=3D NULL);=0D
- return EFI_OUT_OF_RESOURCES;=0D
- }=0D
-=0D
- DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_SUCCESS) {=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
- } else {=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D NULL;=0D
- DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe=
moryConfigVariableGuid, Status =3D %r\n", Status));=0D
- ASSERT_EFI_ERROR (Status);=0D
- }=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
+=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
+ } else {=0D
+ DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does =
not exist (this is likely a first boot)\n"));=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D NULL;=0D
}=0D
=0D
FspmUpd->FspmConfig.TsegSize =3D FixedPcdGet32 (PcdTsegSize=
);=0D
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS=
iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/=
WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/Pei=
SiliconPolicyUpdateLibFsp.inf
index 2c90d0cb94..362dc2c995 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP=
olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP=
olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -2,7 +2,7 @@
# Provide FSP wrapper platform related function.=0D
#=0D
#=0D
-# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -82,7 +82,6 @@
PchInfoLib=0D
PchHsioLib=0D
PchPcieRpLib=0D
- MemoryAllocationLib=0D
DebugPrintErrorLevelLib=0D
SiPolicyLib=0D
PchGbeLib=0D
@@ -132,7 +131,7 @@
gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Lib=
rary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platfo=
rm/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPoli=
cyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index 529c2f1253..1a664b1327 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pe=
iSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pe=
iSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -2,7 +2,7 @@
# FSP silicon policy updates for the Up Xtreme board.=0D
#=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -136,7 +136,7 @@
gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/Fl=
ashMapInclude.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include=
/Fdf/FlashMapInclude.fdf
index f7aa730ae7..698efce248 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapI=
nclude.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapI=
nclude.fdf
@@ -2,7 +2,7 @@
# Flash map for the UpXtreme Board.=0D
#=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -35,16 +35,16 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =
=3D 0x00090000
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x=
00190000 # Flash addr (0xFFAE0000)=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x=
00190000 #=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x=
00320000 # Flash addr (0xFFC70000)=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x=
00170000 #=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x=
00490000 # Flash addr (0xFFDE0000)=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x=
00160000 #=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x=
00480000 # Flash addr (0xFFDD0000)=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x=
00070000 #=0D
-SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x=
00500000 # Flash addr (0xFFE50000)=0D
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x=
004F0000 # Flash addr (0xFFE40000)=0D
SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x=
00050000 #=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x=
00550000 # Flash addr (0xFFEA0000)=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x=
00540000 # Flash addr (0xFFE90000)=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x=
000EA000 #=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x=
0063A000 # Flash addr (0xFFF8A000)=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x=
0062A000 # Flash addr (0xFFF7A000)=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x=
00006000 #=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x=
00640000 # Flash addr (0xFFF90000)=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x=
00630000 # Flash addr (0xFFF80000)=0D
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D 0x=
00010000 #=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x=
00650000 # Flash addr (0xFFFA0000)=0D
-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x=
00060000 #=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x=
00640000 # Flash addr (0xFFF90000)=0D
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x=
00070000 #=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 6/9] TigerlakeOpenBoardPkg: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Heng Luo <heng.luo@intel.com>
---
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi=
b/PeiFspPolicyInitLib.c | 21 ++++++++++++++++++---
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi=
b/PeiFspPolicyInitLib.inf | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/=
FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c
index fc523e93d1..938b74e5d8 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.c
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.c
@@ -9,7 +9,9 @@
#include <Library/FspWrapperApiLib.h>=0D
#include <Library/BaseMemoryLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/PeiLib.h>=0D
#include <Ppi/FspmArchConfigPpi.h>=0D
+#include <PolicyUpdateMacro.h>=0D
=0D
VOID=0D
EFIAPI=0D
@@ -70,9 +72,11 @@ SiliconPolicyDonePreMem(
)=0D
{=0D
EFI_STATUS Status;=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D
- FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D
- EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D
+ FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D
+ EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D
=0D
FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof =
(FSPM_ARCH_CONFIG_PPI));=0D
if (FspmArchConfigPpi =3D=3D NULL) {=0D
@@ -80,7 +84,6 @@ SiliconPolicyDonePreMem(
return EFI_OUT_OF_RESOURCES;=0D
}=0D
FspmArchConfigPpi->Revision =3D 1;=0D
- FspmArchConfigPpi->NvsBufferPtr =3D NULL;=0D
FspmArchConfigPpi->BootLoaderTolumSize =3D 0;=0D
=0D
FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s=
izeof (EFI_PEI_PPI_DESCRIPTOR));=0D
@@ -98,6 +101,18 @@ SiliconPolicyDonePreMem(
ASSERT_EFI_ERROR (Status);=0D
#endif=0D
=0D
+ //=0D
+ // Initialize S3 Data variable (S3DataPtr). It may be used for warm and =
fast boot paths.=0D
+ //=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -=
%r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));=
=0D
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmArchUpd.NvsBufferPtr, FspmA=
rchConfigPpi->NvsBufferPtr, FspNvsBufferPtr);=0D
+ }=0D
+=0D
//=0D
// Install Policy Ready PPI=0D
// While installed, RC assumes the Policy is ready and finalized. So ple=
ase=0D
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp=
PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk=
g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
index 708fbac08f..0236ae45ae 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.inf
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI=
nitLib/PeiFspPolicyInitLib.inf
@@ -181,3 +181,4 @@
gTianoLogoGuid ## CONSUMES=0D
gCnviConfigGuid ## CONSUMES=0D
gHdAudioPreMemConfigGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 5/9] KabylakeOpenBoardPkg/KabylakeRvp3: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 25 ++++++++++----=
-----------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilicon=
PolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 23 +++++++++-----=
---------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilicon=
PolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 2 +-
4 files changed, 22 insertions(+), 33 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li=
brary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Inte=
l/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpda=
teLibFsp/PeiFspMiscUpdUpdateLib.c
index d8aff1960f..699f4297fa 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -1,7 +1,7 @@
/** @file=0D
Implementation of Fsp Misc UPD Initialization.=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -16,7 +16,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
=0D
-#include <Library/MemoryAllocationLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DebugPrintErrorLevelLib.h>=0D
#include <Library/PciLib.h>=0D
@@ -38,25 +37,21 @@ PeiFspMiscUpdUpdatePreMem (
{=0D
EFI_STATUS Status;=0D
UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
+ VOID *FspNvsBufferPtr;=0D
UINT8 MorControl;=0D
VOID *MorControlPtr;=0D
=0D
//=0D
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and =
fast boot paths.=0D
//=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D PeiGetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- &MemorySavedData,=0D
- &VariableSize=0D
- );=0D
- DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid=
- %r\n", Status));=0D
- DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
-=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ VariableSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &VariableSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -=
%r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", VariableSize));=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
+ }=0D
if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) {=0D
//=0D
// Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_P=
MCON_A[23]),=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar=
y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/Ka=
bylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/Pe=
iSiliconPolicyUpdateLib.c
index 2dce9be63c..22aadc0221 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -398,8 +398,8 @@ SiliconPolicyUpdatePreMem (
SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;=0D
MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;=0D
VOID *Buffer;=0D
- UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
UINT8 SpdAddressTable[4];=0D
=0D
DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));=0D
@@ -430,18 +430,13 @@ SiliconPolicyUpdatePreMem (
// Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI a=
dded in FSP 2.1, hence=0D
// the platform specific S3DataPtr must be used instead.=0D
//=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D PeiGetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- &MemorySavedData,=0D
- &VariableSize=0D
- );=0D
- DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHob=
Guid - %r\n", Status));=0D
- DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D
- if (!EFI_ERROR (Status)) {=0D
- MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData;=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVaria=
bleGuid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGu=
id - %r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize=
));=0D
+ MiscPeiPreMemConfig->S3DataPtr =3D FspNvsBufferPtr;=0D
}=0D
=0D
//=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li=
brary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platf=
orm/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPo=
licyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index f8bec0c852..dacec18cd9 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -1,7 +1,7 @@
## @file=0D
# Provide FSP wrapper platform related function.=0D
#=0D
-# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -80,7 +80,6 @@
PchInfoLib=0D
PchHsioLib=0D
PchPcieRpLib=0D
- MemoryAllocationLib=0D
CpuMailboxLib=0D
DebugPrintErrorLevelLib=0D
SiPolicyLib=0D
@@ -141,7 +140,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar=
y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/=
KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/=
PeiSiliconPolicyUpdateLib.inf
index 5c2da68bf9..4b30ba02ea 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -50,7 +50,7 @@
gHsioPciePreMemConfigGuid ## CONSUMES=0D
gHsioSataPreMemConfigGuid ## CONSUMES=0D
gSaMiscPeiPreMemConfigGuid ## CONSUMES=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
=0D
[Pcd]=0D
gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 4/9] KabylakeOpenBoardPkg/GalagoPro3: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSilic=
onPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 25 +++++++++++-----=
---------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSilic=
onPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
2 files changed, 13 insertions(+), 17 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/=
KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLi=
bFsp/PeiFspMiscUpdUpdateLib.c
index 9d6c0176f6..dbc84631ac 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei=
SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei=
SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -1,7 +1,7 @@
/** @file=0D
Implementation of Fsp Misc UPD Initialization.=0D
=0D
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -16,7 +16,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
=0D
-#include <Library/MemoryAllocationLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DebugPrintErrorLevelLib.h>=0D
#include <Library/PciLib.h>=0D
@@ -38,24 +37,22 @@ PeiFspMiscUpdUpdatePreMem (
{=0D
EFI_STATUS Status;=0D
UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
+ VOID *FspNvsBufferPtr;=0D
UINT8 MorControl;=0D
VOID *MorControlPtr;=0D
=0D
//=0D
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and =
fast boot paths.=0D
//=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D PeiGetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- &MemorySavedData,=0D
- &VariableSize=0D
- );=0D
- DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid=
- %r\n", Status));=0D
- DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ VariableSize =3D 0;=0D
+=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &VariableSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -=
%r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", VariableSize));=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
+ }=0D
=0D
if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) {=0D
//=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platfor=
m/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicy=
UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index 463455c90b..ceefe7639e 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei=
SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei=
SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -1,7 +1,7 @@
## @file=0D
# FSP wrapper silicon policy update library.=0D
#=0D
-# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -81,7 +81,6 @@
PchInfoLib=0D
PchHsioLib=0D
PchPcieRpLib=0D
- MemoryAllocationLib=0D
CpuMailboxLib=0D
DebugPrintErrorLevelLib=0D
SiPolicyLib=0D
@@ -138,7 +137,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 3/9] KabylakeOpenBoardPkg/AspireVn7Dash572G:Use same variable name for FspNvsHob

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 24 +++++++++=
+--------------
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 23 +++++++++=
--------------
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P=
eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 7 ++++---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi=
liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 2 +-
4 files changed, 24 insertions(+), 32 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp=
er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform=
/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon=
PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index d8413d284e..a9b7e446c8 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -1,7 +1,7 @@
/** @file=0D
Implementation of Fsp Misc UPD Initialization.=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -11,7 +11,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>=0D
#include <Library/PciLib.h>=0D
#include <Library/PeiLib.h>=0D
-=0D
#include <FspEas.h>=0D
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
@@ -34,24 +33,21 @@ PeiFspMiscUpdUpdatePreMem (
{=0D
EFI_STATUS Status;=0D
UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
+ VOID *FspNvsBufferPtr;=0D
UINT8 MorControl;=0D
VOID *MorControlPtr;=0D
=0D
//=0D
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and =
fast boot paths.=0D
//=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D PeiGetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- &MemorySavedData,=0D
- &VariableSize=0D
- );=0D
- DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid=
- %r\n", Status));=0D
- DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ VariableSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &VariableSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -=
%r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", VariableSize));=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
+ }=0D
=0D
if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) {=0D
//=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L=
ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int=
el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp=
dateLib/PeiSiliconPolicyUpdateLib.c
index c9dfb17e0a..3764f7c3ac 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/=
PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/=
PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -431,8 +431,8 @@ SiliconPolicyUpdatePreMem (
SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;=0D
MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;=0D
VOID *Buffer;=0D
- UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
UINT8 SpdAddressTable[4];=0D
=0D
DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));=0D
@@ -463,18 +463,13 @@ SiliconPolicyUpdatePreMem (
// Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI a=
dded in FSP 2.1, hence=0D
// the platform specific S3DataPtr must be used instead.=0D
//=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D PeiGetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- &MemorySavedData,=0D
- &VariableSize=0D
- );=0D
- DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHob=
Guid - %r\n", Status));=0D
- DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D
- if (!EFI_ERROR (Status)) {=0D
- MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData;=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVaria=
bleGuid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGu=
id - %r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize=
));=0D
+ MiscPeiPreMemConfig->S3DataPtr =3D FspNvsBufferPtr;=0D
}=0D
=0D
//=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp=
er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/=
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/Pe=
iSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index e4a657c5f1..eac9344b0a 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr=
ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -1,7 +1,7 @@
## @file=0D
# Provide FSP wrapper platform related function.=0D
#=0D
-# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -74,7 +74,6 @@
PchInfoLib=0D
PchHsioLib=0D
PchPcieRpLib=0D
- MemoryAllocationLib=0D
SiPolicyLib=0D
PeiLib=0D
=0D
@@ -134,9 +133,11 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector=0D
=0D
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress=0D
+ gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L=
ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I=
ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy=
UpdateLib/PeiSiliconPolicyUpdateLib.inf
index 0a8cf91b07..4dcc000186 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/=
PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/=
PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -52,7 +52,7 @@
gHsioPciePreMemConfigGuid ## CONSUMES=0D
gHsioSataPreMemConfigGuid ## CONSUMES=0D
gSaMiscPeiPreMemConfigGuid ## CONSUMES=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gIoApicConfigGuid ## CONSUMES=0D
gHpetPreMemConfigGuid ## CONSUMES=0D
gLockDownConfigGuid=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 2/9] CometlakeOpenBoardPkg: Use same variable name for FspNvsHob.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

To simplify the implementation the variable Name/GUID has been
changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid
regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2
or FSP_NON_VOLATILE_STORAGE_HOB.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
---
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUp=
dateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++++------------=
-------------------------------------
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUp=
dateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
2 files changed, 16 insertions(+), 52 deletions(-)

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/CometlakeO=
penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUp=
dateLib.c
index 7dbdfa7c16..9e8606ada9 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -2,7 +2,7 @@
Implementation of Fsp Misc UPD Initialization.=0D
=0D
=0D
- Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
=0D
@@ -17,7 +17,6 @@
#include <FspmUpd.h>=0D
#include <FspsUpd.h>=0D
=0D
-#include <Library/MemoryAllocationLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DebugPrintErrorLevelLib.h>=0D
#include <Library/PciLib.h>=0D
@@ -44,55 +43,21 @@ PeiFspMiscUpdUpdatePreMem (
)=0D
{=0D
EFI_STATUS Status;=0D
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;=0D
- UINTN VariableSize;=0D
- VOID *MemorySavedData;=0D
-=0D
- Status =3D PeiServicesLocatePpi (=0D
- &gEfiPeiReadOnlyVariable2PpiGuid,=0D
- 0,=0D
- NULL,=0D
- (VOID **) &VariableServices=0D
- );=0D
- if (EFI_ERROR (Status)) {=0D
- ASSERT_EFI_ERROR (Status);=0D
- return Status;=0D
+ UINTN FspNvsBufferSize;=0D
+ VOID *FspNvsBufferPtr;=0D
+=0D
+ //=0D
+ // Initialize S3 Data variable (S3DataPtr). It may be used for warm and =
fast boot paths.=0D
+ //=0D
+ FspNvsBufferPtr =3D NULL;=0D
+ FspNvsBufferSize =3D 0;=0D
+ Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG=
uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D
+ if (Status =3D=3D EFI_SUCCESS) {=0D
+ DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -=
%r\n", Status));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));=
=0D
+ FspmUpd->FspmArchUpd.NvsBufferPtr =3D FspNvsBufferPtr;=0D
}=0D
=0D
- VariableSize =3D 0;=0D
- MemorySavedData =3D NULL;=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
- MemorySavedData =3D AllocatePool (VariableSize);=0D
- if (MemorySavedData =3D=3D NULL) {=0D
- ASSERT (MemorySavedData !=3D NULL);=0D
- return EFI_OUT_OF_RESOURCES;=0D
- }=0D
-=0D
- DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));=0D
- Status =3D VariableServices->GetVariable (=0D
- VariableServices,=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &VariableSize,=0D
- MemorySavedData=0D
- );=0D
- if (Status =3D=3D EFI_SUCCESS) {=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
- } else {=0D
- DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe=
moryConfigVariableGuid, Status =3D %r\n", Status));=0D
- ASSERT_EFI_ERROR (Status);=0D
- }=0D
- }=0D
- FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D
=0D
return EFI_SUCCESS;=0D
}=0D
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSil=
iconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/Co=
metlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSili=
conPolicyUpdateLibFsp.inf
index c842b7eef6..94776603c4 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol=
icyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -2,7 +2,7 @@
# Provide FSP wrapper platform related function.=0D
#=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -82,7 +82,6 @@
PchInfoLib=0D
PchHsioLib=0D
PchPcieRpLib=0D
- MemoryAllocationLib=0D
DebugPrintErrorLevelLib=0D
SiPolicyLib=0D
PchGbeLib=0D
@@ -132,7 +131,7 @@
gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D
=0D
[Guids]=0D
- gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## CONSUMES=0D
gTianoLogoGuid ## CONSUMES=0D
gEfiMemoryOverwriteControlDataGuid=0D
=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 1/9] MinPlatformPkg: Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2.

Chiu, Chasel
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678

Implementation should search FSP_NON_VOLATILE_STORAGE_HOB2 firstly
and only search FSP_NON_VOLATILE_STORAGE_HOB when former one is not found.

Also added PeiGetLargeVariable () to support the scenarios where the
variable data size is bigger than a single variable size limit. (stored
across multiple variables)

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig=
.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++------------=
-------------------------------------------------
Platform/Intel/MinPlatformPkg/Library/BaseLargeVariableLib/LargeVariableWr=
iteLib.c | 2 +-
Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c =
| 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++----------
Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/PeiVariableReadLi=
b.c | 4 ++--
Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig=
.inf | 8 ++++++--
Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc =
| 1 +
Platform/Intel/MinPlatformPkg/Include/Library/PeiLib.h =
| 40 +++++++++++++++++++++++++++++++++++-----
Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf =
| 4 +++-
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec =
| 1 +
9 files changed, 176 insertions(+), 82 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/Save=
MemoryConfig.c b/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/=
SaveMemoryConfig.c
index 41ed2550bd..820585f676 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryC=
onfig.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryC=
onfig.c
@@ -2,7 +2,7 @@
This is the driver that locates the MemoryConfigurationData HOB, if it=0D
exists, and saves the data to nvRAM.=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -16,7 +16,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/GlobalVariable.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
#include <Library/BaseMemoryLib.h>=0D
-#include <Protocol/VariableLock.h>=0D
+#include <Library/LargeVariableReadLib.h>=0D
+#include <Library/LargeVariableWriteLib.h>=0D
+#include <Guid/FspNonVolatileStorageHob2.h>=0D
=0D
/**=0D
This is the standard EFI driver point that detects whether there is a=0D
@@ -40,86 +42,71 @@ SaveMemoryConfigEntryPoint (
VOID *VariableData;=0D
UINTN DataSize;=0D
UINTN BufferSize;=0D
- EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;=0D
+ BOOLEAN DataIsIdentical;=0D
=0D
- DataSize =3D 0;=0D
- VariableData =3D NULL;=0D
- GuidHob =3D NULL;=0D
- HobData =3D NULL;=0D
+ DataSize =3D 0;=0D
+ BufferSize =3D 0;=0D
+ VariableData =3D NULL;=0D
+ GuidHob =3D NULL;=0D
+ HobData =3D NULL;=0D
+ DataIsIdentical =3D FALSE;=0D
=0D
//=0D
// Search for the Memory Configuration GUID HOB. If it is not present, =
then=0D
// there's nothing we can do. It may not exist on the update path.=0D
+ // Firstly check version2 FspNvsHob.=0D
//=0D
- GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHobGuid);=0D
+ GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHob2Guid);=0D
if (GuidHob !=3D NULL) {=0D
- HobData =3D GET_GUID_HOB_DATA (GuidHob);=0D
- DataSize =3D GET_GUID_HOB_DATA_SIZE(GuidHob);=0D
+ HobData =3D (VOID *) (UINTN) ((FSP_NON_VOLATILE_STORAGE_HOB2 *) (UINTN=
) GuidHob)->NvsDataPtr;=0D
+ DataSize =3D (UINTN) ((FSP_NON_VOLATILE_STORAGE_HOB2 *) (UINTN) GuidHo=
b)->NvsDataLength;=0D
+ } else {=0D
+ //=0D
+ // Fall back to version1 FspNvsHob=0D
+ //=0D
+ GuidHob =3D GetFirstGuidHob (&gFspNonVolatileStorageHobGuid);=0D
+ if (GuidHob !=3D NULL) {=0D
+ HobData =3D GET_GUID_HOB_DATA (GuidHob);=0D
+ DataSize =3D GET_GUID_HOB_DATA_SIZE (GuidHob);=0D
+ }=0D
+ }=0D
+=0D
+ if (HobData !=3D NULL) {=0D
+ DEBUG ((DEBUG_INFO, "FspNvsHob.NvsDataLength:%d\n", DataSize));=0D
+ DEBUG ((DEBUG_INFO, "FspNvsHob.NvsDataPtr : 0x%x\n", HobData));=0D
if (DataSize > 0) {=0D
//=0D
- // Use the HOB to save Memory Configuration Data=0D
+ // Check if the presently saved data is identical to the data given =
by MRC/FSP=0D
//=0D
- BufferSize =3D DataSize;=0D
- VariableData =3D AllocatePool (BufferSize);=0D
- if (VariableData =3D=3D NULL) {=0D
- return EFI_UNSUPPORTED;=0D
- }=0D
- Status =3D gRT->GetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &BufferSize,=0D
- VariableData=0D
- );=0D
-=0D
+ Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariable=
Guid, &BufferSize, NULL);=0D
if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
- FreePool (VariableData);=0D
- VariableData =3D AllocatePool (BufferSize);=0D
- if (VariableData =3D=3D NULL) {=0D
- return EFI_UNSUPPORTED;=0D
+ if (BufferSize =3D=3D DataSize) {=0D
+ VariableData =3D AllocatePool (BufferSize);=0D
+ if (VariableData !=3D NULL) {=0D
+ Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVa=
riableGuid, &BufferSize, VariableData);=0D
+ if (!EFI_ERROR (Status) && (BufferSize =3D=3D DataSize) && (0 =
=3D=3D CompareMem (HobData, VariableData, DataSize))) {=0D
+ DataIsIdentical =3D TRUE;=0D
+ }=0D
+ FreePool (VariableData);=0D
+ }=0D
}=0D
-=0D
- Status =3D gRT->GetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- NULL,=0D
- &BufferSize,=0D
- VariableData=0D
- );=0D
}=0D
+ Status =3D EFI_SUCCESS;=0D
=0D
- if ( (EFI_ERROR(Status)) || BufferSize !=3D DataSize || 0 !=3D Compa=
reMem (HobData, VariableData, DataSize)) {=0D
- Status =3D gRT->SetVariable (=0D
- L"MemoryConfig",=0D
- &gFspNonVolatileStorageHobGuid,=0D
- (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERV=
ICE_ACCESS),=0D
- DataSize,=0D
- HobData=0D
- );=0D
+ if (!DataIsIdentical) {=0D
+ Status =3D SetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariab=
leGuid, TRUE, DataSize, HobData);=0D
ASSERT_EFI_ERROR (Status);=0D
-=0D
- DEBUG((DEBUG_INFO, "Restored Size is 0x%x\n", DataSize));=0D
- }=0D
-=0D
- //=0D
- // Mark MemoryConfig to read-only if the Variable Lock protocol exis=
ts=0D
- //=0D
- Status =3D gBS->LocateProtocol(&gEdkiiVariableLockProtocolGuid, NULL=
, (VOID **)&VariableLock);=0D
- if (!EFI_ERROR(Status)) {=0D
- Status =3D VariableLock->RequestToLock(VariableLock, L"MemoryConfi=
g", &gFspNonVolatileStorageHobGuid);=0D
- ASSERT_EFI_ERROR(Status);=0D
+ DEBUG ((DEBUG_INFO, "Saved size of FSP / MRC Training Data: 0x%x\n=
", DataSize));=0D
+ } else {=0D
+ DEBUG ((DEBUG_INFO, "FSP / MRC Training Data is identical to data =
from last boot, no need to save.\n"));=0D
}=0D
-=0D
- FreePool (VariableData);=0D
- } else {=0D
- DEBUG((DEBUG_INFO, "Memory save size is %d\n", DataSize));=0D
}=0D
} else {=0D
DEBUG((DEBUG_ERROR, "Memory S3 Data HOB was not found\n"));=0D
}=0D
=0D
//=0D
- // This driver does not produce any protocol services, so always unload =
it.=0D
+ // This driver cannot be unloaded because DxeRuntimeVariableWriteLib con=
structor will register ExitBootServices callback.=0D
//=0D
- return EFI_REQUEST_UNLOAD_IMAGE;=0D
+ return EFI_SUCCESS;=0D
}=0D
diff --git a/Platform/Intel/MinPlatformPkg/Library/BaseLargeVariableLib/Lar=
geVariableWriteLib.c b/Platform/Intel/MinPlatformPkg/Library/BaseLargeVaria=
bleLib/LargeVariableWriteLib.c
index 703aca6fd8..e4b97ef1df 100644
--- a/Platform/Intel/MinPlatformPkg/Library/BaseLargeVariableLib/LargeVaria=
bleWriteLib.c
+++ b/Platform/Intel/MinPlatformPkg/Library/BaseLargeVariableLib/LargeVaria=
bleWriteLib.c
@@ -343,7 +343,7 @@ SetLargeVariable (
// Check that it is possible to store the data using less than=0D
// MAX_VARIABLE_SPLIT variables=0D
//=0D
- if ((DataSize / (VariableSplitSize - MAX_VARIABLE_SPLIT_DIGITS)) > MAX=
_VARIABLE_SPLIT) {=0D
+ if ((DataSize / ((UINTN) VariableSplitSize - MAX_VARIABLE_SPLIT_DIGITS=
)) > MAX_VARIABLE_SPLIT) {=0D
DEBUG ((=0D
DEBUG_ERROR,=0D
"SetLargeVariable: More than %d variables are needed to store the =
data, which exceeds the maximum supported\n",=0D
diff --git a/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c b/Platfo=
rm/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c
index 96dfd588dc..3f8cf761a7 100644
--- a/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c
+++ b/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c
@@ -1,6 +1,6 @@
/** @file=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -9,13 +9,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>=0D
#include <Library/PeiServicesLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/LargeVariableReadLib.h>=0D
#include <Ppi/ReadOnlyVariable2.h>=0D
=0D
/**=0D
- Returns the status whether get the variable success. The function retrie=
ves =0D
- variable through the ReadOnlyVariable2 PPI GetVariable(). The =0D
- returned buffer is allocated using AllocatePool(). The caller is respon=
sible=0D
- for freeing this buffer with FreePool().=0D
+ Returns the status whether get the variable success. The function retrie=
ves=0D
+ variable through the ReadOnlyVariable2 PPI GetVariable().=0D
+=0D
+ If the *Size is 0, the returned buffer is allocated using AllocatePool()=
.=0D
+ The buffer is not expected to be freed as PEI does not support a FreePoo=
l().=0D
+=0D
+ If the *Size is non-0, this function just uses caller allocated *Value.=
=0D
=0D
If Name is NULL, then ASSERT().=0D
If Guid is NULL, then ASSERT().=0D
@@ -108,6 +112,71 @@ PeiGetVariable (
return Status;=0D
}=0D
=0D
+/**=0D
+ This function returns a "large variable". A large variable is stored acr=
oss multiple=0D
+ UEFI Variables. This function retrieves the multiple UEFI Variables usin=
g=0D
+ ReadOnlyVariable2 PPI GetVariable().=0D
+ The function uses AllocatePages () to allocate the buffer.=0D
+ The caller is responsible for freeing this buffer with FreePages().=0D
+=0D
+ If Name is NULL, then ASSERT().=0D
+ If Guid is NULL, then ASSERT().=0D
+ If Value is NULL, then ASSERT().=0D
+=0D
+ @param[in] Name The pointer to a Null-terminated Unicode string.=0D
+ @param[in] Guid The pointer to an EFI_GUID structure=0D
+ @param[out] Value The buffer point saved the variable info.=0D
+ @param[out] Size The buffer size of the variable.=0D
+=0D
+ @return EFI_OUT_OF_RESOURCES Allocate buffer failed.=0D
+ @return EFI_SUCCESS Find the specified variable.=0D
+ @return Others Errors Return errors from call to gRT->GetVar=
iable.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PeiGetLargeVariable (=0D
+ IN CHAR16 *Name,=0D
+ IN EFI_GUID *Guid,=0D
+ OUT VOID **Value,=0D
+ OUT UINTN *Size OPTIONAL=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN VariableSize;=0D
+ VOID *VariableData;=0D
+=0D
+ ASSERT (Name !=3D NULL);=0D
+ ASSERT (Guid !=3D NULL);=0D
+ ASSERT (Value !=3D NULL);=0D
+=0D
+ VariableSize =3D 0;=0D
+ VariableData =3D NULL;=0D
+ Status =3D GetLargeVariable (Name, Guid, &VariableSize, NULL);=0D
+ if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {=0D
+ VariableData =3D AllocatePages (EFI_SIZE_TO_PAGES (VariableSize));=0D
+ if (VariableData =3D=3D NULL) {=0D
+ DEBUG ((DEBUG_ERROR, "Error: Cannot create VariableData, out of memo=
ry!\n"));=0D
+ ASSERT (FALSE);=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+ Status =3D GetLargeVariable (Name, Guid, &VariableSize, VariableData);=
=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "Error: Unable to read UEFI variable Status: %r=
\n", Status));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+ }=0D
+ if (Value !=3D NULL) {=0D
+ *Value =3D VariableData;=0D
+ }=0D
+ if (Size !=3D NULL) {=0D
+ *Size =3D VariableSize;=0D
+ }=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+ return Status;=0D
+}=0D
+=0D
EFI_PEI_FILE_HANDLE=0D
InternalGetFfsHandleFromAnyFv (=0D
IN CONST EFI_GUID *NameGuid=0D
@@ -139,7 +208,7 @@ InternalGetFfsHandleFromAnyFv (
=0D
/**=0D
Finds the file in any FV and gets file Address and Size=0D
- =0D
+=0D
@param[in] NameGuid File GUID=0D
@param[out] Address Pointer to the File Address=0D
@param[out] Size Pointer to File Size=0D
@@ -162,7 +231,7 @@ PeiGetFfsFromAnyFv (
if (FfsHandle =3D=3D NULL) {=0D
return EFI_NOT_FOUND;=0D
}=0D
- =0D
+=0D
//=0D
// Need get size=0D
//=0D
@@ -185,7 +254,7 @@ PeiGetFfsFromAnyFv (
@param[in] SectionInstance The Instance of Section to be found=0D
@param[out] OutSectionBuffer The section found, including SECTION_HEAD=
ER=0D
@param[out] OutSectionSize The size of section found, including SECT=
ION_HEADER=0D
- =0D
+=0D
@retval EFI_SUCCESS Successfull in reading the section fr=
om FV=0D
**/=0D
EFI_STATUS=0D
@@ -263,7 +332,7 @@ PeiGetSectionFromAnyFv (
EFI_COMMON_SECTION_HEADER *Section;=0D
VOID *FileBuffer;=0D
UINTN FileBufferSize;=0D
- =0D
+=0D
Status =3D PeiGetFfsFromAnyFv (NameGuid, &FileBuffer, &FileBufferSize);=
=0D
if (EFI_ERROR(Status)) {=0D
return Status;=0D
@@ -282,6 +351,6 @@ PeiGetSectionFromAnyFv (
*Size =3D SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);=
=0D
*Address =3D (UINT8 *)*Address + sizeof (EFI_COMMON_SECTION_HEADER);=0D
}=0D
- =0D
+=0D
return EFI_SUCCESS;=0D
}=0D
diff --git a/Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/PeiVa=
riableReadLib.c b/Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/=
PeiVariableReadLib.c
index 5eeee12a3c..b7885dd6c2 100644
--- a/Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/PeiVariableR=
eadLib.c
+++ b/Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/PeiVariableR=
eadLib.c
@@ -67,7 +67,7 @@ VarLibGetVariable (
&gEfiPeiReadOnlyVariable2PpiGuid,=0D
0,=0D
NULL,=0D
- &VariablePpi=0D
+ (VOID **) &VariablePpi=0D
);=0D
ASSERT_EFI_ERROR (Status);=0D
if (EFI_ERROR (Status)) {=0D
@@ -134,7 +134,7 @@ VarLibGetNextVariableName (
&gEfiPeiReadOnlyVariable2PpiGuid,=0D
0,=0D
NULL,=0D
- &VariablePpi=0D
+ (VOID **) &VariablePpi=0D
);=0D
ASSERT_EFI_ERROR (Status);=0D
if (EFI_ERROR (Status)) {=0D
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/Save=
MemoryConfig.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfi=
g/SaveMemoryConfig.inf
index 0c8689a6f6..e2dbd2fb49 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryC=
onfig.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryC=
onfig.inf
@@ -1,7 +1,7 @@
### @file=0D
# Component information file for SaveMemoryConfig module=0D
#=0D
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -23,11 +23,14 @@
DebugLib=0D
MemoryAllocationLib=0D
BaseMemoryLib=0D
+ LargeVariableReadLib=0D
+ LargeVariableWriteLib=0D
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
MdeModulePkg/MdeModulePkg.dec=0D
IntelFsp2Pkg/IntelFsp2Pkg.dec=0D
+ MinPlatformPkg/MinPlatformPkg.dec=0D
=0D
[Sources]=0D
SaveMemoryConfig.c=0D
@@ -35,10 +38,11 @@
[Protocols]=0D
gEfiVariableArchProtocolGuid ## CONSUMES=0D
gEfiVariableWriteArchProtocolGuid ## CONSUMES=0D
- gEdkiiVariableLockProtocolGuid=0D
=0D
[Guids]=0D
gFspNonVolatileStorageHobGuid ## CONSUMES=0D
+ gFspNonVolatileStorageHob2Guid ## CONSUMES=0D
+ gFspNvsBufferVariableGuid ## PRODUCES=0D
=0D
[Depex]=0D
gEfiVariableArchProtocolGuid AND=0D
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc b/Pla=
tform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
index d3c668d441..c12189bd9a 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
@@ -41,6 +41,7 @@
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in=
f=0D
!endif=0D
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVaria=
bleReadLibNull.inf=0D
=0D
[LibraryClasses.common.PEI_CORE]=0D
TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/PeiAcpiTimerLib.inf=0D
diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/PeiLib.h b/Platf=
orm/Intel/MinPlatformPkg/Include/Library/PeiLib.h
index d8b1a47c58..eed6502d84 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Library/PeiLib.h
+++ b/Platform/Intel/MinPlatformPkg/Include/Library/PeiLib.h
@@ -1,6 +1,6 @@
/** @file=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <PiPei.h>=0D
=0D
/**=0D
- Returns the status whether get the variable success. The function retrie=
ves =0D
+ Returns the status whether get the variable success. The function retrie=
ves=0D
variable through the ReadOnlyVariable2 PPI GetVariable().=0D
=0D
If the *Size is 0, the returned buffer is allocated using AllocatePool()=
.=0D
- The caller is responsible for freeing this buffer with FreePool().=0D
+ The buffer is not expected to be freed as PEI does not support a FreePoo=
l().=0D
=0D
If the *Size is non-0, this function just uses caller allocated *Value.=
=0D
=0D
@@ -38,9 +38,39 @@ PeiGetVariable (
OUT UINTN *Size=0D
);=0D
=0D
+/**=0D
+ This function returns a "large variable". A large variable is stored acr=
oss multiple=0D
+ UEFI Variables. This function retrieves the multiple UEFI Variables usin=
g=0D
+ ReadOnlyVariable2 PPI GetVariable().=0D
+ The function uses AllocatePages () to allocate the buffer.=0D
+ The caller is responsible for freeing this buffer with FreePages().=0D
+=0D
+ If Name is NULL, then ASSERT().=0D
+ If Guid is NULL, then ASSERT().=0D
+ If Value is NULL, then ASSERT().=0D
+=0D
+ @param[in] Name The pointer to a Null-terminated Unicode string.=0D
+ @param[in] Guid The pointer to an EFI_GUID structure=0D
+ @param[out] Value The buffer point saved the variable info.=0D
+ @param[out] Size The buffer size of the variable.=0D
+=0D
+ @return EFI_OUT_OF_RESOURCES Allocate buffer failed.=0D
+ @return EFI_SUCCESS Find the specified variable.=0D
+ @return Others Errors Return errors from call to gRT->GetVar=
iable.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PeiGetLargeVariable (=0D
+ IN CHAR16 *Name,=0D
+ IN EFI_GUID *Guid,=0D
+ OUT VOID **Value,=0D
+ OUT UINTN *Size OPTIONAL=0D
+ );=0D
+=0D
/**=0D
Finds the file in any FV and gets file Address and Size=0D
- =0D
+=0D
@param[in] NameGuid File GUID=0D
@param[out] Address Pointer to the File Address=0D
@param[out] Size Pointer to File Size=0D
@@ -57,7 +87,7 @@ PeiGetFfsFromAnyFv (
=0D
/**=0D
Finds the section in any FV and gets section Address and Size=0D
- =0D
+=0D
@param[in] NameGuid File GUID=0D
@param[in] SectionType The SectionType of Section to be found=
=0D
@param[in] SectionInstance The Instance of Section to be found=0D
diff --git a/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf b/Plat=
form/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf
index 7e740172a0..bd57cf7870 100644
--- a/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf
+++ b/Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf
@@ -1,7 +1,7 @@
## @file=0D
# Component information file for Board Init Test Library=0D
#=0D
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -20,9 +20,11 @@
PeiServicesLib=0D
MemoryAllocationLib=0D
DebugLib=0D
+ LargeVariableReadLib=0D
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MinPlatformPkg/MinPlatformPkg.dec=0D
=0D
[Sources]=0D
PeiLib.c=0D
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In=
tel/MinPlatformPkg/MinPlatformPkg.dec
index bcb42f0ef9..d6e80a66ce 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -50,6 +50,7 @@
gBdsEventBeforeConsoleAfterTrustedConsoleGuid =3D {0x51e49ff5, 0x28a9, =
0x4159, { 0xac, 0x8a, 0xb8, 0xc4, 0x88, 0xa7, 0xfd, 0xee}}=0D
gBdsEventBeforeConsoleBeforeEndOfDxeGuid =3D {0xfcf26e41, 0xbda6, =
0x4633, { 0xb5, 0x73, 0xd4, 0xb8, 0x0e, 0x6d, 0xd0, 0x78}}=0D
gBdsEventAfterConsoleReadyBeforeBootOptionGuid =3D {0x8eb3d5dc, 0xf4e7, =
0x4b57, { 0xa9, 0xe7, 0x27, 0x39, 0x10, 0xf2, 0x18, 0x9f}}=0D
+ gFspNvsBufferVariableGuid =3D {0x9c7715cd, 0x8d66, =
0x4d2a, { 0x90, 0x0d, 0x01, 0x45, 0x9a, 0x57, 0x59, 0x6b}}=0D
=0D
[LibraryClasses]=0D
=0D
--=20
2.28.0.windows.1


[edk2-platforms: PATCH v5 0/9] MinPlatformPkg: Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2.

Chiu, Chasel
 

V5:
Fix GCC build failure in LargeVariableWriteLib.c

V4:
. Switched to LargeVariableRead(Write)Lib in SaveMemoryConfig driver
. Fixed tailing white space issue in PeiLib.c/.h
. Updated function descriptions for PeiGetVariable() and PeiGetLargeVariable()
. Added VariableReadLib to CorePeiLib.dsc for all platforms
. Fixed white space issue in GalagoPro3/.../PeiFspMiscUpdUpdateLib.c

V3:
Fix another GCC build failure.

V2:
Fix GCC build failures.

V1:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3678

Implementation should search FSP_NON_VOLATILE_STORAGE_HOB2 firstly
and only search FSP_NON_VOLATILE_STORAGE_HOB when former one is not found.

Also added PeiGetLargeVariable () to support the scenarios where the
variable data size is bigger than a single variable size limit.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>

Chasel Chiu (9):
MinPlatformPkg: Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2.
CometlakeOpenBoardPkg: Use same variable name for FspNvsHob.
KabylakeOpenBoardPkg/AspireVn7Dash572G:Use same variable name for
FspNvsHob
KabylakeOpenBoardPkg/GalagoPro3: Use same variable name for FspNvsHob.
KabylakeOpenBoardPkg/KabylakeRvp3: Use same variable name for
FspNvsHob.
TigerlakeOpenBoardPkg: Use same variable name for FspNvsHob.
WhiskeylakeOpenBoardPkg: Use same variable name for FspNvsHob.
WhitleyOpenBoardPkg: Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2.
WhitleySiliconPkg: Use same variable name for FspNvsHob.

Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++++-------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 24 ++++++++++--------------
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 23 +++++++++--------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 25 +++++++++++--------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 25 ++++++++++---------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 23 +++++++++--------------
Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Library/BaseLargeVariableLib/LargeVariableWriteLib.c | 2 +-
Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------
Platform/Intel/MinPlatformPkg/Library/PeiVariableReadLib/PeiVariableReadLib.c | 4 ++--
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c | 21 ++++++++++++++++++---
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++---------------------------------------------------
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 63 ++++++++++++---------------------------------------------------
Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.c | 29 +++++++++++++++++++++++------
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c | 35 +++++++++--------------------------
Platform/Intel/CometlakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 7 ++++---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 2 +-
Platform/Intel/MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf | 8 ++++++--
Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiLib.dsc | 1 +
Platform/Intel/MinPlatformPkg/Include/Library/PeiLib.h | 40 +++++++++++++++++++++++++++++++++++-----
Platform/Intel/MinPlatformPkg/Library/PeiLib/PeiLib.inf | 4 +++-
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 1 +
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 1 +
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 5 ++---
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 4 ++--
Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf | 18 +++++++++---------
Platform/Intel/WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf | 4 +++-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 1 +
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf | 3 ++-
33 files changed, 345 insertions(+), 369 deletions(-)

--
2.28.0.windows.1


Re: [PATCH v1 1/1] StandaloneMmPkg: To support CLANGPDB build

Marvin Häuser
 

Hey Ard,

Thanks for commenting!

On 14.10.21 11:09, Ard Biesheuvel wrote:
On Thu, 14 Oct 2021 at 11:08, Marvin Häuser <mhaeuser@posteo.de> wrote:
Hey Steven,

As I said, I prefer my patch, but this would work too of course.
I talked about the PIE stuff with Ard before, so maybe he has an opinion
on this? :)

(Small correction for my last e-mail, of course we are not *guaranteed*
there are *no* relocations in .text, but they'd all point to GOT (or
whatever else the target uses for PIE), and references will probably be
relative; for ARM architectures I remember Ard talking about specific
kinds of relocations being avoided entirely).
Hello all,

As I understand it, we are talking about a native PE/COFF toolchain
here that does not rely on GenFw for ELF to PE/COFF conversion, right?
Yep.

If so, there is no way the self-relocation is going to work anyway, so
whether we pass -fpie or not for AArch64 is immaterial here.
It's not quite, because with -fpie it errors (also maybe PE/COFF PIE will be supported some day?). We can also pass -fno-pie and have some other way to kill compilation for CLANGPDB ARM/AARCH64, but it must not just silently succeed when this is eventually supported.

Best regards,
Marvin





Re: [PATCH v1 1/1] StandaloneMmPkg: To support CLANGPDB build

Ard Biesheuvel
 

On Thu, 14 Oct 2021 at 11:08, Marvin Häuser <mhaeuser@posteo.de> wrote:

Hey Steven,

As I said, I prefer my patch, but this would work too of course.
I talked about the PIE stuff with Ard before, so maybe he has an opinion
on this? :)

(Small correction for my last e-mail, of course we are not *guaranteed*
there are *no* relocations in .text, but they'd all point to GOT (or
whatever else the target uses for PIE), and references will probably be
relative; for ARM architectures I remember Ard talking about specific
kinds of relocations being avoided entirely).
Hello all,

As I understand it, we are talking about a native PE/COFF toolchain
here that does not rely on GenFw for ELF to PE/COFF conversion, right?
If so, there is no way the self-relocation is going to work anyway, so
whether we pass -fpie or not for AArch64 is immaterial here.


Re: [PATCH v1 1/1] StandaloneMmPkg: To support CLANGPDB build

Marvin Häuser
 

Hey Steven,

As I said, I prefer my patch, but this would work too of course.
I talked about the PIE stuff with Ard before, so maybe he has an opinion on this? :)

(Small correction for my last e-mail, of course we are not *guaranteed* there are *no* relocations in .text, but they'd all point to GOT (or whatever else the target uses for PIE), and references will probably be relative; for ARM architectures I remember Ard talking about specific kinds of relocations being avoided entirely).

Best regards,
Marvin

On 14.10.21 11:02, Shi, Steven wrote:

Hi Marvin,

How about we limit the -fno-pie option only apply on IA32 and X64 like below?

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf b/StandaloneMmPkg/Core/StandaloneMmCore.inf

[BuildOptions]

   GCC:*_*_*_CC_FLAGS = -fpie

   GCC:*_*_*_DLINK_FLAGS = -Wl,-z,text,-Bsymbolic,-pie

+  CLANGPDB:*_*_ *IA32*_CC_FLAGS= -fno-pie

+  CLANGPDB:*_*_ *X64*_CC_FLAGS= -fno-pie

diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf

[BuildOptions]

   GCC:*_*_*_CC_FLAGS = -fpie

+  CLANGPDB:*_*_ *IA32*_CC_FLAGS= -fno-pie

+  CLANGPDB:*_*_ *X64*_CC_FLAGS= -fno-pie

Thanks

Steven Shi

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Marvin
Häuser
Sent: Thursday, October 14, 2021 4:05 PM
To: Yang, JiyangX <jiyangx.yang@intel.com>; devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Sami Mujawar
<sami.mujawar@arm.com>; Yao, Jiewen <jiewen.yao@intel.com>; Supreeth
Venkatesh <supreeth.venkatesh@arm.com>; Vitaly Cheptsov
<vit9696@protonmail.com>; Shi, Steven <steven.shi@intel.com>
Subject: Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: To support
CLANGPDB build
Hey Jiyang,
NO! Please do not. :)
Yes, this fixes build, but the AARCH64 core (I did not check ARM)
depends on self-relocation as it is loaded in-place at a location
unknown at compile-time. PIE helps ensure there are no relocations in
.text among other things. I know CLANGPDB does not support
ARM/AARCH64
yet, but if it is added, this may generate binaries with more dangerous
relocations, which means the chance of executing an instruction that
requires relocation without relocating first (relocation is done in C
code now!) is significantly higher. We do not need PIE for IA32 or X64
at all (or more specifically, we only need it for ARM-based
architectures as of now), so I prefer my patch which makes that
explicit. Though we can theoretically use your solution when limited to
non-ARM architectures if you really dislike my patch that much.
I'd prefer to hear from the ARM core maintainers before making any move.
Best regards,
Marvin
On 14.10.21 05:12, Jiyang Yang wrote:
the flag "-fpie" is passed for all builds with a GCC family toolchain,
including CLANGPDB, but CLANGPDB does not support this flag, it will
report "clang: error: unsupported option '-fpie' for target
'x86_64-unknown-windows-gnu'". So we add the CLANGPDB option "-fno-
pie"
later to overwrite it.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org
<mailto:ardb+tianocore@kernel.org>>

Cc: Sami Mujawar <sami.mujawar@arm.com <mailto:sami.mujawar@arm.com>>
Cc: Jiewen Yao <jiewen.yao@intel.com <mailto:jiewen.yao@intel.com>>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com
<mailto:supreeth.venkatesh@arm.com>>

Cc: Vitaly Cheptsov <vit9696@protonmail.com
<mailto:vit9696@protonmail.com>>

Cc: Marvin Häuser <mhaeuser@posteo.de <mailto:mhaeuser@posteo.de>>
Cc: Steven Shi <steven.shi@intel.com <mailto:steven.shi@intel.com>>
Signed-off-by: Jiyang Yang <jiyangx.yang@intel.com
<mailto:jiyangx.yang@intel.com>>

---
StandaloneMmPkg/Core/StandaloneMmCore.inf | 2
++
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmC
oreEntryPoint.inf | 1 +
   2 files changed, 3 insertions(+)
diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf
b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 56042b7b39f4..3213142523f4 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -79,3 +79,5 @@
   [BuildOptions]
     GCC:*_*_*_CC_FLAGS = -fpie
     GCC:*_*_*_DLINK_FLAGS = -Wl,-z,text,-Bsymbolic,-pie
+  CLANGPDB:*_*_*_CC_FLAGS = -fno-pie
+  CLANGPDB:*_*_*_DLINK_FLAGS =
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
index 1762586cfa02..ef69e07d2c07 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
@@ -56,3 +56,4 @@
   [BuildOptions]
     GCC:*_*_*_CC_FLAGS = -fpie
+  CLANGPDB:*_*_*_CC_FLAGS = -fno-pie


Re: [PATCH V2 06/28] MdePkg: Update BaseIoLibIntrinsicSev to support Tdx

Gerd Hoffmann
 

Hi,

Hmm, I guess we should move the pcd then so it cam be used more widely.
Confidential computing has an impact beyond just cpu, it's also memory, io and
more.
How about define ConfidentialComputingAttr PCD in MdePkg.dec?
Looks sensible to me.

take care,
Gerd


Re: [PATCH v1 1/1] StandaloneMmPkg: To support CLANGPDB build

Steven Shi
 

Hi Marvin,

How about we limit the -fno-pie option only apply on IA32 and X64 like below?

 

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf b/StandaloneMmPkg/Core/StandaloneMmCore.inf

[BuildOptions]

   GCC:*_*_*_CC_FLAGS = -fpie

   GCC:*_*_*_DLINK_FLAGS = -Wl,-z,text,-Bsymbolic,-pie

+  CLANGPDB:*_*_ IA32_CC_FLAGS= -fno-pie

+  CLANGPDB:*_*_ X64_CC_FLAGS= -fno-pie

 

diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf

[BuildOptions]

   GCC:*_*_*_CC_FLAGS = -fpie

+  CLANGPDB:*_*_ IA32_CC_FLAGS= -fno-pie

+  CLANGPDB:*_*_ X64_CC_FLAGS= -fno-pie

 

 

Thanks

Steven Shi

 

 

> -----Original Message-----

> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Marvin

> Häuser

> Sent: Thursday, October 14, 2021 4:05 PM

> To: Yang, JiyangX <jiyangx.yang@...>; devel@edk2.groups.io

> Cc: Ard Biesheuvel <ardb+tianocore@...>; Sami Mujawar

> <sami.mujawar@...>; Yao, Jiewen <jiewen.yao@...>; Supreeth

> Venkatesh <supreeth.venkatesh@...>; Vitaly Cheptsov

> <vit9696@...>; Shi, Steven <steven.shi@...>

> Subject: Re: [edk2-devel] [PATCH v1 1/1] StandaloneMmPkg: To support

> CLANGPDB build

>

> Hey Jiyang,

>

> NO! Please do not. :)

> Yes, this fixes build, but the AARCH64 core (I did not check ARM)

> depends on self-relocation as it is loaded in-place at a location

> unknown at compile-time. PIE helps ensure there are no relocations in

> .text among other things. I know CLANGPDB does not support

> ARM/AARCH64

> yet, but if it is added, this may generate binaries with more dangerous

> relocations, which means the chance of executing an instruction that

> requires relocation without relocating first (relocation is done in C

> code now!) is significantly higher. We do not need PIE for IA32 or X64

> at all (or more specifically, we only need it for ARM-based

> architectures as of now), so I prefer my patch which makes that

> explicit. Though we can theoretically use your solution when limited to

> non-ARM architectures if you really dislike my patch that much.

>

> I'd prefer to hear from the ARM core maintainers before making any move.

>

> Best regards,

> Marvin

>

> On 14.10.21 05:12, Jiyang Yang wrote:

> > the flag "-fpie" is passed for all builds with a GCC family toolchain,

> > including CLANGPDB, but CLANGPDB does not support this flag, it will

> > report "clang: error: unsupported option '-fpie' for target

> > 'x86_64-unknown-windows-gnu'". So we add the CLANGPDB option "-fno-

> pie"

> > later to overwrite it.

> >

> > Cc: Ard Biesheuvel <ardb+tianocore@...>

> > Cc: Sami Mujawar <sami.mujawar@...>

> > Cc: Jiewen Yao <jiewen.yao@...>

> > Cc: Supreeth Venkatesh <supreeth.venkatesh@...>

> > Cc: Vitaly Cheptsov <vit9696@...>

> > Cc: Marvin Häuser <mhaeuser@...>

> > Cc: Steven Shi <steven.shi@...>

> > Signed-off-by: Jiyang Yang <jiyangx.yang@...>

> > ---

> >   StandaloneMmPkg/Core/StandaloneMmCore.inf                                         | 2

> ++

> >

> StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmC

> oreEntryPoint.inf | 1 +

> >   2 files changed, 3 insertions(+)

> >

> > diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf

> b/StandaloneMmPkg/Core/StandaloneMmCore.inf

> > index 56042b7b39f4..3213142523f4 100644

> > --- a/StandaloneMmPkg/Core/StandaloneMmCore.inf

> > +++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf

> > @@ -79,3 +79,5 @@

> >   [BuildOptions]

> >     GCC:*_*_*_CC_FLAGS = -fpie

> >     GCC:*_*_*_DLINK_FLAGS = -Wl,-z,text,-Bsymbolic,-pie

> > +  CLANGPDB:*_*_*_CC_FLAGS = -fno-pie

> > +  CLANGPDB:*_*_*_DLINK_FLAGS =

> > diff --git

> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm

> CoreEntryPoint.inf

> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm

> CoreEntryPoint.inf

> > index 1762586cfa02..ef69e07d2c07 100644

> > ---

> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm

> CoreEntryPoint.inf

> > +++

> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm

> CoreEntryPoint.inf

> > @@ -56,3 +56,4 @@

> >

> >   [BuildOptions]

> >     GCC:*_*_*_CC_FLAGS = -fpie

> > +  CLANGPDB:*_*_*_CC_FLAGS = -fno-pie

>

>

>

>

>

 


Re: [PATCH v9 32/32] UefiCpuPkg/MpInitLib: Use SEV-SNP AP Creation NAE event to launch APs

Gerd Hoffmann
 

On Wed, Oct 13, 2021 at 11:57:13AM -0500, Brijesh Singh wrote:
From: Tom Lendacky <thomas.lendacky@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Use the SEV-SNP AP Creation NAE event to create and launch APs under
SEV-SNP. This capability will be advertised in the SEV Hypervisor
Feature Support PCD (PcdSevEsHypervisorFeatures).
Acked-by: Gerd Hoffmann <kraxel@redhat.com>

take care,
Gerd


Re: [PATCH v9 31/32] OvmfPkg/AmdSev: expose the SNP reserved pages through configuration table

Gerd Hoffmann
 

On Wed, Oct 13, 2021 at 11:57:12AM -0500, Brijesh Singh wrote:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Now that both the secrets and cpuid pages are reserved in the HOB,
extract the location details through fixed PCD and make it available
to the guest OS through the configuration table.
Acked-by: Gerd Hoffmann <kraxel@redhat.com>


Re: [PATCH v9 30/32] OvmfPkg/PlatformPei: mark cpuid and secrets memory reserved in EFI map

Gerd Hoffmann
 

On Wed, Oct 13, 2021 at 11:57:11AM -0500, Brijesh Singh wrote:
When SEV-SNP is active, the CPUID and Secrets memory range contains the
information that is used during the VM boot. The content need to be persist
across the kexec boot. Mark the memory range as Reserved in the EFI map
so that guest OS or firmware does not use the range as a system RAM.
Why is this needed? Isn't the complete firmware memory tagged as
reserved anyway?

take care,
Gerd


Re: [PATCH v9 29/32] OvmfPkg/MemEncryptSevLib: skip page state change for Mmio address

Gerd Hoffmann
 

On Wed, Oct 13, 2021 at 11:57:10AM -0500, Brijesh Singh wrote:
The SetMemoryEncDec() is used by the higher level routines to set or clear
the page encryption mask for system RAM and Mmio address. When SEV-SNP is
active, in addition to set/clear page mask it also updates the RMP table.
The RMP table updates are required for the system RAM address and not
the Mmio address.

Add a new parameter in SetMemoryEncDec() to tell whether the specified
address is Mmio. If its Mmio then skip the page state change in the RMP
table.
Acked-by: Gerd Hoffmann <kraxel@redhat.com>

2321 - 2340 of 84265