Date   

[edk2-platforms][PATCH V2 4/5] WhitleyOpenBoardPkg/Acpi: Use binary AcpiPlatform driver

Oram, Isaac W
 

This uses the binary AcpiPlatform driver from FvLateOpenBoard to
produce and update more complete ACPI tables.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 4 ----
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 2 --
2 files changed, 6 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index f0a83fffd1..a6e40e7904 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -741,10 +741,6 @@

$(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf

- $(PLATFORM_PKG)/Acpi/AcpiTables/AcpiPlatform.inf {
- <LibraryClasses>
- BoardAcpiTableLib|$(RP_PKG)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
- }

$(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf {
<LibraryClasses>
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
index d128f61b9d..1ae7435aa0 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
@@ -672,8 +672,6 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

- INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
-
INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf

[FV.FvOsBoot]
--
2.27.0.windows.1


[edk2-platforms][PATCH V2 3/5] WhitleySiliconPkg/Interfaces: Remove PcdsDynamic use.

Oram, Isaac W
 

Remove Dynamic PCD options in favor of DynamicEx only.
Delete some dead code and misleading comments.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 4 ++--
Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 2 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 19 ++++---------------
3 files changed, 7 insertions(+), 18 deletions(-)

diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
index 3a6d87dd7f..902abd30f8 100644
--- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
@@ -516,7 +516,7 @@
WhitleySiliconPkg/WhitleySiliconPkg.dec
}

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32|0x00000020
gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x00000021
gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035
@@ -526,7 +526,7 @@
gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C
gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D

-[PcdsDynamic, PcdsDynamicEx]
+[PcdsDynamicEx]
gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00000048
gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0x00000049
gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
index f30558b5d8..7b027b58c6 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
@@ -49,7 +49,7 @@
gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|FALSE|BOOLEAN|0x10000038
gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]

## Indicates the platform type: desktop, mobile or server.<BR><BR>
# 0 - desktop<BR>
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index ea8fd0a49b..c4993cb897 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -601,17 +601,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
[PcdsFeatureFlag]
gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x10000001
gPlatformTokenSpaceGuid.PcdMultiPchEnabled |FALSE|BOOLEAN|0x10000003
- gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF0000007
-#gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF000000F
-#gSiPkgTokenSpaceGuid.PcdAmtEnable |FALSE|BOOLEAN|0xF0000010
-#gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF0000011
-#gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x00010055
-##
-## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined
-## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS reporting.
-## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information.
-##
-#gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047
+ gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF0000007

gPlatformTokenSpaceGuid.PcdUseRxTxMultiCastRegisters|FALSE|BOOLEAN|0x10000002

@@ -624,8 +614,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,

gSiPkgTokenSpaceGuid.PcdHardwareLocalSemaphores|FALSE|BOOLEAN|0xF0000012

-### [PcdsFixedAtBuild, PcdsPatchableInModule]
-[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic, PcdsDynamicEx]
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
#
# SouthCluster
#
@@ -670,7 +659,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
# VTD PCDs End
#

-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
#
# SouthCluster
#
@@ -968,7 +957,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
#
gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E

-[PcdsDynamic, PcdsDynamicEx]
+[PcdsDynamicEx]
gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007
gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A
gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D
--
2.27.0.windows.1


[edk2-platforms][PATCH V2 2/5] WhitleySiliconPkg/Interfaces: Update to Server-RC-0.2.2.003a

Oram, Isaac W
 

This updates IIO interface adding AltAttenTable and the corresponding
PCD and defaults.
Adds HideWriteDataParityLogs.
Updates PCD defaults for a variety of settings.
Removes Dynamic PCD options in favor of DynamicEx only.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc | 271 +++++++++++++-------
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 2 +-
Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h | 1 +
4 files changed, 181 insertions(+), 94 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
index e356c917fe..0e00a72fcd 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
@@ -1088,6 +1088,7 @@ gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1
gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2 # Time Window (Gen3/4)
gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1 # Gen3 Link Degradation
gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1 # Gen4 Link Degradation
+gStructPcdTokenSpaceGuid.PcdSetup.HideWriteDataParityLogs|0x1 # Hide Data Parity Error Logs
gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1 # IIO Dma Error
gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1 # IIO Dmi Error
gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1 # IIO Error Registers Clear
@@ -1540,6 +1541,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[81]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[82]|0x0 # ACPI PME Interrupt
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[83]|0x0 # ACPI PME Interrupt
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1 # ATS
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[0]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[1]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[2]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[3]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[4]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[5]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[6]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[7]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[8]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[9]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[10]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[11]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[12]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[13]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[14]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[15]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[16]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[17]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[18]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[19]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[20]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[21]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[22]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[23]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[24]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[25]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[26]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[27]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[28]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[29]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[30]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[31]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[32]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[33]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[34]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[35]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[36]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[37]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[38]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[39]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[40]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[41]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[42]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[43]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[44]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[45]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[46]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[47]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[48]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[49]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[50]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[51]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[52]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[53]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[54]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[55]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[56]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[57]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[58]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[59]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[60]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[61]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[62]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[63]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[64]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[65]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[66]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[67]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[68]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[69]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[70]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[71]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[72]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[73]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[74]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[75]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[76]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[77]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[78]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[79]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[80]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[81]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[82]|0x0 # Alt ATTEN Table
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[83]|0x0 # Alt ATTEN Table
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1 # DMA
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1 # DMA
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1 # DMA
@@ -5089,8 +5174,8 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[80]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[81]|0x0 # P2P Memory Read
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[82]|0x0 # P2P Memory Read
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[83]|0x0 # P2P Memory Read
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x1 # PCIe Atomic Operation Request Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 # PCIe Latency Tolerance Reporting
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x2 # PCIe Atomic Op Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 # PCIe LTR Support
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCUF6Hide|0x0 # Hide PCU Func 6
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[1]|0x0 # Hide Port?
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[2]|0x0 # Hide Port?
@@ -5176,7 +5261,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[81]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[82]|0x0 # Hide Port?
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[83]|0x0 # Hide Port?
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pci64BitResourceAllocation|0x1 # PCI 64-Bit Resource Allocation
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x1 # PCIe 10-bit Tag Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x2 # PCIe 10-bit Tag Enable
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[0]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[1]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[2]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3
@@ -5299,90 +5384,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[78]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[79]|0x0 # Port 5D
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAcpiHotPlugEnable|0x0 # PCIe ACPI Hot Plug
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAllocatingFlow|0x1 # PCIe Allocating Write Flows
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x2 # PCI-E ASPM Support
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x2 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x4 # PCI-E ASPM Support
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x4 # PCI-E ASPM Support
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieBiosTrainEnable|0x1 # PCIe Train by BIOS
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[0]|0x1 # PCI-E Port Clocking
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[1]|0x1 # PCI-E Port Clocking
@@ -5636,7 +5721,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[80
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[81]|0x1 # Data Link Feature Exchange
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[82]|0x1 # Data Link Feature Exchange
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[83]|0x1 # Data Link Feature Exchange
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x1 # PCIe Extended Tag Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x2 # PCIe Extended Tag Support
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieGlobalAspm|0x1 # PCI-E ASPM Support (Global)
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugEnable|0x0 # PCIe Hot Plug
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[1]|0x2 # Hot Plug Capable
@@ -6311,7 +6396,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[80]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 # Link Speed
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 # Link Speed
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 # Link Speed
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x0 # PCIe PTM Enable
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x2 # PCIe PTM Support
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 # Pcie Relaxed Ordering
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 # PCIe Slot Item Control
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1 # PCIe Slot 1 OpROM
@@ -7570,7 +7655,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SetMemTested|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ShortStroke2GB|0x0 # 2GB Short Stroke Configuration
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmartTestKey|0x0 # SmartTestKey
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmbSpdAccess|0x0 # SPD-SMBUS Access
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 # Sparing SW Error Match Threshold
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 # SW Per Bank Threshold
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintEn|0x0 # SPD Print
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintLength|0x0 # SPD Print Length
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1 # Publish SRAT
@@ -7705,7 +7790,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[3]|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1 # PDA
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprErrInjTest|0x0 # PPR Error Injection test
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2 # PPR Type
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1 # MRC Promote Warnings
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x0 # MRC Promote Warnings
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1 # Promote Warnings
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1 # Read Vref Centering
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2 # 2x Refresh Enable
@@ -7761,11 +7846,11 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRTP|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWR|0x0 # tWR
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWTR|0x0 # tWTR
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x2 # Throttling Mode
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x0 # Correctable Error Time Window
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x18 # SW Correctable Error Time Window
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1 # Turnaround Time Optimization
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1 # Turnaround Time Optimization PMem
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1 # Tx Eq Training
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1 # Volatile Memory Mode
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x0 # Volatile Memory Mode
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1 # Write Vref Centering
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1 # Bus Resources Allocation Ratio
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1 # Bus Resources Allocation Ratio
diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
index 91eace9aa0..3a6d87dd7f 100644
--- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
@@ -251,7 +251,7 @@
gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0
gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2
gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x0033
+ gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a

#
# MRC DEFAULT SETTINGS
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
index 7df44e93c3..a820cc6c25 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
@@ -437,6 +437,7 @@ typedef struct {
UINT8 VtdPciAcsCtlBit2;
UINT8 VtdPciAcsCtlBit3;
UINT8 VtdPciAcsCtlBit4;
+ UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup
} SOCKET_IIO_CONFIGURATION;
#pragma pack()

diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
index df11dda735..a8e3e69255 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
@@ -379,6 +379,7 @@ typedef struct {
UINT8 DisPMETOAck[MAX_TOTAL_PORTS];
UINT8 ACPIHP[MAX_TOTAL_PORTS];
UINT8 ACPIPM[MAX_TOTAL_PORTS];
+ UINT8 AltAttenTable[MAX_TOTAL_PORTS];
UINT8 SRIS[MAX_TOTAL_PORTS];
UINT8 TXEQ[MAX_TOTAL_PORTS];
UINT8 EcrcGenEn[MAX_TOTAL_PORTS];
--
2.27.0.windows.1


[edk2-platforms][PATCH V2 1/5] WhitleyOpenBoardPkg/Smbios: Add SMBIOS PCD

Oram, Isaac W
 

This adds PCD that need to be produced by the board port to properly
populate the FvOpenBoardPkg SMBIOS support and generate reasonable
SMBIOS tables.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 107 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 5 +-
2 files changed, 110 insertions(+), 2 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
index 8e0b674505..fb4383d484 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -47,6 +47,7 @@
#OEM SKU
gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } }
gPlatformKtiEparamUpdateDataGuid = { 0x7bc065cf, 0xafe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } }
+ gSmbiosTablesTokenSpaceGuid = { 0x5e80ad48, 0xf240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } }
gPlatformGpioInitDataGuid = { 0x9282563e, 0xae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } }
#
# UBA_END
@@ -250,6 +251,7 @@

## This value is used to save memory address of MRC data structure.
gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041
+ gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042

#
# IMR0 programming values
@@ -289,6 +291,93 @@
# FALSE - Disable Intel(R) TXT feature on the platform
gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x3000000f

+ #
+ # SMBIOS Type 0 - BIOS Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B000000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B000001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0x5B000002
+
+ #
+ # SMBIOS Type 1 - System Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID*|0x5B010000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*|0x5B010001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5B010002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID*|0x5B010003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0x5B010004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B010005
+
+ #
+ # SMBIOS Type 2 - Base Board (or Module) Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|VOID*|0x5B020000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VOID*|0x5B020001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|0x5B020002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|VOID*|0x5B020003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*|0x5B020004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"TBD"|VOID*|0x5B020005
+
+ #
+ # SMBIOS Type 3 - System Enclosure or Chassis Information
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOID*|0x5B030000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x5B030001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOID*|0x5B030002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0x5B030003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|0x5B030004
+
+ #
+ # SMBIOS Type 11 - OEM Strings
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B0001
+
+ #
+ # SMBIOS Type 12 - System Configuration Options
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|0x5B0C0001
+
+ #
+ # SMBIOS Type 14 - Group Associations
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001
+
+ #
+ # SMBIOS Type 17 - Memory Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00|UINT8|0x5B110000
+
+ #
+ # SMBIOS Type 27 - Cooling Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD"|VOID*|0x5B1B0000
+
+ #
+ # SMBIOS Type 28 - Temperature Probe
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"TBD"|VOID*|0x5B1C0000
+
+ #
+ # SMBIOS Type 34 - Management Device
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"TBD"|VOID*|0x5B220000
+
+ #
+ # SMBIOS Type 35 - Management Device Component
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDescription|"TBD"|VOID*|0x5B230000
+
+ #
+ # SMBIOS Type 39 - System Power Supply
+ #
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TBD"|VOID*|0x5B270000
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"TBD"|VOID*|0x5B270001
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer|"TBD"|VOID*|0x5B270002
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber|"TBD"|VOID*|0x5B270003
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumber|"TBD"|VOID*|0x5B270004
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNumber|"TBD"|VOID*|0x5B270005
+ gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLevel|"TBD"|VOID*|0x5B270006
+
[PcdsFeatureFlag]
gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00000020

@@ -366,6 +455,24 @@
gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008

gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009
+# Form factor is MemoryFormFactorDimm by default
+# MemoryFormFactorOther = 0x01
+# MemoryFormFactorUnknown = 0x02
+# MemoryFormFactorSimm = 0x03
+# MemoryFormFactorSip = 0x04
+# MemoryFormFactorChip = 0x05
+# MemoryFormFactorDip = 0x06
+# MemoryFormFactorZip = 0x07
+# MemoryFormFactorProprietaryCard = 0x08
+# MemoryFormFactorDimm = 0x09
+# MemoryFormFactorTsop = 0x0A
+# MemoryFormFactorRowOfChips = 0x0B
+# MemoryFormFactorRimm = 0x0C
+# MemoryFormFactorSodimm = 0x0D
+# MemoryFormFactorSrimm = 0x0E
+# MemoryFormFactorFbDimm = 0x0F
+# MemoryFormFactorDie = 0x10
+ gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010

#
# USB
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index dc3dd0e026..f0a83fffd1 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -649,8 +649,9 @@
# Beware of circular dependencies on PCD if you want to use another DebugLib instance.
#
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
- NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD
}
$(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
$(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
--
2.27.0.windows.1


[edk2-platforms][PATCH V2 0/5] WhitleyOpenBoardPkg: Enable VT-D support

Oram, Isaac W
 

This patch series enables VT-D support in the WhitleyOpenBoardPkg.
For the initial patch, I missed that there was a different AcpiPlatform driver required. This patch series
incorporates that requirement and the additional changes that requires.
The AcpiPlatform driver leverages SMBIOS and the AcpiVtd driver to update ACPI tables ultimately providing the VT-D
support.

The original V1 patch for VT-D has been updated to match file naming convention (VTD to Vtd) and to match the
proprietary binary signature format used.

This complete support for VT-D is accomplished by:
Including additional SMBIOS support in FvLateOpenBoard.fv
Including additional ACPI table support in FvLateOpenBoard.fv
Including proprietary AcpiPlatform driver in FvLateOpenBoard.fv
Updating to FSP 2.2.0.3A where the additional FvLateOpenBoard content is present
Adding FvLateOpenBoard.fv DynamicEx PCD support
Adding open source AcpiVtd driver to patch ACPI tables called by AcpiPlatform.

SMBIOS table content is customizable via DynamicEx PCD added.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Cc: Manish Jha <manishj@ami.com>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>

Isaac Oram (4):
WhitleyOpenBoardPkg/Smbios: Add SMBIOS PCD
WhitleySiliconPkg/Interfaces: Update to Server-RC-0.2.2.003a
WhitleySiliconPkg/Interfaces: Remove PcdsDynamic use.
WhitleyOpenBoardPkg/Acpi: Use binary AcpiPlatform driver

Oram, Isaac W (1):
WhitleyOpenBoardPkg: Enable VT-D support

Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c | 604 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf | 66 +++
Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h | 53 ++
Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h | 109 ++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 111 ++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 10 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 3 +-
Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc | 271 ++++++---
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 6 +-
Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 2 +-
Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h | 4 +
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 19 +-
14 files changed, 1140 insertions(+), 120 deletions(-)
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h

--
2.27.0.windows.1


Re: [PATCH 5/5] Platform/RaspberryPi: Disconnect/shutdown all drivers before reboot

Ard Biesheuvel
 

On Tue, 5 Oct 2021 at 23:25, Jeremy Linton <jeremy.linton@arm.com> wrote:

Hi,

On 10/5/21 5:11 AM, Ard Biesheuvel wrote:
On Sat, 2 Oct 2021 at 02:52, Jeremy Linton <jeremy.linton@arm.com> wrote:

In theory we should be properly cleaning up all the device drivers before
pulling the big switch. Particularly the partition mgr will issue
flush commands to attached disks as it goes down. This assures that
devices running in WB mode (that correctly handle flush/sync/etc) commands
are persisted to physical media before we hit reset.

Without this, there are definitly cases where the relevant specifications
don't guarantee persistence of data in their buffers in the face of
reset conditions. We can't really do anything about the many
devices that don't honor persistance requests but we can start here.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Library/ResetLib/ResetLib.c | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)

diff --git a/Platform/RaspberryPi/Library/ResetLib/ResetLib.c b/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
index a70eee485d..036f619cb5 100644
--- a/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
+++ b/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
@@ -19,11 +19,54 @@
#include <Library/TimerLib.h>
#include <Library/EfiResetSystemLib.h>
#include <Library/ArmSmcLib.h>
+#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h>

#include <IndustryStandard/ArmStdSmc.h>

+
+/**
+ Disconnect everything.
+ Modified from the UEFI 2.3 spec (May 2009 version)
+
+ @retval EFI_SUCCESS The operation was successful.
+
+**/
STATIC

+EFI_STATUS
+DisconnectAll(
Space before (

+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleIndex;
+
+ //
+ // Retrieve the list of all handles from the handle database
+ //
+ Status = gBS->LocateHandleBuffer (
+ AllHandles,
+ NULL,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (!EFI_ERROR (Status)) {
I understand that this code is copy/pasted but I'd still prefer to
avoid the 'success handling' anti pattern here.
Sure.


if (EFI_ERROR (Status)) {
return Status;
}

+ for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+ Status = gBS->DisconnectController (
+ HandleBuffer[HandleIndex],
+ NULL,
+ NULL
+ );
+ }
+ gBS->FreePool(HandleBuffer);
+ }
+ return (EFI_SUCCESS);
No need for ()
Yup


+}
+
+
/**
Resets the entire platform.

@@ -57,6 +100,7 @@ LibResetSystem (
if (Delay != 0) {
DEBUG ((DEBUG_INFO, "Platform will be reset in %d.%d seconds...\n",
Delay / 1000000, (Delay % 1000000) / 100000));
+ DisconnectAll ();
Capture Status here and ASSERT_EFI_ERROR() ??

Maybe it is overkill, and maybe DisconnectController() fails
spuriously, so I am not entirely sure, but adding a local function
that returns a value and then ignore it seems slightly sloppy to me.
Which makes the above bits about failure returns sorta redundant as I
should probably just make DisconnectAll() void. There isn't really
anything to do with a failed return other than print a message and
ignore it.

Works for me.



MicroSecondDelay (Delay);
}
}
--
2.13.7


Re: [PATCH 5/5] Platform/RaspberryPi: Disconnect/shutdown all drivers before reboot

Jeremy Linton
 

Hi,

On 10/5/21 5:11 AM, Ard Biesheuvel wrote:
On Sat, 2 Oct 2021 at 02:52, Jeremy Linton <jeremy.linton@arm.com> wrote:

In theory we should be properly cleaning up all the device drivers before
pulling the big switch. Particularly the partition mgr will issue
flush commands to attached disks as it goes down. This assures that
devices running in WB mode (that correctly handle flush/sync/etc) commands
are persisted to physical media before we hit reset.

Without this, there are definitly cases where the relevant specifications
don't guarantee persistence of data in their buffers in the face of
reset conditions. We can't really do anything about the many
devices that don't honor persistance requests but we can start here.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Library/ResetLib/ResetLib.c | 44 ++++++++++++++++++++++++
1 file changed, 44 insertions(+)

diff --git a/Platform/RaspberryPi/Library/ResetLib/ResetLib.c b/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
index a70eee485d..036f619cb5 100644
--- a/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
+++ b/Platform/RaspberryPi/Library/ResetLib/ResetLib.c
@@ -19,11 +19,54 @@
#include <Library/TimerLib.h>
#include <Library/EfiResetSystemLib.h>
#include <Library/ArmSmcLib.h>
+#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h>

#include <IndustryStandard/ArmStdSmc.h>

+
+/**
+ Disconnect everything.
+ Modified from the UEFI 2.3 spec (May 2009 version)
+
+ @retval EFI_SUCCESS The operation was successful.
+
+**/
STATIC

+EFI_STATUS
+DisconnectAll(
Space before (

+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleIndex;
+
+ //
+ // Retrieve the list of all handles from the handle database
+ //
+ Status = gBS->LocateHandleBuffer (
+ AllHandles,
+ NULL,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (!EFI_ERROR (Status)) {
I understand that this code is copy/pasted but I'd still prefer to
avoid the 'success handling' anti pattern here.
Sure.

if (EFI_ERROR (Status)) {
return Status;
}

+ for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+ Status = gBS->DisconnectController (
+ HandleBuffer[HandleIndex],
+ NULL,
+ NULL
+ );
+ }
+ gBS->FreePool(HandleBuffer);
+ }
+ return (EFI_SUCCESS);
No need for ()
Yup


+}
+
+
/**
Resets the entire platform.

@@ -57,6 +100,7 @@ LibResetSystem (
if (Delay != 0) {
DEBUG ((DEBUG_INFO, "Platform will be reset in %d.%d seconds...\n",
Delay / 1000000, (Delay % 1000000) / 100000));
+ DisconnectAll ();
Capture Status here and ASSERT_EFI_ERROR() ??
Maybe it is overkill, and maybe DisconnectController() fails
spuriously, so I am not entirely sure, but adding a local function
that returns a value and then ignore it seems slightly sloppy to me.
Which makes the above bits about failure returns sorta redundant as I should probably just make DisconnectAll() void. There isn't really anything to do with a failed return other than print a message and ignore it.



MicroSecondDelay (Delay);
}
}
--
2.13.7


Re: [PATCH 2/5] Platform/RaspberryPi: Expand locking to cover return data

Jeremy Linton
 

Hi,

On 10/5/21 5:12 AM, Ard Biesheuvel wrote:
On Sat, 2 Oct 2021 at 02:52, Jeremy Linton <jeremy.linton@arm.com> wrote:

While debugging problems with the GET/SET_CLOCK mailbox calls it appeared
that the locking in most of the mailbox commands isn't perfectly
correct. All UEFI firmware calls to the RPi mailbox share a single
mDmaBuffer which is used to fill out the command passed to the vc firmware,
and record its response. The buffer is protected by mMailboxLock, yet in
many cases the result of the request is copied from the buffer after the
lock has been released. This doesn't currently appear to be causing any
problems, but should probably be fixed anyway.

There are a couple other minor tweaks in this patch that are hard to
justify on their own, one is a bit of whitespace cleanup, and the other is
the addition of a debug message to print the returned clock rate for the
requested clock. This latter print would have immediatly shown that the vc
firmware was returning 0 as the emmc clock rate rather than something
reasonable.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
This fails to apply for me - can you rebase onto the last
edk2-platform master please?
Sure. Is it whitespace, or general conflicts? I noticed that groups.io's web UI looked like I had MIME linebreaks sprinked through my patch despite specifying 8bit ASCII. I flirted with 7-bit ASCII with some of the previous patches, but its pretty clear that the arm foss server is mangling what it thinks are MIME emails and putting cr/lf's changes its behavior a bit.


Let me try and force the 7bit again, which git rejects if it finds utf in the files (and a few of them had it in the past <sigh>).



---
.../Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c | 102 ++++++++++++---------
1 file changed, 59 insertions(+), 43 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c b/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
index bf74148bbb..29719aa5ec 100644
--- a/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
+++ b/Platform/RaspberryPi/Drivers/RpiFirmwareDxe/RpiFirmwareDxe.c
@@ -203,7 +203,6 @@ RpiFirmwareSetPowerState (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);

if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
@@ -219,6 +218,7 @@ RpiFirmwareSetPowerState (
__FUNCTION__, PowerState ? "en" : "dis", DeviceId));
Status = EFI_DEVICE_ERROR;
}
+ ReleaseSpinLock (&mMailboxLock);

return Status;
}
@@ -266,18 +266,20 @@ RpiFirmwareGetArmMemory (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);

if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Base = Cmd->TagBody.Base;
*Size = Cmd->TagBody.Size;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -323,17 +325,18 @@ RpiFirmwareGetMacAddress (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

CopyMem (MacAddress, Cmd->TagBody.MacAddress, sizeof (Cmd->TagBody.MacAddress));
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -378,17 +381,17 @@ RpiFirmwareGetSerial (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Serial = Cmd->TagBody.Serial;
+ ReleaseSpinLock (&mMailboxLock);
// Some platforms return 0 or 0x0000000010000000 for serial.
// For those, try to use the MAC address.
if ((*Serial == 0) || ((*Serial & 0xFFFFFFFF0FFFFFFFULL) == 0)) {
@@ -441,17 +444,18 @@ RpiFirmwareGetModel (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Model = Cmd->TagBody.Model;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -496,17 +500,18 @@ RpiFirmwareGetModelRevision (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Revision = Cmd->TagBody.Revision;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -538,17 +543,18 @@ RpiFirmwareGetFirmwareRevision (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Revision = Cmd->TagBody.Revision;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -831,18 +837,19 @@ RpiFirmwareGetFbSize (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Width = Cmd->TagBody.Width;
*Height = Cmd->TagBody.Height;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -872,16 +879,18 @@ RpiFirmwareFreeFb (VOID)
Cmd->EndTag = 0;

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);
- ReleaseSpinLock (&mMailboxLock);

if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -935,19 +944,20 @@ RpiFirmwareAllocFb (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*Pitch = Cmd->Pitch.Pitch;
*FbBase = Cmd->AllocFb.AlignmentBase - BCM2836_DMA_DEVICE_OFFSET;
*FbSize = Cmd->AllocFb.Size;
+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -999,13 +1009,12 @@ RpiFirmwareGetCommmandLine (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

@@ -1013,6 +1022,7 @@ RpiFirmwareGetCommmandLine (
if (Cmd->TagHead.TagValueSize >= BufferSize &&
Cmd->CommandLine[Cmd->TagHead.TagValueSize - 1] != '\0') {
DEBUG ((DEBUG_ERROR, "%a: insufficient buffer size\n", __FUNCTION__));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_OUT_OF_RESOURCES;
}

@@ -1026,6 +1036,7 @@ RpiFirmwareGetCommmandLine (
CommandLine[Cmd->TagHead.TagValueSize] = '\0';
}

+ ReleaseSpinLock (&mMailboxLock);
return EFI_SUCCESS;
}

@@ -1075,18 +1086,20 @@ RpiFirmwareSetClockRate (
Cmd->TagBody.SkipTurbo = SkipTurbo ? 1 : 0;
Cmd->EndTag = 0;

+ DEBUG ((DEBUG_ERROR, "%a: Request clock rate %X = %d\n", __FUNCTION__, ClockId, ClockRate));
Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -1131,20 +1144,23 @@ RpiFirmwareGetClockRate (
Cmd->TagHead.TagValueSize = 0;
Cmd->TagBody.ClockId = ClockId;
Cmd->EndTag = 0;
-
+
Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

*ClockRate = Cmd->TagBody.ClockRate;
+ ReleaseSpinLock (&mMailboxLock);
+
+ DEBUG ((DEBUG_ERROR, "%a: Get Clock Rate return: ClockRate=%d ClockId=%X\n", __FUNCTION__, *ClockRate, ClockId));
+
return EFI_SUCCESS;
}

@@ -1191,7 +1207,7 @@ RpiFirmwareGetMinClockRate (
{
return RpiFirmwareGetClockRate (ClockId, RPI_MBOX_GET_MIN_CLOCK_RATE, ClockRate);
}
-
+
#pragma pack()
typedef struct {
UINT32 ClockId;
@@ -1236,16 +1252,17 @@ RpiFirmwareSetClockState (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
+ ReleaseSpinLock (&mMailboxLock);
return EFI_DEVICE_ERROR;
}

+ ReleaseSpinLock (&mMailboxLock);
+
return EFI_SUCCESS;
}

@@ -1297,16 +1314,15 @@ RpiFirmwareSetGpio (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
}
+ ReleaseSpinLock (&mMailboxLock);
}
-
+
STATIC
VOID
EFIAPI
@@ -1361,8 +1377,6 @@ RpiFirmwareNotifyXhciReset (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
@@ -1370,6 +1384,8 @@ RpiFirmwareNotifyXhciReset (
__FUNCTION__, Status, Cmd->BufferHead.Response));
}

+ ReleaseSpinLock (&mMailboxLock);
+
return Status;
}

@@ -1424,8 +1440,6 @@ RpiFirmwareNotifyGpioGetCfg (

*Polarity = Cmd->TagBody.Polarity;

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
@@ -1433,6 +1447,8 @@ RpiFirmwareNotifyGpioGetCfg (
__FUNCTION__, Status, Cmd->BufferHead.Response));
}

+ ReleaseSpinLock (&mMailboxLock);
+
return Status;
}

@@ -1471,8 +1487,8 @@ RpiFirmwareNotifyGpioSetCfg (

Status = RpiFirmwareNotifyGpioGetCfg (Gpio, &Result);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Failed to get GPIO polarity\n", __FUNCTION__));
- Result = 0; //default polarity
+ DEBUG ((DEBUG_ERROR, "%a: Failed to get GPIO polarity\n", __FUNCTION__));
+ Result = 0; //default polarity
}


@@ -1488,7 +1504,7 @@ RpiFirmwareNotifyGpioSetCfg (
Cmd->BufferHead.Response = 0;
Cmd->TagHead.TagId = RPI_MBOX_SET_GPIO_CONFIG;
Cmd->TagHead.TagSize = sizeof (Cmd->TagBody);
-
+
Cmd->TagBody.Gpio = 128 + Gpio;
Cmd->TagBody.Direction = Direction;
Cmd->TagBody.Polarity = Result;
@@ -1501,17 +1517,17 @@ RpiFirmwareNotifyGpioSetCfg (

Status = MailboxTransaction (Cmd->BufferHead.BufferSize, RPI_MBOX_VC_CHANNEL, &Result);

- ReleaseSpinLock (&mMailboxLock);
-
if (EFI_ERROR (Status) ||
Cmd->BufferHead.Response != RPI_MBOX_RESP_SUCCESS) {
DEBUG ((DEBUG_ERROR,
"%a: mailbox transaction error: Status == %r, Response == 0x%x\n",
__FUNCTION__, Status, Cmd->BufferHead.Response));
}
-
- RpiFirmwareSetGpio (Gpio,!State);
-
+
+ ReleaseSpinLock (&mMailboxLock);
+
+ RpiFirmwareSetGpio (Gpio,!State);
+

return Status;
}
@@ -1540,7 +1556,7 @@ STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL mRpiFirmwareProtocol = {
RPiFirmwareGetModelInstalledMB,
RpiFirmwareNotifyXhciReset,
RpiFirmwareGetCurrentClockState,
- RpiFirmwareSetClockState,
+ RpiFirmwareSetClockState,
RpiFirmwareNotifyGpioSetCfg
};

--
2.13.7


Re: [PATCH v3 12/28] AmpereAltraPkg: Add Ac01PcieLib library instance

Leif Lindholm
 

On Mon, Oct 04, 2021 at 19:03:40 +0700, Nhi Pham wrote:
Hi Leif,

There are two comments that I would like to clarify with you.

On 23/09/2021 20:49, Leif Lindholm wrote:
+VOID
+Ac01PcieMmioWr (
+ UINT64 Addr,
+ UINT32 Val
+ )
+{
+ Ac01PcieCsrOut32Serdes ((VOID *)Addr, (UINT32)Val);
+}
+
+VOID
+Ac01PciePuts (
Wait, what. We have *two* sets of output overlays in this patch?
This function is consumed by PCIe PHY library (PHYLib). We are making this
wrapper function to conform with the function prototype defined by PHYLib.

We will reduce DEBUG_PCIE_PHY by using directly the DEBUG (). Does it look
good to you?
It's still a little bit awkward, but if that's the only way to get
debug out of PCYLib...

+VOID
+Ac01PcieDelay (
+ UINT32 Val
+ )
+{
+ MicroSecondDelay (Val);
No, use MicroSecondDelay directly.
Seems above. This wrapper function is to conform with the function prototype
consumed by PHYLib. It's hard to change it.
So, I'm assuming this PHYLib is a library shared across multiple
codebases?

Would it be possible for PHYLib to link in ArmArchTimerLib directly
and wrap this there instead? Something about this integration just
feels kind of backwards to me.

Because we now have (sort of) an undocumented dircular dependency:
this driver declares a dependency of PciePhyLib, but that library
needs to be manually initialized by this driver.

/
Leif


Re: Mergify is no longer auto closing personal Github PRs

Michael D Kinney
 

Hi Rebecca,

Yes. This is the new behavior after changes were added in July 9, 2021.

https://github.com/tianocore/edk2/commit/b491eace373ea3fa435a0136db3c38e0360e6f11#diff-a3528dea46dcf4932a9c3dfdd1a9e320daeed9256f3906d4174915470add4189

.mergify: Simplify Mergify rules using GitHub status checks

* Enable Mergify queue feature to support auto rebase when
'push' label is set and gauarntee that all EDK II CI checks
are run before merging in changes with linear history.
* Use status checks configured in GitHub branch protections
* Allow non EDK II Maintainers to create a PR
Requires an EDK II Maintainer to accept the change and
request merge by adding 'push' label. Only EDK II Maintainers
have ability to set/clear labels.
* Do not automatically close PRs for personal builds.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

Developers that submit personal builds are responsible for closing
them if they are no longer required. This allows the same PR to be
used if the developer wants to fix issues on the same branch.

We will likely have to do periodic review to close PRs that are left
open for an extended period of time.

Mike

-----Original Message-----
From: Rebecca Cran <rebecca@bsdio.com>
Sent: Tuesday, October 5, 2021 8:24 AM
To: devel@edk2.groups.io; Leif Lindholm <leif@nuviainc.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Andrew Fish
<afish@apple.com>
Subject: Mergify is no longer auto closing personal Github PRs

I noticed that Mergify is no longer auto closing personal builds: for
example https://github.com/tianocore/edk2/pull/2026 is still open.

Compare that to https://github.com/tianocore/edk2/pull/1708 where
mergify commented "All checks passed. Auto close personal build."


--

Rebecca Cran


Re: Python2.7 is not working with the EDK2 build system

Andrew Fish
 

Should we move to require a min Python version at some point?

On Oct 5, 2021, at 9:48 AM, Cole <crobinso@redhat.com> wrote:

On 9/6/21 9:18 PM, gaoliming wrote:
Bob:

Yes. Python3 is the formal support. We recommend user to use Python3.
But, if user meets the issue in Python2, user can still report the issue
in BaseTools. Its priority may be low. For this case, it is the
regression issue caused by the recent change. The patch owner is also
identified. So, I suggest the patch owner to follow up and enhance his
patch.
Sorry for the delayed response, I was on paternity leave since August.

I haven't seen the actual error in this thread. Is there a clear python
error being thrown? Maybe the fix is simple but I can't

But as mentioned elsewhere, python2 has been End of Life since Jan 1
2020, over 1.5 years ago. It's going to become increasingly difficult to
keep code working on python2 and latest python3.

- Cole






Re: 回复: [edk2-devel] Python2.7 is not working with the EDK2 build system

Cole
 

On 9/6/21 9:18 PM, gaoliming wrote:
Bob:

 Yes. Python3 is the formal support. We recommend user to use Python3.
But, if user meets the issue in Python2, user can still report the issue
in BaseTools. Its priority may be low. For this case, it is the
regression issue caused by the recent change. The patch owner is also
identified. So, I suggest the patch owner to follow up and enhance his
patch.
Sorry for the delayed response, I was on paternity leave since August.

I haven't seen the actual error in this thread. Is there a clear python
error being thrown? Maybe the fix is simple but I can't

But as mentioned elsewhere, python2 has been End of Life since Jan 1
2020, over 1.5 years ago. It's going to become increasingly difficult to
keep code working on python2 and latest python3.

- Cole


Re: [PATCH v1 0/2] ACPI 6.4 SBSA generic watchdog renaming

Sami Mujawar
 

Merged as 06a326caf125..942c9bd357d8

Thanks.

Regards,

Sami Mujawar

On 16/08/2021 03:52 PM, Chris Jones wrote:
Bugzilla: 3565 (https://bugzilla.tianocore.org/show_bug.cgi?id=3565)

This patch series updates the Acpiview GTDT parser and DynamicTables
GTDT generator to support ACPI 6.4. This involves the use of Acpi64.h
which requires the "SBSA Generic Watchdog" structure to be renamed to the
"Arm Generic Watchdog" strucutre.

The changes can be seen at: https://github.com/chris-jones-arm/edk2/tree/1822_64_acpi_generic_watchdog_v1

Chris Jones (2):
DynamicTablesPkg: Rename SBSA generic watchdog
ShellPkg: Update Acpiview GTDT parser to ACPI 6.4

.../Include/ArmNameSpaceObjects.h | 8 +--
.../Acpi/Arm/AcpiGtdtLibArm/GtdtGenerator.c | 60 +++++++++----------
.../Parsers/Gtdt/GtdtParser.c | 14 ++---
.../UefiShellAcpiViewCommandLib.c | 2 +-
4 files changed, 42 insertions(+), 42 deletions(-)


Re: [PATCH v1] DynamicTablesPkg: Update FADT generator to ACPI 6.4

Sami Mujawar
 

Merged as 862e814de403..06a326caf125

Thanks.

Regards,

Sami Mujawar

On 17/08/2021 02:50 PM, Chris Jones wrote:
Bugzilla: 3568 (https://bugzilla.tianocore.org/show_bug.cgi?id=3568)

Update the FADT generator to use Acpi64.h. As the FADT revision tracks
the ACPI revision this updates the minor revision value generated.

Mantis ID for change: https://mantis.uefi.org/mantis/view.php?id=2105

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/FadtGenerator.c | 104 ++++++++++----------
1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/FadtGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/FadtGenerator.c
index b748c982b285a8f6c012c0e08fb95c9904f47730..b4ebd463da02ca37f22b73413b038471081f64e7 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/FadtGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/FadtGenerator.c
@@ -1,11 +1,11 @@
/** @file
FADT Table Generator
- Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
+ Copyright (c) 2017 - 2021, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Reference(s):
- - ACPI 6.3 Specification, January 2019
+ - ACPI 6.4 Specification, January 2021
**/
@@ -32,8 +32,8 @@ Requirements:
/** This macro defines the FADT flag options for ARM Platforms.
*/
-#define FADT_FLAGS (EFI_ACPI_6_3_HW_REDUCED_ACPI | \
- EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE)
+#define FADT_FLAGS (EFI_ACPI_6_4_HW_REDUCED_ACPI | \
+ EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE)
/** This macro defines the valid mask for the FADT flag option
if HW_REDUCED_ACPI flag in the table is set.
@@ -42,47 +42,47 @@ Requirements:
22-31 (reserved).
Valid bits are:
- EFI_ACPI_6_3_WBINVD BIT0
- EFI_ACPI_6_3_PWR_BUTTON BIT4
- EFI_ACPI_6_3_SLP_BUTTON BIT5
- EFI_ACPI_6_3_FIX_RTC BIT6
- EFI_ACPI_6_3_DCK_CAP BIT9
- EFI_ACPI_6_3_RESET_REG_SUP BIT10
- EFI_ACPI_6_3_SEALED_CASE BIT11
- EFI_ACPI_6_3_HEADLESS BIT12
- EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15
- EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18
- EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
- EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20
- EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21
+ EFI_ACPI_6_4_WBINVD BIT0
+ EFI_ACPI_6_4_PWR_BUTTON BIT4
+ EFI_ACPI_6_4_SLP_BUTTON BIT5
+ EFI_ACPI_6_4_FIX_RTC BIT6
+ EFI_ACPI_6_4_DCK_CAP BIT9
+ EFI_ACPI_6_4_RESET_REG_SUP BIT10
+ EFI_ACPI_6_4_SEALED_CASE BIT11
+ EFI_ACPI_6_4_HEADLESS BIT12
+ EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15
+ EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18
+ EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19
+ EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20
+ EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21
*/
#define VALID_HARDWARE_REDUCED_FLAG_MASK ( \
- EFI_ACPI_6_3_WBINVD | \
- EFI_ACPI_6_3_PWR_BUTTON | \
- EFI_ACPI_6_3_SLP_BUTTON | \
- EFI_ACPI_6_3_FIX_RTC | \
- EFI_ACPI_6_3_DCK_CAP | \
- EFI_ACPI_6_3_RESET_REG_SUP | \
- EFI_ACPI_6_3_SEALED_CASE | \
- EFI_ACPI_6_3_HEADLESS | \
- EFI_ACPI_6_3_USE_PLATFORM_CLOCK | \
- EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL | \
- EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE | \
- EFI_ACPI_6_3_HW_REDUCED_ACPI | \
- EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE)
+ EFI_ACPI_6_4_WBINVD | \
+ EFI_ACPI_6_4_PWR_BUTTON | \
+ EFI_ACPI_6_4_SLP_BUTTON | \
+ EFI_ACPI_6_4_FIX_RTC | \
+ EFI_ACPI_6_4_DCK_CAP | \
+ EFI_ACPI_6_4_RESET_REG_SUP | \
+ EFI_ACPI_6_4_SEALED_CASE | \
+ EFI_ACPI_6_4_HEADLESS | \
+ EFI_ACPI_6_4_USE_PLATFORM_CLOCK | \
+ EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL | \
+ EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE | \
+ EFI_ACPI_6_4_HW_REDUCED_ACPI | \
+ EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE)
#pragma pack(1)
-/** The AcpiFadt is a template EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE
+/** The AcpiFadt is a template EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE
structure used for generating the FADT Table.
Note: fields marked with "{Template}" will be updated dynamically.
*/
STATIC
-EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
+EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
ACPI_HEADER (
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
),
// UINT32 FirmwareCtrl
0,
@@ -91,7 +91,7 @@ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
// UINT8 Reserved0
EFI_ACPI_RESERVED_BYTE,
// UINT8 PreferredPmProfile
- EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED, // {Template}: Power Management Profile
+ EFI_ACPI_6_4_PM_PROFILE_UNSPECIFIED, // {Template}: Power Management Profile
// UINT16 SciInt
0,
// UINT32 SmiCmd
@@ -160,37 +160,37 @@ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = {
0,
// UINT32 Flags
FADT_FLAGS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg
NULL_GAS,
// UINT8 ResetValue
0,
// UINT16 ArmBootArch
- EFI_ACPI_6_3_ARM_PSCI_COMPLIANT, // {Template}: ARM Boot Architecture Flags
+ EFI_ACPI_6_4_ARM_PSCI_COMPLIANT, // {Template}: ARM Boot Architecture Flags
// UINT8 MinorRevision
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
// UINT64 XFirmwareCtrl
0,
// UINT64 XDsdt
0,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg
NULL_GAS,
- // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+ // EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
NULL_GAS,
// UINT64 HypervisorVendorIdentity
EFI_ACPI_RESERVED_QWORD // {Template}: Hypervisor Vendor ID
@@ -532,7 +532,7 @@ BuildFadtTable (
This,
(EFI_ACPI_DESCRIPTION_HEADER*)&AcpiFadt,
AcpiTableInfo,
- sizeof (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE)
+ sizeof (EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE)
);
if (EFI_ERROR (Status)) {
DEBUG ((
@@ -614,9 +614,9 @@ ACPI_TABLE_GENERATOR FadtGenerator = {
// Generator Description
L"ACPI.STD.FADT.GENERATOR",
// ACPI Table Signature
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
// ACPI Table Revision supported by this Generator
- EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
// Minimum supported ACPI Table Revision
EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
// Creator ID


Mergify is no longer auto closing personal Github PRs

Rebecca Cran
 

I noticed that Mergify is no longer auto closing personal builds: for example https://github.com/tianocore/edk2/pull/2026 is still open.

Compare that to https://github.com/tianocore/edk2/pull/1708 where mergify commented "All checks passed. Auto close personal build."


--

Rebecca Cran


Re: [PATCH V3 00/12] Migrate ArmVirtPkg modules to OvmfPkg

Abner Chang
 

Hi Ard,
This way reduces the impact of MdePkg. We can try it.

Thanks
Abner


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Ard Biesheuvel <ardb@...>
Sent: Tuesday, October 5, 2021 5:30 PM
To: edk2-devel-groups-io <devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>; Leif Lindholm <leif@...>; Sami Mujawar <sami.mujawar@...>; Jiewen Yao <jiewen.yao@...>; Jordan Justen <jordan.l.justen@...>; Gerd Hoffmann <kraxel@...>; Schaefer, Daniel <daniel.schaefer@...>; Sunil V L <sunilvl@...>; Liming Gao <gaoliming@...>; Zhiguang Liu <zhiguang.liu@...>; Michael D Kinney <michael.d.kinney@...>
Subject: Re: [edk2-devel] [PATCH V3 00/12] Migrate ArmVirtPkg modules to OvmfPkg
 
On Thu, 30 Sept 2021 at 03:43, Abner Chang <abner.chang@...> wrote:
>
> In V3: Address comments on V2.
> In V2: Remove HPE license on the files that just moved around or
>        the changes in the file are just code removal.
>
> edk2 BZ #: 3665
> edk2 platform corresponding changes will be submitted after
> this pactch set is reviewed.
>
> This pacthes set is to migrate some modules from ArmVirtPkg
> to under OvmfPkg for the upcoming RiscVVirtPkg that can leverage
> those modules without the dependency with Arm*Pkg.
>
> The modules moved from ArmVirtPkg to OvmfPkg are,
> - FdtClientDxe
> - PciPcdProducerLib
> - HighMemDxe
> - QemuFwCfgLib
> - FdtPciHostBridgeLib
> - VirtioFdtDxe
>
> Below PCDs are moved to under MdePkg and leverage by RiscVVirtPkg.
> This change also remove the dependency on ArmPkg of OvmfPkg.
> - PcdPciIoTranslation
> - PcdPciIoTranslation
> - PcdPciMmio32(64)Translation
>
> Signed-off-by: Abner Chang <abner.chang@...>
> Cc: Ard Biesheuvel <ardb+tianocore@...>
> Cc: Leif Lindholm <leif@...>
> Cc: Sami Mujawar <sami.mujawar@...>
> Cc: Jiewen Yao <jiewen.yao@...>
> Cc: Jordan Justen <jordan.l.justen@...>
> Cc: Gerd Hoffmann <kraxel@...>
> Cc: Daniel Schaefer <daniel.schaefer@...>
> Cc: Sunil V L <sunilvl@...>
> Cc: Liming Gao <gaoliming@...>
> Cc: Zhiguang Liu <zhiguang.liu@...>
> Cc: Michael D Kinney <michael.d.kinney@...>
>
> Abner Chang (12):
>   ArmVirtPkg/FdtClintDxe: Move FdtClientDxe to EmbeddedPkg
>   MdePkg: Add PcdPciIoTranslation PCD
>   ArmPkg: Use PcdPciIoTranslation PCD from MdePkg
>   ArmVirtPkg/FdtPciPcdProducerLib: Relocate PciPcdProducerLib to OvmfPkg
>   ArmVirtPkg/HighMemDxe: Relocate HighMemDxe to OvmfPkg
>   OvmfPkg/HighMemDxe: Add RISC-V in the supported arch.
>   ArmVirtPkg/QemuFwCfgLib: Relocate QemuFwCfgLib to OvmfPkg
>   OvmfPkg/QemuFwCfgLibMMIO: Add RISC-V arch support
>   MdePkg: Add PcdPciMmio32(64)Translation PCDs
>   ArmVirtPkg/FdtPciHostBridgeLib: Relocate FdtPciHostBridgeLib to
>     OvmfPkg/Fdt
>   OvmfPkg/FdtPciHostBridgeLib: Add RISC-V in the supported arch.
>   ArmVirtPkg/VirtioFdtDxe: Relocate VirtioFdtDxe to OvmfPkg/Fdt
>

Hello all,

These patches look ok to me, but I wonder if the MdePkg maintainers
are happy taking these PCD declaration changes. Translations for PCIe
are typically defined per host bridge, and I would rather move away
from using PCDs for this entirely than 'promote' them by carrying them
in MdePkg.

As this issue is somewhat orthogonal to what Abner is trying to fix,
perhaps it is better to avoid MdePkg changes for now, and just
duplicate these PCDs into OvmfPkg. This is reasonable, given that we
know that QEMU only exposes a single host bridge.

The one in ArmPkg can hopefully be removed and replaced with something
that is more appropriate.


>  ArmPkg/ArmPkg.dec                             | 15 ++++++--------
>  ArmVirtPkg/ArmVirtPkg.dec                     |  3 ---
>  EmbeddedPkg/EmbeddedPkg.dec                   |  1 +
>  MdePkg/MdePkg.dec                             | 12 +++++++++++
>  ArmVirtPkg/ArmVirtCloudHv.dsc                 | 18 ++++++++---------
>  ArmVirtPkg/ArmVirtKvmTool.dsc                 | 18 ++++++++---------
>  ArmVirtPkg/ArmVirtQemu.dsc                    | 20 +++++++++----------
>  ArmVirtPkg/ArmVirtQemuKernel.dsc              | 20 +++++++++----------
>  ArmVirtPkg/ArmVirtXen.dsc                     |  2 +-
>  EmbeddedPkg/EmbeddedPkg.dsc                   |  1 +
>  ArmVirtPkg/ArmVirtCloudHv.fdf                 |  6 +++---
>  ArmVirtPkg/ArmVirtKvmTool.fdf                 |  6 +++---
>  ArmVirtPkg/ArmVirtXen.fdf                     |  2 +-
>  ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc          |  6 +++---
>  .../ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf       |  2 +-
>  .../ArmVirtGicArchLib/ArmVirtGicArchLib.inf   |  1 +
>  .../ArmVirtPL031FdtClientLib.inf              |  1 +
>  .../ArmVirtPsciResetSystemLib.inf             |  1 +
>  .../ArmVirtTimerFdtClientLib.inf              |  1 +
>  .../KvmtoolRtcFdtClientLib.inf                |  1 +
>  .../NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf |  1 +
>  .../NorFlashQemuLib/NorFlashQemuLib.inf       |  1 +
>  .../XenAcpiPlatformDxe/XenAcpiPlatformDxe.inf |  1 +
>  ArmVirtPkg/XenioFdtDxe/XenioFdtDxe.inf        |  1 +
>  .../Drivers}/FdtClientDxe/FdtClientDxe.inf    |  1 -
>  .../FdtPciHostBridgeLib.inf                   | 11 +++++-----
>  .../FdtPciPcdProducerLib.inf                  |  5 ++---
>  .../Fdt}/HighMemDxe/HighMemDxe.inf            |  7 ++++---
>  .../Fdt}/VirtioFdtDxe/VirtioFdtDxe.inf        |  2 +-
>  .../Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf |  6 +++---
>  .../Include/Protocol/FdtClient.h              |  0
>  .../Drivers}/FdtClientDxe/FdtClientDxe.c      |  0
>  .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  0
>  .../FdtPciPcdProducerLib.c                    |  0
>  .../Fdt}/HighMemDxe/HighMemDxe.c              |  3 ++-
>  .../Fdt}/VirtioFdtDxe/VirtioFdtDxe.c          |  0
>  .../Library/QemuFwCfgLib/QemuFwCfgLibMmio.c   |  7 ++++---
>  Maintainers.txt                               |  6 ++++++
>  38 files changed, 106 insertions(+), 83 deletions(-)
>  rename {ArmVirtPkg => EmbeddedPkg/Drivers}/FdtClientDxe/FdtClientDxe.inf (92%)
>  rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf (77%)
>  rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf (87%)
>  rename {ArmVirtPkg => OvmfPkg/Fdt}/HighMemDxe/HighMemDxe.inf (83%)
>  rename {ArmVirtPkg => OvmfPkg/Fdt}/VirtioFdtDxe/VirtioFdtDxe.inf (92%)
>  rename ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf => OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf (86%)
>  rename {ArmVirtPkg => EmbeddedPkg}/Include/Protocol/FdtClient.h (100%)
>  rename {ArmVirtPkg => EmbeddedPkg/Drivers}/FdtClientDxe/FdtClientDxe.c (100%)
>  rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c (100%)
>  rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c (100%)
>  rename {ArmVirtPkg => OvmfPkg/Fdt}/HighMemDxe/HighMemDxe.c (95%)
>  rename {ArmVirtPkg => OvmfPkg/Fdt}/VirtioFdtDxe/VirtioFdtDxe.c (100%)
>  rename ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c => OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.c (93%)
>
> --
> 2.17.1
>
>
>
>
>
>






Re: [PATCH v1 12/13] DynamicTablesPkg: Add CM_ARM_LPI_INFO object

Sami Mujawar
 

Hi Pierre,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 23/06/2021 12:40 PM, Pierre.Gondois@arm.com wrote:
From: Pierre Gondois <Pierre.Gondois@arm.com>

Introduce the CM_ARM_LPI_INFO CmObj in the ArmNameSpaceObjects.
This allows to describe LPI state information, as described in
ACPI 6.4, s8.4.4.3 "_LPI (Low Power Idle States)".

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
.../Include/ArmNameSpaceObjects.h | 68 +++++++++++++++++++
.../ConfigurationManagerObjectParser.c | 35 ++++++++++
2 files changed, 103 insertions(+)

diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index 19dcae13b219..9c49091def59 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -58,6 +58,7 @@ typedef enum ArmObjectID {
EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info
EArmObjCmn600Info, ///< 36 - CMN-600 Info
+ EArmObjLpiInfo, ///< 37 - Lpi Info
EArmObjMax
} EARM_OBJECT_ID;
@@ -711,6 +712,10 @@ typedef struct CmArmProcHierarchyInfo {
/// the NoOfPrivateResources is 0, in which case it is recommended to set
/// this field to CM_NULL_TOKEN.
CM_OBJECT_TOKEN PrivateResourcesArrayToken;
+ /// Optional field: Reference Token for the Lpi state of this processor.
+ /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing
+ /// CM_ARM_LPI_INFO objects.
+ CM_OBJECT_TOKEN LpiToken;
} CM_ARM_PROC_HIERARCHY_INFO;
/** A structure that describes the Cache Type Structure (Type 1) in PPTT
@@ -878,6 +883,69 @@ typedef struct CmArmCmn600Info {
CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
} CM_ARM_CMN_600_INFO;
+/** A structure that describes the Lpi information.
+
+ The Low Power Idle states are described in DSDT/SSDT and associated
+ to cpus/clusters in the cpu topology.
+
+ ID: EArmObjLpiInfo
+*/
+typedef struct CmArmLpiInfo {
+ /** Minimum Residency. Time in microseconds after which a
+ state becomes more energy efficient than any shallower state.
+ */
+ UINT32 MinResidency;
+
+ /** Worst case time in microseconds from a wake interrupt
+ being asserted to the return to a running state
+ */
+ UINT32 WorstCaseWakeLatency;
+
+ /** Flags.
+ */
+ UINT32 Flags;
+
+ /** Architecture specific context loss flags.
+ */
+ UINT32 ArchFlags;
+
+ /** Residency counter frequency in cycles-per-second (Hz).
+ */
+ UINT32 ResCntFreq;
+
+ /** Every shallower power state in the parent is also enabled.
+ */
+ UINT32 EnableParentState;
+
+ /** The EntryMethod _LPI field can be described as an integer
+ or in a Register resource data descriptor.
+
+ If IsInteger is TRUE, the IntegerEntryMethod field is used.
+ If IsInteger is FALSE, the RegisterEntryMethod field is used.
+ */
+ BOOLEAN IsInteger;
+
+ /** EntryMethod described as an Integer.
+ */
+ UINT64 IntegerEntryMethod;
+
+ /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.
+ */
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;
+
+ /** Residency counter register.
+ */
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;
+
+ /** Usage counter register.
+ */
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;
+
+ /** String representing the Lpi state
+ */
+ CHAR8 StateName[16];
+} CM_ARM_LPI_INFO;
+
#pragma pack()
#endif // ARM_NAMESPACE_OBJECTS_H_
diff --git a/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c b/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
index 654ead6878e6..da5f5846edd9 100644
--- a/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
+++ b/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
@@ -368,6 +368,39 @@ STATIC CONST CM_OBJ_PARSER CmArmCmn600InfoParser[] = {
{"DtcFlags[3]", 4, "0x%x", NULL}
};
+/** A parser for the EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE structure.
+*/
+STATIC CONST CM_OBJ_PARSER AcpiGenericAddressParser[] = {
+ {"AddressSpaceId", 1, "%d", NULL},
+ {"RegisterBitWidth", 1, "%d", NULL},
+ {"RegisterBitOffset", 1, "%d", NULL},
+ {"AccessSize", 1, "%d", NULL},
+ {"Address", 8, "0x%llx", NULL},
+};
+
+/** A parser for EArmObjLpiInfo.
+*/
+STATIC CONST CM_OBJ_PARSER CmArmLpiInfoParser[] = {
+ {"MinResidency", 4, "0x%llx", NULL},
+ {"WorstCaseWakeLatency", 4, "0x%llx", NULL},
+ {"Flags", 4, "0x%llx", NULL},
+ {"ArchFlags", 4, "0x%llx", NULL},
+ {"ResCntFreq", 4, "0x%llx", NULL},
+ {"EnableParentState", 4, "0x%llx", NULL},
+ {"IsInteger", 1, "%d", NULL},
+ {"IntegerEntryMethod", 8, "0x%llx", NULL},
+ {"RegisterEntryMethod", sizeof (EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE),
+ NULL, NULL, AcpiGenericAddressParser,
+ ARRAY_SIZE (AcpiGenericAddressParser)},
+ {"ResidencyCounterRegister", sizeof (EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE),
+ NULL, NULL, AcpiGenericAddressParser,
+ ARRAY_SIZE (AcpiGenericAddressParser)},
+ {"UsageCounterRegister", sizeof (EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE),
+ NULL, NULL, AcpiGenericAddressParser,
+ ARRAY_SIZE (AcpiGenericAddressParser)},
+ {"StateName", 16, "0x%a", NULL},
+};
+
/** A parser for Arm namespace objects.
*/
STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
@@ -440,6 +473,8 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
ARRAY_SIZE (CmArmSerialPortInfoParser)},
{"EArmObjCmn600Info", CmArmCmn600InfoParser,
ARRAY_SIZE (CmArmCmn600InfoParser)},
+ {"EArmObjLpiInfo", CmArmLpiInfoParser,
+ ARRAY_SIZE (CmArmLpiInfoParser)},
{"EArmObjMax", NULL, 0},
};


Re: [PATCH v1 13/13] DynamicTablesPkg: SSDT CPU topology and LPI state generator

Sami Mujawar
 

Hi Pierre,

I ahve a few minor suggestions marked inline as [SAMI].

With those changed.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar


On 23/06/2021 12:40 PM, Pierre.Gondois@arm.com wrote:
From: Pierre Gondois <Pierre.Gondois@arm.com>

In the GIC interrupt model, logical processors are required to
have a Processor Device object in the DSDT and must convey each
processor's GIC information to the OS using the GICC structure.
Additionally, _LPI objects may be needed as they provide a method
to describe Low Power Idle states that defines the local power
states for each node in a hierarchical processor topology.

Therefore, add support to generate the CPU topology and the LPI
state information in an SSDT table.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
DynamicTablesPkg/DynamicTables.dsc.inc | 6 +
DynamicTablesPkg/Include/AcpiTableGenerator.h | 7 +-
.../SsdtCpuTopologyGenerator.c | 1230 +++++++++++++++++
.../SsdtCpuTopologyGenerator.h | 134 ++
.../SsdtCpuTopologyLibArm.inf | 40 +
5 files changed, 1416 insertions(+), 1 deletion(-)
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.h
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc b/DynamicTablesPkg/DynamicTables.dsc.inc
index ed221d1681eb..292215c39456 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -37,6 +37,9 @@ [Components.common]
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortLibArm.inf
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
+ # AML Codegen
+ DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf
+
#
# Dynamic Table Factory Dxe
#
@@ -56,6 +59,9 @@ [Components.common]
# AML Fixup
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortLibArm.inf
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
+
+ # AML Codegen
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf
}
#
diff --git a/DynamicTablesPkg/Include/AcpiTableGenerator.h b/DynamicTablesPkg/Include/AcpiTableGenerator.h
index 352331d6dc95..45c808ba740d 100644
--- a/DynamicTablesPkg/Include/AcpiTableGenerator.h
+++ b/DynamicTablesPkg/Include/AcpiTableGenerator.h
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -63,6 +63,10 @@ The Dynamic Tables Framework implements the following ACPI table generators:
The SSDT CMN-600 generator collates the CMN-600 information
from the Configuration Manager and patches the SSDT CMN-600
template to build the SSDT CMN-600 table.
+ - SSDT Cpu-Topology:
+ The SSDT Cpu-Topology generator collates the cpu and LPI
+ information from the Configuration Manager and generates a
+ SSDT table describing the CPU hierarchy.
*/
/** The ACPI_TABLE_GENERATOR_ID type describes ACPI table generator ID.
@@ -88,6 +92,7 @@ typedef enum StdAcpiTableId {
EStdAcpiTableIdSrat, ///< SRAT Generator
EStdAcpiTableIdSsdtSerialPort, ///< SSDT Serial-Port Generator
EStdAcpiTableIdSsdtCmn600, ///< SSDT Cmn-600 Generator
+ EStdAcpiTableIdSsdtCpuTopology, ///< SSDT Cpu Topology
EStdAcpiTableIdMax
} ESTD_ACPI_TABLE_ID;
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
new file mode 100644
index 000000000000..88db808760f7
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
@@ -0,0 +1,1230 @@
+/** @file
+ SSDT Cpu Topology Table Generator.
+
+ Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI 6.3 Specification - January 2019 - s8.4 Declaring Processors
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
[SAMI] I think the DBG2 header is not required here. Can you check this and if any other includes below can be removed, please?
+#include <Library/AcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiTable.h>
+
+// Module specific include files.
+#include <AcpiTableGenerator.h>
+#include <ConfigurationManagerObject.h>
+#include <ConfigurationManagerHelper.h>
+#include <Library/AcpiHelperLib.h>
+#include <Library/AmlLib/AmlLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "SsdtCpuTopologyGenerator.h"
+
+/** ARM standard SSDT Cpu Topology Table Generator.
+
+Requirements:
+ The following Configuration Manager Object(s) are required by
+ this Generator:
+ - EArmObjProcHierarchyInfo
+ - EArmObjGicCInfo
+ - EArmObjCmRef
+ - EArmObjLpiInfo
[SAMI] I think the LPI information should be marked as (OPTIONAL).
+*/
+
+/** This macro expands to a function that retrieves the GIC
+ CPU interface Information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjGicCInfo,
+ CM_ARM_GICC_INFO
+ );
+
+/**
+ This macro expands to a function that retrieves the Processor Hierarchy
+ information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjProcHierarchyInfo,
+ CM_ARM_PROC_HIERARCHY_INFO
+ );
+
+/**
+ This macro expands to a function that retrieves the cross-CM-object-
+ reference information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjCmRef,
+ CM_ARM_OBJ_REF
+ );
+
+/**
+ This macro expands to a function that retrieves the Lpi
+ information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjLpiInfo,
+ CM_ARM_LPI_INFO
+ );
+
+/** Initialize the TokenTable.
+
+ One entry should be allocated for each CM_ARM_PROC_HIERARCHY_INFO
+ structure of the platform. The TokenTable allows to have a mapping:
+ Index <-> CM_OBJECT_TOKEN (to CM_ARM_LPI_INFO structures).
+
+ There will always be less sets of Lpi states (CM_ARM_OBJ_REF)
+ than the number of cpus/clusters (CM_ARM_PROC_HIERARCHY_INFO).
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] Count Number of entries to allocate in the TokenTable.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+TokenTableInitialize (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN UINT32 Count
+ )
+{
+ CM_OBJECT_TOKEN * Table;
+
+ if ((Generator == NULL) ||
+ (Count == 0) ||
+ (Count >= MAX_INDEX_NAME)) {
+ ASSERT (0);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Table = AllocateZeroPool (sizeof (CM_OBJECT_TOKEN) * Count);
+ if (Table == NULL) {
+ ASSERT (0);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Generator->TokenTable.Table = Table;
+
+ return EFI_SUCCESS;
+}
+
+/** Free the TokenTable.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+**/
+STATIC
+VOID
+EFIAPI
+TokenTableFree (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator
+ )
+{
+ ASSERT (Generator != NULL);
+ ASSERT (Generator->TokenTable.Table != NULL);
+
+ if (Generator->TokenTable.Table != NULL) {
+ FreePool (Generator->TokenTable.Table);
+ }
+}
+
+/** Add a new entry to the TokenTable and return its index.
+
+ If an entry with Token is already available in the table,
+ return its index without adding a new entry.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] Token New Token entry to add.
+
+ @retval The index of the token entry in the TokenTable.
+**/
+STATIC
+UINT32
+EFIAPI
+TokenTableAdd (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CM_OBJECT_TOKEN Token
+ )
+{
+ CM_OBJECT_TOKEN * Table;
+ UINT32 Index;
+ UINT32 LastIndex;
+
+ ASSERT (Generator != NULL);
+ ASSERT (Generator->TokenTable.Table != NULL);
+
+ Table = Generator->TokenTable.Table;
+ LastIndex = Generator->TokenTable.LastIndex;
+
+ // Search if there is already an entry with this Token.
+ for (Index = 0; Index < LastIndex; Index++) {
+ if (Table[Index] == Token) {
+ return Index;
+ }
+ }
+
+ ASSERT (LastIndex < MAX_INDEX_NAME);
+ ASSERT (LastIndex < Generator->ProcNodeCount);
+
+ // If no, create a new entry.
+ Table[LastIndex] = Token;
+
+ return Generator->TokenTable.LastIndex++;
+}
+
+/** Write a string 'Xxxx\0' in AslName (5 bytes long),
+ with 'X' being the leading char of the name, and
+ with 'xxx' being Value in hexadecimal.
+
+ As 'xxx' in hexadecimal represents a number on 12 bits,
+ we have Value < (2 << 12)
+
+ @param [in] LeadChar Leading char of the name.
+ @param [in] Value Hex value of the name.
+ Must be lower than (2 << 12).
+ @param [in, out] AslName Pointer to write the 'Xxxx' string to.
+ Must be at least 5 bytes long.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WriteAslName (
+ IN CHAR8 LeadChar,
+ IN UINT32 Value,
+ IN OUT CHAR8 * AslName
+ )
+{
+ UINT8 Index;
+
+ if ((Value >= MAX_INDEX_NAME) ||
+ (AslName == NULL)) {
+ ASSERT (0);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AslName[0] = LeadChar;
+ AslName[AML_NAME_SEG_SIZE] = '\0';
+
+ for (Index = 0; Index < AML_NAME_SEG_SIZE - 1; Index++) {
+ AslName[AML_NAME_SEG_SIZE - Index - 1] =
+ AsciiFromHex (((Value >> (4 * Index)) & 0xF));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/** Create and add an _LPI method to Cpu/Cluster Node.
+
+ For instance, transform an AML node from:
+ Device (C002)
+ {
+ Name (_UID, 2)
+ Name (_HID, "ACPI0007")
+ }
+
+ To:
+ Device (C002)
+ {
+ Name (_UID, 2)
+ Name (_HID, "ACPI0007")
+ Method (_LPI, 0, NotSerialized)
+ {
+ Return (\_SB.L003)
+ }
+ }
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] ProcHierarchyNodeInfo CM_ARM_PROC_HIERARCHY_INFO describing
+ the Cpu.
+ @param [in] Node Node to which the _LPI method is
+ attached. Can represent a Cpu or a
+ Cluster.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateAmlLpiMethod (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CM_ARM_PROC_HIERARCHY_INFO * ProcHierarchyNodeInfo,
+ IN AML_OBJECT_NODE_HANDLE * Node
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TokenIndex;
+ CHAR8 AslName[SB_SCOPE_PREFIX_SIZE + AML_NAME_SEG_SIZE];
+
+ ASSERT (Generator != NULL);
+ ASSERT (ProcHierarchyNodeInfo != NULL);
+ ASSERT (ProcHierarchyNodeInfo->LpiToken != CM_NULL_TOKEN);
+ ASSERT (Node != NULL);
+
+ TokenIndex = TokenTableAdd (Generator, ProcHierarchyNodeInfo->LpiToken);
+
+ CopyMem (AslName, SB_SCOPE_PREFIX, SB_SCOPE_PREFIX_SIZE);
+
+ Status = WriteAslName (
+ 'L',
+ TokenIndex,
+ AslName + SB_SCOPE_PREFIX_SIZE - 1
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // ASL:
+ // Method (_LPI, 0) {
+ // Return ([AslName])
+ // }
+ Status = AmlCodeGenMethodRetNameString (
+ "_LPI",
+ AslName,
+ 0,
+ FALSE,
+ 0,
+ Node,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ }
+
+ return Status;
+}
+
+/** Generate all the Lpi states under the '_SB' scope.
+
+ This function generates the following ASL code:
+ Scope (\_SB) {
+ Name (L000, Package() {
+ 0, // Version
+ 0, // Level Index
+ X, // Count
+ Package() {
+ [An Lpi state]
+ },
+ Package() {
+ [Another Lpi state]
+ },
+ } // Name L000
+
+ Name (L001, Package() {
+ ...
+ } // Name L001
+
+ ...
+ } // Scope /_SB
+
+ The Lpi states are fetched from the Configuration Manager.
+ The names of the Lpi states are generated from the TokenTable.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] ScopeNode Scope node handle ('\_SB' scope).
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GenerateLpiStates (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN AML_OBJECT_NODE_HANDLE ScopeNode
+ )
+{
+ EFI_STATUS Status;
+
+ UINT32 Index;
+ UINT32 LastIndex;
+
+ AML_OBJECT_NODE_HANDLE LpiNode;
+ CM_ARM_OBJ_REF * LpiRefInfo;
+ UINT32 LpiRefInfoCount;
+ UINT32 LpiRefIndex;
+ CM_ARM_LPI_INFO * LpiInfo;
+ CHAR8 AslName[AML_NAME_SEG_SIZE + 1];
+
+ ASSERT (Generator != NULL);
+ ASSERT (Generator->TokenTable.Table != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (ScopeNode != NULL);
+
+ LastIndex = Generator->TokenTable.LastIndex;
+
+ // For each entry in the TokenTable, create a name in the AML namespace
+ // under SB_SCOPE, to store the Lpi states associated with the LpiToken.
+ for (Index = 0; Index < LastIndex; Index++) {
+ Status = WriteAslName ('L', Index, AslName);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // We do not support the LevelId field for now, let it to 0.
+ Status = AmlCreateLpiNode (AslName, 1, 0, ScopeNode, &LpiNode);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // Fetch the LPI objects referenced by the token.
+ Status = GetEArmObjCmRef (
+ CfgMgrProtocol,
+ Generator->TokenTable.Table[Index],
+ &LpiRefInfo,
+ &LpiRefInfoCount
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ for (LpiRefIndex = 0; LpiRefIndex < LpiRefInfoCount; LpiRefIndex++) {
+ // For each CM_ARM_LPI_INFO referenced by the token, add an Lpi state.
+ Status = GetEArmObjLpiInfo (
+ CfgMgrProtocol,
+ LpiRefInfo[LpiRefIndex].ReferenceToken,
+ &LpiInfo,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlAddLpiState (
+ LpiInfo->MinResidency,
+ LpiInfo->WorstCaseWakeLatency,
+ LpiInfo->Flags,
+ LpiInfo->ArchFlags,
+ LpiInfo->ResCntFreq,
+ LpiInfo->EnableParentState,
+ LpiInfo->IsInteger ?
+ NULL :
+ &LpiInfo->RegisterEntryMethod,
+ LpiInfo->IsInteger ?
+ LpiInfo->IntegerEntryMethod :
+ 0,
+ &LpiInfo->ResidencyCounterRegister,
+ &LpiInfo->UsageCounterRegister,
+ LpiInfo->StateName,
+ LpiNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+ } // for LpiRefIndex
+ } // for Index
+
+ return EFI_SUCCESS;
+}
+
+/** Create a Cpu in the AML namespace.
+
+ This generates the following ASL code:
+ Device (C002)
+ {
+ Name (_UID, 2)
+ Name (_HID, "ACPI0007")
+ }
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] ParentNode Parent node to attach the Cpu node to.
+ @param [in] GicCInfo CM_ARM_GICC_INFO object used to create the node.
+ @param [in] CpuIndex Index used to generate the node name.
+ @param [out] CpuNodePtr If not NULL, return the created Cpu node.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateAmlCpu (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN AML_NODE_HANDLE ParentNode,
+ IN CM_ARM_GICC_INFO * GicCInfo,
+ IN UINT32 CpuIndex,
+ OUT AML_OBJECT_NODE_HANDLE * CpuNodePtr OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ AML_OBJECT_NODE_HANDLE CpuNode;
+ CHAR8 AslName[AML_NAME_SEG_SIZE + 1];
+
+ ASSERT (Generator != NULL);
+ ASSERT (ParentNode != NULL);
+ ASSERT (GicCInfo != NULL);
+
+ Status = WriteAslName ('C', CpuIndex, AslName);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenDevice (AslName, ParentNode, &CpuNode);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenNameInteger (
+ "_UID",
+ GicCInfo->AcpiProcessorUid,
+ CpuNode,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenNameString (
+ "_HID",
+ ACPI_HID_PROCESSOR_DEVICE,
+ CpuNode,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // If requested, return the handle to the CpuNode.
+ if (CpuNodePtr != NULL) {
+ *CpuNodePtr = CpuNode;
+ }
+
+ return Status;
+}
+
+/** Create a Cpu in the AML namespace from a CM_ARM_PROC_HIERARCHY_INFO
+ CM object.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] ParentNode Parent node to attach the Cpu node to.
+ @param [in] CpuIndex Index used to generate the node name.
+ @param [in] ProcHierarchyNodeInfo CM_ARM_PROC_HIERARCHY_INFO describing
+ the Cpu.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateAmlCpuFromProcHierarchy (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN AML_NODE_HANDLE ParentNode,
+ IN UINT32 CpuIndex,
+ IN CM_ARM_PROC_HIERARCHY_INFO * ProcHierarchyNodeInfo
+ )
+{
+ EFI_STATUS Status;
+ CM_ARM_GICC_INFO * GicCInfo;
+ AML_OBJECT_NODE_HANDLE CpuNode;
+
+ ASSERT (Generator != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (ParentNode != NULL);
+ ASSERT (ProcHierarchyNodeInfo != NULL);
+ ASSERT (ProcHierarchyNodeInfo->GicCToken != CM_NULL_TOKEN);
+
+ Status = GetEArmObjGicCInfo (
+ CfgMgrProtocol,
+ ProcHierarchyNodeInfo->GicCToken,
+ &GicCInfo,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = CreateAmlCpu (Generator, ParentNode, GicCInfo, CpuIndex, &CpuNode);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // If a set of Lpi states is associated with the
+ // CM_ARM_PROC_HIERARCHY_INFO, create an _LPI method returning them.
+ if (ProcHierarchyNodeInfo->LpiToken != CM_NULL_TOKEN) {
+ Status = CreateAmlLpiMethod (Generator, ProcHierarchyNodeInfo, CpuNode);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return Status;
+}
+
+/** Create a Cluster in the AML namespace.
+
+ Any CM_ARM_PROC_HIERARCHY_INFO object with the following flags is
+ assumed to be a cluster:
+ - EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL
+ - EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID
+ - EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF
+
+ This generates the following ASL code:
+ Device (C002)
+ {
+ Name (_UID, 2)
+ Name (_HID, "ACPI0010")
+ }
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] ParentNode Parent node to attach the Cluster
+ node to.
+ @param [in] ProcHierarchyNodeInfo CM_ARM_PROC_HIERARCHY_INFO object used
+ to create the node.
+ @param [in] ClusterIndex Index used to generate the node name.
+ @param [out] ClusterNodePtr If success, contains the created Cluster
+ node.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateAmlCluster (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN AML_NODE_HANDLE ParentNode,
+ IN CM_ARM_PROC_HIERARCHY_INFO * ProcHierarchyNodeInfo,
+ IN UINT32 ClusterIndex,
+ OUT AML_OBJECT_NODE_HANDLE * ClusterNodePtr
+ )
+{
+ EFI_STATUS Status;
+ AML_OBJECT_NODE_HANDLE ClusterNode;
+ CHAR8 AslNameCluster[AML_NAME_SEG_SIZE + 1];
+
+ ASSERT (Generator != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (ParentNode != NULL);
+ ASSERT (ProcHierarchyNodeInfo != NULL);
+ ASSERT (ClusterNodePtr != NULL);
+
+ Status = WriteAslName ('C', ClusterIndex, AslNameCluster);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenDevice (AslNameCluster, ParentNode, &ClusterNode);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // Use the ClusterIndex for the _UID value as there is no AcpiProcessorUid
+ // and EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID is set for non-Cpus.
+ Status = AmlCodeGenNameInteger (
+ "_UID",
+ ClusterIndex,
+ ClusterNode,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ Status = AmlCodeGenNameString (
+ "_HID",
+ ACPI_HID_PROCESSOR_CONTAINER_DEVICE,
+ ClusterNode,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // If a set of Lpi states are associated with the
+ // CM_ARM_PROC_HIERARCHY_INFO, create an _LPI method returning them.
+ if (ProcHierarchyNodeInfo->LpiToken != CM_NULL_TOKEN) {
+ Status = CreateAmlLpiMethod (
+ Generator,
+ ProcHierarchyNodeInfo,
+ ClusterNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+ }
+
+ *ClusterNodePtr = ClusterNode;
+
+ return Status;
+}
+
+/** Create an AML representation of the Cpu topology.
+
+ A cluster is by extension any non-leave device in the cpu topology.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] NodeToken Token of the CM_ARM_PROC_HIERARCHY_INFO
+ currently handled.
+ Cannot be CM_NULL_TOKEN.
+ @param [in] ParentNode Parent node to attach the created
+ node to.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateAmlCpuTopologyTree (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN CM_OBJECT_TOKEN NodeToken,
+ IN AML_NODE_HANDLE ParentNode
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT32 CpuIndex;
+ UINT32 ClusterIndex;
+ AML_OBJECT_NODE_HANDLE ClusterNode;
+
+ ASSERT (Generator != NULL);
+ ASSERT (Generator->ProcNodeList != NULL);
+ ASSERT (Generator->ProcNodeCount != 0);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (NodeToken != CM_NULL_TOKEN);
+ ASSERT (ParentNode != NULL);
+
+ CpuIndex = 0;
+ ClusterIndex = 0;
+
+ for (Index = 0; Index < Generator->ProcNodeCount; Index++) {
+ // Find the children of the CM_ARM_PROC_HIERARCHY_INFO
+ // currently being handled (i.e. ParentToken == NodeToken).
+ if (Generator->ProcNodeList[Index].ParentToken == NodeToken) {
+
+ // Only Cpus (leaves in this tree) have a GicCToken.
+ // Create a Cpu node.
+ if (Generator->ProcNodeList[Index].GicCToken != CM_NULL_TOKEN) {
+ if ((Generator->ProcNodeList[Index].Flags & PPTT_PROCESSOR_MASK) !=
+ PPTT_CPU_PROCESSOR_MASK) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CPU-TOPOLOGY: Invalid flags for cpu: 0x%x.\n",
+ Generator->ProcNodeList[Index].Flags
+ ));
+ ASSERT (0);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = CreateAmlCpuFromProcHierarchy (
+ Generator,
+ CfgMgrProtocol,
+ ParentNode,
+ CpuIndex,
+ &Generator->ProcNodeList[Index]
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ CpuIndex++;
+
+ } else {
+ // If this is not a Cpu, then this is a cluster.
+
+ // Acpi processor Id for clusters is not handled.
+ if ((Generator->ProcNodeList[Index].Flags & PPTT_PROCESSOR_MASK) !=
+ PPTT_CLUSTER_PROCESSOR_MASK) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CPU-TOPOLOGY: Invalid flags for cluster: 0x%x.\n",
+ Generator->ProcNodeList[Index].Flags
+ ));
+ ASSERT (0);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = CreateAmlCluster (
+ Generator,
+ CfgMgrProtocol,
+ ParentNode,
+ &Generator->ProcNodeList[Index],
+ ClusterIndex,
+ &ClusterNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // Nodes must have a unique name in the ASL namespace.
+ // Reset the Cpu index whenever we create a new Cluster.
+ ClusterIndex++;
+ CpuIndex = 0;
+
+ // Recursively continue creating an AML tree.
+ Status = CreateAmlCpuTopologyTree (
+ Generator,
+ CfgMgrProtocol,
+ Generator->ProcNodeList[Index].Token,
+ ClusterNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+ }
+ } // if ParentToken == NodeToken
+ } // for
+
+ return EFI_SUCCESS;
+}
+
+/** Create the processor hierarchy AML tree from CM_ARM_PROC_HIERARCHY_INFO
+ CM objects.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] ScopeNode Scope node handle ('\_SB' scope).
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateTopologyFromProcHierarchy (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN AML_OBJECT_NODE_HANDLE ScopeNode
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINT32 TopLevelProcNodeIndex;
+
+ ASSERT (Generator != NULL);
+ ASSERT (Generator->ProcNodeCount != 0);
+ ASSERT (Generator->ProcNodeList != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (ScopeNode != NULL);
+
+ TopLevelProcNodeIndex = -1;
[SAMI] I think it would be good to use MAX_UINT32 instead of -1 here. Same for the if condition a few lines below.
+
+ Status = TokenTableInitialize (Generator, Generator->ProcNodeCount);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // It is assumed that there is one unique CM_ARM_PROC_HIERARCHY_INFO
+ // structure with no ParentToken and the EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL
+ // flag set. All other CM_ARM_PROC_HIERARCHY_INFO are non-physical and
+ // have a ParentToken.
+ for (Index = 0; Index < Generator->ProcNodeCount; Index++) {
+ if ((Generator->ProcNodeList[Index].ParentToken == CM_NULL_TOKEN) &&
+ (Generator->ProcNodeList[Index].Flags &
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL)) {
+ if (TopLevelProcNodeIndex != -1) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CPU-TOPOLOGY: Top level CM_ARM_PROC_HIERARCHY_INFO "
+ "must be unique\n"
+ ));
+ ASSERT (0);
+ goto exit_handler;
+ }
+ TopLevelProcNodeIndex = Index;
+ }
+ } // for
+
+ Status = CreateAmlCpuTopologyTree (
+ Generator,
+ CfgMgrProtocol,
+ Generator->ProcNodeList[TopLevelProcNodeIndex].Token,
+ ScopeNode
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ goto exit_handler;
+ }
+
+ Status = GenerateLpiStates (Generator, CfgMgrProtocol, ScopeNode);
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ goto exit_handler;
+ }
+
+exit_handler:
+ TokenTableFree (Generator);
+ return Status;
+}
+
+/** Create the processor hierarchy AML tree from CM_ARM_GICC_INFO
+ CM objects.
+
+ A cluster is by extension any non-leave device in the cpu topology.
+
+ @param [in] Generator The SSDT Cpu Topology generator.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in] ScopeNode Scope node handle ('\_SB' scope).
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_OUT_OF_RESOURCES Failed to allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CreateTopologyFromGicC (
+ IN ACPI_CPU_TOPOLOGY_GENERATOR * Generator,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN AML_OBJECT_NODE_HANDLE ScopeNode
+ )
+{
+ EFI_STATUS Status;
+ CM_ARM_GICC_INFO * GicCInfo;
+ UINT32 GicCInfoCount;
+ UINT32 Index;
+
+ ASSERT (Generator != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (ScopeNode != NULL);
+
+ Status = GetEArmObjGicCInfo (
+ CfgMgrProtocol,
+ CM_NULL_TOKEN,
+ &GicCInfo,
+ &GicCInfoCount
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ return Status;
+ }
+
+ // For each CM_ARM_GICC_INFO object, create an AML node.
+ for (Index = 0; Index < GicCInfoCount; Index++) {
+ Status = CreateAmlCpu (
+ Generator,
+ ScopeNode,
+ &GicCInfo[Index],
+ Index,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (0);
+ break;
+ }
+ } // for
+
+ return Status;
+}
+
+/** Construct the SSDT Cpu Topology ACPI table.
+
+ This function invokes the Configuration Manager protocol interface
+ to get the required hardware information for generating the ACPI
+ table.
+
+ If this function allocates any resources then they must be freed
+ in the FreeXXXXTableResources function.
+
+ @param [in] This Pointer to the table generator.
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [out] Table Pointer to the constructed ACPI Table.
+
+ @retval EFI_SUCCESS Table generated successfully.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object was not found.
+ @retval EFI_BAD_BUFFER_SIZE The size returned by the Configuration
+ Manager is less than the Object size for the
+ requested object.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+BuildSsdtCpuTopologyTable (
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ OUT EFI_ACPI_DESCRIPTION_HEADER ** CONST Table
+ )
+{
+ EFI_STATUS Status;
+ AML_ROOT_NODE_HANDLE RootNode;
+ AML_OBJECT_NODE_HANDLE ScopeNode;
+ CM_ARM_PROC_HIERARCHY_INFO * ProcHierarchyNodeList;
+ UINT32 ProcHierarchyNodeCount;
+ ACPI_CPU_TOPOLOGY_GENERATOR * Generator;
+
+ ASSERT (This != NULL);
+ ASSERT (AcpiTableInfo != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (Table != NULL);
+ ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+ ASSERT (AcpiTableInfo->AcpiTableSignature == This->AcpiTableSignature);
+
+ Generator = (ACPI_CPU_TOPOLOGY_GENERATOR*)This;
+
+ Status = AmlCodeGenDefinitionBlock (
+ "SSDT",
+ "ARMLTD",
+ "CPU-TOPO",
+ 1,
+ &RootNode
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = AmlCodeGenScope (SB_SCOPE, RootNode, &ScopeNode);
+ if (EFI_ERROR (Status)) {
+ goto exit_handler;
+ }
+
+ // Get the processor hierarchy info and update the processor topology
+ // structure count with Processor Hierarchy Nodes (Type 0)
+ Status = GetEArmObjProcHierarchyInfo (
+ CfgMgrProtocol,
+ CM_NULL_TOKEN,
+ &ProcHierarchyNodeList,
+ &ProcHierarchyNodeCount
+ );
+ if (EFI_ERROR (Status) &&
+ (Status != EFI_NOT_FOUND)) {
+ goto exit_handler;
+ }
+
+ if (Status == EFI_NOT_FOUND) {
+ // If hierarchy information is not found generate a flat topology
+ // using CM_ARM_GICC_INFO objects.
+ Status = CreateTopologyFromGicC (
+ Generator,
+ CfgMgrProtocol,
+ ScopeNode
+ );
+ if (EFI_ERROR (Status)) {
+ goto exit_handler;
+ }
+ } else {
+ // Generate the topology from CM_ARM_PROC_HIERARCHY_INFO objects.
+ Generator->ProcNodeList = ProcHierarchyNodeList;
+ Generator->ProcNodeCount = ProcHierarchyNodeCount;
+
+ Status = CreateTopologyFromProcHierarchy (
+ Generator,
+ CfgMgrProtocol,
+ ScopeNode
+ );
+ if (EFI_ERROR (Status)) {
+ goto exit_handler;
+ }
+ }
+
+ Status = AmlSerializeDefinitionBlock (
+ RootNode,
+ Table
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CPU-TOPOLOGY: Failed to Serialize SSDT Table Data."
+ " Status = %r\n",
+ Status
+ ));
+ goto exit_handler;
+ }
+
+exit_handler:
+ // Delete the RootNode and its attached children.
+ return AmlDeleteTree (RootNode);
+}
+
+/** Free any resources allocated for constructing the
+ SSDT Cpu Topology ACPI table.
+
+ @param [in] This Pointer to the table generator.
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in, out] Table Pointer to the ACPI Table.
+
+ @retval EFI_SUCCESS The resources were freed successfully.
+ @retval EFI_INVALID_PARAMETER The table pointer is NULL or invalid.
+**/
+STATIC
+EFI_STATUS
+FreeSsdtCpuTopologyTableResources (
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER ** CONST Table
+ )
+{
+ ASSERT (This != NULL);
+ ASSERT (AcpiTableInfo != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+ ASSERT (AcpiTableInfo->AcpiTableSignature == This->AcpiTableSignature);
+
+ if ((Table == NULL) || (*Table == NULL)) {
+ DEBUG ((DEBUG_ERROR, "ERROR: SSDT-CPU-TOPOLOGY: Invalid Table Pointer\n"));
+ ASSERT ((Table != NULL) && (*Table != NULL));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ FreePool (*Table);
+ *Table = NULL;
+ return EFI_SUCCESS;
+}
+
+/** This macro defines the SSDT Cpu Topology Table Generator revision.
+*/
+#define SSDT_CPU_TOPOLOGY_GENERATOR_REVISION CREATE_REVISION (1, 0)
+
+/** The interface for the SSDT Cpu Topology Table Generator.
+*/
+STATIC
+ACPI_CPU_TOPOLOGY_GENERATOR SsdtCpuTopologyGenerator = {
+ // ACPI table generator header
+ {
+ // Generator ID
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtCpuTopology),
+ // Generator Description
+ L"ACPI.STD.SSDT.CPU.TOPOLOGY.GENERATOR",
+ // ACPI Table Signature
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ // ACPI Table Revision - Unused
+ 0,
+ // Minimum ACPI Table Revision - Unused
+ 0,
+ // Creator ID
+ TABLE_GENERATOR_CREATOR_ID_ARM,
+ // Creator Revision
+ SSDT_CPU_TOPOLOGY_GENERATOR_REVISION,
+ // Build Table function
+ BuildSsdtCpuTopologyTable,
+ // Free Resource function
+ FreeSsdtCpuTopologyTableResources,
+ // Extended build function not needed
+ NULL,
+ // Extended build function not implemented by the generator.
+ // Hence extended free resource function is not required.
+ NULL
+ },
+
+ // Private fields are defined from here.
+
+ // TokenTable
+ {
+ // Table
+ NULL,
+ // LastIndex
+ 0
+ },
+ // ProcNodeList
+ NULL,
+ // ProcNodeCount
+ 0
+};
+
+/** Register the Generator with the ACPI Table Factory.
+
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS The Generator is registered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_ALREADY_STARTED The Generator for the Table ID
+ is already registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiSsdtCpuTopologyLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+ Status = RegisterAcpiTableGenerator (&SsdtCpuTopologyGenerator.Header);
+ DEBUG ((
+ DEBUG_INFO,
+ "SSDT-CPU-TOPOLOGY: Register Generator. Status = %r\n",
+ Status
+ ));
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/** Deregister the Generator from the ACPI Table Factory.
+
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS The Generator is deregistered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The Generator is not registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiSsdtCpuTopologyLibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+ Status = DeregisterAcpiTableGenerator (&SsdtCpuTopologyGenerator.Header);
+ DEBUG ((
+ DEBUG_INFO,
+ "SSDT-CPU-TOPOLOGY: Deregister Generator. Status = %r\n",
+ Status
+ ));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.h b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.h
new file mode 100644
index 000000000000..95930a86b186
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.h
@@ -0,0 +1,134 @@
+/** @file
+ SSDT Cpu Topology Table Generator.
+
+ Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI 6.3 Specification - January 2019 - s8.4 Declaring Processors
+**/
+
+#ifndef SSDT_CPU_TOPOLOGY_GENERATOR_H_
+#define SSDT_CPU_TOPOLOGY_GENERATOR_H_
+
+#pragma pack(1)
+
+// Mask for the flags that need to be checked.
+#define PPTT_PROCESSOR_MASK ( \
+ (EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL) | \
+ (EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID << 1) | \
+ (EFI_ACPI_6_3_PPTT_NODE_IS_LEAF << 3))
+
+// Mask for the cpu flags.
+#define PPTT_CPU_PROCESSOR_MASK ( \
+ (EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL) | \
+ (EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID << 1) | \
+ (EFI_ACPI_6_3_PPTT_NODE_IS_LEAF << 3))
+
+// Mask for the cluster flags.
+// Even though a _UID is generated for clusters, it is simpler to use
+// EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID and to not match the cluster id of
+// the PPTT table (not sure the PPTT table is generated).
+#define PPTT_CLUSTER_PROCESSOR_MASK ( \
+ (EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL) | \
+ (EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID << 1) | \
+ (EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF << 3))
+
+/** LPI states are stored in the ASL namespace at '\_SB_.Lxxx',
+ with xxx being the node index of the LPI state.
+*/
+#define SB_SCOPE "\\_SB_"
+#define SB_SCOPE_PREFIX SB_SCOPE "."
+/// Size of the SB_SCOPE_PREFIX string.
+#define SB_SCOPE_PREFIX_SIZE sizeof (SB_SCOPE_PREFIX)
+
+/// HID for a processor device.
+#define ACPI_HID_PROCESSOR_DEVICE "ACPI0007"
+
+/// HID for a processor container device.
+#define ACPI_HID_PROCESSOR_CONTAINER_DEVICE "ACPI0010"
+
+/** Node names of Cpus and Clusters are 'Cxxx', and 'Lxxx' for LPI states.
+ The 'xxx' is an index on 12 bits is given to node name,
+ thus the limitation in the number of nodes.
+*/
+#define MAX_INDEX_NAME (1 << 12)
[SAMI] I think this macro should be renamed to MAX_NODE_COUNT.
+
+/** A structure used to handle the Lpi structures referencing.
+
+ A CM_ARM_PROC_HIERARCHY_INFO structure references a CM_ARM_OBJ_REF.
+ This CM_ARM_OBJ_REF references CM_ARM_LPI_INFO structures.
+
+ Example:
+ (Cpu0) (Cpu1)
+ CM_ARM_PROC_HIERARCHY_INFO CM_ARM_PROC_HIERARCHY_INFO
+ | |
+ +----------------------------------------
+ |
+ v
+ (List of references to Lpi states)
+ CM_ARM_OBJ_REF
+ |
+ +----------------------------------------
+ | |
+ v v
+ (A first Lpi state) (A second Lpi state)
+ CM_ARM_LPI_INFO[0] CM_ARM_LPI_INFO[1]
+
+ Here, Cpu0 and Cpu1 have the same Lpi states. Both CM_ARM_PROC_HIERARCHY_INFO
+ structures reference the same CM_ARM_OBJ_REF. An entry is created in the
+ TokenTable such as:
+ 0 <-> CM_ARM_OBJ_REF
+
+ This will lead to the creation of this pseudo-ASL code where Cpu0 and Cpu1
+ return the same object at \_SB.L000:
+ Scope (\_SB) {
+ Device (C000) {
+ [...]
+ Method (_LPI) {
+ Return (\_SB.L000)
+ }
+ } // C000
+
+ Device (C001) {
+ [...]
+ Method (_LPI) {
+ Return (\_SB.L000)
+ }
+ } // C001
+
+ // Lpi states
+ Name (L000, Package (0x05) {
+ [...]
+ }
+ }
+*/
+typedef struct TokenTable {
+ /// TokenTable, a table allowing to map:
+ /// Index <-> CM_OBJECT_TOKEN (to CM_ARM_LPI_INFO structures).
+ CM_OBJECT_TOKEN * Table;
+
+ /// Last used index of the TokenTable.
+ /// LastIndex is bound by ProcNodeCount.
+ UINT32 LastIndex;
+} TOKEN_TABLE;
+
+/** A structure holding the Cpu topology generator and additional private data.
+*/
+typedef struct AcpiCpuTopologyGenerator {
+ /// ACPI Table generator header
+ ACPI_TABLE_GENERATOR Header;
+
+ // Private fields are defined from here.
+
+ /// Private object used to handle token referencing.
+ TOKEN_TABLE TokenTable;
+ /// List of CM_ARM_PROC_HIERARCHY_INFO CM objects.
+ CM_ARM_PROC_HIERARCHY_INFO * ProcNodeList;
+ /// Count of CM_ARM_PROC_HIERARCHY_INFO CM objects.
+ UINT32 ProcNodeCount;
+} ACPI_CPU_TOPOLOGY_GENERATOR;
+
+#pragma pack()
+
+#endif // SSDT_CPU_TOPOLOGY_GENERATOR_H_
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf
new file mode 100644
index 000000000000..4038499d963d
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyLibArm.inf
@@ -0,0 +1,40 @@
+## @file
+# Ssdt Cpu Topology Table Generator
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = SsdtCpuTopologyLibArm
+ FILE_GUID = F2835EB6-4B05-48D4-A475-147DA0F3755C
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = NULL|DXE_DRIVER
+ CONSTRUCTOR = AcpiSsdtCpuTopologyLibConstructor
+ DESTRUCTOR = AcpiSsdtCpuTopologyLibDestructor
+
+[Sources]
+ SsdtCpuTopologyGenerator.c
+ SsdtCpuTopologyGenerator.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+
+[LibraryClasses]
+ AcpiHelperLib
+ AmlLib
+ BaseLib
+
+[FixedPcd]
+
+[Protocols]
+
+[Guids]
[SAMI] Please remove unused sections.
+


Re: [PATCH v3 00/19] OvmfPkg: Add support for microvm machine type

Ard Biesheuvel
 

On Wed, 8 Sept 2021 at 11:01, Gerd Hoffmann <kraxel@redhat.com> wrote:

This patch series adds basic support for the
microvm machine type to OVMF.

Working:
- uefi shell @ serial console.
- direct kernel boot.

Comming in followup patches:
- virtio-mmio support.
- pcie support.

Usage:
qemu-system-x86_64 -nographic -M microvm -bios MICROVM.fd ...

v2 changes:
- pick up review tags
- add bugzilla link
- fix timer configuration
- fix reset shutdown
- add readme
- add maintainers entry

v3 changes:
- pick up more review tags
- fix CI failures (https://github.com/tianocore/edk2/pull/1949)

Gerd Hoffmann (19):
OvmfPkg/Microvm: copy OvmfPkgX64 files as-is
OvmfPkg/Microvm: rename output files, fix includes
OvmfPkg/Microvm: no smm
OvmfPkg/Microvm: no secure boot
OvmfPkg/Microvm: no tpm
OvmfPkg/Microvm: no sev
OvmfPkg/Microvm: no csm
OvmfPkg/Microvm: no emulated scsi
OvmfPkg/Microvm: use MdePkg/Library/SecPeiDxeTimerLibCpu
OvmfPkg/Microvm: use XenTimerDxe (lapic timer)
OvmfPkg/Microvm: PlatformPei/MemDetect tweaks
OvmfPkg/Microvm: PlatformPei/Platform memory map tweaks
OvmfPkg/Microvm: PlatformPei/Platform: add id.
OvmfPkg/ResetSystemLib: add driver for microvm
OvmfPkg/Microvm: BdsPlatform: PciAcpiInitialization tweak.
OvmfPkg/Microvm: use PciHostBridgeLibNull
OvmfPkg/Microvm: wire up serial console, drop super-io
OvmfPkg/Microvm: add README
OvmfPkg/Microvm: add Maintainers.txt entry
Merged as #2042

Thanks all,


OvmfPkg/Microvm/MicrovmX64.dsc | 839 ++++++++++++++++++
OvmfPkg/Microvm/MicrovmX64.fdf | 462 ++++++++++
.../BaseResetSystemLibMicrovm.inf | 37 +
.../DxeResetSystemLibMicrovm.inf | 40 +
OvmfPkg/Include/IndustryStandard/Microvm.h | 19 +
OvmfPkg/Include/OvmfPlatforms.h | 1 +
.../PlatformBootManagerLib/BdsPlatform.c | 42 +
.../ResetSystemLib/DxeResetSystemLibMicrovm.c | 49 +
.../ResetSystemLib/ResetSystemLibMicrovm.c | 89 ++
OvmfPkg/PlatformPei/MemDetect.c | 4 +
OvmfPkg/PlatformPei/Platform.c | 14 +
Maintainers.txt | 6 +
OvmfPkg/Microvm/README | 54 ++
13 files changed, 1656 insertions(+)
create mode 100644 OvmfPkg/Microvm/MicrovmX64.dsc
create mode 100644 OvmfPkg/Microvm/MicrovmX64.fdf
create mode 100644 OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibMicrovm.inf
create mode 100644 OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.inf
create mode 100644 OvmfPkg/Include/IndustryStandard/Microvm.h
create mode 100644 OvmfPkg/Library/ResetSystemLib/DxeResetSystemLibMicrovm.c
create mode 100644 OvmfPkg/Library/ResetSystemLib/ResetSystemLibMicrovm.c
create mode 100644 OvmfPkg/Microvm/README

--
2.31.1


Re: [PATCH v3 11/19] OvmfPkg/Microvm: PlatformPei/MemDetect tweaks

Ard Biesheuvel
 

On Thu, 9 Sept 2021 at 12:58, Gerd Hoffmann <kraxel@redhat.com> wrote:

Sure. Suggestions? Add a Pcd and set it in Microvm.dsc?
Or is there some better way?
It's all a question of how much we want to overengineer things :)

I'm tempted to suggest a balanced version would be adding
GCC: *_*_*_CC_FLAGS = -D PLATFORM_IS_MICROVM
to [BuildOptions] in the .dsc, and test for that.
How about the approach below?
I am going to go with the original patch. All the workarounds seem
rather intrusive, and there is nothing wrong with probing the config
space and concluding that nothing is there if the response has all
bits set to 1. And to be pedantic, the reason 0xffff is an invalid
device ID is because it cannot be distinguished from a failed read. So
we are not checking whether the device exists and has an invalid
device ID, we are checking whether there's anything there to begin
with.


take care,
Gerd

commit 2d48e3eba022ba92eadcbad2c55e10ed281631c2
Author: Gerd Hoffmann <kraxel@redhat.com>
Date: Tue Jun 1 12:38:38 2021 +0200

OvmfPkg/Microvm: PlatformPei/MemDetect tweaks

Set mHostBridgeDevId to MICROVM_PSEUDO_DEVICE_ID using a
compile time switch.

Skip host bridge setup on microvm.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3599
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>

diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc
index 019b50de7d8f..a000c195d866 100644
--- a/OvmfPkg/Microvm/MicrovmX64.dsc
+++ b/OvmfPkg/Microvm/MicrovmX64.dsc
@@ -73,6 +73,9 @@ [Defines]
!endif

[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DPLATFORM_IS_MICROVM
+ INTEL:*_*_*_CC_FLAGS = /D PLATFORM_IS_MICROVM
+ MSFT:*_*_*_CC_FLAGS = /D PLATFORM_IS_MICROVM
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 2c2c4641ec8a..8125644bc91a 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -15,6 +15,7 @@ Module Name:
//
#include <IndustryStandard/E820.h>
#include <IndustryStandard/I440FxPiix4.h>
+#include <IndustryStandard/Microvm.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <PiPei.h>
#include <Register/Intel/SmramSaveStateMap.h>
@@ -135,6 +136,10 @@ QemuUc32BaseInitialization (
UINT32 LowerMemorySize;
UINT32 Uc32Size;

+ if (mHostBridgeDevId == MICROVM_PSEUDO_DEVICE_ID) {
+ return;
+ }
+
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index d3a20122a2ea..ed93d11c8ac6 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -31,6 +31,7 @@
#include <Library/ResourcePublicationLib.h>
#include <Ppi/MasterBootMode.h>
#include <IndustryStandard/I440FxPiix4.h>
+#include <IndustryStandard/Microvm.h>
#include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <IndustryStandard/QemuCpuHotplug.h>
@@ -714,7 +715,11 @@ InitializePlatform (
//
// Query Host Bridge DID
//
+#ifdef PLATFORM_IS_MICROVM
+ mHostBridgeDevId = MICROVM_PSEUDO_DEVICE_ID;
+#else
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+#endif

MaxCpuCountInitialization ();

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