Date   

Re: [PATCH v3 01/28] Ampere: Initial support for Ampere Altra processor and Mt. Jade platform

Nhi Pham
 

On 16/09/2021 17:46, Leif Lindholm wrote:
On Thu, Sep 16, 2021 at 11:40:45 +0100, Leif Lindholm wrote:
On Wed, Sep 15, 2021 at 22:55:00 +0700, Nhi Pham wrote:
From: Vu Nguyen <vunguyen@...>

This commit adds the support for Ampere’s Altra processor-based Mt. Jade
platform that provides up to 160 processor cores in a dual socket
configuration. The essential modules are wired up enough to boot system
to EDK2 UiApp.

Cc: Thang Nguyen <thang@...>
Cc: Chuong Tran <chuong@...>
Cc: Phong Vo <phong@...>
Cc: Leif Lindholm <leif@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>

Signed-off-by: Vu Nguyen <vunguyen@...>
Reviewed-by: Leif Lindholm <leif@...>
Err, actually, no.

You cannot give sign-off for Vu, but you need to sign off for
yourself. So we will need a v4.
If this patch in that set contains your Signed-off-by, and no-one
elses, that can retain my reviewed-by.
Will fix it.

Please address this situation for all other affected patches in the
set. But don't send out v4 vefore v3 review is complete.
Yes, will fix for all patches violating the sign-off rule.

Thanks,

-Nhi


Best Regards,

Leif


Re: [PATCH v3 00/28] Add new Ampere Mt. Jade platform

Nhi Pham
 

Hi Leif,

On 16/09/2021 17:09, Leif Lindholm wrote:
Hi Nhi,

On Wed, Sep 15, 2021 at 22:54:59 +0700, Nhi Pham wrote:
This patch series adds the support for the Mt. Jade platform based on Ampere's
Altra Family Processor.

Notes:
+ The current patch series was tested with the edk2-stable202108 tag.
+ the added common functions in EmbeddedPkg AcpiLib.
Thanks! Will add in the v4.

+ The IASL compiler version 20201217 is required to build.
+ The edk2-non-osi source is required to build.

You can get code from
https://github.com/AmpereComputing/edk2-platforms/tree/ampere-upstream-wip-v3

Cc: Vu Nguyen <vunguyen@...>
Cc: Nhi Pham <nhi@...>
Cc: Thang Nguyen <thang@...>
Cc: Chuong Tran <chuong@...>
Cc: Phong Vo <phong@...>
Cc: Leif Lindholm <leif@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>

Signed-off-by: Nhi Pham <nhi@...>

Changes since v2:
+ Addressed all Leif's feedback.
This feedback is a bit oversimplified.
There is an entirely new Ac01PcieLib component - which I could quickly
tell because the NOOPT target fails to build for me with:
Oops! Thanks, I will check the NOOPT target and fix in the v4.

---
Building ... /work/git/edk2/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf [AARCH64]
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c: In function ‘Ac01PcieCfgIn32’:
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c:261:42: error: variable ‘Sub’ set but not used [-Werror=unused-but-set-variable]
261 | UINT8 MfHt, Ht, Primary = 0, Sec = 0, Sub = 0;
| ^~~
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c:261:33: error: variable ‘Sec’ set but not used [-Werror=unused-but-set-variable]
261 | UINT8 MfHt, Ht, Primary = 0, Sec = 0, Sub = 0;
| ^~~
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c: In function ‘Ac01PcieCfgIn16’:
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c:324:38: error: variable ‘Sub’ set but not used [-Werror=unused-but-set-variable]
324 | UINT8 MfHt, Primary = 0, Sec = 0, Sub = 0;
| ^~~
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c:324:29: error: variable ‘Sec’ set but not used [-Werror=unused-but-set-variable]
324 | UINT8 MfHt, Primary = 0, Sec = 0, Sub = 0;
| ^~~
make: Nothing to be done for 'tbuild'.
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c: In function ‘Ac01PcieCoreQoSLinkCheckRecovery’:
/work/git/edk2-platforms/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c:1514:16: error: variable ‘CsrAddr’ set but not used [-Werror=unused-but-set-variable]
1514 | VOID *CsrAddr;
| ^~~~~~~
---

Looking at this module in general, I think I will have a fair amount
of feedback on it. But I'll get started with patches 1-11, which at v3
should be much more straightforward.
Thanks a lot for your useful feedback so far.

Have great weekend!

-Nhi

Best Regards,

Leif

Changes since v1:
+ Addressed all Leif's feedback in the thread
https://edk2.groups.io/g/devel/message/70356.
+ Removed the LinuxBoot image as Leif's feedback in the thread
https://edk2.groups.io/g/devel/message/68717. The image will be
pre-produced by users as the instruction in the README before compiling.
+ Other major code improvements from in-house review:
* Create new AmperePlatformPkg and AmpereSiliconPkg packages for
containing common Platform/Silicon modules.
* Remove SMProLib and PMProLib libraries which are replaced by the
MailboxInterfaceLib and SystemFirmwareInterfaceLib libraries for the
communication interface between UEFI and System Firmware.
* Clean up and fix coding styles to conform to EDK II C Coding
Standards Specification.


Nhi Pham (5):
AmperePlatformPkg: Implement FailSafe library
AmperePlatformPkg: Add FailSafe and WDT support
AmpereAltraPkg, JadePkg: Add ACPI support
JadePkg: Add ASpeed GOP driver
AmpereAltraPkg: Add configuration screen for ACPI

Quan Nguyen (3):
AmpereAltraPkg: Add BootProgress support
JadePkg: Add SMBIOS tables support
AmpereAltraPkg: Add configuration screen for RAS

Vu Nguyen (20):
Ampere: Initial support for Ampere Altra processor and Mt. Jade
platform
AmpereAltraPkg: Add MmCommunication modules
AmpereAltraPkg: Add DwI2cLib library
AmpereAltraPkg: Add DwGpioLib library
JadePkg: Implement RealTimeClockLib for PCF85063
AmpereAltraPkg: Support UEFI non-volatile variable
AmpereSiliconPkg: Add PlatformManagerUiLib library instance
AmpereAltraPkg: Add Ac01PcieLib library instance
JadePkg: Add BoardPcieLib library instance
Ampere: PCIe: Add PciHostBridgeLib library instance
Ampere: PCIe: Add PciSegmentLib library instance
JadePkg: Enable PCIe-related libraries and device drivers
Ampere: PCIe: Add PciPlatformDxe driver
AmpereAltraPkg: Add Random Number Generator Support
AmpereAltraPkg: Add DebugInfoPei module
AmpereAltraPkg: Add platform info screen
AmpereAltraPkg: Add configuration screen for memory
AmpereAltraPkg: Add configuration screen for CPU
AmpereAltraPkg: Add configuration screen for Watchdog timer
AmpereAltraPkg: Add configuration screen for Pcie Devices

.../AmperePlatformPkg/AmperePlatformPkg.dec | 31 +
.../Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 72 +
.../AmpereSiliconPkg/AmpereSiliconPkg.dec | 85 +
.../AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 748 +++
Platform/Ampere/JadePkg/Jade.dsc | 205 +
Platform/Ampere/JadePkg/Jade.fdf | 365 ++
.../Drivers/FailSafeDxe/FailSafeDxe.inf | 54 +
.../Library/FailSafeLib/FailSafeLib.inf | 41 +
.../Ampere/JadePkg/AcpiTables/AcpiTables.inf | 20 +
.../AcpiPlatformDxe/AcpiPlatformDxe.inf | 78 +
.../Drivers/PciPlatformDxe/PciPlatformDxe.inf | 37 +
.../SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf | 45 +
.../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 52 +
.../Library/BoardPcieLib/BoardPcieLib.inf | 59 +
.../JadePkg/Library/OemMiscLib/OemMiscLib.inf | 36 +
.../PCF85063RealTimeClockLib.inf | 44 +
.../AcpiCommonTables/AcpiCommonTables.inf | 44 +
.../Drivers/ATFHobPei/ATFHobPeim.inf | 41 +
.../Drivers/AcpiConfigDxe/AcpiConfigDxe.inf | 58 +
.../BootProgressDxe/BootProgressDxe.inf | 51 +
.../BootProgressPeim/BootProgressPeim.inf | 49 +
.../Drivers/CpuConfigDxe/CpuConfigDxe.inf | 58 +
.../Drivers/DebugInfoPei/DebugInfoPei.inf | 40 +
.../Drivers/FlashFvbDxe/FlashFvbDxe.inf | 54 +
.../Drivers/FlashPei/FlashPei.inf | 52 +
.../Drivers/MemInfoDxe/MemInfoDxe.inf | 59 +
.../Drivers/MemoryInitPeim/MemoryInitPeim.inf | 64 +
.../MmCommunicationDxe/MmCommunication.inf | 57 +
.../MmCommunicationPei/MmCommunicationPei.inf | 34 +
.../PlatformInfoDxe/PlatformInfoDxe.inf | 52 +
.../PlatformPcieDeviceConfigDxe.inf | 59 +
.../Drivers/RasConfigDxe/RasConfigDxe.inf | 56 +
.../AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf | 43 +
.../WatchdogConfigDxe/WatchdogConfigDxe.inf | 50 +
.../Library/Ac01PcieLib/Ac01PcieLib.inf | 67 +
.../Library/AmpereCpuLib/AmpereCpuLib.inf | 45 +
.../AmpereCpuLib/RuntimeAmpereCpuLib.inf | 50 +
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 57 +
.../Library/DwGpioLib/DwGpioLib.inf | 33 +
.../Library/DwI2cLib/DwI2cLib.inf | 38 +
.../Library/FlashLib/FlashLib.inf | 36 +
.../MailboxInterfaceLib.inf | 37 +
.../MemoryInitPeiLib/MemoryInitPeiLib.inf | 63 +
.../MmCommunicationLib/MmCommunicationLib.inf | 35 +
.../Library/NVParamLib/NVParamLib.inf | 32 +
.../PciHostBridgeLib/PciHostBridgeLib.inf | 48 +
.../PciSegmentLibPci/PciSegmentLibPci.inf | 28 +
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 42 +
.../AmpereAltraPkg/Library/RngLib/RngLib.inf | 29 +
.../SystemFirmwareInterfaceLib.inf | 30 +
.../Library/TrngLib/TrngLib.inf | 29 +
.../PlatformUiLib/PlatformManagerUiLib.inf | 47 +
.../Drivers/FailSafeDxe/FailSafe.h | 20 +
.../Drivers/FailSafeDxe/Watchdog.h | 29 +
.../Include/Library/FailSafeLib.h | 62 +
.../Drivers/AcpiPlatformDxe/AcpiApei.h | 126 +
.../Drivers/AcpiPlatformDxe/AcpiNfit.h | 49 +
.../Drivers/AcpiPlatformDxe/AcpiPlatform.h | 75 +
.../JadePkg/Library/BoardPcieLib/BoardPcie.h | 45 +
.../Library/BoardPcieLib/BoardPcieScreen.h | 114 +
.../Library/BoardPcieLib/BoardPcieVfr.h | 99 +
.../PCF85063RealTimeClockLib/PCF85063.h | 91 +
.../Drivers/AcpiConfigDxe/AcpiConfigDxe.h | 62 +
.../Drivers/CpuConfigDxe/CpuConfigDxe.h | 52 +
.../CpuConfigDxe/CpuConfigNVDataStruc.h | 19 +
.../Drivers/MemInfoDxe/MemInfoScreen.h | 170 +
.../MemInfoDxe/MemInfoScreenNVDataStruct.h | 47 +
.../MmCommunicationDxe/MmCommunicate.h | 22 +
.../Drivers/PlatformInfoDxe/PlatformInfoHii.h | 22 +
.../PlatformPcieDeviceConfigDxe.h | 78 +
.../PlatformPcieDeviceConfigVfr.h | 56 +
.../PlatformPcieHelper.h | 58 +
.../Drivers/RasConfigDxe/RasConfigDxe.h | 61 +
.../RasConfigDxe/RasConfigNVDataStruct.h | 46 +
.../WatchdogConfigDxe/WatchdogConfigDxe.h | 82 +
.../WatchdogConfigNVDataStruct.h | 27 +
.../AmpereAltraPkg/Include/Ac01PcieCommon.h | 128 +
.../Include/AcpiConfigNVDataStruct.h | 28 +
.../AmpereAltraPkg/Include/AcpiHeader.h | 37 +
.../Include/Guid/AcpiConfigFormSet.h | 19 +
.../Include/Guid/CpuConfigHii.h | 19 +
.../Include/Guid/PlatformInfoHobGuid.h | 17 +
.../Guid/PlatformPcieDeviceConfigHii.h | 19 +
.../Include/Guid/WatchdogConfigHii.h | 19 +
.../Include/Library/Ac01PcieLib.h | 163 +
.../Include/Library/AmpereCpuLib.h | 276 +
.../Include/Library/BoardPcieLib.h | 92 +
.../AmpereAltraPkg/Include/Library/FlashLib.h | 42 +
.../AmpereAltraPkg/Include/Library/GpioLib.h | 76 +
.../AmpereAltraPkg/Include/Library/I2cLib.h | 100 +
.../Include/Library/MailboxInterfaceLib.h | 172 +
.../Include/Library/MmCommunicationLib.h | 19 +
.../Include/Library/NVParamLib.h | 133 +
.../Library/SystemFirmwareInterfaceLib.h | 282 +
.../AmpereAltraPkg/Include/Library/TrngLib.h | 31 +
Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h | 79 +
.../AmpereAltraPkg/Include/NVParamDef.h | 525 ++
.../AmpereAltraPkg/Include/Platform/Ac01.h | 332 +
.../AmpereAltraPkg/Include/PlatformInfoHob.h | 182 +
.../Library/Ac01PcieLib/PcieCore.h | 649 ++
.../Library/Ac01PcieLib/PcieCoreCapCfg.h | 63 +
.../Library/Ac01PcieLib/PciePatchAcpi.h | 30 +
.../ArmPlatformLib/PlatformMemoryMap.h | 135 +
.../Include/Guid/PlatformManagerHii.h | 31 +
.../Library/PlatformUiLib/PlatformManager.h | 51 +
.../PlatformUiLib/PlatformManagerVfr.h | 28 +
.../Library/BoardPcieLib/BoardPcieVfr.vfr | 217 +
.../Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr | 69 +
.../Drivers/CpuConfigDxe/CpuConfigVfr.vfr | 43 +
.../Drivers/MemInfoDxe/MemInfoScreenVfr.vfr | 62 +
.../PlatformInfoDxe/PlatformInfoVfr.vfr | 112 +
.../PlatformPcieDeviceConfigVfr.vfr | 50 +
.../Drivers/RasConfigDxe/RasConfigVfr.vfr | 95 +
.../WatchdogConfigDxe/WatchdogConfigVfr.vfr | 58 +
.../Drivers/FailSafeDxe/FailSafeDxe.c | 184 +
.../Drivers/FailSafeDxe/Watchdog.c | 357 ++
.../Library/FailSafeLib/FailSafeLib.c | 313 +
.../Drivers/AcpiPlatformDxe/AcpiApei.c | 468 ++
.../Drivers/AcpiPlatformDxe/AcpiDsdt.c | 601 ++
.../Drivers/AcpiPlatformDxe/AcpiMadt.c | 348 +
.../Drivers/AcpiPlatformDxe/AcpiNfit.c | 596 ++
.../Drivers/AcpiPlatformDxe/AcpiPcct.c | 413 ++
.../Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c | 178 +
.../Drivers/AcpiPlatformDxe/AcpiPptt.c | 333 +
.../Drivers/AcpiPlatformDxe/AcpiSlit.c | 187 +
.../Drivers/AcpiPlatformDxe/AcpiSrat.c | 271 +
.../Drivers/PciPlatformDxe/PciPlatformDxe.c | 212 +
.../SmbiosMemInfoDxe/SmbiosMemInfoDxe.c | 705 +++
.../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 1049 +++
.../JadePkg/Library/BoardPcieLib/BoardPcie.c | 436 ++
.../Library/BoardPcieLib/BoardPcieCommon.c | 329 +
.../Library/BoardPcieLib/BoardPcieScreen.c | 1244 ++++
.../JadePkg/Library/OemMiscLib/OemMiscLib.c | 323 +
.../PCF85063RealTimeClockLib/PCF85063.c | 317 +
.../PCF85063RealTimeClockLib.c | 257 +
.../Drivers/ATFHobPei/ATFHobPeim.c | 52 +
.../Drivers/AcpiConfigDxe/AcpiConfigDxe.c | 729 +++
.../BootProgressDxe/BootProgressDxe.c | 211 +
.../BootProgressPeim/BootProgressPeim.c | 210 +
.../Drivers/CpuConfigDxe/CpuConfigDxe.c | 530 ++
.../Drivers/DebugInfoPei/DebugInfoPei.c | 210 +
.../Drivers/FlashFvbDxe/FlashFvbDxe.c | 525 ++
.../Drivers/FlashPei/FlashPei.c | 273 +
.../Drivers/MemInfoDxe/MemInfoNvramLib.c | 394 ++
.../Drivers/MemInfoDxe/MemInfoScreen.c | 1325 ++++
.../Drivers/MemoryInitPeim/MemoryInitPeim.c | 151 +
.../MmCommunicationDxe/MmCommunication.c | 454 ++
.../MmCommunicationPei/MmCommunicationPei.c | 37 +
.../Drivers/PlatformInfoDxe/PlatformInfoDxe.c | 391 ++
.../PlatformPcieDeviceConfigDxe.c | 1045 +++
.../PlatformPcieHelper.c | 191 +
.../Drivers/RasConfigDxe/RasConfigDxe.c | 822 +++
.../AmpereAltraPkg/Drivers/RngDxe/RngDxe.c | 164 +
.../WatchdogConfigDxe/WatchdogConfigDxe.c | 460 ++
.../Library/Ac01PcieLib/PcieCore.c | 1659 +++++
.../Library/Ac01PcieLib/PcieCoreLib.c | 556 ++
.../Library/Ac01PcieLib/PciePatchAcpi.c | 646 ++
.../Library/AmpereCpuLib/AmpereCpuLib.c | 43 +
.../Library/AmpereCpuLib/AmpereCpuLibCommon.c | 637 ++
.../AmpereCpuLib/RuntimeAmpereCpuLib.c | 138 +
.../Library/ArmPlatformLib/ArmPlatformLib.c | 169 +
.../ArmPlatformLib/ArmPlatformLibMemory.c | 257 +
.../Library/DwGpioLib/DwGpioLib.c | 314 +
.../Library/DwI2cLib/DwI2cLib.c | 883 +++
.../Library/FlashLib/FlashLib.c | 358 ++
.../MailboxInterfaceLib/MailboxInterfaceLib.c | 281 +
.../MemoryInitPeiLib/MemoryInitPeiLib.c | 93 +
.../MmCommunicationLib/MmCommunicationLib.c | 184 +
.../Library/NVParamLib/NVParamLib.c | 202 +
.../PciHostBridgeLib/PciHostBridgeLib.c | 378 ++
.../Library/PciSegmentLibPci/PciSegmentLib.c | 1189 ++++
.../Library/PlatformPeiLib/PlatformPeiLib.c | 40 +
.../AmpereAltraPkg/Library/RngLib/RngLib.c | 141 +
.../SystemFirmwareInterfaceLib.c | 328 +
.../AmpereAltraPkg/Library/TrngLib/TrngLib.c | 63 +
.../Library/PlatformUiLib/PlatformManager.c | 354 ++
.../Ampere/AmperePlatformPkg/FvRules.fdf.inc | 176 +
Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi | 5639 +++++++++++++++++
Platform/Ampere/JadePkg/AcpiTables/CPU-S1.asi | 5639 +++++++++++++++++
Platform/Ampere/JadePkg/AcpiTables/CPU.asi | 127 +
Platform/Ampere/JadePkg/AcpiTables/Dsdt.asl | 531 ++
.../Ampere/JadePkg/AcpiTables/PCI-PDRC.asi | 217 +
.../JadePkg/AcpiTables/PCI-S0.Rca01.asi | 681 ++
Platform/Ampere/JadePkg/AcpiTables/PCI-S0.asi | 2078 ++++++
Platform/Ampere/JadePkg/AcpiTables/PCI-S1.asi | 2087 ++++++
Platform/Ampere/JadePkg/AcpiTables/PMU-S0.asi | 1303 ++++
Platform/Ampere/JadePkg/AcpiTables/PMU-S1.asi | 1303 ++++
Platform/Ampere/JadePkg/AcpiTables/PMU.asi | 10 +
Platform/Ampere/JadePkg/JadeBoardSetting.cfg | 224 +
.../Library/BoardPcieLib/BoardPcieScreen.uni | 102 +
.../AmpereAltraPkg/AcpiCommonTables/Bert.aslc | 33 +
.../AmpereAltraPkg/AcpiCommonTables/Dbg2.aslc | 87 +
.../AmpereAltraPkg/AcpiCommonTables/Einj.asl | 165 +
.../AmpereAltraPkg/AcpiCommonTables/Fadt.aslc | 87 +
.../AmpereAltraPkg/AcpiCommonTables/Gtdt.aslc | 180 +
.../AmpereAltraPkg/AcpiCommonTables/Hest.asl | 330 +
.../AmpereAltraPkg/AcpiCommonTables/Sdei.asl | 17 +
.../AmpereAltraPkg/AcpiCommonTables/Spcr.aslc | 81 +
.../AmpereAltraPkg/AcpiCommonTables/Ssdt.asl | 15 +
.../AcpiConfigDxe/AcpiConfigStrings.uni | 27 +
.../BootProgressDxe/BootProgressDxe.uni | 16 +
.../BootProgressPeim/BootProgressPeim.uni | 18 +
.../Drivers/CpuConfigDxe/CpuConfigStrings.uni | 17 +
.../Drivers/MemInfoDxe/MemInfoDxe.uni | 9 +
.../Drivers/MemInfoDxe/MemInfoDxeExtra.uni | 9 +
.../MemInfoDxe/MemInfoScreenStrings.uni | 64 +
.../PlatformInfoDxe/PlatformInfoStrings.uni | 56 +
.../PlatformPcieDeviceConfigDxe.uni | 24 +
.../Drivers/RasConfigDxe/RasConfigStrings.uni | 38 +
.../AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni | 10 +
.../Drivers/RngDxe/RngDxeExtra.uni | 9 +
.../WatchdogConfigStrings.uni | 26 +
.../ArmPlatformLib/ArmPlatformHelper.S | 45 +
.../AmpereAltraPkg/Library/RngLib/RngLib.uni | 13 +
.../PlatformUiLib/PlatformManagerStrings.uni | 21 +
.../PlatformUiLib/PlatformManagerUiLib.uni | 13 +
.../PlatformUiLib/PlatformManagerVfr.Vfr | 29 +
217 files changed, 57398 insertions(+)
create mode 100644 Platform/Ampere/AmperePlatformPkg/AmperePlatformPkg.dec
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
create mode 100644 Platform/Ampere/JadePkg/Jade.dsc
create mode 100644 Platform/Ampere/JadePkg/Jade.fdf
create mode 100644 Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/FailSafeDxe.inf
create mode 100644 Platform/Ampere/AmperePlatformPkg/Library/FailSafeLib/FailSafeLib.inf
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
create mode 100644 Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf
create mode 100644 Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
create mode 100644 Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf
create mode 100644 Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf
create mode 100644 Platform/Ampere/JadePkg/Library/PCF85063RealTimeClockLib/PCF85063RealTimeClockLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/Ac01PcieLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.inf
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManagerUiLib.inf
create mode 100644 Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/FailSafe.h
create mode 100644 Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/Watchdog.h
create mode 100644 Platform/Ampere/AmperePlatformPkg/Include/Library/FailSafeLib.h
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.h
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcie.h
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieScreen.h
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieVfr.h
create mode 100644 Platform/Ampere/JadePkg/Library/PCF85063RealTimeClockLib/PCF85063.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigNVDataStruc.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunicate.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigDxe.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigVfr.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieHelper.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigNVDataStruct.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Ac01PcieCommon.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigFormSet.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHobGuid.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformPcieDeviceConfigHii.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Guid/WatchdogConfigHii.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/Ac01PcieLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/BoardPcieLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/FlashLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/GpioLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/I2cLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCoreCapCfg.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PciePatchAcpi.h
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap.h
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Include/Guid/PlatformManagerHii.h
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManager.h
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManagerVfr.h
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigVfr.vfr
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigVfr.vfr
create mode 100644 Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/FailSafeDxe.c
create mode 100644 Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/Watchdog.c
create mode 100644 Platform/Ampere/AmperePlatformPkg/Library/FailSafeLib/FailSafeLib.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPcct.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSlit.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.c
create mode 100644 Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcie.c
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieCommon.c
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieScreen.c
create mode 100644 Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.c
create mode 100644 Platform/Ampere/JadePkg/Library/PCF85063RealTimeClockLib/PCF85063.c
create mode 100644 Platform/Ampere/JadePkg/Library/PCF85063RealTimeClockLib/PCF85063RealTimeClockLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieHelper.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCoreLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PciePatchAcpi.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManager.c
create mode 100644 Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/CPU-S1.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/CPU.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/Dsdt.asl
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PCI-PDRC.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PCI-S0.Rca01.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PCI-S0.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PCI-S1.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PMU-S0.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PMU-S1.asi
create mode 100644 Platform/Ampere/JadePkg/AcpiTables/PMU.asi
create mode 100644 Platform/Ampere/JadePkg/JadeBoardSetting.cfg
create mode 100644 Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieScreen.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Bert.aslc
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Dbg2.aslc
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Einj.asl
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Fadt.aslc
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Gtdt.aslc
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Hest.asl
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Sdei.asl
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Spcr.aslc
create mode 100644 Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Ssdt.asl
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxeExtra.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformPcieDeviceConfigDxe/PlatformPcieDeviceConfigDxe.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxeExtra.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigStrings.uni
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S
create mode 100644 Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManagerStrings.uni
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManagerUiLib.uni
create mode 100644 Silicon/Ampere/AmpereSiliconPkg/Library/PlatformUiLib/PlatformManagerVfr.Vfr

--
2.17.1


Re: [PATCH v3] OvmfPkg: set a default value for the WorkAreaHeader PCD

Corvin Köhne
 

Hi Yao,

looks like the patch isn't formatted correctly. Could you try to apply this patch:

From 3c22fffad51e431fbf953809215eea7022168e81 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Corvin=20K=C3=B6hne?= <c.koehne@...>
Date: Fri, 17 Sep 2021 07:37:24 +0200
Subject: [PATCH] OvmfPkg: set a default value for the WorkAreaHeader PCD
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

SEC checks in IsSevGuest if the PCD defined WorkAreaHeader size
matches the size of the WorkAreaHeader struct definition. Set a
default value for the PCD to avoid unnecessary DSC/FDF file
changes in all OVMF DSC/FDF files.

Signed-off-by: Corvin Köhne <c.koehne@...>
Reviewed-by: Jiewen Yao <jiewen.yao@...>
---
OvmfPkg/Include/WorkArea.h | 4 ++++
OvmfPkg/OvmfPkg.dec | 7 ++++++-
OvmfPkg/OvmfPkgDefines.fdf.inc | 6 ------
3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/Include/WorkArea.h b/OvmfPkg/Include/WorkArea.h
index c16030e3ac..0f9b442e43 100644
--- a/OvmfPkg/Include/WorkArea.h
+++ b/OvmfPkg/Include/WorkArea.h
@@ -25,6 +25,10 @@ typedef enum {
// to the structure need to be kept in sync with the
// PcdOvmfConfidentialComputingWorkAreaHeader.
//
+// PcdOvmfConfidentialComputingWorkAreaHeader ==
+// sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+//
+// PcdOvmfConfidentialComputingWorkAreaHeader defined in OvmfPkg/OvmfPkg.dec
typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER {
UINT8 GuestType;
UINT8 Reserved1[3];
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index c37dafad49..a5119b1909 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -338,7 +338,12 @@
# The size of this header is used early boot, and is provided through
# a fixed PCD. It need to be kept in sync with any changes to the
# header definition.
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|0|UINT32|0x51
+ #
+ # PcdOvmfConfidentialComputingWorkAreaHeader ==
+ # sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+ #
+ # CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER defined in OvmfPkg/Include/WorkArea.h
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51


[PcdsDynamic, PcdsDynamicEx]
diff --git a/OvmfPkg/OvmfPkgDefines.fdf.inc b/OvmfPkg/OvmfPkgDefines.fdf.inc
index 3b5e452539..35fd454b97 100644
--- a/OvmfPkg/OvmfPkgDefines.fdf.inc
+++ b/OvmfPkg/OvmfPkgDefines.fdf.inc
@@ -82,12 +82,6 @@ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(BLOCK_SIZ
SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(VARS_SPARE_SIZE)

-# The OVMF WorkArea contains a fixed size header followed by the actual data.
-# The size of header is accessed through a fixed PCD in the reset vector code.
-# The value need to be kept in sync with the any changes to the Confidential
-# Computing Work Area header defined in the Include/WorkArea.h
-SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader = 4
-
!if $(SMM_REQUIRE) == TRUE
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase
--
2.11.0



Thanks
Corvin

-----Original Message-----
From: Yao, Jiewen <jiewen.yao@...>
Sent: Friday, September 17, 2021 5:23 AM
To: Corvin Köhne <C.Koehne@...>; devel@edk2.groups.io
Cc: ardb+tianocore@...; jordan.l.ljusten@...; kraxel@...; rebecca@...; grehan@...; Corvin Köhne <C.Koehne@...>
Subject: RE: [PATCH v3] OvmfPkg: set a default value for the WorkAreaHeader PCD

CAUTION: External Email!!


Hi Corvin
I try to apply this patch and merge. But I got error:

================
git.exe am --3way --ignore-space-change --keep-cr "C:\home\edkii\edk2\[PATCH-v3]-OvmfPkg-set-a-default-value-for-the-WorkAreaHeader-PCD-warn.patch"
Applying: OvmfPkg: set a default value for the WorkAreaHeader PCD Patch failed at 0001 OvmfPkg: set a default value for the WorkAreaHeader PCD When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

error: corrupt patch at line 38
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch

Fail
=================

Would you please take a look?

Thank you
Yao Jiewen


-----Original Message-----
From: Corvin Köhne <c.koehne@...>
Sent: Thursday, September 16, 2021 5:03 PM
To: devel@edk2.groups.io
Cc: ardb+tianocore@...; Yao, Jiewen <jiewen.yao@...>;
jordan.l.ljusten@...; kraxel@...; rebecca@...;
grehan@...; Köhne, Corvin <c.koehne@...>
Subject: [PATCH v3] OvmfPkg: set a default value for the
WorkAreaHeader PCD

SEC checks in IsSevGuest if the PCD defined WorkAreaHeader size
matches the size of the WorkAreaHeader struct definition. Set a
default value for the PCD to avoid unnecessary DSC/FDF file changes in
all OVMF DSC/FDF files.

Signed-off-by: Corvin Köhne <c.koehne@...>
Reviewed-by: Jiewen Yao <jiewen.yao@...>
---
OvmfPkg/Include/WorkArea.h | 4 ++++
OvmfPkg/OvmfPkg.dec | 7 ++++++-
OvmfPkg/OvmfPkgDefines.fdf.inc | 6 ------
3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/Include/WorkArea.h b/OvmfPkg/Include/WorkArea.h
index c16030e3ac..0f9b442e43 100644
--- a/OvmfPkg/Include/WorkArea.h
+++ b/OvmfPkg/Include/WorkArea.h
@@ -25,6 +25,10 @@ typedef enum {
// to the structure need to be kept in sync with the //
PcdOvmfConfidentialComputingWorkAreaHeader.
//
+// PcdOvmfConfidentialComputingWorkAreaHeader ==
+// sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+//
+// PcdOvmfConfidentialComputingWorkAreaHeader defined in
OvmfPkg/OvmfPkg.dec
typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER {
UINT8 GuestType;
UINT8 Reserved1[3];
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index
c37dafad49..a5119b1909 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -338,7 +338,12 @@
# The size of this header is used early boot, and is provided through
# a fixed PCD. It need to be kept in sync with any changes to the
# header definition.
-
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r|0|UINT32|0x51
+ #
+ # PcdOvmfConfidentialComputingWorkAreaHeader ==
+ # sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+ #
+ # CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER defined in
OvmfPkg/Include/WorkArea.h
+
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r|4|UINT32|0x51


[PcdsDynamic, PcdsDynamicEx]
diff --git a/OvmfPkg/OvmfPkgDefines.fdf.inc
b/OvmfPkg/OvmfPkgDefines.fdf.inc index 3b5e452539..35fd454b97 100644
--- a/OvmfPkg/OvmfPkgDefines.fdf.inc
+++ b/OvmfPkg/OvmfPkgDefines.fdf.inc
@@ -82,12 +82,6 @@ SET
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
$(BLOCK_SIZ SET
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =
$(VARS_SPARE_SIZE)

-# The OVMF WorkArea contains a fixed size header followed by the actual data.
-# The size of header is accessed through a fixed PCD in the reset vector code.
-# The value need to be kept in sync with the any changes to the
Confidential -# Computing Work Area header defined in the
Include/WorkArea.h -SET
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r = 4
-
!if $(SMM_REQUIRE) == TRUE
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase
--
2.11.0

Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys.
Hans Beckhoff Registered office: Verl, Germany | Register court:
Guetersloh HRA
7075
Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans Beckhoff Registered office: Verl, Germany | Register court: Guetersloh HRA 7075


Re: [PATCH v3] OvmfPkg: set a default value for the WorkAreaHeader PCD

Yao, Jiewen
 

Hi Corvin
I try to apply this patch and merge. But I got error:

================
git.exe am --3way --ignore-space-change --keep-cr "C:\home\edkii\edk2\[PATCH-v3]-OvmfPkg-set-a-default-value-for-the-WorkAreaHeader-PCD-warn.patch"
Applying: OvmfPkg: set a default value for the WorkAreaHeader PCD
Patch failed at 0001 OvmfPkg: set a default value for the WorkAreaHeader PCD
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

error: corrupt patch at line 38
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch

Fail
=================

Would you please take a look?

Thank you
Yao Jiewen

-----Original Message-----
From: Corvin Köhne <c.koehne@...>
Sent: Thursday, September 16, 2021 5:03 PM
To: devel@edk2.groups.io
Cc: ardb+tianocore@...; Yao, Jiewen <jiewen.yao@...>;
jordan.l.ljusten@...; kraxel@...; rebecca@...;
grehan@...; Köhne, Corvin <c.koehne@...>
Subject: [PATCH v3] OvmfPkg: set a default value for the WorkAreaHeader PCD

SEC checks in IsSevGuest if the PCD defined WorkAreaHeader size
matches the size of the WorkAreaHeader struct definition. Set a
default value for the PCD to avoid unnecessary DSC/FDF file
changes in all OVMF DSC/FDF files.

Signed-off-by: Corvin Köhne <c.koehne@...>
Reviewed-by: Jiewen Yao <jiewen.yao@...>
---
OvmfPkg/Include/WorkArea.h | 4 ++++
OvmfPkg/OvmfPkg.dec | 7 ++++++-
OvmfPkg/OvmfPkgDefines.fdf.inc | 6 ------
3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/Include/WorkArea.h b/OvmfPkg/Include/WorkArea.h
index c16030e3ac..0f9b442e43 100644
--- a/OvmfPkg/Include/WorkArea.h
+++ b/OvmfPkg/Include/WorkArea.h
@@ -25,6 +25,10 @@ typedef enum {
// to the structure need to be kept in sync with the
// PcdOvmfConfidentialComputingWorkAreaHeader.
//
+// PcdOvmfConfidentialComputingWorkAreaHeader ==
+// sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+//
+// PcdOvmfConfidentialComputingWorkAreaHeader defined in
OvmfPkg/OvmfPkg.dec
typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER {
UINT8 GuestType;
UINT8 Reserved1[3];
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index c37dafad49..a5119b1909 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -338,7 +338,12 @@
# The size of this header is used early boot, and is provided through
# a fixed PCD. It need to be kept in sync with any changes to the
# header definition.
-
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r|0|UINT32|0x51
+ #
+ # PcdOvmfConfidentialComputingWorkAreaHeader ==
+ # sizeof (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER)
+ #
+ # CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER defined in
OvmfPkg/Include/WorkArea.h
+
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r|4|UINT32|0x51


[PcdsDynamic, PcdsDynamicEx]
diff --git a/OvmfPkg/OvmfPkgDefines.fdf.inc
b/OvmfPkg/OvmfPkgDefines.fdf.inc
index 3b5e452539..35fd454b97 100644
--- a/OvmfPkg/OvmfPkgDefines.fdf.inc
+++ b/OvmfPkg/OvmfPkgDefines.fdf.inc
@@ -82,12 +82,6 @@ SET
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
$(BLOCK_SIZ
SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =
$(VARS_SPARE_SIZE)

-# The OVMF WorkArea contains a fixed size header followed by the actual data.
-# The size of header is accessed through a fixed PCD in the reset vector code.
-# The value need to be kept in sync with the any changes to the Confidential
-# Computing Work Area header defined in the Include/WorkArea.h
-SET
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeade
r = 4
-
!if $(SMM_REQUIRE) == TRUE
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase
--
2.11.0

Beckhoff Automation GmbH & Co. KG | Managing Director: Dipl. Phys. Hans
Beckhoff Registered office: Verl, Germany | Register court: Guetersloh HRA
7075


Re: [PATCH V2 1/1] SecurityPkg: Add debug log for indicating IBB verified OBB successfully

Wang, Jian J
 

Reviewed-by: Jian J Wang <jian.j.wang@...>

Regards,
Jian

-----Original Message-----
From: Yang, Longlong <longlong.yang@...>
Sent: Friday, September 17, 2021 10:51 AM
To: devel@edk2.groups.io
Cc: Yang, Longlong <longlong.yang@...>; Yao, Jiewen
<jiewen.yao@...>; Wang, Jian J <jian.j.wang@...>; Xu, Min M
<min.m.xu@...>; Zhang, Qi1 <qi1.zhang@...>
Subject: [PATCH V2 1/1] SecurityPkg: Add debug log for indicating IBB verified
OBB successfully

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3615

Debug message should be added for indicating IBB is successfully verifying
the OBB.

Cc: Jiewen Yao <jiewen.yao@...>
Cc: Jian J Wang <jian.j.wang@...>
Cc: Min M Xu <min.m.xu@...>
Cc: Qi Zhang <qi1.zhang@...>
Signed-off-by: Longlong Yang <longlong.yang@...>
---
SecurityPkg/FvReportPei/FvReportPei.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/SecurityPkg/FvReportPei/FvReportPei.c
b/SecurityPkg/FvReportPei/FvReportPei.c
index e82413e090c0..9f3ebd8ed174 100644
--- a/SecurityPkg/FvReportPei/FvReportPei.c
+++ b/SecurityPkg/FvReportPei/FvReportPei.c
@@ -344,6 +344,8 @@ CheckStoredHashFv (
StoredHashFvPpi->FvNumber, BootMode);
if (!EFI_ERROR (Status)) {

+ DEBUG ((DEBUG_INFO, "OBB verification passed (%r)\r\n", Status));
+
//
// Report the FVs to PEI core and/or DXE core.
//
--
2.31.1.windows.1


回复: [PATCH v1 0/3] Add MM Communication PPI definition to MdePkg

gaoliming
 

Reviewed-by: Liming Gao <gaoliming@...>

-----邮件原件-----
发件人: Kun Qin <kuqin12@...>
发送时间: 2021年9月16日 8:14
收件人: devel@edk2.groups.io
抄送: Michael D Kinney <michael.d.kinney@...>; Liming Gao
<gaoliming@...>; Zhiguang Liu <zhiguang.liu@...>; Sean
Brogan <sean.brogan@...>; Jian J Wang <jian.j.wang@...>
主题: [PATCH v1 0/3] Add MM Communication PPI definition to MdePkg

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629

EFI_PEI_MM_COMMUNICATION_PPI is defined since PI spec v1.5. This patch
series added the interface definition and related GUIDs into MdePkg.

Given gEfiPeiSmmCommunicationPpiGuid and
gEfiPeiMmCommunicationPpiGuid
have the same value, CI build files are also updated accordingly to avoid
build failure caused by duplicate GUIDs.

Patch v1 branch:
https://github.com/kuqin12/edk2/tree/mm_communicate_ppi

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Sean Brogan <sean.brogan@...>
Cc: Jian J Wang <jian.j.wang@...>

Kun Qin (3):
MdePkg: MmCommunication: Added definition of MM Communication PPI
MdePkg: CI YAML: Added new GUID to ignore duplicate list
MdeModulePkg: CI YAML: Added new GUID to ignore duplicate list

MdeModulePkg/MdeModulePkg.ci.yaml | 1 +
MdePkg/Include/Ppi/MmCommunication.h | 72 ++++++++++++++++++++
MdePkg/MdePkg.ci.yaml | 3 +-
MdePkg/MdePkg.dec | 3 +
4 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/Ppi/MmCommunication.h

--
2.32.0.windows.1


回复: [PATCH 1/1] BaseTools: Change RealPath to AbsPath

gaoliming
 

Is there any other case to use RealPath in BaseTools? Or, have you confirm
that all RealPath usage have been removed?

Liming

-----邮件原件-----
发件人: Yuwei Chen <yuwei.chen@...>
发送时间: 2021年9月16日 14:59
收件人: devel@edk2.groups.io
抄送: Bob Feng <bob.c.feng@...>; Liming Gao
<gaoliming@...>
主题: [PATCH 1/1] BaseTools: Change RealPath to AbsPath

Currently the realpath is used when parse modules, which shows the
path with a drive letter in build log. In Windows 'subst' comand is
used to associates a path with a drive letter, when use the mapped
drive letter for build, with realpath function the build log will
have different disk letter info which will cause confusion. In this
situation, if use adspath function to show the path info, it will keep
same letter with the mapped drive letter, which avoids confusion.
This patch modifies the realpath to abspath.

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Signed-off-by: Yuwei Chen <yuwei.chen@...>
---
BaseTools/Source/Python/GenFds/FfsInfStatement.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FfsInfStatement.py
b/BaseTools/Source/Python/GenFds/FfsInfStatement.py
index 20573ca28d2f..568efb6d7685 100644
--- a/BaseTools/Source/Python/GenFds/FfsInfStatement.py
+++ b/BaseTools/Source/Python/GenFds/FfsInfStatement.py
@@ -707,8 +707,8 @@ class FfsInfStatement(FfsInfStatementClassObject):
FileName,
'DEBUG'
)
- OutputPath = os.path.realpath(OutputPath)
- DebugPath = os.path.realpath(DebugPath)
+ OutputPath = os.path.abspath(OutputPath)
+ DebugPath = os.path.abspath(DebugPath)
return OutputPath, DebugPath

## __GenSimpleFileSection__() method
--
2.26.1.windows.1


Re: [edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Chiu, Chasel
 

Reviewed-by: Chasel Chiu <chasel.chiu@...>

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Thursday, September 16, 2021 3:05 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel
<chasel.chiu@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 2/2]
WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Add PlatformSecLib
so that we can build SecCore.
This uses FSP TempRamInit API in dispatch mode, but directly
tears down NEM as a workaround because the current FSP binaries
do not properly produce the TEMP_RAM_EXIT_PPI.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Fs
pWrapperPlatformSecLib.c | 159 +++++++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
32/Fsp.h | 43 +++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
32/PeiCoreEntry.nasm | 124 +++++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
32/SecEntry.nasm | 338 ++++++++++++++++++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia
32/Stack.nasm | 71 ++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Pl
atformInit.c | 48 +++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
cFspWrapperPlatformSecLib.inf | 103 ++++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
cGetPerformance.c | 90 ++++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
cPlatformInformation.c | 79 +++++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
cRamInitData.c | 29 ++

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Se
cTempRamDone.c | 130 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
| 30 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
| 30 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec |
2 -
14 files changed, 1248 insertions(+), 28 deletions(-)

diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
FspWrapperPlatformSecLib.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
FspWrapperPlatformSecLib.c
new file mode 100644
index 0000000000..5e0f2ff1ac
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
FspWrapperPlatformSecLib.c
@@ -0,0 +1,159 @@
+/** @file
+ Sample to provide FSP wrapper platform sec related function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+#include <Ppi/PeiCoreFvLocation.h>
+
+#include <Library/LocalApicLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into
PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of
the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the
EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
*PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC)
phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an
optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data
in SEC,
+ this information is encapsulated into the data structure abstracted by this
service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the
PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC
phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
+ SecGetPerformance
+};
+
+EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
+ (VOID *) (UINTN) FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiPeiCoreFvLocationPpiGuid,
+ &mPeiCoreFvLocationPpi
+ }
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
+ //
+ // This must be the first PPI in the list because it will be patched in
SecPlatformMain ();
+ //
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gTopOfTemporaryRamPpiGuid,
+ NULL
+ }
+};
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param[in,out] SecCoreData The same parameter as passing to PEI
core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ )
+{
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINT8 TopOfTemporaryRamPpiIndex;
+ UINT8 *CopyDestinationPointer;
+ UINTN ReservedSize;
+
+ DEBUG((DEBUG_INFO, "SecPlatformMain\n"));
+
+ ReservedSize = ALIGN_VALUE (PcdGet32 (PcdPeiTemporaryRamRcHeapSize),
SIZE_4KB);
+ ReservedSize += ALIGN_VALUE (PcdGet32 (PcdFspTemporaryRamSize),
SIZE_4KB);
+
+ SecCoreData->PeiTemporaryRamBase = (UINT8 *) SecCoreData-
PeiTemporaryRamBase + ReservedSize;
+ SecCoreData->PeiTemporaryRamSize -= ReservedSize;
+
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n",
SecCoreData->BootFirmwareVolumeBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n",
SecCoreData->BootFirmwareVolumeSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n",
SecCoreData->TemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n",
SecCoreData->TemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n",
SecCoreData->PeiTemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n",
SecCoreData->PeiTemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n",
SecCoreData->StackBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
SecCoreData->StackSize));
+
+ InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
+
+ //
+ // Use middle of Heap as temp buffer, it will be copied by caller.
+ // Do not use Stack, because it will cause wrong calculation on stack by
PeiCore
+ //
+ PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN)
SecCoreData->PeiTemporaryRamSize/2);
+ CopyDestinationPointer = (UINT8 *) PpiList;
+ TopOfTemporaryRamPpiIndex = 0;
+ if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool
(PcdFspDispatchModeUseFspPeiMain)) {
+ //
+ // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
+ //
+ CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
(mPeiCoreFvLocationPpiList));
+ TopOfTemporaryRamPpiIndex = 1;
+ CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
+ }
+ CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof
(mPeiSecPlatformPpi));
+ //
+ // Patch TopOfTemporaryRamPpi
+ //
+ PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData-
TemporaryRamBase + SecCoreData->TemporaryRamSize);
+
+ return PpiList;
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Fsp.h
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Fsp.h
new file mode 100644
index 0000000000..0a8d9bf74a
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Fsp.h
@@ -0,0 +1,43 @@
+/** @file
+ Fsp related definitions
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __FSP_H__
+#define __FSP_H__
+
+//
+// Fv Header
+//
+#define FVH_SIGINATURE_OFFSET 0x28
+#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
+#define FVH_HEADER_LENGTH_OFFSET 0x30
+#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
+#define FVH_EXTHEADER_SIZE_OFFSET 0x10
+
+//
+// Ffs Header
+//
+#define FSP_HEADER_GUID_DWORD1 0x912740BE
+#define FSP_HEADER_GUID_DWORD2 0x47342284
+#define FSP_HEADER_GUID_DWORD3 0xB08471B9
+#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
+#define FFS_HEADER_SIZE_VALUE 0x18
+
+//
+// Section Header
+//
+#define SECTION_HEADER_TYPE_OFFSET 0x03
+#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
+
+//
+// Fsp Header
+//
+#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
+
+#endif
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/PeiCoreEntry.nasm
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/PeiCoreEntry.nasm
new file mode 100644
index 0000000000..917411cac2
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/PeiCoreEntry.nasm
@@ -0,0 +1,124 @@
+;------------------------------------------------------------------------------
+; @file PeiCoreEntry.nasm
+; Find and call SecStartup
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+SECTION .text
+
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
+
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
+ ;
+ ; Obtain the hob list pointer
+ ;
+ mov eax, [esp+4]
+ ;
+ ; Obtain the stack information
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ecx, [esp+8]
+ mov edx, [esp+0xC]
+
+ ;
+ ; Platform init
+ ;
+ pushad
+ push edx
+ push ecx
+ push eax
+ call ASM_PFX(PlatformInit)
+ pop eax
+ pop eax
+ pop eax
+ popad
+
+ ;
+ ; Set stack top pointer
+ ;
+ mov esp, edx
+
+ ;
+ ; Push the hob list pointer
+ ;
+ push eax
+
+ ;
+ ; Save the value
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ebp, esp
+ push ecx
+ push edx
+
+ ;
+ ; Push processor count to stack first, then BIST status (AP then BSP)
+ ;
+ mov eax, 1
+ cpuid
+ shr ebx, 16
+ and ebx, 0xFF
+ cmp bl, 1
+ jae PushProcessorCount
+
+ ;
+ ; Some processors report 0 logical processors. Effectively 0 = 1.
+ ; So we fix up the processor count
+ ;
+ inc ebx
+
+PushProcessorCount:
+ push ebx
+
+ ;
+ ; We need to implement a long-term solution for BIST capture. For now, we
just copy BSP BIST
+ ; for all processor threads
+ ;
+ xor ecx, ecx
+ mov cl, bl
+PushBist:
+ movd eax, mm0
+ push eax
+ loop PushBist
+
+ ; Save Time-Stamp Counter
+ movd eax, mm5
+ push eax
+
+ movd eax, mm6
+ push eax
+
+ ;
+ ; Pass entry point of the PEI core
+ ;
+ mov edi, 0xFFFFFFE0
+ push DWORD [edi]
+
+ ;
+ ; Pass BFV into the PEI Core
+ ;
+ mov edi, 0xFFFFFFFC
+ push DWORD [edi]
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ mov ecx, [ebp - 4]
+ mov edx, [ebp - 8]
+ push ecx ; RamBase
+
+ sub edx, ecx
+ push edx ; RamSize
+
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ call ASM_PFX(SecStartup)
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/SecEntry.nasm
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/SecEntry.nasm
new file mode 100644
index 0000000000..091990d627
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/SecEntry.nasm
@@ -0,0 +1,338 @@
+;------------------------------------------------------------------------------
+; @file SecEntry.nasm
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+#include "Fsp.h"
+
+SECTION .text
+
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+extern ASM_PFX(BoardBeforeTempRamInit)
+
+; Pcds
+extern ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))
+
+;----------------------------------------------------------------------------
+;
+; Procedure: _ModuleEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; Transition to non-paged flat-model protected mode from a
+; hard-coded GDT that provides exactly two descriptors.
+; This is a bare bones transition to protected mode only
+; used for a while in PEI and possibly DXE.
+;
+; After enabling protected mode, a far jump is executed to
+; transfer to PEI using the newly loaded GDT.
+;
+; Return: None
+;
+; MMX Usage:
+; MM0 = BIST State
+; MM5 = Save time-stamp counter value high32bit
+; MM6 = Save time-stamp counter value low32bit.
+;
+;----------------------------------------------------------------------------
+
+BITS 16
+align 4
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+ fninit ; clear any pending Floating point exceptions
+ ;
+ ; Store the BIST value in mm0
+ ;
+ movd mm0, eax
+
+ ;
+ ; Save time-stamp counter value
+ ; rdtsc load 64bit time-stamp counter to EDX:EAX
+ ;
+ rdtsc
+ movd mm5, edx
+ movd mm6, eax
+
+ ;
+ ; Load the GDT table in GdtDesc
+ ;
+ mov esi, GdtDesc
+ DB 66h
+ lgdt [cs:si]
+
+ ;
+ ; Transition to 16 bit protected mode
+ ;
+ mov eax, cr0 ; Get control register 0
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
+ mov cr0, eax ; Activate protected mode
+
+ mov eax, cr4 ; Get control register 4
+ or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit
#10)
+ mov cr4, eax
+
+ ;
+ ; Now we're in 16 bit protected mode
+ ; Set up the selectors for 32 bit protected mode entry
+ ;
+ mov ax, SYS_DATA_SEL
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ ;
+ ; Transition to Flat 32 bit protected mode
+ ; The jump to a far pointer causes the transition to 32 bit mode
+ ;
+ mov esi, ProtectedModeEntryLinearAddress
+ jmp dword far [cs:si]
+
+;----------------------------------------------------------------------------
+;
+; Procedure: ProtectedModeEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; This function handles:
+; Call two basic APIs from FSP binary
+; Initializes stack with some early data (BIST, PEI entry, etc)
+;
+; Return: None
+;
+;----------------------------------------------------------------------------
+
+BITS 32
+align 4
+ProtectedModeEntryPoint:
+ ;
+ ; Early board hooks
+ ;
+ mov esp, BoardBeforeTempRamInitRet
+ jmp ASM_PFX(BoardBeforeTempRamInit)
+
+BoardBeforeTempRamInitRet:
+
+ ; Find the fsp info header
+ mov edi, [ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))]
+
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
+ cmp eax, FVH_SIGINATURE_VALID_VALUE
+ jnz FspHeaderNotFound
+
+ xor eax, eax
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ cmp ax, 0
+ jnz FspFvExtHeaderExist
+
+ xor eax, eax
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ add edi, eax
+ jmp FspCheckFfsHeader
+
+FspFvExtHeaderExist:
+ add edi, eax
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
Header
+ add edi, eax
+
+ ; Round up to 8 byte alignment
+ mov eax, edi
+ and al, 07h
+ jz FspCheckFfsHeader
+
+ and edi, 0FFFFFFF8h
+ add edi, 08h
+
+FspCheckFfsHeader:
+ ; Check the ffs guid
+ mov eax, dword [edi]
+ cmp eax, FSP_HEADER_GUID_DWORD1
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 4]
+ cmp eax, FSP_HEADER_GUID_DWORD2
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 8]
+ cmp eax, FSP_HEADER_GUID_DWORD3
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 0Ch]
+ cmp eax, FSP_HEADER_GUID_DWORD4
+ jnz FspHeaderNotFound
+
+ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
+
+ ; Check the section type as raw section
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
+ cmp al, 019h
+ jnz FspHeaderNotFound
+
+ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
+ jmp FspHeaderFound
+
+FspHeaderNotFound:
+ jmp $
+
+FspHeaderFound:
+ ; Get the fsp TempRamInit Api address
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
+ add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+
+ ; Setup the hardcode stack
+ mov esp, TempRamInitStack
+
+ ; Call the fsp TempRamInit Api
+ jmp eax
+
+TempRamInitDone:
+ cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for
Microcode Update not found.
+ je CallSecFspInit ;If microcode not found, don't hang, but continue.
+
+ cmp eax, 0 ;Check if EFI_SUCCESS retuned.
+ jnz FspApiFailed
+
+ ; ECX: start of range
+ ; EDX: end of range
+CallSecFspInit:
+ xor eax, eax
+ mov esp, edx
+
+ ; Align the stack at DWORD
+ add esp, 3
+ and esp, 0FFFFFFFCh
+
+ push edx
+ push ecx
+ push eax ; zero - no hob list yet
+ call ASM_PFX(CallPeiCoreEntryPoint)
+
+FspApiFailed:
+ jmp $
+
+align 10h
+TempRamInitStack:
+ DD TempRamInitDone
+ DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
+
+;
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase
+;
+align 16
+global ASM_PFX(BootGdtTable)
+
+;
+; GDT[0]: 0x00: Null entry, never used.
+;
+NULL_SEL EQU $ - GDT_BASE ; Selector [0]
+GDT_BASE:
+ASM_PFX(BootGdtTable):
+ DD 0
+ DD 0
+;
+; Linear data segment descriptor
+;
+LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 092h ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Linear code segment descriptor
+;
+LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; System data segment descriptor
+;
+SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+
+;
+; System code segment descriptor
+;
+SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Ah ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0Eh ; Changed from F000 to E000.
+ DB 09Bh ; present, ring 0, code, expand-up, writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
+ DW 0FFFFh ; limit 0xFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+
+;
+; Spare segment descriptor
+;
+SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
+ DW 0 ; limit 0
+ DW 0 ; base 0
+ DB 0
+ DB 0 ; present, ring 0, data, expand-up, writable
+ DB 0 ; page-granular, 32-bit
+ DB 0
+GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
+
+;
+; GDT Descriptor
+;
+GdtDesc: ; GDT descriptor
+ DW GDT_SIZE - 1 ; GDT limit
+ DD GDT_BASE ; GDT base address
+
+
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+ DD ProtectedModeEntryPoint ; Offset of our 32 bit code
+ DW LINEAR_CODE_SEL
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Stack.nasm
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Stack.nasm
new file mode 100644
index 0000000000..80a7a67ecf
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
Ia32/Stack.nasm
@@ -0,0 +1,71 @@
+;------------------------------------------------------------------------------
+; @file Stack.nasm
+; Switch the stack from temporary memory to permenent memory.
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SecSwitchStack (
+; UINT32 TemporaryMemoryBase,
+; UINT32 PermanentMemoryBase
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
+ ;
+ ; Save three register: eax, ebx, ecx
+ ;
+ push eax
+ push ebx
+ push ecx
+ push edx
+
+ ;
+ ; !!CAUTION!! this function address's is pushed into stack after
+ ; migration of whole temporary memory, so need save it to permanent
+ ; memory at first!
+ ;
+
+ mov ebx, [esp + 20] ; Save the first parameter
+ mov ecx, [esp + 24] ; Save the second parameter
+
+ ;
+ ; Save this function's return address into permanent memory at first.
+ ; Then, Fixup the esp point to permanent memory
+ ;
+ mov eax, esp
+ sub eax, ebx
+ add eax, ecx
+ mov edx, dword [esp] ; copy pushed register's value to permanent
memory
+ mov dword [eax], edx
+ mov edx, dword [esp + 4]
+ mov dword [eax + 4], edx
+ mov edx, dword [esp + 8]
+ mov dword [eax + 8], edx
+ mov edx, dword [esp + 12]
+ mov dword [eax + 12], edx
+ mov edx, dword [esp + 16] ; Update this function's return address into
permanent memory
+ mov dword [eax + 16], edx
+ mov esp, eax ; From now, esp is pointed to permanent memory
+
+ ;
+ ; Fixup the ebp point to permanent memory
+ ;
+ mov eax, ebp
+ sub eax, ebx
+ add eax, ecx
+ mov ebp, eax ; From now, ebp is pointed to permanent memory
+
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ ret
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
PlatformInit.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
PlatformInit.c
new file mode 100644
index 0000000000..546b13f8a3
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
PlatformInit.c
@@ -0,0 +1,48 @@
+/** @file
+ Sample to provide platform init function.
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/SecBoardInitLib.h>
+#include <Library/TestPointCheckLib.h>
+
+/**
+ Platform initialization.
+
+ @param[in] FspHobList HobList produced by FSP.
+ @param[in] StartOfRange Start of temporary RAM.
+ @param[in] EndOfRange End of temporary RAM.
+**/
+VOID
+EFIAPI
+PlatformInit (
+ IN VOID *FspHobList,
+ IN VOID *StartOfRange,
+ IN VOID *EndOfRange
+ )
+{
+ //
+ // Platform initialization
+ // Enable Serial port here
+ //
+ if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
+ SerialPortInitialize ();
+ }
+
+ DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
+ DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
+ DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
+ DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
+
+ BoardAfterTempRamInit ();
+
+ TestPointTempMemoryFunction (StartOfRange, EndOfRange);
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecFspWrapperPlatformSecLib.inf
new file mode 100644
index 0000000000..37e0a5cb63
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecFspWrapperPlatformSecLib.inf
@@ -0,0 +1,103 @@
+## @file
+# Provide FSP wrapper platform sec related function.
+#
+# @copyright
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################
################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################
################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SecFspWrapperPlatformSecLib
+ FILE_GUID = 8F1AC44A-CE7E-4E29-95BB-92E321BB1573
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecLib
+
+
+#
+# The following information is for reference only and not required by the build
tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+################################################################
################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################
################
+
+[Sources]
+ FspWrapperPlatformSecLib.c
+ SecRamInitData.c
+ SecPlatformInformation.c
+ SecGetPerformance.c
+ SecTempRamDone.c
+ PlatformInit.c
+
+[Sources.IA32]
+ Ia32/SecEntry.nasm
+ Ia32/PeiCoreEntry.nasm
+ Ia32/Stack.nasm
+ Ia32/Fsp.h
+
+################################################################
################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################
################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhitleyFspBinPkg/WhitleyFspBinPkg.dec
+
+[LibraryClasses]
+ LocalApicLib
+ SerialPortLib
+ DebugLib
+ BaseMemoryLib
+ FspWrapperPlatformLib
+ FspWrapperApiLib
+ SecBoardInitLib
+ TestPointCheckLib
+ PeiServicesTablePointerLib
+
+[Ppis]
+ gEfiSecPlatformInformationPpiGuid ## CONSUMES
+ gPeiSecPerformancePpiGuid ## CONSUMES
+ gTopOfTemporaryRamPpiGuid ## PRODUCES
+ gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
+ gPlatformInitTempRamExitPpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ##
CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
CONSUMES
+
+[FixedPcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ##
CONSUMES
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase ##
CONSUMES
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize ##
CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ##
CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ##
CONSUMES
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecGetPerformance.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecGetPerformance.c
new file mode 100644
index 0000000000..977212737e
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecGetPerformance.c
@@ -0,0 +1,90 @@
+/** @file
+ Sample to provide SecGetPerformance function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPerformance.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys performance information out of the Security (SEC)
phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an
optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data
in SEC,
+ this information is encapsulated into the data structure abstracted by this
service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the
PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC
phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ )
+{
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ UINT64 Ticker;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // |--------------| <- TopOfTemporaryRam - BL
+ // | List Ptr |
+ // |--------------|
+ // | BL RAM Start |
+ // |--------------|
+ // | BL RAM End |
+ // |--------------|
+ // |Number of BSPs|
+ // |--------------|
+ // | BIST |
+ // |--------------|
+ // | .... |
+ // |--------------|
+ // | TSC[63:32] |
+ // |--------------|
+ // | TSC[31:00] |
+ // |--------------|
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));
+ Size = Count * sizeof (UINT32);
+
+ Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof
(UINT32) * 2);
+ Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecPlatformInformation.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecPlatformInformation.c
new file mode 100644
index 0000000000..3d1b9be21c
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecPlatformInformation.c
@@ -0,0 +1,79 @@
+/** @file
+ Sample to provide SecPlatformInformation function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into
PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of
the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the
EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
*PlatformInformationRecord
+ )
+{
+ UINT32 *Bist;
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // The entries of BIST information, together with the number of them,
+ // reside in the bottom of stack, left untouched by normal stack operation.
+ // This routine copies the BIST information to the buffer pointed by
+ // PlatformInformationRecord for output.
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);
+
+ if ((*StructureSize) < (UINT64) Size) {
+ *StructureSize = Size;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ *StructureSize = Size;
+ Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
+
+ CopyMem (PlatformInformationRecord, Bist, Size);
+
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecRamInitData.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecRamInitData.c
new file mode 100644
index 0000000000..a6c7a53d33
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecRamInitData.c
@@ -0,0 +1,29 @@
+/** @file
+ Sample to provide TempRamInitParams data.
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PcdLib.h>
+#include <FspEas.h>
+#include <FsptUpd.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
+ {
+ FSPT_UPD_SIGNATURE,
+ 0x00,
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ },
+ {
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32
(PcdMicrocodeOffsetInFv),
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32
(PcdMicrocodeOffsetInFv),
+ FixedPcdGet32 (PcdFlashSecCacheRegionBase),
+ FixedPcdGet32 (PcdFlashSecCacheRegionSize),
+ }
+};
+
diff --git
a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecTempRamDone.c
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecTempRamDone.c
new file mode 100644
index 0000000000..e6f2c1c4d6
--- /dev/null
+++
b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/
SecTempRamDone.c
@@ -0,0 +1,130 @@
+/** @file
+ Sample to provide SecTemporaryRamDone function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/PlatformInitTempRamExitPpi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/FspWrapperPlatformLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+#include <Guid/FspHeaderFile.h>
+
+#include <Register/ArchitecturalMsr.h>
+
+#define MSR_NEM 0x000002E0
+
+/**
+This interface disables temporary memory in SEC Phase.
+This is for dispatch mode use. We should properly produce the
FSP_TEMP_RAM_EXIT_PPI and then call
+that instead, but the FSP does not produce that PPI
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemoryDispatchHack (
+ VOID
+ )
+{
+ UINT64 MsrValue;
+ UINT64 MtrrDefaultType;
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+
+ //
+ // Force and INVD.
+ //
+ AsmInvd ();
+
+ //
+ // Disable MTRRs.
+ //
+ DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
+ MtrrDefaultType = DefType.Uint64;
+ DefType.Bits.E = 0;
+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
+
+ //
+ // Force and INVD to prevent MCA error.
+ //
+ AsmInvd ();
+
+ //
+ // Clear NEM Run and NEM Setup bits individually.
+ //
+ MsrValue = AsmReadMsr64 (MSR_NEM);
+ MsrValue &= ~((UINT64) BIT1);
+ AsmWriteMsr64 (MSR_NEM, MsrValue);
+ MsrValue &= ~((UINT64) BIT0);
+ AsmWriteMsr64 (MSR_NEM, MsrValue);
+
+ //
+ // Restore MTRR default setting
+ //
+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrDefaultType);
+}
+
+/**
+This interface disables temporary memory in SEC Phase.
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *TempRamExitParam;
+ CONST EFI_PEI_SERVICES **PeiServices;
+ PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
+ PeiServices = GetPeiServicesTablePointer ();
+ ASSERT (PeiServices != NULL);
+ if (PeiServices == NULL) {
+ return ;
+ }
+ ASSERT ((*PeiServices) != NULL);
+ if ((*PeiServices) == NULL) {
+ return;
+ }
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPlatformInitTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PlatformInitTempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
+ ASSERT_EFI_ERROR (Status);
+
+ if (PcdGet8 (PcdFspModeSelection) == 1) {
+ //
+ // FSP API mode
+ //
+ TempRamExitParam = UpdateTempRamExitParam ();
+ Status = CallTempRamExit (TempRamExitParam);
+ DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ SecPlatformDisableTemporaryMemoryDispatchHack ();
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
+ ASSERT_EFI_ERROR(Status);
+
+ return ;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index fa41ae923d..dc3dd0e026 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -48,6 +48,9 @@
#
!include $(SILICON_PKG)/MrcCommonConfig.dsc

+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
!include $(FSP_BIN_PKG)/DynamicExPcd.dsc
!include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
!include $(RP_PKG)/DynamicExPcd.dsc
@@ -192,8 +195,17 @@
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000

+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
!endif
gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000

@@ -310,6 +322,12 @@
!include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc

[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
!if ($(FSP_MODE) == 0)
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
@@ -543,12 +561,11 @@
VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf

[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE,
LibraryClasses.Common.PEIM]
-!if ($(FSP_MODE) == 0)

FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs
pWrapperApiLib.inf

FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/
PeiFspWrapperApiTestLib.inf

FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fsp
WrapperPlatformLib.inf

FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobPr
ocessLib/PeiFspWrapperHobProcessLib.inf
-!endif
+

FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchS
tackLib.inf

FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.i
nf

FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.in
f
@@ -559,6 +576,11 @@
#

TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat
e.inf

+
PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapp
erPlatformSecLib.inf
+
SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecB
oardInitLibNull.inf
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPoi
ntCheckLib.inf
+
VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariabl
eReadLibNull.inf
+
[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
#
# ToDo: Can we remove
@@ -617,6 +639,8 @@

DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
!include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc

MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
@@ -653,8 +677,8 @@

BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInit
LibNull.inf
}

-!if ($(FSP_MODE) == 0)
IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
$(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
!endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
index 927db9e210..d128f61b9d 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
@@ -14,7 +14,7 @@ DEFINE PLATFORM_PKG = MinPlatformPkg
# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof
(EFI_FFS_FILE_HEADER))
DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060

-DEFINE MICROCODE_HEADER_SIZE = 0x00000090
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90
# FV Header plus FFS header

DEFINE VPD_HEADER_SIZE = 0x00000090

@@ -153,24 +153,12 @@ SET
gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize

- #
- # For FSP Dispatch Mode, specify the FV containing the PEI core.
- #
- !if $(FSP_MODE) == 1
- #
- # Tell SEC to use PEI Core from outside FSP for additional debug message
control.
- #
- SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
- !endif
-
#
# For API mode, wrappers have some duplicate PCD as well
#
- !if $(FSP_MODE) == 0
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
- !endif
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase


#################################################################
###############
#
@@ -311,7 +299,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
= 0x01000000
#
# Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
dynamically
#
- SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
$(MICROCODE_HEADER_SIZE)
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase +
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset +
gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize -
gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv

#
# FV Layout (You should not need to modify this section)
@@ -410,12 +399,7 @@ SET
gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
!include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864

- FILE SEC = 1BA0062E-C779-4582-8566-336AE8F78F09 {
- SECTION UI = "SecCore"
- SECTION VERSION = "1.0"
- SECTION Align = 16 PE32 =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/1BA0062E-C779-4582-8566-
336AE8F78F09SecCore.efi
- SECTION Align = 16 RAW =
$(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ResetVec.bin
- }
+ INF UefiCpuPkg/SecCore/SecCore.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf

INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index d7039f65c4..ea8fd0a49b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -905,8 +905,6 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e,
0x4f43, {0x8d, 0xef, 0xa7, 0x43,
gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported
|FALSE|BOOLEAN|0xF0000030
gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault
|FALSE|BOOLEAN|0xF0000031

- gSiPkgTokenSpaceGuid.PcdPeiCoreFv
|0x00000000|UINT32|0xF0000032
-
gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033

#
--
2.27.0.windows.1


Re: [edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables

Chiu, Chasel
 

Reviewed-by: Chasel Chiu <chasel.chiu@...>

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Thursday, September 16, 2021 3:05 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel
<chasel.chiu@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2]
WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables

Update to utilize the larger variables.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---

Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlat
formLib.c | 83 +++++++-------------

Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlat
formLib.inf | 12 +--
2 files changed, 35 insertions(+), 60 deletions(-)

diff --git
a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.c
b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.c
index 453e409523..a6196a78b0 100644
---
a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.c
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspW
+++ rapperPlatformLib.c
@@ -10,76 +10,52 @@
#include <PiPei.h>
#include <Library/PeiServicesLib.h>
#include <Library/DebugLib.h>
-#include <FspmUpd.h>
-#include <Ppi/UpiPolicyPpi.h>
-#include <Guid/PlatformInfo.h>
#include <Library/HobLib.h>
-#include <Ppi/ReadOnlyVariable2.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/LargeVariableReadLib.h>
+
+#include <FspmUpd.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/UpiPolicyPpi.h>

VOID *
-GetPlatformNvs(
+GetFspNvsBuffer (
+ VOID
)
{
EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
- VOID *DataBuffer;
- UINT32 DataBufferSize;
- UINTN VarAttrib;
- CHAR16 EfiMemoryConfigVariable[] = L"MemoryConfig";
+ UINTN FspNvsBufferSize;
+ VOID *FspNvsBufferPtr;

- DEBUG ((EFI_D_INFO, "Start PlatformGetNvs\n"));
-
- Status = PeiServicesLocatePpi (
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **) &PeiVariable
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: PeiServicesLocatePpi not
found\n"));
+ FspNvsBufferPtr = NULL;
+ FspNvsBufferSize = 0;
+ Status = GetLargeVariable (L"FspNvsBuffer",
+ &gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, NULL); if (Status ==
EFI_BUFFER_TOO_SMALL) {
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size = %d\n", FspNvsBufferSize));
+ FspNvsBufferPtr = AllocateZeroPool (FspNvsBufferSize);
+ if (FspNvsBufferPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Error: Cannot create FspNvsBuffer, out of
+ memory!\n"));
ASSERT (FALSE);
return NULL;
}
-
- VarAttrib = EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS;
- DataBufferSize = 0;
- DataBuffer = NULL;
-
- Status = PeiVariable->GetVariable (
- PeiVariable,
- EfiMemoryConfigVariable,
- &gFspNonVolatileStorageHobGuid,
- (UINT32*)&VarAttrib,
- &DataBufferSize,
- NULL
- );
- if (Status == EFI_NOT_FOUND) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid
Variable not found\n"));
+ Status = GetLargeVariable (L"FspNvsBuffer",
&gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, FspNvsBufferPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable
Status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
return NULL;
}

- if (Status != EFI_BUFFER_TOO_SMALL) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Get
Error %r\n", Status));
- ASSERT (FALSE);
+ return FspNvsBufferPtr;
+
+ } else if (Status == EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable
+ does not exist (this is likely a first boot)\n")); } else {
+ DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable
Status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
}

- DataBuffer = AllocateZeroPool(DataBufferSize);
- Status = PeiVariable->GetVariable (
- PeiVariable,
- EfiMemoryConfigVariable,
- &gFspNonVolatileStorageHobGuid,
- (UINT32*)&VarAttrib,
- &DataBufferSize,
- DataBuffer
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid
Variable Error %r\n", Status));
return NULL;
}
- DEBUG ((EFI_D_INFO, "PlatformGetNvs: GetNVS %x %x\n", DataBuffer,
DataBufferSize));
- return DataBuffer;
-}

VOID
EFIAPI
@@ -164,11 +140,10 @@ UpdateFspmUpdData (
FspmUpd->FspmConfig.AllLanesSizeOfTable = Upi->AllLanesSizeOfTable;
FspmUpd->FspmConfig.PerLaneSizeOfTable = Upi->PerLaneSizeOfTable;
FspmUpd->FspmConfig.WaitTimeForPSBP = Upi->WaitTimeForPSBP;
- FspmUpd->FspmConfig.IsKtiNvramDataReady = Upi->IsKtiNvramDataReady;
FspmUpd->FspmConfig.WaSerializationEn = Upi->WaSerializationEn;
FspmUpd->FspmConfig.KtiInEnableMktme = Upi->KtiInEnableMktme;
FspmUpd->FspmConfig.BoardId = PlatformInfo->BoardId;
- FspmUpd->FspmArchUpd.NvsBufferPtr = GetPlatformNvs();
+ FspmUpd->FspmArchUpd.NvsBufferPtr = GetFspNvsBuffer ();
}

/**
diff --git
a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.inf
b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.inf
index 625337c453..3e80ea670c 100644
---
a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl
atformLib.inf
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspW
+++ rapperPlatformLib.inf
@@ -35,7 +35,6 @@
[Sources]
FspWrapperPlatformLib.c

-

#################################################################
###############
#
# Package Dependency Section - list of Package files that are required for @@ -
47,11 +46,11 @@
MdePkg/MdePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- WhitleySiliconPkg/WhitleySiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
WhitleySiliconPkg/SiliconPkg.dec
WhitleySiliconPkg/CpRcPkg.dec
- WhitleyOpenBoardPkg/PlatformPkg.dec
- CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec # For LargeVariableReadLib
+ WhitleyFspBinPkg/WhitleyFspBinPkg.dec

[Ppis]
gUpiSiPolicyPpiGuid
@@ -63,9 +62,10 @@

[LibraryClasses]
PeiServicesLib
+ LargeVariableReadLib

[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ##
CONSUMES
--
2.27.0.windows.1


Re: [edk2-platforms][PATCH V1 0/2] Whitley SEC support

Oram, Isaac W
 

Series pushed as 38b2e75e94f5fe234ccaf80dc3b33b34a68486cf..64394fd2b48f403330feb8f7e954d1cca0822af5

-----Original Message-----
From: Desimone, Nathaniel L <nathaniel.l.desimone@...>
Sent: Thursday, September 16, 2021 2:25 PM
To: Oram, Isaac W <isaac.w.oram@...>; devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>
Subject: RE: [edk2-devel][edk2-platforms][PATCH V1 0/2] Whitley SEC support

For the series...

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Wednesday, September 15, 2021 12:05 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel <chasel.chiu@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 0/2] Whitley SEC support

This series replaces the binary version of the SEC component with a buildable version.
The missing PlatformSecLib instance is implemented allowing the common SecCore component to be built. The resulting SecCore supports both Whitley and CedarIsland platforms in both API and Dispatch FSP modes though the WhitleyOpenBoardPkg does not currently support Whitley FSP API mode.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>

Isaac Oram (2):
WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables
WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c | 159 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm | 124 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm | 338 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm | 71 ++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 103 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c | 90 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 29 ++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c | 130 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 30 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 30 +-
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c | 83 ++---
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf | 12 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 2 -
16 files changed, 1283 insertions(+), 88 deletions(-) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c

--
2.27.0.windows.1


Re: [edk2-platforms][PATCH V1 0/2] Whitley SEC support

Nate DeSimone
 

For the series...

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Wednesday, September 15, 2021 12:05 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel <chasel.chiu@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 0/2] Whitley SEC support

This series replaces the binary version of the SEC component with a buildable version.
The missing PlatformSecLib instance is implemented allowing the common SecCore component to be built. The resulting SecCore supports both Whitley and CedarIsland platforms in both API and Dispatch FSP modes though the WhitleyOpenBoardPkg does not currently support Whitley FSP API mode.

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>

Isaac Oram (2):
WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables
WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c | 159 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm | 124 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm | 338 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm | 71 ++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 103 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c | 90 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 29 ++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c | 130 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 30 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 30 +-
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c | 83 ++---
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf | 12 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 2 -
16 files changed, 1283 insertions(+), 88 deletions(-) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c

--
2.27.0.windows.1


[RFC PATCH 3/3] ArmVirtPkg: Disable the TPM2 platform hierarchy

Stefan Berger
 

From: Stefan Berger <stefanb@...>

Disable the TPM2 platform hierarchy by directly calling
ConfigureTpmPlatformHierarchy().

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Leif Lindholm <leif@...>
Cc: Sami Mujawar <sami.mujawar@...>
Cc: Gerd Hoffmann <kraxel@...>
Signed-off-by: Stefan Berger <stefanb@...>
---
ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c | 6 ++++++
.../PlatformBootManagerLib/PlatformBootManagerLib.inf | 1 +
2 files changed, 7 insertions(+)

diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmVi=
rtPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 69448ff65b..1848042f86 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -16,6 +16,7 @@
#include <Library/PcdLib.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/QemuBootOrderLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>=0D
#include <Library/UefiBootManagerLib.h>=0D
#include <Protocol/DevicePath.h>=0D
#include <Protocol/FirmwareVolume2.h>=0D
@@ -696,6 +697,11 @@ PlatformBootManagerBeforeConsole (
//=0D
EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierarchy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();=0D
+=0D
//=0D
// Dispatch deferred images after EndOfDxe event.=0D
//=0D
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerL=
ib.inf b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.i=
nf
index 9f54224d3e..997eb1a442 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -48,6 +48,7 @@
QemuBootOrderLib=0D
QemuLoadImageLib=0D
ReportStatusCodeLib=0D
+ TpmPlatformHierarchyLib=0D
UefiBootManagerLib=0D
UefiBootServicesTableLib=0D
UefiLib=0D
--=20
2.31.1


[RFC PATCH 1/3] ArmVirtPkg/TPM: Add a NULL implementation of TpmPlatformHierarchyLib

Stefan Berger
 

From: Stefan Berger <stefanb@...>

Add a NULL implementation of the library class TpmPlatformHierarchyLib.

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Leif Lindholm <leif@...>
Cc: Sami Mujawar <sami.mujawar@...>
Cc: Gerd Hoffmann <kraxel@...>
Signed-off-by: Stefan Berger <stefanb@...>
---
ArmVirtPkg/ArmVirtPkg.dec | 1 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 +++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.c | 22 ++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 30 +++++++++++++++++++
4 files changed, 80 insertions(+)
create mode 100644 ArmVirtPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/Pe=
iDxeTpmPlatformHierarchyLib.c
create mode 100644 ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/Pe=
iDxeTpmPlatformHierarchyLib.inf

diff --git a/ArmVirtPkg/ArmVirtPkg.dec b/ArmVirtPkg/ArmVirtPkg.dec
index 4e4d758015..f3bdca118b 100644
--- a/ArmVirtPkg/ArmVirtPkg.dec
+++ b/ArmVirtPkg/ArmVirtPkg.dec
@@ -27,6 +27,7 @@
=0D
[LibraryClasses]=0D
ArmVirtMemInfoLib|Include/Library/ArmVirtMemInfoLib.h=0D
+ TpmPlatformHierarchyLib|Include/Library/TpmPlatformHierarchyLib.h=0D
=0D
[Guids.common]=0D
gArmVirtTokenSpaceGuid =3D { 0x0B6F5CA7, 0x4F53, 0x445A, { 0xB7, 0x6E, 0=
x2E, 0x36, 0x5B, 0x80, 0x63, 0x66 } }=0D
diff --git a/ArmVirtPkg/Include/Library/TpmPlatformHierarchyLib.h b/ArmVirt=
Pkg/Include/Library/TpmPlatformHierarchyLib.h
new file mode 100644
index 0000000000..8d61a4867b
--- /dev/null
+++ b/ArmVirtPkg/Include/Library/TpmPlatformHierarchyLib.h
@@ -0,0 +1,27 @@
+/** @file=0D
+ TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+ Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+ Policy (platformPolicy) can be defined through this function.=0D
+=0D
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) Microsoft Corporation.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+#define TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+=0D
+/**=0D
+ This service will perform the TPM Platform Hierarchy configuration at t=
he SmmReadyToLock event.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ VOID=0D
+ );=0D
+=0D
+#endif=0D
diff --git a/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpm=
PlatformHierarchyLib.c b/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNu=
ll/PeiDxeTpmPlatformHierarchyLib.c
new file mode 100644
index 0000000000..bac1efda63
--- /dev/null
+++ b/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatfor=
mHierarchyLib.c
@@ -0,0 +1,22 @@
+/** @file=0D
+ Null TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides stub functions for customizing the TPM's Platfor=
m Hierarchy.=0D
+=0D
+ Copyright (c) 2021, IBM Corporation.=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+/**=0D
+ A NULL implementation of ConfigureTpmPlatformHierarchy.=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ )=0D
+{=0D
+ /* no nothing */=0D
+}=0D
diff --git a/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpm=
PlatformHierarchyLib.inf b/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLib=
Null/PeiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 0000000000..4f02818bbc
--- /dev/null
+++ b/ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatfor=
mHierarchyLib.inf
@@ -0,0 +1,30 @@
+### @file=0D
+# NULL TPM Platform Hierarchy configuration library.=0D
+#=0D
+# This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+# Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+# Policy (platformPolicy) can be defined through this function.=0D
+#=0D
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) Microsoft Corporation.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+###=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PeiDxeTpmPlatformHierarchyLibNull=0D
+ FILE_GUID =3D 8947A3F2-BfB4-45EF-968D-5C40C1CE6A58=
=0D
+ MODULE_TYPE =3D PEIM=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D TpmPlatformHierarchyLib|PEIM DXE_DRIV=
ER=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+=0D
+[Sources]=0D
+ PeiDxeTpmPlatformHierarchyLib.c=0D
--=20
2.31.1


[RFC PATCH 2/3] ArmVirtPkg: Reference new TPM classes in the build system for compilation

Stefan Berger
 

From: Stefan Berger <stefanb@...>

Cc: Ard Biesheuvel <ardb+tianocore@...>
Cc: Leif Lindholm <leif@...>
Cc: Sami Mujawar <sami.mujawar@...>
Cc: Gerd Hoffmann <kraxel@...>
Signed-off-by: Stefan Berger <stefanb@...>
---
ArmVirtPkg/ArmVirtCloudHv.dsc | 1 +
ArmVirtPkg/ArmVirtQemu.dsc | 2 ++
ArmVirtPkg/ArmVirtQemuKernel.dsc | 1 +
ArmVirtPkg/ArmVirtXen.dsc | 1 +
.../Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 1 +
5 files changed, 6 insertions(+)

diff --git a/ArmVirtPkg/ArmVirtCloudHv.dsc b/ArmVirtPkg/ArmVirtCloudHv.dsc
index f292ba6079..45bf8562e7 100644
--- a/ArmVirtPkg/ArmVirtCloudHv.dsc
+++ b/ArmVirtPkg/ArmVirtCloudHv.dsc
@@ -55,6 +55,7 @@
PciHostBridgeUtilityLib|ArmVirtPkg/Library/ArmVirtPciHostBridgeUtilityLi=
b/ArmVirtPciHostBridgeUtilityLib.inf=0D
=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLib=
Null/PeiDxeTpmPlatformHierarchyLib.inf=0D
=0D
!include MdePkg/MdeLibs.dsc.inc=0D
=0D
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 97539edef7..bbe60b1bad 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -86,8 +86,10 @@
Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLib=
Null/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common.PEIM]=0D
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKerne=
l.dsc
index 28064199c8..d537d9f194 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -80,6 +80,7 @@
PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridge=
Lib.inf=0D
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostB=
ridgeUtilityLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLib=
Null/PeiDxeTpmPlatformHierarchyLib.inf=0D
=0D
[LibraryClasses.common.DXE_DRIVER]=0D
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor=
tStatusCodeLib.inf=0D
diff --git a/ArmVirtPkg/ArmVirtXen.dsc b/ArmVirtPkg/ArmVirtXen.dsc
index 2b07a5ba19..81289e6838 100644
--- a/ArmVirtPkg/ArmVirtXen.dsc
+++ b/ArmVirtPkg/ArmVirtXen.dsc
@@ -50,6 +50,7 @@
PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo=
tManagerLib.inf=0D
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize=
dDisplayLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLib=
Null/PeiDxeTpmPlatformHierarchyLib.inf=0D
=0D
[LibraryClasses.common.UEFI_DRIVER]=0D
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf=0D
diff --git a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerL=
ib.inf b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.i=
nf
index 11f52e019b..9f54224d3e 100644
--- a/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -33,6 +33,7 @@
MdeModulePkg/MdeModulePkg.dec=0D
MdePkg/MdePkg.dec=0D
OvmfPkg/OvmfPkg.dec=0D
+ SecurityPkg/SecurityPkg.dec=0D
ShellPkg/ShellPkg.dec=0D
=0D
[LibraryClasses]=0D
--=20
2.31.1


[RFC PATCH 0/3] ArmVirtPkg: Disable the TPM 2 platform hierarchy

Stefan Berger
 

This series of patches disables the TPM 2 platform hierarchy.
We just added the same functionality to the OvmfPkg. However, on x86, we
could use the notification mechanism around gEfiDxeSmmReadyToLockProtocolGuid
to indirectly invoke ConfigureTpmPlatformHierarchy(). Since ARM does not
have an SMM mode this series now use direct invocation of this function
at the same place in PlatformBootManagerBeforeConsole() as it is done
on x86.

Regards,
Stefan

Stefan Berger (3):
ArmVirtPkg/TPM: Add a NULL implementation of TpmPlatformHierarchyLib
ArmVirtPkg: Reference new TPM classes in the build system for
compilation
ArmVirtPkg: Disable the TPM2 platform hierarchy

ArmVirtPkg/ArmVirtCloudHv.dsc | 1 +
ArmVirtPkg/ArmVirtPkg.dec | 1 +
ArmVirtPkg/ArmVirtQemu.dsc | 2 ++
ArmVirtPkg/ArmVirtQemuKernel.dsc | 1 +
ArmVirtPkg/ArmVirtXen.dsc | 1 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 +++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.c | 22 ++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 30 +++++++++++++++++++
.../PlatformBootManagerLib/PlatformBm.c | 6 ++++
.../PlatformBootManagerLib.inf | 2 ++
10 files changed, 93 insertions(+)
create mode 100644 ArmVirtPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 ArmVirtPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

--
2.31.1


Re: [edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Build: Reduce debug output for default boot.

Nate DeSimone
 

Is it a big increase in messages to have both INFO and LOAD?

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Wednesday, September 8, 2021 3:35 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel <chasel.chiu@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Build: Reduce debug output for default boot.

Replace Info with Load, so we still get component loading details

Cc: Isaac Oram <isaac.w.oram@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index fa41ae923d..64ba4a4dae 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -365,7 +365,7 @@
#

gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000006 # Displayed messages: Error, Load, Warn

gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
--
2.27.0.windows.1


Re: [edk2-platforms][PATCH V1 1/1] MinPlatformPkg/Variable*Lib: Build VariableRead and VariableWrite libs

Nate DeSimone
 

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Wednesday, September 8, 2021 3:30 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>; Liming Gao <gaoliming@...>; Dong, Eric <eric.dong@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] MinPlatformPkg/Variable*Lib: Build VariableRead and VariableWrite libs

Add the VariableReadLib and VariableWriteLib instances to Components to ensure build when building MinPlatformPkg.dsc.
Add a NULL library instance that provides the non-functional library instance for VariableReadLib designed for all phase use.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Liming Gao <gaoliming@...>
Cc: Eric Dong <eric.dong@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c | 75 ++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf | 37 ++++++++++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc | 6 +-
3 files changed, 117 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c
new file mode 100644
index 0000000000..f276b7b6b4
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/Base
+++ VariableReadLibNull.c
@@ -0,0 +1,75 @@
+/** @file
+ NULL implementation of Variable Read Lib
+
+ This library provides phase agnostic access to the UEFI Variable Services.
+ This is done by implementing a wrapper on top of the phase specific
+ mechanism for reading from UEFI variables. For example, the PEI
+ implementation of this library uses EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+ The DXE implementation accesses the UEFI Runtime Services Table, and
+ the SMM implementation uses EFI_SMM_VARIABLE_PROTOCOL.
+
+ Using this library allows code to be written in a generic manner that
+ can be used in PEI, DXE, or SMM without modification.
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Uefi/UefiBaseType.h>
+
+/**
+ Returns the value of a variable.
+
+ @param[in] VariableName A Null-terminated string that is the name of the vendor's
+ variable.
+ @param[in] VendorGuid A unique identifier for the vendor.
+ @param[out] Attributes If not NULL, a pointer to the memory location to return the
+ attributes bitmask for the variable.
+ @param[in, out] DataSize On input, the size in bytes of the return Data buffer.
+ On output the size of data returned in Data.
+ @param[out] Data The buffer to return the contents of the variable. May be NULL
+ with a zero DataSize in order to determine the size buffer needed.
+
+ @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
+
+**/
+EFI_STATUS
+EFIAPI
+VarLibGetVariable (
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ OUT UINT32 *Attributes, OPTIONAL
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Enumerates the current variable names.
+
+ @param[in, out] VariableNameSize The size of the VariableName buffer. The size must be large
+ enough to fit input string supplied in VariableName buffer.
+ @param[in, out] VariableName On input, supplies the last VariableName that was returned
+ by GetNextVariableName(). On output, returns the Nullterminated
+ string of the current variable.
+ @param[in, out] VendorGuid On input, supplies the last VendorGuid that was returned by
+ GetNextVariableName(). On output, returns the
+ VendorGuid of the current variable.
+
+ @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
+
+**/
+EFI_STATUS
+EFIAPI
+VarLibGetNextVariableName (
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VendorGuid
+ )
+{
+ return EFI_UNSUPPORTED;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
new file mode 100644
index 0000000000..3a397998a9
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/Base
+++ VariableReadLibNull.inf
@@ -0,0 +1,37 @@
+## @file
+# Component description file for NULL implementation of Variable Read
+Lib # # This library provides phase agnostic access to the UEFI
+Variable Services.
+# This is done by implementing a wrapper on top of the phase specific
+mechanism # for reading from UEFI variables. For example, the PEI
+implementation of this # library uses EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+The DXE implementation accesses # the UEFI Runtime Services Table, and
+the SMM implementation uses # EFI_SMM_VARIABLE_PROTOCOL.
+#
+# Using this library allows code to be written in a generic manner that
+can be # used in PEI, DXE, or SMM without modification.
+#
+# @copyright
+# Copyright 2021 Intel Corporation. <BR> # # SPDX-License-Identifier:
+BSD-2-Clause-Patent ##
+
+##
+## NOTICE: This library is also available in MinPlatformPkg. This copy was added
+## for the convience of those that are using an older MinPlatformPkg.
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseVariableReadLibNull
+ FILE_GUID = 5C9E2489-329F-4D2A-90F1-F5CB2A88A3E6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = VariableReadLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[Sources]
+ BaseVariableReadLibNull.c
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
index 07b776cecd..a09f8db3ab 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
@@ -74,7 +74,7 @@
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
FspWrapperHobProcessLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
PlatformSecLib|MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
-
+
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVar
+ iableReadLibNull.inf
FspWrapperPlatformLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf

BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
@@ -214,5 +214,9 @@
MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf

+
+ MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull
+ .inf
+ MinPlatformPkg/Library/SmmVariableReadLib/StandaloneMmVariableReadLib.
+ inf
+ MinPlatformPkg/Library/SmmVariableWriteLib/StandaloneMmVariableWriteLi
+ b.inf
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
--
2.27.0.windows.1


Re: [edk2-platforms][PATCH V1 1/1] MinPlatformPkg/Variable*Lib: Build VariableRead and VariableWrite libs

Nate DeSimone
 

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Oram, Isaac W
Sent: Wednesday, September 8, 2021 3:30 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>; Liming Gao <gaoliming@...>; Dong, Eric <eric.dong@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] MinPlatformPkg/Variable*Lib: Build VariableRead and VariableWrite libs

Add the VariableReadLib and VariableWriteLib instances to Components to ensure build when building MinPlatformPkg.dsc.
Add a NULL library instance that provides the non-functional library instance for VariableReadLib designed for all phase use.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Liming Gao <gaoliming@...>
Cc: Eric Dong <eric.dong@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c | 75 ++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf | 37 ++++++++++
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc | 6 +-
3 files changed, 117 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.c
new file mode 100644
index 0000000000..f276b7b6b4
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/Base
+++ VariableReadLibNull.c
@@ -0,0 +1,75 @@
+/** @file
+ NULL implementation of Variable Read Lib
+
+ This library provides phase agnostic access to the UEFI Variable Services.
+ This is done by implementing a wrapper on top of the phase specific
+ mechanism for reading from UEFI variables. For example, the PEI
+ implementation of this library uses EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+ The DXE implementation accesses the UEFI Runtime Services Table, and
+ the SMM implementation uses EFI_SMM_VARIABLE_PROTOCOL.
+
+ Using this library allows code to be written in a generic manner that
+ can be used in PEI, DXE, or SMM without modification.
+
+ @copyright
+ Copyright 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Uefi/UefiBaseType.h>
+
+/**
+ Returns the value of a variable.
+
+ @param[in] VariableName A Null-terminated string that is the name of the vendor's
+ variable.
+ @param[in] VendorGuid A unique identifier for the vendor.
+ @param[out] Attributes If not NULL, a pointer to the memory location to return the
+ attributes bitmask for the variable.
+ @param[in, out] DataSize On input, the size in bytes of the return Data buffer.
+ On output the size of data returned in Data.
+ @param[out] Data The buffer to return the contents of the variable. May be NULL
+ with a zero DataSize in order to determine the size buffer needed.
+
+ @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
+
+**/
+EFI_STATUS
+EFIAPI
+VarLibGetVariable (
+ IN CHAR16 *VariableName,
+ IN EFI_GUID *VendorGuid,
+ OUT UINT32 *Attributes, OPTIONAL
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Enumerates the current variable names.
+
+ @param[in, out] VariableNameSize The size of the VariableName buffer. The size must be large
+ enough to fit input string supplied in VariableName buffer.
+ @param[in, out] VariableName On input, supplies the last VariableName that was returned
+ by GetNextVariableName(). On output, returns the Nullterminated
+ string of the current variable.
+ @param[in, out] VendorGuid On input, supplies the last VendorGuid that was returned by
+ GetNextVariableName(). On output, returns the
+ VendorGuid of the current variable.
+
+ @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
+
+**/
+EFI_STATUS
+EFIAPI
+VarLibGetNextVariableName (
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VendorGuid
+ )
+{
+ return EFI_UNSUPPORTED;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
new file mode 100644
index 0000000000..3a397998a9
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/BaseVariableReadLibNull/Base
+++ VariableReadLibNull.inf
@@ -0,0 +1,37 @@
+## @file
+# Component description file for NULL implementation of Variable Read
+Lib # # This library provides phase agnostic access to the UEFI
+Variable Services.
+# This is done by implementing a wrapper on top of the phase specific
+mechanism # for reading from UEFI variables. For example, the PEI
+implementation of this # library uses EFI_PEI_READ_ONLY_VARIABLE2_PPI.
+The DXE implementation accesses # the UEFI Runtime Services Table, and
+the SMM implementation uses # EFI_SMM_VARIABLE_PROTOCOL.
+#
+# Using this library allows code to be written in a generic manner that
+can be # used in PEI, DXE, or SMM without modification.
+#
+# @copyright
+# Copyright 2021 Intel Corporation. <BR> # # SPDX-License-Identifier:
+BSD-2-Clause-Patent ##
+
+##
+## NOTICE: This library is also available in MinPlatformPkg. This copy was added
+## for the convience of those that are using an older MinPlatformPkg.
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseVariableReadLibNull
+ FILE_GUID = 5C9E2489-329F-4D2A-90F1-F5CB2A88A3E6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = VariableReadLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[Sources]
+ BaseVariableReadLibNull.c
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
index 07b776cecd..a09f8db3ab 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
@@ -74,7 +74,7 @@
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
FspWrapperHobProcessLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
PlatformSecLib|MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
-
+
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVar
+ iableReadLibNull.inf
FspWrapperPlatformLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf

BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
@@ -214,5 +214,9 @@
MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf

+
+ MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull
+ .inf
+ MinPlatformPkg/Library/SmmVariableReadLib/StandaloneMmVariableReadLib.
+ inf
+ MinPlatformPkg/Library/SmmVariableWriteLib/StandaloneMmVariableWriteLi
+ b.inf
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
--
2.27.0.windows.1


Re: [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

Bassa, Damian <damian.bassa@...>
 

I was looking for anything that wouldn’t include reading register but only thing that distinguish device PCI_IO_DEVICE instances with root bridge instances is population of BusNumberRanges structure.

This technically could be used since this is populated only for root bridges and not devices but using this would be just confusing since there is no self-explanatory field there.

For my knowledge this is best way to tackle this issue. Please let me know if there are have some other worth exploring ideas.

 

Damian

 

From: Ni, Ray <ray.ni@...>
Sent: Wednesday, September 15, 2021 3:21 PM
To: Bassa, Damian <damian.bassa@...>; Wu, Hao A <hao.a.wu@...>; devel@edk2.groups.io
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

Extending PciBus to support such case is valid.

 

But can you check if there is other pure software way to detect whether it’s an ECiEP?

 

From: Bassa, Damian <damian.bassa@...>
Sent: Wednesday, September 15, 2021 7:54 PM
To: Wu, Hao A <hao.a.wu@...>; devel@edk2.groups.io; Ni, Ray <ray.ni@...>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

Should we consider this workaround? I’m having issues interpreting this part of PCIe spec.

My understanding of this quote is that this capability can exist in but it shouldn’t be considered.

I would assume it’s possible option that it needs to be considered? Is that wrong?

 

Damian

 

 

From: Wu, Hao A <hao.a.wu@...>
Sent: Wednesday, September 8, 2021 9:17 AM
To: Bassa, Damian <damian.bassa@...>; devel@edk2.groups.io; Ni, Ray <ray.ni@...>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

Really sorry for the late response.

 

So this is a workaround for RCiEP device that is not compliant to the PCIe spec:

|>  ARI is an optional capability. This capability must be implemented by each

|>  Function in an ARI Device. It is not applicable to a Root Port, a Switch

|>  Downstream Port, an RCiEP, or a Root Complex Event Collector.

 

If this the case, could you help to:

* Add a comment that briefly describe this workaround before the newly added code

* Also mention this workaround information in the commit log message.

* Send out a V2 version of the patch?

Thanks in advance.

 

Hello Ray, please help to raise if you have concern on this.

 

Best Regards,

Hao Wu

 

From: Bassa, Damian <damian.bassa@...>
Sent: Wednesday, September 1, 2021 1:45 AM
To: Wu, Hao A <hao.a.wu@...>; devel@edk2.groups.io; Ni, Ray <ray.ni@...>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

It refers to access to the root port device that doesn’t exist in case we are dealing with RCiEP device.

There can be specific case where RCiEP device has ARI extended capability ID (even though it’s unsupported in this case).

In such a case PciSearchDevice goes to CreatePciIoDevice through GatherDeviceInfo. And in this case parent is PCI_IO_DEVICE instance created from CreateRootBridge function, which isn’t valid PCIe device and doesn’t have specific bus, only a range of buses. In that case enumerator tries to use this instance to read operation using default 0 bus number, which isn’t correct.

 

Damian

 

From: Wu, Hao A <hao.a.wu@...>
Sent: Tuesday, August 31, 2021 6:28 AM
To: devel@edk2.groups.io; Wu, Hao A <hao.a.wu@...>; Bassa, Damian <damian.bassa@...>; Ni, Ray <ray.ni@...>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Wu, Hao A
Sent: Tuesday, August 31, 2021 12:25 PM
To: devel@edk2.groups.io; Bassa, Damian <damian.bassa@...>
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

Really sorry,

 

Could you help to provide more information on the below statement?

“undefined parent register accesses”

 

Thanks in advance.

 

Best Regards,

Hao Wu

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Bassa, Damian
Sent: Tuesday, August 24, 2021 11:15 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check for RCiEP before looking for RP

 

Before trying to access parent root port to check ARI capabilities,

enumerator should see if Endpoint device is not Root Complex integrated

to avoid undefined parent register accesses in these cases.

 

Signed-off-by: Damian Bassa damian.bassa@...

 

---

.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c         | 12 +++++++++++-

1 file changed, 11 insertions(+), 1 deletion(-)

 

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

index db1b35f8ef..6451fb8af9 100644

--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

@@ -2153,6 +2153,7 @@ CreatePciIoDevice (

   PCI_IO_DEVICE        *PciIoDevice;

   EFI_PCI_IO_PROTOCOL  *PciIo;

   EFI_STATUS           Status;

+  PCI_REG_PCIE_CAPABILITY Capability;

 

   PciIoDevice = AllocateZeroPool (sizeof (PCI_IO_DEVICE));

   if (PciIoDevice == NULL) {

@@ -2229,7 +2230,16 @@ CreatePciIoDevice (

     return NULL;

   }

 

-  if (PcdGetBool (PcdAriSupport)) {

+  PciIo->Pci.Read (

+                PciIo,

+                EfiPciIoWidthUint16,

+                PciIoDevice->PciExpressCapabilityOffset + OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability),

+                1,

+                &Capability.Uint16

+                );

+

+  if (PcdGetBool (PcdAriSupport) &&

+    Capability.Bits.DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {

     //

     // Check if the device is an ARI device.

     //

--

2.27.0.windows.1

 


Intel Technology Poland sp. z o.o.
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This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

 


Intel Technology Poland sp. z o.o.
ul. Słowackiego 173 | 80-298 Gdańsk | Sąd Rejonowy Gdańsk Północ | VII Wydział Gospodarczy Krajowego Rejestru Sądowego - KRS 101882 | NIP 957-07-52-316 | Kapitał zakładowy 200.000 PLN.

Ta wiadomość wraz z załącznikami jest przeznaczona dla określonego adresata i może zawierać informacje poufne. W razie przypadkowego otrzymania tej wiadomości, prosimy o powiadomienie nadawcy oraz trwałe jej usunięcie; jakiekolwiek przeglądanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.


Re: RFC: Add BaseLib/QuickSort in MdePkg

Chan, Amy <amy.chan@...>
 

Just to double confirm, will we have the null instance of QuickSort in MdePkg?

 

Regards,

Amy

 

From: gaoliming <gaoliming@...>
Sent: Thursday, September 16, 2021 10:23 AM
To: 'Andrew Fish' <afish@...>; 'edk2-devel-groups-io' <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>; 'Gao, Liming' <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
Subject:
回复: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Andrew:

 Thanks for your suggestion. I think your idea is better. We add new QuickSort() API to BaseLib, and update SortLib library instance to consume BaseLib QuickSort() API. This way has no change in current SortLib library class. It is the compatible solution.

 

Thanks

Liming

发件人: Andrew Fish <afish@...>
发送时间: 2021916 10:13
收件人: edk2-devel-groups-io <devel@edk2.groups.io>; Liming Gao <gaoliming@...>
抄送: Ni, Ray <ray.ni@...>; Mike Kinney <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
主题: Re: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

 

 

On Sep 15, 2021, at 6:26 PM, gaoliming <gaoliming@...> wrote:

 

Ray:

 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform. 

 

 

If we add QuickSort() API to the BaseLib can we not just port the existing MdeModulePkg/SortLib to use QuickSort() in the implementation? Or is there some other way to add the new thing in a backward compatible way.

 

Thanks,

 

Andrew Fish

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间:
 2021914 14:15
收件人:
 Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送:
 devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题:
 [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,

 

A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.

 

UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.

 

To address this issue, there are two approaches:

  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.

 

Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.

We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.

 

If you don’t have concerns, I plan to:

  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.

VOID

EFIAPI

QuickSort (

  IN OUT VOID                   *BufferToSort,

  IN CONST UINTN                Count,

  IN CONST UINTN                ElementSize,

  IN       SORT_COMPARE         CompareFunction

  );

 

  1. “Add new ShellPkg/SortCompareLib”

Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.

 

Any concerns?

 

Thanks,

Ray

 

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