Date   

Re: [PATCH v1] IntelFsp2WrapperPkg: Make PcdFspModeSelection dynamic and set it accordingly

Chiu, Chasel
 

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

-----Original Message-----
From: Zhang, Xiaoqiang <xiaoqiang.zhang@intel.com>
Sent: Thursday, September 16, 2021 11:45 AM
To: devel@edk2.groups.io
Cc: Zhang, Xiaoqiang <xiaoqiang.zhang@intel.com>; Chiu, Chasel
<chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>
Subject: [PATCH v1] IntelFsp2WrapperPkg: Make PcdFspModeSelection dynamic
and set it accordingly

From: Zhang Xiaoqiang <xiaoqiang.zhang@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3632

PcdFspModeSelection will be used to set FSP mode.
Make PcdFspModeSelection dynamic and set it accordingly.

Signed-off-by: Zhang Xiaoqiang <xiaoqiang.zhang@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
---
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
index a3b9363779..b8dac1b574 100644
--- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
@@ -82,12 +82,6 @@
# @Prompt Skip FSP API from FSP wrapper.


gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x400
00009



- ## This PCD decides how Wrapper code utilizes FSP

- # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling
FSP API)

- # 1: API mode (FSP Wrapper will call FSP API)

- #

-
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|
0x4000000A

-

## This PCD decides how FSP is measured

# 1) The BootGuard ACM may already measured the FSP component, such as
FSPT/FSPM.

# We need a flag (PCD) to indicate if there is need to do such FSP measurement
or NOT.

@@ -106,6 +100,12 @@

gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig|0x00000000|UI
NT32|0x4000000B



[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]

+ ## This PCD decides how Wrapper code utilizes FSP

+ # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without calling
FSP API)

+ # 1: API mode (FSP Wrapper will call FSP API)

+ #

+
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|
0x4000000A

+

#

## These are the base address of FSP-M/S

#

--
2.32.0.windows.1


Re: RFC: Add BaseLib/QuickSort in MdePkg

Ni, Ray
 

Amy,

No. We only Add QuickSort() function API into BaseLib.h.

 

From: Chan, Amy <amy.chan@...>
Sent: Thursday, September 16, 2021 10:46 AM
To: gaoliming <gaoliming@...>; 'Andrew Fish' <afish@...>; 'edk2-devel-groups-io' <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>; 'Gao, Liming' <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
Subject: RE: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Just to double confirm, will we have the null instance of QuickSort in MdePkg?

 

Regards,

Amy

 

From: gaoliming <gaoliming@...>
Sent: Thursday, September 16, 2021 10:23 AM
To: 'Andrew Fish' <afish@...>; 'edk2-devel-groups-io' <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>; 'Gao, Liming' <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
Subject:
回复: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Andrew:

 Thanks for your suggestion. I think your idea is better. We add new QuickSort() API to BaseLib, and update SortLib library instance to consume BaseLib QuickSort() API. This way has no change in current SortLib library class. It is the compatible solution.

 

Thanks

Liming

发件人: Andrew Fish <afish@...>
发送时间: 2021916 10:13
收件人: edk2-devel-groups-io <devel@edk2.groups.io>; Liming Gao <gaoliming@...>
抄送: Ni, Ray <ray.ni@...>; Mike Kinney <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
主题: Re: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

 

 

On Sep 15, 2021, at 6:26 PM, gaoliming <gaoliming@...> wrote:

 

Ray:

 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform. 

 

 

If we add QuickSort() API to the BaseLib can we not just port the existing MdeModulePkg/SortLib to use QuickSort() in the implementation? Or is there some other way to add the new thing in a backward compatible way.

 

Thanks,

 

Andrew Fish

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间:
 2021914 14:15
收件人:
 Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送:
 devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题:
 [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,

 

A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.

 

UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.

 

To address this issue, there are two approaches:

  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.

 

Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.

We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.

 

If you don’t have concerns, I plan to:

  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.

VOID

EFIAPI

QuickSort (

  IN OUT VOID                   *BufferToSort,

  IN CONST UINTN                Count,

  IN CONST UINTN                ElementSize,

  IN       SORT_COMPARE         CompareFunction

  );

 

  1. “Add new ShellPkg/SortCompareLib”

Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.

 

Any concerns?

 

Thanks,

Ray

 


Re: RFC: Add BaseLib/QuickSort in MdePkg

Ni, Ray
 

Andrew, Liming,

I think your idea works better.

 

UefiCpuPkg  à MdePkg (BaseLib)

xxxPkg à MdeModulePkg (SortLib) à MdePkg (BaseLib)

 

Gradually we will eliminate the MdeModulePkg (SortLib) layer.

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of gaoliming
Sent: Thursday, September 16, 2021 10:23 AM
To: 'Andrew Fish' <afish@...>; 'edk2-devel-groups-io' <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>; 'Gao, Liming' <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
Subject:
回复: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Andrew:

 Thanks for your suggestion. I think your idea is better. We add new QuickSort() API to BaseLib, and update SortLib library instance to consume BaseLib QuickSort() API. This way has no change in current SortLib library class. It is the compatible solution.

 

Thanks

Liming

发件人: Andrew Fish <afish@...>
发送时间: 2021916 10:13
收件人: edk2-devel-groups-io <devel@edk2.groups.io>; Liming Gao <gaoliming@...>
抄送: Ni, Ray <ray.ni@...>; Mike Kinney <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
主题: Re: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

 

 

On Sep 15, 2021, at 6:26 PM, gaoliming <gaoliming@...> wrote:

 

Ray:

 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform. 

 

 

If we add QuickSort() API to the BaseLib can we not just port the existing MdeModulePkg/SortLib to use QuickSort() in the implementation? Or is there some other way to add the new thing in a backward compatible way.

 

Thanks,

 

Andrew Fish

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间: 2021914 14:15
收件人: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送: devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,

 

A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.

 

UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.

 

To address this issue, there are two approaches:

  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.

 

Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.

We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.

 

If you don’t have concerns, I plan to:

  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.

VOID

EFIAPI

QuickSort (

  IN OUT VOID                   *BufferToSort,

  IN CONST UINTN                Count,

  IN CONST UINTN                ElementSize,

  IN       SORT_COMPARE         CompareFunction

  );

 

  1. “Add new ShellPkg/SortCompareLib”

Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.

 

Any concerns?

 

Thanks,

Ray

 


回复: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

gaoliming
 

Andrew:

 Thanks for your suggestion. I think your idea is better. We add new QuickSort() API to BaseLib, and update SortLib library instance to consume BaseLib QuickSort() API. This way has no change in current SortLib library class. It is the compatible solution.

 

Thanks

Liming

发件人: Andrew Fish <afish@...>
发送时间: 2021916 10:13
收件人: edk2-devel-groups-io <devel@edk2.groups.io>; Liming Gao <gaoliming@...>
抄送: Ni, Ray <ray.ni@...>; Mike Kinney <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>; Chan, Amy <amy.chan@...>
主题: Re: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

 



On Sep 15, 2021, at 6:26 PM, gaoliming <gaoliming@...> wrote:

 

Ray:

 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform. 

 

 

If we add QuickSort() API to the BaseLib can we not just port the existing MdeModulePkg/SortLib to use QuickSort() in the implementation? Or is there some other way to add the new thing in a backward compatible way.

 

Thanks,

 

Andrew Fish



Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间: 2021914 14:15
收件人: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送: devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,

 

A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.

 

UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.

 

To address this issue, there are two approaches:

  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.

 

Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.

We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.

 

If you don’t have concerns, I plan to:

  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.

VOID

EFIAPI

QuickSort (

  IN OUT VOID                   *BufferToSort,

  IN CONST UINTN                Count,

  IN CONST UINTN                ElementSize,

  IN       SORT_COMPARE         CompareFunction

  );

 

  1. “Add new ShellPkg/SortCompareLib”

Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.

 

Any concerns?

 

Thanks,

Ray

 


Re: [PATCH v3 0/7] New MM Communicate header and interfaces

Kun Qin
 

Hi EDK2 maintainers,

It has been a while since this v3 patch series were sent. May I please have some feedback on the proposed PI spec change? Any input is appreciated.

Regards,
Kun


Re: RFC: Add BaseLib/QuickSort in MdePkg

Andrew Fish
 



On Sep 15, 2021, at 6:26 PM, gaoliming <gaoliming@...> wrote:

Ray:
 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform. 
 

If we add QuickSort() API to the BaseLib can we not just port the existing MdeModulePkg/SortLib to use QuickSort() in the implementation? Or is there some other way to add the new thing in a backward compatible way.

Thanks,

Andrew Fish

Thanks
Liming
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间: 2021914 14:15
收件人: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送: devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg
 
Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,
 
A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.
 
UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.
 
To address this issue, there are two approaches:
  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.
 
Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.
We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.
 
If you don’t have concerns, I plan to:
  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.
VOID
EFIAPI
QuickSort (
  IN OUT VOID                   *BufferToSort,
  IN CONST UINTN                Count,
  IN CONST UINTN                ElementSize,
  IN       SORT_COMPARE         CompareFunction
  );
 
  1. “Add new ShellPkg/SortCompareLib”
Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.
 
Any concerns?
 
Thanks,
Ray



[PATCH v1 1/2] UefiCpuPkg: Refactor initialization of CPU features during S3 resume

Jason Lou
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3621
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3631

Refactor initialization of CPU features during S3 resume.

In addition, the macro ACPI_CPU_DATA_STRUCTURE_UPDATE is used to fix
incompatibility issue caused by ACPI_CPU_DATA structure update. It will
be removed after all the platform code uses new ACPI_CPU_DATA structure.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
OvmfPkg/CpuS3DataDxe/CpuS3Data.c | 7 +-
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 7 +-
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 12 +-
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 18 +=
--
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 163 +=
+++++++++++--------
UefiCpuPkg/Include/AcpiCpuData.h | 91 +=
+++++-----
6 files changed, 170 insertions(+), 128 deletions(-)

diff --git a/OvmfPkg/CpuS3DataDxe/CpuS3Data.c b/OvmfPkg/CpuS3DataDxe/CpuS3D=
ata.c
index 5ffe1f3cd7..de20d87567 100644
--- a/OvmfPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/OvmfPkg/CpuS3DataDxe/CpuS3Data.c
@@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so thi=
s module does not
support hot plug CPUs. This module can be copied into a CPU specific pack=
age=0D
and customized if these additional features are required.=0D
=0D
-Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2015 - 2020, Red Hat, Inc.=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
@@ -252,10 +252,7 @@ CpuS3DataInitialize (
AcpiCpuDataEx->IdtrProfile.Base =3D (UINTN)Idt;=0D
=0D
if (OldAcpiCpuData !=3D NULL) {=0D
- AcpiCpuData->RegisterTable =3D OldAcpiCpuData->RegisterTable=
;=0D
- AcpiCpuData->PreSmmInitRegisterTable =3D OldAcpiCpuData->PreSmmInitReg=
isterTable;=0D
- AcpiCpuData->ApLocation =3D OldAcpiCpuData->ApLocation;=0D
- CopyMem (&AcpiCpuData->CpuStatus, &OldAcpiCpuData->CpuStatus, sizeof (=
CPU_STATUS_INFORMATION));=0D
+ CopyMem (&AcpiCpuData->CpuFeatureInitData, &OldAcpiCpuData->CpuFeature=
InitData, sizeof (CPU_FEATURE_INIT_DATA));=0D
}=0D
=0D
//=0D
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/=
CpuS3Data.c
index 078af36cfb..61ec7c44b2 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so thi=
s module does not
support hot plug CPUs. This module can be copied into a CPU specific pack=
age=0D
and customized if these additional features are required.=0D
=0D
-Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2015, Red Hat, Inc.=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
@@ -247,10 +247,7 @@ CpuS3DataInitialize (
AcpiCpuDataEx->IdtrProfile.Base =3D (UINTN)Idt;=0D
=0D
if (OldAcpiCpuData !=3D NULL) {=0D
- AcpiCpuData->RegisterTable =3D OldAcpiCpuData->RegisterTable=
;=0D
- AcpiCpuData->PreSmmInitRegisterTable =3D OldAcpiCpuData->PreSmmInitReg=
isterTable;=0D
- AcpiCpuData->ApLocation =3D OldAcpiCpuData->ApLocation;=0D
- CopyMem (&AcpiCpuData->CpuStatus, &OldAcpiCpuData->CpuStatus, sizeof (=
CPU_STATUS_INFORMATION));=0D
+ CopyMem (&AcpiCpuData->CpuFeatureInitData, &OldAcpiCpuData->CpuFeature=
InitData, sizeof (CPU_FEATURE_INIT_DATA));=0D
}=0D
=0D
//=0D
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ=
e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 57511c4efa..6e2ab79518 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -1,7 +1,7 @@
/** @file=0D
CPU Features Initialize functions.=0D
=0D
- Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -152,10 +152,10 @@ CpuInitDataInitialize (
ASSERT (AcpiCpuData !=3D NULL);=0D
CpuFeaturesData->AcpiCpuData=3D AcpiCpuData;=0D
=0D
- CpuStatus =3D &AcpiCpuData->CpuStatus;=0D
+ CpuStatus =3D &AcpiCpuData->CpuFeatureInitData.CpuStatus;=0D
Location =3D AllocateZeroPool (sizeof (EFI_CPU_PHYSICAL_LOCATION) * Numb=
erOfCpus);=0D
ASSERT (Location !=3D NULL);=0D
- AcpiCpuData->ApLocation =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Location;=0D
+ AcpiCpuData->CpuFeatureInitData.ApLocation =3D (EFI_PHYSICAL_ADDRESS)(UI=
NTN)Location;=0D
=0D
for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum=
ber++) {=0D
InitOrder =3D &CpuFeaturesData->InitOrder[ProcessorNumber];=0D
@@ -1131,7 +1131,7 @@ SetProcessorRegister (
CpuFeaturesData =3D (CPU_FEATURES_DATA *) Buffer;=0D
AcpiCpuData =3D CpuFeaturesData->AcpiCpuData;=0D
=0D
- RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTab=
le;=0D
+ RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureI=
nitData.RegisterTable;=0D
=0D
InitApicId =3D GetInitialApicId ();=0D
RegisterTable =3D NULL;=0D
@@ -1147,8 +1147,8 @@ SetProcessorRegister (
=0D
ProgramProcessorRegister (=0D
RegisterTable,=0D
- (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCpuData->ApLocation + ProcInde=
x,=0D
- &AcpiCpuData->CpuStatus,=0D
+ (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCpuData->CpuFeatureInitData.Ap=
Location + ProcIndex,=0D
+ &AcpiCpuData->CpuFeatureInitData.CpuStatus,=0D
&CpuFeaturesData->CpuFlags=0D
);=0D
}=0D
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL=
ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 60daa5cc87..e6ef9c602d 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -952,8 +952,8 @@ GetAcpiCpuData (
AcpiCpuData->NumberOfCpus =3D (UINT32)NumberOfCpus;=0D
}=0D
=0D
- if (AcpiCpuData->RegisterTable =3D=3D 0 ||=0D
- AcpiCpuData->PreSmmInitRegisterTable =3D=3D 0) {=0D
+ if (AcpiCpuData->CpuFeatureInitData.RegisterTable =3D=3D 0 ||=0D
+ AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable =3D=3D 0) {=
=0D
//=0D
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable=
for all CPUs=0D
//=0D
@@ -976,11 +976,11 @@ GetAcpiCpuData (
RegisterTable[NumberOfCpus + Index].AllocatedSize =3D 0;=0D
RegisterTable[NumberOfCpus + Index].RegisterTableEntry =3D 0;=0D
}=0D
- if (AcpiCpuData->RegisterTable =3D=3D 0) {=0D
- AcpiCpuData->RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Register=
Table;=0D
+ if (AcpiCpuData->CpuFeatureInitData.RegisterTable =3D=3D 0) {=0D
+ AcpiCpuData->CpuFeatureInitData.RegisterTable =3D (EFI_PHYSICAL_ADDR=
ESS)(UINTN)RegisterTable;=0D
}=0D
- if (AcpiCpuData->PreSmmInitRegisterTable =3D=3D 0) {=0D
- AcpiCpuData->PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINT=
N)(RegisterTable + NumberOfCpus);=0D
+ if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable =3D=3D 0) =
{=0D
+ AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable =3D (EFI_PHY=
SICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);=0D
}=0D
}=0D
=0D
@@ -1063,9 +1063,9 @@ CpuRegisterTableWriteWorker (
CpuFeaturesData =3D GetCpuFeaturesData ();=0D
if (CpuFeaturesData->RegisterTable =3D=3D NULL) {=0D
AcpiCpuData =3D GetAcpiCpuData ();=0D
- ASSERT ((AcpiCpuData !=3D NULL) && (AcpiCpuData->RegisterTable !=3D 0)=
);=0D
- CpuFeaturesData->RegisterTable =3D (CPU_REGISTER_TABLE *) (UINTN) Acpi=
CpuData->RegisterTable;=0D
- CpuFeaturesData->PreSmmRegisterTable =3D (CPU_REGISTER_TABLE *) (UINTN=
) AcpiCpuData->PreSmmInitRegisterTable;=0D
+ ASSERT ((AcpiCpuData !=3D NULL) && (AcpiCpuData->CpuFeatureInitData.Re=
gisterTable !=3D 0));=0D
+ CpuFeaturesData->RegisterTable =3D (CPU_REGISTER_TABLE *) (UINTN) Acpi=
CpuData->CpuFeatureInitData.RegisterTable;=0D
+ CpuFeaturesData->PreSmmRegisterTable =3D (CPU_REGISTER_TABLE *) (UINTN=
) AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;=0D
}=0D
=0D
if (PreSmmFlag) {=0D
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/=
CpuS3.c
index ab7f39aa2b..1270992f38 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -476,16 +476,22 @@ SetRegister (
IN BOOLEAN PreSmmRegisterTable=0D
)=0D
{=0D
+ CPU_FEATURE_INIT_DATA *FeatureInitData;=0D
CPU_REGISTER_TABLE *RegisterTable;=0D
CPU_REGISTER_TABLE *RegisterTables;=0D
UINT32 InitApicId;=0D
UINTN ProcIndex;=0D
UINTN Index;=0D
=0D
+ FeatureInitData =3D &mAcpiCpuData.CpuFeatureInitData;=0D
+ if (FeatureInitData =3D=3D NULL) {=0D
+ return;=0D
+ }=0D
+=0D
if (PreSmmRegisterTable) {=0D
- RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmIni=
tRegisterTable;=0D
+ RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->PreSm=
mInitRegisterTable;=0D
} else {=0D
- RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterT=
able;=0D
+ RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->Regis=
terTable;=0D
}=0D
if (RegisterTables =3D=3D NULL) {=0D
return;=0D
@@ -503,18 +509,18 @@ SetRegister (
}=0D
ASSERT (RegisterTable !=3D NULL);=0D
=0D
- if (mAcpiCpuData.ApLocation !=3D 0) {=0D
+ if (FeatureInitData->ApLocation !=3D 0) {=0D
ProgramProcessorRegister (=0D
RegisterTable,=0D
- (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)mAcpiCpuData.ApLocation + ProcIn=
dex,=0D
- &mAcpiCpuData.CpuStatus,=0D
+ (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)FeatureInitData->ApLocation + Pr=
ocIndex,=0D
+ &FeatureInitData->CpuStatus,=0D
&mCpuFlags=0D
);=0D
} else {=0D
ProgramProcessorRegister (=0D
RegisterTable,=0D
NULL,=0D
- &mAcpiCpuData.CpuStatus,=0D
+ &FeatureInitData->CpuStatus,=0D
&mCpuFlags=0D
);=0D
}=0D
@@ -1010,6 +1016,71 @@ IsRegisterTableEmpty (
return TRUE;=0D
}=0D
=0D
+/**=0D
+ Copy the data used to initialize processor register into SMRAM.=0D
+=0D
+ @param[in,out] CpuFeatureInitDataDst Pointer to the destination CPU_F=
EATURE_INIT_DATA structure.=0D
+ @param[in] CpuFeatureInitDataSrc Pointer to the source CPU_FEATUR=
E_INIT_DATA structure.=0D
+=0D
+**/=0D
+VOID=0D
+CopyCpuFeatureInitDatatoSmram (=0D
+ IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst,=0D
+ IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc=0D
+ )=0D
+{=0D
+ CPU_STATUS_INFORMATION *CpuStatus;=0D
+=0D
+ if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDa=
taSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {=0D
+ CpuFeatureInitDataDst->PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRE=
SS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TA=
BLE));=0D
+ ASSERT (CpuFeatureInitDataDst->PreSmmInitRegisterTable !=3D 0);=0D
+=0D
+ CopyRegisterTable (=0D
+ (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->PreSmmInitRegist=
erTable,=0D
+ (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegist=
erTable,=0D
+ mAcpiCpuData.NumberOfCpus=0D
+ );=0D
+ }=0D
+=0D
+ if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDa=
taSrc->RegisterTable, mAcpiCpuData.NumberOfCpus)) {=0D
+ CpuFeatureInitDataDst->RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)=
AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));=0D
+ ASSERT (CpuFeatureInitDataDst->RegisterTable !=3D 0);=0D
+=0D
+ CopyRegisterTable (=0D
+ (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataDst->RegisterTable,=0D
+ (CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->RegisterTable,=0D
+ mAcpiCpuData.NumberOfCpus=0D
+ );=0D
+ }=0D
+=0D
+ CpuStatus =3D &CpuFeatureInitDataDst->CpuStatus;=0D
+ CopyMem (CpuStatus, &CpuFeatureInitDataSrc->CpuStatus, sizeof (CPU_STATU=
S_INFORMATION));=0D
+=0D
+ if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage !=3D 0) {=0D
+ CpuStatus->ThreadCountPerPackage =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Allo=
cateCopyPool (=0D
+ sizeof (UINT32) * CpuStatus->P=
ackageCount,=0D
+ (UINT32 *)(UINTN)CpuFeatureIni=
tDataSrc->CpuStatus.ThreadCountPerPackage=0D
+ );=0D
+ ASSERT (CpuStatus->ThreadCountPerPackage !=3D 0);=0D
+ }=0D
+=0D
+ if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore !=3D 0) {=0D
+ CpuStatus->ThreadCountPerCore =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Allocat=
eCopyPool (=0D
+ sizeof (UINT8) * (CpuStatus->P=
ackageCount * CpuStatus->MaxCoreCount),=0D
+ (UINT32 *)(UINTN)CpuFeatureIni=
tDataSrc->CpuStatus.ThreadCountPerCore=0D
+ );=0D
+ ASSERT (CpuStatus->ThreadCountPerCore !=3D 0);=0D
+ }=0D
+=0D
+ if (CpuFeatureInitDataSrc->ApLocation !=3D 0) {=0D
+ CpuFeatureInitDataDst->ApLocation =3D (EFI_PHYSICAL_ADDRESS)(UINTN)All=
ocateCopyPool (=0D
+ mAcpiCpuData.NumberOfCpus * sizeof (EFI_CP=
U_PHYSICAL_LOCATION),=0D
+ (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFea=
tureInitDataSrc->ApLocation=0D
+ );=0D
+ ASSERT (CpuFeatureInitDataDst->ApLocation !=3D 0);=0D
+ }=0D
+}=0D
+=0D
/**=0D
Get ACPI CPU data.=0D
=0D
@@ -1064,39 +1135,13 @@ GetAcpiCpuData (
=0D
CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpu=
Data->IdtrProfile, sizeof (IA32_DESCRIPTOR));=0D
=0D
- if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->Pre=
SmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {=0D
- mAcpiCpuData.PreSmmInitRegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)=
AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));=0D
- ASSERT (mAcpiCpuData.PreSmmInitRegisterTable !=3D 0);=0D
-=0D
- CopyRegisterTable (=0D
- (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,=0D
- (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,=0D
- mAcpiCpuData.NumberOfCpus=0D
- );=0D
- } else {=0D
- mAcpiCpuData.PreSmmInitRegisterTable =3D 0;=0D
- }=0D
-=0D
- if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->Reg=
isterTable, mAcpiCpuData.NumberOfCpus)) {=0D
- mAcpiCpuData.RegisterTable =3D (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePo=
ol (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));=0D
- ASSERT (mAcpiCpuData.RegisterTable !=3D 0);=0D
-=0D
- CopyRegisterTable (=0D
- (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,=0D
- (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,=0D
- mAcpiCpuData.NumberOfCpus=0D
- );=0D
- } else {=0D
- mAcpiCpuData.RegisterTable =3D 0;=0D
- }=0D
-=0D
//=0D
// Copy AP's GDT, IDT and Machine Check handler into SMRAM.=0D
//=0D
Gdtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;=0D
Idtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;=0D
=0D
- GdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcp=
iCpuData.ApMachineCheckHandlerSize);=0D
+ GdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpi=
CpuData.ApMachineCheckHandlerSize);=0D
ASSERT (GdtForAp !=3D NULL);=0D
IdtForAp =3D (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));=0D
MachineCheckHandlerForAp =3D (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + =
1));=0D
@@ -1109,41 +1154,23 @@ GetAcpiCpuData (
Idtr->Base =3D (UINTN)IdtForAp;=0D
mAcpiCpuData.ApMachineCheckHandlerBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)=
MachineCheckHandlerForAp;=0D
=0D
- CpuStatus =3D &mAcpiCpuData.CpuStatus;=0D
- CopyMem (CpuStatus, &AcpiCpuData->CpuStatus, sizeof (CPU_STATUS_INFORMAT=
ION));=0D
- if (AcpiCpuData->CpuStatus.ThreadCountPerPackage !=3D 0) {=0D
- CpuStatus->ThreadCountPerPackage =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Allo=
cateCopyPool (=0D
- sizeof (UINT32) * CpuStatus->P=
ackageCount,=0D
- (UINT32 *)(UINTN)AcpiCpuData->=
CpuStatus.ThreadCountPerPackage=0D
- );=0D
- ASSERT (CpuStatus->ThreadCountPerPackage !=3D 0);=0D
- }=0D
- if (AcpiCpuData->CpuStatus.ThreadCountPerCore !=3D 0) {=0D
- CpuStatus->ThreadCountPerCore =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Allocat=
eCopyPool (=0D
- sizeof (UINT8) * (CpuStatus->P=
ackageCount * CpuStatus->MaxCoreCount),=0D
- (UINT32 *)(UINTN)AcpiCpuData->=
CpuStatus.ThreadCountPerCore=0D
- );=0D
- ASSERT (CpuStatus->ThreadCountPerCore !=3D 0);=0D
- }=0D
- if (AcpiCpuData->ApLocation !=3D 0) {=0D
- mAcpiCpuData.ApLocation =3D (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyP=
ool (=0D
- mAcpiCpuData.NumberOfCpus * sizeof (EFI_CP=
U_PHYSICAL_LOCATION),=0D
- (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)AcpiCp=
uData->ApLocation=0D
- );=0D
- ASSERT (mAcpiCpuData.ApLocation !=3D 0);=0D
- }=0D
- if (CpuStatus->PackageCount !=3D 0) {=0D
- mCpuFlags.CoreSemaphoreCount =3D AllocateZeroPool (=0D
- sizeof (UINT32) * CpuStatus->PackageC=
ount *=0D
- CpuStatus->MaxCoreCount * CpuStatus->=
MaxThreadCount=0D
- );=0D
- ASSERT (mCpuFlags.CoreSemaphoreCount !=3D NULL);=0D
- mCpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (=0D
- sizeof (UINT32) * CpuStatus->Packa=
geCount *=0D
- CpuStatus->MaxCoreCount * CpuStatu=
s->MaxThreadCount=0D
- );=0D
- ASSERT (mCpuFlags.PackageSemaphoreCount !=3D NULL);=0D
- }=0D
+ ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA=
));=0D
+ CopyCpuFeatureInitDatatoSmram (&mAcpiCpuData.CpuFeatureInitData, &AcpiCp=
uData->CpuFeatureInitData);=0D
+=0D
+ CpuStatus =3D &mAcpiCpuData.CpuFeatureInitData.CpuStatus;=0D
+=0D
+ mCpuFlags.CoreSemaphoreCount =3D AllocateZeroPool (=0D
+ sizeof (UINT32) * CpuStatus->PackageCou=
nt *=0D
+ CpuStatus->MaxCoreCount * CpuStatus->Ma=
xThreadCount=0D
+ );=0D
+ ASSERT (mCpuFlags.CoreSemaphoreCount !=3D NULL);=0D
+=0D
+ mCpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (=0D
+ sizeof (UINT32) * CpuStatus->Package=
Count *=0D
+ CpuStatus->MaxCoreCount * CpuStatus-=
MaxThreadCount=0D
+ );=0D
+ ASSERT (mCpuFlags.PackageSemaphoreCount !=3D NULL);=0D
+=0D
InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);=0D
}=0D
=0D
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD=
ata.h
index 62a01b2c6b..2fa8801d1f 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -1,7 +1,7 @@
/** @file=0D
Definitions for CPU S3 data.=0D
=0D
-Copyright (c) 2013 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2013 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -9,6 +9,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _ACPI_CPU_DATA_H_=0D
#define _ACPI_CPU_DATA_H_=0D
=0D
+//=0D
+// This macro definition is used to fix incompatibility issue caused by=0D
+// ACPI_CPU_DATA structure update. It will be removed after all the platfo=
rm=0D
+// code uses new ACPI_CPU_DATA structure.=0D
+//=0D
+#ifndef ACPI_CPU_DATA_STRUCTURE_UPDATE=0D
+#define ACPI_CPU_DATA_STRUCTURE_UPDATE=0D
+#endif=0D
+=0D
//=0D
// Register types in register table=0D
//=0D
@@ -118,6 +127,49 @@ typedef struct {
EFI_PHYSICAL_ADDRESS RegisterTableEntry;=0D
} CPU_REGISTER_TABLE;=0D
=0D
+//=0D
+// Data structure that is used for CPU feature initialization during ACPI =
S3=0D
+// resume.=0D
+//=0D
+typedef struct {=0D
+ //=0D
+ // Physical address of an array of CPU_REGISTER_TABLE structures, with=0D
+ // NumberOfCpus entries. If a register table is not required, then the=
=0D
+ // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to=
0.=0D
+ // If TableLength is > 0, then elements of RegisterTableEntry are used t=
o=0D
+ // initialize the CPU that matches InitialApicId, during an ACPI S3 resu=
me,=0D
+ // before SMBASE relocation is performed.=0D
+ // If a register table is not required for any one of the CPUs, then=0D
+ // PreSmmInitRegisterTable may be set to 0.=0D
+ //=0D
+ EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;=0D
+ //=0D
+ // Physical address of an array of CPU_REGISTER_TABLE structures, with=0D
+ // NumberOfCpus entries. If a register table is not required, then the=
=0D
+ // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to=
0.=0D
+ // If TableLength is > 0, then elements of RegisterTableEntry are used t=
o=0D
+ // initialize the CPU that matches InitialApicId, during an ACPI S3 resu=
me,=0D
+ // after SMBASE relocation is performed.=0D
+ // If a register table is not required for any one of the CPUs, then=0D
+ // RegisterTable may be set to 0.=0D
+ //=0D
+ EFI_PHYSICAL_ADDRESS RegisterTable;=0D
+ //=0D
+ // CPU information which is required when set the register table.=0D
+ //=0D
+ CPU_STATUS_INFORMATION CpuStatus;=0D
+ //=0D
+ // Location info for each AP.=0D
+ // It points to an array which saves all APs location info.=0D
+ // The array count is the AP count in this CPU.=0D
+ //=0D
+ // If the platform does not support MSR setting at S3 resume, and=0D
+ // therefore it doesn't need the dependency semaphores, it should set=0D
+ // this field to 0.=0D
+ //=0D
+ EFI_PHYSICAL_ADDRESS ApLocation;=0D
+} CPU_FEATURE_INIT_DATA;=0D
+=0D
//=0D
// Data structure that is required for ACPI S3 resume. The PCD=0D
// PcdCpuS3DataAddress must be set to the physical address where this stru=
cture=0D
@@ -172,28 +224,6 @@ typedef struct {
//=0D
EFI_PHYSICAL_ADDRESS MtrrTable;=0D
//=0D
- // Physical address of an array of CPU_REGISTER_TABLE structures, with=0D
- // NumberOfCpus entries. If a register table is not required, then the=
=0D
- // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to=
0.=0D
- // If TableLength is > 0, then elements of RegisterTableEntry are used t=
o=0D
- // initialize the CPU that matches InitialApicId, during an ACPI S3 resu=
me,=0D
- // before SMBASE relocation is performed.=0D
- // If a register table is not required for any one of the CPUs, then=0D
- // PreSmmInitRegisterTable may be set to 0.=0D
- //=0D
- EFI_PHYSICAL_ADDRESS PreSmmInitRegisterTable;=0D
- //=0D
- // Physical address of an array of CPU_REGISTER_TABLE structures, with=0D
- // NumberOfCpus entries. If a register table is not required, then the=
=0D
- // TableLength and AllocatedSize fields of CPU_REGISTER_TABLE are set to=
0.=0D
- // If TableLength is > 0, then elements of RegisterTableEntry are used t=
o=0D
- // initialize the CPU that matches InitialApicId, during an ACPI S3 resu=
me,=0D
- // after SMBASE relocation is performed.=0D
- // If a register table is not required for any one of the CPUs, then=0D
- // RegisterTable may be set to 0.=0D
- //=0D
- EFI_PHYSICAL_ADDRESS RegisterTable;=0D
- //=0D
// Physical address of a buffer that contains the machine check handler =
that=0D
// is used during an ACPI S3 Resume. In order for this machine check=0D
// handler to be active on an AP during an ACPI S3 resume, the machine c=
heck=0D
@@ -208,19 +238,10 @@ typedef struct {
//=0D
UINT32 ApMachineCheckHandlerSize;=0D
//=0D
- // CPU information which is required when set the register table.=0D
- //=0D
- CPU_STATUS_INFORMATION CpuStatus;=0D
- //=0D
- // Location info for each AP.=0D
- // It points to an array which saves all APs location info.=0D
- // The array count is the AP count in this CPU.=0D
- //=0D
- // If the platform does not support MSR setting at S3 resume, and=0D
- // therefore it doesn't need the dependency semaphores, it should set=0D
- // this field to 0.=0D
+ // Data structure that is used for CPU feature initialization during ACP=
I S3=0D
+ // resume.=0D
//=0D
- EFI_PHYSICAL_ADDRESS ApLocation;=0D
+ CPU_FEATURE_INIT_DATA CpuFeatureInitData;=0D
} ACPI_CPU_DATA;=0D
=0D
#endif=0D
--=20
2.28.0.windows.1


[PATCH v1 2/2] UefiCpuPkg: Prevent from re-initializing CPU features during S3 resume

Jason Lou
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3621
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3631

Current CPU feature initialization design:
During normal boot, CpuFeaturesPei module (inside FSP) initializes the
CPU features. During S3 boot, CpuFeaturesPei module does nothing, and
CpuSmm driver (in SMRAM) initializes CPU features instead.

This code change prevents CpuSmm driver from re-initializing CPU
features during S3 resume if CpuFeaturesPei module has done the same
initialization.

In addition, EDK2 contains DxeIpl PEIM that calls S3RestoreConfig2 PPI
during S3 boot and this PPI eventually calls CpuSmm driver (in SMRAM) to
initialize the CPU features, so "EDK2 + FSP" does not have the CPU
feature initialization issue during S3 boot. But "coreboot" does not
contain DxeIpl PEIM and the issue appears, unless
"PcdCpuFeaturesInitOnS3Resume" is set to TRUE.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 34 ++++++++++++--------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 3 +-
2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/=
CpuS3.c
index 1270992f38..fece75266d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1155,23 +1155,31 @@ GetAcpiCpuData (
mAcpiCpuData.ApMachineCheckHandlerBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)=
MachineCheckHandlerForAp;=0D
=0D
ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA=
));=0D
- CopyCpuFeatureInitDatatoSmram (&mAcpiCpuData.CpuFeatureInitData, &AcpiCp=
uData->CpuFeatureInitData);=0D
=0D
- CpuStatus =3D &mAcpiCpuData.CpuFeatureInitData.CpuStatus;=0D
+ if (!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) {=0D
+ //=0D
+ // If the CPU features will not be initialized by CpuFeaturesPei modul=
e during=0D
+ // next ACPI S3 resume, copy the CPU features initialization data into=
SMRAM,=0D
+ // which will be consumed in SmmRestoreCpu during next S3 resume.=0D
+ //=0D
+ CopyCpuFeatureInitDatatoSmram (&mAcpiCpuData.CpuFeatureInitData, &Acpi=
CpuData->CpuFeatureInitData);=0D
=0D
- mCpuFlags.CoreSemaphoreCount =3D AllocateZeroPool (=0D
- sizeof (UINT32) * CpuStatus->PackageCou=
nt *=0D
- CpuStatus->MaxCoreCount * CpuStatus->Ma=
xThreadCount=0D
- );=0D
- ASSERT (mCpuFlags.CoreSemaphoreCount !=3D NULL);=0D
+ CpuStatus =3D &mAcpiCpuData.CpuFeatureInitData.CpuStatus;=0D
=0D
- mCpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (=0D
- sizeof (UINT32) * CpuStatus->Package=
Count *=0D
- CpuStatus->MaxCoreCount * CpuStatus-=
MaxThreadCount=0D
- );=0D
- ASSERT (mCpuFlags.PackageSemaphoreCount !=3D NULL);=0D
+ mCpuFlags.CoreSemaphoreCount =3D AllocateZeroPool (=0D
+ sizeof (UINT32) * CpuStatus->PackageC=
ount *=0D
+ CpuStatus->MaxCoreCount * CpuStatus->=
MaxThreadCount=0D
+ );=0D
+ ASSERT (mCpuFlags.CoreSemaphoreCount !=3D NULL);=0D
=0D
- InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);=0D
+ mCpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (=0D
+ sizeof (UINT32) * CpuStatus->Packa=
geCount *=0D
+ CpuStatus->MaxCoreCount * CpuStatu=
s->MaxThreadCount=0D
+ );=0D
+ ASSERT (mCpuFlags.PackageSemaphoreCount !=3D NULL);=0D
+=0D
+ InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);=0D
+ }=0D
}=0D
=0D
/**=0D
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm=
mCpuDxeSmm/PiSmmCpuDxeSmm.inf
index 76b1462996..0e88071c70 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -4,7 +4,7 @@
# This SMM driver performs SMM initialization, deploy SMM Entry Vector,=0D
# provides CPU specific services in SMM.=0D
#=0D
-# Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
@@ -134,6 +134,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ## CONS=
UMES=0D
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## CONS=
UMES=0D
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize ## SOME=
TIMES_CONSUMES=0D
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume ## CONS=
UMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONS=
UMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##=
CONSUMES=0D
--=20
2.28.0.windows.1


回复: [edk2-devel] [PATCH v1 0/3] MdeModulePkg/Core/Pei: Migration improvements and fixes

gaoliming
 

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 gaoliming
发送时间: 2021年9月10日 12:52
收件人: devel@edk2.groups.io; mikuback@linux.microsoft.com
抄送: 'Jian J Wang' <jian.j.wang@intel.com>; 'Dandan Bi'
<dandan.bi@intel.com>
主题: 回复: [edk2-devel] [PATCH v1 0/3] MdeModulePkg/Core/Pei:
Migration improvements and fixes

Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Michael
Kubacki
发送时间: 2021年9月9日 11:46
收件人: devel@edk2.groups.io
抄送: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Dandan Bi <dandan.bi@intel.com>
主题: [edk2-devel] [PATCH v1 0/3] MdeModulePkg/Core/Pei: Migration
improvements and fixes

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3512

This patch series contains three patches. The first two are for
relatively minor improvments - a typo fix in function descriptions
and changing the error level of a debug print. The third patch
fixes a pointer size mismatch.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Dandan Bi <dandan.bi@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

Michael Kubacki (3):
MdeModulePkg/Core/Pei: Fix typo in function descriptions
MdeModulePkg/Core/Pei: Make migrated PEIM message verbose
MdeModulePkg/Core/Pei: Fix pointer size mismatch in
EvacuateTempRam()

MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 13 ++++++++-----
MdeModulePkg/Core/Pei/PeiMain.h | 2 +-
2 files changed, 9 insertions(+), 6 deletions(-)

--
2.28.0.windows.1



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回复: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

gaoliming
 

Ray:

 SortLib has been added since 2015. I would suggest to still keep this library class. To resolve the package dependency, my proposal is to move the library class header file SortLib.h from MdeModulePkg to MdePkg, and still keep the library instance in MdeModulePkg. This proposal has no impact on the existing platform.

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间: 2021914 14:15
收件人: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; Liu, Zhiguang <zhiguang.liu@...>; Wang, Jian J <jian.j.wang@...>; Gao, Zhichao <zhichao.gao@...>
抄送: devel@edk2.groups.io; Chan, Amy <amy.chan@...>
主题: [edk2-devel] RFC: Add BaseLib/QuickSort in MdePkg

 

Hi package maintainers of MdePkg, MdeModulePkg and ShellPkg, community,

 

A commit (UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array) to UefiCpuPkg let
UefiCpuPkg depend on MdeModulePkg because the SortLib class and instances are all in MdeModulePkg.

 

UefiCpuPkg depending on MdeModulePkg breaks the rule that “UefiCpuPkg should ONLY depend on MdePkg”.

 

To address this issue, there are two approaches:

  1. Duplicate the sort logic in UefiCpuPkg to not depend on MdeModulePkg/SortLib
  2. Add QuickSort() API to BaseLib in MdePkg.

 

Approach #2 (MdePkg/BaseLib/QuickSort) makes more sense because quick sort is a standard algorithm.

We encourage consumers to update their code to use the quick sort in MdePkg and gradually deprecate today’s MdeModulePkg/SortLib.

 

If you don’t have concerns, I plan to:

  1. “Add QuickSort() to BaseLib” and update all existing consumers to use this API instead.

VOID

EFIAPI

QuickSort (

  IN OUT VOID                   *BufferToSort,

  IN CONST UINTN                Count,

  IN CONST UINTN                ElementSize,

  IN       SORT_COMPARE         CompareFunction

  );

 

  1. “Add new ShellPkg/SortCompareLib”

Background: ShellPkg requires to sort devicepath/string so 3 APIs in UefiSortLib (DevicePathCompare, StringNoCaseCompare, StringCompare) are provided for Shell usage. we can move the 3 APIs to the SortCompareLib and update Shell code to use BaseLib/QuickSort directly, with the sort compare function from SortCompareLib.

 

Any concerns?

 

Thanks,

Ray


[PATCH v1 3/3] MdeModulePkg: CI YAML: Added new GUID to ignore duplicate list

Kun Qin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629

SMM Communication PPI GUID from MdeModulePkg is defined the same as MM
Communication PPI GUID from MdePkg, according to PI Spec v1.5 and onward.

After introduction of MM Communication PPI definitions, an update in the
ignore duplicate list is needed to avoid breaking CI build.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
---
MdeModulePkg/MdeModulePkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/MdeModulePkg/MdeModulePkg.ci.yaml b/MdeModulePkg/MdeModulePkg.ci.yaml
index aa304f2ccd5c..b8d15a3e952e 100644
--- a/MdeModulePkg/MdeModulePkg.ci.yaml
+++ b/MdeModulePkg/MdeModulePkg.ci.yaml
@@ -84,6 +84,7 @@
"IgnoreDuplicates": [
"gEfiPeiMmAccessPpiGuid=gPeiSmmAccessPpiGuid",
"gPeiSmmControlPpiGuid=gEfiPeiMmControlPpiGuid",
+ "gEfiPeiMmCommunicationPpiGuid=gEfiPeiSmmCommunicationPpiGuid",
]
},

--
2.32.0.windows.1


[PATCH v1 2/3] MdePkg: CI YAML: Added new GUID to ignore duplicate list

Kun Qin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629

SMM Communication PPI GUID from MdeModulePkg is defined the same as MM
Communication PPI GUID from MdePkg, according to PI Spec v1.5 and onward.

After introduction of MM Communication PPI definitions, an update in the
ignore duplicate list is needed to avoid breaking CI build.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
---
MdePkg/MdePkg.ci.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 98eaea1c8248..3ea8eec33152 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -100,7 +100,8 @@
"gEfiProcessorSpecificErrorSectionGuid=gEfiIa32X64ProcessorErrorSectionGuid", ## is this a bug
"gEfiSmmPeriodicTimerDispatch2ProtocolGuid=gEfiMmPeriodicTimerDispatchProtocolGuid",
"gEfiPeiMmAccessPpiGuid=gPeiSmmAccessPpiGuid",
- "gPeiSmmControlPpiGuid=gEfiPeiMmControlPpiGuid"
+ "gPeiSmmControlPpiGuid=gEfiPeiMmControlPpiGuid",
+ "gEfiPeiMmCommunicationPpiGuid=gEfiPeiSmmCommunicationPpiGuid",
]
},

--
2.32.0.windows.1


[PATCH v1 1/3] MdePkg: MmCommunication: Added definition of MM Communication PPI

Kun Qin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629

MM Communication PPI was defined in PI Specification since v1.5. This
change added definition of such PPI and related GUIDs into MdePkg.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
---
MdePkg/Include/Ppi/MmCommunication.h | 72 ++++++++++++++++++++
MdePkg/MdePkg.dec | 3 +
2 files changed, 75 insertions(+)

diff --git a/MdePkg/Include/Ppi/MmCommunication.h b/MdePkg/Include/Ppi/MmCommunication.h
new file mode 100644
index 000000000000..7e06da2ec088
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmCommunication.h
@@ -0,0 +1,72 @@
+/** @file
+ EFI MM Communication PPI definition.
+
+ This PPI provides a means of communicating between drivers outside
+ of MM and MMI handlers inside of MM in PEI phase.
+
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef MM_COMMUNICATION_PPI_H_
+#define MM_COMMUNICATION_PPI_H_
+
+#define EFI_PEI_MM_COMMUNICATION_PPI_GUID \
+ { \
+ 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \
+ }
+
+typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI;
+
+/**
+ Communicates with a registered handler.
+
+ This function provides a service to send and receive messages from a registered PEI service.
+ The EFI_PEI_MM_COMMUNICATION_PPI driver is responsible for doing any of the copies such that
+ the data lives in PEI-service-accessible RAM.
+
+ A given implementation of the EFI_PEI_MM_COMMUNICATION_PPI may choose to use the
+ EFI_MM_CONTROL_PPI for effecting the mode transition, or it may use some other method.
+
+ The agent invoking the communication interface must be physical/virtually 1:1 mapped.
+
+ To avoid confusion in interpreting frames, the CommBuffer parameter should always begin with
+ EFI_MM_COMMUNICATE_HEADER. The header data is mandatory for messages sent into the MM agent.
+
+ Once inside of MM, the MM infrastructure will call all registered handlers with the same
+ HandlerType as the GUID specified by HeaderGuid and the CommBuffer pointing to Data.
+
+ This function is not reentrant.
+
+ @param[in] This The EFI_PEI_MM_COMMUNICATION_PPI instance.
+ @param[in] CommBuffer Pointer to the buffer to convey into MMRAM.
+ @param[in] CommSize The size of the data buffer being passed in. On exit, the
+ size of data being returned. Zero if the handler does not
+ wish to reply with any data.
+
+ @retval EFI_SUCCESS The message was successfully posted.
+ @retval EFI_INVALID_PARAMETER The buffer was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_COMMUNICATE)(
+ IN CONST EFI_PEI_MM_COMMUNICATION_PPI *This,
+ IN OUT VOID *CommBuffer,
+ IN OUT UINTN *CommSize
+ );
+
+///
+/// EFI MM Communication PPI provides services for communicating between PEIM and a registered
+/// MMI handler.
+///
+struct _EFI_PEI_MM_COMMUNICATION_PPI {
+ EFI_PEI_MM_COMMUNICATE Communicate;
+};
+
+extern EFI_GUID gEfiPeiMmCommunicationPpiGuid;
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index a28a2daaffa8..9cdc915ebae9 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -991,6 +991,9 @@ [Ppis]
## Include/Ppi/MmConfiguration.h
gEfiPeiMmConfigurationPpi = { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } }

+ ## Include/Ppi/MmCommunication.h
+ gEfiPeiMmCommunicationPpiGuid = { 0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } }
+
#
# PPIs defined in PI 1.7.
#
--
2.32.0.windows.1


[PATCH v1 0/3] Add MM Communication PPI definition to MdePkg

Kun Qin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3629

EFI_PEI_MM_COMMUNICATION_PPI is defined since PI spec v1.5. This patch
series added the interface definition and related GUIDs into MdePkg.

Given gEfiPeiSmmCommunicationPpiGuid and gEfiPeiMmCommunicationPpiGuid
have the same value, CI build files are also updated accordingly to avoid
build failure caused by duplicate GUIDs.

Patch v1 branch: https://github.com/kuqin12/edk2/tree/mm_communicate_ppi

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Jian J Wang <jian.j.wang@intel.com>

Kun Qin (3):
MdePkg: MmCommunication: Added definition of MM Communication PPI
MdePkg: CI YAML: Added new GUID to ignore duplicate list
MdeModulePkg: CI YAML: Added new GUID to ignore duplicate list

MdeModulePkg/MdeModulePkg.ci.yaml | 1 +
MdePkg/Include/Ppi/MmCommunication.h | 72 ++++++++++++++++++++
MdePkg/MdePkg.ci.yaml | 3 +-
MdePkg/MdePkg.dec | 3 +
4 files changed, 78 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/Ppi/MmCommunication.h

--
2.32.0.windows.1


[edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Oram, Isaac W
 

Add PlatformSecLib
so that we can build SecCore.
This uses FSP TempRamInit API in dispatch mode, but directly
tears down NEM as a workaround because the current FSP binaries
do not properly produce the TEMP_RAM_EXIT_PPI.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c | 159 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm | 124 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm | 338 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm | 71 ++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 103 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c | 90 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 29 ++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c | 130 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 30 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 30 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 2 -
14 files changed, 1248 insertions(+), 28 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
new file mode 100644
index 0000000000..5e0f2ff1ac
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
@@ -0,0 +1,159 @@
+/** @file
+ Sample to provide FSP wrapper platform sec related function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+#include <Ppi/PeiCoreFvLocation.h>
+
+#include <Library/LocalApicLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
+ SecGetPerformance
+};
+
+EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
+ (VOID *) (UINTN) FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiPeiCoreFvLocationPpiGuid,
+ &mPeiCoreFvLocationPpi
+ }
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
+ //
+ // This must be the first PPI in the list because it will be patched in SecPlatformMain ();
+ //
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gTopOfTemporaryRamPpiGuid,
+ NULL
+ }
+};
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param[in,out] SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ )
+{
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINT8 TopOfTemporaryRamPpiIndex;
+ UINT8 *CopyDestinationPointer;
+ UINTN ReservedSize;
+
+ DEBUG((DEBUG_INFO, "SecPlatformMain\n"));
+
+ ReservedSize = ALIGN_VALUE (PcdGet32 (PcdPeiTemporaryRamRcHeapSize), SIZE_4KB);
+ ReservedSize += ALIGN_VALUE (PcdGet32 (PcdFspTemporaryRamSize), SIZE_4KB);
+
+ SecCoreData->PeiTemporaryRamBase = (UINT8 *) SecCoreData->PeiTemporaryRamBase + ReservedSize;
+ SecCoreData->PeiTemporaryRamSize -= ReservedSize;
+
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
+
+ InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
+
+ //
+ // Use middle of Heap as temp buffer, it will be copied by caller.
+ // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
+ //
+ PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
+ CopyDestinationPointer = (UINT8 *) PpiList;
+ TopOfTemporaryRamPpiIndex = 0;
+ if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool (PcdFspDispatchModeUseFspPeiMain)) {
+ //
+ // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
+ //
+ CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
+ TopOfTemporaryRamPpiIndex = 1;
+ CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
+ }
+ CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof (mPeiSecPlatformPpi));
+ //
+ // Patch TopOfTemporaryRamPpi
+ //
+ PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
+
+ return PpiList;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
new file mode 100644
index 0000000000..0a8d9bf74a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
@@ -0,0 +1,43 @@
+/** @file
+ Fsp related definitions
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __FSP_H__
+#define __FSP_H__
+
+//
+// Fv Header
+//
+#define FVH_SIGINATURE_OFFSET 0x28
+#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
+#define FVH_HEADER_LENGTH_OFFSET 0x30
+#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
+#define FVH_EXTHEADER_SIZE_OFFSET 0x10
+
+//
+// Ffs Header
+//
+#define FSP_HEADER_GUID_DWORD1 0x912740BE
+#define FSP_HEADER_GUID_DWORD2 0x47342284
+#define FSP_HEADER_GUID_DWORD3 0xB08471B9
+#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
+#define FFS_HEADER_SIZE_VALUE 0x18
+
+//
+// Section Header
+//
+#define SECTION_HEADER_TYPE_OFFSET 0x03
+#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
+
+//
+// Fsp Header
+//
+#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
new file mode 100644
index 0000000000..917411cac2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
@@ -0,0 +1,124 @@
+;------------------------------------------------------------------------------
+; @file PeiCoreEntry.nasm
+; Find and call SecStartup
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+SECTION .text
+
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
+
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
+ ;
+ ; Obtain the hob list pointer
+ ;
+ mov eax, [esp+4]
+ ;
+ ; Obtain the stack information
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ecx, [esp+8]
+ mov edx, [esp+0xC]
+
+ ;
+ ; Platform init
+ ;
+ pushad
+ push edx
+ push ecx
+ push eax
+ call ASM_PFX(PlatformInit)
+ pop eax
+ pop eax
+ pop eax
+ popad
+
+ ;
+ ; Set stack top pointer
+ ;
+ mov esp, edx
+
+ ;
+ ; Push the hob list pointer
+ ;
+ push eax
+
+ ;
+ ; Save the value
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ebp, esp
+ push ecx
+ push edx
+
+ ;
+ ; Push processor count to stack first, then BIST status (AP then BSP)
+ ;
+ mov eax, 1
+ cpuid
+ shr ebx, 16
+ and ebx, 0xFF
+ cmp bl, 1
+ jae PushProcessorCount
+
+ ;
+ ; Some processors report 0 logical processors. Effectively 0 = 1.
+ ; So we fix up the processor count
+ ;
+ inc ebx
+
+PushProcessorCount:
+ push ebx
+
+ ;
+ ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
+ ; for all processor threads
+ ;
+ xor ecx, ecx
+ mov cl, bl
+PushBist:
+ movd eax, mm0
+ push eax
+ loop PushBist
+
+ ; Save Time-Stamp Counter
+ movd eax, mm5
+ push eax
+
+ movd eax, mm6
+ push eax
+
+ ;
+ ; Pass entry point of the PEI core
+ ;
+ mov edi, 0xFFFFFFE0
+ push DWORD [edi]
+
+ ;
+ ; Pass BFV into the PEI Core
+ ;
+ mov edi, 0xFFFFFFFC
+ push DWORD [edi]
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ mov ecx, [ebp - 4]
+ mov edx, [ebp - 8]
+ push ecx ; RamBase
+
+ sub edx, ecx
+ push edx ; RamSize
+
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ call ASM_PFX(SecStartup)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
new file mode 100644
index 0000000000..091990d627
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -0,0 +1,338 @@
+;------------------------------------------------------------------------------
+; @file SecEntry.nasm
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+#include "Fsp.h"
+
+SECTION .text
+
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+extern ASM_PFX(BoardBeforeTempRamInit)
+
+; Pcds
+extern ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))
+
+;----------------------------------------------------------------------------
+;
+; Procedure: _ModuleEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; Transition to non-paged flat-model protected mode from a
+; hard-coded GDT that provides exactly two descriptors.
+; This is a bare bones transition to protected mode only
+; used for a while in PEI and possibly DXE.
+;
+; After enabling protected mode, a far jump is executed to
+; transfer to PEI using the newly loaded GDT.
+;
+; Return: None
+;
+; MMX Usage:
+; MM0 = BIST State
+; MM5 = Save time-stamp counter value high32bit
+; MM6 = Save time-stamp counter value low32bit.
+;
+;----------------------------------------------------------------------------
+
+BITS 16
+align 4
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+ fninit ; clear any pending Floating point exceptions
+ ;
+ ; Store the BIST value in mm0
+ ;
+ movd mm0, eax
+
+ ;
+ ; Save time-stamp counter value
+ ; rdtsc load 64bit time-stamp counter to EDX:EAX
+ ;
+ rdtsc
+ movd mm5, edx
+ movd mm6, eax
+
+ ;
+ ; Load the GDT table in GdtDesc
+ ;
+ mov esi, GdtDesc
+ DB 66h
+ lgdt [cs:si]
+
+ ;
+ ; Transition to 16 bit protected mode
+ ;
+ mov eax, cr0 ; Get control register 0
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
+ mov cr0, eax ; Activate protected mode
+
+ mov eax, cr4 ; Get control register 4
+ or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
+ mov cr4, eax
+
+ ;
+ ; Now we're in 16 bit protected mode
+ ; Set up the selectors for 32 bit protected mode entry
+ ;
+ mov ax, SYS_DATA_SEL
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ ;
+ ; Transition to Flat 32 bit protected mode
+ ; The jump to a far pointer causes the transition to 32 bit mode
+ ;
+ mov esi, ProtectedModeEntryLinearAddress
+ jmp dword far [cs:si]
+
+;----------------------------------------------------------------------------
+;
+; Procedure: ProtectedModeEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; This function handles:
+; Call two basic APIs from FSP binary
+; Initializes stack with some early data (BIST, PEI entry, etc)
+;
+; Return: None
+;
+;----------------------------------------------------------------------------
+
+BITS 32
+align 4
+ProtectedModeEntryPoint:
+ ;
+ ; Early board hooks
+ ;
+ mov esp, BoardBeforeTempRamInitRet
+ jmp ASM_PFX(BoardBeforeTempRamInit)
+
+BoardBeforeTempRamInitRet:
+
+ ; Find the fsp info header
+ mov edi, [ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))]
+
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
+ cmp eax, FVH_SIGINATURE_VALID_VALUE
+ jnz FspHeaderNotFound
+
+ xor eax, eax
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ cmp ax, 0
+ jnz FspFvExtHeaderExist
+
+ xor eax, eax
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ add edi, eax
+ jmp FspCheckFfsHeader
+
+FspFvExtHeaderExist:
+ add edi, eax
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
+ add edi, eax
+
+ ; Round up to 8 byte alignment
+ mov eax, edi
+ and al, 07h
+ jz FspCheckFfsHeader
+
+ and edi, 0FFFFFFF8h
+ add edi, 08h
+
+FspCheckFfsHeader:
+ ; Check the ffs guid
+ mov eax, dword [edi]
+ cmp eax, FSP_HEADER_GUID_DWORD1
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 4]
+ cmp eax, FSP_HEADER_GUID_DWORD2
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 8]
+ cmp eax, FSP_HEADER_GUID_DWORD3
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 0Ch]
+ cmp eax, FSP_HEADER_GUID_DWORD4
+ jnz FspHeaderNotFound
+
+ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
+
+ ; Check the section type as raw section
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
+ cmp al, 019h
+ jnz FspHeaderNotFound
+
+ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
+ jmp FspHeaderFound
+
+FspHeaderNotFound:
+ jmp $
+
+FspHeaderFound:
+ ; Get the fsp TempRamInit Api address
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
+ add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+
+ ; Setup the hardcode stack
+ mov esp, TempRamInitStack
+
+ ; Call the fsp TempRamInit Api
+ jmp eax
+
+TempRamInitDone:
+ cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
+ je CallSecFspInit ;If microcode not found, don't hang, but continue.
+
+ cmp eax, 0 ;Check if EFI_SUCCESS retuned.
+ jnz FspApiFailed
+
+ ; ECX: start of range
+ ; EDX: end of range
+CallSecFspInit:
+ xor eax, eax
+ mov esp, edx
+
+ ; Align the stack at DWORD
+ add esp, 3
+ and esp, 0FFFFFFFCh
+
+ push edx
+ push ecx
+ push eax ; zero - no hob list yet
+ call ASM_PFX(CallPeiCoreEntryPoint)
+
+FspApiFailed:
+ jmp $
+
+align 10h
+TempRamInitStack:
+ DD TempRamInitDone
+ DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
+
+;
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase
+;
+align 16
+global ASM_PFX(BootGdtTable)
+
+;
+; GDT[0]: 0x00: Null entry, never used.
+;
+NULL_SEL EQU $ - GDT_BASE ; Selector [0]
+GDT_BASE:
+ASM_PFX(BootGdtTable):
+ DD 0
+ DD 0
+;
+; Linear data segment descriptor
+;
+LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 092h ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Linear code segment descriptor
+;
+LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; System data segment descriptor
+;
+SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+
+;
+; System code segment descriptor
+;
+SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Ah ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0Eh ; Changed from F000 to E000.
+ DB 09Bh ; present, ring 0, code, expand-up, writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
+ DW 0FFFFh ; limit 0xFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+
+;
+; Spare segment descriptor
+;
+SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
+ DW 0 ; limit 0
+ DW 0 ; base 0
+ DB 0
+ DB 0 ; present, ring 0, data, expand-up, writable
+ DB 0 ; page-granular, 32-bit
+ DB 0
+GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
+
+;
+; GDT Descriptor
+;
+GdtDesc: ; GDT descriptor
+ DW GDT_SIZE - 1 ; GDT limit
+ DD GDT_BASE ; GDT base address
+
+
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+ DD ProtectedModeEntryPoint ; Offset of our 32 bit code
+ DW LINEAR_CODE_SEL
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
new file mode 100644
index 0000000000..80a7a67ecf
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
@@ -0,0 +1,71 @@
+;------------------------------------------------------------------------------
+; @file Stack.nasm
+; Switch the stack from temporary memory to permenent memory.
+;
+; @copyright
+; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SecSwitchStack (
+; UINT32 TemporaryMemoryBase,
+; UINT32 PermanentMemoryBase
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
+ ;
+ ; Save three register: eax, ebx, ecx
+ ;
+ push eax
+ push ebx
+ push ecx
+ push edx
+
+ ;
+ ; !!CAUTION!! this function address's is pushed into stack after
+ ; migration of whole temporary memory, so need save it to permanent
+ ; memory at first!
+ ;
+
+ mov ebx, [esp + 20] ; Save the first parameter
+ mov ecx, [esp + 24] ; Save the second parameter
+
+ ;
+ ; Save this function's return address into permanent memory at first.
+ ; Then, Fixup the esp point to permanent memory
+ ;
+ mov eax, esp
+ sub eax, ebx
+ add eax, ecx
+ mov edx, dword [esp] ; copy pushed register's value to permanent memory
+ mov dword [eax], edx
+ mov edx, dword [esp + 4]
+ mov dword [eax + 4], edx
+ mov edx, dword [esp + 8]
+ mov dword [eax + 8], edx
+ mov edx, dword [esp + 12]
+ mov dword [eax + 12], edx
+ mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
+ mov dword [eax + 16], edx
+ mov esp, eax ; From now, esp is pointed to permanent memory
+
+ ;
+ ; Fixup the ebp point to permanent memory
+ ;
+ mov eax, ebp
+ sub eax, ebx
+ add eax, ecx
+ mov ebp, eax ; From now, ebp is pointed to permanent memory
+
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ ret
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
new file mode 100644
index 0000000000..546b13f8a3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
@@ -0,0 +1,48 @@
+/** @file
+ Sample to provide platform init function.
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/SecBoardInitLib.h>
+#include <Library/TestPointCheckLib.h>
+
+/**
+ Platform initialization.
+
+ @param[in] FspHobList HobList produced by FSP.
+ @param[in] StartOfRange Start of temporary RAM.
+ @param[in] EndOfRange End of temporary RAM.
+**/
+VOID
+EFIAPI
+PlatformInit (
+ IN VOID *FspHobList,
+ IN VOID *StartOfRange,
+ IN VOID *EndOfRange
+ )
+{
+ //
+ // Platform initialization
+ // Enable Serial port here
+ //
+ if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
+ SerialPortInitialize ();
+ }
+
+ DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
+ DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
+ DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
+ DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
+
+ BoardAfterTempRamInit ();
+
+ TestPointTempMemoryFunction (StartOfRange, EndOfRange);
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
new file mode 100644
index 0000000000..37e0a5cb63
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -0,0 +1,103 @@
+## @file
+# Provide FSP wrapper platform sec related function.
+#
+# @copyright
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SecFspWrapperPlatformSecLib
+ FILE_GUID = 8F1AC44A-CE7E-4E29-95BB-92E321BB1573
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ FspWrapperPlatformSecLib.c
+ SecRamInitData.c
+ SecPlatformInformation.c
+ SecGetPerformance.c
+ SecTempRamDone.c
+ PlatformInit.c
+
+[Sources.IA32]
+ Ia32/SecEntry.nasm
+ Ia32/PeiCoreEntry.nasm
+ Ia32/Stack.nasm
+ Ia32/Fsp.h
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhitleyFspBinPkg/WhitleyFspBinPkg.dec
+
+[LibraryClasses]
+ LocalApicLib
+ SerialPortLib
+ DebugLib
+ BaseMemoryLib
+ FspWrapperPlatformLib
+ FspWrapperApiLib
+ SecBoardInitLib
+ TestPointCheckLib
+ PeiServicesTablePointerLib
+
+[Ppis]
+ gEfiSecPlatformInformationPpiGuid ## CONSUMES
+ gPeiSecPerformancePpiGuid ## CONSUMES
+ gTopOfTemporaryRamPpiGuid ## PRODUCES
+ gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
+ gPlatformInitTempRamExitPpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
+
+[FixedPcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase ## CONSUMES
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSUMES
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
new file mode 100644
index 0000000000..977212737e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
@@ -0,0 +1,90 @@
+/** @file
+ Sample to provide SecGetPerformance function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPerformance.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ )
+{
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ UINT64 Ticker;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // |--------------| <- TopOfTemporaryRam - BL
+ // | List Ptr |
+ // |--------------|
+ // | BL RAM Start |
+ // |--------------|
+ // | BL RAM End |
+ // |--------------|
+ // |Number of BSPs|
+ // |--------------|
+ // | BIST |
+ // |--------------|
+ // | .... |
+ // |--------------|
+ // | TSC[63:32] |
+ // |--------------|
+ // | TSC[31:00] |
+ // |--------------|
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));
+ Size = Count * sizeof (UINT32);
+
+ Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
+ Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
new file mode 100644
index 0000000000..3d1b9be21c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
@@ -0,0 +1,79 @@
+/** @file
+ Sample to provide SecPlatformInformation function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ )
+{
+ UINT32 *Bist;
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // The entries of BIST information, together with the number of them,
+ // reside in the bottom of stack, left untouched by normal stack operation.
+ // This routine copies the BIST information to the buffer pointed by
+ // PlatformInformationRecord for output.
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);
+
+ if ((*StructureSize) < (UINT64) Size) {
+ *StructureSize = Size;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ *StructureSize = Size;
+ Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
+
+ CopyMem (PlatformInformationRecord, Bist, Size);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
new file mode 100644
index 0000000000..a6c7a53d33
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
@@ -0,0 +1,29 @@
+/** @file
+ Sample to provide TempRamInitParams data.
+
+ @copyright
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/PcdLib.h>
+#include <FspEas.h>
+#include <FsptUpd.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
+ {
+ FSPT_UPD_SIGNATURE,
+ 0x00,
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ },
+ {
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv),
+ FixedPcdGet32 (PcdFlashSecCacheRegionBase),
+ FixedPcdGet32 (PcdFlashSecCacheRegionSize),
+ }
+};
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
new file mode 100644
index 0000000000..e6f2c1c4d6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
@@ -0,0 +1,130 @@
+/** @file
+ Sample to provide SecTemporaryRamDone function.
+
+ @copyright
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/PlatformInitTempRamExitPpi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/FspWrapperPlatformLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+#include <Guid/FspHeaderFile.h>
+
+#include <Register/ArchitecturalMsr.h>
+
+#define MSR_NEM 0x000002E0
+
+/**
+This interface disables temporary memory in SEC Phase.
+This is for dispatch mode use. We should properly produce the FSP_TEMP_RAM_EXIT_PPI and then call
+that instead, but the FSP does not produce that PPI
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemoryDispatchHack (
+ VOID
+ )
+{
+ UINT64 MsrValue;
+ UINT64 MtrrDefaultType;
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+
+ //
+ // Force and INVD.
+ //
+ AsmInvd ();
+
+ //
+ // Disable MTRRs.
+ //
+ DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
+ MtrrDefaultType = DefType.Uint64;
+ DefType.Bits.E = 0;
+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
+
+ //
+ // Force and INVD to prevent MCA error.
+ //
+ AsmInvd ();
+
+ //
+ // Clear NEM Run and NEM Setup bits individually.
+ //
+ MsrValue = AsmReadMsr64 (MSR_NEM);
+ MsrValue &= ~((UINT64) BIT1);
+ AsmWriteMsr64 (MSR_NEM, MsrValue);
+ MsrValue &= ~((UINT64) BIT0);
+ AsmWriteMsr64 (MSR_NEM, MsrValue);
+
+ //
+ // Restore MTRR default setting
+ //
+ AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrDefaultType);
+}
+
+/**
+This interface disables temporary memory in SEC Phase.
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *TempRamExitParam;
+ CONST EFI_PEI_SERVICES **PeiServices;
+ PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
+ PeiServices = GetPeiServicesTablePointer ();
+ ASSERT (PeiServices != NULL);
+ if (PeiServices == NULL) {
+ return ;
+ }
+ ASSERT ((*PeiServices) != NULL);
+ if ((*PeiServices) == NULL) {
+ return;
+ }
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPlatformInitTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PlatformInitTempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
+ ASSERT_EFI_ERROR (Status);
+
+ if (PcdGet8 (PcdFspModeSelection) == 1) {
+ //
+ // FSP API mode
+ //
+ TempRamExitParam = UpdateTempRamExitParam ();
+ Status = CallTempRamExit (TempRamExitParam);
+ DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ SecPlatformDisableTemporaryMemoryDispatchHack ();
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
+ ASSERT_EFI_ERROR(Status);
+
+ return ;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index fa41ae923d..dc3dd0e026 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -48,6 +48,9 @@
#
!include $(SILICON_PKG)/MrcCommonConfig.dsc

+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
!include $(FSP_BIN_PKG)/DynamicExPcd.dsc
!include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
!include $(RP_PKG)/DynamicExPcd.dsc
@@ -192,8 +195,17 @@
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000

+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
!endif
gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000

@@ -310,6 +322,12 @@
!include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc

[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
!if ($(FSP_MODE) == 0)
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
@@ -543,12 +561,11 @@
VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf

[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
-!if ($(FSP_MODE) == 0)
FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
-!endif
+
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
@@ -559,6 +576,11 @@
#
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf

+ PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
+
[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
#
# ToDo: Can we remove
@@ -617,6 +639,8 @@
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
!include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc

MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
@@ -653,8 +677,8 @@
BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
}

-!if ($(FSP_MODE) == 0)
IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
$(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
!endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
index 927db9e210..d128f61b9d 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
@@ -14,7 +14,7 @@ DEFINE PLATFORM_PKG = MinPlatformPkg
# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060

-DEFINE MICROCODE_HEADER_SIZE = 0x00000090
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header

DEFINE VPD_HEADER_SIZE = 0x00000090

@@ -153,24 +153,12 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize

- #
- # For FSP Dispatch Mode, specify the FV containing the PEI core.
- #
- !if $(FSP_MODE) == 1
- #
- # Tell SEC to use PEI Core from outside FSP for additional debug message control.
- #
- SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
- !endif
-
#
# For API mode, wrappers have some duplicate PCD as well
#
- !if $(FSP_MODE) == 0
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
- SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
- !endif
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase

################################################################################
#
@@ -311,7 +299,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
#
# Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
#
- SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + $(MICROCODE_HEADER_SIZE)
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv

#
# FV Layout (You should not need to modify this section)
@@ -410,12 +399,7 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
!include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864

- FILE SEC = 1BA0062E-C779-4582-8566-336AE8F78F09 {
- SECTION UI = "SecCore"
- SECTION VERSION = "1.0"
- SECTION Align = 16 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/1BA0062E-C779-4582-8566-336AE8F78F09SecCore.efi
- SECTION Align = 16 RAW = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ResetVec.bin
- }
+ INF UefiCpuPkg/SecCore/SecCore.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf

INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index d7039f65c4..ea8fd0a49b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -905,8 +905,6 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported |FALSE|BOOLEAN|0xF0000030
gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault |FALSE|BOOLEAN|0xF0000031

- gSiPkgTokenSpaceGuid.PcdPeiCoreFv |0x00000000|UINT32|0xF0000032
-
gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033

#
--
2.27.0.windows.1


[edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables

Oram, Isaac W
 

Update to utilize the larger variables.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c | 83 +++++++-------------
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf | 12 +--
2 files changed, 35 insertions(+), 60 deletions(-)

diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
index 453e409523..a6196a78b0 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
@@ -10,76 +10,52 @@
#include <PiPei.h>
#include <Library/PeiServicesLib.h>
#include <Library/DebugLib.h>
-#include <FspmUpd.h>
-#include <Ppi/UpiPolicyPpi.h>
-#include <Guid/PlatformInfo.h>
#include <Library/HobLib.h>
-#include <Ppi/ReadOnlyVariable2.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/LargeVariableReadLib.h>
+
+#include <FspmUpd.h>
+#include <Guid/PlatformInfo.h>
+#include <Ppi/UpiPolicyPpi.h>

VOID *
-GetPlatformNvs(
+GetFspNvsBuffer (
+ VOID
)
{
EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
- VOID *DataBuffer;
- UINT32 DataBufferSize;
- UINTN VarAttrib;
- CHAR16 EfiMemoryConfigVariable[] = L"MemoryConfig";
+ UINTN FspNvsBufferSize;
+ VOID *FspNvsBufferPtr;

- DEBUG ((EFI_D_INFO, "Start PlatformGetNvs\n"));
-
- Status = PeiServicesLocatePpi (
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **) &PeiVariable
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: PeiServicesLocatePpi not found\n"));
+ FspNvsBufferPtr = NULL;
+ FspNvsBufferSize = 0;
+ Status = GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, NULL);
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ DEBUG ((DEBUG_INFO, "FspNvsBuffer Size = %d\n", FspNvsBufferSize));
+ FspNvsBufferPtr = AllocateZeroPool (FspNvsBufferSize);
+ if (FspNvsBufferPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Error: Cannot create FspNvsBuffer, out of memory!\n"));
ASSERT (FALSE);
return NULL;
}
-
- VarAttrib = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS;
- DataBufferSize = 0;
- DataBuffer = NULL;
-
- Status = PeiVariable->GetVariable (
- PeiVariable,
- EfiMemoryConfigVariable,
- &gFspNonVolatileStorageHobGuid,
- (UINT32*)&VarAttrib,
- &DataBufferSize,
- NULL
- );
- if (Status == EFI_NOT_FOUND) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variable not found\n"));
+ Status = GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, FspNvsBufferPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable Status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
return NULL;
}

- if (Status != EFI_BUFFER_TOO_SMALL) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Get Error %r\n", Status));
- ASSERT (FALSE);
+ return FspNvsBufferPtr;
+
+ } else if (Status == EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does not exist (this is likely a first boot)\n"));
+ } else {
+ DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable Status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
}

- DataBuffer = AllocateZeroPool(DataBufferSize);
- Status = PeiVariable->GetVariable (
- PeiVariable,
- EfiMemoryConfigVariable,
- &gFspNonVolatileStorageHobGuid,
- (UINT32*)&VarAttrib,
- &DataBufferSize,
- DataBuffer
- );
- if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variable Error %r\n", Status));
return NULL;
}
- DEBUG ((EFI_D_INFO, "PlatformGetNvs: GetNVS %x %x\n", DataBuffer, DataBufferSize));
- return DataBuffer;
-}

VOID
EFIAPI
@@ -164,11 +140,10 @@ UpdateFspmUpdData (
FspmUpd->FspmConfig.AllLanesSizeOfTable = Upi->AllLanesSizeOfTable;
FspmUpd->FspmConfig.PerLaneSizeOfTable = Upi->PerLaneSizeOfTable;
FspmUpd->FspmConfig.WaitTimeForPSBP = Upi->WaitTimeForPSBP;
- FspmUpd->FspmConfig.IsKtiNvramDataReady = Upi->IsKtiNvramDataReady;
FspmUpd->FspmConfig.WaSerializationEn = Upi->WaSerializationEn;
FspmUpd->FspmConfig.KtiInEnableMktme = Upi->KtiInEnableMktme;
FspmUpd->FspmConfig.BoardId = PlatformInfo->BoardId;
- FspmUpd->FspmArchUpd.NvsBufferPtr = GetPlatformNvs();
+ FspmUpd->FspmArchUpd.NvsBufferPtr = GetFspNvsBuffer ();
}

/**
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
index 625337c453..3e80ea670c 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
@@ -35,7 +35,6 @@
[Sources]
FspWrapperPlatformLib.c

-
################################################################################
#
# Package Dependency Section - list of Package files that are required for
@@ -47,11 +46,11 @@
MdePkg/MdePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- WhitleySiliconPkg/WhitleySiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
WhitleySiliconPkg/SiliconPkg.dec
WhitleySiliconPkg/CpRcPkg.dec
- WhitleyOpenBoardPkg/PlatformPkg.dec
- CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec # For LargeVariableReadLib
+ WhitleyFspBinPkg/WhitleyFspBinPkg.dec

[Ppis]
gUpiSiPolicyPpiGuid
@@ -63,9 +62,10 @@

[LibraryClasses]
PeiServicesLib
+ LargeVariableReadLib

[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSUMES
--
2.27.0.windows.1


[edk2-platforms][PATCH V1 0/2] Whitley SEC support

Oram, Isaac W
 

This series replaces the binary version of the SEC component with a buildable version.
The missing PlatformSecLib instance is implemented allowing the common SecCore component to be built. The resulting SecCore supports both Whitley and CedarIsland platforms in both API and Dispatch FSP modes though the WhitleyOpenBoardPkg does not currently support Whitley FSP API mode.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>

Isaac Oram (2):
WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables
WhitleyOpenBoardPkg/SecCore: Add SecCore source code support

Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c | 159 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm | 124 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm | 338 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm | 71 ++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 103 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c | 90 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c | 29 ++
Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c | 130 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 30 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 30 +-
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c | 83 ++---
Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf | 12 +-
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 2 -
16 files changed, 1283 insertions(+), 88 deletions(-)
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c

--
2.27.0.windows.1


Re: [PATCH v7 09/31] OvmfPkg/SecMain: register GHCB gpa for the SEV-SNP guest

Brijesh Singh
 

On 9/15/21 12:08 PM, Erdem Aktas wrote:
On Mon, Sep 13, 2021 at 9:20 PM Brijesh Singh <brijesh.singh@amd.com> wrote:
+*/
+STATIC
+VOID
+SevSnpGhcbRegister (
+ UINTN Address
+ )
+{
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+ MSR_SEV_ES_GHCB_REGISTER CurrentMsr;
+ EFI_PHYSICAL_ADDRESS GuestFrameNumber;
+
+ GuestFrameNumber = Address >> EFI_PAGE_SHIFT;
+
+ //
+ // Save the current MSR Value
+ //
+ CurrentMsr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
We are backing the current MSR value but when was it initialized
before ? Also is not this function supposed to set the Address as the
GHCB address? If it is, do we care about the old value?
Good point, there is no reason to read and restore the old GHCB, I will remove it in next version. The function does not set this as a GHCB address, it send request to hypervisor saying that it would like to use this address. If hypervisor is not okay with the address then it may recommend something else. We don't support working with the hypervisor preferred address. Setting the GHCB address code is common between Snp and Es but checking with hypervisor whether its okay to use is new in the GHCBv2 and is SNP specific.



+ // Restore the MSR
+ //
+ AsmWriteMsr64 (MSR_SEV_ES_GHCB, CurrentMsr.GhcbPhysicalAddress);
Why are we restoring the old value? I may have misunderstood but I
thought this function will set Address as the new GHCB address?
Thanks
-Erdem


Re: [edk2-libc Patch 1/1] AppPkg/Applications/Python/Python3.6.8: add support for atexit builtin module in py 3.6.8

Rebecca Cran
 

Reviewed-by: Rebecca Cran <rebecca@nuviainc.com>


Pushed as 60added7a61075607080ff718d7fa5e764a37044.


--
Rebecca Cran

On 9/14/21 9:28 AM, Jayaprakash, N wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3626

This commit adds support for the atexit a builtin module
in standard python 3.6.8 to it's UEFI port. There are tools
like Chipsec which are dependent on it but it can be used by
other python scripts running on UEFI shell with the help of
py 3.6.8 interpreter. Tested the changes on IA32 and X64 emulators
and it is working good.

Cc: Rebecca Cran <rebecca@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jayaprakash N <n.jayaprakash@intel.com>
---
AppPkg/Applications/Python/Python-3.6.8/Py368ReadMe.txt | 1 +
.../Python/Python-3.6.8/PyMod-3.6.8/Modules/config.c | 2 ++
AppPkg/Applications/Python/Python-3.6.8/Python368.inf | 1 +
3 files changed, 4 insertions(+)

diff --git a/AppPkg/Applications/Python/Python-3.6.8/Py368ReadMe.txt b/AppPkg/Applications/Python/Python-3.6.8/Py368ReadMe.txt
index 69bb6bd..fb81228 100644
--- a/AppPkg/Applications/Python/Python-3.6.8/Py368ReadMe.txt
+++ b/AppPkg/Applications/Python/Python-3.6.8/Py368ReadMe.txt
@@ -175,6 +175,7 @@ system as follows:
_symtable Modules/symtablemodule.c
_weakref Modules/_weakref.c
array Modules/arraymodule.c
+ atexit Modules/atexitmodule.c
binascii Modules/binascii.c
cmath Modules/cmathmodule.c
datetime Modules/_datetimemodule.c
diff --git a/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/config.c b/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/config.c
index 4b1eb0f..5ee42d8 100644
--- a/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/config.c
+++ b/AppPkg/Applications/Python/Python-3.6.8/PyMod-3.6.8/Modules/config.c
@@ -65,6 +65,7 @@ extern PyObject* PyInit__weakref(void);
extern PyObject* init_winreg(void);
extern PyObject* PyInit_zlib(void);
extern PyObject* initbz2(void);
+extern PyObject* PyInit_atexit(void);
extern PyObject* PyMarshal_Init(void);
extern PyObject* _PyWarnings_Init(void);
@@ -111,6 +112,7 @@ struct _inittab _PyImport_Inittab[] = {
{"gc", PyInit_gc},
{"math", PyInit_math},
{"array", PyInit_array},
+ {"atexit", PyInit_atexit},
{"_datetime", PyInit__datetime},
{"parser", PyInit_parser},
{"pyexpat", PyInit_pyexpat},
diff --git a/AppPkg/Applications/Python/Python-3.6.8/Python368.inf b/AppPkg/Applications/Python/Python-3.6.8/Python368.inf
index d2e6e73..b98b4a7 100644
--- a/AppPkg/Applications/Python/Python-3.6.8/Python368.inf
+++ b/AppPkg/Applications/Python/Python-3.6.8/Python368.inf
@@ -215,6 +215,7 @@
Modules/_io/iobase.c #
Modules/_io/stringio.c #
Modules/_io/textio.c #
+ Modules/atexitmodule.c #
#Modules/cjkcodecs
Modules/cjkcodecs/multibytecodec.c #


Re: [PATCH v7 09/31] OvmfPkg/SecMain: register GHCB gpa for the SEV-SNP guest

Erdem Aktas
 

On Mon, Sep 13, 2021 at 9:20 PM Brijesh Singh <brijesh.singh@amd.com> wrote:
+*/
+STATIC
+VOID
+SevSnpGhcbRegister (
+ UINTN Address
+ )
+{
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+ MSR_SEV_ES_GHCB_REGISTER CurrentMsr;
+ EFI_PHYSICAL_ADDRESS GuestFrameNumber;
+
+ GuestFrameNumber = Address >> EFI_PAGE_SHIFT;
+
+ //
+ // Save the current MSR Value
+ //
+ CurrentMsr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
We are backing the current MSR value but when was it initialized
before ? Also is not this function supposed to set the Address as the
GHCB address? If it is, do we care about the old value?


+ // Restore the MSR
+ //
+ AsmWriteMsr64 (MSR_SEV_ES_GHCB, CurrentMsr.GhcbPhysicalAddress);
Why are we restoring the old value? I may have misunderstood but I
thought this function will set Address as the new GHCB address?

Thanks
-Erdem

4961 - 4980 of 85635