Date   

[PATCH v3 27/28] AmpereAltraPkg: Add configuration screen for Watchdog timer

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

There are secure and non-secure watchdog timers supported in the Mt.
Jade system. They are used to monitor the system booting like system
firmware, UEFI, and OS. The system will be reset if the timer expires.
So, this patch adds the configuration screen for the watchdog timer
which provides options to configure the timeout of these timers.

By default, the values of these options are 5 minutes.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 3 +
Platform/Ampere/JadePkg/Jade.dsc | 1 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf | 50 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.h | 82 ++++
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigNVDataStruct.h | 27 ++
Silicon/Ampere/AmpereAltraPkg/Include/Guid/WatchdogConfigHii.h | 19 +
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigVfr.vfr | 58 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.c | 460 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigStrings.uni | 26 ++
10 files changed, 727 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
index 196611d67280..b0e1f3ec6f2a 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
@@ -56,6 +56,9 @@ [Guids]
# GUID for the ACPI HII configuration form
gAcpiConfigFormSetGuid = { 0x0ceb6764, 0xd415, 0x4b01, { 0xa8, 0x43, 0xd1, 0x01, 0xbc, 0xb0, 0xd8, 0x29 } }

+ # GUID for the Watchdog HII configuration form
+ gWatchdogConfigFormSetGuid = { 0xC3F8EC6E, 0x95EE, 0x460C, { 0xA4, 0x8D, 0xEA, 0x54, 0x2F, 0xFF, 0x01, 0x61 } }
+
## NVParam MM GUID
gNVParamMmGuid = { 0xE4AC5024, 0x29BE, 0x4ADC, { 0x93, 0x36, 0x87, 0xB5, 0xA0, 0x76, 0x23, 0x2D } }

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index b5ac2547c8f8..b752ea3e5264 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -201,3 +201,4 @@ [Components.common]
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index e0d4b049f6bf..8f3df6ccf01b 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -359,5 +359,6 @@ [FV.FvMain]
INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf

!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf
new file mode 100644
index 000000000000..3ed37bfb15da
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.inf
@@ -0,0 +1,50 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = WatchdogConfigDxe
+ FILE_GUID = 135A0CA5-4851-4EF5-9E1A-C6E4610C39A9
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = WatchdogConfigInitialize
+
+[Sources.common]
+ WatchdogConfigNVDataStruct.h
+ WatchdogConfigVfr.vfr
+ WatchdogConfigStrings.uni
+ WatchdogConfigDxe.c
+ WatchdogConfigDxe.h
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DevicePathLib
+ HiiLib
+ NVParamLib
+ PrintLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gPlatformManagerFormsetGuid
+ gWatchdogConfigFormSetGuid
+
+[Protocols]
+ gEfiDevicePathProtocolGuid ## CONSUMES
+ gEfiHiiConfigRoutingProtocolGuid ## CONSUMES
+ gEfiHiiConfigAccessProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.h
new file mode 100644
index 000000000000..5f47531c538e
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.h
@@ -0,0 +1,82 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef WATCHDOG_CONFIG_DXE_H_
+#define WATCHDOG_CONFIG_DXE_H_
+
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NVParamLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <NVParamDef.h>
+#include <Protocol/HiiConfigAccess.h>
+#include <Protocol/HiiConfigRouting.h>
+
+#include "WatchdogConfigNVDataStruct.h"
+
+//
+// This is the generated IFR binary data for each formset defined in VFR.
+//
+extern UINT8 WatchdogConfigVfrBin[];
+
+//
+// This is the generated String package data for all .UNI files.
+//
+extern UINT8 WatchdogConfigDxeStrings[];
+
+#define WATCHDOG_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('W', 'D', 'T', 'C')
+
+typedef struct {
+ UINTN Signature;
+
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ WATCHDOG_CONFIG_VARSTORE_DATA Configuration;
+
+ //
+ // Consumed protocol
+ //
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Produced protocol
+ //
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+} WATCHDOG_CONFIG_PRIVATE_DATA;
+
+#define WATCHDOG_CONFIG_PRIVATE_FROM_THIS(a) CR (a, WATCHDOG_CONFIG_PRIVATE_DATA, ConfigAccess, WATCHDOG_CONFIG_PRIVATE_SIGNATURE)
+
+#pragma pack(1)
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+EFI_STATUS
+WatchdogConfigNvParamSet (
+ IN WATCHDOG_CONFIG_VARSTORE_DATA *VarStoreConfig
+ );
+
+EFI_STATUS
+WatchdogConfigNvParamGet (
+ OUT WATCHDOG_CONFIG_VARSTORE_DATA *VarStoreConfig
+ );
+
+#endif /* WATCHDOG_CONFIG_DXE_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigNVDataStruct.h
new file mode 100644
index 000000000000..470a2821ffe7
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigNVDataStruct.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef WATCHDOG_CONFIG_NV_DATA_STRUCT_H_
+#define WATCHDOG_CONFIG_NV_DATA_STRUCT_H_
+
+#include <Guid/WatchdogConfigHii.h>
+
+#define WATCHDOG_CONFIG_VARSTORE_ID 0x1234
+#define WATCHDOG_CONFIG_FORM_ID 0x1235
+
+#define NWDT_UEFI_DEFAULT_VALUE 300 // 5 minutes
+#define SWDT_DEFAULT_VALUE 300 // 5 minutes
+
+#pragma pack(1)
+typedef struct {
+ UINT32 WatchdogTimerUEFITimeout;
+ UINT32 SecureWatchdogTimerTimeout;
+} WATCHDOG_CONFIG_VARSTORE_DATA;
+#pragma pack()
+
+#endif /* WATCHDOG_CONFIG_NV_DATA_STRUCT_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/WatchdogConfigHii.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/WatchdogConfigHii.h
new file mode 100644
index 000000000000..16319d61a759
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/WatchdogConfigHii.h
@@ -0,0 +1,19 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef WATCHDOG_CONFIG_HII_H_
+#define WATCHDOG_CONFIG_HII_H_
+
+#define WATCHDOG_CONFIG_FORMSET_GUID \
+ { \
+ 0xC3F8EC6E, 0x95EE, 0x460C, { 0xA4, 0x8D, 0xEA, 0x54, 0x2F, 0xFF, 0x01, 0x61 } \
+ }
+
+extern EFI_GUID gWatchdogConfigFormSetGuid;
+
+#endif /* WATCHDOG_CONFIG_HII_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigVfr.vfr
new file mode 100644
index 000000000000..48f2aef227f6
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigVfr.vfr
@@ -0,0 +1,58 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "WatchdogConfigNVDataStruct.h"
+
+formset
+ guid = WATCHDOG_CONFIG_FORMSET_GUID,
+ title = STRING_TOKEN(STR_WATCHDOG_CONFIG_FORM),
+ help = STRING_TOKEN(STR_WATCHDOG_CONFIG_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ //
+ // Define a variable Storage
+ //
+ varstore WATCHDOG_CONFIG_VARSTORE_DATA,
+ varid = WATCHDOG_CONFIG_VARSTORE_ID,
+ name = WatchdogConfigNVData,
+ guid = WATCHDOG_CONFIG_FORMSET_GUID;
+
+ form
+ formid = WATCHDOG_CONFIG_FORM_ID,
+ title = STRING_TOKEN(STR_WATCHDOG_CONFIG_FORM);
+ subtitle text = STRING_TOKEN(STR_WATCHDOG_CONFIG_FORM_HELP);
+
+ oneof varid = WatchdogConfigNVData.WatchdogTimerUEFITimeout,
+ prompt = STRING_TOKEN(STR_NWDT_TIMEOUT_UEFI),
+ help = STRING_TOKEN(STR_NWDT_TIMEOUT_UEFI_HELP),
+ flags = RESET_REQUIRED,
+ option text = STRING_TOKEN (STR_WDT_TIME_DISABLE), value = 0, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_5MIN), value = 300, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_6MIN), value = 360, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_10MIN), value = 600, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_15MIN), value = 900, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_20MIN), value = 1200, flags = 0;
+ default = NWDT_UEFI_DEFAULT_VALUE,
+ endoneof;
+
+ oneof varid = WatchdogConfigNVData.SecureWatchdogTimerTimeout,
+ prompt = STRING_TOKEN(STR_SWDT_TIMEOUT),
+ help = STRING_TOKEN(STR_SWDT_TIMEOUT_HELP),
+ flags = RESET_REQUIRED,
+ option text = STRING_TOKEN (STR_WDT_TIME_DISABLE), value = 0, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_5MIN), value = 300, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_6MIN), value = 360, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_10MIN), value = 600, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_15MIN), value = 900, flags = 0;
+ option text = STRING_TOKEN (STR_WDT_TIME_20MIN), value = 1200, flags = 0;
+ default = SWDT_DEFAULT_VALUE,
+ endoneof;
+
+ endform;
+
+endformset;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.c
new file mode 100644
index 000000000000..bd7b929dccda
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigDxe.c
@@ -0,0 +1,460 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "WatchdogConfigDxe.h"
+
+CHAR16 WatchDogConfigVarstoreDataName[] = L"WatchdogConfigNVData";
+
+EFI_HANDLE mDriverHandle = NULL;
+WATCHDOG_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+
+HII_VENDOR_DEVICE_PATH mWatchdogConfigHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ WATCHDOG_CONFIG_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+EFI_STATUS
+WatchdogConfigNvParamGet (
+ OUT WATCHDOG_CONFIG_VARSTORE_DATA *VarStoreConfig
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+ BOOLEAN SetDefault;
+
+ SetDefault = FALSE;
+ Status = NVParamGet (
+ NV_SI_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->WatchdogTimerUEFITimeout = NWDT_UEFI_DEFAULT_VALUE;
+ if (Status == EFI_NOT_FOUND) {
+ SetDefault = TRUE;
+ } else {
+ ASSERT (FALSE);
+ }
+ } else {
+ VarStoreConfig->WatchdogTimerUEFITimeout = Value * 60;
+ }
+
+ Status = NVParamGet (
+ NV_SI_SEC_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->SecureWatchdogTimerTimeout = SWDT_DEFAULT_VALUE;
+ if (Status == EFI_NOT_FOUND) {
+ SetDefault = TRUE;
+ } else {
+ ASSERT (FALSE);
+ }
+ } else {
+ VarStoreConfig->SecureWatchdogTimerTimeout = Value;
+ }
+
+ if (SetDefault) {
+ WatchdogConfigNvParamSet (VarStoreConfig);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+WatchdogConfigNvParamSet (
+ IN WATCHDOG_CONFIG_VARSTORE_DATA *VarStoreConfig
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ Status = NVParamGet (
+ NV_SI_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)
+ || Value != (VarStoreConfig->WatchdogTimerUEFITimeout / 60))
+ {
+ Status = NVParamSet (
+ NV_SI_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ (VarStoreConfig->WatchdogTimerUEFITimeout / 60)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ Status = NVParamGet (
+ NV_SI_SEC_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)
+ || Value != VarStoreConfig->SecureWatchdogTimerTimeout)
+ {
+ Status = NVParamSet (
+ NV_SI_SEC_WDT_BIOS_EXP_MINS,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ VarStoreConfig->SecureWatchdogTimerTimeout
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function allows a caller to extract the current configuration for one
+ or more named elements from the target driver.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Request A null-terminated Unicode string in
+ <ConfigRequest> format.
+ @param Progress On return, points to a character in the Request
+ string. Points to the string's null terminator if
+ request was successful. Points to the most recent
+ '&' before the first failing name/value pair (or
+ the beginning of the string if the failure is in
+ the first name/value pair) if the request was not
+ successful.
+ @param Results A null-terminated Unicode string in
+ <ConfigAltResp> format which has all values filled
+ in for the names in the Request string. String to
+ be allocated by the called function.
+
+ @retval EFI_SUCCESS The Results is filled with the requested values.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results.
+ @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogConfigExtractConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ WATCHDOG_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if (Progress == NULL || Results == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
+
+ if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &gWatchdogConfigFormSetGuid, WatchDogConfigVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ PrivateData = WATCHDOG_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+
+ //
+ // Get current setting from NVParam.
+ //
+ Status = WatchdogConfigNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ BufferSize = sizeof (WATCHDOG_CONFIG_VARSTORE_DATA);
+ ConfigRequest = Request;
+ if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
+ //
+ // Request has no request element, construct full request string.
+ // Allocate and fill a buffer large enough to hold the <ConfigHdr> template
+ // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (&gWatchdogConfigFormSetGuid, WatchDogConfigVarstoreDataName, PrivateData->DriverHandle);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ if (ConfigRequest == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
+ FreePool (ConfigRequestHdr);
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ Status = HiiConfigRouting->BlockToConfig (
+ HiiConfigRouting,
+ ConfigRequest,
+ (UINT8 *)&PrivateData->Configuration,
+ BufferSize,
+ Results,
+ Progress
+ );
+
+ //
+ // Free the allocated config request string.
+ //
+ if (AllocatedRequest) {
+ FreePool (ConfigRequest);
+ ConfigRequest = NULL;
+ }
+
+ //
+ // Set Progress string to the original request string.
+ //
+ if (Request == NULL) {
+ *Progress = NULL;
+ } else if (StrStr (Request, L"OFFSET") == NULL) {
+ *Progress = Request + StrLen (Request);
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Configuration A null-terminated Unicode string in <ConfigResp>
+ format.
+ @param Progress A pointer to a string filled in with the offset of
+ the most recent '&' before the first failing
+ name/value pair (or the beginning of the string if
+ the failure is in the first name/value pair) or
+ the terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The Results is processed successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogConfigRouteConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ WATCHDOG_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ if (Configuration == NULL || Progress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrivateData = WATCHDOG_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+ *Progress = Configuration;
+
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Configuration, &gWatchdogConfigFormSetGuid, WatchDogConfigVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Get configuration data from NVParam
+ //
+ Status = WatchdogConfigNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
+ //
+ BufferSize = sizeof (WATCHDOG_CONFIG_VARSTORE_DATA);
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Store configuration data back to NVParam
+ //
+ Status = WatchdogConfigNvParamSet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogConfigCallback (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+{
+ if (Action != EFI_BROWSER_ACTION_CHANGING) {
+ //
+ // Do nothing for other UEFI Action. Only do call back when data is changed.
+ //
+ return EFI_UNSUPPORTED;
+ }
+ if (((Value == NULL)
+ && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+WatchdogConfigInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Initialize driver private data
+ //
+ mPrivateData = AllocateZeroPool (sizeof (WATCHDOG_CONFIG_PRIVATE_DATA));
+ if (mPrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->Signature = WATCHDOG_CONFIG_PRIVATE_SIGNATURE;
+
+ mPrivateData->ConfigAccess.ExtractConfig = WatchdogConfigExtractConfig;
+ mPrivateData->ConfigAccess.RouteConfig = WatchdogConfigRouteConfig;
+ mPrivateData->ConfigAccess.Callback = WatchdogConfigCallback;
+
+ //
+ // Locate ConfigRouting protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID **)&HiiConfigRouting);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mPrivateData->HiiConfigRouting = HiiConfigRouting;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mWatchdogConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mPrivateData->DriverHandle = mDriverHandle;
+
+ //
+ // Publish our HII data
+ //
+ HiiHandle = HiiAddPackages (
+ &gWatchdogConfigFormSetGuid,
+ mDriverHandle,
+ WatchdogConfigDxeStrings,
+ WatchdogConfigVfrBin,
+ NULL
+ );
+ if (HiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mWatchdogConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->HiiHandle = HiiHandle;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigStrings.uni
new file mode 100644
index 000000000000..1d0f820e456f
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/WatchdogConfigDxe/WatchdogConfigStrings.uni
@@ -0,0 +1,26 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English"
+
+#string STR_WATCHDOG_CONFIG_FORM #language en-US "Watchdog Configuration"
+#string STR_WATCHDOG_CONFIG_FORM_HELP #language en-US "Watchdog Configuration"
+
+#string STR_WDT_TIME_DISABLE #language en-US "Disabled"
+#string STR_WDT_TIME_3MIN #language en-US "3 minutes"
+#string STR_WDT_TIME_4MIN #language en-US "4 minutes"
+#string STR_WDT_TIME_5MIN #language en-US "5 minutes"
+#string STR_WDT_TIME_6MIN #language en-US "6 minutes"
+#string STR_WDT_TIME_10MIN #language en-US "10 minutes"
+#string STR_WDT_TIME_15MIN #language en-US "15 minutes"
+#string STR_WDT_TIME_20MIN #language en-US "20 minutes"
+
+#string STR_NWDT_TIMEOUT_OS #language en-US "OS Watchdog Timeout"
+#string STR_NWDT_TIMEOUT_OS_HELP #language en-US "Timeout when boot OS."
+#string STR_NWDT_TIMEOUT_UEFI #language en-US "UEFI Watchdog Timeout"
+#string STR_NWDT_TIMEOUT_UEFI_HELP #language en-US "Timeout when boot UEFI"
+#string STR_SWDT_TIMEOUT #language en-US "Secure Watchdog Timeout"
+#string STR_SWDT_TIMEOUT_HELP #language en-US "Timeout when SCP will reset system if it doesn't receive response from ARMv8."
--
2.17.1


[PATCH v3 23/28] AmpereAltraPkg: Add configuration screen for memory

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Provide memory screen with below info:
* Memory total capacity
* Memory RAS and Performance Configuration
* Per DIMM Information

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Platform/Ampere/JadePkg/Jade.dsc | 1 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf | 59 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h | 170 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h | 47 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenVfr.vfr | 62 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c | 394 ++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c | 1325 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.uni | 9 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxeExtra.uni | 9 +
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenStrings.uni | 64 +
11 files changed, 2141 insertions(+)

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index f723be6997e6..5fc83745cdbc 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -197,3 +197,4 @@ [Components.common]
# HII
#
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index c54b46f95ad5..6fe023025034 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -355,5 +355,6 @@ [FV.FvMain]
# HII
#
INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf

!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
new file mode 100644
index 000000000000..fbb2ac9dad21
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
@@ -0,0 +1,59 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = MemInfoDxe
+ MODULE_UNI_FILE = MemInfoDxe.uni
+ FILE_GUID = D9EFCEFE-189B-4599-BB07-04F0A8DF5C2F
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = MemInfoScreenInitialize
+
+[Sources]
+ MemInfoNvramLib.c
+ MemInfoScreen.c
+ MemInfoScreen.h
+ MemInfoScreenStrings.uni
+ MemInfoScreenNVDataStruct.h
+ MemInfoScreenVfr.vfr
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ BaseLib
+ DevicePathLib
+ HiiLib
+ HobLib
+ MemoryAllocationLib
+ NVParamLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gEfiIfrTianoGuid ## PRODUCES ## UNDEFINED
+ gPlatformManagerFormsetGuid
+ gPlatformHobGuid
+
+[Protocols]
+ gEfiDevicePathProtocolGuid ## CONSUMES
+ gEfiHiiConfigRoutingProtocolGuid ## CONSUMES
+ gEfiHiiConfigAccessProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ MemInfoDxeExtra.uni
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h
new file mode 100644
index 000000000000..4b4b498062c8
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h
@@ -0,0 +1,170 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MEM_INFO_SCREEN_H_
+#define MEM_INFO_SCREEN_H_
+
+#include <Uefi.h>
+
+#include <Guid/MdeModuleHii.h>
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/HiiConfigAccess.h>
+#include <Protocol/HiiConfigKeyword.h>
+#include <Protocol/HiiConfigRouting.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/HiiString.h>
+
+#include "MemInfoScreenNVDataStruct.h"
+
+//
+// This is the generated IFR binary data for each formset defined in VFR.
+// This data array is ready to be used as input of HiiAddPackages() to
+// create a packagelist (which contains Form packages, String packages, etc).
+//
+extern UINT8 MemInfoScreenVfrBin[];
+
+//
+// This is the generated String package data for all .UNI files.
+// This data array is ready to be used as input of HiiAddPackages() to
+// create a packagelist (which contains Form packages, String packages, etc).
+//
+extern UINT8 MemInfoDxeStrings[];
+
+enum DDR_ECC_MODE {
+ ECC_DISABLE = 0,
+ ECC_SECDED,
+ SYMBOL_ECC
+};
+
+enum DDR_ERROR_CTRL_MODE_DE {
+ ERRCTLR_DE_DISABLE = 0,
+ ERRCTLR_DE_ENABLE,
+};
+
+enum DDR_ERROR_CTRL_MODE_FI {
+ ERRCTLR_FI_DISABLE = 0,
+ ERRCTLR_FI_ENABLE,
+};
+
+#define MEM_INFO_DDR_SPEED_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DDRSpeedSel)
+#define MEM_INFO_ECC_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, EccMode)
+#define MEM_INFO_ERR_CTRL_DE_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_DE)
+#define MEM_INFO_ERR_CTRL_FI_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_FI)
+#define MEM_INFO_ERR_SLAVE_32BIT_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Slave32bit)
+#define MEM_INFO_DDR_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ScrubPatrol)
+#define MEM_INFO_DDR_DEMAND_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DemandScrub)
+#define MEM_INFO_DDR_WRITE_CRC_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, WriteCrc)
+#define MEM_INFO_FGR_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, FGRMode)
+#define MEM_INFO_REFRESH2X_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Refresh2x)
+#define MEM_INFO_NVDIMM_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, NvdimmModeSel)
+
+#define MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('M', 'E', 'M', 'i')
+
+#define MEM_INFO_DDR_SPEED_SEL_QUESTION_ID 0x8001
+#define MEM_INFO_FORM_PERFORMANCE_QUESTION_ID 0x8002
+#define MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID 0x8003
+#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID 0x8004
+#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID 0x8005
+#define MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID 0x8006
+#define MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID 0x8007
+#define MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID 0x8008
+#define MEM_INFO_DDR_WRITE_CRC_QUESTION_ID 0x8009
+#define MEM_INFO_FGR_MODE_QUESTION_ID 0x800A
+#define MEM_INFO_REFRESH2X_MODE_QUESTION_ID 0x800B
+#define MEM_INFO_FORM_NVDIMM_QUESTION_ID 0x800C
+#define MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID 0x800D
+
+#define MAX_NUMBER_OF_HOURS_IN_A_DAY 24
+
+#define DDR_DEFAULT_SCRUB_PATROL_DURATION 24
+#define DDR_DEFAULT_DEMAND_SCRUB 1
+#define DDR_DEFAULT_WRITE_CRC 0
+#define DDR_DEFAULT_FGR_MODE 0
+#define DDR_DEFAULT_REFRESH2X_MODE 0
+#define DDR_DEFAULT_NVDIMM_MODE_SEL 3
+
+#define DDR_FGR_MODE_GET(Value) ((Value) & 0x3) /* Bit 0, 1 */
+#define DDR_FGR_MODE_SET(Dst, Src) do { Dst = (((Dst) & ~0x3) | ((Src) & 0x3)); } while (0)
+
+#define DDR_REFRESH_2X_GET(Value) ((Value) & 0x10000) >> 16 /* Bit 16 only */
+#define DDR_REFRESH_2X_SET(Dst, Src) do { Dst = (((Dst) & ~0x10000) | ((Src) & 0x1) << 16); } while (0)
+
+#define DDR_NVDIMM_MODE_SEL_MASK 0x7FFFFFFF
+#define DDR_NVDIMM_MODE_SEL_VALID_BIT BIT31
+
+typedef struct {
+ UINTN Signature;
+
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ MEM_INFO_VARSTORE_DATA VarStoreConfig;
+
+ //
+ // Consumed protocol
+ //
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
+ EFI_HII_STRING_PROTOCOL *HiiString;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
+ EFI_FORM_BROWSER2_PROTOCOL *FormBrowser2;
+
+ //
+ // Produced protocol
+ //
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+} MEM_INFO_SCREEN_PRIVATE_DATA;
+
+#define MEM_INFO_SCREEN_PRIVATE_FROM_THIS(a) CR (a, MEM_INFO_SCREEN_PRIVATE_DATA, ConfigAccess, MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE)
+
+#pragma pack(1)
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+EFI_STATUS
+MemInfoScreenInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+EFI_STATUS
+MemInfoScreenUnload (
+ IN EFI_HANDLE ImageHandle
+ );
+
+EFI_STATUS
+MemInfoNvparamGet (
+ OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ );
+
+EFI_STATUS
+MemInfoNvparamSet (
+ IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ );
+
+#endif /* MEM_INFO_SCREEN_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h
new file mode 100644
index 000000000000..75960c367880
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h
@@ -0,0 +1,47 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MEM_INFO_SCREEN_NV_DATA_STRUCT_H_
+#define MEM_INFO_SCREEN_NV_DATA_STRUCT_H_
+
+#define MEM_INFO_VARSTORE_NAME L"MemInfoIfrNVData"
+#define MEM_INFO_VARSTORE_ID 0x1234
+#define MEM_INFO_FORM_ID 0x1235
+#define MEM_INFO_FORM_PERFORMANCE_ID 0x1236
+#define MEM_INFO_FORM_NVDIMM_ID 0x1237
+#define MEM_INFO_FORM_SET_GUID { 0xd58338ee, 0xe9f7, 0x4d8d, { 0xa7, 0x08, 0xdf, 0xb2, 0xc6, 0x66, 0x1d, 0x61 } }
+#define MEM_INFO_FORM_SET_PERFORMANCE_GUID { 0x4a072c78, 0x42f9, 0x11ea, { 0xb7, 0x7f, 0x2e, 0x28, 0xce, 0x88, 0x12, 0x62 } }
+
+#pragma pack(1)
+
+//
+// NV data structure definition
+//
+typedef struct {
+ UINT32 DDRSpeedSel;
+ UINT32 EccMode;
+ UINT32 ErrCtrl_DE;
+ UINT32 ErrCtrl_FI;
+ UINT32 Slave32bit;
+ UINT32 ScrubPatrol;
+ UINT32 DemandScrub;
+ UINT32 WriteCrc;
+ UINT32 FGRMode;
+ UINT32 Refresh2x;
+ UINT32 NvdimmModeSel;
+} MEM_INFO_VARSTORE_DATA;
+
+//
+// Labels definition
+//
+#define LABEL_UPDATE 0x2223
+#define LABEL_END 0x2224
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenVfr.vfr
new file mode 100644
index 000000000000..e3d7aa0c44bd
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenVfr.vfr
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Guid/PlatformManagerHii.h>
+#include "MemInfoScreenNVDataStruct.h"
+
+formset
+ guid = MEM_INFO_FORM_SET_GUID,
+ title = STRING_TOKEN(STR_MEM_INFO_FORM),
+ help = STRING_TOKEN(STR_MEM_INFO_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ //
+ // Define a variable Storage
+ //
+ varstore MEM_INFO_VARSTORE_DATA,
+ varid = MEM_INFO_VARSTORE_ID,
+ name = MemInfoIfrNVData,
+ guid = MEM_INFO_FORM_SET_GUID;
+
+ form
+ formid = MEM_INFO_FORM_ID,
+ title = STRING_TOKEN(STR_MEM_INFO_FORM);
+
+ subtitle text = STRING_TOKEN(STR_MEM_INFO_FORM);
+
+ label LABEL_UPDATE;
+ // dynamic content here
+ label LABEL_END;
+
+ endform;
+
+ form
+ formid = MEM_INFO_FORM_PERFORMANCE_ID,
+ title = STRING_TOKEN(STR_MEM_INFO_PERFORMANCE_FORM);
+
+ subtitle text = STRING_TOKEN(STR_MEM_INFO_PERFORMANCE_FORM);
+
+ label LABEL_UPDATE;
+ // dynamic content here
+ label LABEL_END;
+
+ endform;
+
+ form
+ formid = MEM_INFO_FORM_NVDIMM_ID,
+ title = STRING_TOKEN(STR_MEM_INFO_NVDIMM_FORM);
+
+ subtitle text = STRING_TOKEN(STR_MEM_INFO_NVDIMM_FORM);
+
+ label LABEL_UPDATE;
+ // dynamic content here
+ label LABEL_END;
+
+ endform;
+
+endformset;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c
new file mode 100644
index 000000000000..c83f489f4078
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c
@@ -0,0 +1,394 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/NVParamLib.h>
+
+#include "MemInfoScreen.h"
+#include "NVParamDef.h"
+
+#define DDR_NVPARAM_ERRCTRL_DE_FIELD_SHIFT 0
+#define DDR_NVPARAM_ERRCTRL_DE_FIELD_MASK 0x1
+
+#define DDR_NVPARAM_ERRCTRL_FI_FIELD_SHIFT 1
+#define DDR_NVPARAM_ERRCTRL_FI_FIELD_MASK 0x2
+
+/**
+ This is function collects meminfo from NVParam
+
+ @param Data The buffer to return the contents.
+
+ @retval EFI_SUCCESS Get response data successfully.
+ @retval Other value Failed to get meminfo from NVParam
+**/
+EFI_STATUS
+MemInfoNvparamGet (
+ OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ )
+{
+ UINT32 Value;
+ EFI_STATUS Status;
+
+ ASSERT (VarStoreConfig != NULL);
+
+ Status = NVParamGet (
+ NV_SI_DDR_SPEED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->DDRSpeedSel = 0; /* Default auto mode */
+ } else {
+ VarStoreConfig->DDRSpeedSel = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_ECC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->EccMode = ECC_SECDED; /* Default enable */
+ } else {
+ VarStoreConfig->EccMode = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_ERRCTRL,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->ErrCtrl_DE = ERRCTLR_DE_ENABLE;
+ VarStoreConfig->ErrCtrl_FI = ERRCTLR_FI_ENABLE;
+ } else {
+ VarStoreConfig->ErrCtrl_DE = (Value & DDR_NVPARAM_ERRCTRL_DE_FIELD_MASK) >> DDR_NVPARAM_ERRCTRL_DE_FIELD_SHIFT;
+ VarStoreConfig->ErrCtrl_FI = (Value & DDR_NVPARAM_ERRCTRL_FI_FIELD_MASK) >> DDR_NVPARAM_ERRCTRL_FI_FIELD_SHIFT;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_SLAVE_32BIT_MEM_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->Slave32bit = 0; /* Default disabled */
+ } else {
+ VarStoreConfig->Slave32bit = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_SCRUB_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->ScrubPatrol = DDR_DEFAULT_SCRUB_PATROL_DURATION;
+ } else {
+ VarStoreConfig->ScrubPatrol = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_WR_BACK_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->DemandScrub = DDR_DEFAULT_DEMAND_SCRUB;
+ } else {
+ VarStoreConfig->DemandScrub = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_CRC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->WriteCrc = DDR_DEFAULT_WRITE_CRC;
+ } else {
+ VarStoreConfig->WriteCrc = Value;
+ }
+
+ Status = NVParamGet (
+ NV_SI_DDR_REFRESH_GRANULARITY,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->FGRMode = DDR_DEFAULT_FGR_MODE;
+ VarStoreConfig->Refresh2x = DDR_DEFAULT_REFRESH2X_MODE;
+ } else {
+ VarStoreConfig->FGRMode = DDR_FGR_MODE_GET (Value);
+ VarStoreConfig->Refresh2x = DDR_REFRESH_2X_GET (Value);
+ }
+
+ Status = NVParamGet (
+ NV_SI_NVDIMM_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ VarStoreConfig->NvdimmModeSel = DDR_DEFAULT_NVDIMM_MODE_SEL;
+ } else {
+ VarStoreConfig->NvdimmModeSel = Value & DDR_NVDIMM_MODE_SEL_MASK; /* Mask out valid bit */
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This is function stores meminfo to corresponding NVParam
+
+ @param VarStoreConfig The contents for the variable.
+
+ @retval EFI_SUCCESS Set data successfully.
+ @retval Other value Failed to set meminfo to NVParam
+
+**/
+EFI_STATUS
+MemInfoNvparamSet (
+ IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value, TmpValue, Value2, Update;
+
+ ASSERT (VarStoreConfig != NULL);
+
+ /* Set DDR speed */
+ Status = NVParamGet (
+ NV_SI_DDR_SPEED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != VarStoreConfig->DDRSpeedSel) {
+ Status = NVParamSet (
+ NV_SI_DDR_SPEED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ VarStoreConfig->DDRSpeedSel
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Set ECC mode */
+ Status = NVParamGet (
+ NV_SI_DDR_ECC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != VarStoreConfig->EccMode) {
+ Status = NVParamSet (
+ NV_SI_DDR_ECC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ VarStoreConfig->EccMode
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Set ErrCtrl */
+ TmpValue = (VarStoreConfig->ErrCtrl_DE << DDR_NVPARAM_ERRCTRL_DE_FIELD_SHIFT) |
+ (VarStoreConfig->ErrCtrl_FI << DDR_NVPARAM_ERRCTRL_FI_FIELD_SHIFT);
+ Status = NVParamGet (
+ NV_SI_DDR_ERRCTRL,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != TmpValue ) {
+ Status = NVParamSet (
+ NV_SI_DDR_ERRCTRL,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ TmpValue
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Set slave's 32bit region */
+ TmpValue = VarStoreConfig->Slave32bit;
+ Status = NVParamGet (
+ NV_SI_DDR_SLAVE_32BIT_MEM_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != TmpValue ) {
+ if (TmpValue == 0) {
+ /* Default is disabled so just clear nvparam */
+ Status = NVParamClr (
+ NV_SI_DDR_SLAVE_32BIT_MEM_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC
+ );
+ } else {
+ Status = NVParamSet (
+ NV_SI_DDR_SLAVE_32BIT_MEM_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ TmpValue
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Set Scrub patrol */
+ TmpValue = VarStoreConfig->ScrubPatrol;
+ Status = NVParamGet (
+ NV_SI_DDR_SCRUB_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != TmpValue ) {
+ if (TmpValue == DDR_DEFAULT_SCRUB_PATROL_DURATION) {
+ Status = NVParamClr (
+ NV_SI_DDR_SCRUB_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC
+ );
+ } else {
+ Status = NVParamSet (
+ NV_SI_DDR_SCRUB_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ TmpValue
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Demand Scrub */
+ TmpValue = VarStoreConfig->DemandScrub;
+ Status = NVParamGet (
+ NV_SI_DDR_WR_BACK_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != TmpValue ) {
+ if (TmpValue == DDR_DEFAULT_DEMAND_SCRUB) {
+ Status = NVParamClr (
+ NV_SI_DDR_WR_BACK_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC
+ );
+ } else {
+ Status = NVParamSet (
+ NV_SI_DDR_WR_BACK_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ TmpValue
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Write CRC */
+ TmpValue = VarStoreConfig->WriteCrc;
+ Status = NVParamGet (
+ NV_SI_DDR_CRC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || Value != TmpValue ) {
+ if (TmpValue == DDR_DEFAULT_WRITE_CRC) {
+ Status = NVParamClr (
+ NV_SI_DDR_CRC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC
+ );
+ } else {
+ Status = NVParamSet (
+ NV_SI_DDR_CRC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ TmpValue
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Write FGR/Refresh2X */
+ Value = 0;
+ Update = 0;
+ TmpValue = VarStoreConfig->FGRMode;
+ Status = NVParamGet (
+ NV_SI_DDR_REFRESH_GRANULARITY,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ Value2 = DDR_FGR_MODE_GET (Value);
+ if ((EFI_ERROR (Status) && TmpValue != DDR_DEFAULT_FGR_MODE)
+ || Value2 != TmpValue)
+ {
+ DDR_FGR_MODE_SET (Value, TmpValue);
+ Update = 1;
+ }
+
+ Value2 = DDR_REFRESH_2X_GET (Value);
+ TmpValue = VarStoreConfig->Refresh2x;
+ if ((EFI_ERROR (Status) && TmpValue != DDR_DEFAULT_REFRESH2X_MODE)
+ || Value2 != TmpValue)
+ {
+ DDR_REFRESH_2X_SET (Value, TmpValue);
+ Update = 1;
+ }
+
+ if (Update == 1) {
+ Status = NVParamSet (
+ NV_SI_DDR_REFRESH_GRANULARITY,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ /* Write NVDIMM-N Mode selection */
+ Value = 0;
+ TmpValue = VarStoreConfig->NvdimmModeSel;
+ Status = NVParamGet (
+ NV_SI_NVDIMM_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ Value2 = Value & DDR_NVDIMM_MODE_SEL_MASK; /* Mask out valid bit */
+ if (EFI_ERROR (Status) || Value2 != TmpValue ) {
+ if (TmpValue == DDR_DEFAULT_NVDIMM_MODE_SEL) {
+ Status = NVParamClr (
+ NV_SI_NVDIMM_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC
+ );
+ } else {
+ Value = TmpValue | DDR_NVDIMM_MODE_SEL_VALID_BIT; /* Add valid bit */
+ Status = NVParamSet (
+ NV_SI_NVDIMM_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c
new file mode 100644
index 000000000000..3a1a5840db9d
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c
@@ -0,0 +1,1325 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MemInfoScreen.h"
+
+#define MAX_STRING_SIZE 64
+#define GB_SCALE_FACTOR (1024*1024*1024)
+#define MB_SCALE_FACTOR (1024*1024)
+
+EFI_GUID gMemInfoFormSetGuid = MEM_INFO_FORM_SET_GUID;
+
+HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ MEM_INFO_FORM_SET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+EFI_HANDLE DriverHandle = NULL;
+MEM_INFO_SCREEN_PRIVATE_DATA *mPrivateData = NULL;
+
+/**
+ This function allows a caller to extract the current configuration for one
+ or more named elements from the target driver.
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Request A null-terminated Unicode string in
+ <ConfigRequest> format.
+ @param Progress On return, points to a character in the Request
+ string. Points to the string's null terminator if
+ request was successful. Points to the most recent
+ '&' before the first failing name/value pair (or
+ the beginning of the string if the failure is in
+ the first name/value pair) if the request was not
+ successful.
+ @param Results A null-terminated Unicode string in
+ <ConfigAltResp> format which has all values filled
+ in for the names in the Request string. String to
+ be allocated by the called function.
+ @retval EFI_SUCCESS The Results is filled with the requested values.
+ @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+**/
+EFI_STATUS
+EFIAPI
+ExtractConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ CHAR16 *StrPointer;
+ BOOLEAN AllocatedRequest;
+
+ if (Progress == NULL || Results == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
+
+ PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+
+ //
+ // Get Buffer Storage data from EFI variable.
+ // Try to get the current setting from variable.
+ //
+ BufferSize = sizeof (MEM_INFO_VARSTORE_DATA);
+ Status = MemInfoNvparamGet (&PrivateData->VarStoreConfig);
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (Request == NULL) {
+ //
+ // Request is set to NULL, construct full request string.
+ //
+
+ //
+ // Allocate and fill a buffer large enough to hold the <ConfigHdr> template
+ // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (&gMemInfoFormSetGuid, MEM_INFO_VARSTORE_NAME, PrivateData->DriverHandle);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
+ FreePool (ConfigRequestHdr);
+ ConfigRequestHdr = NULL;
+ } else {
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Request, &gMemInfoFormSetGuid, NULL)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Set Request to the unified request string.
+ //
+ ConfigRequest = Request;
+
+ //
+ // Check whether Request includes Request Element.
+ //
+ if (StrStr (Request, L"OFFSET") == NULL) {
+ //
+ // Check Request Element does exist in Request String
+ //
+ StrPointer = StrStr (Request, L"PATH");
+ if (StrPointer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if (StrStr (StrPointer, L"&") == NULL) {
+ Size = (StrLen (Request) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", Request, (UINT64)BufferSize);
+ }
+ }
+ }
+
+ //
+ // Check if requesting Name/Value storage
+ //
+ if (StrStr (ConfigRequest, L"OFFSET") == NULL) {
+ //
+ // Don't have any Name/Value storage names
+ //
+ Status = EFI_SUCCESS;
+ } else {
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ Status = HiiConfigRouting->BlockToConfig (
+ HiiConfigRouting,
+ ConfigRequest,
+ (UINT8 *)&PrivateData->VarStoreConfig,
+ BufferSize,
+ Results,
+ Progress
+ );
+ }
+
+ //
+ // Free the allocated config request string.
+ //
+ if (AllocatedRequest) {
+ FreePool (ConfigRequest);
+ }
+
+ if (ConfigRequestHdr != NULL) {
+ FreePool (ConfigRequestHdr);
+ }
+ //
+ // Set Progress string to the original request string.
+ //
+ if (Request == NULL) {
+ *Progress = NULL;
+ } else if (StrStr (Request, L"OFFSET") == NULL) {
+ *Progress = Request + StrLen (Request);
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Configuration A null-terminated Unicode string in <ConfigResp>
+ format.
+ @param Progress A pointer to a string filled in with the offset of
+ the most recent '&' before the first failing
+ name/value pair (or the beginning of the string if
+ the failure is in the first name/value pair) or
+ the terminating NULL if all was successful.
+ @retval EFI_SUCCESS The Results is processed successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+**/
+EFI_STATUS
+EFIAPI
+RouteConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ if (Configuration == NULL || Progress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+ *Progress = Configuration;
+
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Configuration, &gMemInfoFormSetGuid, NULL)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Get Buffer Storage data from NVParam
+ //
+ Status = MemInfoNvparamGet (&PrivateData->VarStoreConfig);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Check if configuring Name/Value storage
+ //
+ if (StrStr (Configuration, L"OFFSET") == NULL) {
+ //
+ // Don't have any Name/Value storage names
+ //
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
+ //
+ BufferSize = sizeof (MEM_INFO_VARSTORE_DATA);
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->VarStoreConfig,
+ &BufferSize,
+ Progress
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Store Buffer Storage back to NVParam
+ //
+ Status = MemInfoNvparamSet (&PrivateData->VarStoreConfig);
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_UNSUPPORTED The specified Action is not supported by the
+ callback.
+**/
+EFI_STATUS
+EFIAPI
+DriverCallback (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+{
+ if (((Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (Action) {
+ case EFI_BROWSER_ACTION_FORM_OPEN:
+ case EFI_BROWSER_ACTION_FORM_CLOSE:
+ break;
+
+ case EFI_BROWSER_ACTION_DEFAULT_STANDARD:
+ case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING:
+ {
+ switch (QuestionId) {
+ case MEM_INFO_DDR_SPEED_SEL_QUESTION_ID:
+ //
+ // DDR speed selection default to auto
+ //
+ Value->u32 = 0;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID:
+ //
+ // ECC mode default to be enabled
+ //
+ Value->u32 = ECC_SECDED;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID:
+ //
+ // ErrCtrl_DE default to be enabled
+ //
+ Value->u32 = ERRCTLR_DE_ENABLE;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID:
+ //
+ // ErrCtrl_FI default to be enabled
+ //
+ Value->u32 = ERRCTLR_FI_ENABLE;
+ break;
+
+ case MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID:
+ //
+ // Slave's 32bit region to be disabled
+ //
+ Value->u32 = 0;
+ break;
+
+ case MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_SCRUB_PATROL_DURATION;
+ break;
+
+ case MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_DEMAND_SCRUB;
+ break;
+
+ case MEM_INFO_DDR_WRITE_CRC_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_WRITE_CRC;
+ break;
+
+ case MEM_INFO_FGR_MODE_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_FGR_MODE;
+ break;
+
+ case MEM_INFO_REFRESH2X_MODE_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_REFRESH2X_MODE;
+ break;
+
+ case MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_NVDIMM_MODE_SEL;
+ break;
+ }
+ }
+ break;
+
+ case EFI_BROWSER_ACTION_RETRIEVE:
+ case EFI_BROWSER_ACTION_CHANGING:
+ case EFI_BROWSER_ACTION_SUBMITTED:
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MemInfoMainScreen (
+ PLATFORM_INFO_HOB *PlatformHob
+ )
+{
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
+ EFI_STATUS Status;
+ VOID *StartOpCodeHandle;
+ VOID *OptionsOpCodeHandle;
+ VOID *OptionsOpCodeHandle1;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ EFI_STRING_ID StringId;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ CHAR16 Str[MAX_STRING_SIZE], Str1[MAX_STRING_SIZE];
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
+ PLATFORM_DIMM_INFO *DimmInfo;
+ UINT64 Size;
+ UINTN Count;
+
+ //
+ // Get Buffer Storage data from EFI variable
+ //
+ Status = MemInfoNvparamGet (&PrivateData->VarStoreConfig);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EFI_SUCCESS;
+
+ /* Update Total memory */
+ UnicodeSPrint (Str, sizeof (Str), L"%d GB", PlatformHob->DramInfo.TotalSize / GB_SCALE_FACTOR);
+ HiiSetString (
+ PrivateData->HiiHandle,
+ STRING_TOKEN (STR_MEM_INFO_TOTAL_MEM_VALUE),
+ Str,
+ NULL
+ );
+
+ /* Update effective memory */
+ Size = 0;
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
+ while (ResHob != NULL) {
+ if ((ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)) {
+ Size += ResHob->ResourceLength;
+ }
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+ }
+ UnicodeSPrint (Str, sizeof (Str), L"%d GB", Size / GB_SCALE_FACTOR);
+ HiiSetString (
+ PrivateData->HiiHandle,
+ STRING_TOKEN (STR_MEM_INFO_EFFECT_MEM_VALUE),
+ Str,
+ NULL
+ );
+
+ /* Update current DDR speed */
+ UnicodeSPrint (Str, sizeof (Str), L"%d MHz", PlatformHob->DramInfo.MaxSpeed);
+ HiiSetString (
+ PrivateData->HiiHandle,
+ STRING_TOKEN (STR_MEM_INFO_CURRENT_SPEED_VALUE),
+ Str,
+ NULL
+ );
+
+ //
+ // Initialize the container for dynamic opcodes
+ //
+ StartOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (StartOpCodeHandle != NULL);
+
+ EndOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (EndOpCodeHandle != NULL);
+
+ //
+ // Create Option OpCode to display speed configuration
+ //
+ OptionsOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (OptionsOpCodeHandle != NULL);
+
+ //
+ // Create Option OpCode to display FGR mode configuration
+ //
+ OptionsOpCodeHandle1 = HiiAllocateOpCodeHandle ();
+ ASSERT (OptionsOpCodeHandle1 != NULL);
+
+ //
+ // Create Hii Extend Label OpCode as the start opcode
+ //
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ StartLabel->Number = LABEL_UPDATE;
+
+ //
+ // Create Hii Extend Label OpCode as the end opcode
+ //
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ EndLabel->Number = LABEL_END;
+
+ //
+ // Create a total mem title
+ //
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_TOTAL_MEM),
+ STRING_TOKEN (STR_MEM_INFO_TOTAL_MEM),
+ STRING_TOKEN (STR_MEM_INFO_TOTAL_MEM_VALUE)
+ );
+
+ //
+ // Create a effective mem title
+ //
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_EFFECT_MEM),
+ STRING_TOKEN (STR_MEM_INFO_EFFECT_MEM),
+ STRING_TOKEN (STR_MEM_INFO_EFFECT_MEM_VALUE)
+ );
+
+ //
+ // Create a current speed title
+ //
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_CURRENT_SPEED),
+ STRING_TOKEN (STR_MEM_INFO_CURRENT_SPEED),
+ STRING_TOKEN (STR_MEM_INFO_CURRENT_SPEED_VALUE)
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE0),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 0
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE1),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2133
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE2),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2400
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE3),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2666
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE4),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2933
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_VALUE5),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 3200
+ );
+
+ HiiCreateOneOfOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_DDR_SPEED_SEL_QUESTION_ID, // Question ID (or call it "key")
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_DDR_SPEED_SEL_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_SPEED_SELECT_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
+ EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
+ OptionsOpCodeHandle, // Option Opcode list
+ NULL // Default Opcode is NULl
+ );
+
+ if (IsSlaveSocketActive ()) {
+ /* Display enable slave's 32bit region */
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_ERR_SLAVE_32BIT_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_32GB_SLAVE_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_32GB_SLAVE_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+ }
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle1,
+ STRING_TOKEN (STR_MEM_INFO_FGR_MODE_VALUE0),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 0
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle1,
+ STRING_TOKEN (STR_MEM_INFO_FGR_MODE_VALUE1),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 1
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle1,
+ STRING_TOKEN (STR_MEM_INFO_FGR_MODE_VALUE2),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2
+ );
+
+ HiiCreateOneOfOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FGR_MODE_QUESTION_ID, // Question ID (or call it "key")
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_FGR_MODE_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_FGR_MODE_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_FGR_MODE_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
+ EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
+ OptionsOpCodeHandle1, // Option Opcode list
+ NULL // Default Opcode is NULl
+ );
+
+ //
+ // Create a Goto OpCode to ras memory configuration
+ //
+ HiiCreateGotoOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_PERFORMANCE_ID, // Target Form ID
+ STRING_TOKEN (STR_MEM_INFO_PERFORMANCE_FORM), // Prompt text
+ STRING_TOKEN (STR_MEM_INFO_PERFORMANCE_FORM_HELP), // Help text
+ 0, // Question flag
+ MEM_INFO_FORM_PERFORMANCE_QUESTION_ID // Question ID
+ );
+
+ //
+ // Create a Goto OpCode to nvdimm-n configuration
+ //
+ HiiCreateGotoOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_NVDIMM_ID, // Target Form ID
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_FORM), // Prompt text
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_FORM_HELP), // Help text
+ 0, // Question flag
+ MEM_INFO_FORM_NVDIMM_QUESTION_ID // Question ID
+ );
+
+ //
+ // Display DIMM list info
+ //
+ HiiCreateSubTitleOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_DIMM_INFO),
+ 0,
+ 0,
+ 0
+ );
+
+ for (Count = 0; Count < PlatformHob->DimmList.BoardDimmSlots; Count++) {
+ DimmInfo = &PlatformHob->DimmList.Dimm[Count].Info;
+ switch (DimmInfo->DimmType) {
+ case UDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"UDIMM");
+ break;
+
+ case RDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"RDIMM");
+ break;
+
+ case SODIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"SODIMM");
+ break;
+
+ case LRDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"LRDIMM");
+ break;
+
+ case RSODIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"RSODIMM");
+ break;
+
+ case NVRDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"NV-RDIMM");
+ break;
+
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"Unknown Type");
+ }
+ if (DimmInfo->DimmStatus == DIMM_INSTALLED_OPERATIONAL) {
+ UnicodeSPrint (Str1, sizeof (Str1), L"Slot %2d: %d GB %s Installed&Operational", Count + 1, DimmInfo->DimmSize, Str);
+ } else if (DimmInfo->DimmStatus == DIMM_NOT_INSTALLED) {
+ UnicodeSPrint (Str1, sizeof (Str1), L"Slot %2d: Not Installed", Count + 1, PlatformHob->DimmList.Dimm[Count].NodeId);
+ } else if (DimmInfo->DimmStatus == DIMM_INSTALLED_NONOPERATIONAL) {
+ UnicodeSPrint (Str1, sizeof (Str1), L"Slot %2d: Installed&Non-Operational", Count + 1, PlatformHob->DimmList.Dimm[Count].NodeId);
+ } else {
+ UnicodeSPrint (Str1, sizeof (Str1), L"Slot %2d: Installed&Failed", Count + 1, PlatformHob->DimmList.Dimm[Count].NodeId);
+ }
+
+ StringId = HiiSetString (PrivateData->HiiHandle, 0, Str1, NULL);
+
+ HiiCreateSubTitleOpCode (
+ StartOpCodeHandle,
+ StringId,
+ 0,
+ 0,
+ 0
+ );
+ }
+
+ HiiUpdateForm (
+ PrivateData->HiiHandle, // HII handle
+ &gMemInfoFormSetGuid, // Formset GUID
+ MEM_INFO_FORM_ID, // Form ID
+ StartOpCodeHandle, // Label for where to insert opcodes
+ EndOpCodeHandle // Insert data
+ );
+
+ HiiFreeOpCodeHandle (StartOpCodeHandle);
+ HiiFreeOpCodeHandle (EndOpCodeHandle);
+ HiiFreeOpCodeHandle (OptionsOpCodeHandle);
+
+ return Status;
+}
+
+EFI_STATUS
+MemInfoMainPerformanceScreen (
+ PLATFORM_INFO_HOB *PlatformHob
+ )
+{
+ EFI_STATUS Status;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
+ VOID *StartOpCodeHandle;
+ VOID *OptionsEccOpCodeHandle, *OptionsScrubOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ EFI_STRING_ID StringId;
+ CHAR16 Str[MAX_STRING_SIZE];
+ UINTN Idx;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Initialize the container for dynamic opcodes
+ //
+ StartOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (StartOpCodeHandle != NULL);
+
+ EndOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (EndOpCodeHandle != NULL);
+
+ //
+ // Create Hii Extend Label OpCode as the start opcode
+ //
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ StartLabel->Number = LABEL_UPDATE;
+
+ //
+ // Create Hii Extend Label OpCode as the end opcode
+ //
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ EndLabel->Number = LABEL_END;
+
+ /* Display ECC mode selection */
+ OptionsEccOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (OptionsEccOpCodeHandle != NULL);
+
+ UnicodeSPrint (Str, sizeof (Str), L"Disabled");
+ StringId = HiiSetString (PrivateData->HiiHandle, 0, Str, NULL);
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsEccOpCodeHandle,
+ StringId,
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 0
+ );
+
+ UnicodeSPrint (Str, sizeof (Str), L"SECDED");
+ StringId = HiiSetString (PrivateData->HiiHandle, 0, Str, NULL);
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsEccOpCodeHandle,
+ StringId,
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 1
+ );
+
+ UnicodeSPrint (Str, sizeof (Str), L"Symbol");
+ StringId = HiiSetString (PrivateData->HiiHandle, 0, Str, NULL);
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsEccOpCodeHandle,
+ StringId,
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2
+ );
+
+ HiiCreateOneOfOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID, // Question ID (or call it "key")
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_ECC_MODE_SEL_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ECC_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ECC_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
+ EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
+ OptionsEccOpCodeHandle, // Option Opcode list
+ NULL // Default Opcode is NULl
+ );
+
+ /*
+ * Display ErrCtrl options
+ */
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_ERR_CTRL_DE_MODE_SEL_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ERRCTRL_DE_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ERRCTRL_DE_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_ERR_CTRL_FI_MODE_SEL_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ERRCTRL_FI_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_ERRCTRL_FI_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+
+ /* Display Scrub Patrol selection */
+ OptionsScrubOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (OptionsScrubOpCodeHandle != NULL);
+
+ UnicodeSPrint (Str, sizeof (Str), L"Disabled");
+ StringId = HiiSetString (PrivateData->HiiHandle, 0, Str, NULL);
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsScrubOpCodeHandle,
+ StringId,
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 0
+ );
+
+ for (Idx = 1; Idx <= MAX_NUMBER_OF_HOURS_IN_A_DAY; Idx++) {
+ UnicodeSPrint (Str, sizeof (Str), L"%d", Idx);
+ StringId = HiiSetString (
+ PrivateData->HiiHandle,
+ 0,
+ Str,
+ NULL
+ );
+ HiiCreateOneOfOptionOpCode (
+ OptionsScrubOpCodeHandle,
+ StringId,
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ Idx
+ );
+ }
+
+ HiiCreateOneOfOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID, // Question ID (or call it "key")
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_DDR_SCRUB_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_SCRUB), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_SCRUB_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
+ EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
+ OptionsScrubOpCodeHandle, // Option Opcode list
+ NULL // Default Opcode is NULl
+ );
+
+ /*
+ * Display Demand Scrub options
+ */
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_DDR_DEMAND_SCRUB_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_DEMAND_SCRUB_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_DEMAND_SCRUB_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+
+ /*
+ * Display Write CRC options
+ */
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_DDR_WRITE_CRC_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_DDR_WRITE_CRC_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_WRITE_CRC_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_ENABLE_WRITE_CRC_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+
+ /*
+ * Display CVE-2020-10255 options
+ */
+ HiiCreateCheckBoxOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_REFRESH2X_MODE_QUESTION_ID, // Question ID
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_REFRESH2X_MODE_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_REFRESH2X_MODE_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_REFRESH2X_MODE_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ 0,
+ NULL
+ );
+
+ HiiUpdateForm (
+ PrivateData->HiiHandle, // HII handle
+ &gMemInfoFormSetGuid, // Formset GUID
+ MEM_INFO_FORM_PERFORMANCE_ID, // Form ID
+ StartOpCodeHandle, // Label for where to insert opcodes
+ EndOpCodeHandle // Insert data
+ );
+
+ HiiFreeOpCodeHandle (StartOpCodeHandle);
+ HiiFreeOpCodeHandle (EndOpCodeHandle);
+ HiiFreeOpCodeHandle (OptionsEccOpCodeHandle);
+ HiiFreeOpCodeHandle (OptionsScrubOpCodeHandle);
+
+ return Status;
+}
+
+EFI_STATUS
+MemInfoMainNvdimmScreen (
+ PLATFORM_INFO_HOB *PlatformHob
+ )
+{
+ EFI_STATUS Status;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ VOID *StartOpCodeHandle;
+ VOID *OptionsOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ CHAR16 Str[MAX_STRING_SIZE];
+
+ Status = EFI_SUCCESS;
+ PrivateData = mPrivateData;
+
+ if (PlatformHob == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Initialize the container for dynamic opcodes
+ //
+ StartOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (StartOpCodeHandle != NULL);
+
+ EndOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (EndOpCodeHandle != NULL);
+
+ //
+ // Create Hii Extend Label OpCode as the start opcode
+ //
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ StartOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ StartLabel->Number = LABEL_UPDATE;
+
+ //
+ // Create Hii Extend Label OpCode as the end opcode
+ //
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ EndOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ EndLabel->Number = LABEL_END;
+
+ //
+ // Update Current NVDIMM-N Mode title Socket0
+ //
+ switch (PlatformHob->DramInfo.NvdimmMode[0]) {
+ case 0:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
+ break;
+
+ case 1:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
+ break;
+
+ case 2:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
+ break;
+
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
+ break;
+ }
+
+ HiiSetString (
+ PrivateData->HiiHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK0_VALUE),
+ Str,
+ NULL
+ );
+
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK0),
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK0),
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK0_VALUE)
+ );
+
+ //
+ // Update Current NVDIMM-N Mode title Socket1
+ //
+ if (IsSlaveSocketActive ()) {
+ switch (PlatformHob->DramInfo.NvdimmMode[1]) {
+ case 0:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
+ break;
+
+ case 1:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
+ break;
+
+ case 2:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
+ break;
+
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
+ break;
+ }
+
+ HiiSetString (
+ PrivateData->HiiHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK1_VALUE),
+ Str,
+ NULL
+ );
+
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK1),
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK1),
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK1_VALUE)
+ );
+ }
+ //
+ // Create Option OpCode to NVDIMM-N Mode Selection
+ //
+ OptionsOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (OptionsOpCodeHandle != NULL);
+
+ //
+ // Create OpCode to NVDIMM-N Mode Selection
+ //
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE0),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 0
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE1),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 1
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE2),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 2
+ );
+
+ HiiCreateOneOfOptionOpCode (
+ OptionsOpCodeHandle,
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE3),
+ 0,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 3
+ );
+
+ HiiCreateOneOfOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID, // Question ID (or call it "key")
+ MEM_INFO_VARSTORE_ID, // VarStore ID
+ (UINT16)MEM_INFO_NVDIMM_MODE_SEL_OFFSET, // Offset in Buffer Storage
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_MEM_INFO_NVDIMM_MODE_SEL_HELP), // Question help text
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
+ EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
+ OptionsOpCodeHandle, // Option Opcode list
+ NULL // Default Opcode is NULl
+ );
+
+ HiiUpdateForm (
+ PrivateData->HiiHandle, // HII handle
+ &gMemInfoFormSetGuid, // Formset GUID
+ MEM_INFO_FORM_NVDIMM_ID, // Form ID
+ StartOpCodeHandle, // Label for where to insert opcodes
+ EndOpCodeHandle // Insert data
+ );
+
+ HiiFreeOpCodeHandle (StartOpCodeHandle);
+ HiiFreeOpCodeHandle (EndOpCodeHandle);
+ HiiFreeOpCodeHandle (OptionsOpCodeHandle);
+
+ return Status;
+}
+
+/**
+ This function sets up the first elements of the form.
+ @param PrivateData Private data.
+ @retval EFI_SUCCESS The form is set up successfully.
+**/
+EFI_STATUS
+MemInfoScreenSetup (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *Hob;
+ PLATFORM_INFO_HOB *PlatformHob;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ Status = MemInfoMainScreen (PlatformHob);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = MemInfoMainPerformanceScreen (PlatformHob);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = MemInfoMainNvdimmScreen (PlatformHob);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MemInfoScreenInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ BOOLEAN ActionFlag;
+ EFI_STRING ConfigRequestHdr;
+
+ //
+ // Initialize driver private data
+ //
+ mPrivateData = AllocateZeroPool (sizeof (MEM_INFO_SCREEN_PRIVATE_DATA));
+ if (mPrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->Signature = MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE;
+
+ mPrivateData->ConfigAccess.ExtractConfig = ExtractConfig;
+ mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
+ mPrivateData->ConfigAccess.Callback = DriverCallback;
+
+ //
+ // Locate ConfigRouting protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID **)&HiiConfigRouting);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mPrivateData->HiiConfigRouting = HiiConfigRouting;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &DriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mPrivateData->DriverHandle = DriverHandle;
+
+ //
+ // Publish our HII data
+ //
+ HiiHandle = HiiAddPackages (
+ &gMemInfoFormSetGuid,
+ DriverHandle,
+ MemInfoDxeStrings,
+ MemInfoScreenVfrBin,
+ NULL
+ );
+ if (HiiHandle == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->HiiHandle = HiiHandle;
+
+ //
+ // Try to read NV config EFI variable first
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (
+ &gMemInfoFormSetGuid,
+ MEM_INFO_VARSTORE_NAME,
+ DriverHandle
+ );
+ ASSERT (ConfigRequestHdr != NULL);
+
+ //
+ // Validate Current Setting
+ //
+ ActionFlag = HiiValidateSettings (ConfigRequestHdr);
+ if (!ActionFlag) {
+ MemInfoScreenUnload (ImageHandle);
+ return EFI_INVALID_PARAMETER;
+ }
+ FreePool (ConfigRequestHdr);
+
+ Status = MemInfoScreenSetup ();
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+MemInfoScreenUnload (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ ASSERT (mPrivateData != NULL);
+
+ if (DriverHandle != NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ DriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ DriverHandle = NULL;
+ }
+
+ if (mPrivateData->HiiHandle != NULL) {
+ HiiRemovePackages (mPrivateData->HiiHandle);
+ }
+
+ FreePool (mPrivateData);
+ mPrivateData = NULL;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.uni
new file mode 100644
index 000000000000..a8c7cb99d6a7
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.uni
@@ -0,0 +1,9 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#string STR_MODULE_ABSTRACT #language en-US "An Altra DDR screen setup driver"
+
+#string STR_MODULE_DESCRIPTION #language en-US "This driver exposes a screen setup for DDR information and configuration."
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxeExtra.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxeExtra.uni
new file mode 100644
index 000000000000..f44f210594be
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxeExtra.uni
@@ -0,0 +1,9 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"Ampere Altra MemInfo DXE Driver"
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenStrings.uni
new file mode 100644
index 000000000000..d170f9ee7313
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenStrings.uni
@@ -0,0 +1,64 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English" // English
+
+#string STR_MEM_INFO_FORM #language en-US "Memory Configuration"
+#string STR_MEM_INFO_FORM_HELP #language en-US "Memory Configuration"
+#string STR_MEM_INFO_TOTAL_MEM #language en-US "Total Memory"
+#string STR_MEM_INFO_TOTAL_MEM_VALUE #language en-US "0 GB"
+#string STR_MEM_INFO_EFFECT_MEM #language en-US "Effective Memory"
+#string STR_MEM_INFO_EFFECT_MEM_VALUE #language en-US "0 MB"
+#string STR_MEM_INFO_CURRENT_SPEED #language en-US "Memory Speed"
+#string STR_MEM_INFO_CURRENT_SPEED_VALUE #language en-US "0 MHz"
+#string STR_MEM_INFO_SPEED_SELECT_PROMPT #language en-US "Memory Operating Speed Selection"
+#string STR_MEM_INFO_SPEED_SELECT_HELP #language en-US "Force specific Memory Operating Speed or use Auto setting."
+#string STR_MEM_INFO_SPEED_SELECT_VALUE0 #language en-US "Auto"
+#string STR_MEM_INFO_SPEED_SELECT_VALUE1 #language en-US "2133"
+#string STR_MEM_INFO_SPEED_SELECT_VALUE2 #language en-US "2400"
+#string STR_MEM_INFO_SPEED_SELECT_VALUE3 #language en-US "2666"
+#string STR_MEM_INFO_SPEED_SELECT_VALUE4 #language en-US "2933"
+#string STR_MEM_INFO_SPEED_SELECT_VALUE5 #language en-US "3200"
+#string STR_MEM_INFO_DIMM_INFO #language en-US "DIMM Information"
+
+#string STR_MEM_INFO_PERFORMANCE_FORM #language en-US "Memory RAS and Performance Configuration"
+#string STR_MEM_INFO_PERFORMANCE_FORM_HELP #language en-US "Displays and provides options to change the memory RAS and performance Settings"
+#string STR_MEM_INFO_ENABLE_ECC_PROMPT #language en-US "ECC mode"
+#string STR_MEM_INFO_ENABLE_ECC_HELP #language en-US "ECC mode: Disabled, SECDED or Symbol"
+#string STR_MEM_INFO_ENABLE_ERRCTRL_DE_PROMPT #language en-US "Defer uncorrectable read errors"
+#string STR_MEM_INFO_ENABLE_ERRCTRL_DE_HELP #language en-US "When enabled the DMC defers uncorrectable read errors to the consumer by sending an OK response and setting the TXDAT poison flag on the CHI-B interconnect. If this bit is clear the DMC defaults to non-deferred behavior when encountering an unrecoverable error"
+#string STR_MEM_INFO_ENABLE_ERRCTRL_FI_PROMPT #language en-US "Fault handling interrupt"
+#string STR_MEM_INFO_ENABLE_ERRCTRL_FI_HELP #language en-US "Enables fault handling interrupt. The fault handling interrupt is raised to give notice that ECC fault has been recorded"
+#string STR_MEM_INFO_ENABLE_SCRUB #language en-US "Scrub Patrol duration (hour)"
+#string STR_MEM_INFO_ENABLE_SCRUB_HELP #language en-US "Select duration (hour) for Scrub Patrol"
+#string STR_MEM_INFO_ENABLE_DEMAND_SCRUB_PROMPT #language en-US "Demand scrub"
+#string STR_MEM_INFO_ENABLE_DEMAND_SCRUB_HELP #language en-US "Enable/Disable the ability to write corrected data back to the memory once a correctable error is detected"
+#string STR_MEM_INFO_ENABLE_WRITE_CRC_PROMPT #language en-US "Write CRC"
+#string STR_MEM_INFO_ENABLE_WRITE_CRC_HELP #language en-US "Enable/Disable Cyclic Redundancy Check (CRC) functionality on write data. Be noted that enabling CRC will degrade Write bandwidth"
+
+
+#string STR_MEM_INFO_ENABLE_32GB_SLAVE_PROMPT #language en-US "Enable Slave 32bit memory region"
+#string STR_MEM_INFO_ENABLE_32GB_SLAVE_HELP #language en-US "Enables 32bit memory region (2GB) for slave socket"
+#string STR_MEM_INFO_FGR_MODE_PROMPT #language en-US "Fine Granularity Refresh (FGR)"
+#string STR_MEM_INFO_FGR_MODE_VALUE0 #language en-US "1x"
+#string STR_MEM_INFO_FGR_MODE_VALUE1 #language en-US "2x"
+#string STR_MEM_INFO_FGR_MODE_VALUE2 #language en-US "4x"
+#string STR_MEM_INFO_FGR_MODE_HELP #language en-US "Select DDR Fine Granularity Refresh (FGR) mode 1x/2x/4x"
+#string STR_MEM_INFO_REFRESH2X_MODE_PROMPT #language en-US "CVE-2020-10255 mitigation"
+#string STR_MEM_INFO_REFRESH2X_MODE_HELP #language en-US "Enable mitigation for CVE-2020-10255, TRRespass"
+
+#string STR_MEM_INFO_NVDIMM_FORM #language en-US "NVDIMM-N Configuration"
+#string STR_MEM_INFO_NVDIMM_FORM_HELP #language en-US "Displays and provides options to change the NVDIMM-N Settings"
+#string STR_MEM_INFO_NVDIMM_CUR_MODE_SK0 #language en-US "Socket0 Configured Mode"
+#string STR_MEM_INFO_NVDIMM_CUR_MODE_SK1 #language en-US "Socket1 Configured Mode"
+#string STR_MEM_INFO_NVDIMM_CUR_MODE_SK0_VALUE #language en-US "Non-NVDIMM"
+#string STR_MEM_INFO_NVDIMM_CUR_MODE_SK1_VALUE #language en-US "Non-NVDIMM"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_PROMPT #language en-US "Mode Selection"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE0 #language en-US "Non-NVDIMM"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE1 #language en-US "Non-Hashed"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE2 #language en-US "Hashed"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_VALUE3 #language en-US "Auto"
+#string STR_MEM_INFO_NVDIMM_MODE_SEL_HELP #language en-US "Select NVDIMM-N Mode (Non-NVDIMM/Non-Hashed/Hashed/Auto)"
--
2.17.1


[PATCH v3 26/28] AmpereAltraPkg: Add configuration screen for RAS

Nhi Pham
 

From: Quan Nguyen <quan@os.amperecomputing.com>

This supports user to enable/disable RAS APEI components running in the
system firmware such as HEST, BERT, and EINJ.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
---
Platform/Ampere/JadePkg/Jade.dsc | 1 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf | 56 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h | 61 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h | 46 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigVfr.vfr | 95 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c | 822 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigStrings.uni | 38 +
8 files changed, 1120 insertions(+)

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index daac52e84ea2..b5ac2547c8f8 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -200,3 +200,4 @@ [Components.common]
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 1564e45c30cd..e0d4b049f6bf 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -358,5 +358,6 @@ [FV.FvMain]
INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf

!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
new file mode 100644
index 000000000000..9b03ed57944f
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.inf
@@ -0,0 +1,56 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RasConfigDxe
+ FILE_GUID = 5b5ee6e3-3135-45f7-ad21-46a3f36813cc
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RasConfigEntryPoint
+
+[Sources.common]
+ RasConfigNVDataStruct.h
+ RasConfigDxe.c
+ RasConfigDxe.h
+ RasConfigVfr.vfr
+ RasConfigStrings.uni
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ DevicePathLib
+ HiiLib
+ MemoryAllocationLib
+ NVParamLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+
+[Guids]
+ gEfiIfrTianoGuid
+ gPlatformManagerFormsetGuid
+ gAcpiConfigFormSetGuid
+
+[Protocols]
+ gEfiDevicePathProtocolGuid ## CONSUMES
+ gEfiHiiConfigRoutingProtocolGuid ## CONSUMES
+ gEfiHiiConfigAccessProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h
new file mode 100644
index 000000000000..1258fbeda6a1
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h
@@ -0,0 +1,61 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RAS_CONFIG_DXE_H_
+#define RAS_CONFIG_DXE_H_
+
+#include "RasConfigNVDataStruct.h"
+
+//
+// This is the generated IFR binary data for each formset defined in VFR.
+//
+extern UINT8 RasConfigVfrBin[];
+
+//
+// This is the generated String package data for all .UNI files.
+//
+extern UINT8 RasConfigDxeStrings[];
+
+#define RAS_DDR_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, RasDdrCeThreshold)
+#define RAS_2P_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, Ras2pCeThreshold)
+
+#define RAS_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('R', 'A', 'S', 'C')
+
+typedef struct {
+ UINTN Signature;
+
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ RAS_CONFIG_VARSTORE_DATA Configuration;
+
+ //
+ // Consumed protocol
+ //
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Produced protocol
+ //
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+} RAS_CONFIG_PRIVATE_DATA;
+
+#define RAS_CONFIG_PRIVATE_FROM_THIS(a) CR (a, RAS_CONFIG_PRIVATE_DATA, ConfigAccess, RAS_CONFIG_PRIVATE_SIGNATURE)
+
+#pragma pack(1)
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+#endif /* RAS_CONFIG_DXE_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h
new file mode 100644
index 000000000000..8c528f043c27
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h
@@ -0,0 +1,46 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RAS_CONFIG_NV_DATA_STRUCT_H_
+#define RAS_CONFIG_NV_DATA_STRUCT_H_
+
+#define RAS_CONFIG_VARSTORE_ID 0x1234
+#define RAS_CONFIG_FORM_ID 0x1235
+
+#define RAS_VARSTORE_NAME L"RasConfigNVData"
+
+#define RAS_CONFIG_FORMSET_GUID \
+ { \
+ 0x96934cc6, 0xcb15, 0x4d8a, { 0xbe, 0x5f, 0x8e, 0x7d, 0x55, 0x0e, 0xc9, 0xc6 } \
+ }
+
+//
+// Labels definition
+//
+#define LABEL_UPDATE 0x3234
+#define LABEL_END 0xffff
+
+#pragma pack(1)
+
+//
+// Ras Configuration NV data structure definition
+//
+typedef struct {
+ UINT32 RasHardwareEinj;
+ UINT32 RasPcieAerFwFirstEnabled;
+ UINT32 RasBertEnabled;
+ UINT32 RasSdeiEnabled;
+ UINT32 RasDdrCeThreshold;
+ UINT32 Ras2pCeThreshold;
+ UINT32 RasCpmCeThreshold;
+ UINT32 RasLinkErrThreshold;
+} RAS_CONFIG_VARSTORE_DATA;
+
+#pragma pack()
+
+#endif /* RAS_CONFIG_NV_DATA_STRUCT_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigVfr.vfr
new file mode 100644
index 000000000000..ec38eb186c1b
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigVfr.vfr
@@ -0,0 +1,95 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RasConfigNVDataStruct.h"
+
+formset
+ guid = RAS_CONFIG_FORMSET_GUID,
+ title = STRING_TOKEN(STR_RAS_FORM),
+ help = STRING_TOKEN(STR_RAS_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ //
+ // Define a variable Storage
+ //
+ varstore RAS_CONFIG_VARSTORE_DATA,
+ varid = RAS_CONFIG_VARSTORE_ID,
+ name = RasConfigNVData,
+ guid = RAS_CONFIG_FORMSET_GUID;
+
+ form formid = RAS_CONFIG_FORM_ID,
+ title = STRING_TOKEN(STR_RAS_FORM);
+
+ subtitle text = STRING_TOKEN(STR_RAS_FORM);
+
+ oneof varid = RasConfigNVData.RasHardwareEinj,
+ prompt = STRING_TOKEN(STR_RAS_HARDWARE_EINJ_PROMPT),
+ help = STRING_TOKEN(STR_RAS_HARDWARE_EINJ_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_RAS_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_RAS_COMMON_DISABLE), value = 0, flags = 0;
+
+ endoneof;
+
+ oneof varid = RasConfigNVData.RasPcieAerFwFirstEnabled,
+ prompt = STRING_TOKEN(STR_RAS_PCIE_AER_FW_FIRST_PROMPT),
+ help = STRING_TOKEN(STR_RAS_PCIE_AER_FW_FIRST_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_RAS_COMMON_ENABLE), value = 1, flags = 0;
+ option text = STRING_TOKEN(STR_RAS_COMMON_DISABLE), value = 0, flags = DEFAULT;
+
+ endoneof;
+
+ oneof varid = RasConfigNVData.RasBertEnabled,
+ prompt = STRING_TOKEN(STR_RAS_BERT_ENABLED_PROMPT),
+ help = STRING_TOKEN(STR_RAS_BERT_ENABLED_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_RAS_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_RAS_COMMON_DISABLE), value = 0, flags = 0;
+
+ endoneof;
+
+ oneof varid = RasConfigNVData.RasSdeiEnabled,
+ prompt = STRING_TOKEN(STR_RAS_SDEI_ENABLED_PROMPT),
+ help = STRING_TOKEN(STR_RAS_SDEI_ENABLED_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_RAS_COMMON_ENABLE), value = 1, flags = 0;
+ option text = STRING_TOKEN(STR_RAS_COMMON_DISABLE), value = 0, flags = DEFAULT;
+
+ endoneof;
+
+ label LABEL_UPDATE;
+ //
+ // This is where we will dynamically add other Action type op-code
+ //
+ label LABEL_END;
+
+ numeric varid = RasConfigNVData.RasCpmCeThreshold,
+ prompt = STRING_TOKEN(STR_RAS_CPM_CE_THRESHOLD_PROMPT),
+ help = STRING_TOKEN(STR_RAS_CPM_CE_THRESHOLD_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ minimum = 1,
+ maximum = 8192,
+ default = 1,
+
+ endnumeric;
+
+ numeric varid = RasConfigNVData.RasLinkErrThreshold,
+ prompt = STRING_TOKEN(STR_RAS_LINK_ERR_THRESHOLD_PROMPT),
+ help = STRING_TOKEN(STR_RAS_LINK_ERR_THRESHOLD_HELP),
+ flags = NUMERIC_SIZE_4 | RESET_REQUIRED,
+ minimum = 1,
+ maximum = 8192,
+ default = 1,
+
+ endnumeric;
+
+
+ endform;
+
+endformset;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c
new file mode 100644
index 000000000000..41554775a0b4
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c
@@ -0,0 +1,822 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Guid/MdeModuleHii.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NVParamLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <NVParamDef.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/HiiConfigAccess.h>
+#include <Protocol/HiiConfigRouting.h>
+
+#include "RasConfigDxe.h"
+
+CHAR16 RasConfigVarstoreDataName[] = L"RasConfigNVData";
+
+EFI_HANDLE mDriverHandle = NULL;
+RAS_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+
+EFI_GUID mRasConfigFormSetGuid = RAS_CONFIG_FORMSET_GUID;
+
+//
+// Default RAS Settings
+//
+#define RAS_DEFAULT_HARDWARE_EINJ_SUPPORT 0
+#define RAS_DEFAULT_PCIE_AER_FW_FIRST 0
+#define RAS_DEFAULT_BERT_SUPPORT 1
+#define RAS_DEFAULT_SDEI_SUPPORT 0
+#define RAS_DEFAULT_DDR_CE_THRESHOLD 1
+#define RAS_DEFAULT_2P_CE_THRESHOLD 1
+#define RAS_DEFAULT_PROCESSOR_CE_THRESHOLD 1
+#define RAS_DEFAULT_DDR_LINK_ERROR_THRESHOLD 1
+
+
+HII_VENDOR_DEVICE_PATH mRasConfigHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ RAS_CONFIG_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+BOOLEAN
+IsDdrCeWindowEnabled (
+ VOID
+ )
+{
+ UINT32 DdrCeWindow;
+ EFI_STATUS Status;
+
+ Status = NVParamGet (
+ NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &DdrCeWindow
+ );
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+
+ return (DdrCeWindow != 0) ? TRUE : FALSE;
+}
+
+EFI_STATUS
+RasConfigNvParamGet (
+ OUT RAS_CONFIG_VARSTORE_DATA *Configuration
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ Status = NVParamGet (
+ NV_SI_HARDWARE_EINJ,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_HARDWARE_EINJ_SUPPORT;
+ Status = NVParamSet (
+ NV_SI_HARDWARE_EINJ,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasHardwareEinj = Value;
+
+ Status = NVParamGet (
+ NV_SI_RAS_PCIE_AER_FW_FIRST,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_PCIE_AER_FW_FIRST;
+ Status = NVParamSet (
+ NV_SI_RAS_PCIE_AER_FW_FIRST,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasPcieAerFwFirstEnabled = Value;
+
+ Status = NVParamGet (
+ NV_SI_RAS_BERT_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_BERT_SUPPORT;
+ Status = NVParamSet (
+ NV_SI_RAS_BERT_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasBertEnabled = Value;
+
+ Status = NVParamGet (
+ NV_SI_RAS_SDEI_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_SDEI_SUPPORT;
+ Status = NVParamSet (
+ NV_SI_RAS_SDEI_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasSdeiEnabled = Value;
+
+ Status = NVParamGet (
+ NV_SI_DDR_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_DDR_CE_THRESHOLD;
+ Status = NVParamSet (
+ NV_SI_DDR_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasDdrCeThreshold = Value;
+
+ Status = NVParamGet (
+ NV_SI_2P_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_2P_CE_THRESHOLD;
+ Status = NVParamSet (
+ NV_SI_2P_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->Ras2pCeThreshold = Value;
+
+ Status = NVParamGet (
+ NV_SI_CPM_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_PROCESSOR_CE_THRESHOLD;
+ Status = NVParamSet (
+ NV_SI_CPM_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasCpmCeThreshold = Value;
+
+ Status = NVParamGet (
+ NV_SI_LINK_ERR_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Value = RAS_DEFAULT_DDR_LINK_ERROR_THRESHOLD;
+ Status = NVParamSet (
+ NV_SI_LINK_ERR_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d NVParamSet() failed!\n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ Value = 0;
+ }
+ }
+ Configuration->RasLinkErrThreshold = Value;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+RasConfigNvParamSet (
+ IN RAS_CONFIG_VARSTORE_DATA *Configuration
+ )
+{
+ EFI_STATUS Status;
+
+ Status = NVParamSet (
+ NV_SI_HARDWARE_EINJ,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasHardwareEinj
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_RAS_PCIE_AER_FW_FIRST,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasPcieAerFwFirstEnabled
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_RAS_BERT_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasBertEnabled
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_RAS_SDEI_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasSdeiEnabled
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_DDR_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasDdrCeThreshold
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_2P_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->Ras2pCeThreshold
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_CPM_CE_RAS_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasCpmCeThreshold
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = NVParamSet (
+ NV_SI_LINK_ERR_THRESHOLD,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->RasLinkErrThreshold
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function allows a caller to extract the current configuration for one
+ or more named elements from the target driver.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Request A null-terminated Unicode string in
+ <ConfigRequest> format.
+ @param Progress On return, points to a character in the Request
+ string. Points to the string's null terminator if
+ request was successful. Points to the most recent
+ '&' before the first failing name/value pair (or
+ the beginning of the string if the failure is in
+ the first name/value pair) if the request was not
+ successful.
+ @param Results A null-terminated Unicode string in
+ <ConfigAltResp> format which has all values filled
+ in for the names in the Request string. String to
+ be allocated by the called function.
+
+ @retval EFI_SUCCESS The Results is filled with the requested values.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results.
+ @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+RasConfigExtractConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ RAS_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if (Progress == NULL || Results == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
+
+ if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &mRasConfigFormSetGuid, RasConfigVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+
+ //
+ // Get current setting from NVParam.
+ //
+ Status = RasConfigNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ BufferSize = sizeof (RAS_CONFIG_VARSTORE_DATA);
+ ConfigRequest = Request;
+ if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
+ //
+ // Request has no request element, construct full request string.
+ // Allocate and fill a buffer large enough to hold the <ConfigHdr> template
+ // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (&mRasConfigFormSetGuid, RasConfigVarstoreDataName, PrivateData->DriverHandle);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ if (ConfigRequest == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
+ FreePool (ConfigRequestHdr);
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ Status = HiiConfigRouting->BlockToConfig (
+ HiiConfigRouting,
+ ConfigRequest,
+ (UINT8 *)&PrivateData->Configuration,
+ BufferSize,
+ Results,
+ Progress
+ );
+
+ //
+ // Free the allocated config request string.
+ //
+ if (AllocatedRequest) {
+ FreePool (ConfigRequest);
+ ConfigRequest = NULL;
+ }
+
+ //
+ // Set Progress string to the original request string.
+ //
+ if (Request == NULL) {
+ *Progress = NULL;
+ } else if (StrStr (Request, L"OFFSET") == NULL) {
+ *Progress = Request + StrLen (Request);
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Configuration A null-terminated Unicode string in <ConfigResp>
+ format.
+ @param Progress A pointer to a string filled in with the offset of
+ the most recent '&' before the first failing
+ name/value pair (or the beginning of the string if
+ the failure is in the first name/value pair) or
+ the terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The Results is processed successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+RasConfigRouteConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ RAS_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ if (Configuration == NULL || Progress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+ *Progress = Configuration;
+
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Configuration, &mRasConfigFormSetGuid, RasConfigVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Get configuration data from NVParam
+ //
+ Status = RasConfigNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
+ //
+ BufferSize = sizeof (RAS_CONFIG_VARSTORE_DATA);
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Store configuration data back to NVParam
+ //
+ Status = RasConfigNvParamSet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
+
+**/
+EFI_STATUS
+EFIAPI
+RasConfigCallback (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+{
+ if (Action != EFI_BROWSER_ACTION_CHANGING) {
+ //
+ // Do nothing for other UEFI Action. Only do call back when data is changed.
+ //
+ return EFI_UNSUPPORTED;
+ }
+ if (((Value == NULL)
+ && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+UpdateRasConfigScreen (
+ IN RAS_CONFIG_PRIVATE_DATA *PrivateData
+ )
+{
+ EFI_STATUS Status;
+ VOID *StartOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+
+ //
+ // Initialize the container for dynamic opcodes
+ //
+ StartOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (StartOpCodeHandle != NULL);
+
+ EndOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (EndOpCodeHandle != NULL);
+
+ //
+ // Create Hii Extend Label OpCode as the start opcode
+ //
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ StartOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ if (StartLabel == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FreeOpCodeBuffer;
+ }
+ StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ StartLabel->Number = LABEL_UPDATE;
+
+ //
+ // Create Hii Extend Label OpCode as the end opcode
+ //
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ EndOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ if (EndLabel == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto FreeOpCodeBuffer;
+ }
+ EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ EndLabel->Number = LABEL_END;
+
+ //
+ // Create the numeric for DDR CE threshold
+ //
+ if (!IsDdrCeWindowEnabled ()) {
+ HiiCreateNumericOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ 0x8004, // Question ID
+ RAS_CONFIG_VARSTORE_ID, // VarStore ID
+ (UINT16)RAS_DDR_CE_THRESHOLD_OFST, // Offset in Buffer Storage
+ STRING_TOKEN (STR_RAS_DDR_CE_THRESHOLD_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_RAS_DDR_CE_THRESHOLD_HELP),
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 1,
+ 8192,
+ 1,
+ NULL
+ );
+ }
+
+ //
+ // Create the numeric for 2P CE threshold
+ //
+ if (IsSlaveSocketActive ()) {
+ HiiCreateNumericOpCode (
+ StartOpCodeHandle, // Container for dynamic created opcodes
+ 0x8005, // Question ID
+ RAS_CONFIG_VARSTORE_ID, // VarStore ID
+ (UINT16)RAS_2P_CE_THRESHOLD_OFST, // Offset in Buffer Storage
+ STRING_TOKEN (STR_RAS_2P_CE_THRESHOLD_PROMPT), // Question prompt text
+ STRING_TOKEN (STR_RAS_2P_CE_THRESHOLD_HELP),
+ EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED,
+ EFI_IFR_NUMERIC_SIZE_4,
+ 1,
+ 8192,
+ 1,
+ NULL
+ );
+ }
+
+ Status = HiiUpdateForm (
+ PrivateData->HiiHandle, // HII handle
+ &mRasConfigFormSetGuid, // Formset GUID
+ RAS_CONFIG_FORM_ID, // Form ID
+ StartOpCodeHandle, // Label for where to insert opcodes
+ EndOpCodeHandle // Insert data
+ );
+
+FreeOpCodeBuffer:
+ HiiFreeOpCodeHandle (StartOpCodeHandle);
+ HiiFreeOpCodeHandle (EndOpCodeHandle);
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+RasConfigUnload (
+ VOID
+ )
+{
+ ASSERT (mPrivateData != NULL);
+
+ if (mDriverHandle != NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mRasConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ mDriverHandle = NULL;
+ }
+
+ if (mPrivateData->HiiHandle != NULL) {
+ HiiRemovePackages (mPrivateData->HiiHandle);
+ }
+
+ FreePool (mPrivateData);
+ mPrivateData = NULL;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+RasConfigEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Initialize driver private data
+ //
+ mPrivateData = AllocateZeroPool (sizeof (RAS_CONFIG_PRIVATE_DATA));
+ if (mPrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->Signature = RAS_CONFIG_PRIVATE_SIGNATURE;
+
+ mPrivateData->ConfigAccess.ExtractConfig = RasConfigExtractConfig;
+ mPrivateData->ConfigAccess.RouteConfig = RasConfigRouteConfig;
+ mPrivateData->ConfigAccess.Callback = RasConfigCallback;
+
+ //
+ // Locate ConfigRouting protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID **)&HiiConfigRouting);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mPrivateData->HiiConfigRouting = HiiConfigRouting;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mRasConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mPrivateData->DriverHandle = mDriverHandle;
+
+ //
+ // Publish our HII data
+ //
+ HiiHandle = HiiAddPackages (
+ &mRasConfigFormSetGuid,
+ mDriverHandle,
+ RasConfigDxeStrings,
+ RasConfigVfrBin,
+ NULL
+ );
+ if (HiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mRasConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->HiiHandle = HiiHandle;
+
+ Status = UpdateRasConfigScreen (mPrivateData);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a %d Fail to update Memory Configuration screen \n",
+ __FUNCTION__,
+ __LINE__
+ ));
+ RasConfigUnload ();
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigStrings.uni
new file mode 100644
index 000000000000..c502093a2bbf
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigStrings.uni
@@ -0,0 +1,38 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English"
+
+#string STR_RAS_FORM #language en-US "RAS Configuration"
+#string STR_RAS_FORM_HELP #language en-US "RAS Configuration"
+
+#string STR_RAS_FORM_SEPERATE_LINE #language en-US ""
+#string STR_RAS_COMMON_ENABLE #language en-US "Enabled"
+#string STR_RAS_COMMON_DISABLE #language en-US "Disabled"
+
+#string STR_RAS_HARDWARE_EINJ_PROMPT #language en-US "Hardware EINJ"
+#string STR_RAS_HARDWARE_EINJ_HELP #language en-US "Enable hardware EINJ support, if disabled EINJ is software simulated"
+
+#string STR_RAS_PCIE_AER_FW_FIRST_PROMPT #language en-US "PCIe AER Firmware First"
+#string STR_RAS_PCIE_AER_FW_FIRST_HELP #language en-US "Enable firmware to detect PCIe AER, if disabled OS detects AER"
+
+#string STR_RAS_BERT_ENABLED_PROMPT #language en-US "Enable BERT"
+#string STR_RAS_BERT_ENABLED_HELP #language en-US "Enable Boot Error Record Table, if disabled BERT will not be populated"
+
+#string STR_RAS_SDEI_ENABLED_PROMPT #language en-US "Enable SDEI"
+#string STR_RAS_SDEI_ENABLED_HELP #language en-US "Enable Software Delegated Exception Interface for NMI support"
+
+#string STR_RAS_DDR_CE_THRESHOLD_PROMPT #language en-US "DDR CE Threshold"
+#string STR_RAS_DDR_CE_THRESHOLD_HELP #language en-US "Number of DDR CEs to occur before using SCI notification to OS rather than polled notification"
+
+#string STR_RAS_2P_CE_THRESHOLD_PROMPT #language en-US "2P CE Threshold"
+#string STR_RAS_2P_CE_THRESHOLD_HELP #language en-US "Number of 2P CEs to occur before using SCI notification to OS rather than polled notification"
+
+#string STR_RAS_CPM_CE_THRESHOLD_PROMPT #language en-US "Processor CE Threshold"
+#string STR_RAS_CPM_CE_THRESHOLD_HELP #language en-US "Number of processor CEs to occur before using SCI notification to OS rather than polled notification"
+
+#string STR_RAS_LINK_ERR_THRESHOLD_PROMPT #language en-US "DDR Link Error Threshold"
+#string STR_RAS_LINK_ERR_THRESHOLD_HELP #language en-US "Number of DDR link errors before considering it fatal severity"
--
2.17.1


[PATCH v3 25/28] AmpereAltraPkg: Add configuration screen for ACPI

Nhi Pham
 

This supports:
* Enable/Disable APEI Support
* Enable/Disable CPPC Support
* Enable/Disable LPI support
* Enable/Disable Max Performance Mode

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 3 +
Platform/Ampere/JadePkg/Jade.dsc | 1 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 1 +
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf | 58 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h | 7 +-
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h | 62 ++
Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h | 28 +
Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigFormSet.h | 19 +
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr | 69 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c | 25 +-
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c | 729 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigStrings.uni | 27 +
13 files changed, 1026 insertions(+), 4 deletions(-)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
index 6ea247c75e87..196611d67280 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
@@ -53,6 +53,9 @@ [Guids]
# GUID for the CPU HII configuration form
gCpuConfigFormSetGuid = { 0x43FAA144, 0xA2DF, 0x4050, { 0xA7, 0xFD, 0xEE, 0x17, 0xC9, 0xB8, 0x88, 0x8E } }

+ # GUID for the ACPI HII configuration form
+ gAcpiConfigFormSetGuid = { 0x0ceb6764, 0xd415, 0x4b01, { 0xa8, 0x43, 0xd1, 0x01, 0xbc, 0xb0, 0xd8, 0x29 } }
+
## NVParam MM GUID
gNVParamMmGuid = { 0xE4AC5024, 0x29BE, 0x4ADC, { 0x93, 0x36, 0x87, 0xB5, 0xA0, 0x76, 0x23, 0x2D } }

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index 8ca3a729728f..daac52e84ea2 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -199,3 +199,4 @@ [Components.common]
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index d9552886fbcf..1564e45c30cd 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -357,5 +357,6 @@ [FV.FvMain]
INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf

!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
index 2b2a3728a406..a2b3886a0236 100644
--- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -66,6 +66,7 @@ [Guids]
gArmMpCoreInfoGuid
gEfiAcpiTableGuid
gEfiEventReadyToBootGuid
+ gAcpiConfigFormSetGuid
gPlatformHobGuid

[Protocols]
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
new file mode 100644
index 000000000000..075183aa9c58
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = AcpiConfigDxe
+ FILE_GUID = F36685AE-2623-4231-ABC0-2C151451E6B7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiConfigEntryPoint
+
+[Sources.common]
+ AcpiConfigDxe.c
+ AcpiConfigDxe.h
+ AcpiConfigVfr.vfr
+ AcpiConfigStrings.uni
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AcpiLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ HiiLib
+ HobLib
+ MemoryAllocationLib
+ SystemFirmwareInterfaceLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gPlatformManagerFormsetGuid
+ gAcpiConfigFormSetGuid
+ gEfiEventReadyToBootGuid
+ gPlatformHobGuid
+
+[Protocols]
+ gEfiAcpiSdtProtocolGuid ## COMSUMES
+ gEfiDevicePathProtocolGuid ## CONSUMES
+ gEfiHiiConfigRoutingProtocolGuid ## CONSUMES
+ gEfiHiiConfigAccessProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
index 2e763422cbc6..035912a1a331 100644
--- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
@@ -9,7 +9,9 @@
#ifndef ACPI_APEI_H_
#define ACPI_APEI_H_

+#include <AcpiConfigNVDataStruct.h>
#include <Base.h>
+#include <Guid/AcpiConfigFormSet.h>
#include <IndustryStandard/Acpi63.h>
#include <Library/AcpiLib.h>
#include <Library/AmpereCpuLib.h>
@@ -34,9 +36,10 @@
#define PLAT_CRASH_ITERATOR_SIZE 0x398
#define SMPRO_CRASH_SIZE 0x800
#define PMPRO_CRASH_SIZE 0x800
+#define RASIP_CRASH_SIZE 0x1000
#define HEST_NUM_ENTRIES_PER_SOC 3

-#define CURRENT_BERT_VERSION 0x10
+#define CURRENT_BERT_VERSION 0x11
#define BERT_FLASH_OFFSET 0x91B30000ULL
#define BERT_DDR_OFFSET 0x88230000ULL
#define BERT_DDR_LENGTH 0x50000
@@ -53,8 +56,10 @@ typedef struct {
UINT8 BertRev;
UINT8 S0PmproRegisters[PMPRO_CRASH_SIZE];
UINT8 S0SmproRegisters[SMPRO_CRASH_SIZE];
+ UINT8 S0RasIpRegisters[RASIP_CRASH_SIZE];
UINT8 S1PmproRegisters[PMPRO_CRASH_SIZE];
UINT8 S1SmproRegisters[SMPRO_CRASH_SIZE];
+ UINT8 S1RasIpRegisters[RASIP_CRASH_SIZE];
UINT8 AtfDump[PLATFORM_CPU_MAX_NUM_CORES * PLAT_CRASH_ITERATOR_SIZE];
} APEI_CRASH_DUMP_DATA;

diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h
new file mode 100644
index 000000000000..8a2cc2f5e679
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_CONFIG_DXE_H_
+#define ACPI_CONFIG_DXE_H_
+
+//
+// This is the generated IFR binary data for each formset defined in VFR.
+//
+extern UINT8 AcpiConfigVfrBin[];
+
+//
+// This is the generated String package data for all .UNI files.
+//
+extern UINT8 AcpiConfigDxeStrings[];
+
+//
+// Signature: Ampere Computing ACPI Configuration
+//
+#define ACPI_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('A', 'C', 'A', 'C')
+
+typedef struct {
+ UINTN Signature;
+
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ ACPI_CONFIG_VARSTORE_DATA Configuration;
+ PLATFORM_INFO_HOB *PlatformHob;
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
+ EFI_ACPI_HANDLE AcpiTableHandle;
+
+ //
+ // Consumed protocol
+ //
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Produced protocol
+ //
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+} ACPI_CONFIG_PRIVATE_DATA;
+
+#define ACPI_CONFIG_PRIVATE_FROM_THIS(a) CR (a, ACPI_CONFIG_PRIVATE_DATA, ConfigAccess, ACPI_CONFIG_PRIVATE_SIGNATURE)
+
+#pragma pack(1)
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h
new file mode 100644
index 000000000000..a56bfa9aa694
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h
@@ -0,0 +1,28 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_CONFIG_NV_DATA_STRUC_H_
+#define ACPI_CONFIG_NV_DATA_STRUC_H_
+
+#pragma pack(1)
+
+//
+// ACPI Configuration NV data structure definition
+//
+typedef struct {
+ UINT32 EnableApeiSupport;
+ UINT32 AcpiCppcEnable;
+ UINT32 AcpiLpiEnable;
+ UINT32 AcpiTurboSupport;
+ UINT32 AcpiTurboMode;
+ UINT32 Reserved[4];
+} ACPI_CONFIG_VARSTORE_DATA;
+
+#pragma pack()
+
+#endif /* ACPI_CONFIG_NV_DATA_STRUC_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigFormSet.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigFormSet.h
new file mode 100644
index 000000000000..1779a4543769
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigFormSet.h
@@ -0,0 +1,19 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_CONFIG_FORMSET_GUID_H_
+#define ACPI_CONFIG_FORMSET_GUID_H_
+
+#define ACPI_CONFIGURATION_FORMSET_GUID \
+ { \
+ 0x0ceb6764, 0xd415, 0x4b01, { 0xa8, 0x43, 0xd1, 0x01, 0xbc, 0xb0, 0xd8, 0x29 } \
+ }
+
+extern EFI_GUID gAcpiConfigFormSetGuid;
+
+#endif /* ACPI_CONFIG_FORMSET_GUID_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr
new file mode 100644
index 000000000000..18b44f90ddd9
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigVfr.vfr
@@ -0,0 +1,69 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <Guid/AcpiConfigFormSet.h>
+#include <AcpiConfigNVDataStruct.h>
+
+#define ACPI_CONFIG_FORM_ID 1
+
+formset
+ guid = ACPI_CONFIGURATION_FORMSET_GUID,
+ title = STRING_TOKEN(STR_ACPI_FORM),
+ help = STRING_TOKEN(STR_ACPI_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ varstore ACPI_CONFIG_VARSTORE_DATA,
+ name = AcpiConfigNVData,
+ guid = ACPI_CONFIGURATION_FORMSET_GUID;
+
+ form
+ formid = ACPI_CONFIG_FORM_ID,
+ title = STRING_TOKEN(STR_ACPI_FORM);
+ subtitle text = STRING_TOKEN(STR_ACPI_FORM_HELP);
+
+ oneof
+ varid = AcpiConfigNVData.EnableApeiSupport,
+ prompt = STRING_TOKEN(STR_ACPI_APEI_SUPPORT_PROMPT),
+ help = STRING_TOKEN(STR_ACPI_APEI_SUPPORT_HELP),
+ option text = STRING_TOKEN(STR_ACPI_COMMON_DISABLE), value = 0, flags = 0;
+ option text = STRING_TOKEN(STR_ACPI_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ endoneof;
+
+ oneof
+ varid = AcpiConfigNVData.AcpiCppcEnable,
+ prompt = STRING_TOKEN(STR_ACPI_CPPC_PROMPT),
+ help = STRING_TOKEN(STR_ACPI_CPPC_HELP),
+ option text = STRING_TOKEN(STR_ACPI_COMMON_DISABLE), value = 0, flags = 0;
+ option text = STRING_TOKEN(STR_ACPI_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ endoneof;
+
+ oneof
+ varid = AcpiConfigNVData.AcpiLpiEnable,
+ prompt = STRING_TOKEN(STR_ACPI_LPI_PROMPT),
+ help = STRING_TOKEN(STR_ACPI_LPI_HELP),
+ option text = STRING_TOKEN(STR_ACPI_COMMON_DISABLE), value = 0, flags = 0;
+ option text = STRING_TOKEN(STR_ACPI_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ endoneof;
+
+ grayoutif ideqval AcpiConfigNVData.AcpiTurboSupport == 0;
+ oneof
+ varid = AcpiConfigNVData.AcpiTurboMode,
+ prompt = STRING_TOKEN(STR_ACPI_TURBO_PROMPT),
+ help = STRING_TOKEN(STR_ACPI_TURBO_HELP),
+ option text = STRING_TOKEN(STR_ACPI_COMMON_ENABLE), value = 1, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ACPI_COMMON_DISABLE), value = 0, flags = 0;
+ suppressif ideqval AcpiConfigNVData.AcpiTurboSupport > 0;
+ option text = STRING_TOKEN(STR_ACPI_UNSUPPORTED), value = 2, flags = 0;
+ endif;
+ endoneof;
+ endif;
+
+ endform;
+
+endformset;
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
index a216edac60ce..8a46e038c1a7 100644
--- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
@@ -149,7 +149,7 @@ WrapBertErrorData (
CrashSize = PLAT_CRASH_ITERATOR_SIZE *
GetNumberOfSupportedSockets () *
GetMaximumNumberOfCores ();
- CrashSize += 2 * (SMPRO_CRASH_SIZE + PMPRO_CRASH_SIZE);
+ CrashSize += 2 * (SMPRO_CRASH_SIZE + PMPRO_CRASH_SIZE + RASIP_CRASH_SIZE);
CrashSize += sizeof (WrappedError->Bed.Vendor) + sizeof (WrappedError->Bed.BertRev);

WrappedError->Ges.BlockStatus.ErrorDataEntryCount = 1;
@@ -437,8 +437,27 @@ AcpiApeiUpdate (
VOID
)
{
- if (!IsSlaveSocketActive ()) {
- AcpiApeiHestUpdateTable1P ();
+ EFI_STATUS Status;
+ ACPI_CONFIG_VARSTORE_DATA AcpiConfigData;
+ UINTN BufferSize;
+
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ Status = gRT->GetVariable (
+ L"AcpiConfigNVData",
+ &gAcpiConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &AcpiConfigData
+ );
+ if (!EFI_ERROR (Status) && (AcpiConfigData.EnableApeiSupport == 0)) {
+ AcpiApeiUninstallTable (EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE);
+ AcpiApeiUninstallTable (EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE);
+ AcpiApeiUninstallTable (EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE);
+ AcpiApeiUninstallTable (EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE);
+ } else {
+ if (!IsSlaveSocketActive ()) {
+ AcpiApeiHestUpdateTable1P ();
+ }
}

if (!IsSdeiEnabled ()) {
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c
new file mode 100644
index 000000000000..d085389d2865
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c
@@ -0,0 +1,729 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <AcpiConfigNVDataStruct.h>
+#include <Guid/AcpiConfigFormSet.h>
+#include <Guid/MdeModuleHii.h>
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Library/AcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/SystemFirmwareInterfaceLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Protocol/HiiConfigAccess.h>
+#include <Protocol/HiiConfigRouting.h>
+
+#include "AcpiConfigDxe.h"
+
+#define ACPI_VARSTORE_ATTRIBUTES EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+ EFI_VARIABLE_RUNTIME_ACCESS | \
+ EFI_VARIABLE_NON_VOLATILE
+
+CHAR16 AcpiVarstoreDataName[] = L"AcpiConfigNVData";
+
+EFI_HANDLE mDriverHandle = NULL;
+ACPI_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+
+HII_VENDOR_DEVICE_PATH mAcpiConfigHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ ACPI_CONFIGURATION_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+/**
+ This function allows a caller to extract the current configuration for one
+ or more named elements from the target driver.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Request A null-terminated Unicode string in
+ <ConfigRequest> format.
+ @param Progress On return, points to a character in the Request
+ string. Points to the string's null terminator if
+ request was successful. Points to the most recent
+ '&' before the first failing name/value pair (or
+ the beginning of the string if the failure is in
+ the first name/value pair) if the request was not
+ successful.
+ @param Results A null-terminated Unicode string in
+ <ConfigAltResp> format which has all values filled
+ in for the names in the Request string. String to
+ be allocated by the called function.
+
+ @retval EFI_SUCCESS The Results is filled with the requested values.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results.
+ @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+ExtractConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ ACPI_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if (Progress == NULL || Results == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
+
+ if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &gAcpiConfigFormSetGuid, AcpiVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+
+ //
+ // Get Buffer Storage data from EFI variable.
+ // Try to get the current setting from variable.
+ //
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ Status = gRT->GetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ ConfigRequest = Request;
+ if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
+ //
+ // Request has no request element, construct full request string.
+ // Allocate and fill a buffer large enough to hold the <ConfigHdr> template
+ // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (
+ &gAcpiConfigFormSetGuid,
+ AcpiVarstoreDataName,
+ PrivateData->DriverHandle
+ );
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ if (ConfigRequest == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
+ FreePool (ConfigRequestHdr);
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ Status = HiiConfigRouting->BlockToConfig (
+ HiiConfigRouting,
+ ConfigRequest,
+ (UINT8 *)&PrivateData->Configuration,
+ BufferSize,
+ Results,
+ Progress
+ );
+
+ //
+ // Free the allocated config request string.
+ //
+ if (AllocatedRequest) {
+ FreePool (ConfigRequest);
+ ConfigRequest = NULL;
+ }
+
+ //
+ // Set Progress string to the original request string.
+ //
+ if (Request == NULL) {
+ *Progress = NULL;
+ } else if (StrStr (Request, L"OFFSET") == NULL) {
+ *Progress = Request + StrLen (Request);
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Configuration A null-terminated Unicode string in <ConfigResp>
+ format.
+ @param Progress A pointer to a string filled in with the offset of
+ the most recent '&' before the first failing
+ name/value pair (or the beginning of the string if
+ the failure is in the first name/value pair) or
+ the terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The Results is processed successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+RouteConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ ACPI_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ if (Configuration == NULL || Progress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+ *Progress = Configuration;
+
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Configuration, &gAcpiConfigFormSetGuid, AcpiVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Get Buffer Storage data from EFI variable
+ //
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ Status = gRT->GetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
+ //
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Store Buffer Storage back to EFI variable
+ //
+ Status = gRT->SetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ ACPI_VARSTORE_ATTRIBUTES,
+ sizeof (ACPI_CONFIG_VARSTORE_DATA),
+ &PrivateData->Configuration
+ );
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
+
+**/
+EFI_STATUS
+EFIAPI
+DriverCallback (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+{
+ if (Action != EFI_BROWSER_ACTION_CHANGING) {
+ //
+ // Do nothing for other UEFI Action. Only do call back when data is changed.
+ //
+ return EFI_UNSUPPORTED;
+ }
+ if (((Value == NULL)
+ && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+AcpiNVDataUpdate (
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ )
+{
+ EFI_STATUS Status;
+ PLATFORM_INFO_HOB *PlatformHob;
+ UINT32 TurboSupport;
+
+ ASSERT (PrivateData != NULL);
+
+ PlatformHob = PrivateData->PlatformHob;
+ TurboSupport = PlatformHob->TurboCapability[0] + PlatformHob->TurboCapability[1];
+
+ if (TurboSupport == 0) {
+ PrivateData->Configuration.AcpiTurboMode = 2; // Unsupported mode
+ PrivateData->Configuration.AcpiTurboSupport = 0;
+ } else {
+ PrivateData->Configuration.AcpiTurboSupport = 1;
+ }
+
+ Status = gRT->SetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ ACPI_VARSTORE_ATTRIBUTES,
+ sizeof (ACPI_CONFIG_VARSTORE_DATA),
+ &PrivateData->Configuration
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a %d gRT->SetVariable() failed \n", __FUNCTION__, __LINE__));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+UpdateTurboModeConfig (
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ )
+{
+ EFI_STATUS Status;
+ PLATFORM_INFO_HOB *PlatformHob;
+ BOOLEAN EnableTurbo;
+
+ ASSERT (PrivateData != NULL);
+
+ if (PrivateData->Configuration.AcpiTurboSupport != 0) {
+ PlatformHob = PrivateData->PlatformHob;
+ EnableTurbo = (PrivateData->Configuration.AcpiTurboMode != 0) ? TRUE : FALSE;
+
+ if (PlatformHob->TurboCapability[0] != 0) {
+ Status = MailboxMsgTurboConfig (0, EnableTurbo);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ if (PlatformHob->TurboCapability[1] != 0) {
+ Status = MailboxMsgTurboConfig (1, EnableTurbo);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "%a: Turbo mode is unsupported! \n", __FUNCTION__));
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+UpdateCPPCConfig (
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ )
+{
+ EFI_STATUS Status;
+ CHAR8 Buffer[64];
+
+ ASSERT (PrivateData != NULL);
+
+ AsciiSPrint (Buffer, sizeof (Buffer), "\\_SB.CPCE");
+ Status = AcpiAmlObjectUpdateInteger (
+ PrivateData->AcpiSdtProtocol,
+ PrivateData->AcpiTableHandle,
+ Buffer,
+ PrivateData->Configuration.AcpiCppcEnable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+UpdateLPIConfig (
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ )
+{
+ EFI_STATUS Status;
+ CHAR8 Buffer[64];
+
+ ASSERT (PrivateData != NULL);
+
+ AsciiSPrint (Buffer, sizeof (Buffer), "\\_SB.LPIE");
+ Status = AcpiAmlObjectUpdateInteger (
+ PrivateData->AcpiSdtProtocol,
+ PrivateData->AcpiTableHandle,
+ Buffer,
+ PrivateData->Configuration.AcpiLpiEnable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+STATIC
+VOID
+UpdateAcpiOnReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
+ EFI_ACPI_DESCRIPTION_HEADER *Table;
+ EFI_ACPI_HANDLE TableHandle;
+ UINTN TableKey;
+ UINTN TableIndex;
+
+ ASSERT (mPrivateData != NULL);
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSdtProtocolGuid,
+ NULL,
+ (VOID **)&AcpiSdtProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to locate ACPI table protocol\n"));
+ return;
+ }
+
+ mPrivateData->AcpiSdtProtocol = AcpiSdtProtocol;
+
+ TableIndex = 0;
+ Status = AcpiLocateTableBySignature (
+ AcpiSdtProtocol,
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ &TableIndex,
+ &Table,
+ &TableKey
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = AcpiSdtProtocol->OpenSdt (TableKey, &TableHandle);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ mPrivateData->AcpiTableHandle = TableHandle;
+
+ Status = UpdateCPPCConfig (mPrivateData);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = UpdateLPIConfig (mPrivateData);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = UpdateTurboModeConfig (mPrivateData);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // Close DSDT Table
+ //
+ AcpiSdtProtocol->Close (TableHandle);
+ AcpiUpdateChecksum ((UINT8 *)Table, Table->Length);
+}
+
+STATIC
+EFI_STATUS
+AcpiConfigUnload (
+ VOID
+ )
+{
+ ASSERT (mPrivateData != NULL);
+
+ if (mDriverHandle != NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mAcpiConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ mDriverHandle = NULL;
+ }
+
+ if (mPrivateData->HiiHandle != NULL) {
+ HiiRemovePackages (mPrivateData->HiiHandle);
+ }
+
+ FreePool (mPrivateData);
+ mPrivateData = NULL;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+AcpiConfigEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ UINTN BufferSize;
+ ACPI_CONFIG_VARSTORE_DATA *Configuration;
+ BOOLEAN ActionFlag;
+ EFI_STRING ConfigRequestHdr;
+ EFI_EVENT ReadyToBootEvent;
+ PLATFORM_INFO_HOB *PlatformHob;
+ VOID *Hob;
+
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+
+ //
+ // Initialize driver private data
+ //
+ mPrivateData = AllocateZeroPool (sizeof (ACPI_CONFIG_PRIVATE_DATA));
+ if (mPrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->Signature = ACPI_CONFIG_PRIVATE_SIGNATURE;
+
+ mPrivateData->ConfigAccess.ExtractConfig = ExtractConfig;
+ mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
+ mPrivateData->ConfigAccess.Callback = DriverCallback;
+
+ //
+ // Get the Platform HOB
+ //
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ ASSERT (Hob != NULL);
+ if (Hob == NULL) {
+ AcpiConfigUnload ();
+ return EFI_DEVICE_ERROR;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ mPrivateData->PlatformHob = PlatformHob;
+
+ //
+ // Locate ConfigRouting protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID **)&HiiConfigRouting);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mPrivateData->HiiConfigRouting = HiiConfigRouting;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mAcpiConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mPrivateData->DriverHandle = mDriverHandle;
+
+ //
+ // Publish our HII data
+ //
+ HiiHandle = HiiAddPackages (
+ &gAcpiConfigFormSetGuid,
+ mDriverHandle,
+ AcpiConfigDxeStrings,
+ AcpiConfigVfrBin,
+ NULL
+ );
+ if (HiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mAcpiConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->HiiHandle = HiiHandle;
+
+ //
+ // Initialize configuration data
+ //
+ Configuration = &mPrivateData->Configuration;
+ ZeroMem (Configuration, sizeof (ACPI_CONFIG_VARSTORE_DATA));
+
+ //
+ // Try to read NV config EFI variable first
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (&gAcpiConfigFormSetGuid, AcpiVarstoreDataName, mDriverHandle);
+ ASSERT (ConfigRequestHdr != NULL);
+
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ Status = gRT->GetVariable (AcpiVarstoreDataName, &gAcpiConfigFormSetGuid, NULL, &BufferSize, Configuration);
+ if (EFI_ERROR (Status)) {
+ //
+ // Store zero data Buffer Storage to EFI variable
+ //
+ Status = gRT->SetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ ACPI_VARSTORE_ATTRIBUTES,
+ sizeof (ACPI_CONFIG_VARSTORE_DATA),
+ Configuration
+ );
+ if (EFI_ERROR (Status)) {
+ AcpiConfigUnload ();
+ return Status;
+ }
+ //
+ // EFI variable for NV config doesn't exit, we should build this variable
+ // based on default values stored in IFR
+ //
+ ActionFlag = HiiSetToDefaults (ConfigRequestHdr, EFI_HII_DEFAULT_CLASS_STANDARD);
+ if (!ActionFlag) {
+ AcpiConfigUnload ();
+ return EFI_INVALID_PARAMETER;
+ }
+ } else {
+ //
+ // EFI variable does exist and Validate Current Setting
+ //
+ ActionFlag = HiiValidateSettings (ConfigRequestHdr);
+ if (!ActionFlag) {
+ AcpiConfigUnload ();
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+ FreePool (ConfigRequestHdr);
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ UpdateAcpiOnReadyToBoot,
+ NULL,
+ &gEfiEventReadyToBootGuid,
+ &ReadyToBootEvent
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to create ready to boot event %r!\n", Status));
+ return Status;
+ }
+
+ Status = AcpiNVDataUpdate (mPrivateData);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigStrings.uni
new file mode 100644
index 000000000000..21a6188518fd
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigStrings.uni
@@ -0,0 +1,27 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English"
+
+#string STR_ACPI_FORM #language en-US "ACPI Configuration"
+#string STR_ACPI_FORM_HELP #language en-US "ACPI Configuration"
+
+#string STR_ACPI_FORM_SEPERATE_LINE #language en-US ""
+#string STR_ACPI_COMMON_ENABLE #language en-US "Enabled"
+#string STR_ACPI_COMMON_DISABLE #language en-US "Disabled"
+#string STR_ACPI_UNSUPPORTED #language en-US "Unsupported"
+
+#string STR_ACPI_APEI_SUPPORT_PROMPT #language en-US "APEI Support"
+#string STR_ACPI_APEI_SUPPORT_HELP #language en-US "Enable/Disable ACPI Platform Error Interface support"
+
+#string STR_ACPI_CPPC_PROMPT #language en-US "CPPC Support"
+#string STR_ACPI_CPPC_HELP #language en-US "Enables or Disables System ability to CPPC (Collaborative Processor Performance Control)"
+
+#string STR_ACPI_LPI_PROMPT #language en-US "LPI Support"
+#string STR_ACPI_LPI_HELP #language en-US "Enables or Disables System ability to LPI (Lower Power Idle)"
+
+#string STR_ACPI_TURBO_PROMPT #language en-US "Max Performance"
+#string STR_ACPI_TURBO_HELP #language en-US "Enables or Disables System ability to Max Performance"
--
2.17.1


[PATCH v3 24/28] AmpereAltraPkg: Add configuration screen for CPU

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

This screen is to add configuration regarding CPU. Currently, this
screen just adds a option for SubNUMA mode selection.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 3 +
Platform/Ampere/JadePkg/Jade.dsc | 1 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf | 58 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h | 52 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigNVDataStruc.h | 19 +
Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h | 19 +
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigVfr.vfr | 43 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c | 530 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigStrings.uni | 17 +
10 files changed, 743 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
index 93da9b38def5..6ea247c75e87 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
@@ -50,6 +50,9 @@ [LibraryClasses]
TrngLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h

[Guids]
+ # GUID for the CPU HII configuration form
+ gCpuConfigFormSetGuid = { 0x43FAA144, 0xA2DF, 0x4050, { 0xA7, 0xFD, 0xEE, 0x17, 0xC9, 0xB8, 0x88, 0x8E } }
+
## NVParam MM GUID
gNVParamMmGuid = { 0xE4AC5024, 0x29BE, 0x4ADC, { 0x93, 0x36, 0x87, 0xB5, 0xA0, 0x76, 0x23, 0x2D } }

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index 5fc83745cdbc..8ca3a729728f 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -198,3 +198,4 @@ [Components.common]
#
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 6fe023025034..d9552886fbcf 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -356,5 +356,6 @@ [FV.FvMain]
#
INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoDxe.inf
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf

!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
new file mode 100644
index 000000000000..2b13ef526685
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = CpuConfigDxe
+ MODULE_UNI_FILE = CpuConfigDxe.uni
+ FILE_GUID = A20D8E6E-EE6C-43C5-809F-19BB930653AE
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = CpuConfigDxeEntryPoint
+
+[Sources.common]
+ CpuConfigDxe.c
+ CpuConfigDxe.h
+ CpuConfigNVDataStruc.h
+ CpuConfigVfr.vfr
+ CpuConfigStrings.uni
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ DebugLib
+ DevicePathLib
+ HiiLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ NVParamLib
+ PcdLib
+ PrintLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+
+[Protocols]
+ gEfiHiiConfigRoutingProtocolGuid ## CONSUMES
+ gEfiHiiConfigAccessProtocolGuid ## PRODUCES
+ gEfiDevicePathProtocolGuid ## PRODUCES
+
+[Guids]
+ gCpuConfigFormSetGuid
+ gPlatformManagerFormsetGuid
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h
new file mode 100644
index 000000000000..b7e74a09da5b
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h
@@ -0,0 +1,52 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_CONFIG_H_
+#define CPU_CONFIG_H_
+
+#include "CpuConfigNVDataStruc.h"
+
+//
+// This is the generated IFR binary data for each formset defined in VFR.
+//
+extern UINT8 CpuConfigVfrBin[];
+
+//
+// This is the generated String package data for all .UNI files.
+//
+extern UINT8 CpuConfigDxeStrings[];
+
+#define CPU_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('C', 'P', 'U', '_')
+
+typedef struct {
+ UINTN Signature;
+
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ CPU_VARSTORE_DATA Configuration;
+
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+} CPU_CONFIG_PRIVATE_DATA;
+
+#define CPU_CONFIG_PRIVATE_FROM_THIS(a) CR (a, CPU_CONFIG_PRIVATE_DATA, ConfigAccess, CPU_CONFIG_PRIVATE_SIGNATURE)
+
+#pragma pack(1)
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+#endif /* CPU_CONFIG_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigNVDataStruc.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigNVDataStruc.h
new file mode 100644
index 000000000000..dbcaebded1b7
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigNVDataStruc.h
@@ -0,0 +1,19 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_CONFIG_NV_DATA_STRUC_H_
+#define CPU_CONFIG_NV_DATA_STRUC_H_
+
+#pragma pack(1)
+typedef struct {
+ UINT32 CpuSubNumaMode;
+} CPU_VARSTORE_DATA;
+
+#pragma pack()
+
+#endif /* CPU_CONFIG_NV_DATA_STRUC_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h
new file mode 100644
index 000000000000..71c8492f76a1
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h
@@ -0,0 +1,19 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_CONFIG_HII_H_
+#define CPU_CONFIG_HII_H_
+
+#define CPU_CONFIGURATION_FORMSET_GUID \
+ { \
+ 0x43FAA144, 0xA2DF, 0x4050, { 0xA7, 0xFD, 0xEE, 0x17, 0xC9, 0xB8, 0x88, 0x8E } \
+ }
+
+extern EFI_GUID gCpuConfigFormSetGuid;
+
+#endif /* CPU_CONFIG_HII_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigVfr.vfr
new file mode 100644
index 000000000000..8e68b1e9dcb7
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigVfr.vfr
@@ -0,0 +1,43 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Guid/PlatformManagerHii.h>
+#include <Guid/CpuConfigHii.h>
+#include "CpuConfigNVDataStruc.h"
+
+#define SUBNUMA_MODE_FORM_ID 1
+
+formset
+ guid = CPU_CONFIGURATION_FORMSET_GUID,
+ title = STRING_TOKEN(STR_CPU_FORM),
+ help = STRING_TOKEN(STR_CPU_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ varstore CPU_VARSTORE_DATA,
+ name = CpuConfigNVData,
+ guid = CPU_CONFIGURATION_FORMSET_GUID;
+
+ form
+ formid = SUBNUMA_MODE_FORM_ID,
+ title = STRING_TOKEN(STR_CPU_FORM);
+ subtitle text = STRING_TOKEN(STR_CPU_FORM_HELP);
+
+ oneof
+ varid = CpuConfigNVData.CpuSubNumaMode,
+ prompt = STRING_TOKEN(STR_CPU_SUBNUMA_MODE_PROMPT),
+ help = STRING_TOKEN(STR_CPU_SUBNUMA_MODE_HELP),
+ flags = RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_CPU_SUBNUMA_MODE_MONOLITHIC), value = 0x0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_CPU_SUBNUMA_MODE_HEMISPHERE), value = 0x1, flags = 0;
+ option text = STRING_TOKEN(STR_CPU_SUBNUMA_MODE_QUADRANT), value = 0x2, flags = 0;
+ endoneof;
+
+ endform;
+
+endformset;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c
new file mode 100644
index 000000000000..a5cab9eb8d9a
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c
@@ -0,0 +1,530 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Guid/CpuConfigHii.h>
+#include <Guid/MdeModuleHii.h>
+#include <Guid/PlatformManagerHii.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NVParamLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <NVParamDef.h>
+#include <Protocol/HiiConfigAccess.h>
+#include <Protocol/HiiConfigRouting.h>
+
+#include "CpuConfigDxe.h"
+
+//
+// Default settings definitions
+//
+#define NV_SI_SUBNUMA_MODE_DEFAULT 0x00 /* Monolithic mode */
+#define WA_ERRATUM_1542419_DEFAULT 0x00 /* Disable I-Cache coherency */
+#define NEAR_ATOMIC_DISABLE_DEFAULT 0x00 /* Enable Near Atomic */
+#define CPU_SLC_REPLACE_POLICY 0x00 /* eLRU */
+
+CHAR16 CpuVarstoreDataName[] = L"CpuConfigNVData";
+
+EFI_HANDLE mDriverHandle = NULL;
+CPU_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+
+HII_VENDOR_DEVICE_PATH mCpuConfigHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ CPU_CONFIGURATION_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+STATIC
+EFI_STATUS
+CpuNvParamGet (
+ OUT CPU_VARSTORE_DATA *Configuration
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ ASSERT (Configuration != NULL);
+
+ Status = NVParamGet (
+ NV_SI_SUBNUMA_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a %d Fail to write NVParam \n", __FUNCTION__, __LINE__));
+ Configuration->CpuSubNumaMode = SUBNUMA_MODE_MONOLITHIC;
+ } else {
+ Configuration->CpuSubNumaMode = Value;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+CpuNvParamSet (
+ IN CPU_VARSTORE_DATA *Configuration
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ ASSERT (Configuration != NULL);
+
+ Status = NVParamGet (
+ NV_SI_SUBNUMA_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status) || Value != Configuration->CpuSubNumaMode) {
+ Status = NVParamSet (
+ NV_SI_SUBNUMA_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ Configuration->CpuSubNumaMode
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a %d Fail to access NVParam \n", __FUNCTION__, __LINE__));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SetupDefaultSettings (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ //
+ // Subnuma Mode
+ //
+ Status = NVParamGet (
+ NV_SI_SUBNUMA_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ Status = NVParamSet (
+ NV_SI_SUBNUMA_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ NV_SI_SUBNUMA_MODE_DEFAULT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // ARM ERRATA 1542419 workaround
+ //
+ Status = NVParamSet (
+ NV_SI_ERRATUM_1542419_WA,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ WA_ERRATUM_1542419_DEFAULT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Near atomic
+ //
+ Status = NVParamSet (
+ NV_SI_NEAR_ATOMIC_DISABLE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ NEAR_ATOMIC_DISABLE_DEFAULT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // SLC Replacement Policy
+ //
+ Status = NVParamSet (
+ NV_SI_HNF_AUX_CTL_32_63,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ NV_PERM_BIOS | NV_PERM_MANU,
+ CPU_SLC_REPLACE_POLICY
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function allows a caller to extract the current configuration for one
+ or more named elements from the target driver.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Request A null-terminated Unicode string in
+ <ConfigRequest> format.
+ @param Progress On return, points to a character in the Request
+ string. Points to the string's null terminator if
+ request was successful. Points to the most recent
+ '&' before the first failing name/value pair (or
+ the beginning of the string if the failure is in
+ the first name/value pair) if the request was not
+ successful.
+ @param Results A null-terminated Unicode string in
+ <ConfigAltResp> format which has all values filled
+ in for the names in the Request string. String to
+ be allocated by the called function.
+
+ @retval EFI_SUCCESS The Results is filled with the requested values.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results.
+ @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown name.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuConfigExtractConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ CPU_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if (Progress == NULL || Results == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize the local variables.
+ //
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
+
+ if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &gCpuConfigFormSetGuid, CpuVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+
+ //
+ // Get current setting from NVParam.
+ //
+ Status = CpuNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ BufferSize = sizeof (CPU_VARSTORE_DATA);
+ ConfigRequest = Request;
+ if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
+ //
+ // Request has no request element, construct full request string.
+ // Allocate and fill a buffer large enough to hold the <ConfigHdr> template
+ // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
+ //
+ ConfigRequestHdr = HiiConstructConfigHdr (&gCpuConfigFormSetGuid, CpuVarstoreDataName, PrivateData->DriverHandle);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
+ ASSERT (ConfigRequest != NULL);
+ if (ConfigRequest == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ AllocatedRequest = TRUE;
+ UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
+ FreePool (ConfigRequestHdr);
+ }
+
+ //
+ // Convert buffer data to <ConfigResp> by helper function BlockToConfig()
+ //
+ Status = HiiConfigRouting->BlockToConfig (
+ HiiConfigRouting,
+ ConfigRequest,
+ (UINT8 *)&PrivateData->Configuration,
+ BufferSize,
+ Results,
+ Progress
+ );
+
+ //
+ // Free the allocated config request string.
+ //
+ if (AllocatedRequest) {
+ FreePool (ConfigRequest);
+ ConfigRequest = NULL;
+ }
+
+ //
+ // Set Progress string to the original request string.
+ //
+ if (Request == NULL) {
+ *Progress = NULL;
+ } else if (StrStr (Request, L"OFFSET") == NULL) {
+ *Progress = Request + StrLen (Request);
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Configuration A null-terminated Unicode string in <ConfigResp>
+ format.
+ @param Progress A pointer to a string filled in with the offset of
+ the most recent '&' before the first failing
+ name/value pair (or the beginning of the string if
+ the failure is in the first name/value pair) or
+ the terminating NULL if all was successful.
+
+ @retval EFI_SUCCESS The Results is processed successfully.
+ @retval EFI_INVALID_PARAMETER Configuration is NULL.
+ @retval EFI_NOT_FOUND Routing data doesn't match any storage in this
+ driver.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuConfigRouteConfig (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ CPU_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ if (Configuration == NULL || Progress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
+ HiiConfigRouting = PrivateData->HiiConfigRouting;
+ *Progress = Configuration;
+
+ //
+ // Check routing data in <ConfigHdr>.
+ // Note: if only one Storage is used, then this checking could be skipped.
+ //
+ if (!HiiIsConfigHdrMatch (Configuration, &gCpuConfigFormSetGuid, CpuVarstoreDataName)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Get configuration data from NVParam
+ //
+ Status = CpuNvParamGet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
+ //
+ BufferSize = sizeof (CPU_VARSTORE_DATA);
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Store configuration data back to NVParam
+ //
+ Status = CpuNvParamSet (&PrivateData->Configuration);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return Status;
+}
+
+/**
+ This function processes the results of changes in configuration.
+
+ @param This Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
+ @param Action Specifies the type of action taken by the browser.
+ @param QuestionId A unique value which is sent to the original
+ exporting driver so that it can identify the type
+ of data to expect.
+ @param Type The type of value for the question.
+ @param Value A pointer to the data being sent to the original
+ exporting driver.
+ @param ActionRequest On return, points to the action requested by the
+ callback function.
+
+ @retval EFI_SUCCESS The callback successfully handled the action.
+ @retval EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuConfigCallback (
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ )
+{
+ if (Action != EFI_BROWSER_ACTION_CHANGING) {
+ //
+ // Do nothing for other UEFI Action. Only do call back when data is changed.
+ //
+ return EFI_UNSUPPORTED;
+ }
+ if (((Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN) && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))||
+ (ActionRequest == NULL))
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+CpuConfigDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+
+ //
+ // Initialize driver private data
+ //
+ mPrivateData = AllocateZeroPool (sizeof (CPU_CONFIG_PRIVATE_DATA));
+ if (mPrivateData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->Signature = CPU_CONFIG_PRIVATE_SIGNATURE;
+
+ mPrivateData->ConfigAccess.ExtractConfig = CpuConfigExtractConfig;
+ mPrivateData->ConfigAccess.RouteConfig = CpuConfigRouteConfig;
+ mPrivateData->ConfigAccess.Callback = CpuConfigCallback;
+
+ //
+ // Locate ConfigRouting protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID **)&HiiConfigRouting);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ mPrivateData->HiiConfigRouting = HiiConfigRouting;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mCpuConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mPrivateData->DriverHandle = mDriverHandle;
+
+ //
+ // Publish our HII data
+ //
+ HiiHandle = HiiAddPackages (
+ &gCpuConfigFormSetGuid,
+ mDriverHandle,
+ CpuConfigDxeStrings,
+ CpuConfigVfrBin,
+ NULL
+ );
+ if (HiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mCpuConfigHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mPrivateData->HiiHandle = HiiHandle;
+
+ //
+ // With the fresh system, the NVParam value is invalid (0xFFFFFFFF).
+ // It causes reading from the NVParam is failed.
+ // So, the NVParam should be setting with default values if any params is invalid.
+ //
+ Status = SetupDefaultSettings ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigStrings.uni
new file mode 100644
index 000000000000..70c01f65e4b6
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigStrings.uni
@@ -0,0 +1,17 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English"
+
+#string STR_CPU_FORM #language en-US "CPU Configuration"
+#string STR_CPU_FORM_HELP #language en-US "CPU Configuration"
+#string STR_CPU_FORM_SEPERATE_LINE #language en-US ""
+
+#string STR_CPU_SUBNUMA_MODE_PROMPT #language en-US "ANC mode"
+#string STR_CPU_SUBNUMA_MODE_HELP #language en-US "Provides 3 modes: Monolithic, Hemisphere, Quadrant. System with Monolithic mode has single NUMA partition per socket. System with Hemisphere has 2 NUMA partitions per socket. System with Quandrant has 4 NUMA partitions per socket"
+#string STR_CPU_SUBNUMA_MODE_MONOLITHIC #language en-US "Monolithic"
+#string STR_CPU_SUBNUMA_MODE_HEMISPHERE #language en-US "Hemisphere"
+#string STR_CPU_SUBNUMA_MODE_QUADRANT #language en-US "Quadrant"
--
2.17.1


[PATCH v3 22/28] AmpereAltraPkg: Add platform info screen

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Provide screen menu with basic platform information include:
* Platform name
* SCP firmware info
* System bus clock frequency.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Ampere/JadePkg/Jade.dsc | 5 +
Platform/Ampere/JadePkg/Jade.fdf | 5 +
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf | 52 +++
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h | 22 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoVfr.vfr | 112 ++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c | 391 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoStrings.uni | 56 +++
7 files changed, 643 insertions(+)

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index 5b40d552e2e5..f723be6997e6 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -192,3 +192,8 @@ [Components.common]
Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
+
+ #
+ # HII
+ #
+ Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 56a54b307f04..c54b46f95ad5 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -351,4 +351,9 @@ [FV.FvMain]
INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
INF Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf

+ #
+ # HII
+ #
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
+
!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
new file mode 100644
index 000000000000..a55983dd738e
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.inf
@@ -0,0 +1,52 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformInfoDxe
+ FILE_GUID = 6FDFB3E8-105E-48C4-94AA-3D7646F9B50D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformInfoEntryPoint
+
+[Sources.common]
+ PlatformInfoDxe.c
+ PlatformInfoHii.h
+ PlatformInfoVfr.vfr
+ PlatformInfoStrings.uni
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ DevicePathLib
+ HiiLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gPlatformManagerFormsetGuid
+ gEfiIfrTianoGuid
+ gPlatformHobGuid
+
+[Protocols]
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h
new file mode 100644
index 000000000000..7f363160afc8
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h
@@ -0,0 +1,22 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_INFO_HII_H_
+#define PLATFORM_INFO_HII_H_
+
+#define PLATFORM_INFO_FORMSET_GUID \
+ { \
+ 0x8DF0F6FB, 0x65A5, 0x434B, { 0xB2, 0xA6, 0xCE, 0xDF, 0xD2, 0x0A, 0x96, 0x8A } \
+ }
+
+#define LABEL_UPDATE 0x2223
+#define LABEL_END 0x2224
+
+#define PLATFORM_INFO_FORM_ID 0x1
+
+#endif
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoVfr.vfr
new file mode 100644
index 000000000000..5dd32a30f0ad
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoVfr.vfr
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformInfoHii.h"
+
+formset
+ guid = PLATFORM_INFO_FORMSET_GUID,
+ title = STRING_TOKEN(STR_PLATFORM_INFO_FORM),
+ help = STRING_TOKEN(STR_PLATFORM_INFO_FORM_HELP),
+ classguid = gPlatformManagerFormsetGuid,
+
+ form
+ formid = PLATFORM_INFO_FORM_ID,
+ title = STRING_TOKEN(STR_PLATFORM_INFO_FORM);
+ subtitle text = STRING_TOKEN(STR_PLATFORM_INFO_FORM_HELP);
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_BOARD),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_BOARD),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_BOARD_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_SCPVER),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SCPVER),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SCPVER_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_SCPBUILD),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SCPBUILD),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SCPBUILD_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_CPUINFO),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_CPUINFO),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_CPUINFO_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_CPUCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_CPUCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_CPUCLK_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_PCPCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_PCPCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_PCPCLK_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_L1ICACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L1ICACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L1ICACHE_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_L1DCACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L1DCACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L1DCACHE_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_L2CACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L2CACHE),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_L2CACHE_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_SOCCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SOCCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SOCCLK_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_SYSCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SYSCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_SYSCLK_VALUE),
+ flags = 0,
+ key = 0;
+
+ text
+ help = STRING_TOKEN(STR_PLATFORM_INFO_AHBCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_AHBCLK),
+ text = STRING_TOKEN(STR_PLATFORM_INFO_AHBCLK_VALUE),
+ flags = 0,
+ key = 0;
+
+ label LABEL_UPDATE;
+ // dynamic content here
+ label LABEL_END;
+
+ endform;
+
+endformset;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c
new file mode 100644
index 000000000000..6308ed4b4f3c
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c
@@ -0,0 +1,391 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Guid/MdeModuleHii.h>
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <PlatformInfoHob.h>
+
+#include "PlatformInfoHii.h"
+
+//
+// uni string and Vfr Binary data.
+//
+extern UINT8 PlatformInfoVfrBin[];
+extern UINT8 PlatformInfoDxeStrings[];
+
+EFI_HANDLE mDriverHandle = NULL;
+EFI_HII_HANDLE mHiiHandle = NULL;
+
+#pragma pack(1)
+
+//
+// HII specific Vendor Device Path definition.
+//
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+#pragma pack()
+
+// PLATFORM_INFO_FORMSET_GUID
+EFI_GUID gPlatformInfoFormSetGuid = PLATFORM_INFO_FORMSET_GUID;
+
+HII_VENDOR_DEVICE_PATH mPlatformInfoHiiVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ PLATFORM_INFO_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+#define MAX_STRING_SIZE 64
+#define MHZ_SCALE_FACTOR 1000000
+
+STATIC
+CHAR8 *
+GetCCIXLinkSpeed (
+ IN UINTN Speed
+ )
+{
+ switch (Speed) {
+ case 1:
+ return "2.5 GT/s";
+
+ case 2:
+ return "5 GT/s";
+
+ case 3:
+ return "8 GT/s";
+
+ case 4:
+ case 6:
+ return "16 GT/s";
+
+ case 0xa:
+ return "20 GT/s";
+
+ case 0xf:
+ return "25 GT/s";
+ }
+
+ return "Unknown";
+}
+
+STATIC
+EFI_STATUS
+UpdatePlatformInfoScreen (
+ IN EFI_HII_HANDLE *HiiHandle
+ )
+{
+ VOID *Hob;
+ PLATFORM_INFO_HOB *PlatformHob;
+ CHAR16 Str[MAX_STRING_SIZE];
+
+ VOID *StartOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ /* SCP Version */
+ AsciiStrToUnicodeStrS ((const CHAR8 *)PlatformHob->SmPmProVer, Str, MAX_STRING_SIZE);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_SCPVER_VALUE),
+ Str,
+ NULL
+ );
+
+ /* SCP build */
+ AsciiStrToUnicodeStrS ((const CHAR8 *)PlatformHob->SmPmProBuild, Str, MAX_STRING_SIZE);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_SCPBUILD_VALUE),
+ Str,
+ NULL
+ );
+
+ /* CPU Info */
+ AsciiStrToUnicodeStrS ((const CHAR8 *)PlatformHob->CpuInfo, Str, MAX_STRING_SIZE);
+ UnicodeSPrint (Str, sizeof (Str), L"%s", Str);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_CPUINFO_VALUE),
+ Str,
+ NULL
+ );
+
+ /* CPU clock */
+ UnicodeSPrint (Str, sizeof (Str), L"%dMHz", PlatformHob->CpuClk / MHZ_SCALE_FACTOR);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_CPUCLK_VALUE),
+ Str,
+ NULL
+ );
+
+ /* PCP clock */
+ UnicodeSPrint (Str, sizeof (Str), L"%dMHz", PlatformHob->PcpClk / MHZ_SCALE_FACTOR);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_PCPCLK_VALUE),
+ Str,
+ NULL
+ );
+
+ /* SOC clock */
+ UnicodeSPrint (Str, sizeof (Str), L"%dMHz", PlatformHob->SocClk / MHZ_SCALE_FACTOR);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_SOCCLK_VALUE),
+ Str,
+ NULL
+ );
+
+ /* L1 Cache */
+ UnicodeSPrint (Str, sizeof (Str), L"64KB");
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_L1ICACHE_VALUE),
+ Str,
+ NULL
+ );
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_L1DCACHE_VALUE),
+ Str,
+ NULL
+ );
+
+ /* L2 Cache */
+ UnicodeSPrint (Str, sizeof (Str), L"1MB");
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_L2CACHE_VALUE),
+ Str,
+ NULL
+ );
+
+ /* AHB clock */
+ UnicodeSPrint (Str, sizeof (Str), L"%dMHz", PlatformHob->AhbClk / MHZ_SCALE_FACTOR);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_AHBCLK_VALUE),
+ Str,
+ NULL
+ );
+
+ /* SYS clock */
+ UnicodeSPrint (Str, sizeof (Str), L"%dMHz", PlatformHob->SysClk / MHZ_SCALE_FACTOR);
+ HiiSetString (
+ HiiHandle,
+ STRING_TOKEN (STR_PLATFORM_INFO_SYSCLK_VALUE),
+ Str,
+ NULL
+ );
+
+ /* Initialize the container for dynamic opcodes */
+ StartOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (StartOpCodeHandle != NULL);
+
+ EndOpCodeHandle = HiiAllocateOpCodeHandle ();
+ ASSERT (EndOpCodeHandle != NULL);
+
+ /* Create Hii Extend Label OpCode as the start opcode */
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ StartOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ ASSERT (StartLabel != NULL);
+ StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ StartLabel->Number = LABEL_UPDATE;
+
+ /* Create Hii Extend Label OpCode as the end opcode */
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (
+ EndOpCodeHandle,
+ &gEfiIfrTianoGuid,
+ NULL,
+ sizeof (EFI_IFR_GUID_LABEL)
+ );
+ ASSERT (EndLabel != NULL);
+ EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
+ EndLabel->Number = LABEL_END;
+
+ if (IsSlaveSocketActive ()) {
+ /* Create the inter socket link text string */
+ UnicodeSPrint (
+ Str,
+ sizeof (Str),
+ L"Width x%d / Speed %a",
+ PlatformHob->Link2PWidth[0],
+ GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[0])
+ );
+
+ HiiSetString (
+ mHiiHandle,
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK0_VALUE),
+ Str,
+ NULL
+ );
+
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK0),
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK0),
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK0_VALUE)
+ );
+
+ UnicodeSPrint (
+ Str,
+ sizeof (Str),
+ L"Width x%d / Speed %a",
+ PlatformHob->Link2PWidth[1],
+ GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[1])
+ );
+
+ HiiSetString (
+ mHiiHandle,
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK1_VALUE),
+ Str,
+ NULL
+ );
+
+ HiiCreateTextOpCode (
+ StartOpCodeHandle,
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK1),
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK1),
+ STRING_TOKEN (STR_CPU_FORM_INTER_SOCKET_LINK1_VALUE)
+ );
+ }
+
+ HiiUpdateForm (
+ mHiiHandle, // HII handle
+ &gPlatformInfoFormSetGuid, // Formset GUID
+ PLATFORM_INFO_FORM_ID, // Form ID
+ StartOpCodeHandle, // Label for where to insert opcodes
+ EndOpCodeHandle // Insert data
+ );
+
+ HiiFreeOpCodeHandle (StartOpCodeHandle);
+ HiiFreeOpCodeHandle (EndOpCodeHandle);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformInfoUnload (
+ VOID
+ )
+{
+ if (mDriverHandle != NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mPlatformInfoHiiVendorDevicePath,
+ NULL
+ );
+ mDriverHandle = NULL;
+ }
+
+ if (mHiiHandle != NULL) {
+ HiiRemovePackages (mHiiHandle);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformInfoEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mPlatformInfoHiiVendorDevicePath,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Publish our HII data
+ //
+ mHiiHandle = HiiAddPackages (
+ &gPlatformInfoFormSetGuid,
+ mDriverHandle,
+ PlatformInfoDxeStrings,
+ PlatformInfoVfrBin,
+ NULL
+ );
+ if (mHiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mPlatformInfoHiiVendorDevicePath,
+ NULL
+ );
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = UpdatePlatformInfoScreen (mHiiHandle);
+ if (EFI_ERROR (Status)) {
+ PlatformInfoUnload ();
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a %d Fail to update the platform info screen \n",
+ __FUNCTION__,
+ __LINE__
+ ));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoStrings.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoStrings.uni
new file mode 100644
index 000000000000..235d104c217f
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoStrings.uni
@@ -0,0 +1,56 @@
+//
+// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#langdef en-US "English"
+
+#string STR_PLATFORM_INFO_FORM #language en-US "Platform Board Information"
+#string STR_PLATFORM_INFO_FORM_HELP #language en-US "Platform Board Information"
+
+#string STR_PLATFORM_INFO_SEPERATE_LINE #language en-US ""
+
+#string STR_PLATFORM_INFO_BOARD #language en-US "Board"
+#string STR_PLATFORM_INFO_BOARD_VALUE #language en-US "Mt. Jade"
+
+#string STR_PLATFORM_INFO_SCPVER #language en-US "SCP FW Version"
+#string STR_PLATFORM_INFO_SCPVER_VALUE #language en-US "0"
+
+#string STR_PLATFORM_INFO_RCVER #language en-US "Reference Code version"
+#string STR_PLATFORM_INFO_RCVER_VALUE #language en-US "0"
+
+#string STR_PLATFORM_INFO_SCPBUILD #language en-US "SCP FW Build"
+#string STR_PLATFORM_INFO_SCPBUILD_VALUE #language en-US "0"
+
+#string STR_PLATFORM_INFO_CPUINFO #language en-US "CPU"
+#string STR_PLATFORM_INFO_CPUINFO_VALUE #language en-US " "
+
+#string STR_PLATFORM_INFO_CPUCLK #language en-US "CPU Clock"
+#string STR_PLATFORM_INFO_CPUCLK_VALUE #language en-US "0MHz"
+
+#string STR_PLATFORM_INFO_PCPCLK #language en-US "PCP Clock"
+#string STR_PLATFORM_INFO_PCPCLK_VALUE #language en-US "0MHz"
+
+#string STR_PLATFORM_INFO_L1ICACHE #language en-US "L1I CACHE"
+#string STR_PLATFORM_INFO_L1ICACHE_VALUE #language en-US "0KB"
+
+#string STR_PLATFORM_INFO_L1DCACHE #language en-US "L1D CACHE"
+#string STR_PLATFORM_INFO_L1DCACHE_VALUE #language en-US "0KB"
+
+#string STR_PLATFORM_INFO_L2CACHE #language en-US "L2 CACHE"
+#string STR_PLATFORM_INFO_L2CACHE_VALUE #language en-US "0KB"
+
+#string STR_PLATFORM_INFO_SOCCLK #language en-US "SOC Clock"
+#string STR_PLATFORM_INFO_SOCCLK_VALUE #language en-US "0MHz"
+
+#string STR_PLATFORM_INFO_SYSCLK #language en-US "Sys Clock"
+#string STR_PLATFORM_INFO_SYSCLK_VALUE #language en-US "0MHz"
+
+#string STR_PLATFORM_INFO_AHBCLK #language en-US "AHB Clock"
+#string STR_PLATFORM_INFO_AHBCLK_VALUE #language en-US "0MHz"
+
+#string STR_CPU_FORM_INTER_SOCKET_LINK0 #language en-US "Inter Socket Connection: Link 0"
+#string STR_CPU_FORM_INTER_SOCKET_LINK0_VALUE #language en-US ""
+#string STR_CPU_FORM_INTER_SOCKET_LINK1 #language en-US "Inter Socket Connection: Link 1"
+#string STR_CPU_FORM_INTER_SOCKET_LINK1_VALUE #language en-US ""
--
2.17.1


[PATCH v3 21/28] AmpereAltraPkg: Add DebugInfoPei module

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Helps to show various system information like CPU info and Board Setting
values to UART console during boot process.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 4 +
Platform/Ampere/JadePkg/Jade.fdf | 2 +
Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf | 40 ++++
Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c | 210 ++++++++++++++++++++
4 files changed, 256 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
index 459d06c33c02..aadbf6dae83e 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
@@ -543,6 +543,10 @@ [Components.common]
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf
+ Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf {
+ <LibraryClasses>
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ }
Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf
Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 96213edb2676..56a54b307f04 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -167,6 +167,8 @@ [FV.FVMAIN_COMPACT]
#
# Print platform information before passing control into the Driver Execution Environment (DXE) phase
#
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf
+
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf
new file mode 100644
index 000000000000..1f50f811f273
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.inf
@@ -0,0 +1,40 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = DebugInfo
+ FILE_GUID = C0571D26-6176-11E9-8647-D663BD873D93
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = DebugInfoPeiEntryPoint
+
+[Sources]
+ DebugInfoPei.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ ArmLib
+ DebugLib
+ HobLib
+ NVParamLib
+ PeimEntryPoint
+
+[Guids]
+ gPlatformHobGuid
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c
new file mode 100644
index 000000000000..ece9295864a8
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c
@@ -0,0 +1,210 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Uefi.h>
+
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/NVParamLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+#include <NVParamDef.h>
+#include <PlatformInfoHob.h>
+
+#define GB_SCALE_FACTOR 1073741824
+#define MB_SCALE_FACTOR 1048576
+#define KB_SCALE_FACTOR 1024
+#define MHZ_SCALE_FACTOR 1000000
+
+/**
+ Print any existence NVRAM.
+**/
+STATIC VOID
+PrintNVRAM (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ NVPARAM Idx;
+ UINT32 Val;
+ UINT16 ACLRd = NV_PERM_ALL;
+ BOOLEAN Flag;
+
+ Flag = FALSE;
+ for (Idx = NV_PREBOOT_PARAM_START; Idx <= NV_PREBOOT_PARAM_MAX; Idx += NVPARAM_SIZE) {
+ Status = NVParamGet (Idx, ACLRd, &Val);
+ if (!EFI_ERROR (Status)) {
+ if (!Flag) {
+ DebugPrint (DEBUG_INIT, "Pre-boot Configuration Setting:\n");
+ Flag = TRUE;
+ }
+ DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
+ }
+ }
+
+ Flag = FALSE;
+ for (Idx = NV_MANU_PARAM_START; Idx <= NV_MANU_PARAM_MAX; Idx += NVPARAM_SIZE) {
+ Status = NVParamGet (Idx, ACLRd, &Val);
+ if (!EFI_ERROR (Status)) {
+ if (!Flag) {
+ DebugPrint (DEBUG_INIT, "Manufacturer Configuration Setting:\n");
+ Flag = TRUE;
+ }
+ DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
+ }
+ }
+
+ Flag = FALSE;
+ for (Idx = NV_USER_PARAM_START; Idx <= NV_USER_PARAM_MAX; Idx += NVPARAM_SIZE) {
+ Status = NVParamGet (Idx, ACLRd, &Val);
+ if (!EFI_ERROR (Status)) {
+ if (!Flag) {
+ DebugPrint (DEBUG_INIT, "User Configuration Setting:\n");
+ Flag = TRUE;
+ }
+ DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
+ }
+ }
+
+ Flag = FALSE;
+ for (Idx = NV_BOARD_PARAM_START; Idx <= NV_BOARD_PARAM_MAX; Idx += NVPARAM_SIZE) {
+ Status = NVParamGet (Idx, ACLRd, &Val);
+ if (!EFI_ERROR (Status)) {
+ if (!Flag) {
+ DebugPrint (DEBUG_INIT, "Board Configuration Setting:\n");
+ Flag = TRUE;
+ }
+ DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
+ }
+ }
+}
+
+STATIC
+CHAR8 *
+GetCCIXLinkSpeed (
+ IN UINTN Speed
+ )
+{
+ switch (Speed) {
+ case 1:
+ return "2.5 GT/s";
+
+ case 2:
+ return "5 GT/s";
+
+ case 3:
+ return "8 GT/s";
+
+ case 4:
+ case 6:
+ return "16 GT/s";
+
+ case 0xa:
+ return "20 GT/s";
+
+ case 0xf:
+ return "25 GT/s";
+ }
+
+ return "Unknown";
+}
+
+/**
+ Print system info
+**/
+STATIC VOID
+PrintSystemInfo (
+ VOID
+ )
+{
+ UINTN Idx;
+ VOID *Hob;
+ PLATFORM_INFO_HOB *PlatformHob;
+
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ DebugPrint (DEBUG_INIT, "SCP FW version : %a\n", (const CHAR8 *)PlatformHob->SmPmProVer);
+ DebugPrint (DEBUG_INIT, "SCP FW build date : %a\n", (const CHAR8 *)PlatformHob->SmPmProBuild);
+
+ DebugPrint (DEBUG_INIT, "Failsafe status : %d\n", PlatformHob->FailSafeStatus);
+ DebugPrint (DEBUG_INIT, "Reset status : %d\n", PlatformHob->ResetStatus);
+ DebugPrint (DEBUG_INIT, "CPU info\n");
+ DebugPrint (DEBUG_INIT, " CPU ID : %X\n", ArmReadMidr ());
+ DebugPrint (DEBUG_INIT, " CPU Clock : %d MHz\n", PlatformHob->CpuClk / MHZ_SCALE_FACTOR);
+ DebugPrint (DEBUG_INIT, " Number of active sockets : %d\n", GetNumberOfActiveSockets ());
+ DebugPrint (DEBUG_INIT, " Number of active cores : %d\n", GetNumberOfActiveCores ());
+ if (IsSlaveSocketActive ()) {
+ DebugPrint (DEBUG_INIT,
+ " Inter Socket Connection 0 : Width: x%d / Speed %a\n",
+ PlatformHob->Link2PWidth[0],
+ GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[0])
+ );
+ DebugPrint (DEBUG_INIT,
+ " Inter Socket Connection 1 : Width: x%d / Speed %a\n",
+ PlatformHob->Link2PWidth[1],
+ GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[1])
+ );
+ }
+ for (Idx = 0; Idx < GetNumberOfActiveSockets (); Idx++) {
+ DebugPrint (DEBUG_INIT, " Socket[%d]: Core voltage : %d\n", Idx, PlatformHob->CoreVoltage[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: SCU ProductID : %X\n", Idx, PlatformHob->ScuProductId[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: Max cores : %d\n", Idx, PlatformHob->MaxNumOfCore[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: Warranty : %d\n", Idx, PlatformHob->Warranty[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: Subnuma : %d\n", Idx, PlatformHob->SubNumaMode[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: RC disable mask : %X\n", Idx, PlatformHob->RcDisableMask[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: AVS enabled : %d\n", Idx, PlatformHob->AvsEnable[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: AVS voltage : %d\n", Idx, PlatformHob->AvsVoltageMV[Idx]);
+ }
+
+ DebugPrint (DEBUG_INIT, "SOC info\n");
+ DebugPrint (DEBUG_INIT, " DDR Frequency : %d MHz\n", PlatformHob->DramInfo.MaxSpeed);
+ for (Idx = 0; Idx < GetNumberOfActiveSockets (); Idx++) {
+ DebugPrint (DEBUG_INIT, " Socket[%d]: Soc voltage : %d\n", Idx, PlatformHob->SocVoltage[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: DIMM1 voltage : %d\n", Idx, PlatformHob->Dimm1Voltage[Idx]);
+ DebugPrint (DEBUG_INIT, " Socket[%d]: DIMM2 voltage : %d\n", Idx, PlatformHob->Dimm2Voltage[Idx]);
+ }
+
+ DebugPrint (DEBUG_INIT, " PCP Clock : %d MHz\n", PlatformHob->PcpClk / MHZ_SCALE_FACTOR);
+ DebugPrint (DEBUG_INIT, " SOC Clock : %d MHz\n", PlatformHob->SocClk / MHZ_SCALE_FACTOR);
+ DebugPrint (DEBUG_INIT, " SYS Clock : %d MHz\n", PlatformHob->SysClk / MHZ_SCALE_FACTOR);
+ DebugPrint (DEBUG_INIT, " AHB Clock : %d MHz\n", PlatformHob->AhbClk / MHZ_SCALE_FACTOR);
+}
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+DebugInfoPeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ PrintSystemInfo ();
+ PrintNVRAM ();
+
+ return EFI_SUCCESS;
+}
--
2.17.1


[PATCH v3 20/28] JadePkg: Add SMBIOS tables support

Nhi Pham
 

From: Quan Nguyen <quan@os.amperecomputing.com>

This supports various SMBIOS tables type 0, 1, 2, 3, 4, 7, 8, 9, 11,
13, 16, 17, 19, 24 and 32.

SMBIOS Type 1, 2 and 3 are hardcoded as Host-BMC communication is not
supported yet. And, this module does not support fixup tables to reflect
changes of the system at booting time.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec | 12 +
Platform/Ampere/JadePkg/Jade.dsc | 35 +
Platform/Ampere/JadePkg/Jade.fdf | 8 +
Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf | 45 +
Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 52 +
Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf | 36 +
Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.c | 705 +++++++++++++
Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 1049 ++++++++++++++++++++
Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.c | 323 ++++++
9 files changed, 2265 insertions(+)

diff --git a/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec b/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
index 36b1249c7a08..a6c896231b3b 100644
--- a/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+++ b/Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
@@ -63,11 +63,23 @@ [PcdsFixedAtBuild]
gAmpereTokenSpaceGuid.PcdSmproNsMailboxIndex|0x1|UINT32|0x00000003
gAmpereTokenSpaceGuid.PcdPmproDbBaseReg|0x100001540000|UINT64|0x00000004

+ #
+ # SMBIOS Type 1 Pcd
+ #
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MajorVersion|0|UINT8|0x00000005
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MinorVersion|0|UINT8|0x00000006
+
[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx]
#
# Firmware Volume Pcds
#
gAmpereTokenSpaceGuid.PcdFvBlockSize|0|UINT32|0xB0000001

+ #
+ # SMBIOS, default or template values
+ #
+ # SMBIOS Type 0 - BIOS Information
+ gAmpereTokenSpaceGuid.PcdSmbiosTables0BiosReleaseDate|"MM/DD/YYYY"|VOID*|0xB0000002 # Must follow this MM/DD/YYYY SMBIOS date format
+
# NVRam Pcds
gAmpereTokenSpaceGuid.PcdNvramErased|FALSE|BOOLEAN|0xB0000009
diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index ce5f2c0dc4e1..5b40d552e2e5 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -93,6 +93,8 @@ [LibraryClasses]
#
BoardPcieLib|Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf

+ OemMiscLib|Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf
+
################################################################################
#
# Specific Platform Pcds
@@ -104,12 +106,34 @@ [PcdsFeatureFlag.common]
#
gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+[PcdsFixedAtBuild]
+!ifdef $(FIRMWARE_VER)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+!endif
+
[PcdsFixedAtBuild.common]
#
# NVRAM
#
gAmpereTokenSpaceGuid.PcdNvramUuid|"$(NVRAM_UUID)"

+ #
+ # SMBIOS PCDs
+ #
+ gArmTokenSpaceGuid.PcdProcessorManufacturer|L"Ampere(R)"
+ gArmTokenSpaceGuid.PcdProcessorVersion|L"Ampere(R) Altra(R) Processor"
+
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MajorVersion|$(MAJOR_VER)
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MinorVersion|$(MINOR_VER)
+
+ # Clearing BIT0 in this PCD prevents installing a 32-bit SMBIOS entry point,
+ # if the entry point version is >= 3.0. AARCH64 OSes cannot assume the
+ # presence of the 32-bit entry point anyway (because many AARCH64 systems
+ # don't have 32-bit addressable physical RAM), and the additional allocations
+ # below 4 GB needlessly fragment the memory map. So expose the 64-bit entry
+ # point only, for entry point versions >= 3.0.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
+
!if $(SECURE_BOOT_ENABLE) == TRUE
# Override the default values from SecurityPkg to ensure images
# from all sources are verified in secure boot
@@ -118,6 +142,9 @@ [PcdsFixedAtBuild.common]
gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
!endif

+[PcdsDynamicDefault.common.DEFAULT]
+ # SMBIOS Type 0 - BIOS Information
+ gAmpereTokenSpaceGuid.PcdSmbiosTables0BiosReleaseDate|"MM/DD/YYYY"

[PcdsPatchableInModule]
#
@@ -157,3 +184,11 @@ [Components.common]
# VGA Aspeed
#
Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf
+
+ #
+ # SMBIOS
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+ ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+ Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 06c8a4fa1b09..96213edb2676 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -341,4 +341,12 @@ [FV.FvMain]
INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
INF RuleOverride=ACPITABLE Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf

+ #
+ # SMBIOS
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+ INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+ INF Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
+
!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf b/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
new file mode 100644
index 000000000000..87b9123df856
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf
@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = SmbiosMemInfoDxe
+ FILE_GUID = ECF38190-EBF8-11EA-B646-830715BDF83A
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SmbiosMemInfoDxeEntry
+
+[Sources]
+ SmbiosMemInfoDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ ArmLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid ## CONSUMED
+
+[Guids]
+ gPlatformHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
diff --git a/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
new file mode 100644
index 000000000000..73a601b0df08
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -0,0 +1,52 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = SmbiosPlatformDxe
+ FILE_GUID = F0CC7D0B-CD83-4DDA-A5D4-613AB02D4E52
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SmbiosPlatformDxeEntry
+
+[Sources]
+ SmbiosPlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid ## CONSUMED
+
+[Pcd]
+ # Type 0
+ gAmpereTokenSpaceGuid.PcdSmbiosTables0BiosReleaseDate
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MajorVersion
+ gAmpereTokenSpaceGuid.PcdSmbiosTables1MinorVersion
+
+ gArmTokenSpaceGuid.PcdFdSize
+
+[Guids]
+ gPlatformHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
diff --git a/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf b/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf
new file mode 100644
index 000000000000..b67ce01fb27f
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.inf
@@ -0,0 +1,36 @@
+#/** @file
+# OemMiscLib.inf
+#
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.29
+ BASE_NAME = OemMiscLib
+ FILE_GUID = A84551A1-CF71-4CC4-A63B-B087048A87AD
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OemMiscLib
+
+[Sources.common]
+ OemMiscLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+
+[LibraryClasses]
+ AmpereCpuLib
+ ArmLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
diff --git a/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.c b/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.c
new file mode 100644
index 000000000000..376075fdb0af
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.c
@@ -0,0 +1,705 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Guid/SmBios.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/Smbios.h>
+
+#define TYPE16_ADDITIONAL_STRINGS \
+ "\0" /* no string*/
+
+#define TYPE17_ADDITIONAL_STRINGS \
+ "Device Locator not set \0" \
+ "Bank Locator not set \0" \
+ "Manufacturer not set \0" \
+ "Serial Number not set \0" \
+ "Asset Tag not set \0" \
+ "Part Number not set \0" \
+
+#define TYPE19_ADDITIONAL_STRINGS \
+ "\0" /* no string */
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+ SMBIOS_TABLE_TYPE16 Base;
+ CHAR8 Strings[sizeof (TYPE16_ADDITIONAL_STRINGS)];
+} ARM_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ CHAR8 Strings[sizeof (TYPE17_ADDITIONAL_STRINGS)];
+} ARM_TYPE17;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE19 Base;
+ CHAR8 Strings[sizeof (TYPE19_ADDITIONAL_STRINGS)];
+} ARM_TYPE19;
+
+#pragma pack()
+// Type 16 Physical Memory Array
+STATIC ARM_TYPE16 mArmDefaultType16 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ MemoryArrayLocationSystemBoard, // on motherboard
+ MemoryArrayUseSystemMemory, // system RAM
+ MemoryErrorCorrectionMultiBitEcc, // ECC RAM
+ 0x80000000,
+ 0xFFFE, // No error information structure
+ 0x10,
+ 0x40000000000ULL,
+ },
+ TYPE16_ADDITIONAL_STRINGS
+};
+
+// Type 17 Memory Device
+STATIC ARM_TYPE17 mArmDefaultType17 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE,
+ sizeof (SMBIOS_TABLE_TYPE17),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 0xFFFF, // array to which this module belongs
+ 0xFFFE, // no errors
+ 72, // single DIMM with ECC
+ 64, // data width of this device (64-bits)
+ 0, // no module installed
+ 0x09, // DIMM
+ 1, // part of a set
+ 1, // device locator
+ 2, // bank locator
+ MemoryTypeDdr4, // DDR4
+ {}, // type detail
+ 0, // ? MHz
+ 3, // manufacturer
+ 4, // serial
+ 5, // asset tag
+ 6, // part number
+ 0, // rank
+ },
+ TYPE17_ADDITIONAL_STRINGS
+};
+
+// Type 19 Memory Array Mapped Address
+STATIC ARM_TYPE19 mArmDefaultType19 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS,
+ sizeof (SMBIOS_TABLE_TYPE19),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 0xFFFFFFFF, // invalid, look at extended addr field
+ 0xFFFFFFFF,
+ 0xFFFF, // handle
+ 1,
+ 0x0,
+ 0x0,
+ },
+ TYPE19_ADDITIONAL_STRINGS
+};
+
+typedef struct _JEDEC_MF_ID {
+ UINT8 VendorId;
+ CHAR8 *ManufacturerString;
+} JEDEC_MF_ID;
+
+JEDEC_MF_ID Bank0Table[] = {
+ { 0x01, "AMD" },
+ { 0x04, "Fujitsu" },
+ { 0x07, "Hitachi" },
+ { 0x89, "Intel" },
+ { 0x10, "NEC" },
+ { 0x97, "Texas Instrument" },
+ { 0x98, "Toshiba" },
+ { 0x1c, "Mitsubishi" },
+ { 0x1f, "Atmel" },
+ { 0x20, "STMicroelectronics" },
+ { 0xa4, "IBM" },
+ { 0x2c, "Micron Technology" },
+ { 0xad, "SK Hynix" },
+ { 0xb0, "Sharp" },
+ { 0xb3, "IDT" },
+ { 0x3e, "Oracle" },
+ { 0xbf, "SST" },
+ { 0x40, "ProMos/Mosel" },
+ { 0xc1, "Infineon" },
+ { 0xc2, "Macronix" },
+ { 0x45, "SanDisk" },
+ { 0xce, "Samsung" },
+ { 0xda, "Winbond" },
+ { 0xe0, "LG Semi" },
+ { 0x62, "Sanyo" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank1Table[] = {
+ { 0x98, "Kingston" },
+ { 0xba, "PNY" },
+ { 0x4f, "Transcend" },
+ { 0x7a, "Apacer" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank2Table[] = {
+ { 0x9e, "Corsair" },
+ { 0xfe, "Elpida" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank3Table[] = {
+ { 0x0b, "Nanya" },
+ { 0x94, "Mushkin" },
+ { 0x25, "Kingmax" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank4Table[] = {
+ { 0xb0, "OCZ" },
+ { 0xcb, "A-DATA" },
+ { 0xcd, "G Skill" },
+ { 0xef, "Team" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank5Table[] = {
+ { 0x02, "Patriot" },
+ { 0x9b, "Crucial" },
+ { 0x51, "Qimonda" },
+ { 0x57, "AENEON" },
+ { 0xf7, "Avant" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank6Table[] = {
+ { 0x34, "Super Talent" },
+ { 0xd3, "Silicon Power" },
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID Bank7Table[] = {
+ { 0xff, "Undefined" }
+};
+
+JEDEC_MF_ID *ManufacturerJedecIdBankTable[] = {
+ Bank0Table,
+ Bank1Table,
+ Bank2Table,
+ Bank3Table,
+ Bank4Table,
+ Bank5Table,
+ Bank6Table,
+ Bank7Table
+};
+
+STATIC
+UINTN
+GetStringPackSize (
+ CHAR8 *StringPack
+ )
+{
+ UINTN StrCount;
+ CHAR8 *StrStart;
+
+ if ((*StringPack == 0) && (*(StringPack + 1) == 0)) {
+ return 0;
+ }
+
+ // String section ends in double-null (0000h)
+ for (StrCount = 0, StrStart = StringPack;
+ ((*StrStart != 0) || (*(StrStart + 1) != 0)); StrStart++, StrCount++)
+ {
+ }
+
+ return StrCount + 2; // Included the double NULL
+}
+
+// Update String at String number to String Pack
+EFI_STATUS
+UpdateStringPack (
+ CHAR8 *StringPack,
+ CHAR8 *String,
+ UINTN StringNumber
+ )
+{
+ CHAR8 *StrStart;
+ UINTN StrIndex;
+ UINTN InputStrLen;
+ UINTN TargetStrLen;
+ UINTN BufferSize;
+ CHAR8 *Buffer;
+
+ StrStart = StringPack;
+ for (StrIndex = 1; StrIndex < StringNumber; StrStart++) {
+ // A string ends in 00h
+ if (*StrStart == 0) {
+ StrIndex++;
+ }
+ // String section ends in double-null (0000h)
+ if ((*StrStart == 0) && (*(StrStart + 1) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+ }
+
+ if (*StrStart == 0) {
+ StrStart++;
+ }
+
+ InputStrLen = AsciiStrLen (String);
+ TargetStrLen = AsciiStrLen (StrStart);
+ BufferSize = GetStringPackSize (StrStart + TargetStrLen + 1);
+
+ // Replace the String if length matched
+ // OR this is the last string
+ if ((InputStrLen == TargetStrLen) || (BufferSize == 0)) {
+ CopyMem (StrStart, String, InputStrLen);
+ }
+ // Otherwise, buffer is needed to apply new string
+ else {
+ Buffer = AllocateZeroPool (BufferSize);
+ if (Buffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ CopyMem (Buffer, StrStart + TargetStrLen + 1, BufferSize);
+ CopyMem (StrStart, String, InputStrLen + 1);
+ CopyMem (StrStart + InputStrLen + 1, Buffer, BufferSize);
+
+ FreePool (Buffer);
+ }
+
+ return EFI_SUCCESS;
+}
+
+UINT8
+GetMemoryType (
+ IN UINT8 *SpdData
+ )
+{
+ return (SpdData[2] == 0x08) ? 1 : // DDR2
+ (SpdData[2] == 0x0B) ? 2 : // DDR3
+ (SpdData[2] == 0x0C) ? 3 : 0; // DDR4
+}
+
+EFI_STATUS
+UpdateManufacturer (
+ IN VOID *Table,
+ IN UINT8 *SpdData
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN i;
+ UINT8 Data8;
+ UINT8 MemType;
+ JEDEC_MF_ID *IdTblPtr = NULL;
+
+ MemType = GetMemoryType (SpdData);
+
+ switch (MemType) {
+ case 1:
+ for (i = 0; i < 8; i++) { // DDR2
+ Data8 = SpdData[64 + i];
+ if (Data8 != 0x7f) {
+ break;
+ }
+ }
+ break;
+
+ case 2: // DDR3
+ i = SpdData[117] & 0x7f; // Remove parity bit
+ Data8 = SpdData[118];
+ break;
+
+ case 3: // DDR4
+ i = SpdData[320] & 0x7f; // Remove parity bit
+ Data8 = SpdData[321];
+ break;
+
+ default:
+ return EFI_UNSUPPORTED; // Not supported
+ }
+
+ if (i > 7) {
+ i = 7;
+ }
+ IdTblPtr = ManufacturerJedecIdBankTable[i];
+
+ // Search in Manufacturer table
+ while ((IdTblPtr->VendorId != Data8) && (IdTblPtr->VendorId != 0xff)) {
+ IdTblPtr++;
+ }
+
+ if (IdTblPtr->VendorId != 0xff) {
+ Status = UpdateStringPack (
+ ((ARM_TYPE17 *)Table)->Strings,
+ IdTblPtr->ManufacturerString,
+ ((ARM_TYPE17 *)Table)->Base.Manufacturer
+ );
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+UpdateSerialNumber (
+ IN VOID *Table,
+ IN UINT8 *SpdData
+ )
+{
+ UINT8 MemType;
+ UINTN Offset;
+ CHAR8 Str[64];
+
+ MemType = GetMemoryType (SpdData);
+
+ switch (MemType) {
+ case 1:
+ Offset = 95;
+ break;
+
+ case 2: // DDR3
+ Offset = 122;
+ break;
+
+ case 3: // DDR4
+ Offset = 325;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED; // Not supported
+ }
+
+ AsciiSPrint (
+ Str,
+ sizeof (Str),
+ "%02X%02X%02X%02X",
+ SpdData[Offset],
+ SpdData[Offset + 1],
+ SpdData[Offset + 2],
+ SpdData[Offset + 3]
+ );
+
+ return UpdateStringPack (
+ ((ARM_TYPE17 *)Table)->Strings,
+ Str,
+ ((ARM_TYPE17 *)Table)->Base.SerialNumber
+ );
+}
+
+CHAR8
+Printable (
+ IN CHAR8 Character
+ )
+{
+ if((Character >= 0x20) && (Character <= 0x7E)) {
+ return Character;
+ }
+
+ return ' ';
+}
+
+EFI_STATUS
+UpdatePartNumber (
+ IN VOID *Table,
+ IN UINT8 *SpdData
+ )
+{
+ UINT8 MemType;
+ UINTN Offset;
+ CHAR8 Str[64];
+
+ MemType = GetMemoryType (SpdData);
+
+ switch (MemType) {
+ case 1:
+ Offset = 73;
+ break;
+
+ case 2: // DDR3
+ Offset = 128;
+ break;
+
+ case 3: // DDR4
+ Offset = 329;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED; // Not supported
+ }
+
+ AsciiSPrint (
+ Str,
+ sizeof (Str),
+ "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ Printable (SpdData[Offset]),
+ Printable (SpdData[Offset + 1]),
+ Printable (SpdData[Offset + 2]),
+ Printable (SpdData[Offset + 3]),
+ Printable (SpdData[Offset + 4]),
+ Printable (SpdData[Offset + 5]),
+ Printable (SpdData[Offset + 6]),
+ Printable (SpdData[Offset + 7]),
+ Printable (SpdData[Offset + 8]),
+ Printable (SpdData[Offset + 9]),
+ Printable (SpdData[Offset + 10]),
+ Printable (SpdData[Offset + 11]),
+ Printable (SpdData[Offset + 12]),
+ Printable (SpdData[Offset + 13]),
+ Printable (SpdData[Offset + 14]),
+ Printable (SpdData[Offset + 15]),
+ Printable (SpdData[Offset + 16]),
+ Printable (SpdData[Offset + 17])
+ );
+
+ return UpdateStringPack (
+ ((ARM_TYPE17 *)Table)->Strings,
+ Str,
+ ((ARM_TYPE17 *)Table)->Base.PartNumber
+ );
+}
+
+/**
+ Install SMBIOS Type 16 17 and 19 table
+
+ @param Smbios SMBIOS protocol.
+**/
+EFI_STATUS
+InstallMemStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_HANDLE Type16Handle;
+ PLATFORM_INFO_HOB *PlatformHob;
+ PLATFORM_DIMM *Dimm;
+ CHAR8 *Table;
+ VOID *Hob;
+ UINTN Index;
+ UINTN SlotIndex;
+ UINTN MemRegionIndex;
+ UINT64 MemorySize = 0;
+ CHAR8 Str[64];
+
+ ASSERT (Smbios != NULL);
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ ASSERT (Hob != NULL);
+ if (Hob == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ Table = AllocateZeroPool (sizeof (ARM_TYPE17));
+ if (Table == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ for ( Index = 0; Index < GetNumberOfSupportedSockets (); Index++ ) {
+ // Copy template to Type 16
+ CopyMem (Table, (VOID *)&mArmDefaultType16, sizeof (ARM_TYPE16));
+
+ ((ARM_TYPE16 *)Table)->Base.MaximumCapacity = 0x80000000;
+ ((ARM_TYPE16 *)Table)->Base.ExtendedMaximumCapacity = 0x40000000000ULL; /* 4TB per socket */
+ ((ARM_TYPE16 *)Table)->Base.MemoryErrorCorrection = MemoryErrorCorrectionMultiBitEcc;
+
+ // Install Type 16 and hold the handle so that the subsequence type17/19 could use
+ Type16Handle = ((ARM_TYPE16 *)Table)->Base.Hdr.Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &Type16Handle,
+ (EFI_SMBIOS_TABLE_HEADER *)Table
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: adding SMBIOS type 16 socket %d failed\n", __FUNCTION__, Index));
+ FreePool (Table);
+ // stop adding rather than continuing
+ return Status;
+ }
+
+ for (SlotIndex = 0; SlotIndex < PlatformHob->DimmList.BoardDimmSlots; SlotIndex++) {
+ // Copy Tempplate to Type 17
+ CopyMem (Table, (VOID *)&mArmDefaultType17, sizeof (ARM_TYPE17));
+
+ // Fill up type 17 table's content here
+ Dimm = &PlatformHob->DimmList.Dimm[SlotIndex];
+ if (Dimm->NodeId != Index) {
+ continue;
+ }
+
+ if (Dimm->Info.DimmStatus == DIMM_INSTALLED_OPERATIONAL) {
+
+ UpdateManufacturer ((VOID *)Table, Dimm->SpdData.Data);
+ UpdateSerialNumber ((VOID *)Table, Dimm->SpdData.Data);
+ UpdatePartNumber ((VOID *)Table, Dimm->SpdData.Data);
+
+ MemorySize = Dimm->Info.DimmSize * 1024;
+ if (MemorySize >= 0x7FFF) {
+ ((ARM_TYPE17 *)Table)->Base.Size = 0x7FFF;
+ ((ARM_TYPE17 *)Table)->Base.ExtendedSize = MemorySize;
+ } else {
+ ((ARM_TYPE17 *)Table)->Base.Size = (UINT16)MemorySize;
+ ((ARM_TYPE17 *)Table)->Base.ExtendedSize = 0;
+ }
+
+ ((ARM_TYPE17 *)Table)->Base.MemoryType = 0x1A; /* DDR4 */
+ ((ARM_TYPE17 *)Table)->Base.Speed = (UINT16)PlatformHob->DramInfo.MaxSpeed;
+ ((ARM_TYPE17 *)Table)->Base.ConfiguredMemoryClockSpeed = (UINT16)PlatformHob->DramInfo.MaxSpeed;
+ ((ARM_TYPE17 *)Table)->Base.Attributes = Dimm->Info.DimmNrRank & 0x0F;
+ ((ARM_TYPE17 *)Table)->Base.ConfiguredVoltage = 1200;
+ ((ARM_TYPE17 *)Table)->Base.MinimumVoltage = 1140;
+ ((ARM_TYPE17 *)Table)->Base.MaximumVoltage = 1260;
+ ((ARM_TYPE17 *)Table)->Base.DeviceSet = 0; // None
+
+ if (Dimm->Info.DimmType == UDIMM || Dimm->Info.DimmType == SODIMM) {
+ ((ARM_TYPE17 *)Table)->Base.TypeDetail.Unbuffered = 1; /* BIT 14: unregistered */
+ } else if (Dimm->Info.DimmType == RDIMM
+ || Dimm->Info.DimmType == LRDIMM
+ || Dimm->Info.DimmType == RSODIMM)
+ {
+ ((ARM_TYPE17 *)Table)->Base.TypeDetail.Registered = 1; /* BIT 13: registered */
+ }
+ // We should determine if need to set technology to NVDIMM-* when supported
+ ((ARM_TYPE17 *)Table)->Base.MemoryTechnology = 0x3; // DRAM
+ }
+ AsciiSPrint (Str, sizeof (Str), "Socket %d DIMM %d", Index, SlotIndex);
+ UpdateStringPack (((ARM_TYPE17 *)Table)->Strings, Str, ((ARM_TYPE17 *)Table)->Base.DeviceLocator);
+ AsciiSPrint (Str, sizeof (Str), "Bank %d", SlotIndex);
+ UpdateStringPack (((ARM_TYPE17 *)Table)->Strings, Str, ((ARM_TYPE17 *)Table)->Base.BankLocator);
+ AsciiSPrint (Str, sizeof (Str), "Array %d Asset Tag %d", Index, SlotIndex);
+ UpdateStringPack (((ARM_TYPE17 *)Table)->Strings, Str, ((ARM_TYPE17 *)Table)->Base.AssetTag);
+
+ // Update Type 16 handle
+ ((ARM_TYPE17 *)Table)->Base.MemoryArrayHandle = Type16Handle;
+
+ // Install structure
+ SmbiosHandle = ((ARM_TYPE17 *)Table)->Base.Hdr.Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)Table
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: adding SMBIOS type 17 Socket %d Slot %d failed\n",
+ __FUNCTION__,
+ Index,
+ SlotIndex
+ ));
+ FreePool (Table);
+ // stop adding rather than continuing
+ return Status;
+ }
+ }
+
+ for (MemRegionIndex = 0; MemRegionIndex < PlatformHob->DramInfo.NumRegion; MemRegionIndex++) {
+ // Copy Tempplate to Type 19
+ CopyMem (Table, (VOID *)&mArmDefaultType19, sizeof (ARM_TYPE19));
+
+ if (PlatformHob->DramInfo.NvdRegion[MemRegionIndex] > 0
+ || PlatformHob->DramInfo.Socket[MemRegionIndex] != Index)
+ {
+ continue;
+ }
+
+ ((ARM_TYPE19 *)Table)->Base.StartingAddress = 0xFFFFFFFF;
+ ((ARM_TYPE19 *)Table)->Base.EndingAddress = 0xFFFFFFFF;
+ ((ARM_TYPE19 *)Table)->Base.ExtendedStartingAddress = PlatformHob->DramInfo.Base[MemRegionIndex];
+ ((ARM_TYPE19 *)Table)->Base.ExtendedEndingAddress = PlatformHob->DramInfo.Base[MemRegionIndex] +
+ PlatformHob->DramInfo.Size[MemRegionIndex] - 1;
+
+ if (MemorySize != 0) {
+ ((ARM_TYPE19 *)Table)->Base.PartitionWidth = (PlatformHob->DramInfo.Size[MemRegionIndex] - 1) / MemorySize + 1;
+ }
+
+ // Update Type 16 handle
+ ((ARM_TYPE19 *)Table)->Base.MemoryArrayHandle = Type16Handle;
+
+ // Install structure
+ SmbiosHandle = ((ARM_TYPE19 *)Table)->Base.Hdr.Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)Table
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: adding SMBIOS type 19 Socket %d MemRegion %d failed\n",
+ __FUNCTION__,
+ Index,
+ MemRegionIndex
+ ));
+ FreePool (Table);
+ // stop adding rather than continuing
+ return Status;
+ }
+ }
+ }
+
+ FreePool (Table);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SmbiosMemInfoDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ //
+ // Find the SMBIOS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&Smbios
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to locate SMBIOS Protocol"));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ Status = InstallMemStructures (Smbios);
+ DEBUG ((DEBUG_ERROR, "SmbiosMemInfoDxe install: %r\n", Status));
+
+ return Status;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
new file mode 100644
index 000000000000..af3cf5630591
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -0,0 +1,1049 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Guid/PlatformInfoHobGuid.h>
+#include <Guid/SmBios.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/Smbios.h>
+
+// Type0 Data
+#define VENDOR_TEMPLATE "Ampere(R)\0"
+#define BIOS_VERSION_TEMPLATE "TianoCore EDKII\0"
+#define RELEASE_DATE_TEMPLATE "MM/DD/YYYY\0"
+
+#define TYPE0_ADDITIONAL_STRINGS \
+ VENDOR_TEMPLATE /* Vendor */ \
+ BIOS_VERSION_TEMPLATE /* BiosVersion */ \
+ RELEASE_DATE_TEMPLATE /* BiosReleaseDate */
+
+// Type1 Data
+#define MANUFACTURER_TEMPLATE "Ampere(R)\0"
+#define PRODUCT_NAME_TEMPLATE "Mt. Jade\0"
+#define SYS_VERSION_TEMPLATE "PR010\0"
+#define SERIAL_TEMPLATE "123456789ABCDEFF123456789ABCDEFF\0"
+#define SKU_TEMPLATE "FEDCBA9876543211FEDCBA9876543211\0"
+#define FAMILY_TEMPLATE "Altra\0"
+
+#define TYPE1_ADDITIONAL_STRINGS \
+ MANUFACTURER_TEMPLATE /* Manufacturer */ \
+ PRODUCT_NAME_TEMPLATE /* Product Name */ \
+ SYS_VERSION_TEMPLATE /* Version */ \
+ SERIAL_TEMPLATE /* Serial Number */ \
+ SKU_TEMPLATE /* SKU Number */ \
+ FAMILY_TEMPLATE /* Family */
+
+#define TYPE2_ADDITIONAL_STRINGS \
+ MANUFACTURER_TEMPLATE /* Manufacturer */ \
+ PRODUCT_NAME_TEMPLATE /* Product Name */ \
+ "EVT2\0" /* Version */ \
+ "Serial Not Set\0" /* Serial */ \
+ "Base of Chassis\0" /* board location */ \
+ "FF\0" /* Version */ \
+ "FF\0" /* Version */
+
+#define CHASSIS_VERSION_TEMPLATE "None \0"
+#define CHASSIS_SERIAL_TEMPLATE "Serial Not Set \0"
+#define CHASSIS_ASSET_TAG_TEMPLATE "Asset Tag Not Set \0"
+
+#define TYPE3_ADDITIONAL_STRINGS \
+ MANUFACTURER_TEMPLATE /* Manufacturer */ \
+ CHASSIS_VERSION_TEMPLATE /* Version */ \
+ CHASSIS_SERIAL_TEMPLATE /* Serial */ \
+ CHASSIS_ASSET_TAG_TEMPLATE /* Asset Tag */ \
+ SKU_TEMPLATE /* SKU Number */
+
+#define TYPE8_ADDITIONAL_STRINGS \
+ "VGA1 - Rear VGA Connector\0" \
+ "DB-15 Male (VGA) \0"
+
+#define TYPE9_ADDITIONAL_STRINGS \
+ "Socket 0 Riser 1 x32 - Slot 1\0"
+
+#define TYPE11_ADDITIONAL_STRINGS \
+ "www.amperecomputing.com\0"
+
+#define TYPE13_ADDITIONAL_STRINGS \
+ "en|US|iso8859-1\0"
+
+#define TYPE41_ADDITIONAL_STRINGS \
+ "Onboard VGA\0"
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+ SMBIOS_TABLE_TYPE0 Base;
+ CHAR8 Strings[sizeof (TYPE0_ADDITIONAL_STRINGS)];
+} ARM_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE1 Base;
+ CHAR8 Strings[sizeof (TYPE1_ADDITIONAL_STRINGS)];
+} ARM_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE2 Base;
+ CHAR8 Strings[sizeof (TYPE2_ADDITIONAL_STRINGS)];
+} ARM_TYPE2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE3 Base;
+ CHAR8 Strings[sizeof (TYPE3_ADDITIONAL_STRINGS)];
+} ARM_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE8 Base;
+ CHAR8 Strings[sizeof (TYPE8_ADDITIONAL_STRINGS)];
+} ARM_TYPE8;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ CHAR8 Strings[sizeof (TYPE9_ADDITIONAL_STRINGS)];
+} ARM_TYPE9;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE11 Base;
+ CHAR8 Strings[sizeof (TYPE11_ADDITIONAL_STRINGS)];
+} ARM_TYPE11;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE13 Base;
+ CHAR8 Strings[sizeof (TYPE13_ADDITIONAL_STRINGS)];
+} ARM_TYPE13;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE41 Base;
+ CHAR8 Strings[sizeof (TYPE41_ADDITIONAL_STRINGS)];
+} ARM_TYPE41;
+
+#pragma pack()
+
+//-------------------------------------
+// SMBIOS Platform Common
+//-------------------------------------
+enum {
+ ADDITIONAL_STR_INDEX_1 = 1,
+ ADDITIONAL_STR_INDEX_2,
+ ADDITIONAL_STR_INDEX_3,
+ ADDITIONAL_STR_INDEX_4,
+ ADDITIONAL_STR_INDEX_5,
+ ADDITIONAL_STR_INDEX_6,
+ ADDITIONAL_STR_INDEX_MAX
+};
+
+
+// Type 0 BIOS information
+STATIC ARM_TYPE0 mArmDefaultType0 = {
+ {
+ { // Header
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length, The length of the structure's string-set is not included.
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+
+ ADDITIONAL_STR_INDEX_1, // SMBIOS_TABLE_STRING Vendor
+ ADDITIONAL_STR_INDEX_2, // SMBIOS_TABLE_STRING BiosVersion
+ 0, // UINT16 BiosSegment
+ ADDITIONAL_STR_INDEX_3, // SMBIOS_TABLE_STRING BiosReleaseDate
+ 0, // UINT8 BiosSize
+
+ // MISC_BIOS_CHARACTERISTICS BiosCharacteristics
+ {
+ 0,0,0,0,0,0,
+ 1, // PCI supported
+ 0,
+ 1, // PNP supported
+ 0,
+ 1, // BIOS upgradable
+ 0, 0, 0,
+ 0, // Boot from CD
+ 1, // selectable boot
+ },
+
+ // BIOSCharacteristicsExtensionBytes[2]
+ {
+ 0,
+ 0,
+ },
+
+ 0, // UINT8 SystemBiosMajorRelease
+ 0, // UINT8 SystemBiosMinorRelease
+
+ // If the system does not have field upgradeable embedded controller
+ // firmware, the value is 0FFh
+ 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease
+ 0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease
+ },
+
+ // Text strings (unformatted area)
+ TYPE0_ADDITIONAL_STRINGS
+};
+
+// Type 1 System information
+STATIC ARM_TYPE1 mArmDefaultType1 = {
+ {
+ { // Header
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
+ sizeof (SMBIOS_TABLE_TYPE1),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+
+ ADDITIONAL_STR_INDEX_1, // Manufacturer
+ ADDITIONAL_STR_INDEX_2, // Product Name
+ ADDITIONAL_STR_INDEX_3, // Version
+ ADDITIONAL_STR_INDEX_4, // Serial Number
+ { 0x12345678, 0x9ABC, 0xDEFF, { 0x12,0x34,0x56,0x78,0x9A,0xBC,0xDE,0xFF }}, // UUID
+ SystemWakeupTypePowerSwitch, // Wakeup type
+ ADDITIONAL_STR_INDEX_5, // SKU Number
+ ADDITIONAL_STR_INDEX_6, // Family
+ },
+
+ // Text strings (unformatted)
+ TYPE1_ADDITIONAL_STRINGS
+};
+
+// Type 2 Baseboard
+STATIC ARM_TYPE2 mArmDefaultType2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // Manufacturer
+ ADDITIONAL_STR_INDEX_2, // Product Name
+ ADDITIONAL_STR_INDEX_3, // Version
+ ADDITIONAL_STR_INDEX_4, // Serial
+ 0, // Asset tag
+ {1}, // motherboard, not replaceable
+ ADDITIONAL_STR_INDEX_5, // location of board
+ 0xFFFF, // chassis handle
+ BaseBoardTypeMotherBoard,
+ 0,
+ {0},
+ },
+ TYPE2_ADDITIONAL_STRINGS
+};
+
+// Type 3 Enclosure
+STATIC CONST ARM_TYPE3 mArmDefaultType3 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // Manufacturer
+ MiscChassisTypeRackMountChassis, // Rack-mounted chassis
+ ADDITIONAL_STR_INDEX_2, // version
+ ADDITIONAL_STR_INDEX_3, // serial
+ ADDITIONAL_STR_INDEX_4, // asset tag
+ ChassisStateUnknown, // boot chassis state
+ ChassisStateSafe, // power supply state
+ ChassisStateSafe, // thermal state
+ ChassisSecurityStatusNone, // security state
+ {0,0,0,0}, // OEM defined
+ 1, // 1U height
+ 2, // number of power cords
+ 0, // no contained elements
+ 3, // ContainedElementRecordLength;
+ },
+ TYPE3_ADDITIONAL_STRINGS
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8Vga = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortConnectorTypeDB15Female, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortTypeOther, // ExternalConnectorType;
+ PortTypeVideoPort, // PortType;
+ },
+ "VGA1 - Rear VGA Connector\0" \
+ "DB-15 Male (VGA)\0"
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8USBFront = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortConnectorTypeUsb, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortTypeOther, // ExternalConnectorType;
+ PortTypeUsb, // PortType;
+ },
+ "Front Panel USB 3.0\0" \
+ "USB\0"
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8USBRear = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortConnectorTypeUsb, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortTypeOther, // ExternalConnectorType;
+ PortTypeUsb, // PortType;
+ },
+ "Rear Panel USB 3.0\0" \
+ "USB\0"
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8NetRJ45 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortConnectorTypeRJ45, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortConnectorTypeRJ45, // ExternalConnectorType;
+ PortTypeNetworkPort, // PortType;
+ },
+ "RJ1 - BMC RJ45 Port\0" \
+ "RJ45 Connector\0"
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8NetOcp = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortTypeOther, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortTypeOther, // ExternalConnectorType;
+ PortTypeNetworkPort, // PortType;
+ },
+ "OCP1 - OCP NIC 3.0 Connector\0" \
+ "OCP NIC 3.0\0"
+};
+
+// Type 8 Port Connector Information
+STATIC CONST ARM_TYPE8 mArmDefaultType8Uart = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE8), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1, // InternalReferenceDesignator String
+ PortTypeOther, // InternalConnectorType;
+ ADDITIONAL_STR_INDEX_2, // ExternalReferenceDesignator String
+ PortConnectorTypeDB9Female, // ExternalConnectorType;
+ PortTypeSerial16550Compatible, // PortType;
+ },
+ "UART1 - BMC UART5 Connector\0" \
+ "DB-9 female\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk0RiserX32Slot1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth16X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 0,
+ 0,
+ 0,
+ },
+ "S0 Riser 1 x32 - Slot 1\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk0RiserX32Slot2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 4,
+ 0,
+ 0,
+ },
+ "S0 Riser x32 - Slot 2\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk0RiserX32Slot3 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 5,
+ 0,
+ 0,
+ },
+ "S0 Riser x32 - Slot 3\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1RiserX24Slot1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 7,
+ 0,
+ 0,
+ },
+ "S1 Riser x24 - Slot 1\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1RiserX24Slot2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 8,
+ 0,
+ 0,
+ },
+ "S1 Riser x24 - Slot 2\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1RiserX24Slot3 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 9,
+ 0,
+ 0,
+ },
+ "S1 Riser x24 - Slot 3\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1RiserX8Slot1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth8X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 8,
+ 0,
+ 0,
+ },
+ "S1 Riser x8 - Slot 1\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk0OcpNic = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth16X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 1,
+ 0,
+ 0,
+ },
+ "S0 OCP NIC 3.0\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1NvmeM2Slot1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth4X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 5,
+ 0,
+ 0,
+ },
+ "S1 NVMe M.2 - Slot 1\0"
+};
+
+// Type 9 System Slots
+STATIC ARM_TYPE9 mArmDefaultType9Sk1NvmeM2Slot2 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1,
+ SlotTypePciExpressGen3,
+ SlotDataBusWidth4X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1}, // Provides 3.3 Volts
+ {1}, // PME
+ 5,
+ 0,
+ 0,
+ },
+ "S1 NVMe M.2 - Slot 2\0"
+};
+
+// Type 11 OEM Strings
+STATIC ARM_TYPE11 mArmDefaultType11 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_OEM_STRINGS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE11), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ ADDITIONAL_STR_INDEX_1
+ },
+ TYPE11_ADDITIONAL_STRINGS
+};
+
+// Type 13 BIOS Language Information
+STATIC ARM_TYPE13 mArmDefaultType13 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1,
+ 0,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ 1,
+ },
+ TYPE13_ADDITIONAL_STRINGS
+};
+
+// Type 24 Hardware Security
+STATIC SMBIOS_TABLE_TYPE24 mArmDefaultType24 = {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_HARDWARE_SECURITY, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE24), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 0
+};
+
+// Type 32 System Boot Information
+STATIC SMBIOS_TABLE_TYPE32 mArmDefaultType32 = {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ {0, 0, 0, 0, 0, 0},
+ 0
+};
+
+// Type 38 IPMI Device Information
+STATIC SMBIOS_TABLE_TYPE38 mArmDefaultType38 = {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE38), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ IPMIDeviceInfoInterfaceTypeSSIF,
+ 0x20,
+ 0x20,
+ 0xFF,
+ 0x20
+};
+
+// Type 41 Onboard Devices Extended Information
+STATIC ARM_TYPE41 mArmDefaultType41 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION,
+ sizeof (SMBIOS_TABLE_TYPE41),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ 1,
+ 0x83, // OnBoardDeviceExtendedTypeVideo, Enabled
+ 1,
+ 4,
+ 2,
+ 0,
+ },
+ TYPE41_ADDITIONAL_STRINGS
+};
+
+// Type 42 System Boot Information
+STATIC SMBIOS_TABLE_TYPE42 mArmDefaultType42 = {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE,
+ sizeof (SMBIOS_TABLE_TYPE42),
+ SMBIOS_HANDLE_PI_RESERVED,
+ },
+ MCHostInterfaceTypeOemDefined,
+ 4,
+ {0xFF, 0, 0, 0}
+};
+
+STATIC CONST VOID *DefaultCommonTables[] =
+{
+ &mArmDefaultType0,
+ &mArmDefaultType1,
+ &mArmDefaultType2,
+ &mArmDefaultType8Vga,
+ &mArmDefaultType8USBFront,
+ &mArmDefaultType8USBRear,
+ &mArmDefaultType8NetRJ45,
+ &mArmDefaultType8NetOcp,
+ &mArmDefaultType8Uart,
+ &mArmDefaultType9Sk0RiserX32Slot1,
+ &mArmDefaultType9Sk0RiserX32Slot2,
+ &mArmDefaultType9Sk0RiserX32Slot3,
+ &mArmDefaultType9Sk1RiserX24Slot1,
+ &mArmDefaultType9Sk1RiserX24Slot2,
+ &mArmDefaultType9Sk1RiserX24Slot3,
+ &mArmDefaultType9Sk1RiserX8Slot1,
+ &mArmDefaultType9Sk0OcpNic,
+ &mArmDefaultType9Sk1NvmeM2Slot1,
+ &mArmDefaultType9Sk1NvmeM2Slot2,
+ &mArmDefaultType11,
+ &mArmDefaultType13,
+ &mArmDefaultType24,
+ &mArmDefaultType32,
+ &mArmDefaultType38,
+ &mArmDefaultType41,
+ &mArmDefaultType42,
+ NULL
+};
+
+typedef struct {
+ CHAR8 MonthNameStr[4]; // example "Jan", Compiler build date, month
+ CHAR8 DigitStr[3]; // example "01", Smbios date format, month
+} MonthStringDig;
+
+STATIC MonthStringDig MonthMatch[12] = {
+ { "Jan", "01" },
+ { "Feb", "02" },
+ { "Mar", "03" },
+ { "Apr", "04" },
+ { "May", "05" },
+ { "Jun", "06" },
+ { "Jul", "07" },
+ { "Aug", "08" },
+ { "Sep", "09" },
+ { "Oct", "10" },
+ { "Nov", "11" },
+ { "Dec", "12" }
+};
+
+STATIC
+VOID
+ConstructBuildDate (
+ OUT CHAR8 *DateBuf
+ )
+{
+ UINTN i;
+
+ // GCC __DATE__ format is "Feb 2 1996"
+ // If the day of the month is less than 10, it is padded with a space on the left
+ CHAR8 *BuildDate = __DATE__;
+
+ // SMBIOS spec date string: MM/DD/YYYY
+ CHAR8 SmbiosDateStr[sizeof (RELEASE_DATE_TEMPLATE)] = { 0 };
+
+ SmbiosDateStr[sizeof (RELEASE_DATE_TEMPLATE) - 1] = '\0';
+
+ SmbiosDateStr[2] = '/';
+ SmbiosDateStr[5] = '/';
+
+ // Month
+ for (i = 0; i < sizeof (MonthMatch) / sizeof (MonthMatch[0]); i++) {
+ if (AsciiStrnCmp (&BuildDate[0], MonthMatch[i].MonthNameStr, AsciiStrLen (MonthMatch[i].MonthNameStr)) == 0) {
+ CopyMem (&SmbiosDateStr[0], MonthMatch[i].DigitStr, AsciiStrLen (MonthMatch[i].DigitStr));
+ break;
+ }
+ }
+
+ // Day
+ CopyMem (&SmbiosDateStr[3], &BuildDate[4], 2);
+ if (BuildDate[4] == ' ') {
+ // day is less then 10, SAPCE filed by compiler, SMBIOS requires 0
+ SmbiosDateStr[3] = '0';
+ }
+
+ // Year
+ CopyMem (&SmbiosDateStr[6], &BuildDate[7], 4);
+
+ CopyMem (DateBuf, SmbiosDateStr, AsciiStrLen (RELEASE_DATE_TEMPLATE));
+}
+
+STATIC
+UINT8
+GetBiosVerMajor (
+ VOID
+ )
+{
+ return (PcdGet8 (PcdSmbiosTables1MajorVersion));
+}
+
+STATIC
+UINT8
+GetBiosVerMinor (
+ VOID
+ )
+{
+ return (PcdGet8 (PcdSmbiosTables1MinorVersion));
+}
+
+STATIC
+EFI_STATUS
+UpdateSmbiosType0 (
+ PLATFORM_INFO_HOB *PlatformHob
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ MISC_BIOS_CHARACTERISTICS_EXTENSION *MiscExt = NULL;
+ CHAR8 *ReleaseDateBuf = NULL;
+ CHAR8 *PcdReleaseDate = NULL;
+ CHAR8 AsciiVersion[32];
+ UINTN Index;
+
+ //
+ // Update Type0 information
+ //
+ ReleaseDateBuf = &mArmDefaultType0.Strings[0]
+ + sizeof (VENDOR_TEMPLATE) - 1
+ + sizeof (BIOS_VERSION_TEMPLATE) - 1;
+ PcdReleaseDate = (CHAR8 *)PcdGetPtr (PcdSmbiosTables0BiosReleaseDate);
+
+ if (AsciiStrnCmp (PcdReleaseDate, RELEASE_DATE_TEMPLATE, AsciiStrLen (RELEASE_DATE_TEMPLATE)) == 0) {
+ // If PCD is still template date MM/DD/YYYY, use compiler date
+ ConstructBuildDate (ReleaseDateBuf);
+ } else {
+ // PCD is updated somehow, use PCD date
+ CopyMem (ReleaseDateBuf, PcdReleaseDate, AsciiStrLen (PcdReleaseDate));
+ }
+
+ if (PcdGet32 (PcdFdSize) < SIZE_16MB) {
+ mArmDefaultType0.Base.BiosSize = (PcdGet32 (PcdFdSize) / SIZE_64KB) - 1;
+
+ mArmDefaultType0.Base.ExtendedBiosSize.Size = 0;
+ mArmDefaultType0.Base.ExtendedBiosSize.Unit = 0;
+ } else {
+ // Need to update Extended BIOS ROM Size
+ mArmDefaultType0.Base.BiosSize = 0xFF;
+
+ // As a reminder
+ ASSERT (FALSE);
+ }
+
+ // Type0 BIOS Characteristics Extension Byte 1
+ MiscExt = (MISC_BIOS_CHARACTERISTICS_EXTENSION *)&(mArmDefaultType0.Base.BIOSCharacteristicsExtensionBytes);
+
+ MiscExt->BiosReserved.AcpiIsSupported = 1;
+
+ // Type0 BIOS Characteristics Extension Byte 2
+ MiscExt->SystemReserved.BiosBootSpecIsSupported = 1;
+ MiscExt->SystemReserved.FunctionKeyNetworkBootIsSupported = 1;
+ MiscExt->SystemReserved.UefiSpecificationSupported = 1;
+
+ // Type0 BIOS Release
+ // Decide another way: If the system does not support the use of this
+ // field, the value is 0FFh
+ mArmDefaultType0.Base.SystemBiosMajorRelease = GetBiosVerMajor ();
+ mArmDefaultType0.Base.SystemBiosMinorRelease = GetBiosVerMinor ();
+
+ /* Update SMBIOS Type 0 EC Info */
+ CopyMem (
+ (VOID *)&AsciiVersion,
+ (VOID *)&PlatformHob->SmPmProVer,
+ sizeof (PlatformHob->SmPmProVer)
+ );
+ /* The AsciiVersion is formated as "major.minor" */
+ for (Index = 0; Index < (UINTN)AsciiStrLen (AsciiVersion); Index++) {
+ if (AsciiVersion[Index] == '.') {
+ AsciiVersion[Index] = '\0';
+ break;
+ }
+ }
+
+ mArmDefaultType0.Base.EmbeddedControllerFirmwareMajorRelease =
+ (UINT8)AsciiStrDecimalToUintn (AsciiVersion);
+ mArmDefaultType0.Base.EmbeddedControllerFirmwareMinorRelease =
+ (UINT8)AsciiStrDecimalToUintn (AsciiVersion + Index + 1);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+InstallType3Structure (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+
+ ASSERT (Smbios != NULL);
+
+ SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*) &mArmDefaultType3)->Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)&mArmDefaultType3
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "adding SMBIOS type 3 failed\n"));
+ // stop adding rather than continuing
+ return Status;
+ }
+
+ // Save this handle to type 2 table
+ mArmDefaultType2.Base.ChassisHandle = SmbiosHandle;
+
+ return Status;
+}
+
+/**
+ Install a whole table worth of structures
+
+ @param Smbios SMBIOS protocol.
+ @param DefaultTables A pointer to the default SMBIOS table structure.
+**/
+EFI_STATUS
+InstallStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios,
+ IN CONST VOID *DefaultTables[]
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ UINTN TableIndex;
+
+ ASSERT (Smbios != NULL);
+
+ for (TableIndex = 0; DefaultTables[TableIndex] != NULL; TableIndex++) {
+ SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableIndex])->Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableIndex]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: adding %d failed\n", __FUNCTION__, TableIndex));
+
+ // stop adding rather than continuing
+ return Status;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+UpdateSmbiosInfo (
+ VOID
+ )
+{
+ VOID *Hob;
+ PLATFORM_INFO_HOB *PlatformHob;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ ASSERT (Hob != NULL);
+ if (Hob == NULL) {
+ return;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ //
+ // Update Type0 information
+ //
+ UpdateSmbiosType0 (PlatformHob);
+
+}
+
+/**
+ Install all structures from the DefaultTables structure
+
+ @param Smbios SMBIOS protocol
+
+**/
+EFI_STATUS
+InstallAllStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ ASSERT (Smbios != NULL);
+
+ // Update SMBIOS Tables
+ UpdateSmbiosInfo ();
+
+ // Install Type 3 table
+ InstallType3Structure (Smbios);
+
+ // Install Tables
+ Status = InstallStructures (Smbios, DefaultCommonTables);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Installs SMBIOS information for ARM platforms
+
+ @param ImageHandle Module's image handle
+ @param SystemTable Pointer of EFI_SYSTEM_TABLE
+
+ @retval EFI_SUCCESS Smbios data successfully installed
+ @retval Other Smbios data was not installed
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosPlatformDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ //
+ // Find the SMBIOS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&Smbios
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = InstallAllStructures (Smbios);
+ DEBUG ((DEBUG_ERROR, "SmbiosPlatform install - %r\n", Status));
+
+ return Status;
+}
diff --git a/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.c b/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.c
new file mode 100644
index 000000000000..c6048b399b5a
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Library/OemMiscLib/OemMiscLib.c
@@ -0,0 +1,323 @@
+/** @file
+* OemMiscLib.c
+*
+* Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+* Copyright (c) 2021, NUVIA Inc. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/OemMiscLib.h>
+
+UINT32
+GetCacheConfig (
+ IN UINT32 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
+ )
+{
+ CSSELR_DATA Csselr;
+ UINT64 Ccsidr;
+ BOOLEAN SupportWB;
+ BOOLEAN SupportWT;
+
+ Csselr.Data = 0;
+ Csselr.Bits.Level = CacheLevel - 1;
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+
+ Ccsidr = ReadCCSIDR (Csselr.Data);
+ SupportWT = (Ccsidr & (1 << 31)) ? TRUE : FALSE;
+ SupportWB = (Ccsidr & (1 << 30)) ? TRUE : FALSE;
+
+ if (SupportWT && SupportWB) {
+ return 2; // Varies with Memory Address
+ }
+
+ if (SupportWT) {
+ return 0; // Write Through
+ }
+
+ if (SupportWB) {
+ return 1; // Write Back
+ }
+
+ return 3; // Unknown
+}
+
+/** Gets the CPU frequency of the specified processor.
+
+ @param ProcessorIndex Index of the processor to get the frequency for.
+
+ @return CPU frequency in Hz
+**/
+UINTN
+EFIAPI
+OemGetCpuFreq (
+ IN UINT8 ProcessorIndex
+ )
+{
+ return CpuGetCurrentFreq (ProcessorIndex);
+}
+
+/** Gets information about the specified processor and stores it in
+ the structures provided.
+
+ @param ProcessorIndex Index of the processor to get the information for.
+ @param ProcessorStatus Processor status.
+ @param ProcessorCharacteristics Processor characteritics.
+ @param MiscProcessorData Miscellaneous processor information.
+
+ @return TRUE on success, FALSE on failure.
+**/
+BOOLEAN
+EFIAPI
+OemGetProcessorInformation (
+ IN UINTN ProcessorIndex,
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
+ )
+{
+ UINT16 ProcessorCount;
+
+ ProcessorCount = GetNumberOfActiveSockets ();
+
+ if (ProcessorIndex < ProcessorCount) {
+ ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled
+ ProcessorStatus->Bits.Reserved1 = 0;
+ ProcessorStatus->Bits.SocketPopulated = 1;
+ ProcessorStatus->Bits.Reserved2 = 0;
+ } else {
+ ProcessorStatus->Bits.CpuStatus = 0; // CPU disabled
+ ProcessorStatus->Bits.Reserved1 = 0;
+ ProcessorStatus->Bits.SocketPopulated = 0;
+ ProcessorStatus->Bits.Reserved2 = 0;
+ }
+
+ ProcessorCharacteristics->ProcessorReserved1 = 0;
+ ProcessorCharacteristics->ProcessorUnknown = 0;
+ ProcessorCharacteristics->Processor64BitCapable = 1;
+ ProcessorCharacteristics->ProcessorMultiCore = 1;
+ ProcessorCharacteristics->ProcessorHardwareThread = 0;
+ ProcessorCharacteristics->ProcessorExecuteProtection = 1;
+ ProcessorCharacteristics->ProcessorEnhancedVirtualization = 1;
+ ProcessorCharacteristics->ProcessorPowerPerformanceCtrl = 1;
+ ProcessorCharacteristics->Processor128BitCapable = 0;
+ ProcessorCharacteristics->ProcessorReserved2 = 0;
+
+ MiscProcessorData->Voltage = CpuGetVoltage (ProcessorIndex);
+ MiscProcessorData->CurrentSpeed = (UINT16)CpuGetCurrentFreq (ProcessorIndex);
+ MiscProcessorData->MaxSpeed = (UINT16)CpuGetMaxFreq (ProcessorIndex);
+ MiscProcessorData->CoreCount = GetMaximumNumberOfCores ();
+ MiscProcessorData->ThreadCount = GetMaximumNumberOfCores ();
+ MiscProcessorData->CoresEnabled = GetNumberOfActiveCoresPerSocket (ProcessorIndex);
+
+ return TRUE;
+}
+
+/** Gets information about the cache at the specified cache level.
+
+ @param ProcessorIndex The processor to get information for.
+ @param CacheLevel The cache level to get information for.
+ @param DataCache Whether the cache is a data cache.
+ @param UnifiedCache Whether the cache is a unified cache.
+ @param SmbiosCacheTable The SMBIOS Type7 cache information structure.
+
+ @return TRUE on success, FALSE on failure.
+**/
+BOOLEAN
+EFIAPI
+OemGetCacheInformation (
+ IN UINT8 ProcessorIndex,
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
+ )
+{
+ SmbiosCacheTable->CacheConfiguration = CacheLevel - 1;
+ SmbiosCacheTable->CacheConfiguration |= (1 << 7); // Enable
+ SmbiosCacheTable->CacheConfiguration |= (GetCacheConfig (CacheLevel, DataCache, UnifiedCache) << 8);
+
+ SmbiosCacheTable->SupportedSRAMType.Unknown = 0;
+ SmbiosCacheTable->SupportedSRAMType.Synchronous = 1;
+ SmbiosCacheTable->CurrentSRAMType.Unknown = 0;
+ SmbiosCacheTable->CurrentSRAMType.Synchronous = 1;
+
+ if (CacheLevel == 1 && !DataCache && !UnifiedCache) {
+ SmbiosCacheTable->ErrorCorrectionType = CacheErrorParity;
+ } else {
+ SmbiosCacheTable->ErrorCorrectionType = CacheErrorSingleBit;
+ }
+
+ return TRUE;
+}
+
+/** Gets the maximum number of processors supported by the platform.
+
+ @return The maximum number of processors.
+**/
+UINT8
+EFIAPI
+OemGetMaxProcessors (
+ VOID
+ )
+{
+ return GetNumberOfSupportedSockets ();
+}
+
+/** Gets the type of chassis for the system.
+
+ @retval The type of the chassis.
+**/
+MISC_CHASSIS_TYPE
+EFIAPI
+OemGetChassisType (
+ VOID
+ )
+{
+ return MiscChassisTypeRackMountChassis;
+}
+
+/** Returns whether the specified processor is present or not.
+
+ @param ProcessIndex The processor index to check.
+
+ @return TRUE is the processor is present, FALSE otherwise.
+**/
+BOOLEAN
+EFIAPI
+OemIsProcessorPresent (
+ IN UINTN ProcessorIndex
+ )
+{
+ //
+ // Platform only supports 2 sockets: Master and Slave.
+ // The master socket is always online.
+ //
+ if (ProcessorIndex == 0) {
+ return TRUE;
+ } else if (ProcessorIndex == 1) {
+ return IsSlaveSocketPresent ();
+ }
+
+ return FALSE;
+}
+
+/** Updates the HII string for the specified field.
+
+ @param HiiHandle The HII handle.
+ @param TokenToUpdate The string to update.
+ @param Field The field to get information about.
+**/
+VOID
+EFIAPI
+OemUpdateSmbiosInfo (
+ IN EFI_HII_HANDLE HiiHandle,
+ IN EFI_STRING_ID TokenToUpdate,
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
+ )
+{
+ return;
+}
+
+/** Fetches the Type 32 boot information status.
+
+ @return Boot status.
+**/
+MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
+EFIAPI
+OemGetBootStatus (
+ VOID
+ )
+{
+ return BootInformationStatusNoError;
+}
+
+/** Fetches the chassis status when it was last booted.
+
+ @return Chassis status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisBootupState (
+ VOID
+ )
+{
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis power supply/supplies status when last booted.
+
+ @return Chassis power supply/supplies status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisPowerSupplyState (
+ VOID
+ )
+{
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis thermal status when last booted.
+
+ @return Chassis thermal status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisThermalState (
+ VOID
+ )
+{
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis security status when last booted.
+
+ @return Chassis security status.
+**/
+MISC_CHASSIS_SECURITY_STATE
+EFIAPI
+OemGetChassisSecurityStatus (
+ VOID
+ )
+{
+ return ChassisSecurityStatusNone;
+}
+
+/** Fetches the chassis height in RMUs (Rack Mount Units).
+
+ @return The height of the chassis.
+**/
+UINT8
+EFIAPI
+OemGetChassisHeight (
+ VOID
+ )
+{
+ return 1U;
+}
+
+/** Fetches the number of power cords.
+
+ @return The number of power cords.
+**/
+UINT8
+EFIAPI
+OemGetChassisNumPowerCords (
+ VOID
+ )
+{
+ return 2;
+}
--
2.17.1


[PATCH v3 19/28] AmpereAltraPkg: Add Random Number Generator Support

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

This change is to produce RNG protocol which is required by several
modules.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 5 +
Platform/Ampere/JadePkg/Jade.fdf | 5 +
Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf | 43 +++++
Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c | 164 ++++++++++++++++++++
Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni | 10 ++
Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxeExtra.uni | 9 ++
6 files changed, 236 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
index 655cf0258608..459d06c33c02 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
@@ -691,6 +691,11 @@ [Components.common]
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+ #
+ # Random Number Generator Support
+ #
+ Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf
+
#
# Bds
#
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 8ddfabcdd9a8..06c8a4fa1b09 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -305,6 +305,11 @@ [FV.FvMain]
#
INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf

+ #
+ # Random Number Generator Support
+ #
+ INF Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf
new file mode 100644
index 000000000000..c5f249e31090
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.inf
@@ -0,0 +1,43 @@
+## @file
+#
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = RngDxe
+ FILE_GUID = 4FCC006E-C740-4027-BC97-787907C8D286
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RngDriverEntry
+ MODULE_UNI_FILE = RngDxe.uni
+
+[Sources.common]
+ RngDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ TrngLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gEfiRngAlgorithmRaw ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
+
+[Protocols]
+ gEfiRngProtocolGuid ## PRODUCES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RngDxeExtra.uni
+
+[Depex]
+ TRUE
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c
new file mode 100644
index 000000000000..bb8140cfeb2f
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c
@@ -0,0 +1,164 @@
+/** @file
+
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TrngLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/Rng.h>
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
+ On output with a return code of EFI_SUCCESS, the size
+ in bytes of the data returned in RNGAlgorithmList. On output
+ with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of RNGAlgorithmList required to obtain the list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver
+ with one EFI_RNG_ALGORITHM element for each supported
+ RNG algorithm. The list must not change across multiple
+ calls to the same driver. The first algorithm in the list
+ is the default algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned successfully.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetInfo (
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ if (This == NULL || RNGAlgorithmListSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) {
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ if (RNGAlgorithmList == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RNGAlgorithmListSize = sizeof (EFI_RNG_ALGORITHM);
+ CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG
+ algorithm to use. May be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by
+ RNGValue. The driver shall return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the
+ resulting RNG value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by
+ this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or
+ firmware error.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ EFI_STATUS Status;
+
+ if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // We only support the raw algorithm, so reject requests for anything else
+ //
+ if (RNGAlgorithm != NULL &&
+ !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw))
+ {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = GenerateRandomNumbers (RNGValue, RNGValueLength);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a:%d Failed to generate a random number. \n",
+ __FUNCTION__,
+ __LINE__
+ ));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * The Random Number Generator (RNG) protocol
+ */
+EFI_RNG_PROTOCOL mRng = {
+ RngGetInfo,
+ RngGetRNG
+};
+
+/**
+ The user Entry Point for the Random Number Generator (RNG) driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval EFI_NOT_SUPPORTED Platform does not support RNG.
+ @retval Other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+RngDriverEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ //
+ // Install UEFI RNG (Random Number Generator) Protocol
+ //
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRngProtocolGuid,
+ &mRng,
+ NULL
+ );
+
+ return Status;
+}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni
new file mode 100644
index 000000000000..cd9dde97a236
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.uni
@@ -0,0 +1,10 @@
+//
+// Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Produces UEFI Random Number Generator protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "This module will produce UEFI Random Number Generator protocol."
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxeExtra.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxeExtra.uni
new file mode 100644
index 000000000000..9a3696b25442
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxeExtra.uni
@@ -0,0 +1,9 @@
+//
+// Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"Ampere UEFI Random Number Generator DXE"
--
2.17.1


[PATCH v3 18/28] Ampere: PCIe: Add PciPlatformDxe driver

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Registers the Platform NotifyPhase() to prevent unexpected issues
caused by the enabled PCIe controllers which have unstable link.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Platform/Ampere/JadePkg/Jade.dsc | 5 +
Platform/Ampere/JadePkg/Jade.fdf | 1 +
Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf | 37 ++++
Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c | 212 ++++++++++++++++++++
4 files changed, 255 insertions(+)

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index b733f8430806..ce5f2c0dc4e1 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -148,6 +148,11 @@ [Components.common]
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf

+ #
+ # PCIe
+ #
+ Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf
+
#
# VGA Aspeed
#
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 195da2d63a7a..8ddfabcdd9a8 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -298,6 +298,7 @@ [FV.FvMain]
#
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf

#
# VGA Aspeed
diff --git a/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf
new file mode 100644
index 000000000000..5f5316055217
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf
@@ -0,0 +1,37 @@
+## @file
+#
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciPlatformDxe
+ FILE_GUID = 73276F3D-DCBC-49B2-9890-7564F917501D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciPlatformDriverEntry
+
+[Sources]
+ PciPlatformDxe.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+
+[LibraryClasses]
+ Ac01PcieLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiDevicePathProtocolGuid
+ gEfiPciHostBridgeResourceAllocationProtocolGuid
+ gEfiPciPlatformProtocolGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c
new file mode 100644
index 000000000000..196f857175e9
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c
@@ -0,0 +1,212 @@
+/** @file
+
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/Ac01PcieLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciPlatform.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+/**
+
+ Perform initialization by the phase indicated.
+
+ @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ @param HostBridge The associated PCI host bridge handle.
+ @param Phase The phase of the PCI controller enumeration.
+ @param ChipsetPhase Defines the execution phase of the PCI chipset driver.
+
+ @retval EFI_SUCCESS Must return with success.
+
+**/
+EFI_STATUS
+EFIAPI
+PhaseNotify (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+{
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *RootBridgeDevPath;
+ EFI_HANDLE RootBridgeHandle = NULL;
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL;
+ EFI_STATUS Status;
+
+ if (ChipsetPhase != ChipsetExit) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Get HostBridgeInstance from HostBridge handle.
+ //
+ Status = gBS->HandleProtocol (
+ HostBridge,
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid,
+ (VOID **)&ResAlloc
+ );
+
+ while (TRUE) {
+ Status = ResAlloc->GetNextRootBridge (ResAlloc, &RootBridgeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ Status = gBS->HandleProtocol (
+ RootBridgeHandle,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **)&RootBridgeDevPath
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a %d: Failed to locate RootBridge DevicePath\n", __FUNCTION__, __LINE__));
+ break;
+ }
+
+ Ac01PcieHostBridgeNotifyPhase (RootBridgeDevPath->AcpiDevicePath.UID, 0, Phase);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ The PlatformPrepController() function can be used to notify the platform driver so that
+ it can perform platform-specific actions. No specific actions are required.
+ Several notification points are defined at this time. More synchronization points may be
+ added as required in the future. The PCI bus driver calls the platform driver twice for
+ every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver
+ is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has
+ been notified.
+ This member function may not perform any error checking on the input parameters. It also
+ does not return any error codes. If this member function detects any error condition, it
+ needs to handle those errors on its own because there is no way to surface any errors to
+ the caller.
+
+ @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance.
+ @param HostBridge The associated PCI host bridge handle.
+ @param RootBridge The associated PCI root bridge handle.
+ @param PciAddress The address of the PCI device on the PCI bus.
+ @param Phase The phase of the PCI controller enumeration.
+ @param ChipsetPhase Defines the execution phase of the PCI chipset driver.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_UNSUPPORTED Not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformPrepController (
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE HostBridge,
+ IN EFI_HANDLE RootBridge,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS.
+
+ @param This The pointer to the Protocol itself.
+ @param PciPolicy The returned Policy.
+
+ @retval EFI_UNSUPPORTED Function not supported.
+ @retval EFI_INVALID_PARAMETER Invalid PciPolicy value.
+
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformPolicy (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ Return a PCI ROM image for the onboard device represented by PciHandle.
+
+ @param This Protocol instance pointer.
+ @param PciHandle PCI device to return the ROM image for.
+ @param RomImage PCI Rom Image for onboard device.
+ @param RomSize Size of RomImage in bytes.
+
+ @retval EFI_SUCCESS RomImage is valid.
+ @retval EFI_NOT_FOUND No RomImage.
+
+**/
+EFI_STATUS
+EFIAPI
+GetPciRom (
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,
+ IN EFI_HANDLE PciHandle,
+ OUT VOID **RomImage,
+ OUT UINTN *RomSize
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+//
+// Interface defintion of PCI Platform protocol.
+//
+EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol = {
+ .PlatformNotify = PhaseNotify,
+ .PlatformPrepController = PlatformPrepController,
+ .GetPlatformPolicy = GetPlatformPolicy,
+ .GetPciRom = GetPciRom
+};
+
+/**
+
+ The Entry point of the Pci Platform Driver.
+
+ @param ImageHandle Handle to the image.
+ @param SystemTable Handle to System Table.
+
+ @retval EFI_STATUS Status of the function calling.
+
+**/
+EFI_STATUS
+PciPlatformDriverEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE PciPlatformHandle;
+
+ //
+ // Install on a new handle
+ //
+ PciPlatformHandle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &PciPlatformHandle,
+ &gEfiPciPlatformProtocolGuid,
+ &mPciPlatformProtocol,
+ NULL
+ );
+
+ return Status;
+}
--
2.17.1


[PATCH v3 15/28] Ampere: PCIe: Add PciSegmentLib library instance

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Provides wrapper calls to the Ac01PcieLib to handle the PCIe access.
As Ampere Altra processor supports upto 16 PCIe Root Complexs, the
target Root Complex will depend on the segment number parsed from the
input address.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 1 +
Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf | 28 +
Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c | 1189 ++++++++++++++++++++
3 files changed, 1218 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
index dc66b711aba8..dbcd1c9acaa2 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
@@ -229,6 +229,7 @@ [LibraryClasses.common.DXE_DRIVER]
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
FlashLib|Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.inf
PciHostBridgeLib|Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+ PciSegmentLib|Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf

[LibraryClasses.common.UEFI_APPLICATION]
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCustomDecompressLib.inf
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
new file mode 100644
index 000000000000..64897653e126
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
@@ -0,0 +1,28 @@
+## @file
+#
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciSegmentLibPci
+ FILE_GUID = 0AF5E76D-D31E-492B-AE69-A7B441FF62D9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+
+[LibraryClasses]
+ Ac01PcieLib
+ BaseLib
+ DebugLib
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
new file mode 100644
index 000000000000..c893c56dfadf
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
@@ -0,0 +1,1189 @@
+/** @file
+
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/Ac01PcieLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PciLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#include <Ac01PcieCommon.h>
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+ and the segment should be 0.
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+/**
+ Convert the PCI Segment library address to PCI library address.
+
+ @param A The address to convert.
+**/
+#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN)(UINT32)A)
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+ return PciRegisterForRuntimeAccess (PCI_SEGMENT_TO_PCI_ADDRESS (Address));
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return PciRead8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return PciRead16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return PciWrite16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by OrData, and
+ writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned. This function
+ must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+ the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciRead32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciWrite32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param Address PCI configuration register to read.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param Value New value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param Address PCI configuration register to write.
+ @param StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param AndData The value to AND with the PCI configuration register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ Status = Ac01PcieConfigRW (NULL, StartAddress, FALSE, Size, Buffer);
+ ASSERT_EFI_ERROR (Status);
+
+ return Size;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAddress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+ @param Size Size in bytes of the transfer.
+ @param Buffer Pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ Status = Ac01PcieConfigRW (NULL, StartAddress, TRUE, Size, Buffer);
+ ASSERT_EFI_ERROR (Status);
+
+ return Size;
+}
--
2.17.1


[PATCH v3 17/28] JadePkg: Add ASpeed GOP driver

Nhi Pham
 

This wires up the pre-built binary placed in the edk2-non-osi
repository for PCIe VGA Controller support.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Ampere/JadePkg/Jade.dsc | 12 ++++++++++++
Platform/Ampere/JadePkg/Jade.fdf | 5 +++++
2 files changed, 17 insertions(+)

diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index afea3407a256..b733f8430806 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -119,6 +119,13 @@ [PcdsFixedAtBuild.common]
!endif


+[PcdsPatchableInModule]
+ #
+ # Console Resolution (HD mode)
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
################################################################################
#
# Specific Platform Component
@@ -140,3 +147,8 @@ [Components.common]
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
+
+ #
+ # VGA Aspeed
+ #
+ Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 3f1ad9a49cd0..195da2d63a7a 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -299,6 +299,11 @@ [FV.FvMain]
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+ #
+ # VGA Aspeed
+ #
+ INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2500GopDxe.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
2.17.1


[PATCH v3 16/28] JadePkg: Enable PCIe-related libraries and device drivers

Nhi Pham
 

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

This change also enables the support for SCSI, NVMe, USB keyboard, and
USB storage devices.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Vu Nguyen <vunguyen@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 34 ++++++++++++++++++++
Platform/Ampere/JadePkg/Jade.fdf | 33 +++++++++++++++++++
2 files changed, 67 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
index dbcd1c9acaa2..655cf0258608 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
@@ -82,6 +82,7 @@ [LibraryClasses.common]
NVParamLib|Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf
MailboxInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.inf
SystemFirmwareInterfaceLib|Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.inf
+ PciePhyLib|Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf
Ac01PcieLib|Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/Ac01PcieLib.inf
AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
@@ -657,6 +658,39 @@ [Components.common]
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf

+ #
+ # SCSI Bus and Disk Driver
+ #
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # SATA Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # NVME Support
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # PCIe Support
+ #
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
#
# Bds
#
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 2c6f9fac76fd..3f1ad9a49cd0 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -266,6 +266,39 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+ #
+ # SCSI Bus and Disk Driver
+ #
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+ #
+ # SATA Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # NVME Support
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # PCIe Support
+ #
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
2.17.1


[PATCH v3 11/28] AmpereAltraPkg, JadePkg: Add ACPI support

Nhi Pham
 

Add various ACPI tables for the Mt. Jade platform including: DSDT, SPCR,
DBG2, GTDT, FACP, SSDT, MADT, PPTT, PCCT, SLIT, SRAT, and NFIT.

Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Acked-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 8 +
Platform/Ampere/JadePkg/Jade.dsc | 21 +
Platform/Ampere/JadePkg/Jade.fdf | 8 +
Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf | 20 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 77 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf | 44 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h | 121 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.h | 49 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h | 75 +
Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h | 37 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c | 449 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c | 601 +++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c | 348 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.c | 596 +++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPcct.c | 413 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c | 178 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c | 333 ++
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSlit.c | 187 +
Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c | 271 +
Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi | 5639 ++++++++++++++++++++
Platform/Ampere/JadePkg/AcpiTables/CPU-S1.asi | 5639 ++++++++++++++++++++
Platform/Ampere/JadePkg/AcpiTables/CPU.asi | 127 +
Platform/Ampere/JadePkg/AcpiTables/Dsdt.asl | 531 ++
Platform/Ampere/JadePkg/AcpiTables/PCI-PDRC.asi | 217 +
Platform/Ampere/JadePkg/AcpiTables/PCI-S0.Rca01.asi | 681 +++
Platform/Ampere/JadePkg/AcpiTables/PCI-S0.asi | 2078 ++++++++
Platform/Ampere/JadePkg/AcpiTables/PCI-S1.asi | 2087 ++++++++
Platform/Ampere/JadePkg/AcpiTables/PMU-S0.asi | 1303 +++++
Platform/Ampere/JadePkg/AcpiTables/PMU-S1.asi | 1303 +++++
Platform/Ampere/JadePkg/AcpiTables/PMU.asi | 10 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Bert.aslc | 33 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Dbg2.aslc | 87 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Einj.asl | 165 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Fadt.aslc | 87 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Gtdt.aslc | 180 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Hest.asl | 330 ++
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Sdei.asl | 17 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Spcr.aslc | 81 +
Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/Ssdt.asl | 15 +
39 files changed, 24446 insertions(+)

diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
index aee00f114666..4af85f721cb3 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
@@ -468,6 +468,14 @@ [PcdsFixedAtBuild.common]
#
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }

+ #
+ # ACPI table
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"Ampere"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020206172746C41 # Altra
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x2E504D41 # AMP.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013
+
#
# Enable strict image permissions for all images. (This applies
# only to images that were built with >= 4 KB section alignment.)
diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc
index c670fd0f34b6..118c03eab42f 100644
--- a/Platform/Ampere/JadePkg/Jade.dsc
+++ b/Platform/Ampere/JadePkg/Jade.dsc
@@ -83,12 +83,22 @@ [LibraryClasses]
#
FailSafeLib|Platform/Ampere/AmperePlatformPkg/Library/FailSafeLib/FailSafeLib.inf

+ #
+ # ACPI Libraries
+ #
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+
################################################################################
#
# Specific Platform Pcds
#
################################################################################
[PcdsFeatureFlag.common]
+ #
+ # Activate AcpiSdtProtocol
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
[PcdsFixedAtBuild.common]
#
# NVRAM
@@ -114,3 +124,14 @@ [Components.common]
# FailSafe and Watchdog Timer
#
Platform/Ampere/AmperePlatformPkg/Drivers/FailSafeDxe/FailSafeDxe.inf
+
+ #
+ # ACPI
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2B
+ }
+ Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
+ Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf
index 375455086d0b..2c6f9fac76fd 100644
--- a/Platform/Ampere/JadePkg/Jade.fdf
+++ b/Platform/Ampere/JadePkg/Jade.fdf
@@ -289,4 +289,12 @@ [FV.FvMain]
#
!include NetworkPkg/Network.fdf.inc

+ #
+ # ACPI
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
+ INF RuleOverride=ACPITABLE Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
+
!include Platform/Ampere/AmperePlatformPkg/FvRules.fdf.inc
diff --git a/Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf b/Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..1cf632f8a406
--- /dev/null
+++ b/Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf
@@ -0,0 +1,20 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = JadeAcpiTables
+ FILE_GUID = 5ADDBC13-8634-480C-9B94-671B7855CDB8
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 000000000000..2b2a3728a406
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,77 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = AcpiPlatformDxe
+ FILE_GUID = CDA4ED56-6960-4092-885D-FEF37D29093E
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformDxeInitialize
+
+[Sources.common]
+ AcpiApei.c
+ AcpiApei.h
+ AcpiDsdt.c
+ AcpiMadt.c
+ AcpiNfit.c
+ AcpiPcct.c
+ AcpiPptt.c
+ AcpiPlatform.h
+ AcpiPlatformDxe.c
+ AcpiSlit.c
+ AcpiSrat.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+ Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec
+
+[LibraryClasses]
+ AcpiLib
+ AmpereCpuLib
+ ArmLib
+ BaseLib
+ DebugLib
+ FlashLib
+ MailboxInterfaceLib
+ SystemFirmwareInterfaceLib
+ TimerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gAmpereTokenSpaceGuid.PcdPmproDbBaseReg
+ gAmpereTokenSpaceGuid.PcdSmproDbBaseReg
+
+[Guids]
+ gArmMpCoreInfoGuid
+ gEfiAcpiTableGuid
+ gEfiEventReadyToBootGuid
+ gPlatformHobGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED
+ gEfiAcpiSdtProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
diff --git a/Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf b/Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
new file mode 100644
index 000000000000..acc4092c650d
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf
@@ -0,0 +1,44 @@
+## @file
+#
+# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = AcpiCommonTables
+ FILE_GUID = CEFA2AEB-357E-4F48-8066-EA950853056E
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Bert.aslc
+ Dbg2.aslc
+ Einj.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Hest.asl
+ Sdei.asl
+ Spcr.aslc
+ Ssdt.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt ## CONSUMES
+ gArmPlatformTokenSpaceGuid.PcdWatchdogCount ## CONSUMES
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES
+
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## CONSUMES
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
new file mode 100644
index 000000000000..2e763422cbc6
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.h
@@ -0,0 +1,121 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_APEI_H_
+#define ACPI_APEI_H_
+
+#include <Base.h>
+#include <IndustryStandard/Acpi63.h>
+#include <Library/AcpiLib.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Platform/Ac01.h>
+#include <Protocol/AcpiTable.h>
+
+#pragma pack(1)
+#define BERT_MSG_SIZE 0x2C
+#define BERT_ERROR_TYPE 0x7F
+#define BERT_UEFI_FAILURE 5
+#define RAS_2P_TYPE 0x03
+#define BERT_DEFAULT_ERROR_SEVERITY 0x1
+#define GENERIC_ERROR_DATA_REVISION 0x300
+
+
+#define PLAT_CRASH_ITERATOR_SIZE 0x398
+#define SMPRO_CRASH_SIZE 0x800
+#define PMPRO_CRASH_SIZE 0x800
+#define HEST_NUM_ENTRIES_PER_SOC 3
+
+#define CURRENT_BERT_VERSION 0x10
+#define BERT_FLASH_OFFSET 0x91B30000ULL
+#define BERT_DDR_OFFSET 0x88230000ULL
+#define BERT_DDR_LENGTH 0x50000
+
+typedef struct {
+ UINT8 Type;
+ UINT8 SubType;
+ UINT16 Instance;
+ CHAR8 Msg[BERT_MSG_SIZE];
+} APEI_BERT_ERROR_DATA;
+
+typedef struct {
+ APEI_BERT_ERROR_DATA Vendor;
+ UINT8 BertRev;
+ UINT8 S0PmproRegisters[PMPRO_CRASH_SIZE];
+ UINT8 S0SmproRegisters[SMPRO_CRASH_SIZE];
+ UINT8 S1PmproRegisters[PMPRO_CRASH_SIZE];
+ UINT8 S1SmproRegisters[SMPRO_CRASH_SIZE];
+ UINT8 AtfDump[PLATFORM_CPU_MAX_NUM_CORES * PLAT_CRASH_ITERATOR_SIZE];
+} APEI_CRASH_DUMP_DATA;
+
+typedef struct {
+ EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE Ges;
+ EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE Ged;
+ APEI_CRASH_DUMP_DATA Bed;
+} APEI_CRASH_DUMP_BERT_ERROR;
+#pragma pack()
+
+VOID
+EFIAPI
+CreateDefaultBertData (
+ APEI_BERT_ERROR_DATA *Data
+ );
+
+VOID
+EFIAPI
+WrapBertErrorData (
+ APEI_CRASH_DUMP_BERT_ERROR *WrappedError
+ );
+
+VOID
+EFIAPI
+PullBertSpinorData (
+ APEI_CRASH_DUMP_DATA *BertErrorData
+ );
+
+VOID
+EFIAPI
+AdjustBERTRegionLen (
+ UINT32 Len
+ );
+
+BOOLEAN
+EFIAPI
+IsBertEnabled (
+ VOID
+ );
+
+VOID
+EFIAPI
+WriteDDRBertTable (
+ APEI_CRASH_DUMP_BERT_ERROR *Data
+ );
+
+VOID
+WriteSpinorDefaultBertTable (
+ APEI_CRASH_DUMP_DATA *SpiRefrenceData
+ );
+
+EFI_STATUS
+EFIAPI
+AcpiApeiUpdate (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AcpiPopulateBert (
+ VOID
+ );
+
+#endif /* ACPI_APEI_H_ */
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.h b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.h
new file mode 100644
index 000000000000..920579281dd5
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.h
@@ -0,0 +1,49 @@
+/** @file
+
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_NFIT_H_
+#define ACPI_NFIT_H_
+
+#include <Platform/Ac01.h>
+
+#define NVDIMM_SK0 0
+#define NVDIMM_SK1 1
+#define NVDIMM_NUM_PER_SK (PLATFORM_NVDIMM_MCU_MAX_PER_SK * PLATFORM_NVDIMM_NUM_MAX_PER_MCU)
+#define ONE_GB (1024 * 1024 * 1024)
+
+enum NvdimmMode {
+ NVDIMM_DISABLED = 0,
+ NVDIMM_NON_HASHED = 1,
+ NVDIMM_HASHED = 2
+};
+
+typedef struct {
+ BOOLEAN Enabled;
+ UINT64 NvdSize;
+ UINT32 DeviceHandle;
+ UINT16 PhysId;
+ UINT8 InterleaveWays;
+ UINT64 RegionOffset;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 RevisionId;
+ UINT16 SubVendorId;
+ UINT16 SubDeviceId;
+ UINT16 SubRevisionId;
+ UINT32 SerialNumber;
+} NVDIMM_INFO;
+
+typedef struct {
+ UINT8 NvdRegionNum;
+ UINT8 NvdRegionId[PLATFORM_NVDIMM_REGION_MAX_PER_SK];
+ UINT8 NvdMode;
+ UINT8 NvdNum;
+ NVDIMM_INFO NvdInfo[NVDIMM_NUM_PER_SK];
+} NVDIMM_DATA;
+
+#endif
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h
new file mode 100644
index 000000000000..a321bfbf3adb
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatform.h
@@ -0,0 +1,75 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_PLATFORM_H_
+#define ACPI_PLATFORM_H_
+
+#include <Uefi.h>
+
+#include <AcpiHeader.h>
+#include <Guid/EventGroup.h>
+#include <Guid/PlatformInfoHobGuid.h>
+#include <IndustryStandard/Acpi63.h>
+#include <Library/ArmLib/ArmLibPrivate.h>
+#include <Library/AcpiLib.h>
+#include <Library/AmpereCpuLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Platform/Ac01.h>
+#include <PlatformInfoHob.h>
+#include <Protocol/AcpiTable.h>
+
+EFI_STATUS
+AcpiPatchDsdtTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallMadtTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallNfitTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiPcctInitializeSharedMemory (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallPcctTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallPpttTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallSlitTable (
+ VOID
+ );
+
+EFI_STATUS
+AcpiInstallSratTable (
+ VOID
+ );
+
+#endif /* ACPI_PLATFORM_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h
new file mode 100644
index 000000000000..d604b712d8c8
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h
@@ -0,0 +1,37 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ACPI_HEADER_H_
+#define ACPI_HEADER_H_
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_OEM_ID {'A','m','p','e','r','e'}
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('A','l','t','r','a',' ',' ',' ')
+#define EFI_ACPI_OEM_REVISION FixedPcdGet32 (PcdAcpiDefaultOemRevision)
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('A','M','P','.')
+#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define __ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ EFI_ACPI_OEM_ID, /* UINT8 OemId[6] */ \
+ EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#endif /* ACPI_HEADER_H_ */
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
new file mode 100644
index 000000000000..a216edac60ce
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiApei.c
@@ -0,0 +1,449 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/FlashLib.h>
+#include <Library/NVParamLib.h>
+#include <NVParamDef.h>
+
+#include "AcpiApei.h"
+
+UINT8 AMPERE_GUID[16] = {0x8d, 0x89, 0xed, 0xe8, 0x16, 0xdf, 0xcc, 0x43, 0x8e, 0xcc, 0x54, 0xf0, 0x60, 0xef, 0x15, 0x7f};
+CHAR8 DEFAULT_BERT_REBOOT_MSG[BERT_MSG_SIZE] = "Unknown reboot reason";
+
+STATIC VOID
+AcpiApeiUninstallTable (
+ UINT32 Signature
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableSdtProtocol;
+ EFI_ACPI_SDT_HEADER *Table;
+ UINTN TableKey;
+ UINTN TableIndex;
+
+ /*
+ * Get access to ACPI tables
+ */
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTableProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d: Unable to locate ACPI table protocol\n", __FUNCTION__, __LINE__));
+ return;
+ }
+
+ Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&AcpiTableSdtProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d: Unable to locate ACPI table support protocol\n", __FUNCTION__, __LINE__));
+ return;
+ }
+
+ /*
+ * Search for ACPI Table Signature
+ */
+ TableIndex = 0;
+ Status = AcpiLocateTableBySignature (
+ AcpiTableSdtProtocol,
+ Signature,
+ &TableIndex,
+ (EFI_ACPI_DESCRIPTION_HEADER **)&Table,
+ &TableKey
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d Unable to get ACPI table\n", __FUNCTION__, __LINE__));
+ return;
+ }
+
+ /*
+ * Uninstall ACPI Table
+ */
+ Status = AcpiTableProtocol->UninstallAcpiTable (AcpiTableProtocol, TableKey);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d: Unable to uninstall table\n", __FUNCTION__, __LINE__));
+ }
+}
+
+VOID
+AdjustBERTRegionLen (
+ UINT32 Len
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableSdtProtocol;
+ UINTN TableKey;
+ UINTN TableIndex;
+ EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER *Table;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSdtProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableSdtProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "APEI: Unable to locate ACPI table support protocol\n"));
+ return;
+ }
+
+ /*
+ * Search for ACPI Table Signature
+ */
+ TableIndex = 0;
+ Status = AcpiLocateTableBySignature (
+ AcpiTableSdtProtocol,
+ EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE,
+ &TableIndex,
+ (EFI_ACPI_DESCRIPTION_HEADER **)&Table,
+ &TableKey
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d Unable to get ACPI BERT table\n", __FUNCTION__, __LINE__));
+ return;
+ }
+
+ /*
+ * Adjust Boot Error Region Length
+ */
+ Table->BootErrorRegionLength = Len;
+
+ AcpiUpdateChecksum ((UINT8 *)Table, Table->Header.Length);
+}
+
+/*
+ * Retrieve Bert data from SPI NOR
+ */
+VOID
+PullBertSpinorData (
+ APEI_CRASH_DUMP_DATA *BertErrorData
+ )
+{
+ UINTN Length;
+
+ Length = sizeof (*BertErrorData);
+
+ FlashReadCommand (
+ (UINT8 *)BERT_FLASH_OFFSET,
+ (UINT8 *)BertErrorData,
+ &Length
+ );
+}
+
+/*
+ * wrap raw bert error data
+ *
+ * @param IN BertErrorData Bert Error record to be wrapped
+ * @param OUT WrappedError Generic error data for OS to consume.
+ */
+VOID
+WrapBertErrorData (
+ APEI_CRASH_DUMP_BERT_ERROR *WrappedError
+ )
+{
+ UINT32 CrashSize;
+
+ CrashSize = PLAT_CRASH_ITERATOR_SIZE *
+ GetNumberOfSupportedSockets () *
+ GetMaximumNumberOfCores ();
+ CrashSize += 2 * (SMPRO_CRASH_SIZE + PMPRO_CRASH_SIZE);
+ CrashSize += sizeof (WrappedError->Bed.Vendor) + sizeof (WrappedError->Bed.BertRev);
+
+ WrappedError->Ges.BlockStatus.ErrorDataEntryCount = 1;
+ WrappedError->Ges.BlockStatus.UncorrectableErrorValid = 1;
+ WrappedError->Ged.ErrorSeverity = BERT_DEFAULT_ERROR_SEVERITY;
+ WrappedError->Ged.Revision = GENERIC_ERROR_DATA_REVISION;
+
+ if (WrappedError->Bed.Vendor.Type == RAS_2P_TYPE ||
+ (WrappedError->Bed.Vendor.Type == BERT_ERROR_TYPE &&
+ (WrappedError->Bed.Vendor.SubType == 0 ||
+ WrappedError->Bed.Vendor.SubType == BERT_UEFI_FAILURE)))
+ {
+ WrappedError->Ged.ErrorDataLength = sizeof (WrappedError->Bed.Vendor) +
+ sizeof (WrappedError->Bed.BertRev);
+ WrappedError->Ges.DataLength = sizeof (WrappedError->Bed.Vendor) +
+ sizeof (WrappedError->Bed.BertRev) +
+ sizeof (WrappedError->Ged);
+ AdjustBERTRegionLen (
+ sizeof (WrappedError->Bed.Vendor) +
+ sizeof (WrappedError->Bed.BertRev) +
+ sizeof (WrappedError->Ged) +
+ sizeof (WrappedError->Ges)
+ );
+ } else {
+ WrappedError->Ged.ErrorDataLength = CrashSize;
+ WrappedError->Ges.DataLength = CrashSize + sizeof (WrappedError->Ged);
+ AdjustBERTRegionLen (
+ CrashSize +
+ sizeof (WrappedError->Ged) +
+ sizeof (WrappedError->Ges)
+ );
+ }
+ CopyMem (
+ WrappedError->Ged.SectionType,
+ AMPERE_GUID,
+ sizeof (AMPERE_GUID)
+ );
+}
+
+
+/*
+ * create default bert error
+ * Msg: Unknown reboot reason
+ */
+VOID
+CreateDefaultBertData (
+ APEI_BERT_ERROR_DATA *Data
+ )
+{
+ Data->Type = BERT_ERROR_TYPE;
+ AsciiStrCpyS (
+ Data->Msg,
+ BERT_MSG_SIZE,
+ DEFAULT_BERT_REBOOT_MSG
+ );
+}
+
+/*
+ * Ensures BertErrorData In SPINOR matches
+ * the record produced by CreateDefaultBertData.
+ * @param Bed Crash dump Data
+ */
+VOID
+WriteSpinorDefaultBertTable (
+ APEI_CRASH_DUMP_DATA *Bed
+ )
+{
+ UINT8 BertRev;
+ UINTN Length;
+ UINT64 Offset;
+ UINT32 MsgDiff;
+ APEI_BERT_ERROR_DATA DefaultData = {0};
+
+ CreateDefaultBertData (&DefaultData);
+ if ((Bed->Vendor.Type != DefaultData.Type)) {
+ Offset = BERT_FLASH_OFFSET +
+ OFFSET_OF (APEI_CRASH_DUMP_DATA, Vendor) +
+ OFFSET_OF (APEI_BERT_ERROR_DATA, Type);
+ Length = sizeof (DefaultData.Type);
+ FlashEraseCommand ((UINT8 *)Offset, Length);
+ FlashProgramCommand (
+ (UINT8 *)Offset,
+ (UINT8 *)&(DefaultData.Type),
+ &Length
+ );
+ }
+
+ if ((Bed->Vendor.SubType != DefaultData.SubType)) {
+ Offset = BERT_FLASH_OFFSET +
+ OFFSET_OF (APEI_CRASH_DUMP_DATA, Vendor) +
+ OFFSET_OF (APEI_BERT_ERROR_DATA, SubType);
+ Length = sizeof (DefaultData.SubType);
+ FlashEraseCommand ((UINT8 *)Offset, Length);
+ FlashProgramCommand (
+ (UINT8 *)Offset,
+ (UINT8 *)&(DefaultData.SubType),
+ &Length
+ );
+ }
+
+ if ((Bed->Vendor.Instance != DefaultData.Instance)) {
+ Offset = BERT_FLASH_OFFSET +
+ OFFSET_OF (APEI_CRASH_DUMP_DATA, Vendor) +
+ OFFSET_OF (APEI_BERT_ERROR_DATA, Instance);
+ Length = sizeof (DefaultData.Instance);
+ FlashEraseCommand ((UINT8 *)Offset, Length);
+ FlashProgramCommand (
+ (UINT8 *)Offset,
+ (UINT8 *)&(DefaultData.Instance),
+ &Length
+ );
+ }
+
+ MsgDiff = AsciiStrnCmp (Bed->Vendor.Msg, DefaultData.Msg, BERT_MSG_SIZE);
+ if (MsgDiff != 0) {
+ Offset = BERT_FLASH_OFFSET +
+ OFFSET_OF (APEI_CRASH_DUMP_DATA, Vendor) +
+ OFFSET_OF (APEI_BERT_ERROR_DATA, Msg);
+ Length = sizeof (DefaultData.Msg);
+ FlashEraseCommand ((UINT8 *)Offset, Length);
+ FlashProgramCommand (
+ (UINT8 *)Offset,
+ (UINT8 *)&(DefaultData.Msg),
+ &Length
+ );
+ }
+
+ if (Bed->BertRev != CURRENT_BERT_VERSION) {
+ Offset = BERT_FLASH_OFFSET + OFFSET_OF (APEI_CRASH_DUMP_DATA, BertRev);
+ Length = sizeof (Bed->BertRev);
+ BertRev = CURRENT_BERT_VERSION;
+ FlashEraseCommand ((UINT8 *)Offset, Length);
+ FlashProgramCommand ((UINT8 *)Offset, (UINT8 *)&BertRev, &Length);
+ }
+
+}
+
+/*
+ * Checks Status of NV_SI_RAS_BERT_ENABLED
+ * Returns TRUE if enabled and FALSE if disabled
+ */
+BOOLEAN
+IsBertEnabled (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ Status = NVParamGet (
+ NV_SI_RAS_BERT_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ // BERT is enabled by default
+ return TRUE;
+ }
+
+ return (Value != 0) ? TRUE : FALSE;
+}
+
+/*
+ * Write bert table to DDR
+ */
+VOID
+WriteDDRBertTable (
+ APEI_CRASH_DUMP_BERT_ERROR *Data
+ )
+{
+ VOID *Blk = (VOID *)BERT_DDR_OFFSET;
+
+ /*
+ * writing sizeof data to ddr produces alignment error
+ * this is a temporary workaround
+ */
+ CopyMem (Blk, Data, BERT_DDR_LENGTH);
+}
+
+/*
+ * Update Bert Table
+ */
+EFI_STATUS
+AcpiPopulateBert (
+ VOID
+ )
+{
+ APEI_CRASH_DUMP_BERT_ERROR *DDRError;
+
+ DDRError =
+ (APEI_CRASH_DUMP_BERT_ERROR *)
+ AllocateZeroPool (sizeof (APEI_CRASH_DUMP_BERT_ERROR));
+
+ if (DDRError == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (IsBertEnabled ()) {
+ PullBertSpinorData (&(DDRError->Bed));
+ if ((DDRError->Bed.BertRev == CURRENT_BERT_VERSION)) {
+ WrapBertErrorData (DDRError);
+ WriteDDRBertTable (DDRError);
+ }
+ WriteSpinorDefaultBertTable (&(DDRError->Bed));
+ }
+
+ FreePool (DDRError);
+ return EFI_SUCCESS;
+}
+
+/*
+ * Checks Status of NV_SI_RAS_SDEI_ENABLED
+ * Returns TRUE if enabled and FALSE if disabled or error occurred
+ */
+BOOLEAN
+IsSdeiEnabled (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ Status = NVParamGet (
+ NV_SI_RAS_SDEI_ENABLED,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status)) {
+ // SDEI is disabled by default
+ return FALSE;
+ }
+
+ return (Value != 0) ? TRUE : FALSE;
+}
+
+STATIC
+VOID
+AcpiApeiHestUpdateTable1P (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiTableSdtProtocol;
+ EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestTablePointer;
+ UINTN TableKey;
+ UINTN TableIndex;
+
+ Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&AcpiTableSdtProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "APEI: Unable to locate ACPI table support protocol\n"));
+ return;
+ }
+
+ /*
+ * Search for ACPI Table Signature
+ */
+ TableIndex = 0;
+ Status = AcpiLocateTableBySignature (
+ AcpiTableSdtProtocol,
+ EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE,
+ &TableIndex,
+ (EFI_ACPI_DESCRIPTION_HEADER **)&HestTablePointer,
+ &TableKey
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a:%d Unable to get ACPI HEST table\n", __FUNCTION__, __LINE__));
+ return;
+ }
+
+ HestTablePointer->ErrorSourceCount -= HEST_NUM_ENTRIES_PER_SOC;
+ HestTablePointer->Header.Length -=
+ (HEST_NUM_ENTRIES_PER_SOC *
+ sizeof (EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE));
+
+ AcpiUpdateChecksum ((UINT8 *)HestTablePointer, HestTablePointer->Header.Length);
+}
+
+/*
+ * Update APEI
+ *
+ */
+EFI_STATUS
+EFIAPI
+AcpiApeiUpdate (
+ VOID
+ )
+{
+ if (!IsSlaveSocketActive ()) {
+ AcpiApeiHestUpdateTable1P ();
+ }
+
+ if (!IsSdeiEnabled ()) {
+ AcpiApeiUninstallTable (EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c
new file mode 100644
index 000000000000..3c0a4860e62d
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiDsdt.c
@@ -0,0 +1,601 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Protocol/PciRootBridgeIo.h>
+#include <Library/NVParamLib.h>
+#include <NVParamDef.h>
+
+#include "AcpiNfit.h"
+#include "AcpiPlatform.h"
+
+#define PCIE_DEVICE_CONTROL_OFFSET 0x078
+#define PCIE_DEVICE_CONTROL_UNSUPPORT_REQ_REP_EN 0x08
+#define PCIE_DEVICE_CONTROL_FATAL_ERR_REPORT_EN 0x04
+#define PCIE_DEVICE_CONTROL_NON_FATAL_ERR_REPORT_EN 0x02
+#define PCIE_DEVICE_CONTROL_CORR_ERR_REPORT_EN 0x01
+
+#define PCIE_ROOT_ERR_CMD_OFFSET 0x12C
+#define PCIE_ROOT_ERR_CMD_FATAL_ERR_REPORTING_EN 0x4
+#define PCIE_ROOT_ERR_CMD_NON_FATAL_ERR_REPORTING_EN 0x2
+#define PCIE_ROOT_ERR_CMD_CORR_ERR_REPORTING_EN 0x1
+
+#define PCIE_MAX_DEVICE_PER_ROOT_PORT 8
+
+#pragma pack(1)
+typedef struct {
+ UINT8 DWordPrefix;
+ UINT32 DWordData;
+} OP_REGION_DWORD_DATA;
+
+typedef struct {
+ UINT8 ExtOpPrefix;
+ UINT8 ExtOpCode;
+ UINT8 NameString[4];
+ UINT8 RegionSpace;
+ OP_REGION_DWORD_DATA RegionBase;
+ OP_REGION_DWORD_DATA RegionLen;
+} AML_OP_REGION;
+#pragma pack()
+
+EFI_STATUS
+UpdateStatusMethodObject (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle,
+ CHAR8 *AsciiObjectPath,
+ CHAR8 ReturnValue
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE ObjectHandle;
+ EFI_ACPI_DATA_TYPE DataType;
+ CHAR8 *Buffer;
+ UINTN DataSize;
+
+ Status = AcpiSdtProtocol->FindPath (TableHandle, AsciiObjectPath, &ObjectHandle);
+ if (EFI_ERROR (Status) || ObjectHandle == NULL) {
+ return EFI_SUCCESS;
+ }
+ ASSERT (ObjectHandle != NULL);
+
+ Status = AcpiSdtProtocol->GetOption (ObjectHandle, 2, &DataType, (VOID *)&Buffer, &DataSize);
+ if (!EFI_ERROR (Status) && Buffer[2] == AML_BYTE_PREFIX) {
+ //
+ // Only patch when the initial value is byte object.
+ //
+ Buffer[3] = ReturnValue;
+ }
+
+ AcpiSdtProtocol->Close (ObjectHandle);
+ return Status;
+}
+
+EFI_STATUS
+GetOpRegionBase (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle,
+ CHAR8 *AsciiObjectPath,
+ UINT32 *Value
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE ObjectHandle;
+ EFI_ACPI_DATA_TYPE DataType;
+ CHAR8 *Buffer;
+ UINTN DataSize;
+ AML_OP_REGION *OpRegion;
+
+ Status = AcpiSdtProtocol->FindPath (TableHandle, AsciiObjectPath, &ObjectHandle);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_NOT_FOUND;
+ goto Exit;
+ }
+
+ Status = AcpiSdtProtocol->GetOption (ObjectHandle, 0, &DataType, (VOID *)&Buffer, &DataSize);
+ if (!EFI_ERROR (Status) && Buffer != NULL) {
+ OpRegion = (AML_OP_REGION *)Buffer;
+
+ if (OpRegion->ExtOpCode != AML_EXT_REGION_OP
+ || OpRegion->RegionBase.DWordPrefix != AML_DWORD_PREFIX)
+ {
+ AcpiSdtProtocol->Close (TableHandle);
+ Status = EFI_NOT_FOUND;
+ goto Exit;
+ }
+
+ *Value = OpRegion->RegionBase.DWordData;
+ }
+
+Exit:
+ AcpiSdtProtocol->Close (ObjectHandle);
+ return Status;
+}
+
+EFI_STATUS
+SetOpRegionBase (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle,
+ CHAR8 *AsciiObjectPath,
+ UINT32 Value
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_HANDLE ObjectHandle;
+ EFI_ACPI_DATA_TYPE DataType;
+ CHAR8 *Buffer;
+ UINTN DataSize;
+ AML_OP_REGION *OpRegion;
+
+ Status = AcpiSdtProtocol->FindPath (TableHandle, AsciiObjectPath, &ObjectHandle);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_NOT_FOUND;
+ goto Exit;
+ }
+
+ Status = AcpiSdtProtocol->GetOption (ObjectHandle, 0, &DataType, (VOID *)&Buffer, &DataSize);
+ if (!EFI_ERROR (Status) && Buffer != NULL) {
+ OpRegion = (AML_OP_REGION *)Buffer;
+
+ if (OpRegion->ExtOpCode != AML_EXT_REGION_OP
+ || OpRegion->RegionBase.DWordPrefix != AML_DWORD_PREFIX)
+ {
+ AcpiSdtProtocol->Close (TableHandle);
+ Status = EFI_NOT_FOUND;
+ goto Exit;
+ }
+
+ OpRegion->RegionBase.DWordData = Value;
+ }
+
+Exit:
+ AcpiSdtProtocol->Close (ObjectHandle);
+ return Status;
+}
+
+STATIC VOID
+AcpiPatchCmn600 (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINTN Index;
+
+ for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.CMN%1X._STA", Index);
+ if (GetNumberOfActiveCPMsPerSocket (Index) > 0) {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0xF);
+ } else {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+}
+
+STATIC VOID
+AcpiPatchDmc620 (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINTN Index, Index1;
+ PLATFORM_INFO_HOB *PlatformHob;
+ UINT32 McuMask;
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) {
+ McuMask = PlatformHob->DramInfo.McuMask[Index];
+ for (Index1 = 0; Index1 < sizeof (McuMask) * 8; Index1++) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.MC%1X%1X._STA", Index, Index1);
+ if (McuMask & (0x1 << Index1)) {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0xF);
+ } else {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+ }
+}
+
+STATIC VOID
+AcpiPatchNvdimm (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINTN NvdRegionNumSK0, NvdRegionNumSK1, NvdRegionNum, Count;
+ PLATFORM_INFO_HOB *PlatformHob;
+ VOID *Hob;
+ UINT32 OpRegionBase;;
+ EFI_STATUS Status;
+
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ NvdRegionNumSK0 = 0;
+ NvdRegionNumSK1 = 0;
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ if (PlatformHob->DramInfo.NvdRegion[Count] > 0) {
+ if (PlatformHob->DramInfo.Socket[Count] == 0) {
+ NvdRegionNumSK0++;
+ } else {
+ NvdRegionNumSK1++;
+ }
+ }
+ }
+ NvdRegionNum = NvdRegionNumSK0 + NvdRegionNumSK1;
+
+ /* Disable NVDIMM Root Device */
+ if (NvdRegionNum == 0) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ /* Update NVDIMM Device _STA for SK0 */
+ if (NvdRegionNumSK0 == 0) {
+ /* Disable NVD1/2 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD1._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD2._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ } else if (NvdRegionNumSK0 == 1) {
+ if (PlatformHob->DramInfo.NvdimmMode[NVDIMM_SK0] == NVDIMM_NON_HASHED) {
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ if (PlatformHob->DramInfo.NvdRegion[Count] > 0 &&
+ PlatformHob->DramInfo.Socket[Count] == 0)
+ {
+ if (PlatformHob->DramInfo.Base[Count] ==
+ PLATFORM_NVDIMM_SK0_NHASHED_REGION0)
+ {
+ /* Disable NVD2 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD2._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ } else if (PlatformHob->DramInfo.Base[Count] ==
+ PLATFORM_NVDIMM_SK0_NHASHED_REGION1)
+ {
+ /* Disable NVD1 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD1._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+ }
+ }
+ }
+ /* Update NVDIMM Device _STA and OpRegions for SK1 */
+ if (NvdRegionNumSK1 == 0) {
+ /* Use NVD1 OpRegion base for NVD3 */
+ OpRegionBase = 0;
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD1.BUF1");
+ Status = GetOpRegionBase (AcpiSdtProtocol, TableHandle, NodePath, &OpRegionBase);
+ ASSERT ((!EFI_ERROR (Status)) && (OpRegionBase != 0));
+
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD3.BUF1");
+ Status = SetOpRegionBase (AcpiSdtProtocol, TableHandle, NodePath, OpRegionBase);
+
+ /* Use NVD2 OpRegion base for NVD4 */
+ OpRegionBase = 0;
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD2.BUF1");
+ Status = GetOpRegionBase (AcpiSdtProtocol, TableHandle, NodePath, &OpRegionBase);
+ ASSERT ((!EFI_ERROR (Status)) && (OpRegionBase != 0));
+
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD4.BUF1");
+ Status = SetOpRegionBase (AcpiSdtProtocol, TableHandle, NodePath, OpRegionBase);
+
+ /* Disable NVD3/4 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD3._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD4._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ } else if (NvdRegionNumSK1 == 1) {
+ if (PlatformHob->DramInfo.NvdimmMode[NVDIMM_SK1] == NVDIMM_NON_HASHED) {
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ if (PlatformHob->DramInfo.NvdRegion[Count] > 0 &&
+ PlatformHob->DramInfo.Socket[Count] == 1)
+ {
+ if (PlatformHob->DramInfo.Base[Count] ==
+ PLATFORM_NVDIMM_SK1_NHASHED_REGION0)
+ {
+ /* Disable NVD4 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD4._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ } else if (PlatformHob->DramInfo.Base[Count] ==
+ PLATFORM_NVDIMM_SK1_NHASHED_REGION1)
+ {
+ /* Disable NVD3 */
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.NVDR.NVD3._STA");
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+ }
+ }
+ }
+}
+
+STATIC VOID
+AcpiPatchHwmon (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINT8 Index;
+
+ // PCC Hardware Monitor Devices
+ for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.HM0%1X._STA", Index);
+ if (GetNumberOfActiveCPMsPerSocket (Index) > 0) {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0xF);
+ } else {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+
+ // Ampere Altra SoC Hardware Monitor Devices
+ for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.HM0%1X._STA", Index + 2);
+ if (GetNumberOfActiveCPMsPerSocket (Index) > 0) {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0xF);
+ } else {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+}
+
+STATIC VOID
+AcpiPatchDsu (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINTN Index;
+
+ for (Index = 0; Index < PLATFORM_CPU_MAX_NUM_CORES; Index += PLATFORM_CPU_NUM_CORES_PER_CPM) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.DU%2X._STA", Index / PLATFORM_CPU_NUM_CORES_PER_CPM);
+ if (IsCpuEnabled (Index)) {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0xF);
+ } else {
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, 0x0);
+ }
+ }
+}
+
+VOID
+AcpiPatchPcieNuma (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ CHAR8 NodePath[256];
+ UINTN Index;
+ UINTN NumaIdx;
+ UINTN NumPciePort;
+ UINTN NumaAssignment[3][16] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, // Monolithic Node 0 (S0)
+ 1, 1, 1, 1, 1, 1, 1, 1 }, // Monolithic Node 1 (S1)
+ { 0, 1, 0, 1, 0, 0, 1, 1, // Hemisphere Node 0, 1 (S0)
+ 2, 3, 2, 3, 2, 2, 3, 3 }, // Hemisphere Node 2, 3 (S1)
+ { 0, 2, 1, 3, 1, 1, 3, 3, // Quadrant Node 0, 1, 2, 3 (S0)
+ 4, 6, 5, 7, 5, 5, 7, 7 }, // Quadrant Node 4, 5, 6, 7 (S1)
+ };
+
+ switch (CpuGetSubNumaMode ()) {
+ case SUBNUMA_MODE_MONOLITHIC:
+ NumaIdx = 0;
+ break;
+
+ case SUBNUMA_MODE_HEMISPHERE:
+ NumaIdx = 1;
+ break;
+
+ case SUBNUMA_MODE_QUADRANT:
+ NumaIdx = 2;
+ break;
+
+ default:
+ NumaIdx = 0;
+ break;
+ }
+
+ if (IsSlaveSocketActive ()) {
+ NumPciePort = 16; // 16 ports total (8 per socket)
+ } else {
+ NumPciePort = 8; // 8 ports total
+ }
+
+ for (Index = 0; Index < NumPciePort; Index++) {
+ AsciiSPrint (NodePath, sizeof (NodePath), "\\_SB.PCI%X._PXM", Index);
+ UpdateStatusMethodObject (AcpiSdtProtocol, TableHandle, NodePath, NumaAssignment[NumaIdx][Index]);
+ }
+}
+
+EFI_STATUS
+AcpiPatchPcieAerFwFirst (
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol,
+ EFI_ACPI_HANDLE TableHandle
+ )
+{
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS Address;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ CHAR8 ObjectPath[8];
+ EFI_STATUS Status;
+ UINT32 AerFwFirstConfigValue;
+ UINT32 RegData;
+ UINT16 Device;
+ UINT32 Index;
+
+ //
+ // Check if PCIe AER Firmware First should be enabled
+ //
+ Status = NVParamGet (
+ NV_SI_RAS_PCIE_AER_FW_FIRST,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &AerFwFirstConfigValue
+ );
+ if (EFI_ERROR (Status)) {
+ Status = NVParamGet (
+ NV_SI_RO_BOARD_PCIE_AER_FW_FIRST,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &AerFwFirstConfigValue
+ );
+ if (EFI_ERROR (Status)) {
+ AerFwFirstConfigValue = 0;
+ }
+ }
+
+ if (AerFwFirstConfigValue == 0) {
+ //
+ // By default, the PCIe AER FW-First (ACPI Object "AERF") is set to 0
+ // in the DSDT table.
+ //
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Update Name Object "AERF" (PCIe AER Firmware-First) to enable PCIe AER Firmware-First
+ //
+ AsciiSPrint (ObjectPath, sizeof (ObjectPath), "\\AERF");
+ Status = AcpiAmlObjectUpdateInteger (AcpiSdtProtocol, TableHandle, ObjectPath, 1);
+
+ //
+ // For PCIe AER Firmware First, PCIe capability registers need
+ // to be updated to allow Firmware to detect AER errors.
+ //
+
+ HandleCount = 0;
+ HandleBuffer = NULL;
+ PciRootBridgeIo = NULL;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Loop through each root complex
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciRootBridgeIoProtocolGuid,
+ (VOID **)&PciRootBridgeIo
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Loop through each root port
+ //
+ for (Device = 1; Device <= PCIE_MAX_DEVICE_PER_ROOT_PORT; Device++) {
+ Address.Bus = 0;
+ Address.Device = Device;
+ Address.Function = 0;
+ Address.Register = 0;
+
+ Address.ExtendedRegister = PCIE_DEVICE_CONTROL_OFFSET;
+ PciRootBridgeIo->Pci.Read (PciRootBridgeIo, EfiPciWidthUint32, *((UINT64 *)&Address), 1, &RegData);
+
+ if (RegData == 0xFFFFFFFF) {
+ continue;
+ }
+
+ RegData |= PCIE_DEVICE_CONTROL_UNSUPPORT_REQ_REP_EN
+ | PCIE_DEVICE_CONTROL_FATAL_ERR_REPORT_EN
+ | PCIE_DEVICE_CONTROL_NON_FATAL_ERR_REPORT_EN
+ | PCIE_DEVICE_CONTROL_CORR_ERR_REPORT_EN;
+
+ PciRootBridgeIo->Pci.Write (PciRootBridgeIo, EfiPciWidthUint32, *((UINT64 *)&Address), 1, &RegData);
+
+ RegData = 0;
+ Address.ExtendedRegister = PCIE_ROOT_ERR_CMD_OFFSET;
+ PciRootBridgeIo->Pci.Read (PciRootBridgeIo, EfiPciWidthUint32, *((UINT64 *)&Address), 1, &RegData);
+
+ RegData |= PCIE_ROOT_ERR_CMD_FATAL_ERR_REPORTING_EN
+ | PCIE_ROOT_ERR_CMD_NON_FATAL_ERR_REPORTING_EN
+ | PCIE_ROOT_ERR_CMD_CORR_ERR_REPORTING_EN;
+
+ PciRootBridgeIo->Pci.Write (PciRootBridgeIo, EfiPciWidthUint32, *((UINT64 *)&Address), 1, &RegData);
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+AcpiPatchDsdtTable (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
+ EFI_ACPI_DESCRIPTION_HEADER *Table;
+ UINTN TableKey;
+ UINTN TableIndex;
+ EFI_ACPI_HANDLE TableHandle;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiSdtProtocolGuid,
+ NULL,
+ (VOID **)&AcpiSdtProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to locate ACPI table protocol\n"));
+ return Status;
+ }
+
+ TableIndex = 0;
+ Status = AcpiLocateTableBySignature (
+ AcpiSdtProtocol,
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ &TableIndex,
+ &Table,
+ &TableKey
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "ACPI DSDT table not found!\n"));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ Status = AcpiSdtProtocol->OpenSdt (TableKey, &TableHandle);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ AcpiSdtProtocol->Close (TableHandle);
+ return Status;
+ }
+
+ AcpiPatchCmn600 (AcpiSdtProtocol, TableHandle);
+ AcpiPatchDmc620 (AcpiSdtProtocol, TableHandle);
+ AcpiPatchDsu (AcpiSdtProtocol, TableHandle);
+ AcpiPatchHwmon (AcpiSdtProtocol, TableHandle);
+ AcpiPatchNvdimm (AcpiSdtProtocol, TableHandle);
+ AcpiPatchPcieNuma (AcpiSdtProtocol, TableHandle);
+ AcpiPatchPcieAerFwFirst (AcpiSdtProtocol, TableHandle);
+
+ AcpiSdtProtocol->Close (TableHandle);
+ AcpiUpdateChecksum ((UINT8 *)Table, Table->Length);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
new file mode 100644
index 000000000000..1dea9ba2f2bc
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c
@@ -0,0 +1,348 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiPlatform.h"
+
+EFI_ACPI_6_3_GIC_ITS_STRUCTURE GicItsTemplate = {
+ EFI_ACPI_6_3_GIC_ITS,
+ sizeof (EFI_ACPI_6_3_GIC_ITS_STRUCTURE),
+ EFI_ACPI_RESERVED_WORD,
+ 0, /* GicItsId */
+ 0, /* PhysicalBaseAddress */
+ 0, /* Reserved2 */
+};
+
+EFI_ACPI_6_3_GICR_STRUCTURE GicRTemplate = {
+ EFI_ACPI_6_3_GICR,
+ sizeof (EFI_ACPI_6_3_GICR_STRUCTURE),
+ EFI_ACPI_RESERVED_WORD,
+ GICR_MASTER_BASE_REG, /* DiscoveryRangeBaseAddress */
+ 0x1000000, /* DiscoveryRangeLength */
+};
+
+EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE GicDTemplate = {
+ EFI_ACPI_6_3_GICD,
+ sizeof (EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE),
+ EFI_ACPI_RESERVED_WORD,
+ 0, /* GicDistHwId */
+ GICD_BASE_REG, /* GicDistBase */
+ 0, /* GicDistVector */
+ 0x3, /* GicVersion */
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}
+};
+
+EFI_ACPI_6_3_GIC_STRUCTURE GiccTemplate = {
+ EFI_ACPI_6_3_GIC,
+ sizeof (EFI_ACPI_6_3_GIC_STRUCTURE),
+ EFI_ACPI_RESERVED_WORD,
+ 0, /* GicId */
+ 0, /* AcpiCpuUid */
+ 0, /* Flags */
+ 0,
+ 23, /* PmuIrq */
+ 0,
+ 0,
+ 0,
+ 0,
+ 25, /* GsivId */
+ 0, /* GicRBase */
+ 0, /* Mpidr */
+ 0, /* ProcessorPowerEfficiencyClass */
+ 0, /* Reserved2 */
+ 21, /* SPE irq */
+};
+
+EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER MADTTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+};
+
+UINT32 Ac01CoreOrderMonolithic[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 36, 52, 40, 56, 32, 48, 44, 60,
+ 20, 68, 24, 72, 16, 64, 28, 76,
+ 4, 8, 0, 12, 38, 54, 42, 58,
+ 34, 50, 46, 62, 22, 70, 26, 74,
+ 18, 66, 30, 78, 6, 10, 2, 14,
+ 37, 53, 41, 57, 33, 49, 45, 61,
+ 21, 69, 25, 73, 17, 65, 29, 77,
+ 5, 9, 1, 13, 39, 55, 43, 59,
+ 35, 51, 47, 63, 23, 71, 27, 75,
+ 19, 67, 31, 79, 7, 11, 3, 15,
+};
+
+UINT32 Ac01CoreOrderHemisphere[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 32, 48, 16, 64, 36, 52, 0, 20,
+ 68, 4, 34, 50, 18, 66, 38, 54,
+ 2, 22, 70, 6, 33, 49, 17, 65,
+ 37, 53, 1, 21, 69, 5, 35, 51,
+ 19, 67, 39, 55, 3, 23, 71, 7,
+ 44, 60, 28, 76, 40, 56, 12, 24,
+ 72, 8, 46, 62, 30, 78, 42, 58,
+ 14, 26, 74, 10, 45, 61, 29, 77,
+ 41, 57, 13, 25, 73, 9, 47, 63,
+ 31, 79, 43, 59, 15, 27, 75, 11,
+};
+
+UINT32 Ac01CoreOrderQuadrant[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 16, 32, 0, 20, 4, 18, 34, 2,
+ 22, 6, 17, 33, 1, 21, 5, 19,
+ 35, 3, 23, 7, 48, 64, 52, 68,
+ 36, 50, 66, 54, 70, 38, 49, 65,
+ 53, 69, 37, 51, 67, 55, 71, 39,
+ 28, 44, 12, 24, 8, 30, 46, 14,
+ 26, 10, 29, 45, 13, 25, 9, 31,
+ 47, 15, 27, 11, 60, 76, 56, 72,
+ 40, 62, 78, 58, 74, 42, 61, 77,
+ 57, 73, 41, 63, 79, 59, 75, 43,
+};
+
+EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtTablePointer;
+
+UINT32 *
+CpuGetCoreOrder (
+ VOID
+ )
+{
+ UINT8 SubNumaMode;
+
+ SubNumaMode = CpuGetSubNumaMode ();
+ switch (SubNumaMode) {
+ case SUBNUMA_MODE_MONOLITHIC:
+ return (UINT32 *)&Ac01CoreOrderMonolithic;
+
+ case SUBNUMA_MODE_HEMISPHERE:
+ return (UINT32 *)&Ac01CoreOrderHemisphere;
+
+ case SUBNUMA_MODE_QUADRANT:
+ return (UINT32 *)&Ac01CoreOrderQuadrant;
+
+ default:
+ // Should never reach here
+ ASSERT (FALSE);
+ return NULL;
+ }
+
+ return NULL;
+}
+
+UINT32
+AcpiInstallMadtProcessorNode (
+ VOID *EntryPointer,
+ UINT32 CpuId
+ )
+{
+ EFI_ACPI_6_3_GIC_STRUCTURE *MadtProcessorEntryPointer = EntryPointer;
+ UINT32 SocketId;
+ UINT32 ClusterId;
+ UINTN Size;
+
+ Size = sizeof (GiccTemplate);
+ CopyMem (MadtProcessorEntryPointer, &GiccTemplate, Size);
+
+ SocketId = SOCKET_ID (CpuId);
+ ClusterId = CLUSTER_ID (CpuId);
+
+ //
+ // GICv2 compatibility mode is not supported.
+ // Hence, set GIC's CPU Interface Number to 0.
+ //
+ MadtProcessorEntryPointer->CPUInterfaceNumber = 0;
+ MadtProcessorEntryPointer->AcpiProcessorUid =
+ (SocketId << PLATFORM_SOCKET_UID_BIT_OFFSET) +
+ (ClusterId << 8) + (CpuId % PLATFORM_CPU_NUM_CORES_PER_CPM);
+ MadtProcessorEntryPointer->Flags = 1;
+ MadtProcessorEntryPointer->MPIDR =
+ (((ClusterId << 8) + (CpuId % PLATFORM_CPU_NUM_CORES_PER_CPM)) << 8);
+ MadtProcessorEntryPointer->MPIDR += (((UINT64)SocketId) << 32);
+
+ return Size;
+}
+
+UINT32
+AcpiInstallMadtGicD (
+ VOID *EntryPointer
+ )
+{
+ EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE *GicDEntryPointer = EntryPointer;
+ UINTN Size;
+
+ Size = sizeof (GicDTemplate);
+ CopyMem (GicDEntryPointer, &GicDTemplate, Size);
+
+ return Size;
+}
+
+UINT32
+AcpiInstallMadtGicR (
+ VOID *EntryPointer,
+ UINT32 SocketId
+ )
+{
+ EFI_ACPI_6_3_GICR_STRUCTURE *GicREntryPointer = EntryPointer;
+ UINTN Size;
+
+ /*
+ * If the Slave socket is not present, discard the Slave socket
+ * GIC redistributor region
+ */
+ if (SocketId == 1 && !IsSlaveSocketActive ()) {
+ return 0;
+ }
+
+ Size = sizeof (GicRTemplate);
+ CopyMem (GicREntryPointer, &GicRTemplate, Size);
+
+ if (SocketId == 1) {
+ GicREntryPointer->DiscoveryRangeBaseAddress = GICR_SLAVE_BASE_REG;
+ }
+
+ return Size;
+}
+
+UINT32
+AcpiInstallMadtGicIts (
+ VOID *EntryPointer,
+ UINT32 Index
+ )
+{
+ EFI_ACPI_6_3_GIC_ITS_STRUCTURE *GicItsEntryPointer = EntryPointer;
+ UINTN Size, Offset;
+ UINT64 GicBase = GICD_BASE_REG;
+ UINT32 ItsId = Index;
+
+ if (Index > SOCKET0_LAST_RC) { /* Socket 1, Index: 8-15 */
+ GicBase = GICD_SLAVE_BASE_REG;
+ Index -= (SOCKET0_LAST_RC + 1); /* Socket 1, Index:8 -> RCA0 */
+ }
+ Size = sizeof (GicItsTemplate);
+ CopyMem (GicItsEntryPointer, &GicItsTemplate, Size);
+ Offset = 0x40000 + Index * 0x20000;
+ GicItsEntryPointer->GicItsId = ItsId;
+ GicItsEntryPointer->PhysicalBaseAddress = Offset + GicBase;
+
+ return Size;
+}
+
+/*
+ * Install MADT table.
+ */
+EFI_STATUS
+AcpiInstallMadtTable (
+ VOID
+ )
+{
+ EFI_ACPI_6_3_GIC_STRUCTURE *GiccEntryPointer = NULL;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ UINTN MadtTableKey = 0;
+ INTN Index;
+ EFI_STATUS Status;
+ UINTN Size;
+ UINT32 *CoreOrder;
+ UINT32 SktMaxCoreNum;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Size = sizeof (MADTTableHeaderTemplate) +
+ (PLATFORM_CPU_MAX_NUM_CORES * sizeof (GiccTemplate)) +
+ sizeof (GicDTemplate) +
+ (PLATFORM_CPU_MAX_SOCKET * sizeof (GicRTemplate)) +
+ ((SOCKET0_LAST_RC - SOCKET0_FIRST_RC + 1) * sizeof (GicItsTemplate));
+ if (IsSlaveSocketActive ()) {
+ Size += ((SOCKET1_LAST_RC - SOCKET1_FIRST_RC + 1) * sizeof (GicItsTemplate));
+ } else if (!IsSlaveSocketPresent ()) {
+ Size += 2 * sizeof (GicItsTemplate); /* RCA0/1 */
+ }
+
+ MadtTablePointer =
+ (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (MadtTablePointer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ GiccEntryPointer =
+ (EFI_ACPI_6_3_GIC_STRUCTURE *)((UINT64)MadtTablePointer +
+ sizeof (MADTTableHeaderTemplate));
+
+ /* Install Gic interface for each processor */
+ Size = 0;
+ CoreOrder = CpuGetCoreOrder ();
+ ASSERT (CoreOrder != NULL);
+ SktMaxCoreNum = PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM;
+ for (Index = 0; Index < SktMaxCoreNum; Index++) {
+ if (IsCpuEnabled (CoreOrder[Index])) {
+ Size += AcpiInstallMadtProcessorNode ((VOID *)((UINT64)GiccEntryPointer + Size), CoreOrder[Index]);
+ }
+ }
+
+ for (Index = 0; Index < SktMaxCoreNum; Index++) {
+ if (IsCpuEnabled (CoreOrder[Index] + SktMaxCoreNum)) {
+ Size += AcpiInstallMadtProcessorNode ((VOID *)((UINT64)GiccEntryPointer + Size), CoreOrder[Index] + SktMaxCoreNum);
+ }
+ }
+
+ /* Install Gic Distributor */
+ Size += AcpiInstallMadtGicD ((VOID *)((UINT64)GiccEntryPointer + Size));
+
+ /* Install Gic Redistributor */
+ for (Index = 0; Index < PLATFORM_CPU_MAX_SOCKET; Index++) {
+ Size += AcpiInstallMadtGicR ((VOID *)((UINT64)GiccEntryPointer + Size), Index);
+ }
+
+ /* Install Gic ITS */
+ if (!IsSlaveSocketPresent ()) {
+ for (Index = 0; Index <= 1; Index++) { /* RCA0/1 */
+ Size += AcpiInstallMadtGicIts ((VOID *)((UINT64)GiccEntryPointer + Size), Index);
+ }
+ }
+ for (Index = SOCKET0_FIRST_RC; Index <= SOCKET0_LAST_RC; Index++) {
+ Size += AcpiInstallMadtGicIts ((VOID *)((UINT64)GiccEntryPointer + Size), Index);
+ }
+ if (IsSlaveSocketActive ()) {
+ for (Index = SOCKET1_FIRST_RC; Index <= SOCKET1_LAST_RC; Index++) {
+ Size += AcpiInstallMadtGicIts ((VOID *)((UINT64)GiccEntryPointer + Size), Index);
+ }
+ }
+ CopyMem (
+ MadtTablePointer,
+ &MADTTableHeaderTemplate,
+ sizeof (MADTTableHeaderTemplate)
+ );
+
+ Size += sizeof (MADTTableHeaderTemplate);
+ MadtTablePointer->Header.Length = Size;
+ CopyMem (
+ MadtTablePointer->Header.OemId,
+ PcdGetPtr (PcdAcpiDefaultOemId),
+ sizeof (MadtTablePointer->Header.OemId)
+ );
+
+ AcpiUpdateChecksum ((UINT8 *)MadtTablePointer, MadtTablePointer->Header.Length);
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)MadtTablePointer,
+ MadtTablePointer->Header.Length,
+ &MadtTableKey
+ );
+ FreePool ((VOID *)MadtTablePointer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.c
new file mode 100644
index 000000000000..fe59c47932d1
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiNfit.c
@@ -0,0 +1,596 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiNfit.h"
+#include "AcpiPlatform.h"
+
+EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE NfitSPATemplate = {
+ EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE,
+ sizeof (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE),
+ 0, // The uniue index - need to be filled.
+ 0, // The flags - need to be filled.
+ 0, // Reserved.
+ 0, // Proximity domain - need to be filled.
+ EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION, // PM range type.
+ 0, // Start address - need to be filled.
+ 0, // Size - need to be filled.
+ EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB |
+ EFI_MEMORY_WP | EFI_MEMORY_UCE, // attribute - need to be filled.
+};
+
+EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE NvdimmControlRegionTemplate = {
+ EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE,
+ sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE),
+ 0, // The unique index - need to be filled.
+ 0, // The vendor id - need to be filled.
+ 0, // The device id - need to be filled.
+ 0, // The revision - need to be filled.
+ 0, // The subsystem nvdimm id - need to be filled.
+ 0, // The subsystem nvdimm device id - need to be filled.
+ 0, // The subsystem revision - need to be filled.
+ 0, // The valid field.
+ 0, // The manufacturing location - not valid.
+ 0, // The manufacturing date - not valid.
+ {0}, // Reserved.
+ 0, // The serial number - need to be filled.
+ 0, // The region format interface code - dummy value.
+ 0, // The number of block control windows.
+ 0, // The size of block control windows.
+ 0, // The Command Register Offset in Block Control Window.
+ 0, // The Size of Command Register in Block Control Windows.
+ 0, // The Status Register Offset in Block Control Window.
+ 0, // Size of Status Register in Block Control Windows.
+ 0, // The NVDIMM Control Region Flag.
+ {0}, // Reserved.
+};
+
+EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE NvdimmRegionMappingTemplate = {
+ EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE,
+ sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE),
+ {0}, // _ADR of the NVDIMM device - need to be filled.
+ 0, // Dimm smbios handle index - need to be filled.
+ 0, // The unique region index - need to be filled.
+ 0, // The SPA range index - need to be filled.
+ 0, // The control region index - need to be filled.
+ 0, // The region size - need to be filled.
+ 0, // The region offset - need to be filled.
+ 0, // The region base - need to be filled.
+ 0, // The interleave structure index - need to be filled.
+ 0, // The interleave ways - need to be filled.
+ 0, // NVDIMM flags - need to be filled.
+ 0, // Reserved.
+};
+
+EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE NFITTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION
+ ),
+ 0x00000000, // Reserved
+};
+
+NVDIMM_DATA NvdData[PLATFORM_CPU_MAX_SOCKET] = { { 0 } };
+
+EFI_STATUS
+AcpiNvdInfoInit (
+ IN OUT NVDIMM_INFO *NvdInfoPtr,
+ IN UINTN NvdId
+ )
+{
+ PLATFORM_INFO_HOB *PlatformHob;
+ VOID *Hob;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL || NvdInfoPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ NvdInfoPtr->Enabled = TRUE;
+ NvdInfoPtr->PhysId = NvdId;
+ NvdInfoPtr->NvdSize = PlatformHob->DimmList.Dimm[NvdId].Info.DimmSize * ONE_GB;
+ NvdInfoPtr->VendorId =
+ *((UINT16 *)&PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[320]);
+ NvdInfoPtr->DeviceId =
+ *((UINT16 *)&PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[192]);
+ NvdInfoPtr->RevisionId =
+ (UINT16)PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[349];
+ NvdInfoPtr->SubVendorId =
+ *((UINT16 *)&PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[194]);
+ NvdInfoPtr->SubDeviceId =
+ *((UINT16 *)&PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[196]);
+ NvdInfoPtr->SubRevisionId =
+ (UINT16)PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[198];
+ NvdInfoPtr->SerialNumber =
+ *((UINT32 *)&PlatformHob->DimmList.Dimm[NvdId].SpdData.Data[325]);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+AcpiNvdDataInit (
+ IN UINTN Socket
+ )
+{
+ PLATFORM_INFO_HOB *PlatformHob;
+ NVDIMM_INFO *NvdInfo;
+ UINTN Count;
+ VOID *Hob;
+ UINTN NvdRegionNum, RegionId;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ NvdRegionNum = 0;
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ if (PlatformHob->DramInfo.NvdRegion[Count] != 0
+ && (PlatformHob->DramInfo.Socket[Count] == Socket))
+ {
+ NvdData[Socket].NvdRegionId[NvdRegionNum] = Count;
+ NvdRegionNum++;
+ }
+ }
+ if (NvdRegionNum == 0) {
+ return EFI_SUCCESS;
+ }
+
+ NvdData[Socket].NvdRegionNum = NvdRegionNum;
+ NvdData[Socket].NvdMode = PlatformHob->DramInfo.NvdimmMode[Socket];
+ if (NvdData[Socket].NvdMode == NVDIMM_HASHED) {
+ NvdInfo = &NvdData[Socket].NvdInfo[NVDIMM_SK0];
+ NvdInfo->DeviceHandle =
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD1_DEVICE_HANDLE :
+ PLATFORM_NVDIMM_NVD3_DEVICE_HANDLE;
+ NvdInfo->InterleaveWays = PLATFORM_NVDIMM_HASHED_INTERLEAVE_WAYS;
+ NvdInfo->RegionOffset = 0;
+ AcpiNvdInfoInit (
+ NvdInfo,
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD1_DIMM_ID :
+ PLATFORM_NVDIMM_NVD3_DIMM_ID
+ );
+
+ NvdInfo = &NvdData[Socket].NvdInfo[1];
+ NvdInfo->DeviceHandle =
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD2_DEVICE_HANDLE :
+ PLATFORM_NVDIMM_NVD4_DEVICE_HANDLE;
+ NvdInfo->InterleaveWays = PLATFORM_NVDIMM_HASHED_INTERLEAVE_WAYS;
+ NvdInfo->RegionOffset = PLATFORM_NVDIMM_HASHED_REGION_OFFSET;
+ AcpiNvdInfoInit (
+ NvdInfo,
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD2_DIMM_ID :
+ PLATFORM_NVDIMM_NVD4_DIMM_ID
+ );
+
+ /* Update NvdNum */
+ NvdData[Socket].NvdNum = 0;
+ for (Count = 0; Count < NVDIMM_NUM_PER_SK; Count++) {
+ if (NvdData[Socket].NvdInfo[Count].Enabled) {
+ NvdData[Socket].NvdNum++;
+ }
+ }
+ return EFI_SUCCESS;
+ }
+ /* NVDIMM_NON_HASHED */
+ NvdData[Socket].NvdNum = 0;
+ for (Count = 0; Count < NvdData[Socket].NvdRegionNum; Count++) {
+ RegionId = NvdData[Socket].NvdRegionId[Count];
+ if (PlatformHob->DramInfo.Base[RegionId] ==
+ PLATFORM_NVDIMM_SK0_NHASHED_REGION0 ||
+ PlatformHob->DramInfo.Base[RegionId] ==
+ PLATFORM_NVDIMM_SK1_NHASHED_REGION0)
+ {
+ NvdInfo = &NvdData[Socket].NvdInfo[0];
+ NvdInfo->DeviceHandle =
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD1_DEVICE_HANDLE :
+ PLATFORM_NVDIMM_NVD3_DEVICE_HANDLE;
+ NvdInfo->InterleaveWays = PLATFORM_NVDIMM_NHASHED_INTERLEAVE_WAYS;
+ NvdInfo->RegionOffset = 0;
+ AcpiNvdInfoInit (
+ NvdInfo,
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD1_DIMM_ID :
+ PLATFORM_NVDIMM_NVD3_DIMM_ID
+ );
+
+ } else if (PlatformHob->DramInfo.Base[RegionId] ==
+ PLATFORM_NVDIMM_SK0_NHASHED_REGION1 ||
+ PlatformHob->DramInfo.Base[RegionId] ==
+ PLATFORM_NVDIMM_SK1_NHASHED_REGION1)
+ {
+ NvdInfo = &NvdData[Socket].NvdInfo[1];
+ NvdInfo->DeviceHandle =
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD2_DEVICE_HANDLE :
+ PLATFORM_NVDIMM_NVD4_DEVICE_HANDLE;
+ NvdInfo->InterleaveWays = PLATFORM_NVDIMM_NHASHED_INTERLEAVE_WAYS;
+ NvdInfo->RegionOffset = 0;
+ AcpiNvdInfoInit (
+ NvdInfo,
+ (Socket == 0) ? PLATFORM_NVDIMM_NVD2_DIMM_ID :
+ PLATFORM_NVDIMM_NVD4_DIMM_ID
+ );
+ }
+ }
+ /* Update NvdNum */
+ NvdData[Socket].NvdNum = 0;
+ for (Count = 0; Count < NVDIMM_NUM_PER_SK; Count++) {
+ if (NvdData[Socket].NvdInfo[Count].Enabled) {
+ NvdData[Socket].NvdNum++;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/*
+ * Fill in SPA structure
+ */
+VOID
+AcpiNfitFillSPA (
+ IN OUT EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *NfitSpaPointer,
+ IN UINTN NvdRegionIndex,
+ IN UINT64 NvdRegionBase,
+ IN UINT64 NvdRegionSize
+ )
+{
+ ASSERT (NfitSpaPointer != NULL);
+
+ NfitSpaPointer->Flags = 0;
+ NfitSpaPointer->SPARangeStructureIndex = NvdRegionIndex;
+ NfitSpaPointer->SystemPhysicalAddressRangeBase = NvdRegionBase;
+ NfitSpaPointer->SystemPhysicalAddressRangeLength = NvdRegionSize;
+}
+
+VOID
+NfitFillControlRegion (
+ IN OUT EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *NfitControlRegionPointer,
+ IN NVDIMM_INFO *NvdInfo,
+ IN UINTN NvdControlRegionIndex
+ )
+{
+ ASSERT (
+ NfitControlRegionPointer != NULL
+ && NvdInfo != NULL
+ );
+
+ NfitControlRegionPointer->NVDIMMControlRegionStructureIndex =
+ NvdControlRegionIndex;
+ NfitControlRegionPointer->VendorID = NvdInfo->VendorId;
+ NfitControlRegionPointer->DeviceID = NvdInfo->DeviceId;
+ NfitControlRegionPointer->RevisionID = NvdInfo->RevisionId;
+ NfitControlRegionPointer->SubsystemVendorID = NvdInfo->SubVendorId;
+ NfitControlRegionPointer->SubsystemDeviceID = NvdInfo->SubDeviceId;
+ NfitControlRegionPointer->SubsystemRevisionID = NvdInfo->SubRevisionId;
+ NfitControlRegionPointer->SerialNumber = NvdInfo->SerialNumber;
+}
+
+VOID
+NfitFillRegionMapping (
+ IN OUT EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE *NfitRegionMappingPointer,
+ IN EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *NfitControlRegionPointer,
+ IN EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *NfitSpaPointer,
+ IN NVDIMM_INFO *NvdInfo,
+ IN UINTN NvdRegionID
+ )
+{
+ ASSERT (
+ NfitRegionMappingPointer != NULL
+ && NfitRegionMappingPointer != NULL
+ && NfitRegionMappingPointer != NULL
+ && NfitRegionMappingPointer != NULL
+ && NvdInfo != NULL
+ );
+
+ NfitRegionMappingPointer->NVDIMMRegionID = NvdRegionID;
+ NfitRegionMappingPointer->NVDIMMPhysicalID = NvdInfo->PhysId;
+ NfitRegionMappingPointer->InterleaveWays = NvdInfo->InterleaveWays;
+ NfitRegionMappingPointer->RegionOffset = NvdInfo->RegionOffset;
+ NfitRegionMappingPointer->NVDIMMRegionSize = NvdInfo->NvdSize;
+ NfitRegionMappingPointer->NFITDeviceHandle.DIMMNumber =
+ NvdInfo->DeviceHandle & 0x0F;
+ NfitRegionMappingPointer->NFITDeviceHandle.MemoryChannelNumber =
+ (NvdInfo->DeviceHandle >> 4) & 0x0F;
+ NfitRegionMappingPointer->NFITDeviceHandle.MemoryControllerID =
+ (NvdInfo->DeviceHandle >> 8) & 0x0F;
+ NfitRegionMappingPointer->NFITDeviceHandle.SocketID =
+ (NvdInfo->DeviceHandle >> 12) & 0x0F;
+ NfitRegionMappingPointer->SPARangeStructureIndex =
+ NfitSpaPointer->SPARangeStructureIndex;
+ NfitRegionMappingPointer->NVDIMMPhysicalAddressRegionBase =
+ NfitSpaPointer->SystemPhysicalAddressRangeBase;
+ NfitRegionMappingPointer->NVDIMMControlRegionStructureIndex =
+ NfitControlRegionPointer->NVDIMMControlRegionStructureIndex;
+}
+
+EFI_STATUS
+AcpiNfitFillTableBySK (
+ IN EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *NfitSpaPointerStart,
+ IN OUT EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE **NfitSpaPointerNext,
+ IN UINTN Socket
+ )
+{
+ EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *NfitSpaPointer;
+ EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *NfitControlRegionPointer;
+ EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE *NfitRegionMappingPointer;
+ PLATFORM_INFO_HOB *PlatformHob;
+ VOID *Hob;
+ UINT64 NvdRegionBase,
+ NvdRegionSize;
+ UINTN NvdCount, MaxNvdCount, RegionCount;
+ UINTN RegionId, NvdRegionIndex, NvdIndex;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL
+ || NfitSpaPointerStart == NULL
+ || NfitSpaPointerNext == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+ NvdRegionIndex = (Socket == 0) ? 0 : NvdData[NVDIMM_SK0].NvdRegionNum;
+ NvdIndex = (Socket == 0) ? 0 : NvdData[NVDIMM_SK0].NvdNum;
+ if (NvdData[Socket].NvdMode == NVDIMM_HASHED) {
+ /* Table Type 0: SPA Range Structure */
+ NfitSpaPointer = NfitSpaPointerStart;
+ CopyMem (
+ (VOID *)NfitSpaPointer,
+ (VOID *)&NfitSPATemplate,
+ sizeof (NfitSPATemplate)
+ );
+ RegionId = NvdData[Socket].NvdRegionId[0];
+ NvdRegionBase = PlatformHob->DramInfo.Base[RegionId];
+ NvdRegionSize = PlatformHob->DramInfo.Size[RegionId];
+ NvdRegionIndex++;
+ AcpiNfitFillSPA (
+ NfitSpaPointer,
+ NvdRegionIndex,
+ NvdRegionBase,
+ NvdRegionSize
+ );
+
+ NfitControlRegionPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *)
+ (NfitSpaPointer + 1);
+ for (NvdCount = 0; NvdCount < NVDIMM_NUM_PER_SK; NvdCount++) {
+ if (!NvdData[Socket].NvdInfo[NvdCount].Enabled) {
+ continue;
+ }
+ NvdIndex++;
+ /* Table Type 4: NVDIMM Control Region Structure Mark */
+ CopyMem (
+ (VOID *)NfitControlRegionPointer,
+ (VOID *)&NvdimmControlRegionTemplate,
+ sizeof (NvdimmControlRegionTemplate)
+ );
+ NfitFillControlRegion (
+ NfitControlRegionPointer,
+ &NvdData[Socket].NvdInfo[NvdCount],
+ NvdIndex
+ );
+
+ NfitRegionMappingPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE *)
+ (NfitControlRegionPointer + 1);
+
+ /* Table Type 1: NVDIMM Region Mapping Structure */
+ CopyMem (
+ (VOID *)NfitRegionMappingPointer,
+ (VOID *)&NvdimmRegionMappingTemplate,
+ sizeof (NvdimmRegionMappingTemplate)
+ );
+ NfitFillRegionMapping (
+ NfitRegionMappingPointer,
+ NfitControlRegionPointer,
+ NfitSpaPointer,
+ &NvdData[Socket].NvdInfo[NvdCount],
+ NvdIndex - 1
+ );
+
+ NfitControlRegionPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *)
+ (NfitRegionMappingPointer + 1);
+ }
+ NfitSpaPointer =
+ (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *)
+ NfitControlRegionPointer;
+ } else { /* NVDIMM_NON_HASHED */
+ NfitSpaPointer = NfitSpaPointerStart;
+ for (RegionCount = 0; RegionCount < NvdData[Socket].NvdRegionNum;
+ RegionCount++)
+ {
+ /* Table Type 0: SPA Range Structure */
+ CopyMem (
+ (VOID *)NfitSpaPointer,
+ (VOID *)&NfitSPATemplate,
+ sizeof (NfitSPATemplate)
+ );
+ RegionId = NvdData[Socket].NvdRegionId[RegionCount];
+ NvdRegionBase = PlatformHob->DramInfo.Base[RegionId];
+ NvdRegionSize = PlatformHob->DramInfo.Size[RegionId];
+ NvdRegionIndex++;
+ AcpiNfitFillSPA (
+ NfitSpaPointer,
+ NvdRegionIndex,
+ NvdRegionBase,
+ NvdRegionSize
+ );
+
+ NfitControlRegionPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *)
+ (NfitSpaPointer + 1);
+ NvdCount = ((NvdRegionBase == PLATFORM_NVDIMM_SK0_NHASHED_REGION0) ||
+ (NvdRegionBase == PLATFORM_NVDIMM_SK1_NHASHED_REGION0)) ?
+ 0 : PLATFORM_NVDIMM_NUM_MAX_PER_MCU;
+ MaxNvdCount = NvdCount + PLATFORM_NVDIMM_NUM_MAX_PER_MCU;
+ for (; NvdCount < MaxNvdCount; NvdCount++) {
+ if (!NvdData[Socket].NvdInfo[NvdCount].Enabled) {
+ continue;
+ }
+ NvdIndex++;
+
+ /* Table Type 4: NVDIMM Control Region Structure Mark */
+ CopyMem (
+ (VOID *)NfitControlRegionPointer,
+ (VOID *)&NvdimmControlRegionTemplate,
+ sizeof (NvdimmControlRegionTemplate)
+ );
+ NfitFillControlRegion (
+ NfitControlRegionPointer,
+ &NvdData[Socket].NvdInfo[NvdCount],
+ NvdIndex
+ );
+
+ NfitRegionMappingPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE *)
+ (NfitControlRegionPointer + 1);
+
+ /* Table Type 1: NVDIMM Region Mapping Structure */
+ CopyMem (
+ (VOID *)NfitRegionMappingPointer,
+ (VOID *)&NvdimmRegionMappingTemplate,
+ sizeof (NvdimmRegionMappingTemplate)
+ );
+ NfitFillRegionMapping (
+ NfitRegionMappingPointer,
+ NfitControlRegionPointer,
+ NfitSpaPointer,
+ &NvdData[Socket].NvdInfo[NvdCount],
+ NvdIndex - 1
+ );
+
+ NfitControlRegionPointer =
+ (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE *)
+ (NfitRegionMappingPointer + 1);
+ }
+ NfitSpaPointer =
+ (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *)
+ NfitControlRegionPointer;
+ }
+ }
+ /* Update NfitSpaPointerNext */
+ *NfitSpaPointerNext = NfitSpaPointer;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+AcpiNfitFillTable (
+ IN EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE *NfitTablePointer
+ )
+{
+ EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *NfitSpaPointerNext;
+
+ if (NfitTablePointer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NfitSpaPointerNext = (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE *)
+ (NfitTablePointer + 1);
+
+ if (NvdData[NVDIMM_SK0].NvdRegionNum != 0) {
+ AcpiNfitFillTableBySK (NfitSpaPointerNext, &NfitSpaPointerNext, NVDIMM_SK0);
+ }
+
+ if (NvdData[NVDIMM_SK1].NvdRegionNum != 0) {
+ AcpiNfitFillTableBySK (NfitSpaPointerNext, &NfitSpaPointerNext, NVDIMM_SK1);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Install NFIT table.
+ */
+EFI_STATUS
+AcpiInstallNfitTable (
+ VOID
+ )
+{
+ EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE *NfitTablePointer;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ UINTN NfitTableKey = 0;
+ EFI_STATUS Status;
+ UINTN Size;
+ UINTN NvdRegionNum;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Status = AcpiNvdDataInit (NVDIMM_SK0);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Status = AcpiNvdDataInit (NVDIMM_SK1);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ NvdRegionNum = NvdData[NVDIMM_SK0].NvdRegionNum +
+ NvdData[NVDIMM_SK1].NvdRegionNum;
+ if (NvdRegionNum == 0) {
+ return EFI_INVALID_PARAMETER; /* No NVDIMM Region */
+ }
+ Size = sizeof (EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE);
+ if (NvdData[NVDIMM_SK0].NvdRegionNum != 0) {
+ Size +=
+ (sizeof (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE) *
+ NvdData[NVDIMM_SK0].NvdRegionNum) +
+ (sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE) *
+ NvdData[NVDIMM_SK0].NvdNum) +
+ (sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE) *
+ NvdData[NVDIMM_SK0].NvdNum);
+ }
+ if (NvdData[NVDIMM_SK1].NvdRegionNum != 0) {
+ Size +=
+ (sizeof (EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE) *
+ NvdData[NVDIMM_SK1].NvdRegionNum) +
+ (sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE) *
+ NvdData[NVDIMM_SK1].NvdNum) +
+ (sizeof (EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE) *
+ NvdData[NVDIMM_SK1].NvdNum);
+ }
+ NfitTablePointer =
+ (EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE *)AllocateZeroPool (Size);
+ if (NfitTablePointer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (
+ (VOID *)NfitTablePointer,
+ (VOID *)&NFITTableHeaderTemplate,
+ sizeof (NFITTableHeaderTemplate)
+ );
+
+ NfitTablePointer->Header.Length = Size;
+
+ Status = AcpiNfitFillTable (NfitTablePointer);
+ if (EFI_ERROR (Status)) {
+ FreePool ((VOID *)NfitTablePointer);
+ return Status;
+ }
+ AcpiUpdateChecksum ((UINT8 *)NfitTablePointer, NfitTablePointer->Header.Length);
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)NfitTablePointer,
+ NfitTablePointer->Header.Length,
+ &NfitTableKey
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool ((VOID *)NfitTablePointer);
+ }
+ return Status;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPcct.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPcct.c
new file mode 100644
index 000000000000..6f4b252ab366
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPcct.c
@@ -0,0 +1,413 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiPlatform.h"
+
+#include <Library/MailboxInterfaceLib.h>
+#include <Library/SystemFirmwareInterfaceLib.h>
+#include <Library/TimerLib.h>
+
+//
+// The communication data for advertising the shared memory address to the SMpro/PMpro.
+//
+#define PCC_PAYLOAD_ADVERTISE_ADDRESS 0x0F000000
+#define PCC_PAYLOAD_SIZE 12 // Bytes
+
+//
+// ACPI Platform Communication Channel (PCC)
+//
+#define PCC_SUBSPACE_SHARED_MEM_SIGNATURE 0x50434300 // "PCC"
+#define PCC_SUBSPACE_SHARED_MEM_SIZE 0x4000 // Number of Bytes
+
+//
+// Mask for available doorbells. This is used to reserve
+// doorbells which are for other communications with OS.
+//
+// Each bit in the mask represents each doorbell channel
+// from PMpro Doorbell 0 to PMpro Doorbell 7 and SMpro
+// Doorbell channel 0 to SMpro Doorbell channel 7.
+//
+#define PCC_AVAILABLE_DOORBELL_MASK 0xEFFFEFFF
+
+#define PCC_MAX_VALID_DOORBELL_COUNT (NUMBER_OF_DOORBELLS_PER_SOCKET * PLATFORM_CPU_MAX_SOCKET)
+
+#define PCC_NOMINAL_LATENCY_US 1000 // us
+#define PCC_MAX_PERIODIC_ACCESS_RATE 0 // no limitation
+#define PCC_MIN_REQ_TURNAROUND_TIME_US 0
+
+// Polling interval for PCC Command Complete
+#define PCC_COMMAND_POLL_INTERVAL_US 10
+
+#define PCC_COMMAND_POLL_COUNT (PCC_NOMINAL_LATENCY_US / PCC_COMMAND_POLL_INTERVAL_US)
+
+//
+// Doorbell Channel for CPPC
+//
+#define PCC_CPPC_DOORBELL_ID (PMproDoorbellChannel2)
+
+#define PCC_CPPC_NOMINAL_LATENCY_US 100
+#define PCC_CPPC_MIN_REQ_TURNAROUND_TIME_US 110
+
+//
+// Shared memory regions allocated for PCC subspaces
+//
+STATIC EFI_PHYSICAL_ADDRESS mPccSharedMemoryAddress;
+STATIC UINTN mPccSharedMemorySize;
+
+
+EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS PcctSubspaceTemplate = {
+ EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS,
+ sizeof (EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS),
+ 0, // PlatformInterrupt
+ 0, // PlatformInterruptFlags
+ 0, // Reserved
+ 0, // BaseAddress
+ 0x100, // AddressLength
+ { 0, 0x20, 0, 0x3, 0x0 }, // DoorbellRegister
+ 0, // DoorbellPreserve
+ 0x53000040, // DoorbellWrite
+ 1, // NominalLatency
+ 1, // MaximumPeriodicAccessRate
+ 1, // MinimumRequestTurnaroundTime
+ { 0, 0x20, 0, 0x3, 0x0 }, // PlatformInterruptAckRegister
+ 0, // PlatformInterruptAckPreserve
+ 0x10001, // PlatformInterruptAckWrite
+};
+
+EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER PcctTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER,
+ EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION
+ ),
+ EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT,
+};
+
+
+/**
+ Check whether the Doorbell is reserved or not.
+
+**/
+BOOLEAN
+PcctIsDoorbellReserved (
+ IN UINT16 Doorbell
+ )
+{
+ ASSERT (Doorbell <= PCC_MAX_VALID_DOORBELL_COUNT);
+
+ if (((1 << Doorbell) & PCC_AVAILABLE_DOORBELL_MASK) == 0) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Get number of available doorbells for the usage of PCC communication.
+
+**/
+UINT16
+PcctGetNumberOfAvailableDoorbells (
+ VOID
+ )
+{
+ UINT16 Doorbell;
+ UINT16 AvailableDoorbellCount;
+
+ AvailableDoorbellCount = 0;
+ for (Doorbell = 0; Doorbell < NUMBER_OF_DOORBELLS_PER_SOCKET; Doorbell++ ) {
+ if (((1 << Doorbell) & PCC_AVAILABLE_DOORBELL_MASK) != 0) {
+ AvailableDoorbellCount++;
+ }
+ }
+ ASSERT (AvailableDoorbellCount <= PCC_MAX_VALID_DOORBELL_COUNT);
+
+ return AvailableDoorbellCount;
+}
+
+/**
+ Allocate memory pages for the PCC shared memory region.
+
+**/
+EFI_STATUS
+PcctAllocateSharedMemory (
+ IN UINT16 SubspaceCount,
+ OUT EFI_PHYSICAL_ADDRESS *PccSharedMemoryPtr
+ )
+{
+ EFI_STATUS Status;
+
+ mPccSharedMemorySize = PCC_SUBSPACE_SHARED_MEM_SIZE * SubspaceCount;
+
+ Status = gBS->AllocatePages (
+ AllocateAnyPages,
+ EfiRuntimeServicesData,
+ EFI_SIZE_TO_PAGES (mPccSharedMemorySize),
+ &mPccSharedMemoryAddress
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate PCC shared memory\n"));
+ mPccSharedMemorySize = 0;
+ return Status;
+ }
+
+ *PccSharedMemoryPtr = mPccSharedMemoryAddress;
+
+ return EFI_SUCCESS;
+}
+
+EFI_PHYSICAL_ADDRESS
+PcctGetSharedMemoryAddress (
+ IN UINT8 Socket,
+ IN UINT16 Subspace
+ )
+{
+ ASSERT (Socket < PLATFORM_CPU_MAX_SOCKET);
+
+ return (mPccSharedMemoryAddress + PCC_SUBSPACE_SHARED_MEM_SIZE * Subspace);
+}
+
+/**
+ Free the whole shared memory region that is allocated by
+ the PcctAllocateSharedMemory() function.
+
+**/
+VOID
+PcctFreeSharedMemory (
+ VOID
+ )
+{
+ if (mPccSharedMemoryAddress != 0 && mPccSharedMemorySize != 0) {
+ gBS->FreePages (
+ mPccSharedMemoryAddress,
+ EFI_SIZE_TO_PAGES (mPccSharedMemorySize)
+ );
+
+ mPccSharedMemoryAddress = 0;
+ }
+}
+
+/**
+ This function is to advertise the shared memory region address
+ to the platform (SMpro/PMpro).
+
+**/
+EFI_STATUS
+PcctAdvertiseSharedMemoryAddress (
+ IN UINT8 Socket,
+ IN UINT16 Doorbell,
+ IN UINT16 Subspace
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER *PccSharedMemoryRegion;
+ UINT32 CommunicationData;
+ UINTN Timeout;
+
+ if (Socket >= PLATFORM_CPU_MAX_SOCKET
+ || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PccSharedMemoryRegion = (EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER *)
+ PcctGetSharedMemoryAddress (Socket, Subspace);
+ ASSERT (PccSharedMemoryRegion != NULL);
+
+ //
+ // Zero shared memory region for each PCC subspace
+ //
+ SetMem (
+ (VOID *)PccSharedMemoryRegion,
+ sizeof (EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER) + PCC_PAYLOAD_SIZE,
+ 0
+ );
+
+ // Advertise shared memory address to Platform (SMpro/PMpro)
+ // by ringing the doorbell with dummy PCC message
+ //
+ CommunicationData = PCC_PAYLOAD_ADVERTISE_ADDRESS;
+
+ //
+ // Write Data into Communication Space Region
+ //
+ CopyMem ((VOID *)(PccSharedMemoryRegion + 1), &CommunicationData, sizeof (CommunicationData));
+
+ PccSharedMemoryRegion->Status.CommandComplete = 0;
+ PccSharedMemoryRegion->Signature = PCC_SUBSPACE_SHARED_MEM_SIGNATURE | Subspace;
+
+ Status = MailboxMsgSetPccSharedMem (Socket, Doorbell, TRUE, (UINT64)PccSharedMemoryRegion);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to send mailbox message!\n", __FUNCTION__));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // Polling CMD_COMPLETE bit
+ //
+ Timeout = PCC_COMMAND_POLL_COUNT;
+ while (PccSharedMemoryRegion->Status.CommandComplete != 1) {
+ if (--Timeout <= 0) {
+ DEBUG ((DEBUG_ERROR, "%a - Timeout occurred when polling the PCC Status Complete\n", __FUNCTION__));
+ return EFI_TIMEOUT;
+ }
+ MicroSecondDelay (PCC_COMMAND_POLL_INTERVAL_US);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+AcpiPcctInitializeSharedMemory (
+ VOID
+ )
+{
+ UINT8 SocketCount;
+ UINT8 Socket;
+ UINT16 Doorbell;
+ UINT16 Subspace;
+
+ SocketCount = GetNumberOfActiveSockets ();
+ Subspace = 0;
+
+ for (Socket = 0; Socket < SocketCount; Socket++) {
+ for (Doorbell = 0; Doorbell < NUMBER_OF_DOORBELLS_PER_SOCKET; Doorbell++ ) {
+ if (PcctIsDoorbellReserved (Doorbell + NUMBER_OF_DOORBELLS_PER_SOCKET * Socket)) {
+ continue;
+ }
+ PcctAdvertiseSharedMemoryAddress (Socket, Doorbell, Subspace);
+ MailboxUnmaskInterrupt (Socket, Doorbell);
+
+ Subspace++;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Install PCCT table.
+
+ PCC channels are associated with hardware doorbell instances to provide
+ bi-directional communication between the OS and platform entities.
+
+**/
+EFI_STATUS
+AcpiInstallPcctTable (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *PcctTableHeader;
+ EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS *PccSubspacePtr;
+ EFI_PHYSICAL_ADDRESS PccSharedMemoryPtr;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ UINTN PcctTableKey;
+ UINT8 SocketCount;
+ UINT8 Socket;
+ UINT16 Doorbell;
+ UINT16 Subspace;
+ UINT16 SubspaceCount;
+ UINTN Size;
+ UINTN DoorbellAddress;
+ UINTN DoorbellCount;
+
+ Subspace = 0;
+ SocketCount = GetNumberOfActiveSockets ();
+ DoorbellCount = PcctGetNumberOfAvailableDoorbells ();
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ SubspaceCount = DoorbellCount * SocketCount;
+
+ PcctAllocateSharedMemory (SubspaceCount, &PccSharedMemoryPtr);
+ if (PccSharedMemoryPtr == (EFI_PHYSICAL_ADDRESS)(UINTN)NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Size = sizeof (EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER) +
+ SubspaceCount * sizeof (EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS);
+
+ PcctTableHeader = (EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (PcctTableHeader == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PccSubspacePtr = (EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS *)(PcctTableHeader + 1);
+
+ for (Socket = 0; Socket < SocketCount; Socket++) {
+ for (Doorbell = 0; Doorbell < NUMBER_OF_DOORBELLS_PER_SOCKET; Doorbell++ ) {
+ if (PcctIsDoorbellReserved (Doorbell + NUMBER_OF_DOORBELLS_PER_SOCKET * Socket)) {
+ continue;
+ }
+
+ CopyMem (
+ PccSubspacePtr,
+ &PcctSubspaceTemplate,
+ sizeof (EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS)
+ );
+
+ PccSubspacePtr->BaseAddress = (UINT64)PccSharedMemoryPtr + PCC_SUBSPACE_SHARED_MEM_SIZE * Subspace;
+ PccSubspacePtr->AddressLength = PCC_SUBSPACE_SHARED_MEM_SIZE;
+
+ DoorbellAddress = MailboxGetDoorbellAddress (Socket, Doorbell);
+
+ PccSubspacePtr->DoorbellRegister.Address = DoorbellAddress + DB_OUT_REG_OFST;
+ PccSubspacePtr->PlatformInterrupt = MailboxGetDoorbellInterruptNumber (Socket, Doorbell);
+ PccSubspacePtr->PlatformInterruptAckRegister.Address = DoorbellAddress + DB_STATUS_REG_OFST;
+
+ if (Doorbell == PCC_CPPC_DOORBELL_ID) {
+ PccSubspacePtr->DoorbellWrite = MAILBOX_URGENT_CPPC_MESSAGE;
+ PccSubspacePtr->NominalLatency = PCC_CPPC_NOMINAL_LATENCY_US;
+ PccSubspacePtr->MinimumRequestTurnaroundTime = PCC_CPPC_MIN_REQ_TURNAROUND_TIME_US;
+ } else {
+ PccSubspacePtr->DoorbellWrite = MAILBOX_TYPICAL_PCC_MESSAGE;
+ PccSubspacePtr->NominalLatency = PCC_NOMINAL_LATENCY_US;
+ PccSubspacePtr->MinimumRequestTurnaroundTime = PCC_MIN_REQ_TURNAROUND_TIME_US;
+ }
+ PccSubspacePtr->MaximumPeriodicAccessRate = PCC_MAX_PERIODIC_ACCESS_RATE;
+
+ PccSubspacePtr++;
+ Subspace++;
+ }
+ }
+
+ CopyMem (
+ PcctTableHeader,
+ &PcctTableHeaderTemplate,
+ sizeof (EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER)
+ );
+
+ PcctTableHeader->Header.Length = Size;
+
+ AcpiUpdateChecksum (
+ (UINT8 *)PcctTableHeader,
+ PcctTableHeader->Header.Length
+ );
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)PcctTableHeader,
+ PcctTableHeader->Header.Length,
+ &PcctTableKey
+ );
+ if (EFI_ERROR (Status)) {
+ PcctFreeSharedMemory ();
+ FreePool ((VOID *)PcctTableHeader);
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c
new file mode 100644
index 000000000000..4a04343c9ea0
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c
@@ -0,0 +1,178 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiApei.h"
+#include "AcpiPlatform.h"
+
+STATIC EFI_EVENT mAcpiRegistration = NULL;
+
+/*
+ * This GUID must match the FILE_GUID in AcpiTables.inf of each boards
+ */
+STATIC CONST EFI_GUID mAcpiCommonTableFile = { 0xCEFA2AEB, 0x357E, 0x4F48, { 0x80, 0x66, 0xEA, 0x95, 0x08, 0x53, 0x05, 0x6E } } ;
+STATIC CONST EFI_GUID mJadeAcpiTableFile = { 0x5addbc13, 0x8634, 0x480c, { 0x9b, 0x94, 0x67, 0x1b, 0x78, 0x55, 0xcd, 0xb8 } };
+/**
+ * Callback called when ACPI Protocol is installed
+ */
+STATIC VOID
+AcpiNotificationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
+
+ Status = LocateAndInstallAcpiFromFv (&mAcpiCommonTableFile);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = LocateAndInstallAcpiFromFv (&mJadeAcpiTableFile);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Find ACPI table RSD_PTR from the system table.
+ //
+ Status = EfiGetSystemConfigurationTable (&gEfiAcpiTableGuid, (VOID **)&Rsdp);
+ if (EFI_ERROR (Status)) {
+ Status = EfiGetSystemConfigurationTable (&gEfiAcpi10TableGuid, (VOID **)&Rsdp);
+ }
+
+ if (!EFI_ERROR (Status) &&
+ Rsdp != NULL &&
+ Rsdp->Revision >= EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION &&
+ Rsdp->RsdtAddress != 0)
+ {
+ // ARM Platforms must set the RSDT address to NULL
+ Rsdp->RsdtAddress = 0;
+ }
+
+ DEBUG ((DEBUG_INFO, "[%a:%d]-\n", __FUNCTION__, __LINE__));
+}
+
+VOID
+EFIAPI
+InstallAcpiOnReadyToBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ Status = AcpiInstallMadtTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Installed MADT table\n"));
+ }
+
+ Status = AcpiInstallPpttTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Installed PPTT table\n"));
+ }
+
+ Status = AcpiInstallSlitTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Installed SLIT table\n"));
+ }
+
+ Status = AcpiInstallSratTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Installed SRAT table\n"));
+ }
+
+ Status = AcpiInstallPcctTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Installed PCCT table\n"));
+ }
+
+ Status = AcpiInstallNfitTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Installed NFIT table\n"));
+ }
+
+ Status = AcpiPopulateBert ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "Populate BERT record\n"));
+ }
+
+ //
+ // Close the event, so it will not be signalled again.
+ //
+ gBS->CloseEvent (Event);
+}
+
+VOID
+EFIAPI
+UpdateAcpiOnExitBootServices (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ Status = AcpiPatchDsdtTable ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "DSDT Table updated!\n"));
+ }
+
+ // Configure ACPI Platform Error Interfaces
+ Status = AcpiApeiUpdate ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "APEI Table updated!\n"));
+ }
+
+ // Advertise shared memory regions to SMpro/PMpro and unmask interrupt
+ Status = AcpiPcctInitializeSharedMemory ();
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "PCCT Table updated!\n"));
+ }
+
+ //
+ // Close the event, so it will not be signalled again.
+ //
+ gBS->CloseEvent (Event);
+}
+
+EFI_STATUS
+EFIAPI
+AcpiPlatformDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_EVENT ReadyToBootEvent;
+ EFI_EVENT ExitBootServicesEvent;
+ EFI_STATUS Status;
+
+ EfiCreateProtocolNotifyEvent (
+ &gEfiAcpiTableProtocolGuid,
+ TPL_CALLBACK,
+ AcpiNotificationEvent,
+ NULL,
+ &mAcpiRegistration
+ );
+
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_CALLBACK,
+ UpdateAcpiOnExitBootServices,
+ NULL,
+ &ExitBootServicesEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ InstallAcpiOnReadyToBoot,
+ NULL,
+ &gEfiEventReadyToBootGuid,
+ &ReadyToBootEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c
new file mode 100644
index 000000000000..0e09a17cc52d
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c
@@ -0,0 +1,333 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/ArmCache.h>
+#include <Library/ArmLib.h>
+#include "AcpiPlatform.h"
+
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR PPTTProcessorTemplate = {
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ {0}, /* Flags */
+ 0, /* Parent */
+ 0, /* AcpiProcessorId */
+ 0 /* NumberOfPrivateResources */
+};
+
+EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE PPTTCacheTemplate = {
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ {0}, /* Flags */
+ 0, /* NextLevelOfCache */
+ 0, /* Size */
+ 0, /* NumberOfSets */
+ 0, /* Associativity */
+ {0}, /* Attributes */
+ 0
+};
+
+EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER PPTTTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ ),
+};
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *PpttTablePointer;
+STATIC UINT32 PpttClusterOffset[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_MAX_SOCKET];
+STATIC UINT32 PpttSocketOffset[PLATFORM_CPU_MAX_SOCKET];
+STATIC UINT32 PpttRootOffset;
+STATIC UINT32 PpttL1DataCacheOffset[PLATFORM_CPU_MAX_NUM_CORES];
+STATIC UINT32 PpttL1InstructionCacheOffset[PLATFORM_CPU_MAX_NUM_CORES];
+STATIC UINT32 PpttL2CacheOffset[PLATFORM_CPU_MAX_NUM_CORES];
+
+UINT32
+AcpiPpttProcessorCoreNode (
+ VOID *EntryPointer,
+ UINT32 CpuId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *PpttProcessorEntryPointer = EntryPointer;
+ UINT32 *ResPointer;
+ UINTN ClusterIdPerSocket, CoreIdPerCpm, SocketId;
+
+ CopyMem (
+ PpttProcessorEntryPointer,
+ &PPTTProcessorTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)
+ );
+
+ ClusterIdPerSocket = (CpuId / PLATFORM_CPU_NUM_CORES_PER_CPM) % PLATFORM_CPU_MAX_CPM;
+ SocketId = (CpuId / PLATFORM_CPU_NUM_CORES_PER_CPM) / PLATFORM_CPU_MAX_CPM;
+ CoreIdPerCpm = CpuId % PLATFORM_CPU_NUM_CORES_PER_CPM;
+ PpttProcessorEntryPointer->Flags.AcpiProcessorIdValid = 1;
+ PpttProcessorEntryPointer->Flags.NodeIsALeaf = 1;
+ PpttProcessorEntryPointer->Flags.IdenticalImplementation = 1;
+ PpttProcessorEntryPointer->AcpiProcessorId = (SocketId << PLATFORM_SOCKET_UID_BIT_OFFSET) | (ClusterIdPerSocket << 8) | CoreIdPerCpm;
+ PpttProcessorEntryPointer->Parent = (UINT32)PpttClusterOffset[CpuId / PLATFORM_CPU_NUM_CORES_PER_CPM];
+ PpttProcessorEntryPointer->NumberOfPrivateResources = 2; /* L1I + L1D */
+
+ ResPointer = (UINT32 *)((UINT64)EntryPointer +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ ResPointer[0] = PpttL1InstructionCacheOffset[CpuId];
+ ResPointer[1] = PpttL1DataCacheOffset[CpuId];
+
+ PpttProcessorEntryPointer->Length = sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + 2 * sizeof (UINT32);
+
+ return PpttProcessorEntryPointer->Length;
+}
+
+STATIC UINT32
+AcpiPpttClusterNode (
+ VOID *EntryPointer,
+ UINT32 ClusterId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *PpttProcessorEntryPointer = EntryPointer;
+
+ PpttClusterOffset[ClusterId] = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+
+ CopyMem (
+ PpttProcessorEntryPointer,
+ &PPTTProcessorTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)
+ );
+
+ PpttProcessorEntryPointer->Parent = (UINT32)PpttSocketOffset[ClusterId / PLATFORM_CPU_MAX_CPM];
+ PpttProcessorEntryPointer->Flags.IdenticalImplementation = 1;
+
+ return PpttProcessorEntryPointer->Length;
+}
+
+STATIC UINT32
+AcpiPpttSocketNode (
+ VOID *EntryPointer,
+ UINT32 SocketId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *PpttProcessorEntryPointer = EntryPointer;
+
+ PpttSocketOffset[SocketId] = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+
+ CopyMem (
+ PpttProcessorEntryPointer,
+ &PPTTProcessorTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)
+ );
+
+ PpttProcessorEntryPointer->Flags.PhysicalPackage = 1;
+ PpttProcessorEntryPointer->Flags.IdenticalImplementation = 1;
+ PpttProcessorEntryPointer->Parent = (UINT32)PpttRootOffset;
+
+ return PpttProcessorEntryPointer->Length;
+}
+
+STATIC UINT32
+AcpiPpttRootNode (
+ VOID *EntryPointer
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *PpttProcessorEntryPointer = EntryPointer;
+
+ PpttRootOffset = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+
+ CopyMem (
+ PpttProcessorEntryPointer,
+ &PPTTProcessorTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)
+ );
+
+ PpttProcessorEntryPointer->Flags.IdenticalImplementation = 1;
+
+ return PpttProcessorEntryPointer->Length;
+}
+
+STATIC VOID
+AcpiPpttFillCacheSizeInfo (
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *Node,
+ UINT32 Level,
+ BOOLEAN DataCache,
+ BOOLEAN UnifiedCache
+ )
+{
+ CSSELR_DATA CsselrData;
+ CCSIDR_DATA CcsidrData;
+
+ CsselrData.Data = 0;
+ CsselrData.Bits.Level = Level - 1;
+ CsselrData.Bits.InD = (!DataCache && !UnifiedCache);
+
+ CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+ Node->Flags.LineSizeValid = 1;
+ Node->Flags.NumberOfSetsValid = 1;
+ Node->Flags.AssociativityValid = 1;
+ Node->Flags.SizePropertyValid = 1;
+ Node->Flags.CacheTypeValid = 1;
+ Node->NumberOfSets = (UINT16)CcsidrData.BitsNonCcidx.NumSets + 1;
+ Node->Associativity = (UINT16)CcsidrData.BitsNonCcidx.Associativity + 1;
+ Node->LineSize = (UINT16)(1 << (CcsidrData.BitsNonCcidx.LineSize + 4));;
+ Node->Size = Node->NumberOfSets *
+ Node->Associativity *
+ Node->LineSize;
+}
+
+STATIC UINT32
+AcpiPpttL1DataCacheNode (
+ VOID *EntryPointer,
+ UINT32 CpuId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *PpttCacheEntryPointer = EntryPointer;
+
+ PpttL1DataCacheOffset[CpuId] = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+ CopyMem (
+ PpttCacheEntryPointer,
+ &PPTTCacheTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)
+ );
+
+ AcpiPpttFillCacheSizeInfo (PpttCacheEntryPointer, 1, TRUE, FALSE);
+ PpttCacheEntryPointer->Attributes.CacheType = 0x0; /* Data Cache */
+ PpttCacheEntryPointer->NextLevelOfCache = PpttL2CacheOffset[CpuId];
+
+ return PpttCacheEntryPointer->Length;
+}
+
+STATIC UINT32
+AcpiPpttL1InstructionCacheNode (
+ VOID *EntryPointer,
+ UINT32 CpuId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *PpttCacheEntryPointer = EntryPointer;
+
+ PpttL1InstructionCacheOffset[CpuId] = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+ CopyMem (
+ PpttCacheEntryPointer,
+ &PPTTCacheTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)
+ );
+
+ AcpiPpttFillCacheSizeInfo (PpttCacheEntryPointer, 1, FALSE, FALSE);
+ PpttCacheEntryPointer->Attributes.CacheType = 0x1; /* Instruction Cache */
+ PpttCacheEntryPointer->NextLevelOfCache = PpttL2CacheOffset[CpuId];
+
+ return PpttCacheEntryPointer->Length;
+}
+
+STATIC UINT32
+AcpiPpttL2CacheNode (
+ VOID *EntryPointer,
+ UINT32 CpuId
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *PpttCacheEntryPointer = EntryPointer;
+
+ PpttL2CacheOffset[CpuId] = (UINT64)EntryPointer - (UINT64)PpttTablePointer;
+ CopyMem (
+ PpttCacheEntryPointer,
+ &PPTTCacheTemplate,
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)
+ );
+
+ AcpiPpttFillCacheSizeInfo (PpttCacheEntryPointer, 2, FALSE, TRUE);
+ PpttCacheEntryPointer->Attributes.CacheType = 0x3; /* Unified Cache */
+ PpttCacheEntryPointer->NextLevelOfCache = 0;
+
+ return PpttCacheEntryPointer->Length;
+}
+
+/*
+ * Install PPTT table.
+ */
+EFI_STATUS
+AcpiInstallPpttTable (
+ VOID
+ )
+{
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *PpttProcessorEntryPointer = NULL;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ UINTN PpttTableKey = 0;
+ INTN Count;
+ EFI_STATUS Status;
+ UINTN Size;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Size = sizeof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + /* Root node */
+ (PLATFORM_CPU_MAX_SOCKET * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)) + /* Socket node */
+ (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_MAX_SOCKET * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)) + /* Cluster node */
+ (PLATFORM_CPU_MAX_NUM_CORES * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + 2 * sizeof (UINT32))) + /* Core node */
+ (PLATFORM_CPU_MAX_NUM_CORES * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) + /* L1I node */
+ (PLATFORM_CPU_MAX_NUM_CORES * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) + /* L1D node */
+ (PLATFORM_CPU_MAX_NUM_CORES * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); /* L2 node */
+
+ PpttTablePointer =
+ (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (PpttTablePointer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ PpttProcessorEntryPointer =
+ (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)((UINT64)PpttTablePointer +
+ sizeof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER));
+
+ Size = 0;
+ Size += AcpiPpttRootNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size));
+
+ for (Count = 0; Count < PLATFORM_CPU_MAX_SOCKET; Count++) {
+ Size += AcpiPpttSocketNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ }
+
+ for (Count = 0; Count < PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_MAX_SOCKET; Count++) {
+ Size += AcpiPpttClusterNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ }
+
+ for (Count = 0; Count < PLATFORM_CPU_MAX_NUM_CORES; Count++) {
+ Size += AcpiPpttL2CacheNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ Size += AcpiPpttL1InstructionCacheNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ Size += AcpiPpttL1DataCacheNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ Size += AcpiPpttProcessorCoreNode ((VOID *)((UINT64)PpttProcessorEntryPointer + Size), Count);
+ }
+
+ CopyMem (
+ PpttTablePointer,
+ &PPTTTableHeaderTemplate,
+ sizeof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER)
+ );
+
+ Size += sizeof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER);
+ PpttTablePointer->Header.Length = Size;
+
+ AcpiUpdateChecksum ((UINT8 *)PpttTablePointer, PpttTablePointer->Header.Length);
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)PpttTablePointer,
+ PpttTablePointer->Header.Length,
+ &PpttTableKey
+ );
+ FreePool ((VOID *)PpttTablePointer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSlit.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSlit.c
new file mode 100644
index 000000000000..0b534e739b4e
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSlit.c
@@ -0,0 +1,187 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiPlatform.h"
+
+#define MAX_NODES_PER_SOCKET 4
+#define SELF_DISTANCE 10
+#define REMOTE_DISTANCE 20
+
+EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER SLITTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION
+ ),
+ 0,
+};
+
+VOID
+ComputeCoordinatesForNode (
+ UINTN Node,
+ UINTN *X,
+ UINTN *Y
+ )
+{
+ switch (Node) {
+ case 0:
+ *X = 0;
+ *Y = 0;
+ break;
+ case 1:
+ *X = 1;
+ *Y = 0;
+ break;
+ case 2:
+ *X = 0;
+ *Y = 1;
+ break;
+ case 3:
+ *X = 1;
+ *Y = 1;
+ break;
+ default:
+ *X = 0;
+ *Y = 0;
+ break;
+ }
+}
+
+/**
+ Compute the distance between between two nodes on socket.
+**/
+UINT8
+ComputeSlitDistanceOnSocket (
+ UINTN Node1,
+ UINTN Node2
+ )
+{
+ UINTN X1, Y1, X2, Y2;
+ UINTN XDistance, YDistance;
+
+ ComputeCoordinatesForNode (Node1, &X1, &Y1);
+ ComputeCoordinatesForNode (Node2, &X2, &Y2);
+
+ XDistance = ABS ((INTN)(X1 - X2));
+ YDistance = ABS ((INTN)(Y1 - Y2));
+
+ return (UINT8)(XDistance + YDistance + SELF_DISTANCE);
+}
+
+/**
+ Compute the distance between between two nodes on
+ different sockets.
+ Node1 - local socket node number
+ Node2 - remote socket node number
+**/
+UINT8
+ComputeSlitDistanceOnRemoteSocket (
+ UINTN LocalNode,
+ UINTN RemoteNode
+ )
+{
+ UINTN LocalDistance, RemoteDistance;
+
+ //
+ // Mesh forwards traffic between sockets over both CCIX links when going from
+ // one quadrant to another. For example, memory access from Node 0 to Node 4
+ // results in traffic being split between RCA0 and 1. Hence distance is
+ // different only between upper half and lower half of sockets and not
+ // between quadrants. Hemisphere configuration is not impacted as there
+ // is no upper-half.
+ //
+ LocalDistance = 0;
+ RemoteDistance = 0;
+ if (LocalNode >= (MAX_NODES_PER_SOCKET / 2)) {
+ LocalDistance = 1;
+ }
+ if (RemoteNode >= (MAX_NODES_PER_SOCKET / 2)) {
+ RemoteDistance = 1;
+ }
+
+ return (UINT8)(LocalDistance + RemoteDistance + REMOTE_DISTANCE);
+}
+
+UINT8
+ComputeSlitDistance (
+ UINTN Node1,
+ UINTN Node2,
+ UINTN DomainsPerSocket
+ )
+{
+ UINT8 Distance;
+
+ Distance = 0;
+ if ((Node1 / DomainsPerSocket) == (Node2 / DomainsPerSocket)) {
+ Distance = ComputeSlitDistanceOnSocket (
+ Node1 % DomainsPerSocket,
+ Node2 % DomainsPerSocket
+ );
+ } else {
+ Distance = ComputeSlitDistanceOnRemoteSocket (
+ Node1 % DomainsPerSocket,
+ Node2 % DomainsPerSocket
+ );
+ }
+
+ return Distance;
+}
+
+EFI_STATUS
+AcpiInstallSlitTable (
+ VOID
+ )
+{
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ EFI_STATUS Status;
+ UINTN NumDomain, Count, Count1;
+ EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER *SlitTablePointer;
+ UINT8 *TmpPtr;
+ UINTN SlitTableKey;
+ UINTN NumDomainPerSocket;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ NumDomainPerSocket = CpuGetNumberOfSubNumaRegion ();
+ NumDomain = NumDomainPerSocket * GetNumberOfActiveSockets ();
+
+ SlitTablePointer = (EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER *)
+ AllocateZeroPool (sizeof (SLITTableHeaderTemplate) + NumDomain * NumDomain);
+ if (SlitTablePointer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem ((VOID *)SlitTablePointer, (VOID *)&SLITTableHeaderTemplate, sizeof (SLITTableHeaderTemplate));
+ SlitTablePointer->NumberOfSystemLocalities = NumDomain;
+ TmpPtr = (UINT8 *)SlitTablePointer + sizeof (SLITTableHeaderTemplate);
+ for (Count = 0; Count < NumDomain; Count++) {
+ for (Count1 = 0; Count1 < NumDomain; Count1++, TmpPtr++) {
+ *TmpPtr = ComputeSlitDistance (Count, Count1, NumDomainPerSocket);
+ }
+ }
+
+ SlitTablePointer->Header.Length = sizeof (SLITTableHeaderTemplate) + NumDomain * NumDomain;
+
+ AcpiUpdateChecksum ((UINT8 *)SlitTablePointer, SlitTablePointer->Header.Length);
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)SlitTablePointer,
+ SlitTablePointer->Header.Length,
+ &SlitTableKey
+ );
+ FreePool ((VOID *)SlitTablePointer);
+
+ return Status;
+}
diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
new file mode 100644
index 000000000000..ccd4f9eaeca9
--- /dev/null
+++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
@@ -0,0 +1,271 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Guid/ArmMpCoreInfo.h>
+#include "AcpiPlatform.h"
+
+EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER SRATTableHeaderTemplate = {
+ __ACPI_HEADER (
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ 0, /* need fill in */
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ ),
+ 0x00000001,
+ 0x0000000000000000,
+};
+
+EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE GicItsAffinityTemplate = {
+ .Type = EFI_ACPI_6_3_GIC_ITS_AFFINITY,
+ sizeof (EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE),
+ .ProximityDomain = 0, /* ProximityDomain */
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
+ .ItsId = 0,
+};
+
+STATIC
+UINTN
+SratCalculateNumMemoryRegion (
+ VOID
+ )
+{
+ PLATFORM_INFO_HOB *PlatformHob;
+ UINTN Count;
+ UINT64 TmpVal;
+ VOID *Hob;
+ UINTN Result;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return 0;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ Result = 0;
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ TmpVal = PlatformHob->DramInfo.Size[Count];
+ if (TmpVal > 0) {
+ Result++;
+ }
+ }
+
+ return Result;
+}
+
+STATIC
+EFI_STATUS
+SratAddMemAffinity (
+ EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE *SratMemAffinity
+ )
+{
+ PLATFORM_INFO_HOB *PlatformHob;
+ UINTN Count, NumRegion;
+ UINT64 RegionSize, RegionBase;
+ VOID *Hob;
+ UINTN ProximityDomain;
+
+ /* Get the Platform HOB */
+ Hob = GetFirstGuidHob (&gPlatformHobGuid);
+ if (Hob == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
+
+ NumRegion = 0;
+
+ for (Count = 0; Count < PlatformHob->DramInfo.NumRegion; Count++) {
+ RegionSize = PlatformHob->DramInfo.Size[Count];
+ RegionBase = PlatformHob->DramInfo.Base[Count];
+ ProximityDomain = PlatformHob->DramInfo.Node[Count];
+ if (RegionSize > 0) {
+ ZeroMem ((VOID *)&SratMemAffinity[NumRegion], sizeof (SratMemAffinity[NumRegion]));
+ SratMemAffinity[NumRegion].Flags = EFI_ACPI_6_3_MEMORY_ENABLED;
+ if (PlatformHob->DramInfo.NvdRegion[Count] != 0) {
+ /* Mark NVDIMM-N region as HOT_PLUGGABLE and NON-VOLATILE */
+ SratMemAffinity[NumRegion].Flags |= EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE |
+ EFI_ACPI_6_3_MEMORY_NONVOLATILE;
+ }
+ SratMemAffinity[NumRegion].LengthLow =
+ (UINT32)(RegionSize & 0xFFFFFFFF);
+ SratMemAffinity[NumRegion].LengthHigh =
+ (UINT32)((RegionSize & 0xFFFFFFFF00000000ULL) >> 32);
+ SratMemAffinity[NumRegion].AddressBaseLow =
+ (UINT32)(RegionBase & 0xFFFFFFFF);
+ SratMemAffinity[NumRegion].AddressBaseHigh =
+ (UINT32)((RegionBase & 0xFFFFFFFF00000000ULL) >> 32);
+ SratMemAffinity[NumRegion].ProximityDomain = (UINT32)(ProximityDomain);
+ SratMemAffinity[NumRegion].Type = EFI_ACPI_6_3_MEMORY_AFFINITY;
+ SratMemAffinity[NumRegion].Length = sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE);
+ NumRegion++;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SratAddGiccAffinity (
+ EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE *SratGiccAffinity
+ )
+{
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ UINTN Count, NumNode, Idx;
+ UINT32 AcpiProcessorUid;
+ UINT8 Socket;
+ UINT8 Cpm;
+
+ for (Idx = 0; Idx < gST->NumberOfTableEntries; Idx++) {
+ if (CompareGuid (&gArmMpCoreInfoGuid, &(gST->ConfigurationTable[Idx].VendorGuid))) {
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE *)gST->ConfigurationTable[Idx].VendorTable;
+ ArmCoreInfoTable = ArmProcessorTable->ArmCpus;
+ break;
+ }
+ }
+
+ if (Idx == gST->NumberOfTableEntries) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Count = 0;
+ NumNode = 0;
+ while (Count != ArmProcessorTable->NumberOfEntries) {
+ for (Idx = 0; Idx < ArmProcessorTable->NumberOfEntries; Idx++ ) {
+ Socket = ArmCoreInfoTable[Idx].ClusterId;
+ Cpm = (ArmCoreInfoTable[Idx].CoreId >> PLATFORM_CPM_UID_BIT_OFFSET);
+ if (CpuGetSubNumNode (Socket, Cpm) != NumNode) {
+ /* We add nodes based on ProximityDomain order */
+ continue;
+ }
+ AcpiProcessorUid = (ArmCoreInfoTable[Idx].ClusterId << PLATFORM_SOCKET_UID_BIT_OFFSET) +
+ ArmCoreInfoTable[Idx].CoreId;
+ ZeroMem ((VOID *)&SratGiccAffinity[Count], sizeof (SratGiccAffinity[Count]));
+ SratGiccAffinity[Count].AcpiProcessorUid = AcpiProcessorUid;
+ SratGiccAffinity[Count].Flags = 1;
+ SratGiccAffinity[Count].Length = sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE);
+ SratGiccAffinity[Count].Type = EFI_ACPI_6_3_GICC_AFFINITY;
+ SratGiccAffinity[Count].ProximityDomain = CpuGetSubNumNode (Socket, Cpm);
+ Count++;
+ }
+ NumNode++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC UINT32
+InstallGicItsAffinity (
+ VOID *EntryPointer,
+ UINT32 Index
+ )
+{
+ EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE *ItsAffinityEntryPointer = EntryPointer;
+ UINTN Size;
+
+ Size = sizeof (GicItsAffinityTemplate);
+ CopyMem (ItsAffinityEntryPointer, &GicItsAffinityTemplate, Size);
+ return Size;
+}
+
+STATIC
+EFI_STATUS
+SratAddGicItsAffinity (
+ VOID *TmpPtr
+ )
+{
+ UINTN Size = 0;
+ UINTN Index;
+
+ /* Install Gic ITSAffinity */
+ if (!IsSlaveSocketPresent ()) {
+ for (Index = 0; Index <= 1; Index++) { /* RCA0/1 */
+ GicItsAffinityTemplate.ItsId = Index;
+ GicItsAffinityTemplate.ProximityDomain = 0;
+ Size += InstallGicItsAffinity ((VOID *)((UINT64)TmpPtr + Size), Index);
+ }
+ }
+
+ for (Index = SOCKET0_FIRST_RC; Index <= SOCKET0_LAST_RC; Index++) {
+ GicItsAffinityTemplate.ItsId = Index;
+ GicItsAffinityTemplate.ProximityDomain = 0;
+ Size += InstallGicItsAffinity ((VOID *)((UINT64)TmpPtr + Size), Index);
+ }
+
+ if (IsSlaveSocketActive ()) {
+ for (Index = SOCKET1_FIRST_RC; Index <= SOCKET1_LAST_RC; Index++) {
+ GicItsAffinityTemplate.ItsId = Index;
+ GicItsAffinityTemplate.ProximityDomain = 1;
+ Size += InstallGicItsAffinity ((VOID *)((UINT64)TmpPtr + Size), Index);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+AcpiInstallSratTable (
+ VOID
+ )
+{
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
+ EFI_STATUS Status;
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER *SratTablePointer;
+ UINT8 *TmpPtr;
+ UINTN SratTableKey;
+ UINTN Size;
+
+ Status = gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&AcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Size = sizeof (SRATTableHeaderTemplate) +
+ SratCalculateNumMemoryRegion () * sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE) +
+ GetNumberOfActiveCores () * sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE) +
+ ((SOCKET0_LAST_RC - SOCKET0_FIRST_RC + 1) * sizeof (GicItsAffinityTemplate));
+ if (IsSlaveSocketActive ()) {
+ Size += (SOCKET1_LAST_RC - SOCKET1_FIRST_RC + 1) * sizeof (GicItsAffinityTemplate);
+ } else if (!IsSlaveSocketPresent ()) {
+ Size += 2 * sizeof (GicItsAffinityTemplate); /* RCA0/1 */
+ }
+
+ SratTablePointer = (EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (SratTablePointer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem ((VOID *)SratTablePointer, (VOID *)&SRATTableHeaderTemplate, sizeof (SRATTableHeaderTemplate));
+
+ TmpPtr = (UINT8 *)SratTablePointer + sizeof (SRATTableHeaderTemplate);
+ Status = SratAddMemAffinity ((EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE *)TmpPtr);
+ ASSERT_EFI_ERROR (Status);
+
+ TmpPtr += SratCalculateNumMemoryRegion () * sizeof (EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE);
+ Status = SratAddGiccAffinity ((EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE *)TmpPtr);
+ ASSERT_EFI_ERROR (Status);
+
+ TmpPtr += GetNumberOfActiveCores () * sizeof (EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE);
+ SratAddGicItsAffinity ((VOID *)(UINT64)TmpPtr);
+ SratTablePointer->Header.Length = Size;
+
+ AcpiUpdateChecksum ((UINT8 *)SratTablePointer, SratTablePointer->Header.Length);
+
+ Status = AcpiTableProtocol->InstallAcpiTable (
+ AcpiTableProtocol,
+ (VOID *)SratTablePointer,
+ SratTablePointer->Header.Length,
+ &SratTableKey
+ );
+ FreePool ((VOID *)SratTablePointer);
+
+ return Status;
+}
diff --git a/Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi b/Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi
new file mode 100644
index 000000000000..969cece130ad
--- /dev/null
+++ b/Platform/Ampere/JadePkg/AcpiTables/CPU-S0.asi
@@ -0,0 +1,5639 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Device(C000) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x0)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x000, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x004, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x008, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x00c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x010, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x014, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x050, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x054, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x058, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 0, 0xFD, 2}
+ }) // Domain 0
+}
+
+Device(C001) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x080, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x084, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x088, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x08c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x090, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x094, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x0d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x0d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x0d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 1, 0xFD, 2}
+ }) // Domain 1
+}
+
+Device(C002) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x100)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x100, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x104, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x108, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x10c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x114, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x12c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x134, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x13c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x150, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x154, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x158, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 2, 0xFD, 2}
+ }) // Domain 2
+}
+
+Device(C003) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x101)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x180, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x184, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x188, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x18c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x190, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x194, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 3, 0xFD, 2}
+ }) // Domain 3
+}
+
+Device(C004) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x200)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x200, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x204, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x208, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x20c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x210, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x214, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x22c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x234, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x23c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x250, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x254, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x258, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 4, 0xFD, 2}
+ }) // Domain 4
+}
+
+Device(C005) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x201)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x280, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x284, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x288, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x28c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x290, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x294, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 5, 0xFD, 2}
+ }) // Domain 5
+}
+
+Device(C006) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x300)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x300, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x304, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x308, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x30c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x310, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x314, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x32c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x334, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x33c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x350, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x354, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x358, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 6, 0xFD, 2}
+ }) // Domain 6
+}
+
+Device(C007) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x301)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x380, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x384, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x388, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x38c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x390, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x394, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 7, 0xFD, 2}
+ }) // Domain 7
+}
+
+Device(C008) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x400)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x400, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x404, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x408, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x40c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x410, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x414, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x42c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x434, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x43c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x450, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x454, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x458, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 8, 0xFD, 2}
+ }) // Domain 8
+}
+
+Device(C009) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x401)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x480, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x484, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x488, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x48c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x490, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x494, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x4ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x4b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x4bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x4d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x4d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x4d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 9, 0xFD, 2}
+ }) // Domain 9
+}
+
+Device(C010) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x500)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x500, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x504, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x508, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x50c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x510, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x514, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x52c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x534, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x53c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x550, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x554, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x558, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 10, 0xFD, 2}
+ }) // Domain 10
+}
+
+Device(C011) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x501)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x580, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x584, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x588, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x58c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x590, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x594, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x5ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x5b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x5bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x5d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x5d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x5d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 11, 0xFD, 2}
+ }) // Domain 11
+}
+
+Device(C012) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x600)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x600, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x604, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x608, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x60c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x610, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x614, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x62c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x634, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x63c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x650, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x654, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x658, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 12, 0xFD, 2}
+ }) // Domain 12
+}
+
+Device(C013) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x601)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x680, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x684, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x688, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x68c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x690, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x694, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x6ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x6b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x6bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x6d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x6d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x6d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 13, 0xFD, 2}
+ }) // Domain 13
+}
+
+Device(C014) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x700)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x700, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x704, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x708, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x70c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x710, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x714, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x72c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x734, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x73c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x750, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x754, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x758, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 14, 0xFD, 2}
+ }) // Domain 14
+}
+
+Device(C015) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x701)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x780, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x784, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x788, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x78c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x790, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x794, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x7ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x7b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x7bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x7d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x7d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x7d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 15, 0xFD, 2}
+ }) // Domain 15
+}
+
+Device(C016) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x800)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x800, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x804, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x808, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x80c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x810, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x814, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x82c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x834, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x83c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x850, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x854, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x858, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 16, 0xFD, 2}
+ }) // Domain 16
+}
+
+Device(C017) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x801)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x880, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x884, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x888, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x88c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x890, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x894, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x8ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x8b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x8bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x8d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x8d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x8d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 17, 0xFD, 2}
+ }) // Domain 17
+}
+
+Device(C018) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x900)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x900, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x904, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x908, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x90c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x910, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x914, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x92c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x934, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x93c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x950, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x954, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x958, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 18, 0xFD, 2}
+ }) // Domain 18
+}
+
+Device(C019) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x901)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x980, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x984, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x988, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x98c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x990, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x994, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x9ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x9b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x9bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x9d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x9d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x9d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 19, 0xFD, 2}
+ }) // Domain 19
+}
+
+Device(C020) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xa00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xa2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xa34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 20, 0xFD, 2}
+ }) // Domain 20
+}
+
+Device(C021) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xa01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xa94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xaac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xab4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xabc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xad0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xad4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xad8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 21, 0xFD, 2}
+ }) // Domain 21
+}
+
+Device(C022) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xb00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xb2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xb34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 22, 0xFD, 2}
+ }) // Domain 22
+}
+
+Device(C023) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xb01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xb94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xbac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xbb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xbbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xbd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xbd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xbd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 23, 0xFD, 2}
+ }) // Domain 23
+}
+
+Device(C024) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xc00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xc2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xc34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 24, 0xFD, 2}
+ }) // Domain 24
+}
+
+Device(C025) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xc01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xc94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xcac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xcb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xcbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xcd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xcd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xcd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 25, 0xFD, 2}
+ }) // Domain 25
+}
+
+Device(C026) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xd00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xd2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xd34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 26, 0xFD, 2}
+ }) // Domain 26
+}
+
+Device(C027) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xd01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xd94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xdac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xdb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xdbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xdd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xdd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xdd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 27, 0xFD, 2}
+ }) // Domain 27
+}
+
+Device(C028) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xe00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xe2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xe34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 28, 0xFD, 2}
+ }) // Domain 28
+}
+
+Device(C029) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xe01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xe94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xeac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xeb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xebc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xed0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xed4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xed8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 29, 0xFD, 2}
+ }) // Domain 29
+}
+
+Device(C030) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xf00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xf2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xf34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 30, 0xFD, 2}
+ }) // Domain 30
+}
+
+Device(C031) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0xf01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xf94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0xfac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0xfb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xfbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xfd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xfd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0xfd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 31, 0xFD, 2}
+ }) // Domain 31
+}
+
+Device(C032) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1000)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1000, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1004, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1008, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x100c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1010, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1014, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x102c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1034, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x103c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1050, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1054, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1058, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 32, 0xFD, 2}
+ }) // Domain 32
+}
+
+Device(C033) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1001)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1080, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1084, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1088, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x108c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1090, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1094, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x10ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x10b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x10bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x10d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x10d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x10d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 33, 0xFD, 2}
+ }) // Domain 33
+}
+
+Device(C034) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1100)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1100, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1104, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1108, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x110c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1110, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1114, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x112c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1134, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x113c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1150, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1154, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1158, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 34, 0xFD, 2}
+ }) // Domain 34
+}
+
+Device(C035) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1101)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1180, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1184, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1188, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x118c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1190, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1194, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x11ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x11b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x11bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x11d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x11d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x11d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 35, 0xFD, 2}
+ }) // Domain 35
+}
+
+Device(C036) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1200)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1200, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1204, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1208, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x120c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1210, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1214, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x122c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1234, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x123c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1250, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1254, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1258, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 36, 0xFD, 2}
+ }) // Domain 36
+}
+
+Device(C037) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1201)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1280, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1284, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1288, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x128c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1290, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1294, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x12ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x12b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x12bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x12d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x12d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x12d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 37, 0xFD, 2}
+ }) // Domain 37
+}
+
+Device(C038) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1300)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1300, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1304, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1308, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x130c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1310, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1314, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x132c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1334, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x133c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1350, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1354, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1358, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 38, 0xFD, 2}
+ }) // Domain 38
+}
+
+Device(C039) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1301)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1380, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1384, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1388, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x138c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1390, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1394, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x13ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x13b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x13bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x13d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x13d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x13d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 39, 0xFD, 2}
+ }) // Domain 39
+}
+
+Device(C040) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1400)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1400, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1404, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1408, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x140c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1410, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1414, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x142c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1434, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x143c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1450, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1454, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1458, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 40, 0xFD, 2}
+ }) // Domain 40
+}
+
+Device(C041) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1401)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1480, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1484, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1488, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x148c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1490, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1494, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x14ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x14b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x14bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x14d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x14d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x14d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 41, 0xFD, 2}
+ }) // Domain 41
+}
+
+Device(C042) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1500)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1500, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1504, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1508, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x150c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1510, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1514, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x152c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1534, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x153c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1550, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1554, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1558, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 42, 0xFD, 2}
+ }) // Domain 42
+}
+
+Device(C043) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1501)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1580, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1584, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1588, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x158c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1590, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1594, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x15ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x15b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x15bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x15d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x15d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x15d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 43, 0xFD, 2}
+ }) // Domain 43
+}
+
+Device(C044) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1600)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1600, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1604, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1608, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x160c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1610, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1614, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x162c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1634, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x163c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1650, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1654, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1658, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 44, 0xFD, 2}
+ }) // Domain 44
+}
+
+Device(C045) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1601)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1680, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1684, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1688, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x168c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1690, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1694, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x16ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x16b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x16bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x16d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x16d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x16d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 45, 0xFD, 2}
+ }) // Domain 45
+}
+
+Device(C046) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1700)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1700, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1704, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1708, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x170c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1710, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1714, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x172c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1734, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x173c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1750, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1754, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1758, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 46, 0xFD, 2}
+ }) // Domain 46
+}
+
+Device(C047) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1701)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1780, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1784, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1788, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x178c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1790, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1794, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x17ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x17b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x17bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x17d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x17d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x17d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 47, 0xFD, 2}
+ }) // Domain 47
+}
+
+Device(C048) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1800)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1800, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1804, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1808, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x180c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1810, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1814, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x182c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1834, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x183c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1850, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1854, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1858, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 48, 0xFD, 2}
+ }) // Domain 48
+}
+
+Device(C049) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1801)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1880, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1884, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1888, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x188c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1890, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1894, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x18ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x18b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x18bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x18d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x18d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x18d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 49, 0xFD, 2}
+ }) // Domain 49
+}
+
+Device(C050) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1900)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1900, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1904, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1908, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x190c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1910, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1914, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x192c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1934, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x193c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1950, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1954, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1958, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 50, 0xFD, 2}
+ }) // Domain 50
+}
+
+Device(C051) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1901)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1980, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1984, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1988, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x198c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1990, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1994, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x19ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x19b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x19bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x19d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x19d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x19d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 51, 0xFD, 2}
+ }) // Domain 51
+}
+
+Device(C052) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1a00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1a2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1a34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 52, 0xFD, 2}
+ }) // Domain 52
+}
+
+Device(C053) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1a01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1a94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1aac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1ab4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1abc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ad0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ad4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ad8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 53, 0xFD, 2}
+ }) // Domain 53
+}
+
+Device(C054) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1b00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1b2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1b34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 54, 0xFD, 2}
+ }) // Domain 54
+}
+
+Device(C055) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1b01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1b94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1bac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1bb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1bbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1bd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1bd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1bd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 55, 0xFD, 2}
+ }) // Domain 5
+}
+
+Device(C056) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1c00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1c2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1c34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 56, 0xFD, 2}
+ }) // Domain 56
+}
+
+Device(C057) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1c01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1c94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1cac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1cb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1cbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1cd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1cd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1cd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 57, 0xFD, 2}
+ }) // Domain 57
+}
+
+Device(C058) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1d00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1d2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1d34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 58, 0xFD, 2}
+ }) // Domain 58
+}
+
+Device(C059) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1d01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1d94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1dac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1db4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1dbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1dd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1dd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1dd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 59, 0xFD, 2}
+ }) // Domain 59
+}
+
+Device(C060) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1e00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1e2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1e34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 60, 0xFD, 2}
+ }) // Domain 60
+}
+
+Device(C061) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1e01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1e94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1eac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1eb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ebc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ed0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ed4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1ed8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 61, 0xFD, 2}
+ }) // Domain 61
+}
+
+Device(C062) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1f00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1f2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1f34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 62, 0xFD, 2}
+ }) // Domain 62
+}
+
+Device(C063) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x1f01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1f94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1fac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x1fb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1fbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1fd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1fd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x1fd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 63, 0xFD, 2}
+ }) // Domain 63
+}
+
+Device(C064) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2000)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2000, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2004, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2008, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x200c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2010, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2014, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x202c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2034, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x203c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2050, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2054, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2058, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 64, 0xFD, 2}
+ }) // Domain 64
+}
+
+Device(C065) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2001)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2080, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2084, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2088, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x208c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2090, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2094, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x20ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x20b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x20bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x20d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x20d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x20d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 65, 0xFD, 2}
+ }) // Domain 65
+}
+
+Device(C066) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2100)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2100, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2104, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2108, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x210c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2110, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2114, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x212c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2134, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x213c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2150, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2154, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2158, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 66, 0xFD, 2}
+ }) // Domain 66
+}
+
+Device(C067) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2101)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2180, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2184, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2188, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x218c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2190, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2194, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x21ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x21b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x21bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x21d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x21d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x21d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 67, 0xFD, 2}
+ }) // Domain 67
+}
+
+Device(C068) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2200)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2200, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2204, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2208, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x220c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2210, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2214, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x222c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2234, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x223c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2250, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2254, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2258, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 68, 0xFD, 2}
+ }) // Domain 68
+}
+
+Device(C069) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2201)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2280, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2284, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2288, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x228c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2290, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2294, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x22ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x22b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x22bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x22d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x22d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x22d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 69, 0xFD, 2}
+ }) // Domain 69
+}
+
+Device(C070) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2300)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2300, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2304, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2308, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x230c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2310, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2314, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x232c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2334, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x233c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2350, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2354, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2358, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 70, 0xFD, 2}
+ }) // Domain 70
+}
+
+Device(C071) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2301)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2380, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2384, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2388, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x238c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2390, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2394, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x23ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x23b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x23bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x23d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x23d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x23d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 71, 0xFD, 2}
+ }) // Domain 71
+}
+
+Device(C072) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2400)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2400, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2404, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2408, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x240c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2410, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2414, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x242c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2434, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x243c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2450, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2454, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2458, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 72, 0xFD, 2}
+ }) // Domain 72
+}
+
+Device(C073) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2401)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2480, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2484, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2488, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x248c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2490, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2494, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x24ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x24b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x24bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x24d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x24d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x24d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 73, 0xFD, 2}
+ }) // Domain 73
+}
+
+Device(C074) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2500)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2500, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2504, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2508, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x250c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2510, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2514, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x252c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2534, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x253c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2550, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2554, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2558, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 74, 0xFD, 2}
+ }) // Domain 74
+}
+
+Device(C075) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2501)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2580, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2584, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2588, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x258c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2590, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2594, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x25ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x25b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x25bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x25d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x25d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x25d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 75, 0xFD, 2}
+ }) // Domain 75
+}
+
+Device(C076) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2600)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2600, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2604, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2608, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x260c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2610, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2614, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x262c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2634, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x263c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2650, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2654, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2658, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 76, 0xFD, 2}
+ }) // Domain 76
+}
+
+Device(C077) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2601)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2680, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2684, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2688, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x268c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2690, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2694, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x26ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x26b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x26bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x26d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x26d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x26d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 77, 0xFD, 2}
+ }) // Domain 77
+}
+
+Device(C078) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2700)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2700, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2704, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2708, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x270c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2710, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2714, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x272c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2734, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x273c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2750, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2754, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2758, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 78, 0xFD, 2}
+ }) // Domain 78
+}
+
+Device(C079) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2701)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2780, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2784, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2788, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x278c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2790, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2794, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x27ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x27b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x27bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x27d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x27d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x27d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 79, 0xFD, 2}
+ }) // Domain 79
+}
+
+Device(C080) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2800)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2800, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2804, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2808, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x280c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2810, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2814, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x282c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2834, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x283c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2850, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2854, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2858, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 80, 0xFD, 2}
+ }) // Domain 80
+}
+
+Device(C081) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2801)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2880, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2884, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2888, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x288c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2890, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2894, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x28ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x28b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x28bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x28d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x28d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x28d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 81, 0xFD, 2}
+ }) // Domain 81
+}
+
+Device(C082) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2900)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2900, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2904, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2908, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x290c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2910, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2914, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x292c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2934, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x293c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2950, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2954, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2958, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 82, 0xFD, 2}
+ }) // Domain 82
+}
+
+Device(C083) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2901)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2980, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2984, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2988, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x298c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2990, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2994, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x29ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x29b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x29bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x29d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x29d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x29d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 83, 0xFD, 2}
+ }) // Domain 83
+}
+
+Device(C084) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2a00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2a2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2a34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 84, 0xFD, 2}
+ }) // Domain 84
+}
+
+Device(C085) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2a01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2a94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2aac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2ab4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2abc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ad0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ad4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ad8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 85, 0xFD, 2}
+ }) // Domain 85
+}
+
+Device(C086) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2b00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2b2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2b34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 86, 0xFD, 2}
+ }) // Domain 86
+}
+
+Device(C087) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2b01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2b94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2bac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2bb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2bbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2bd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2bd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2bd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 87, 0xFD, 2}
+ }) // Domain 87
+}
+
+Device(C088) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2c00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2c2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2c34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 88, 0xFD, 2}
+ }) // Domain 88
+}
+
+Device(C089) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2c01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2c94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2cac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2cb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2cbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2cd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2cd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2cd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 89, 0xFD, 2}
+ }) // Domain 89
+}
+
+Device(C090) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2d00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2d2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2d34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 90, 0xFD, 2}
+ }) // Domain 90
+}
+
+Device(C091) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2d01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2d94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2dac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2db4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2dbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2dd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2dd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2dd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 91, 0xFD, 2}
+ }) // Domain 91
+}
+
+Device(C092) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2e00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2e2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2e34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 92, 0xFD, 2}
+ }) // Domain 92
+}
+
+Device(C093) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2e01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2e94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2eac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2eb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ebc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ed0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ed4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2ed8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 93, 0xFD, 2}
+ }) // Domain 93
+}
+
+Device(C094) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2f00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2f2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2f34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 94, 0xFD, 2}
+ }) // Domain 94
+}
+
+Device(C095) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x2f01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2f94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2fac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x2fb4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2fbc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2fd0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2fd4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x2fd8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 95, 0xFD, 2}
+ }) // Domain 95
+}
+
+Device(C096) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3000)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3000, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3004, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3008, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x300c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3010, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3014, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x302c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3034, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x303c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3050, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3054, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3058, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 96, 0xFD, 2}
+ }) // Domain 96
+}
+
+Device(C097) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3001)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3080, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3084, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3088, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x308c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3090, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3094, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x30ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x30b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x30bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x30d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x30d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x30d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 97, 0xFD, 2}
+ }) // Domain 97
+}
+
+Device(C098) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3100)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3100, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3104, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3108, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x310c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3110, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3114, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x312c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3134, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x313c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3150, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3154, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3158, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 98, 0xFD, 2}
+ }) // Domain 98
+}
+
+Device(C099) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3101)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3180, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3184, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3188, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x318c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3190, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3194, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x31ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x31b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x31bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x31d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x31d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x31d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 99, 0xFD, 2}
+ }) // Domain 99
+}
+
+Device(C100) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3200)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3200, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3204, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3208, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x320c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3210, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3214, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x322c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3234, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x323c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3250, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3254, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3258, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 100, 0xFD, 2}
+ }) // Domain 100
+}
+
+Device(C101) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3201)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3280, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3284, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3288, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x328c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3290, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3294, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x32ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x32b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x32bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x32d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x32d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x32d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 101, 0xFD, 2}
+ }) // Domain 101
+}
+
+Device(C102) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3300)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3300, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3304, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3308, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x330c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3310, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3314, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x332c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3334, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x333c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3350, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3354, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3358, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 102, 0xFD, 2}
+ }) // Domain 102
+}
+
+Device(C103) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3301)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3380, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3384, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3388, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x338c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3390, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3394, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x33ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x33b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x33bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x33d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x33d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x33d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 103, 0xFD, 2}
+ }) // Domain 103
+}
+
+Device(C104) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3400)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3400, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3404, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3408, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x340c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3410, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3414, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x342c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3434, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x343c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3450, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3454, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3458, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 104, 0xFD, 2}
+ }) // Domain 104
+}
+
+Device(C105) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3401)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3480, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3484, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3488, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x348c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3490, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3494, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x34ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x34b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x34bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x34d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x34d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x34d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 105, 0xFD, 2}
+ }) // Domain 105
+}
+
+Device(C106) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3500)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3500, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3504, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3508, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x350c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3510, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3514, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x352c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3534, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x353c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3550, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3554, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3558, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 106, 0xFD, 2}
+ }) // Domain 106
+}
+
+Device(C107) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3501)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3580, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3584, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3588, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x358c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3590, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3594, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x35ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x35b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x35bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x35d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x35d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x35d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 107, 0xFD, 2}
+ }) // Domain 107
+}
+
+Device(C108) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3600)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3600, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3604, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3608, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x360c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3610, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3614, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x362c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3634, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x363c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3650, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3654, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3658, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 108, 0xFD, 2}
+ }) // Domain 108
+}
+
+Device(C109) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3601)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3680, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3684, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3688, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x368c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3690, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3694, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x36ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x36b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x36bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x36d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x36d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x36d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 109, 0xFD, 2}
+ }) // Domain 109
+}
+
+Device(C110) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3700)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3700, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3704, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3708, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x370c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3710, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3714, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x372c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3734, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x373c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3750, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3754, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3758, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 110, 0xFD, 2}
+ }) // Domain 110
+}
+
+Device(C111) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3701)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3780, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3784, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3788, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x378c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3790, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3794, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x37ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x37b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x37bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x37d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x37d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x37d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 111, 0xFD, 2}
+ }) // Domain 111
+}
+
+Device(C112) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3800)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3800, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3804, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3808, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x380c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3810, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3814, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x382c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3834, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x383c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3850, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3854, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3858, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 112, 0xFD, 2}
+ }) // Domain 112
+}
+
+Device(C113) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3801)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3880, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3884, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3888, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x388c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3890, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3894, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x38ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x38b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x38bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x38d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x38d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x38d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 113, 0xFD, 2}
+ }) // Domain 113
+}
+
+Device(C114) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3900)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3900, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3904, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3908, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x390c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3910, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3914, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x392c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3934, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x393c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3950, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3954, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3958, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 114, 0xFD, 2}
+ }) // Domain 114
+}
+
+Device(C115) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3901)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3980, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3984, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3988, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x398c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3990, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3994, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x39ac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x39b4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x39bc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x39d0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x39d4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x39d8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package(){
+ Package() {5, 0, 115, 0xFD, 2}
+ }) // Domain 115
+}
+
+Device(C116) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3a00)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a00, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a04, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a08, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a0c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a10, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a14, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3a2c, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3a34, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a3c, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a50, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a54, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a58, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE, 0x1)) {
+ Method (_CPC, 0, NotSerialized) {
+ return(PCPC)
+ }
+ }
+ //Performance State dependency
+ Name(_PSD, Package() {
+ Package() {5, 0, 116, 0xFD, 2}
+ }) // Domain 116
+}
+
+Device(C117) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0x3a01)
+
+ Method (_LPI, 0, NotSerialized) {
+ return(PLPI)
+ }
+
+ Name(PCPC, Package() {
+ 23, // NumEntries
+ 3, // Revision
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a80, 2)}, // Highest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a84, 2)}, // Nominal Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a88, 2)}, // Lowest Nonlinear Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a8c, 2)}, // Lowest Performance
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a90, 2)}, // Guaranteed Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3a94, 2)}, // Desired Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Reduction Tolerance Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3aac, 2)}, // Reference Counter Register
+ ResourceTemplate(){Register(PCC, 64, 0, 0x3ab4, 2)}, // Delivered Counter Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3abc, 2)}, // Performance Limited Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Enable Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
+ ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3ad0, 2)}, // Reference Performance Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3ad4, 2)}, // Lowest Frequency Register
+ ResourceTemplate(){Register(PCC, 32, 0, 0x3ad8, 2)}, // Nominal Frequency Register
+ })
+ If (LEqual(CPCE,