Date   

[edk2-platforms][PATCH v1 1/1] MinPlatformPkg/AcpiTables: Update structures for ACPI 6.3

Michael Kubacki
 

From: Daniel Maddy <danmad@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3535

Updates ACPI table structures in MinPlatformPkg for ACPI 6.3.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Daniel Maddy <danmad@microsoft.com>
Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 203 +++++=
+++++----------
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c | 11 +-
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c | 74 ++++-=
--
3 files changed, 150 insertions(+), 138 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c=
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2fd..5e3c4c0672f9 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -2,6 +2,7 @@
ACPI Platform Driver
=20
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -13,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
=20
typedef struct {
- UINT32 AcpiProcessorId;
+ UINT32 AcpiProcessorUid;
UINT32 ApicId;
UINT32 Flags;
UINT32 SwProcApicId;
@@ -27,9 +28,9 @@ typedef struct {
// Define Union of IO APIC & Local APIC structure;
//
typedef union {
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
- EFI_ACPI_4_0_IO_APIC_STRUCTURE AcpiIoApic;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE AcpiIoApic;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
struct {
UINT8 Type;
UINT8 Length;
@@ -38,9 +39,9 @@ typedef union {
=20
#pragma pack()
=20
-extern EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs;
-extern EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt;
-extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet;
+extern EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs;
+extern EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt;
+extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet;
extern EFI_ACPI_WSMT_TABLE Wsmt;
=20
VOID *mLocalTable[] =3D {
@@ -217,7 +218,7 @@ DebugDisplayReOrderTable(
DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\=
n"));
for (Index=3D0; Index<MAX_CPU_NUM; Index++) {
DEBUG ((EFI_D_ERROR, " %02d 0x%02X 0x%02X %d 0x=
%02X %d\n",
- Index, mCpuApicIdOrderTable[Index].AcpiProces=
sorId,
+ Index, mCpuApicIdOrderTable[Index].AcpiProces=
sorUid,
mCpuApicIdOrderTable[Index].ApicId,
mCpuApicIdOrderTable[Index].Flags,
mCpuApicIdOrderTable[Index].SwProcApicId,
@@ -232,31 +233,31 @@ AppendCpuMapTableEntry (
)
{
EFI_STATUS Status;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE *LocalApicPtr;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE *LocalApicPtr;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
UINT8 Type;
=20
Status =3D EFI_SUCCESS;
Type =3D ((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiApicCommon.Type;
- LocalApicPtr =3D (EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE *)(&((AC=
PI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
- LocalX2ApicPtr =3D (EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)(&=
((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
+ LocalApicPtr =3D (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE *)(&((AC=
PI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
+ LocalX2ApicPtr =3D (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)(&=
((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
=20
- if(Type =3D=3D EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC) {
+ if(Type =3D=3D EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
if(!mX2ApicEnabled) {
- LocalApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].Flags;
- LocalApicPtr->ApicId =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].ApicId;
- LocalApicPtr->AcpiProcessorId =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].AcpiProcessorId;
+ LocalApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].Flags;
+ LocalApicPtr->ApicId =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].ApicId;
+ LocalApicPtr->AcpiProcessorUid =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].AcpiProcessorUid;
} else {
- LocalApicPtr->Flags =3D 0;
- LocalApicPtr->ApicId =3D 0xFF;
- LocalApicPtr->AcpiProcessorId =3D (UINT8)0xFF;
+ LocalApicPtr->Flags =3D 0;
+ LocalApicPtr->ApicId =3D 0xFF;
+ LocalApicPtr->AcpiProcessorUid =3D (UINT8)0xFF;
Status =3D EFI_UNSUPPORTED;
}
- } else if(Type =3D=3D EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC) {
+ } else if(Type =3D=3D EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
if(mX2ApicEnabled) {
LocalX2ApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[L=
ocalApicCounter].Flags;
LocalX2ApicPtr->X2ApicId =3D mCpuApicIdOrderTable[LocalApi=
cCounter].ApicId;
- LocalX2ApicPtr->AcpiProcessorUid =3D mCpuApicIdOrderTable[LocalApi=
cCounter].AcpiProcessorId;
+ LocalX2ApicPtr->AcpiProcessorUid =3D mCpuApicIdOrderTable[LocalApi=
cCounter].AcpiProcessorUid;
} else {
LocalX2ApicPtr->Flags =3D 0;
LocalX2ApicPtr->X2ApicId =3D (UINT32)-1;
@@ -311,8 +312,8 @@ SortCpuLocalApicInTable (
CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId=
;
CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROC=
ESSOR_ENABLED_BIT) !=3D 0);
CpuIdMapPtr->SocketNum =3D (UINT32)ProcessorInfoBuffer.Location.=
Package;
- CpuIdMapPtr->AcpiProcessorId =3D (CpuIdMapPtr->SocketNum * Fixed=
PcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + Get=
IndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
- CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.Loca=
tion.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.Processor=
Id) & CoreThreadMask));
+ CpuIdMapPtr->AcpiProcessorUid =3D (CpuIdMapPtr->SocketNum * Fixe=
dPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + Ge=
tIndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
+ CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.=
Location.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.Proce=
ssorId) & CoreThreadMask));
if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it st=
arts from base 0 and contiguous
//may not necessory!!!!!
}
@@ -321,18 +322,18 @@ SortCpuLocalApicInTable (
if (CpuIdMapPtr->Flags =3D=3D 1) {
=20
if(mForceX2ApicId) {
- CpuIdMapPtr->SocketNum &=3D 0x7;
- CpuIdMapPtr->AcpiProcessorId &=3D 0xFF; //keep lower 8bit du=
e to use Proc obj in dsdt
- CpuIdMapPtr->SwProcApicId &=3D 0xFF;
+ CpuIdMapPtr->SocketNum &=3D 0x7;
+ CpuIdMapPtr->AcpiProcessorUid &=3D 0xFF; //keep lower 8bit d=
ue to use Proc obj in dsdt
+ CpuIdMapPtr->SwProcApicId &=3D 0xFF;
}
}
} else { //not enabled
- CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[In=
dex];
- CpuIdMapPtr->ApicId =3D (UINT32)-1;
- CpuIdMapPtr->Flags =3D 0;
- CpuIdMapPtr->AcpiProcessorId =3D (UINT32)-1;
- CpuIdMapPtr->SwProcApicId =3D (UINT32)-1;
- CpuIdMapPtr->SocketNum =3D (UINT32)-1;
+ CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuA=
picIdOrderTable[Index];
+ CpuIdMapPtr->ApicId =3D (UINT32)-1;
+ CpuIdMapPtr->Flags =3D 0;
+ CpuIdMapPtr->AcpiProcessorUid =3D (UINT32)-1;
+ CpuIdMapPtr->SwProcApicId =3D (UINT32)-1;
+ CpuIdMapPtr->SocketNum =3D (UINT32)-1;
} //end if PROC ENABLE
} //end for CurrentProcessor
=20
@@ -366,9 +367,9 @@ SortCpuLocalApicInTable (
mCpuApicIdOrderTable[Index].SwProcApicId =3D mCpuApicIdOrderTable[=
0].SwProcApicId;
mCpuApicIdOrderTable[0].SwProcApicId =3D TempVal;
//swap AcpiProcId
- TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[Index].AcpiProcessorId =3D mCpuApicIdOrderTab=
le[0].AcpiProcessorId;
- mCpuApicIdOrderTable[0].AcpiProcessorId =3D TempVal;
+ TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorUid;
+ mCpuApicIdOrderTable[Index].AcpiProcessorUid =3D mCpuApicIdOrderTa=
ble[0].AcpiProcessorUid;
+ mCpuApicIdOrderTable[0].AcpiProcessorUid =3D TempVal;
=20
}
=20
@@ -377,23 +378,23 @@ SortCpuLocalApicInTable (
=20
if(mCpuApicIdOrderTable[CurrProcessor].Flags =3D=3D 0) {
//make sure disabled entry has ProcId set to FFs
- mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D (UINT32)=
-1;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32=
)-1;
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D (UINT32=
)-1;
+ mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32=
)-1;
=20
for(Index =3D CurrProcessor+1; Index < MAX_CPU_NUM; Index++) {
if(mCpuApicIdOrderTable[Index].Flags =3D=3D 1) {
//move enabled entry up
- mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1;
- mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCpuApicIdOrd=
erTable[Index].ApicId;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D mCpu=
ApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCpuApi=
cIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCpuApicId=
OrderTable[Index].SocketNum;
+ mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1;
+ mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCp=
uApicIdOrderTable[Index].ApicId;
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D mCp=
uApicIdOrderTable[Index].AcpiProcessorUid;
+ mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCp=
uApicIdOrderTable[Index].SwProcApicId;
+ mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCp=
uApicIdOrderTable[Index].SocketNum;
//disable moved entry
- mCpuApicIdOrderTable[Index].Flags =3D 0;
- mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1;
- mCpuApicIdOrderTable[Index].AcpiProcessorId =3D (UINT32)-1;
- mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].Flags =3D 0;
+ mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].AcpiProcessorUid =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1;
break;
}
}
@@ -422,17 +423,17 @@ typedef struct {
} STRUCTURE_HEADER;
=20
STRUCTURE_HEADER mMadtStructureTable[] =3D {
- {EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_APIC_STRUCTURE)},
- {EFI_ACPI_4_0_IO_APIC, sizeof (EFI_ACPI_4_0_IO_A=
PIC_STRUCTURE)},
- {EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE, sizeof (EFI_ACPI_4_0_INTE=
RRUPT_SOURCE_OVERRIDE_STRUCTURE)},
- {EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE, sizeof (EFI_ACPI_4_0_NON_=
MASKABLE_INTERRUPT_SOURCE_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_APIC_NMI, sizeof (EFI_ACPI_4_0_LOCA=
L_APIC_NMI_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE, sizeof (EFI_ACPI_4_0_LOCA=
L_APIC_ADDRESS_OVERRIDE_STRUCTURE)},
- {EFI_ACPI_4_0_IO_SAPIC, sizeof (EFI_ACPI_4_0_IO_S=
APIC_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_SAPIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_SAPIC_STRUCTURE)},
- {EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES, sizeof (EFI_ACPI_4_0_PLAT=
FORM_INTERRUPT_SOURCES_STRUCTURE)},
- {EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_X2APIC_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_X2APIC_NMI, sizeof (EFI_ACPI_4_0_LOCA=
L_X2APIC_NMI_STRUCTURE)}
+ {EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_IO_APIC, sizeof (EFI_ACPI_6_3_IO_A=
PIC_STRUCTURE)},
+ {EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, sizeof (EFI_ACPI_6_3_INTE=
RRUPT_SOURCE_OVERRIDE_STRUCTURE)},
+ {EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE, sizeof (EFI_ACPI_6_3_NON_=
MASKABLE_INTERRUPT_SOURCE_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_APIC_NMI, sizeof (EFI_ACPI_6_3_LOCA=
L_APIC_NMI_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE, sizeof (EFI_ACPI_6_3_LOCA=
L_APIC_ADDRESS_OVERRIDE_STRUCTURE)},
+ {EFI_ACPI_6_3_IO_SAPIC, sizeof (EFI_ACPI_6_3_IO_S=
APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_SAPIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_SAPIC_STRUCTURE)},
+ {EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES, sizeof (EFI_ACPI_6_3_PLAT=
FORM_INTERRUPT_SOURCES_STRUCTURE)},
+ {EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_X2APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_X2APIC_NMI, sizeof (EFI_ACPI_6_3_LOCA=
L_X2APIC_NMI_STRUCTURE)}
};
=20
/**
@@ -591,7 +592,7 @@ InitializeHeader (
**/
EFI_STATUS
InitializeMadtHeader (
- IN OUT EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtHeader
+ IN OUT EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtHeader
)
{
EFI_STATUS Status;
@@ -603,8 +604,8 @@ InitializeMadtHeader (
=20
Status =3D InitializeHeader (
&MadtHeader->Header,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
0
);
if (EFI_ERROR (Status)) {
@@ -612,7 +613,7 @@ InitializeMadtHeader (
}
=20
MadtHeader->LocalApicAddress =3D PcdGet32(PcdLocalApicAddress);
- MadtHeader->Flags =3D EFI_ACPI_4_0_PCAT_COMPAT;
+ MadtHeader->Flags =3D EFI_ACPI_6_3_PCAT_COMPAT;
=20
return EFI_SUCCESS;
}
@@ -649,7 +650,7 @@ CopyStructure (
//
// Initialize the number of table entries and the table based on the t=
able header passed in.
//
- if (Header->Signature =3D=3D EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TA=
BLE_SIGNATURE) {
+ if (Header->Signature =3D=3D EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TA=
BLE_SIGNATURE) {
TableNumEntries =3D sizeof (mMadtStructureTable) / sizeof (STRUCTURE=
_HEADER);
StructureTable =3D mMadtStructureTable;
} else {
@@ -759,7 +760,7 @@ BuildAcpiTable (
return EFI_INVALID_PARAMETER;
}
=20
- if (AcpiHeader->Signature !=3D EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_=
TABLE_SIGNATURE) {
+ if (AcpiHeader->Signature !=3D EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_=
TABLE_SIGNATURE) {
DEBUG ((
DEBUG_ERROR,
"MADT header signature is expected, actually 0x%08x\n",
@@ -850,15 +851,15 @@ InstallMadtFromScratch (
{
EFI_STATUS Status;
UINTN Index;
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *NewMadtTable;
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *NewMadtTable;
UINTN TableHandle;
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER MadtTableHeader;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE ProcLocalApicStruc=
t;
- EFI_ACPI_4_0_IO_APIC_STRUCTURE IoApicStruct;
- EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE IntSrcOverrideStru=
ct;
- EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE LocalApciNmiStruct=
;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE ProcLocalX2ApicStr=
uct;
- EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE LocalX2ApicNmiStru=
ct;
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER MadtTableHeader;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE ProcLocalApicStruc=
t;
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApicStruct;
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE IntSrcOverrideStru=
ct;
+ EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE LocalApciNmiStruct=
;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE ProcLocalX2ApicStr=
uct;
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE LocalX2ApicNmiStru=
ct;
STRUCTURE_HEADER **MadtStructs;
UINTN MaxMadtStructCount=
;
UINTN MadtStructsIndex;
@@ -915,11 +916,11 @@ InstallMadtFromScratch (
//
// Build Processor Local APIC Structures and Processor Local X2APIC St=
ructures
//
- ProcLocalApicStruct.Type =3D EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC;
- ProcLocalApicStruct.Length =3D sizeof (EFI_ACPI_4_0_PROCESSOR_LOCAL_AP=
IC_STRUCTURE);
+ ProcLocalApicStruct.Type =3D EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC;
+ ProcLocalApicStruct.Length =3D sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_AP=
IC_STRUCTURE);
=20
- ProcLocalX2ApicStruct.Type =3D EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC;
- ProcLocalX2ApicStruct.Length =3D sizeof (EFI_ACPI_4_0_PROCESSOR_LOCAL_=
X2APIC_STRUCTURE);
+ ProcLocalX2ApicStruct.Type =3D EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC;
+ ProcLocalX2ApicStruct.Length =3D sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_=
X2APIC_STRUCTURE);
ProcLocalX2ApicStruct.Reserved[0] =3D 0;
ProcLocalX2ApicStruct.Reserved[1] =3D 0;
=20
@@ -930,9 +931,9 @@ InstallMadtFromScratch (
// use a processor local x2APIC structure.
//
if (!mX2ApicEnabled && mCpuApicIdOrderTable[Index].ApicId < MAX_UINT=
8) {
- ProcLocalApicStruct.Flags =3D (UINT8) mCpuApicIdOrderTab=
le[Index].Flags;
- ProcLocalApicStruct.ApicId =3D (UINT8) mCpuApicIdOrderTab=
le[Index].ApicId;
- ProcLocalApicStruct.AcpiProcessorId =3D (UINT8) mCpuApicIdOrderTab=
le[Index].AcpiProcessorId;
+ ProcLocalApicStruct.Flags =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].Flags;
+ ProcLocalApicStruct.ApicId =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].ApicId;
+ ProcLocalApicStruct.AcpiProcessorUid =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].AcpiProcessorUid;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -943,7 +944,7 @@ InstallMadtFromScratch (
} else if (mCpuApicIdOrderTable[Index].ApicId !=3D 0xFFFFFFFF) {
ProcLocalX2ApicStruct.Flags =3D (UINT8) mCpuApicIdOrder=
Table[Index].Flags;
ProcLocalX2ApicStruct.X2ApicId =3D mCpuApicIdOrderTable[In=
dex].ApicId;
- ProcLocalX2ApicStruct.AcpiProcessorUid =3D mCpuApicIdOrderTable[In=
dex].AcpiProcessorId;
+ ProcLocalX2ApicStruct.AcpiProcessorUid =3D mCpuApicIdOrderTable[In=
dex].AcpiProcessorUid;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -961,8 +962,8 @@ InstallMadtFromScratch (
//
// Build I/O APIC Structures
//
- IoApicStruct.Type =3D EFI_ACPI_4_0_IO_APIC;
- IoApicStruct.Length =3D sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE);
+ IoApicStruct.Type =3D EFI_ACPI_6_3_IO_APIC;
+ IoApicStruct.Length =3D sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE);
IoApicStruct.Reserved =3D 0;
=20
PcIoApicEnable =3D PcdGet32(PcdPcIoApicEnable);
@@ -1008,8 +1009,8 @@ InstallMadtFromScratch (
//
// Build Interrupt Source Override Structures
//
- IntSrcOverrideStruct.Type =3D EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE;
- IntSrcOverrideStruct.Length =3D sizeof (EFI_ACPI_4_0_INTERRUPT_SOURCE_=
OVERRIDE_STRUCTURE);
+ IntSrcOverrideStruct.Type =3D EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE;
+ IntSrcOverrideStruct.Length =3D sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_=
OVERRIDE_STRUCTURE);
=20
//
// IRQ0=3D>IRQ2 Interrupt Source Override Structure
@@ -1052,11 +1053,11 @@ InstallMadtFromScratch (
//
// Build Local APIC NMI Structures
//
- LocalApciNmiStruct.Type =3D EFI_ACPI_4_0_LOCAL_APIC_NMI;
- LocalApciNmiStruct.Length =3D sizeof (EFI_ACPI_4_0_LOCAL_APIC_NMI_STRU=
CTURE);
- LocalApciNmiStruct.AcpiProcessorId =3D 0xFF; // Applies to all pr=
ocessors
- LocalApciNmiStruct.Flags =3D 0x0005; // Flags - Edge-tigg=
ered, Active High
- LocalApciNmiStruct.LocalApicLint =3D 0x1;
+ LocalApciNmiStruct.Type =3D EFI_ACPI_6_3_LOCAL_APIC_NMI;
+ LocalApciNmiStruct.Length =3D sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRU=
CTURE);
+ LocalApciNmiStruct.AcpiProcessorUid =3D 0xFF; // Applies to all p=
rocessors
+ LocalApciNmiStruct.Flags =3D 0x0005; // Flags - Edge-tig=
gered, Active High
+ LocalApciNmiStruct.LocalApicLint =3D 0x1;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -1073,8 +1074,8 @@ InstallMadtFromScratch (
// Build Local x2APIC NMI Structure
//
if (mX2ApicEnabled) {
- LocalX2ApicNmiStruct.Type =3D EFI_ACPI_4_0_LOCAL_X2APIC_NMI;
- LocalX2ApicNmiStruct.Length =3D sizeof (EFI_ACPI_4_0_LOCAL_X2APIC_NM=
I_STRUCTURE);
+ LocalX2ApicNmiStruct.Type =3D EFI_ACPI_6_3_LOCAL_X2APIC_NMI;
+ LocalX2ApicNmiStruct.Length =3D sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NM=
I_STRUCTURE);
LocalX2ApicNmiStruct.Flags =3D 0x000D; // Flags - Le=
vel-tiggered, Active High
LocalX2ApicNmiStruct.AcpiProcessorUid =3D 0xFFFFFFFF; // Applies to=
all processors
LocalX2ApicNmiStruct.LocalX2ApicLint =3D 0x01;
@@ -1099,7 +1100,7 @@ InstallMadtFromScratch (
//
Status =3D BuildAcpiTable (
(EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
- sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
MadtStructs,
MadtStructsIndex,
(UINT8 **)&NewMadtTable
@@ -1222,7 +1223,7 @@ PlatformUpdateTables (
EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
UINT8 *TempOemId;
UINT64 TempOemTableId;
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader;
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *HpetTable;
UINT32 HpetBaseAddress;
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID HpetBlockId;
@@ -1279,12 +1280,12 @@ PlatformUpdateTables (
//
switch (Table->Signature) {
=20
- case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
+ case EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
ASSERT(FALSE);
break;
=20
- case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
- FadtHeader =3D (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *) Tabl=
e;
+ case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
+ FadtHeader =3D (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
=20
FadtHeader->PreferredPmProfile =3D PcdGet8 (PcdFadtPreferredPmProfil=
e);
FadtHeader->IaPcBootArch =3D PcdGet16 (PcdFadtIaPcBootArch);
@@ -1329,7 +1330,7 @@ PlatformUpdateTables (
DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));
break;
=20
- case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
+ case EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
HpetTable =3D (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *)Ta=
ble;
HpetBaseAddress =3D PcdGet32 (PcdHpetBaseAddress);
HpetTable->BaseAddressLower32Bit.Address =3D HpetBaseAddress;
@@ -1381,8 +1382,8 @@ IsHardwareChange (
UINTN HWChangeSize;
UINT32 PciId;
UINTN Handle;
- EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
- EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
=20
HandleCount =3D 0;
HandleBuffer =3D NULL;
@@ -1428,7 +1429,7 @@ IsHardwareChange (
//
Handle =3D 0;
Status =3D LocateAcpiTableBySignature (
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
(EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
&Handle
);
@@ -1450,7 +1451,7 @@ IsHardwareChange (
//
// Set HardwareSignature value based on CRC value.
//
- FacsPtr =3D (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFA=
DT->FirmwareCtrl;
+ FacsPtr =3D (EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFA=
DT->FirmwareCtrl;
FacsPtr->HardwareSignature =3D CRC;
FreePool( HWChange );
}
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c b/=
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
index cde6e478c6b9..8700c44e633d 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
@@ -1,9 +1,10 @@
/** @file
- This file contains a structure definition for the ACPI 5.0 Firmware AC=
PI
+ This file contains a structure definition for the ACPI 6.3 Firmware AC=
PI
Control Structure (FACS). The contents of this file should only be mo=
dified
for bug fixes, no porting is required.
=20
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -35,9 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Please modify all values in Facs.h only.
//
=20
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE),
=20
//
// Hardware Signature will be updated at runtime
@@ -48,7 +49,7 @@ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
EFI_ACPI_GLOBAL_LOCK,
EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
{
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c b/=
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
index 6efb38cda40d..38e767856de7 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
@@ -1,9 +1,10 @@
/** @file
- This file contains a structure definition for the ACPI 5.0 Fixed ACPI
+ This file contains a structure definition for the ACPI 6.3 Fixed ACPI
Description Table (FADT). The contents of this file should only be mo=
dified
for bug fixes, no porting is required.
=20
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -47,6 +48,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
=20
#define EFI_ACPI_IAPC_BOOT_ARCH 0 // To be fixed
=20
+//
+// ARM Boot Architecture Flags
+//
+
+#define EFI_ACPI_ARM_BOOT_ARCH 0 // To be fixed
+
//
// Fixed Feature Flags
//
@@ -55,7 +62,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1A Event Register Block Generic Address Information
//
-#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS 0 // To be fixed
@@ -63,7 +70,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1B Event Register Block Generic Address Information
//
-#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0 // To be fixed
@@ -71,7 +78,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1A Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS 0 // To be fixed
@@ -79,7 +86,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1B Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0 // To be fixed
@@ -87,7 +94,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM2 Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM2_CNT_BLK_ADDRESS 0 // To be fixed
@@ -96,7 +103,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Power Management Timer Control Register Block Generic Address
// Information
//
-#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM_TMR_BLK_ADDRESS 0 // To be fixed
@@ -105,7 +112,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// General Purpose Event 0 Register Block Generic Address
// Information
//
-#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0 // size of R_PCH_ACPI_GPE=
0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96
#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_GPE0_BLK_ADDRESS 0 // To be fixed
@@ -114,14 +121,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// General Purpose Event 1 Register Block Generic Address
// Information
//
-#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0
#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0
#define EFI_ACPI_GPE1_BLK_ADDRESS 0 // To be fixed
//
// Reset Register Generic Address Information
//
-#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
#define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9
@@ -162,11 +169,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Please modify all values in Fadt.h only.
//
=20
-EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
+EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
{
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
=20
//
// Checksum will be updated at runtime
@@ -187,9 +194,9 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
//
// These addresses will be updated at runtime
//
- 0x00000000,=20
0x00000000,
- =20
+ 0x00000000,
+
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_PREFERRED_PM_PROFILE,
EFI_ACPI_SCI_INT,
@@ -198,7 +205,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_ACPI_DISABLE,
EFI_ACPI_S4_BIOS_REQ,
EFI_ACPI_PSTATE_CNT,
- =20
+
EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
@@ -240,15 +247,13 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D =
{
EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
EFI_ACPI_RESET_REG_BIT_WIDTH,
EFI_ACPI_RESET_REG_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_RESET_REG_ADDRESS
},
EFI_ACPI_RESET_VALUE,
- {
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE
- },
+
+ EFI_ACPI_ARM_BOOT_ARCH,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
=20
//
// These addresses will be updated at runtime
@@ -263,7 +268,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1A_EVT_BLK_ADDRESS
},
{
@@ -273,7 +278,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1B_EVT_BLK_ADDRESS
},
{
@@ -283,7 +288,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1A_CNT_BLK_ADDRESS
},
{
@@ -293,7 +298,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1B_CNT_BLK_ADDRESS
},
{
@@ -303,7 +308,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_PM2_CNT_BLK_ADDRESS
},
{
@@ -313,7 +318,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_DWORD,
+ EFI_ACPI_6_3_DWORD,
EFI_ACPI_PM_TMR_BLK_ADDRESS
},
{
@@ -323,7 +328,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_GPE0_BLK_BIT_WIDTH,
EFI_ACPI_GPE0_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_GPE0_BLK_ADDRESS
},
{
@@ -333,7 +338,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_GPE1_BLK_BIT_WIDTH,
EFI_ACPI_GPE1_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_GPE1_BLK_ADDRESS
},
{
@@ -355,5 +360,10 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
0,
0,
0
- }
+ },
+
+ //
+ // Hypervisor Vendor Identity
+ //
+ 0x0000000000000000,
};
--=20
2.28.0.windows.1


Re: [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Zhiguang Liu
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [edk2-devel] [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Add the three PCDs as fixed at build PCD:
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
The default value is defined as Macro, so it can be passed in at build command.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index bcedf1c746..ba54f2057f 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -91,6 +91,13 @@
DEFINE EMU_VARIABLE_ENABLE = TRUE DEFINE DISABLE_RESET_SYSTEM = FALSE + # Dfine the maximum size of the capsule image without a reset flag that the platform can support.+ DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa00000++ # Define RTC related register.+ DEFINE RTC_INDEX_REGISTER = 0x70+ DEFINE RTC_TARGET_REGISTER = 0x71+ [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG@@ -324,7 +331,9 @@
!else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F !endif-+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|$(MAX_SIZE_NON_POPULATE_CAPSULE)+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER) # # The following parameters are set by Library/PlatformHookLib #--
2.32.0.windows.2



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Re: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Define some PCDs as DynamicEX PCD to be used as global variable.
Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code to set it in platformlib. That code was actually redundant.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c | 5 -----
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c | 4 ----
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/UefiPayloadPkg.dsc | 28 ++++++++++++++++++----------
5 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
index 72a17dc8a7..d8453e5957 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -75,11 +75,6 @@ PlatformHookSerialPortInitialize (
return Status; } - Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);- if (RETURN_ERROR (Status)) {- return Status;- }- Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz); if (RETURN_ERROR (Status)) { return Status;diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
index 2415d99c64..3eeb94d8fa 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -35,5 +35,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCESdiff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
index 6705f29505..bd433bdbe0 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.c
@@ -70,10 +70,6 @@ PlatformHookSerialPortInitialize (
if (RETURN_ERROR (Status)) { return Status; }- Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate);- if (RETURN_ERROR (Status)) {- return Status;- } return RETURN_SUCCESS; }diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
index 41e05ddf54..2dfd8b1216 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.inf
@@ -38,4 +38,3 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCESdiff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index ba54f2057f..d293211e46 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -308,11 +308,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0-!if $(TARGET) == DEBUG- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE-!else- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE-!endif gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE @@ -352,11 +347,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE) - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)@@ -369,6 +359,24 @@
################################################################################ [PcdsDynamicExDefault]+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize+!if $(TARGET) == DEBUG+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE+!else+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE+!endif gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0--
2.32.0.windows.2


Re: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Change the default value of the below PCDs to diable some legacy feature.
gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index d293211e46..002d2a8fa7 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -297,6 +297,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

## This PCD specified whether ACPI SDT protocol is installed.

gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE



[PcdsFixedAtBuild]

gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000

@@ -350,7 +352,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)



gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)

-

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0



################################################################################

#

--
2.32.0.windows.2


Re: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

This patch doesn't change the default behavior.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 ++++ UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
2 files changed, 6 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 002d2a8fa7..b4a30be381 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -98,6 +98,8 @@
DEFINE RTC_INDEX_REGISTER = 0x70 DEFINE RTC_TARGET_REGISTER = 0x71 + DEFINE SERIAL_DRIVER_ENABLE = TRUE+ [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG@@ -536,7 +538,9 @@
# # ISA Support #+!if $(SERIAL_DRIVER_ENABLE) == TRUE MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if $(PS2_KEYBOARD_ENABLE) == TRUE OvmfPkg/SioBusDxe/SioBusDxe.inf MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.infdiff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 041fed842c..b2cfb6b405 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -136,7 +136,9 @@ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
# # ISA Support #+!if $(SERIAL_DRIVER_ENABLE) == TRUE INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if $(PS2_KEYBOARD_ENABLE) == TRUE INF OvmfPkg/SioBusDxe/SioBusDxe.inf INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf--
2.32.0.windows.2


Re: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Friday, August 6, 2021 1:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit payload sets 4-level page table to CR3 resulting CPU exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
.../UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
.../UniversalPayloadEntry.inf | 1 -
.../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
) { UINT32 RegEax;- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 RegEdx; UINT8 PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAddress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
UINTN TotalPagesNum; UINTN BigPageAddress; VOID *Hob;- BOOLEAN Page5LevelSupport;+ BOOLEAN Enable5LevelPaging; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask;@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
} } - Page5LevelSupport = FALSE;- if (PcdGetBool (PcdUse5LevelPageTable)) {- AsmCpuidEx (- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,- &EcxFlags.Uint32, NULL, NULL- );- if (EcxFlags.Bits.FiveLevelPage != 0) {- Page5LevelSupport = TRUE;- }- }+ //+ // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.+ // Because this code runs at both IA-32e (64bit) mode and legacy protected (32bit) mode,+ // below logic inherits the 5-level paging setting from bootloader in IA-32e mode+ // and uses 4-level paging in legacy protected mode.+ //+ Cr4.UintN = AsmReadCr4 ();+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); - DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+ DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport)); // // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
// due to either unsupported by HW, or disabled by PCD. // ASSERT (PhysicalAddressBits <= 52);- if (!Page5LevelSupport && PhysicalAddressBits > 48) {+ if (!Enable5LevelPaging && PhysicalAddressBits > 48) { PhysicalAddressBits = 48; } @@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
// // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled. //- if (!Page5LevelSupport) {+ if (!Enable5LevelPaging) { TotalPagesNum--; } @@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // PageMap = (VOID *) BigPageAddress;- if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // By architecture only one PageMapLevel5 exists - so lets allocate storage for it. //@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
PageMapLevel4Entry = (VOID *) BigPageAddress; BigPageAddress += SIZE_4KB; - if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // Make a PML5 Entry //@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)); } - if (Page5LevelSupport) {- Cr4.UintN = AsmReadCr4 ();- Cr4.Bits.LA57 = 1;- AsmWriteCr4 (Cr4.UintN);+ if (Enable5LevelPaging) { // // For the PML5 entries we are not using fill in a null entry. //--
2.32.0.windows.1


[RFC PATCH 6/7] OVMF: Reference new classes in the build system for compilation

Stefan Berger <stefanb@...>
 

Compile the added code now.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 3 +++
.../Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 3 +++
OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++
OvmfPkg/OvmfPkgX64.dsc | 3 +++
5 files changed, 13 insertions(+)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index e6cd10b759..6b582626ff 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -209,9 +209,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -836,6 +838,7 @@
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D
<LibraryClasses>=0D
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR=
outerDxe.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterDxe.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.=
inf b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index e470b9a6a3..e7d1917022 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -56,6 +56,7 @@
PlatformBmPrintScLib=0D
Tcg2PhysicalPresenceLib=0D
XenPlatformLib=0D
+ TpmPlatformHierarchyLib=0D
=0D
[Pcd]=0D
gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent=0D
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index d1d92c97ba..374a1ea652 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -235,9 +235,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -711,6 +713,7 @@
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D
<LibraryClasses>=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterPei.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256=
.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384=
.inf=0D
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a467ab7090..7b7dffcd94 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -239,9 +239,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -1034,6 +1036,7 @@
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D
<LibraryClasses>=0D
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR=
outerDxe.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterDxe.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index e56b83d95e..34c6e833e4 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -239,9 +239,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -723,6 +725,7 @@
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D
<LibraryClasses>=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterPei.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256=
.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384=
.inf=0D
--=20
2.31.1


[RFC PATCH 3/7] SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)

Stefan Berger <stefanb@...>
 

To avoid this type of build errors, disable
'PcdGetBool (PcdRandomizePlatformHierarchy)'.

Building ... /home/stefanb/dev/edk2/SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf [X64]
In file included from /home/stefanb/dev/edk2/Build/OvmfX64/DEBUG_GCC5/X64/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib/DEBUG/AutoGen.h:17,
from <command-line>:
/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c: In function ‘ConfigureTpmPlatformHierarchy’:
/home/stefanb/dev/edk2/MdePkg/Include/Library/PcdLib.h:424:45: error: ‘_PCD_GET_MODE_BOOL_PcdRandomizePlatformHierarchy’ undeclared (first use in this function)
424 | #define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName
| ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
index 9812ab99ab..bea10d37a4 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
@@ -252,7 +252,7 @@ EFIAPI
ConfigureTpmPlatformHierarchy (
)
{
- if (PcdGetBool (PcdRandomizePlatformHierarchy)) {
+ if (1 /*PcdGetBool (PcdRandomizePlatformHierarchy)*/) {
//
// Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth being null
//
--
2.31.1


[RFC PATCH 7/7] OVMF: Disable the TPM2 platform hierarchy

Stefan Berger <stefanb@...>
 

Use the newly added functions to disable the TPM2 platform hierarchy.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c | 6 ++++++
OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c | 6 ++++++
OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c | 6 ++++++
3 files changed, 18 insertions(+)

diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg=
/Library/PlatformBootManagerLib/BdsPlatform.c
index b0e9742937..5bf145ba25 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -11,6 +11,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
#include <Library/XenPlatformLib.h>=0D
=0D
=0D
@@ -1516,6 +1517,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierarchy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Process QEMU's -kernel command line option=0D
//=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c b/Ov=
mfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
index eaade4adea..09418dc4ff 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
@@ -12,6 +12,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
=0D
#include <Protocol/BlockIo.h>=0D
=0D
@@ -1450,6 +1451,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierarchy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Perform some platform specific connect sequence=0D
//=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c b/Ovm=
fPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
index 7cceeea487..508e2b6403 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
@@ -12,6 +12,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
=0D
=0D
//=0D
@@ -1315,6 +1316,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierachy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Process QEMU's -kernel command line option=0D
//=0D
--=20
2.31.1


[RFC PATCH 5/7] SecurityPkg/TPM: Add a NULL implementation of PeiDxeTpmPlatformHierarchyLib

Stefan Berger <stefanb@...>
 

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.c | 23 +++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 39 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
new file mode 100644
index 0000000000..e871ada230
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
@@ -0,0 +1,23 @@
+/** @file
+ Null TPM Platform Hierarchy configuration library.
+
+ This library provides stub functions for customizing the TPM's Platform Hierarchy
+ Authorization Value (platformAuth) and Platform Hierarchy Authorization
+ Policy (platformPolicy) can be defined through this function.
+
+ Copyright (c) 2021, IBM Corporation.
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+VOID
+EFIAPI
+ConfigureTpmPlatformHierarchy (
+ )
+{
+ /* no nothing */
+}
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 0000000000..678f38410a
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
@@ -0,0 +1,39 @@
+### @file
+#
+# TPM Platform Hierarchy configuration library.
+#
+# This library provides functions for customizing the TPM's Platform Hierarchy
+# Authorization Value (platformAuth) and Platform Hierarchy Authorization
+# Policy (platformPolicy) can be defined through this function.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiDxeTpmPlatformHierarchyLibNull
+ FILE_GUID = 7794F92C-4E8E-4E57-9E4A-49A0764C7D73
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TpmPlatformHierarchyLib|PEIM DXE_DRIVER
+
+[LibraryClasses]
+ BaseLib
+# BaseMemoryLib
+# DebugLib
+# MemoryAllocationLib
+# PcdLib
+# RngLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+
+[Sources]
+ PeiDxeTpmPlatformHierarchyLib.c
--
2.31.1


[RFC PATCH 4/7] SecurityPkg/TPM: Disable a Pcd

Stefan Berger <stefanb@...>
 

Fix the following build issue.

/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pe=
iDxeTpmPlatformHierarchyLib.inf(46): error 4000: Value of Guid [gMinPlatfor=
mPkgTokenSpaceGuid] is not found under [Guids] section in
/home/stefanb/dev/edk2/MdePkg/MdePkg.dec
/home/stefanb/dev/edk2/MdeModulePkg/MdeModulePkg.dec
/home/stefanb/dev/edk2/SecurityPkg/SecurityPkg.dec
/home/stefanb/dev/edk2/CryptoPkg/CryptoPkg.dec

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.inf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P=
eiDxeTpmPlatformHierarchyLib.inf
index 1f23032e46..f1effd3ffb 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
@@ -42,5 +42,5 @@
[Sources]=0D
PeiDxeTpmPlatformHierarchyLib.c=0D
=0D
-[Pcd]=0D
- gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy=0D
+#[Pcd]=0D
+# gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy=0D
--=20
2.31.1


[RFC PATCH 2/7] SecruityPkg/TPM: Disable dependency on MinPlatformPkg

Stefan Berger <stefanb@...>
 

Disable the dependency on the MinPlatformPkg to avoid this type of build
errors:

/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pe=
iDxeTpmPlatformHierarchyLib.inf(39): error 000E: File/directory not found i=
n workspace
/home/stefanb/dev/edk2/MinPlatformPkg/MinPlatformPkg.dec

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.inf | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P=
eiDxeTpmPlatformHierarchyLib.inf
index b7a7fb0a08..1f23032e46 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
@@ -36,7 +36,8 @@
MdeModulePkg/MdeModulePkg.dec=0D
SecurityPkg/SecurityPkg.dec=0D
CryptoPkg/CryptoPkg.dec=0D
- MinPlatformPkg/MinPlatformPkg.dec=0D
+=0D
+# MinPlatformPkg/MinPlatformPkg.dec=0D
=0D
[Sources]=0D
PeiDxeTpmPlatformHierarchyLib.c=0D
--=20
2.31.1


[RFC PATCH 1/7] SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from edk2-platforms

Stefan Berger <stefanb@...>
 

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 266 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 45 +++
3 files changed, 338 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDx=
eTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDx=
eTpmPlatformHierarchyLib.inf

diff --git a/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h b/Securi=
tyPkg/Include/Library/TpmPlatformHierarchyLib.h
new file mode 100644
index 0000000000..a872fa09dc
--- /dev/null
+++ b/SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
@@ -0,0 +1,27 @@
+/** @file=0D
+ TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+ Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+ Policy (platformPolicy) can be defined through this function.=0D
+=0D
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) Microsoft Corporation.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+#define _TPM_PLATFORM_HIERARCHY_LIB_H_=0D
+=0D
+/**=0D
+ This service will perform the TPM Platform Hierarchy configuration at t=
he SmmReadyToLock event.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ VOID=0D
+ );=0D
+=0D
+#endif=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/Pei=
DxeTpmPlatformHierarchyLib.c
new file mode 100644
index 0000000000..9812ab99ab
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.c
@@ -0,0 +1,266 @@
+/** @file=0D
+ TPM Platform Hierarchy configuration library.=0D
+=0D
+ This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+ Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+ Policy (platformPolicy) can be defined through this function.=0D
+=0D
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) Microsoft Corporation.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+ @par Specification Reference:=0D
+ https://trustedcomputinggroup.org/resource/tcg-tpm-v2-0-provisioning-g=
uidance/=0D
+**/=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <Library/RngLib.h>=0D
+#include <Library/Tpm2CommandLib.h>=0D
+#include <Library/Tpm2DeviceLib.h>=0D
+=0D
+//=0D
+// The authorization value may be no larger than the digest produced by th=
e hash=0D
+// algorithm used for context integrity.=0D
+//=0D
+#define MAX_NEW_AUTHORIZATION_SIZE SHA512_DIGEST_SIZE=0D
+=0D
+UINT16 mAuthSize;=0D
+=0D
+/**=0D
+ Generate high-quality entropy source through RDRAND.=0D
+=0D
+ @param[in] Length Size of the buffer, in bytes, to fill with.=0D
+ @param[out] Entropy Pointer to the buffer to store the entropy da=
ta.=0D
+=0D
+ @retval EFI_SUCCESS Entropy generation succeeded.=0D
+ @retval EFI_NOT_READY Failed to request random data.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+RdRandGenerateEntropy (=0D
+ IN UINTN Length,=0D
+ OUT UINT8 *Entropy=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN BlockCount;=0D
+ UINT64 Seed[2];=0D
+ UINT8 *Ptr;=0D
+=0D
+ Status =3D EFI_NOT_READY;=0D
+ BlockCount =3D Length / 64;=0D
+ Ptr =3D (UINT8 *)Entropy;=0D
+=0D
+ //=0D
+ // Generate high-quality seed for DRBG Entropy=0D
+ //=0D
+ while (BlockCount > 0) {=0D
+ Status =3D GetRandomNumber128 (Seed);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ CopyMem (Ptr, Seed, 64);=0D
+=0D
+ BlockCount--;=0D
+ Ptr =3D Ptr + 64;=0D
+ }=0D
+=0D
+ //=0D
+ // Populate the remained data as request.=0D
+ //=0D
+ Status =3D GetRandomNumber128 (Seed);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ CopyMem (Ptr, Seed, (Length % 64));=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ This function returns the maximum size of TPM2B_AUTH; this structure is =
used for an authorization value=0D
+ and limits an authValue to being no larger than the largest digest produ=
ced by a TPM.=0D
+=0D
+ @param[out] AuthSize Tpm2 Auth size=0D
+=0D
+ @retval EFI_SUCCESS Auth size returned.=0D
+ @retval EFI_DEVICE_ERROR Can not return platform auth due to=
device error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+GetAuthSize (=0D
+ OUT UINT16 *AuthSize=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ TPML_PCR_SELECTION Pcrs;=0D
+ UINTN Index;=0D
+ UINT16 DigestSize;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ while (mAuthSize =3D=3D 0) {=0D
+=0D
+ mAuthSize =3D SHA1_DIGEST_SIZE;=0D
+ ZeroMem (&Pcrs, sizeof (TPML_PCR_SELECTION));=0D
+ Status =3D Tpm2GetCapabilityPcrs (&Pcrs);=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs fail!\n"));=0D
+ break;=0D
+ }=0D
+=0D
+ DEBUG ((DEBUG_ERROR, "Tpm2GetCapabilityPcrs - %08x\n", Pcrs.count));=0D
+=0D
+ for (Index =3D 0; Index < Pcrs.count; Index++) {=0D
+ DEBUG ((DEBUG_ERROR, "alg - %x\n", Pcrs.pcrSelections[Index].hash));=
=0D
+=0D
+ switch (Pcrs.pcrSelections[Index].hash) {=0D
+ case TPM_ALG_SHA1:=0D
+ DigestSize =3D SHA1_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA256:=0D
+ DigestSize =3D SHA256_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA384:=0D
+ DigestSize =3D SHA384_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SHA512:=0D
+ DigestSize =3D SHA512_DIGEST_SIZE;=0D
+ break;=0D
+ case TPM_ALG_SM3_256:=0D
+ DigestSize =3D SM3_256_DIGEST_SIZE;=0D
+ break;=0D
+ default:=0D
+ DigestSize =3D SHA1_DIGEST_SIZE;=0D
+ break;=0D
+ }=0D
+=0D
+ if (DigestSize > mAuthSize) {=0D
+ mAuthSize =3D DigestSize;=0D
+ }=0D
+ }=0D
+ break;=0D
+ }=0D
+=0D
+ *AuthSize =3D mAuthSize;=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ Set PlatformAuth to random value.=0D
+**/=0D
+VOID=0D
+RandomizePlatformAuth (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT16 AuthSize;=0D
+ UINT8 *Rand;=0D
+ UINTN RandSize;=0D
+ TPM2B_AUTH NewPlatformAuth;=0D
+=0D
+ //=0D
+ // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth=
being null=0D
+ //=0D
+=0D
+ GetAuthSize (&AuthSize);=0D
+=0D
+ ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
+ NewPlatformAuth.size =3D AuthSize;=0D
+=0D
+ //=0D
+ // Allocate one buffer to store random data.=0D
+ //=0D
+ RandSize =3D MAX_NEW_AUTHORIZATION_SIZE;=0D
+ Rand =3D AllocatePool (RandSize);=0D
+=0D
+ RdRandGenerateEntropy (RandSize, Rand);=0D
+ CopyMem (NewPlatformAuth.buffer, Rand, AuthSize);=0D
+=0D
+ FreePool (Rand);=0D
+=0D
+ //=0D
+ // Send Tpm2HierarchyChangeAuth command with the new Auth value=0D
+ //=0D
+ Status =3D Tpm2HierarchyChangeAuth (TPM_RH_PLATFORM, NULL, &NewPlatformA=
uth);=0D
+ DEBUG ((DEBUG_INFO, "Tpm2HierarchyChangeAuth Result: - %r\n", Status));=
=0D
+ ZeroMem (NewPlatformAuth.buffer, AuthSize);=0D
+ ZeroMem (Rand, RandSize);=0D
+}=0D
+=0D
+/**=0D
+ Disable the TPM platform hierarchy.=0D
+=0D
+ @retval EFI_SUCCESS The TPM was disabled successfully.=0D
+ @retval Others An error occurred attempting to disable the =
TPM platform hierarchy.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+DisableTpmPlatformHierarchy (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ // Make sure that we have use of the TPM.=0D
+ Status =3D Tpm2RequestUseTpm ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "%a:%a() - Tpm2RequestUseTpm Failed! %r\n", gEfiC=
allerBaseName, __FUNCTION__, Status));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Let's do what we can to shut down the hierarchies.=0D
+=0D
+ // Disable the PH NV.=0D
+ // IMPORTANT NOTE: We *should* be able to disable the PH NV here, but TP=
M parts have=0D
+ // been known to store the EK cert in the PH NV. If we d=
isable it, the=0D
+ // EK cert will be unreadable.=0D
+=0D
+ // Disable the PH.=0D
+ Status =3D Tpm2HierarchyControl (=0D
+ TPM_RH_PLATFORM, // AuthHandle=0D
+ NULL, // AuthSession=0D
+ TPM_RH_PLATFORM, // Hierarchy=0D
+ NO // State=0D
+ );=0D
+ DEBUG ((DEBUG_VERBOSE, "%a:%a() - Disable PH =3D %r\n", gEfiCallerBaseN=
ame, __FUNCTION__, Status));=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "%a:%a() - Disable PH Failed! %r\n", gEfiCallerB=
aseName, __FUNCTION__, Status));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ This service defines the configuration of the Platform Hierarchy Author=
ization Value (platformAuth)=0D
+ and Platform Hierarchy Authorization Policy (platformPolicy)=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+ConfigureTpmPlatformHierarchy (=0D
+ )=0D
+{=0D
+ if (PcdGetBool (PcdRandomizePlatformHierarchy)) {=0D
+ //=0D
+ // Send Tpm2HierarchyChange Auth with random value to avoid PlatformAu=
th being null=0D
+ //=0D
+ RandomizePlatformAuth ();=0D
+ } else {=0D
+ //=0D
+ // Disable the hierarchy entirely (do not randomize it)=0D
+ //=0D
+ DisableTpmPlatformHierarchy ();=0D
+ }=0D
+}=0D
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPla=
tformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P=
eiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 0000000000..b7a7fb0a08
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHi=
erarchyLib.inf
@@ -0,0 +1,45 @@
+### @file=0D
+#=0D
+# TPM Platform Hierarchy configuration library.=0D
+#=0D
+# This library provides functions for customizing the TPM's Platform Hie=
rarchy=0D
+# Authorization Value (platformAuth) and Platform Hierarchy Authorizatio=
n=0D
+# Policy (platformPolicy) can be defined through this function.=0D
+#=0D
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) Microsoft Corporation.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+###=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PeiDxeTpmPlatformHierarchyLib=0D
+ FILE_GUID =3D 7794F92C-4E8E-4E57-9E4A-49A0764C7D73=
=0D
+ MODULE_TYPE =3D PEIM=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D TpmPlatformHierarchyLib|PEIM DXE_DRIV=
ER=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ BaseMemoryLib=0D
+ DebugLib=0D
+ MemoryAllocationLib=0D
+ PcdLib=0D
+ RngLib=0D
+ Tpm2CommandLib=0D
+ Tpm2DeviceLib=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ SecurityPkg/SecurityPkg.dec=0D
+ CryptoPkg/CryptoPkg.dec=0D
+ MinPlatformPkg/MinPlatformPkg.dec=0D
+=0D
+[Sources]=0D
+ PeiDxeTpmPlatformHierarchyLib.c=0D
+=0D
+[Pcd]=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdRandomizePlatformHierarchy=0D
--=20
2.31.1


[RFC PATCH 0/7] OVMF: Disable the TPM2 platform hierarchy

Stefan Berger <stefanb@...>
 

This series imports code from the edk2-platforms project related to
changing the password of the TPM2 platform hierarchy and uses it to
disable the TPM2 platform hierarchy in OVMF. It addresses the OVMF
aspects of the following bugs:

https://bugzilla.tianocore.org/show_bug.cgi?id=3510
https://bugzilla.tianocore.org/show_bug.cgi?id=3499

There's no doubt that my struggles with the build system and handling
of dependencies are visible in this series. Quite a few aspects of
getting things right are more or less guesswork and I am often not sure
what the correct way of doing things are. If 'you' wanted to fix
things up and repost it, please go ahead...

Stefan

Stefan Berger (7):
SecurityPkg/TPM: Import PeiDxeTpmPlatformHierarchyLib.c from
edk2-platforms
SecruityPkg/TPM: Disable dependency on MinPlatformPkg
SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)
SecurityPkg/TPM: Disable a Pcd
SecurityPkg/TPM: Add a NULL implementation of
PeiDxeTpmPlatformHierarchyLib
OVMF: Reference new classes in the build system for compilation
OVMF: Disable the TPM2 platform hierarchy

OvmfPkg/AmdSev/AmdSevX64.dsc | 3 +
.../PlatformBootManagerLib/BdsPlatform.c | 6 +
.../PlatformBootManagerLib.inf | 1 +
.../PlatformBootManagerLibBhyve/BdsPlatform.c | 6 +
.../PlatformBootManagerLibGrub/BdsPlatform.c | 6 +
OvmfPkg/OvmfPkgIa32.dsc | 3 +
OvmfPkg/OvmfPkgIa32X64.dsc | 3 +
OvmfPkg/OvmfPkgX64.dsc | 3 +
.../Include/Library/TpmPlatformHierarchyLib.h | 27 ++
.../PeiDxeTpmPlatformHierarchyLib.c | 266 ++++++++++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 46 +++
.../PeiDxeTpmPlatformHierarchyLib.c | 23 ++
.../PeiDxeTpmPlatformHierarchyLib.inf | 39 +++
13 files changed, 432 insertions(+)
create mode 100644 SecurityPkg/Include/Library/TpmPlatformHierarchyLib.h
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

--
2.31.1


Re: [Patch 0/3] Ext4Pkg: Add Ext4Pkg

Michael D Kinney
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Pedro Falcato
Sent: Thursday, August 5, 2021 3:50 PM
To: Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io
Cc: Leif Lindholm <leif@nuviainc.com>; Bret Barkelew <Bret.Barkelew@microsoft.com>
Subject: Re: [edk2-devel] [Patch 0/3] Ext4Pkg: Add Ext4Pkg

Hi Mike,

Thanks for the helpful pointers. I'll consider everything for V2,
which I'll submit as soon as possible (hopefully tomorrow).

RE: Code style. I'll re-run ECC and try to solve the issues. One thing
though: Is it possible to make an exception for the naming of
ext4-specific struct members?
Example: Members' names like "bg_block_bitmap_lo" in
This is ok since this is a structure that is based on the EXT4
documentation,

EXT4_BLOCK_GROUP_DESC. I'd like to make a case for it; from my
experience with my own hobby project's ext2 driver, having names
similar to what's used in the documentation/other source code is
incredibly helpful when trying to work on the code; with the original
docs' names, which are admittedly not compliant with the EDK2 coding
style, it really makes everything much clearer when using other code
or documentation as reference. Of course, if it's not possible I'll
rename them all.

Thanks,

Pedro


On Thu, 5 Aug 2021 at 19:33, Kinney, Michael D
<michael.d.kinney@intel.com> wrote:

Hi Pedro,

1) Ext4Pkg/Ext4Dxe/Ext4Dxe.inf:

* To be consistent with other drivers, BASE_NAME should be changed from Ext4 to Ext4Dxe.
* For proper dependency checking in incremental builds, please add the .h files to the [Sources] section

Ext4Disk.h
Ext4Dxe.h

2) There are a number of code style issues that need to be addressed. Can you fix those for V2?

3) I did a quick pass to find the IA32 NOOPT VS2019 issues. With the following changes, I can get it to build. Do not
know if I introduced any functional changes by mistake.

diff --git a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
index 10a82d40a0..f2db93f02c 100644
--- a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
+++ b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
@@ -61,7 +61,7 @@ Ext4ReadInode (
Partition,
Inode,
Partition->InodeSize,
- Ext4BlockToByteOffset (Partition, InodeTableStart) + InodeOffset * Partition->InodeSize
+ Ext4BlockToByteOffset (Partition, InodeTableStart) + MultU64x32 (InodeOffset, Partition->InodeSize)
);

if (EFI_ERROR (Status)) {
diff --git a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
index 1cafdd64cd..65109809c0 100644
--- a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
+++ b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
@@ -45,7 +45,7 @@ Ext4ReadBlocks (
IN EXT4_BLOCK_NR BlockNumber
)
{
- return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * Partition->BlockSize, BlockNumber * Partition->BlockSize);
+ return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * Partition->BlockSize, MultU64x32 (BlockNumber, Partition-
BlockSize));
}

/**
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
index d790e70be1..8aa584df14 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
@@ -445,6 +445,6 @@ typedef struct {
typedef UINT64 EXT4_BLOCK_NR;
typedef UINT32 EXT4_INO_NR;

-#define EXT4_INODE_SIZE(ino) (((UINT64)ino->i_size_hi << 32) | ino->i_size_lo)
+#define EXT4_INODE_SIZE(ino) (LShiftU64 (ino->i_size_hi, 32) | ino->i_size_lo)

#endif
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
index f6875c919e..a055a139e1 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
@@ -244,7 +244,7 @@ Ext4MakeBlockNumberFromHalfs (
)
{
// High might have garbage if it's not a 64 bit filesystem
- return Ext4Is64Bit (Partition) ? Low | ((UINT64)High << 32) : Low;
+ return Ext4Is64Bit (Partition) ? (Low | LShiftU64 (High, 32)) : Low;
}

/**
@@ -297,7 +297,7 @@ Ext4BlockToByteOffset (
IN EXT4_BLOCK_NR Block
)
{
- return Partition->BlockSize * Block;
+ return MultU64x32 (Block, Partition->BlockSize);
}

/**
@@ -333,7 +333,7 @@ Ext4InodeSize (
CONST EXT4_INODE *Inode
)
{
- return ((UINT64)Inode->i_size_hi << 32) | Inode->i_size_lo;
+ return (LShiftU64 (Inode->i_size_hi, 32) | Inode->i_size_lo);
}

/**
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
index 102b12d613..fc0185285e 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
@@ -111,6 +111,8 @@ [Sources]
Collation.c
Crc32c.c
Crc16.c
+ Ext4Disk.h
+ Ext4Dxe.h

[Packages]
MdePkg/MdePkg.dec
diff --git a/Features/Ext4Pkg/Ext4Dxe/Extents.c b/Features/Ext4Pkg/Ext4Dxe/Extents.c
index db4bf5aa3f..8c9b4a4c75 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Extents.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Extents.c
@@ -210,7 +210,7 @@ Ext4ExtentIdxLeafBlock (
IN EXT4_EXTENT_INDEX *Index
)
{
- return ((UINT64)Index->ei_leaf_hi << 32) | Index->ei_leaf_lo;
+ return LShiftU64(Index->ei_leaf_hi, 32) | Index->ei_leaf_lo;
}

STATIC UINTN GetExtentRequests = 0;
diff --git a/Features/Ext4Pkg/Ext4Dxe/File.c b/Features/Ext4Pkg/Ext4Dxe/File.c
index 10dda64b16..71d36d1990 100644
--- a/Features/Ext4Pkg/Ext4Dxe/File.c
+++ b/Features/Ext4Pkg/Ext4Dxe/File.c
@@ -487,8 +487,8 @@ Ext4GetFilesystemInfo (
Info->BlockSize = Part->BlockSize;
Info->Size = NeededLength;
Info->ReadOnly = Part->ReadOnly;
- Info->VolumeSize = TotalBlocks * Part->BlockSize;
- Info->FreeSpace = FreeBlocks * Part->BlockSize;
+ Info->VolumeSize = MultU64x32 (TotalBlocks, Part->BlockSize);
+ Info->FreeSpace = MultU64x32 (FreeBlocks, Part->BlockSize);

if (VolumeName != NULL) {
StrCpyS (Info->VolumeLabel, VolNameLength + 1, VolumeName);
diff --git a/Features/Ext4Pkg/Ext4Dxe/Inode.c b/Features/Ext4Pkg/Ext4Dxe/Inode.c
index 304bf0c4a9..2a9f534d7e 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Inode.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Inode.c
@@ -154,7 +154,7 @@ Ext4Read (
UINT64 ExtentOffset;
UINTN ExtentMayRead;

- ExtentStartBytes = (((UINT64)Extent.ee_start_hi << 32) | Extent.ee_start_lo) * Partition->BlockSize;
+ ExtentStartBytes = MultU64x32 (LShiftU64 (Extent.ee_start_hi, 32) | Extent.ee_start_lo, Partition->BlockSize);
ExtentLengthBytes = Extent.ee_len * Partition->BlockSize;
ExtentLogicalBytes = (UINT64)Extent.ee_block * Partition->BlockSize;
ExtentOffset = CurrentSeek - ExtentLogicalBytes;
@@ -276,17 +276,17 @@ Ext4FilePhysicalSpace (
Blocks = File->Inode->i_blocks;

if(HugeFile) {
- Blocks |= ((UINT64)File->Inode->i_osd2.data_linux.l_i_blocks_high) << 32;
+ Blocks |= LShiftU64 (File->Inode->i_osd2.data_linux.l_i_blocks_high, 32);

// If HUGE_FILE is enabled and EXT4_HUGE_FILE_FL is set in the inode's flags, each unit
// in i_blocks corresponds to an actual filesystem block
if(File->Inode->i_flags & EXT4_HUGE_FILE_FL) {
- return Blocks * File->Partition->BlockSize;
+ return MultU64x32 (Blocks, File->Partition->BlockSize);
}
}

// Else, each i_blocks unit corresponds to 512 bytes
- return Blocks * 512;
+ return MultU64x32 (Blocks, 512);
}

// Copied from EmbeddedPkg at my mentor's request.
@@ -368,7 +368,7 @@ EpochToEfiTime (
UINT32 Nanoseconds = 0; \
\
if (Ext4InodeHasField (Inode, Field ## _extra)) { \
- SecondsEpoch |= ((UINT64)(Inode->Field ## _extra & EXT4_EXTRA_TIMESTAMP_MASK)) << 32; \
+ SecondsEpoch |= LShiftU64 ((UINT64)(Inode->Field ## _extra & EXT4_EXTRA_TIMESTAMP_MASK), 32); \
Nanoseconds = Inode->Field ## _extra >> 2; \
} \
EpochToEfiTime ((UINTN)SecondsEpoch, Time); \
diff --git a/Features/Ext4Pkg/Ext4Dxe/Superblock.c b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
index 18d8295a1f..88d01b62a8 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Superblock.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
@@ -161,7 +161,7 @@ Ext4OpenSuperblock (

DEBUG ((EFI_D_INFO, "Read only = %u\n", Partition->ReadOnly));

- Partition->BlockSize = 1024 << Sb->s_log_block_size;
+ Partition->BlockSize = (UINT32)LShiftU64 (1024, Sb->s_log_block_size);

// The size of a block group can also be calculated as 8 * Partition->BlockSize
if(Sb->s_blocks_per_group != 8 * Partition->BlockSize) {
@@ -195,7 +195,7 @@ Ext4OpenSuperblock (
}

NrBlocks = (UINTN)DivU64x32Remainder (
- Partition->NumberBlockGroups * Partition->DescSize,
+ MultU64x32 (Partition->NumberBlockGroups, Partition->DescSize),
Partition->BlockSize,
&NrBlocksRem
);
diff --git a/Features/Ext4Pkg/Ext4Pkg.dsc b/Features/Ext4Pkg/Ext4Pkg.dsc
index 62cb4e69cf..57f279a4d9 100644
--- a/Features/Ext4Pkg/Ext4Pkg.dsc
+++ b/Features/Ext4Pkg/Ext4Pkg.dsc
@@ -20,6 +20,8 @@ [Defines]
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT

+!include MdePkg/MdeLibs.dsc.inc
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES




Thanks,

Mike




-----Original Message-----
From: Pedro Falcato <pedro.falcato@gmail.com>
Sent: Friday, July 30, 2021 9:17 AM
To: devel@edk2.groups.io
Cc: Pedro Falcato <pedro.falcato@gmail.com>; Leif Lindholm <leif@nuviainc.com>; Kinney, Michael D
<michael.d.kinney@intel.com>; Bret Barkelew <Bret.Barkelew@microsoft.com>
Subject: [Patch 0/3] Ext4Pkg: Add Ext4Pkg

This patch-set adds Ext4Pkg, a package designed to hold various drivers and
utilities related to the EXT4 filesystem.

Right now, it holds a single read-only UEFI EXT4 driver (Ext4Dxe), which consumes the
DISK_IO, BLOCK_IO and DISK_IO2 protocols and produce EFI_FILE_PROTOCOL and
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL; this driver allows the mounting of EXT4 partitions and
the reading of their contents.

Relevant RFC discussion, which includes a more in-depth walkthrough of EXT4 internals and
driver limitations is available at https://edk2.groups.io/g/devel/topic/84368561.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>

Pedro Falcato (3):
Ext4Pkg: Add Ext4Pkg.dec and Ext4Pkg.uni.
Ext4Pkg: Add Ext4Dxe driver.
Ext4Pkg: Add .DSC file.

Features/Ext4Pkg/Ext4Dxe/BlockGroup.c | 208 ++++++
Features/Ext4Pkg/Ext4Dxe/Collation.c | 157 +++++
Features/Ext4Pkg/Ext4Dxe/Crc16.c | 75 ++
Features/Ext4Pkg/Ext4Dxe/Crc32c.c | 84 +++
Features/Ext4Pkg/Ext4Dxe/Directory.c | 492 ++++++++++++++
Features/Ext4Pkg/Ext4Dxe/DiskUtil.c | 83 +++
Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h | 450 ++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c | 454 +++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h | 942 ++++++++++++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf | 147 ++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.uni | 15 +
Features/Ext4Pkg/Ext4Dxe/Extents.c | 616 +++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/File.c | 583 ++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/Inode.c | 468 +++++++++++++
Features/Ext4Pkg/Ext4Dxe/Partition.c | 120 ++++
Features/Ext4Pkg/Ext4Dxe/Superblock.c | 257 +++++++
Features/Ext4Pkg/Ext4Pkg.dec | 17 +
Features/Ext4Pkg/Ext4Pkg.dsc | 68 ++
Features/Ext4Pkg/Ext4Pkg.uni | 14 +
19 files changed, 5250 insertions(+)
create mode 100644 Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Collation.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Crc16.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Crc32c.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Directory.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.uni
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Extents.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/File.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Inode.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Partition.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Superblock.c
create mode 100644 Features/Ext4Pkg/Ext4Pkg.dec
create mode 100644 Features/Ext4Pkg/Ext4Pkg.dsc
create mode 100644 Features/Ext4Pkg/Ext4Pkg.uni

--
2.32.0

--
Pedro Falcato




Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Andrei Warkentin
 

Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would eventually move to DEN0115).

I still think that (in general) would be a good idea - if not for the benefit of the Pi, then for the next upstreamed platform where you could avoid implementing custom config access code...

Reviewed-by: Andrei Warkentin <awarkentin@...>

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware


From: Andrei Warkentin <awarkentin@...>
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; jeremy.linton@... <jeremy.linton@...>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; René Treffer <treffer+groups.io@...>
Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
 
Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton@...>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Andrei Warkentin <awarkentin@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; Jeremy Linton <jeremy.linton@...>; René Treffer <treffer+groups.io@...>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
 
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer <treffer+groups.io@...>
Signed-off-by: Jeremy Linton <jeremy.linton@...>
---
 .../Bcm2711PciHostBridgeLibConstructor.c           |  5 -----
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++++++++++++++-------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) != 0x030) && (Timeout));
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
 
-  if ((Data & 0x30) != 0x30) {
-    DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-    return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) != 0x80) {
     DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
     return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
   UINT64        Base;
   UINT64        Offset;
   UINT32        Dev;
+  UINT32        Bus;
+  UINT32        Data;
 
   Base = PCIE_REG_BASE;
   Offset = Address & 0xFFF;         /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
     Base += PCIE_EXT_CFG_DATA;
     if (mPciSegmentLastAccess != Address) {
       Dev = EFI_PCI_ADDR_DEV (Address);
+      Bus = EFI_PCI_ADDR_BUS (Address);
+     
       /*
-       * Scan things out directly rather than translating the "bus" to a device, etc..
-       * only we need to limit each bus to a single device.
+       * There can only be a single device on bus 1 (downstream of root).
+       * Subsequent busses (behind a PCIe switch) can have more.
        */
-      if (Dev < 1) {
-          MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-          mPciSegmentLastAccess = Address;
-      } else {
-          mPciSegmentLastAccess = 0;
+      if (Dev > 0 && (Bus < 2)) {
           return 0xFFFFFFFF;
       }
+
+      /* Don't probe slots if the link is down */
+      Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+      if ((Data & 0x30) != 0x30) {
+          DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+          return 0xFFFFFFFF;
+      }
+
+      MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+      mPciSegmentLastAccess = Address;
     }
   }
   return Base + Offset;
--
2.13.7







Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Andrei Warkentin
 

Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton@...>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Andrei Warkentin <awarkentin@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; Jeremy Linton <jeremy.linton@...>; René Treffer <treffer+groups.io@...>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
 
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer <treffer+groups.io@...>
Signed-off-by: Jeremy Linton <jeremy.linton@...>
---
 .../Bcm2711PciHostBridgeLibConstructor.c           |  5 -----
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++++++++++++++-------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) != 0x030) && (Timeout));
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
 
-  if ((Data & 0x30) != 0x30) {
-    DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
-    return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) != 0x80) {
     DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
     return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
   UINT64        Base;
   UINT64        Offset;
   UINT32        Dev;
+  UINT32        Bus;
+  UINT32        Data;
 
   Base = PCIE_REG_BASE;
   Offset = Address & 0xFFF;         /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
     Base += PCIE_EXT_CFG_DATA;
     if (mPciSegmentLastAccess != Address) {
       Dev = EFI_PCI_ADDR_DEV (Address);
+      Bus = EFI_PCI_ADDR_BUS (Address);
+     
       /*
-       * Scan things out directly rather than translating the "bus" to a device, etc..
-       * only we need to limit each bus to a single device.
+       * There can only be a single device on bus 1 (downstream of root).
+       * Subsequent busses (behind a PCIe switch) can have more.
        */
-      if (Dev < 1) {
-          MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-          mPciSegmentLastAccess = Address;
-      } else {
-          mPciSegmentLastAccess = 0;
+      if (Dev > 0 && (Bus < 2)) {
           return 0xFFFFFFFF;
       }
+
+      /* Don't probe slots if the link is down */
+      Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+      if ((Data & 0x30) != 0x30) {
+          DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+          return 0xFFFFFFFF;
+      }
+
+      MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+      mPciSegmentLastAccess = Address;
     }
   }
   return Base + Offset;
--
2.13.7







Re: [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT

Andrei Warkentin
 

Reviewed-by: Andrei Warkentin <awarkentin@...>

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton@...>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Andrei Warkentin <awarkentin@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; Jeremy Linton <jeremy.linton@...>
Subject: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT
 
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.

Signed-off-by: Jeremy Linton <jeremy.linton@...>
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf     |  1 +
 Platform/RaspberryPi/AcpiTables/Dsdt.asl           |  3 --
 Platform/RaspberryPi/AcpiTables/Xhci.asl           | 35 ++++++++++++++--------
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |  8 +++++
 4 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
   SpcrPl011.aslc
   Pptt.aslc
   SsdtThermal.asl
+  Xhci.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
   Scope (\_SB_)
   {
     include ("Pep.asl")
-#if (RPI_MODEL == 4)
-    include ("Xhci.asl")
-#endif
 
     Device (CPU0)
     {
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
 
 #include <IndustryStandard/Bcm2711.h>
 
+#include "AcpiTables.h"
+
 /*
  * The following can be used to remove parenthesis from
  * defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
  */
 #define XHCI_REG_LENGTH                 0x1000
 
-Device (SCB0) {
-    Name (_HID, "ACPI0004")
-    Name (_UID, 0x0)
-    Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+  Scope (\_SB_)
+  {
+
+    Device (SCB0) {
+      Name (_HID, "ACPI0004")
+      Name (_UID, 0x0)
+      Name (_CCA, 0x0)
 
-    Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+      Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
         /*
          * Container devices with _DMA must have _CRS, meaning SCB0
          * to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
         Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
         Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
         Return (RBUF)
-    }
+      }
 
-    Name (_DMA, ResourceTemplate() {
+      Name (_DMA, ResourceTemplate() {
         /*
          * XHC0 is limited to DMA to first 3GB. Note this
          * only applies to PCIe, not GENET or other devices
          * next to the A72.
          */
-        QWordMemory (ResourceConsumer,
+        QWordMemory (ResourceProducer,
             ,
             MinFixed,
             MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
             ,
             ,
             )
-    })
+      })
 
-    Device (XHC0)
-    {
+      Device (XHC0)
+      {
         Name (_HID, "PNP0D10")      // _HID: Hardware ID
         Name (_UID, 0x0)            // _UID: Unique ID
         Name (_CCA, 0x0)            // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
             Debug = "xHCI enable"
             Store (0x6, CMND)
         }
-    }
-}
+      } // end XHC0
+    } //end SCB0
+  } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
     PcdToken(PcdSdIsArasan),
     SsdtEmmcNameOpReplace
   },
+#if (RPI_MODEL == 4)
+  {
+    SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+    0,
+    PcdToken(PcdXhciPci),
+    NULL
+  },
+#endif
   { // DSDT
     SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
     0,
--
2.13.7



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Re: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

Andrei Warkentin
 

Hi Jeremy,

Reviewed-by: Andrei Warkentin <awarkentin@...>

MADT -> MCFG

Root port registers would be NonCacheable just like the outbound mapping. (Also, with https://mantis.uefi.org/mantis/view.php?id=2220, _MEM attributes aside from  NonCacheable and Prefetchable are effectively deprecated).

Note: I really wish we had sorted out the HID/CID story for the PCIe RC... i.e. at least to make the HID custom for non-ECAM implementations and push PNP0A08/PNP0A03 in the CID... this would make linux,pcie-quirk unnecessary, using standard ACPI driver binding mechanisms to separate quirks from proper ECAM. Sadly, I think the train to do that has long left the station (with so many ACPI Arm systems out there and non-ECAM or not-quite-ECAM RCs using PNP0A08/PNP0A03 alone. ESXi, for example, ends up keying on the Table Ids (which is arguably even worse than the DT props)

Note 2: Given that DT has users in U-Boot and the BSDs (and potentially anywhere else), there's a long term hope to make DT bindings separate from Linux. To that end "linux,pcie-quirk" and "linux,pcie-nomsi" should probably be named something else (although I recognise that you're probably just wiring up something that already exists).

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware


From: Jeremy Linton <jeremy.linton@...>
Sent: Thursday, August 5, 2021 7:40 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Andrei Warkentin <awarkentin@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; Jeremy Linton <jeremy.linton@...>
Subject: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support
 
Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".

As the RPI isn't really ECAM this is a bit more
involved because the MADT can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MADT, so we need an additional way to tell linux
what it needs to know about this platform.

Signed-off-by: Jeremy Linton <jeremy.linton@...>
---
 Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
index 34474f13ef..3e7fd0d5b7 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -123,6 +123,15 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
         Name(_BBN, Zero) // PCI Base Bus Number
         Name(_CCA, 0)    // Mark the PCI noncoherent
 
+        Name (_DSD, Package () {
+          ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+              Package () { "linux,pcie-quirk", "bcm2711" },
+              Package () { "linux,pcie-nomsi", 1 },
+            }
+        })
+
+
         // Root Complex 0
         Device (RP0) {
          Name(_ADR, 0xF0000000)    // Dev 0, Func 0
@@ -176,6 +185,18 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
               2                               // SANITIZED_PCIE_MMIO_LEN + 1
               ,,,MMI1,,TypeTranslation
             )
+
+            QWordMemory ( // Root port registers, not to be used if SMCCC is utilized
+              ResourceConsumer, ,
+              MinFixed, MaxFixed,
+              NonCacheable, ReadWrite,        // cacheable? is that right?
+              0x00000000,                     // Granularity
+              0xFD500000,                     // Root port begin
+              0xFD509FFF,                     // Root port end
+              0x00000000,                     // no translation
+              0x0000A000,                     // size
+              ,,
+            )
           }) // end Name(RBUF)
 
           // Work around ASL's inability to add in a resource definition
--
2.13.7


Re: [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Andrei Warkentin
 

Hi Jeremy,

MADT -> MCFG (and in other patches as well, where you refer to MADT)

The other feedback that Ard provided makes sense to me as well.

A

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton@...>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@... <pete@...>; ardb+tianocore@... <ardb+tianocore@...>; Andrei Warkentin <awarkentin@...>; Sunny.Wang@... <Sunny.Wang@...>; samer.el-haj-mahmoud@... <samer.el-haj-mahmoud@...>; Jeremy Linton <jeremy.linton@...>
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
 
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@...>
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf     |   3 +
 Platform/RaspberryPi/AcpiTables/Pci.asl            | 237 +++++++++++++++++++++
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +
 3 files changed, 246 insertions(+)
 create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
   Pptt.aslc
   SsdtThermal.asl
   Xhci.asl
+  Pci.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
   gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
   gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)               __VA_ARGS__
+#define REMOVE_PARENTHESES(x)           ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN         REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH                 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq)                                 \
+  Device(Link_Name) {                                                         \
+      Name(_HID, EISAID("PNP0C0F"))                                           \
+      Name(_UID, Unique_Id)                                                   \
+      Name(_PRS, ResourceTemplate() {                                         \
+          Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
+      })                                                                      \
+      Method (_CRS, 0) { Return (_PRS) }                                      \
+      Method (_SRS, 1) { }                                                    \
+      Method (_DIS) { }                                                       \
+  }
+
+#define PRT_ENTRY(Address, Pin, Link)                                                            \
+        Package (4) {                                                                            \
+            Address,    /* uses the same format as _ADR */                                       \
+            Pin,        /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+            Link,       /* Interrupt allocated via Link device. */                               \
+            Zero        /* global system interrupt number (no used) */                           \
+          }
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+
+    Device (SCB0) {
+      Name (_HID, "ACPI0004")
+      Name (_UID, 0x0)
+      Name (_CCA, 0x0)
+
+      Method (_CRS, 0, Serialized) {
+        // Container devices with _DMA must have _CRS,
+        // meaning SCB0 to provide all resources that
+        // PCI0 consumes (except interrupts).
+        Name (RBUF, ResourceTemplate () {
+            QWordMemory (ResourceProducer,
+                ,
+                MinFixed,
+                MaxFixed,
+                NonCacheable,
+                ReadWrite,
+                0x0,
+                SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+                SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+                0x0,
+                0x1,                            // LEN
+                ,
+                ,
+                MMIO
+                )
+        })
+        CreateQwordField (RBUF, MMIO._MAX, MMBE)
+        CreateQwordField (RBUF, MMIO._LEN, MMLE)
+        Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+        Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+        Return (RBUF)
+      }
+
+      Name (_DMA, ResourceTemplate() {
+        // PCIe can only DMA to first 3GB with early SOC's
+        // But we keep the restriction on the later ones
+        // To avoid DMA translation problems.
+        QWordMemory (ResourceProducer,
+            ,
+            MinFixed,
+            MaxFixed,
+            NonCacheable,
+            ReadWrite,
+            0x0,
+            0x0,        // MIN
+            0xbfffffff, // MAX
+            0x0,        // TRA
+            0xc0000000, // LEN
+            ,
+            ,
+            )
+      })
+
+      //
+      // PCI Root Complex
+      //
+      LNK_DEVICE(1, LNKA, 175)
+      LNK_DEVICE(2, LNKB, 176)
+      LNK_DEVICE(3, LNKC, 177)
+      LNK_DEVICE(4, LNKD, 178)
+
+      Device(PCI0)
+      {
+        Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+        Name(_SEG, Zero) // PCI Segment Group number
+        Name(_BBN, Zero) // PCI Base Bus Number
+        Name(_CCA, 0)    // Mark the PCI noncoherent
+
+        // Root Complex 0
+        Device (RP0) {
+         Name(_ADR, 0xF0000000)    // Dev 0, Func 0
+        }
+
+        Name (_DMA, ResourceTemplate() {
+          QWordMemory (ResourceConsumer,
+            ,
+            MinFixed,
+            MaxFixed,
+            NonCacheable,
+            ReadWrite,
+            0x0,
+            0x0,        // MIN
+            0xbfffffff, // MAX
+            0x0,        // TRA
+            0xc0000000, // LEN
+            ,
+            ,
+            )
+        })
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+          ROOT_PRT_ENTRY(0, LNKA),   // INTA
+          ROOT_PRT_ENTRY(1, LNKB),   // INTB
+          ROOT_PRT_ENTRY(2, LNKC),   // INTC
+          ROOT_PRT_ENTRY(3, LNKD),   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {
+          Name (RBUF, ResourceTemplate () {
+            WordBusNumber ( // Bus numbers assigned to this root
+              ResourceProducer,
+              MinFixed, MaxFixed, PosDecode,
+              0,   // AddressGranularity
+              0,   // AddressMinimum - Minimum Bus Number
+              255, // AddressMaximum - Maximum Bus Number
+              0,   // AddressTranslation - Set to 0
+              256  // RangeLength - Number of Busses
+            )
+
+            QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+              ResourceProducer, PosDecode,
+              MinFixed, MaxFixed,
+              NonCacheable, ReadWrite,        //cacheable? is that right?
+              0x00000000,                     // Granularity
+              0,                              // SANITIZED_PCIE_PCI_MMIO_BEGIN
+              1,                              // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+              SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+              2                               // SANITIZED_PCIE_MMIO_LEN + 1
+              ,,,MMI1,,TypeTranslation
+            )
+          }) // end Name(RBUF)
+
+          // Work around ASL's inability to add in a resource definition
+          // or for that matter compute the min,max,len properly
+          CreateQwordField (RBUF, MMI1._MIN, MMIB)
+          CreateQwordField (RBUF, MMI1._MAX, MMIE)
+          CreateQwordField (RBUF, MMI1._TRA, MMIT)
+          CreateQwordField (RBUF, MMI1._LEN, MMIL)
+          Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+          Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+          Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+          Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+          Return (RBUF)
+        } // end Method(_CRS)
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Support Field value
+        Name(CTRL, Zero) // PCI _OSC Control Field value
+
+        // See [1] 6.2.10, [2] 4.5
+        Method(_OSC,4) {
+          // Note, This code is very similar to the code in the PCIe firmware
+          // specification which can be used as a reference
+          // Check for proper UUID
+          If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+            // Create DWord-adressable fields from the Capabilities Buffer
+            CreateDWordField(Arg3,0,CDW1)
+            CreateDWordField(Arg3,4,CDW2)
+            CreateDWordField(Arg3,8,CDW3)
+            // Save Capabilities DWord2 & 3
+            Store(CDW2,SUPP)
+            Store(CDW3,CTRL)
+            // Mask out Native HotPlug
+            And(CTRL,0x1E,CTRL)
+            // Always allow native PME, AER (no dependencies)
+            // Never allow SHPC (no SHPC controller in this system)
+            And(CTRL,0x1D,CTRL)
+
+            If(LNotEqual(Arg1,One)) { // Unknown revision
+              Or(CDW1,0x08,CDW1)
+            }
+
+            If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
+              Or(CDW1,0x10,CDW1)
+            }
+            // Update DWORD3 in the buffer
+            Store(CTRL,CDW3)
+            Return(Arg3)
+          } Else {
+            Or(CDW1,4,CDW1) // Unrecognized UUID
+            Return(Arg3)
+          }
+        } // End _OSC
+      } // PCI0
+    } //end SCB0
+  } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
     PcdToken(PcdXhciPci),
     NULL
   },
+  {
+    SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+    PcdToken(PcdXhciPci),
+    0,
+    NULL
+  },
 #endif
   { // DSDT
     SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7



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