Date   

[PATCH v3] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Jason Lou
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3508

Sort the CpuCacheInfo array by CPU package ID, core type, cache level
and cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 47 ++++++++=
+++++++++++-
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 2 +-
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 4 +-
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 27 ++++++++=
+++
UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 4 +-
5 files changed, 80 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpu=
Pkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..ae81ea9ce2 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,47 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+------------------------------------------=
--------------------------------------------+\n"));=0D
}=0D
=0D
+/**=0D
+ Function to compare CPU package ID, core type, cache level and cache typ=
e for use in QuickSort.=0D
+=0D
+ @param[in] Buffer1 pointer to CPU_CACHE_INFO poiner to comp=
are=0D
+ @param[in] Buffer2 pointer to second CPU_CACHE_INFO pointer=
to compare=0D
+=0D
+ @retval 0 Buffer1 equal to Buffer2=0D
+ @retval 1 Buffer1 is greater than Buffer2=0D
+ @retval -1 Buffer1 is less than Buffer2=0D
+**/=0D
+INTN=0D
+EFIAPI=0D
+CpuCacheInfoCompare (=0D
+ IN CONST VOID *Buffer1,=0D
+ IN CONST VOID *Buffer2=0D
+ )=0D
+{=0D
+ CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;=0D
+=0D
+ ZeroMem (&Comparator1, sizeof (Comparator1));=0D
+ ZeroMem (&Comparator2, sizeof (Comparator2));=0D
+=0D
+ Comparator1.Bits.Package =3D ((CPU_CACHE_INFO*)Buffer1)->Package;=0D
+ Comparator1.Bits.CoreType =3D ((CPU_CACHE_INFO*)Buffer1)->CoreType;=0D
+ Comparator1.Bits.CacheLevel =3D ((CPU_CACHE_INFO*)Buffer1)->CacheLevel;=
=0D
+ Comparator1.Bits.CacheType =3D ((CPU_CACHE_INFO*)Buffer1)->CacheType;=0D
+=0D
+ Comparator2.Bits.Package =3D ((CPU_CACHE_INFO*)Buffer2)->Package;=0D
+ Comparator2.Bits.CoreType =3D ((CPU_CACHE_INFO*)Buffer2)->CoreType;=0D
+ Comparator2.Bits.CacheLevel =3D ((CPU_CACHE_INFO*)Buffer2)->CacheLevel;=
=0D
+ Comparator2.Bits.CacheType =3D ((CPU_CACHE_INFO*)Buffer2)->CacheType;=0D
+=0D
+ if (Comparator1.Uint64 =3D=3D Comparator2.Uint64) {=0D
+ return 0;=0D
+ } else if (Comparator1.Uint64 > Comparator2.Uint64) {=0D
+ return 1;=0D
+ } else {=0D
+ return -1;=0D
+ }=0D
+}=0D
+=0D
/**=0D
Get the total number of package and package ID in the platform.=0D
=0D
@@ -325,6 +366,10 @@ CpuCacheInfoCollectCpuCacheInfoData (
if (*CacheInfoCount < LocalCacheInfoCount) {=0D
Status =3D EFI_BUFFER_TOO_SMALL;=0D
} else {=0D
+ //=0D
+ // Sort LocalCacheInfo array by CPU package ID, core type, cache level=
and cache type.=0D
+ //=0D
+ PerformQuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalC=
acheInfo), (SORT_COMPARE) CpuCacheInfoCompare);=0D
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheIn=
foCount);=0D
DEBUG_CODE (=0D
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);=
=0D
@@ -340,7 +385,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
}=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The array is sorted by CPU package ID, core=
type, cache level and cache type.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Incl=
ude/Library/CpuCacheInfoLib.h
index a66152bce0..3422997f54 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,7 @@ typedef struct {
} CPU_CACHE_INFO;=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The array is sorted by CPU package ID, core=
type, cache level and cache type.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
UefiBootServicesTableLib=0D
+ SortLib=0D
=0D
[Protocols]=0D
gEfiMpServiceProtocolGuid=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b=
/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index b6e6ae5bc5..26e1f46516 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -17,8 +17,35 @@
#include <Library/DebugLib.h>=0D
#include <Library/BaseMemoryLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/SortLib.h>=0D
#include <Library/CpuCacheInfoLib.h>=0D
=0D
+typedef union {=0D
+ struct {=0D
+ //=0D
+ // Type of the cache that this package's this type of logical processo=
r corresponds to.=0D
+ // Value =3D CPUID.04h:EAX[04:00]=0D
+ //=0D
+ UINT32 CacheType : 5;=0D
+ //=0D
+ // Level of the cache that this package's this type of logical process=
or corresponds to.=0D
+ // Value =3D CPUID.04h:EAX[07:05]=0D
+ //=0D
+ UINT32 CacheLevel : 3;=0D
+ //=0D
+ // Core type of logical processor.=0D
+ // Value =3D CPUID.1Ah:EAX[31:24]=0D
+ //=0D
+ UINT32 CoreType : 8;=0D
+ UINT32 Reserved : 16;=0D
+ //=0D
+ // Package number.=0D
+ //=0D
+ UINT32 Package;=0D
+ } Bits;=0D
+ UINT64 Uint64;=0D
+} CPU_CACHE_INFO_COMPARATOR;=0D
+=0D
typedef struct {=0D
//=0D
// Package ID, the information comes from=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
index 0c73015cac..0864497849 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
PeiServicesTablePointerLib=0D
+ SortLib=0D
=0D
[Ppis]=0D
gEdkiiPeiMpServices2PpiGuid=0D
--=20
2.28.0.windows.1


Re: [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Jason Lou
 

Sure, I will rename "Fields" and "Data64" in v3 patch.


Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Jeremy Linton
 

Hi,

On 8/6/21 8:42 AM, Ard Biesheuvel wrote:
On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Please split this into two patches.
Your talking about the linkup move, vs expanding the dev<0 check?

Ok.



---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));

- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;

Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7


Re: [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Ni, Ray
 

With the renaming, Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Ni, Ray
Sent: Friday, August 6, 2021 9:55 PM
To: Lou, Yun <Yun.Lou@intel.com>; devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul1 <Rahul1.Kumar@intel.com>
Subject: RE: [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

The patch looks good to me. 2 minor comments:
+ } Fields;
1. Can you rename to "Bits" to align to existing naming convention?


+ UINT64 Data64;
2. Can you rename to "Uint64"?


Re: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Friday, August 6, 2021 12:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin
<benjamin.you@intel.com>
Subject: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

This patch doesn't change the default behavior.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 ++++
UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
2 files changed, 6 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 002d2a8fa7..b4a30be381 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -98,6 +98,8 @@
DEFINE RTC_INDEX_REGISTER = 0x70

DEFINE RTC_TARGET_REGISTER = 0x71



+ DEFINE SERIAL_DRIVER_ENABLE = TRUE

+

[BuildOptions]

*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG

@@ -536,7 +538,9 @@
#

# ISA Support

#

+!if $(SERIAL_DRIVER_ENABLE) == TRUE

MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+!endif

!if $(PS2_KEYBOARD_ENABLE) == TRUE

OvmfPkg/SioBusDxe/SioBusDxe.inf

MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf

diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 041fed842c..b2cfb6b405 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -136,7 +136,9 @@ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
#

# ISA Support

#

+!if $(SERIAL_DRIVER_ENABLE) == TRUE

INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+!endif

!if $(PS2_KEYBOARD_ENABLE) == TRUE

INF OvmfPkg/SioBusDxe/SioBusDxe.inf

INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf

--
2.32.0.windows.2


Re: [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Friday, August 6, 2021 12:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin
<benjamin.you@intel.com>
Subject: [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Add the three PCDs as fixed at build PCD:
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
The default value is defined as Macro, so it can be passed in at build
command.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index bcedf1c746..ba54f2057f 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -91,6 +91,13 @@
DEFINE EMU_VARIABLE_ENABLE = TRUE

DEFINE DISABLE_RESET_SYSTEM = FALSE



+ # Dfine the maximum size of the capsule image without a reset flag that the platform can support.

+ DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa00000

+

+ # Define RTC related register.

+ DEFINE RTC_INDEX_REGISTER = 0x70

+ DEFINE RTC_TARGET_REGISTER = 0x71

+

[BuildOptions]

*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG

@@ -324,7 +331,9 @@
!else

gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F

!endif

-

+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|$(MAX_SIZE_NON_POPULATE_CAPSULE)

+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)

+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER)

#

# The following parameters are set by Library/PlatformHookLib

#

--
2.32.0.windows.2


Re: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Friday, August 6, 2021 12:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin
<benjamin.you@intel.com>
Subject: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Change the default value of the below PCDs to diable some legacy feature.
gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index d293211e46..002d2a8fa7 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -297,6 +297,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

## This PCD specified whether ACPI SDT protocol is installed.

gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE



[PcdsFixedAtBuild]

gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000

@@ -350,7 +352,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)



gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)

-

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0



################################################################################

#

--
2.32.0.windows.2


Re: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Friday, August 6, 2021 12:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin
<benjamin.you@intel.com>
Subject: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Define some PCDs as DynamicEX PCD to be used as global variable.
Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code
to set it in platformlib. That code was actually redundant.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c | 5 -----
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c | 4 ----
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/UefiPayloadPkg.dsc | 28 ++++++++++++++++++----------
5 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
index 72a17dc8a7..d8453e5957 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -75,11 +75,6 @@ PlatformHookSerialPortInitialize (
return Status;

}



- Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);

- if (RETURN_ERROR (Status)) {

- return Status;

- }

-

Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);

if (RETURN_ERROR (Status)) {

return Status;

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
index 2415d99c64..3eeb94d8fa 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -35,5 +35,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES

gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES

gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES

gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES

diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
index 6705f29505..bd433bdbe0 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
@@ -70,10 +70,6 @@ PlatformHookSerialPortInitialize (
if (RETURN_ERROR (Status)) {

return Status;

}

- Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate);

- if (RETURN_ERROR (Status)) {

- return Status;

- }



return RETURN_SUCCESS;

}

diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
index 41e05ddf54..2dfd8b1216 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
@@ -38,4 +38,3 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES

gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES

gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index ba54f2057f..d293211e46 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -308,11 +308,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE



gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0

-!if $(TARGET) == DEBUG

- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE

-!else

- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE

-!endif

gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE

gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE



@@ -352,11 +347,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)

gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)



- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)

- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)

- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)

gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)



gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)

@@ -369,6 +359,24 @@
################################################################################



[PcdsDynamicExDefault]

+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)

+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)

+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)

+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)

+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)

+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport

+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport

+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport

+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize

+!if $(TARGET) == DEBUG

+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE

+!else

+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE

+!endif

gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE

gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0

gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0

--
2.32.0.windows.2


Re: [PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Ni, Ray
 

The patch looks good to me. 2 minor comments:
+ } Fields;
1. Can you rename to "Bits" to align to existing naming convention?


+ UINT64 Data64;
2. Can you rename to "Uint64"?


Re: [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

Ard Biesheuvel
 

On Fri, 6 Aug 2021 at 10:30, Grzegorz Bernacki <gjb@semihalf.com> wrote:

This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file and BootDiscoveryPolicyUiLib should be added to
UiApp libraries.
... or the platform will be broken once we apply this patch, right? If
so, please propose patches for all platforms in edk2-platforms that
use this library - we can't just break them.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 5 +
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c | 96 +++++++++++++++++++-
2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 353d7a967b..86751b45f8 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -65,11 +65,15 @@

[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy

[Guids]
+ gBootDiscoveryPolicyMgrFormsetGuid
gEdkiiNonDiscoverableEhciDeviceGuid
gEdkiiNonDiscoverableUhciDeviceGuid
gEdkiiNonDiscoverableXhciDeviceGuid
+ gEfiBootManagerPolicyNetworkGuid
+ gEfiBootManagerPolicyConnectAllGuid
gEfiFileInfoGuid
gEfiFileSystemInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
@@ -79,6 +83,7 @@

[Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid
+ gEfiBootManagerPolicyProtocolGuid
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
gEfiLoadedImageProtocolGuid
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 5ceb23d822..4332c45bb7 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -2,9 +2,10 @@
Implementation for PlatformBootManagerLib library class interfaces.

Copyright (C) 2015-2016, Red Hat, Inc.
- Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2021, Semihalf All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -19,6 +20,7 @@
#include <Library/UefiBootManagerLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/BootManagerPolicy.h>
#include <Protocol/DevicePath.h>
#include <Protocol/EsrtManagement.h>
#include <Protocol/GraphicsOutput.h>
@@ -27,6 +29,7 @@
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PlatformBootManager.h>
+#include <Guid/BootDiscoveryPolicy.h>
#include <Guid/EventGroup.h>
#include <Guid/NonDiscoverableDevice.h>
#include <Guid/TtyTerm.h>
@@ -703,6 +706,91 @@ HandleCapsules (

#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "

+/**
+ This functions checks the value of BootDiscoverPolicy variable and
+ connect devices of class specified by that variable. Then it refreshes
+ Boot order for newly discovered boot device.
+
+ @retval EFI_SUCCESS Devices connected succesfully or connection
+ not required.
+ @retval others Return values from GetVariable(), LocateProtocol()
+ and ConnectDeviceClass().
+--*/
+STATIC
+EFI_STATUS
+BootDiscoveryPolicyHandler (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 DiscoveryPolicy;
+ UINTN Size;
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+ EFI_GUID *Class;
+
+ Size = sizeof (DiscoveryPolicy);
+ Status = gRT->GetVariable (
+ BOOT_DISCOVERY_POLICY_VAR,
+ &gBootDiscoveryPolicyMgrFormsetGuid,
+ NULL,
+ &Size,
+ &DiscoveryPolicy
+ );
+ if (Status == EFI_NOT_FOUND) {
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 (PcdBootDiscoveryPolicy));
+ if (Status == EFI_NOT_FOUND) {
+ return EFI_SUCCESS;
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
+ return EFI_SUCCESS;
+ }
+
+ switch (DiscoveryPolicy) {
+ case BDP_CONNECT_NET:
+ Class = &gEfiBootManagerPolicyNetworkGuid;
+ break;
+ case BDP_CONNECT_ALL:
+ Class = &gEfiBootManagerPolicyConnectAllGuid;
+ break;
+ default:
+ DEBUG ((
+ DEBUG_INFO,
+ "%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery Policy\n",
+ __FUNCTION__,
+ DiscoveryPolicy
+ ));
+ return EFI_SUCCESS;
+ }
+
+ Status = gBS->LocateProtocol (
+ &gEfiBootManagerPolicyProtocolGuid,
+ NULL,
+ (VOID **)&BMPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
+ "Driver connect will be skipped.\n", __FUNCTION__));
+ return Status;
+ }
+
+ Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
+ if (EFI_ERROR (Status)){
+ DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));
+ return Status;
+ }
+
+ EfiBootManagerRefreshAllBootOption();
+
+ return EFI_SUCCESS;
+}
+
/**
Do the platform specific action after the console is ready
Possible things that can be done in PlatformBootManagerAfterConsole:
@@ -753,6 +841,12 @@ PlatformBootManagerAfterConsole (
}
}

+ //
+ // Connect device specified by BootDiscoverPolicy variable and
+ // refresh Boot order for newly discovered boot devices
+ //
+ BootDiscoveryPolicyHandler ();
+
//
// On ARM, there is currently no reason to use the phased capsule
// update approach where some capsules are dispatched before EndOfDxe
--
2.25.1


Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Ard Biesheuvel
 

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Please split this into two patches.

---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));

- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;

Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7


Re: [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Ard Biesheuvel
 

On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:

Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl

[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
This can be done in a much simpler way - SynQuacer uses this, for instance

Name (_PRT, Package () {
Package () { 0xFFFF, 0, Zero, 222 }, // INTA
Package () { 0xFFFF, 1, Zero, 222 }, // INTB
Package () { 0xFFFF, 2, Zero, 222 }, // INTC
Package () { 0xFFFF, 3, Zero, 222 }, // INTD
})

+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
Even if this file and the xhci one should never be exposed to the OS
at the same time, can we please use unique UIDs?


+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
Can we just drop this?

+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
Do we need this method on the host bridge device as well as on the container?

+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7


Re: [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm machines

Etienne Carriere
 

Hello Liming

Thanks a lot for helping these patches to land.
I'm back on this and will address comments in a PATCH v5.

Regards,
etienne

On Wed, 28 Jul 2021 at 09:43, gaoliming <gaoliming@byosoft.com.cn> wrote:

Etienne:

I check the build log. Two build failure here. Can you update the patch to fix them?

1. Two modules are only for AARCH64. They should be specified in [Components.AARCH64] in ArmPkg\ArmPkg.dsc
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf

2. StandaloneMmCoreEntryPoint library class header file is changed. It should also be updated in StandaloneMmPkg\StandaloneMmPkg.dec

ERROR - Library StandaloneMmCoreEntryPoint with path Include/Library/AArch64/StandaloneMmCoreEntryPoint.h not found in package filesystem
ERROR - Library Header File Include/Library/Arm/StandaloneMmCoreEntryPoint.h not declared in package DEC StandaloneMmPkg/StandaloneMmPkg.dec

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ard
Biesheuvel
发送时间: 2021年7月28日 14:52
收件人: Sami Mujawar <Sami.Mujawar@arm.com>
抄送: gaoliming <gaoliming@byosoft.com.cn>; devel@edk2.groups.io;
Etienne Carriere <etienne.carriere@linaro.org>; Achin Gupta
<Achin.Gupta@arm.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>;
Jiewen Yao <jiewen.yao@intel.com>; Leif Lindholm <leif@nuviainc.com>;
Sughosh Ganu <sughosh.ganu@linaro.org>; nd <nd@arm.com>
主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for 32bit arm
machines

On Wed, 28 Jul 2021 at 08:41, Sami Mujawar <Sami.Mujawar@arm.com>
wrote:

Hi Liming,

I will look into this shortly.
I submitted it here

https://github.com/tianocore/edk2/pull/1823

but it triggered a CI failure that was not immediately obvious to me,
and I haven't had time yet to dig into it.



________________________________
From: gaoliming <gaoliming@byosoft.com.cn>
Sent: Wednesday, 28 July 2021, 7:33 am
To: devel@edk2.groups.io; gaoliming@byosoft.com.cn; ardb@kernel.org
Cc: Sami Mujawar; 'Etienne Carriere'; Achin Gupta; 'Ard Biesheuvel';
'Jiewen Yao'; 'Leif Lindholm'; 'Sughosh Ganu'; nd
Subject: 回复: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
32bit arm machines

Ard and Sami:
Will you help merge this patch set for 202108 stable tag?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 gaoliming
发送时间: 2021年7月20日 17:21
收件人: devel@edk2.groups.io; ardb@kernel.org
抄送: 'Sami Mujawar' <sami.mujawar@arm.com>; 'Etienne Carriere'
<etienne.carriere@linaro.org>; 'Achin Gupta' <achin.gupta@arm.com>;
'Ard
Biesheuvel' <ardb+tianocore@kernel.org>; 'Jiewen Yao'
<jiewen.yao@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>; 'Sughosh
Ganu' <sughosh.ganu@linaro.org>; 'nd' <nd@arm.com>
主题: 回复: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
32bit
arm machines

Ard:
Thanks! I have added this feature into
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Release-Planni
ng.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ard
Biesheuvel
发送时间: 2021年7月20日 15:46
收件人: edk2-devel-groups-io <devel@edk2.groups.io>; Liming Gao
(Byosoft
address) <gaoliming@byosoft.com.cn>
抄送: Sami Mujawar <sami.mujawar@arm.com>; Etienne Carriere
<etienne.carriere@linaro.org>; Achin Gupta <achin.gupta@arm.com>;
Ard
Biesheuvel <ardb+tianocore@kernel.org>; Jiewen Yao
<jiewen.yao@intel.com>; Leif Lindholm <leif@nuviainc.com>; Sughosh
Ganu
<sughosh.ganu@linaro.org>; nd <nd@arm.com>
主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
32bit
arm
machines

On Tue, 20 Jul 2021 at 04:01, gaoliming <gaoliming@byosoft.com.cn>
wrote:

Hi, all
This patch set has passed code review. How about merge it for this
stable tag edk2 202108?
OK, I will pick these up. Would you mind creating the entry for the
release notes?


Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表
Sami
Mujawar
发送时间: 2021年5月19日 17:58
收件人: Etienne Carriere <etienne.carriere@linaro.org>;
devel@edk2.groups.io
抄送: Achin Gupta <achin.gupta@arm.com>; Ard Biesheuvel
<ardb+tianocore@kernel.org>; Jiewen Yao <jiewen.yao@intel.com>;
Leif
Lindholm <leif@nuviainc.com>; Sughosh Ganu
<sughosh.ganu@linaro.org>;
nd@arm.com
主题: Re: [edk2-devel] [PATCH v4 5/5] StandaloneMmPkg: build for
32bit
arm
machines

Hi Etienn,

This patch looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 19/05/2021 08:14 AM, Etienne Carriere wrote:
This change allows to build StandaloneMmPkg components for
32bit
Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side
directory
for several components: StandaloneMmCpu,
StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b
and
64b
Arm targets.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
Changes since v3:
- Fix BuildOptions.ARM in StandaloneMmPkg.
- Remove Cc tags.

No change since v2

Changes since v1:
- ARM_SMC_ID_MM_COMMUNICATE 32b/64b agnostic helper ID
is
defined
in ArmStdSmc.h (see 1st commit in this series) instead of being
local to EventHandle.c.
- Fix void occurrence to VOID.
- Fix path in StandaloneMmPkg/StandaloneMmPkg.dsc
---
StandaloneMmPkg/Core/StandaloneMmCore.inf
| 2 +-
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64
=> }/EventHandle.c
| 5 +++--
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64
=> }/StandaloneMmCpu.c
| 2 +-
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64
=> }/StandaloneMmCpu.h
| 0
StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64
=> }/StandaloneMmCpu.inf
| 0
StandaloneMmPkg/Include/Library/{AArch64 =>
Arm}/StandaloneMmCoreEntryPoint.h
| 0
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64
=>
Arm}/CreateHobList.c |
2 +-
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64
=>
Arm}/SetPermissions.c | 2
+-
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64
=>
Arm}/StandaloneMmCoreEntryPoint.c | 16
++++++++--------
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCor
eEntryPoint.inf | 14
+++++++-------
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64
=>
Arm}/StandaloneMmCoreHobLib.c
|
0
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64
=>
Arm}/StandaloneMmCoreHobLibInternal.c
|
0
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreH
obLib.inf | 8
++++----
StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMm
MemLibInternal.c => ArmStandaloneMmMemLibInternal.c} | 9
++++++++-
StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.i
nf |
6
+++---
StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependenc
y.inf |
2 +-
StandaloneMmPkg/StandaloneMmPkg.dsc
| 12 ++++++++----
17 files changed, 46 insertions(+), 34 deletions(-)

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf
b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
PI_SPECIFICATION_VERSION = 0x00010032
ENTRY_POINT =
StandaloneMmMain

-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
ARM

[Sources]
StandaloneMmCore.c
diff --git
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 95%
rename from
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to
StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..165d696f99 100644
---
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@

Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2021, Linaro Limited

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -92,8 +93,8 @@ PiMmStandaloneArmTfCpuDriverEntry (
// receipt of a synchronous MM request. Use the Event ID to
distinguish
// between synchronous and asynchronous events.
//
- if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId)
&&
-
(ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 !=
EventId)) {
+ if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
+ (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId))
{
DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n",
EventId));
return EFI_INVALID_PARAMETER;
}
diff --git
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCp
u.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
similarity index 96%
rename from
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.
c
rename to
StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index d4590bcd19..10097f792f 100644
---
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCp
u.c
+++
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -10,7 +10,7 @@

#include <Base.h>
#include <Pi/PiMmCis.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/DebugLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/ArmLib.h>
diff --git
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCp
u.h
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
similarity index 100%
rename from
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.
h
rename to
StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
diff --git
a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCp
u.inf
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
similarity index 100%
rename from
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.i
nf
rename to
StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
diff --git
a/StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoin
t.h
b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
similarity index 100%
rename from
StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h
rename to
StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/Create
HobList.c
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHob
List.c
similarity index 97%
rename from
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHo
bList.c
rename to
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobLis
t.c
index 4d4cf3d5ff..85f8194687 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/Create
HobList.c
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHob
List.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier:
BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPer
missions.c
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissi
ons.c
similarity index 96%
rename from
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermi
ssions.c
rename to
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissio
ns.c
index 4a380df4a6..cd4b90823e 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPer
missions.c
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissi
ons.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier:
BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/Standa
loneMmCoreEntryPoint.c
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/Standalone
MmCoreEntryPoint.c
similarity index 94%
rename from
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/Standalo
neMmCoreEntryPoint.c
rename to
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneM
mCoreEntryPoint.c
index b445d6942e..49cf51a789 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/Standa
loneMmCoreEntryPoint.c
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/Standalone
MmCoreEntryPoint.c
@@ -10,7 +10,7 @@ SPDX-License-Identifier:
BSD-2-Clause-Patent

#include <PiMm.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>

#include <PiPei.h>
#include <Guid/MmramMemoryReserve.h>
@@ -182,13 +182,13 @@ DelegatedEventLoop (
}

if (FfaEnabled) {
- EventCompleteSvcArgs->Arg0 =
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ EventCompleteSvcArgs->Arg0 =
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
EventCompleteSvcArgs->Arg1 = 0;
EventCompleteSvcArgs->Arg2 = 0;
- EventCompleteSvcArgs->Arg3 =
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg3 =
ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg4 = SvcStatus;
} else {
- EventCompleteSvcArgs->Arg0 =
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg0 =
ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg1 = SvcStatus;
}
}
@@ -273,13 +273,13 @@ InitArmSvcArgs (
)
{
if (FeaturePcdGet (PcdFfaEnable)) {
- InitMmFoundationSvcArgs->Arg0 =
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 =
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
InitMmFoundationSvcArgs->Arg1 = 0;
InitMmFoundationSvcArgs->Arg2 = 0;
- InitMmFoundationSvcArgs->Arg3 =
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg3 =
ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg4 = *Ret;
} else {
- InitMmFoundationSvcArgs->Arg0 =
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 =
ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg1 = *Ret;
}
}
@@ -395,7 +395,7 @@ _ModuleEntryPoint (
//
ProcessModuleEntryPointList (HobStart);

- DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP 0x%lx\n",
(UINT64)
CpuDriverEntryPoint));
+ DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP %p\n", (VOID *)
CpuDriverEntryPoint));

finish:
if (Status == RETURN_UNSUPPORTED) {
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
index 4fa426f58e..1762586cfa 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMm
CoreEntryPoint.inf
@@ -21,10 +21,10 @@
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
(EBC
is
for
build only)
#

-[Sources.AARCH64]
- AArch64/StandaloneMmCoreEntryPoint.c
- AArch64/SetPermissions.c
- AArch64/CreateHobList.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreEntryPoint.c
+ Arm/SetPermissions.c
+ Arm/CreateHobList.c

[Sources.X64]
X64/StandaloneMmCoreEntryPoint.c
@@ -34,14 +34,14 @@
MdeModulePkg/MdeModulePkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec

-[Packages.AARCH64]
+[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec

[LibraryClasses]
BaseLib
DebugLib

-[LibraryClasses.AARCH64]
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
StandaloneMmMmuLib
ArmSvcLib

@@ -51,7 +51,7 @@
gEfiStandaloneMmNonSecureBufferGuid
gEfiArmTfCpuDriverEpDescriptorGuid

-[FeaturePcd.AARCH64]
+[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable

[BuildOptions]
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/Standalon
eMmCoreHobLib.c
b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneM
mCoreHobLib.c
similarity index 100%
rename from
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/Standalone
MmCoreHobLib.c
rename to
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmC
oreHobLib.c
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/Standalon
eMmCoreHobLibInternal.c
b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneM
mCoreHobLibInternal.c
similarity index 100%
rename from
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/Standalone
MmCoreHobLibInternal.c
rename to
StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmC
oreHobLibInternal.c
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCore
HobLib.inf
b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCore
HobLib.inf
index a2559920e8..34ed536480 100644
---
a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCore
HobLib.inf
+++
b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCore
HobLib.inf
@@ -22,7 +22,7 @@
LIBRARY_CLASS =
HobLib|MM_CORE_STANDALONE

#
-# VALID_ARCHITECTURES = X64 AARCH64
+# VALID_ARCHITECTURES = X64 AARCH64 ARM
#
[Sources.common]
Common.c
@@ -30,9 +30,9 @@
[Sources.X64]
X64/StandaloneMmCoreHobLib.c

-[Sources.AARCH64]
- AArch64/StandaloneMmCoreHobLib.c
- AArch64/StandaloneMmCoreHobLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreHobLib.c
+ Arm/StandaloneMmCoreHobLibInternal.c

[Packages]
MdePkg/MdePkg.dec
diff --git
a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneM
mMemLibInternal.c
b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMe
mLibInternal.c
similarity index 86%
rename from
StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMm
MemLibInternal.c
rename to
StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemL
ibInternal.c
index 4124959e04..fa7df46413 100644
---
a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneM
mMemLibInternal.c
+++
b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMe
mLibInternal.c
@@ -20,6 +20,13 @@
//
extern EFI_PHYSICAL_ADDRESS
mMmMemLibInternalMaximumSupportAddress;

+#ifdef MDE_CPU_AARCH64
+#define ARM_PHYSICAL_ADDRESS_BITS 36
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_PHYSICAL_ADDRESS_BITS 32
+#endif
+
/**
Calculate and save the maximum support address.

@@ -31,7 +38,7 @@
MmMemLibInternalCalculateMaximumSupportAddress (
{
UINT8 PhysicalAddressBits;

- PhysicalAddressBits = 36;
+ PhysicalAddressBits = ARM_PHYSICAL_ADDRESS_BITS;

//
// Save the maximum support address in one global variable
diff --git
a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib
.inf
b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib
.inf
index 062b0d7a11..b29d97a746 100644
---
a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib
.inf
+++
b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib
.inf
@@ -28,7 +28,7 @@
#
# The following information is for reference only and not
required
by
the
build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
ARM
#

[Sources.Common]
@@ -37,8 +37,8 @@
[Sources.IA32, Sources.X64]
X86StandaloneMmMemLibInternal.c

-[Sources.AARCH64]
- AArch64/StandaloneMmMemLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ ArmStandaloneMmMemLibInternal.c

[Packages]
MdePkg/MdePkg.dec
diff --git
a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDepende
ncy.inf
b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDepende
ncy.inf
index a2a059c5d6..ffb2a6d083 100644
---
a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDepende
ncy.inf
+++
b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDepende
ncy.inf
@@ -20,7 +20,7 @@
#
# The following information is for reference only and not
required
by
the
build tools.
#
-# VALID_ARCHITECTURES = AARCH64
+# VALID_ARCHITECTURES = AARCH64|ARM
#
#

diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc
b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 0c45df95e2..8012f93b7d 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -20,7 +20,7 @@
PLATFORM_VERSION = 1.0
DSC_SPECIFICATION = 0x00010011
OUTPUT_DIRECTORY =
Build/StandaloneMm
- SUPPORTED_ARCHITECTURES = AARCH64|X64
+ SUPPORTED_ARCHITECTURES = AARCH64|X64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT

@@ -60,7 +60,7 @@
StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryP
oint/StandaloneMmDriverEntryPoint.inf
VariableMmDependency|StandaloneMmPkg/Library/VariableMmDependenc
y/VariableMmDependency.inf

-[LibraryClasses.AARCH64]
+[LibraryClasses.AARCH64, LibraryClasses.ARM]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
StandaloneMmMmuLib|ArmPkg/Library/StandaloneMmMmuLib/ArmMmuSt
andaloneMmLib.inf
ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
@@ -118,8 +118,8 @@
StandaloneMmPkg/Library/StandaloneMmMemoryAllocationLib/Standalone
MmMemoryAllocationLib.inf
StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependenc
y.inf

-[Components.AARCH64]
-
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.i
nf
+[Components.AARCH64, Components.ARM]
+
StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/Standalone
MmPeCoffExtraActionLib.inf

##############################################################
#####################################
@@ -135,6 +135,10 @@
GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
-march=armv8-a+nofp -mstrict-align
GCC:*_*_*_CC_FLAGS = -mstrict-align

+[BuildOptions.ARM]
+GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
-march=armv7-a
+GCC:*_*_*_CC_FLAGS = -fno-stack-protector
+
[BuildOptions.X64]
MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
GCC:*_GCC*_*_DLINK_FLAGS = -z
common-page-size=0x1000























[PATCH v2] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Jason Lou
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3508

Sort the CpuCacheInfo array by CPU package ID, core type, cache level
and cache type.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 47 ++++++++=
+++++++++++-
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 2 +-
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 4 +-
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 27 ++++++++=
+++
UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 4 +-
5 files changed, 80 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpu=
Pkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..7474fe0f50 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,47 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+------------------------------------------=
--------------------------------------------+\n"));=0D
}=0D
=0D
+/**=0D
+ Function to compare CPU package ID, core type, cache level and cache typ=
e for use in QuickSort.=0D
+=0D
+ @param[in] Buffer1 pointer to CPU_CACHE_INFO poiner to comp=
are=0D
+ @param[in] Buffer2 pointer to second CPU_CACHE_INFO pointer=
to compare=0D
+=0D
+ @retval 0 Buffer1 equal to Buffer2=0D
+ @retval 1 Buffer1 is greater than Buffer2=0D
+ @retval -1 Buffer1 is less than Buffer2=0D
+**/=0D
+INTN=0D
+EFIAPI=0D
+CpuCacheInfoCompare (=0D
+ IN CONST VOID *Buffer1,=0D
+ IN CONST VOID *Buffer2=0D
+ )=0D
+{=0D
+ CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;=0D
+=0D
+ ZeroMem (&Comparator1, sizeof (Comparator1));=0D
+ ZeroMem (&Comparator2, sizeof (Comparator2));=0D
+=0D
+ Comparator1.Fields.Package =3D ((CPU_CACHE_INFO*)Buffer1)->Package;=0D
+ Comparator1.Fields.CoreType =3D ((CPU_CACHE_INFO*)Buffer1)->CoreType;=
=0D
+ Comparator1.Fields.CacheLevel =3D ((CPU_CACHE_INFO*)Buffer1)->CacheLevel=
;=0D
+ Comparator1.Fields.CacheType =3D ((CPU_CACHE_INFO*)Buffer1)->CacheType;=
=0D
+=0D
+ Comparator2.Fields.Package =3D ((CPU_CACHE_INFO*)Buffer2)->Package;=0D
+ Comparator2.Fields.CoreType =3D ((CPU_CACHE_INFO*)Buffer2)->CoreType;=
=0D
+ Comparator2.Fields.CacheLevel =3D ((CPU_CACHE_INFO*)Buffer2)->CacheLevel=
;=0D
+ Comparator2.Fields.CacheType =3D ((CPU_CACHE_INFO*)Buffer2)->CacheType;=
=0D
+=0D
+ if (Comparator1.Data64 =3D=3D Comparator2.Data64) {=0D
+ return 0;=0D
+ } else if (Comparator1.Data64 > Comparator2.Data64) {=0D
+ return 1;=0D
+ } else {=0D
+ return -1;=0D
+ }=0D
+}=0D
+=0D
/**=0D
Get the total number of package and package ID in the platform.=0D
=0D
@@ -325,6 +366,10 @@ CpuCacheInfoCollectCpuCacheInfoData (
if (*CacheInfoCount < LocalCacheInfoCount) {=0D
Status =3D EFI_BUFFER_TOO_SMALL;=0D
} else {=0D
+ //=0D
+ // Sort LocalCacheInfo array by CPU package ID, core type, cache level=
and cache type.=0D
+ //=0D
+ PerformQuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalC=
acheInfo), (SORT_COMPARE) CpuCacheInfoCompare);=0D
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheIn=
foCount);=0D
DEBUG_CODE (=0D
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);=
=0D
@@ -340,7 +385,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
}=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The array is sorted by CPU package ID, core=
type, cache level and cache type.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Incl=
ude/Library/CpuCacheInfoLib.h
index a66152bce0..3422997f54 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,7 @@ typedef struct {
} CPU_CACHE_INFO;=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The array is sorted by CPU package ID, core=
type, cache level and cache type.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
UefiBootServicesTableLib=0D
+ SortLib=0D
=0D
[Protocols]=0D
gEfiMpServiceProtocolGuid=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b=
/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index b6e6ae5bc5..6135215e5f 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -17,8 +17,35 @@
#include <Library/DebugLib.h>=0D
#include <Library/BaseMemoryLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/SortLib.h>=0D
#include <Library/CpuCacheInfoLib.h>=0D
=0D
+typedef union {=0D
+ struct {=0D
+ //=0D
+ // Type of the cache that this package's this type of logical processo=
r corresponds to.=0D
+ // Value =3D CPUID.04h:EAX[04:00]=0D
+ //=0D
+ UINT32 CacheType : 5;=0D
+ //=0D
+ // Level of the cache that this package's this type of logical process=
or corresponds to.=0D
+ // Value =3D CPUID.04h:EAX[07:05]=0D
+ //=0D
+ UINT32 CacheLevel : 3;=0D
+ //=0D
+ // Core type of logical processor.=0D
+ // Value =3D CPUID.1Ah:EAX[31:24]=0D
+ //=0D
+ UINT32 CoreType : 8;=0D
+ UINT32 Reserved : 16;=0D
+ //=0D
+ // Package number.=0D
+ //=0D
+ UINT32 Package;=0D
+ } Fields;=0D
+ UINT64 Data64;=0D
+} CPU_CACHE_INFO_COMPARATOR;=0D
+=0D
typedef struct {=0D
//=0D
// Package ID, the information comes from=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
index 0c73015cac..0864497849 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
PeiServicesTablePointerLib=0D
+ SortLib=0D
=0D
[Ppis]=0D
gEdkiiPeiMpServices2PpiGuid=0D
--=20
2.28.0.windows.1


[PATCH v1] UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo array

Jason Lou
 

From: Jason <yun.lou@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3508

Sort the CpuCacheInfo array by the core type values from largest to
smallest.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 67 ++++++++=
+++++++++++-
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 3 +-
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 4 +-
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 1 +
UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 4 +-
5 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpu=
Pkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..fa4850c4fe 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,69 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+------------------------------------------=
--------------------------------------------+\n"));=0D
}=0D
=0D
+/**=0D
+ Function to compare core type for use in QuickSort.=0D
+=0D
+ @param[in] Buffer1 pointer to core type poiner to compare=0D
+ @param[in] Buffer2 pointer to second core type pointer to c=
ompare=0D
+=0D
+ @retval 0 Buffer1 equal to Buffer2=0D
+ @retval 1 Buffer1 is less than Buffer2=0D
+ @retval -1 Buffer1 is greater than Buffer2=0D
+**/=0D
+INTN=0D
+EFIAPI=0D
+CpuCacheInfoCompareCoreType (=0D
+ IN CONST VOID *Buffer1,=0D
+ IN CONST VOID *Buffer2=0D
+ )=0D
+{=0D
+ if (((CPU_CACHE_INFO*)Buffer1)->CoreType =3D=3D ((CPU_CACHE_INFO*)Buffer=
2)->CoreType) {=0D
+ return 0;=0D
+ } else if (((CPU_CACHE_INFO*)Buffer1)->CoreType < ((CPU_CACHE_INFO*)Buff=
er2)->CoreType) {=0D
+ return 1;=0D
+ } else {=0D
+ return -1;=0D
+ }=0D
+}=0D
+=0D
+/**=0D
+ Sort CpuCacheInfo array by the core type values from largest to smallest=
.=0D
+=0D
+ @param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
+ @param[in] CpuCacheInfoCount The length of CpuCacheInfo array.=0D
+=0D
+**/=0D
+VOID=0D
+CpuCacheInfoSort (=0D
+ IN OUT CPU_CACHE_INFO *CpuCacheInfo,=0D
+ IN UINTN CpuCacheInfoCount=0D
+ )=0D
+{=0D
+ UINTN Index;=0D
+ UINTN NextIndex;=0D
+ UINT32 CurrentPackage;=0D
+ UINT8 CacheInfoCountPerPackage;=0D
+=0D
+ for (Index =3D 0; Index < CpuCacheInfoCount; Index +=3D CacheInfoCountPe=
rPackage) {=0D
+ //=0D
+ // Calculate the number of CpuCacheInfo current processor has.=0D
+ //=0D
+ CurrentPackage =3D CpuCacheInfo[Index].Package;=0D
+ CacheInfoCountPerPackage =3D 1;=0D
+ for (NextIndex =3D Index + 1; NextIndex < CpuCacheInfoCount; NextIndex=
++) {=0D
+ if (CurrentPackage =3D=3D CpuCacheInfo[NextIndex].Package) {=0D
+ CacheInfoCountPerPackage++;=0D
+ }=0D
+ }=0D
+=0D
+ //=0D
+ // Sort CpuCacheInfo for current processor by the core type values fro=
m largest to smallest.=0D
+ //=0D
+ PerformQuickSort (&CpuCacheInfo[Index], CacheInfoCountPerPackage, size=
of (*CpuCacheInfo), (SORT_COMPARE) CpuCacheInfoCompareCoreType);=0D
+ }=0D
+}=0D
+=0D
/**=0D
Get the total number of package and package ID in the platform.=0D
=0D
@@ -325,6 +388,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
if (*CacheInfoCount < LocalCacheInfoCount) {=0D
Status =3D EFI_BUFFER_TOO_SMALL;=0D
} else {=0D
+ CpuCacheInfoSort (LocalCacheInfo, LocalCacheInfoCount);=0D
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheIn=
foCount);=0D
DEBUG_CODE (=0D
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);=
=0D
@@ -340,7 +404,8 @@ CpuCacheInfoCollectCpuCacheInfoData (
}=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID =
from smallest to largest,=0D
+ by core type from largest to smallest and by cache level from smallest t=
o largest.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Incl=
ude/Library/CpuCacheInfoLib.h
index a66152bce0..d813f53bf7 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,8 @@ typedef struct {
} CPU_CACHE_INFO;=0D
=0D
/**=0D
- Get CpuCacheInfo data array.=0D
+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID =
from smallest to largest,=0D
+ by core type from largest to smallest and by cache level from smallest t=
o largest.=0D
=0D
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D
@param[in, out] CpuCacheInfoCount As input, point to the length of res=
ponse CpuCacheInfo array.=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
UefiBootServicesTableLib=0D
+ SortLib=0D
=0D
[Protocols]=0D
gEfiMpServiceProtocolGuid=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b=
/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index b6e6ae5bc5..089d259b3f 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -17,6 +17,7 @@
#include <Library/DebugLib.h>=0D
#include <Library/BaseMemoryLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/SortLib.h>=0D
#include <Library/CpuCacheInfoLib.h>=0D
=0D
typedef struct {=0D
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf b/Ue=
fiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
index 0c73015cac..0864497849 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#=0D
# Provides cache info for each package, core type, cache level and cache =
type.=0D
#=0D
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -25,6 +25,7 @@
=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
UefiCpuPkg/UefiCpuPkg.dec=0D
=0D
[LibraryClasses]=0D
@@ -33,6 +34,7 @@
BaseMemoryLib=0D
MemoryAllocationLib=0D
PeiServicesTablePointerLib=0D
+ SortLib=0D
=0D
[Ppis]=0D
gEdkiiPeiMpServices2PpiGuid=0D
--=20
2.28.0.windows.1


[PATCH EDK2 v1 1/1] BaseTools: Remove dependence of libuuid

wenyi,xie
 

The uuid.h only included in file GenFvInternalLib.c,
but no interface from libuuid is used in this file.
So remove this include and link to libuuid.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
---
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 5 -----
BaseTools/Source/C/DevicePath/GNUmakefile | 4 ----
BaseTools/Source/C/GenFv/GNUmakefile | 4 ----
BaseTools/Source/C/GenFw/GNUmakefile | 4 ----
BaseTools/Source/C/GenSec/GNUmakefile | 4 ----
5 files changed, 21 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6b2..80bab7fb1381 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -13,11 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Include files
//

-#if defined(__FreeBSD__)
-#include <uuid.h>
-#elif defined(__GNUC__)
-#include <uuid/uuid.h>
-#endif
#ifdef __GNUC__
#include <sys/stat.h>
#endif
diff --git a/BaseTools/Source/C/DevicePath/GNUmakefile b/BaseTools/Source/C/DevicePath/GNUmakefile
index 7ca08af9662d..1271555df8d5 100644
--- a/BaseTools/Source/C/DevicePath/GNUmakefile
+++ b/BaseTools/Source/C/DevicePath/GNUmakefile
@@ -18,7 +18,3 @@ ifeq ($(CYGWIN), CYGWIN)
LIBS += -L/lib/e2fsprogs -luuid
endif

-ifeq ($(LINUX), Linux)
- LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenFv/GNUmakefile b/BaseTools/Source/C/GenFv/GNUmakefile
index 7c7b95ba1be2..fd8f16903ade 100644
--- a/BaseTools/Source/C/GenFv/GNUmakefile
+++ b/BaseTools/Source/C/GenFv/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
LIBS += -L/lib/e2fsprogs -luuid
endif

-ifeq ($(LINUX), Linux)
- LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenFw/GNUmakefile b/BaseTools/Source/C/GenFw/GNUmakefile
index 76cda7e7a3f6..3b9a781b5cf6 100644
--- a/BaseTools/Source/C/GenFw/GNUmakefile
+++ b/BaseTools/Source/C/GenFw/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
LIBS += -L/lib/e2fsprogs -luuid
endif

-ifeq ($(LINUX), Linux)
- LIBS += -luuid
-endif
-
diff --git a/BaseTools/Source/C/GenSec/GNUmakefile b/BaseTools/Source/C/GenSec/GNUmakefile
index 9f0844c1b8fe..c2f440f21ebf 100644
--- a/BaseTools/Source/C/GenSec/GNUmakefile
+++ b/BaseTools/Source/C/GenSec/GNUmakefile
@@ -17,7 +17,3 @@ ifeq ($(CYGWIN), CYGWIN)
LIBS += -L/lib/e2fsprogs -luuid
endif

-ifeq ($(LINUX), Linux)
- LIBS += -luuid
-endif
-
--
2.20.1.windows.1


[PATCH EDK2 v1 0/1] BaseTools: Remove dependence of libuuid

wenyi,xie
 

Main Changes :
1.remove include uuid.h and link to libuuid. And try to build under linux, the building is sucessful.

Wenyi Xie (1):
BaseTools: Remove dependence of libuuid

BaseTools/Source/C/GenFv/GenFvInternalLib.c | 5 -----
BaseTools/Source/C/DevicePath/GNUmakefile | 4 ----
BaseTools/Source/C/GenFv/GNUmakefile | 4 ----
BaseTools/Source/C/GenFw/GNUmakefile | 4 ----
BaseTools/Source/C/GenSec/GNUmakefile | 4 ----
5 files changed, 21 deletions(-)

--
2.20.1.windows.1


Re: [PATCH v3 0/2] Relocate LINUX_EFI_INITRD_MEDIA_GUID to MdePkg

Ard Biesheuvel
 

On Thu, 5 Aug 2021 at 00:03, Jeff Brasen <jbrasen@nvidia.com> wrote:

Relocate LINUX_EFI_INITRD_MEDIA_GUID from OvmfPkg to MdePkg as it has
use outside of Ovmf applications

Jeff Brasen (2):
OvmfPkg: Remove Initrd LINUX_EFI_INITRD_MEDIA_GUID
MdePkg: add definition of LINUX_EFI_INITRD_MEDIA_GUID

MdePkg/MdePkg.dec | 5 ++++
OvmfPkg/OvmfPkg.dec | 1 -
MdePkg/Include/Guid/LinuxEfiInitrdMedia.h | 31 ++++++++++++++++++++++
OvmfPkg/Include/Guid/LinuxEfiInitrdMedia.h | 17 ------------
4 files changed, 36 insertions(+), 18 deletions(-)
create mode 100644 MdePkg/Include/Guid/LinuxEfiInitrdMedia.h
delete mode 100644 OvmfPkg/Include/Guid/LinuxEfiInitrdMedia.h

Merged as #1869

Thanks,


Re: [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

Sunny Wang
 

Looks good. Thanks, Greg.
Reviewed-by: Sunny Wang <sunny.wang@arm.com>

For others' reference, this patch is similar to the one below for Rasberry Pi that just got merged.
- https://edk2.groups.io/g/devel/message/78514
After merging this change, we should be able to easily enable "boot discovery policy" on other ARM platforms. For the platform that doesn't include BootManagerPolicyDxe driver but using ArmPkg PlatformBootManagerLib, it would just do nothing (the behavior will be kept the same as before).

Best Regards,
Sunny Wang

-----Original Message-----
From: Grzegorz Bernacki <gjb@semihalf.com>
Sent: Friday, August 6, 2021 4:30 PM
To: devel@edk2.groups.io
Cc: leif@nuviainc.com; ardb+tianocore@kernel.org; Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>; Sunny Wang <Sunny.Wang@arm.com>; mw@semihalf.com; upstream@semihalf.com; Grzegorz Bernacki <gjb@semihalf.com>
Subject: [PATCH] ArmPkg: Enable boot discovery policy for ARM package.

This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file and BootDiscoveryPolicyUiLib should be added to
UiApp libraries.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 5 +
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c | 96 +++++++++++++++++++-
2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 353d7a967b..86751b45f8 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -65,11 +65,15 @@

[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy

[Guids]
+ gBootDiscoveryPolicyMgrFormsetGuid
gEdkiiNonDiscoverableEhciDeviceGuid
gEdkiiNonDiscoverableUhciDeviceGuid
gEdkiiNonDiscoverableXhciDeviceGuid
+ gEfiBootManagerPolicyNetworkGuid
+ gEfiBootManagerPolicyConnectAllGuid
gEfiFileInfoGuid
gEfiFileSystemInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
@@ -79,6 +83,7 @@

[Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid
+ gEfiBootManagerPolicyProtocolGuid
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
gEfiLoadedImageProtocolGuid
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 5ceb23d822..4332c45bb7 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -2,9 +2,10 @@
Implementation for PlatformBootManagerLib library class interfaces.

Copyright (C) 2015-2016, Red Hat, Inc.
- Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2021, Semihalf All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -19,6 +20,7 @@
#include <Library/UefiBootManagerLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/BootManagerPolicy.h>
#include <Protocol/DevicePath.h>
#include <Protocol/EsrtManagement.h>
#include <Protocol/GraphicsOutput.h>
@@ -27,6 +29,7 @@
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PlatformBootManager.h>
+#include <Guid/BootDiscoveryPolicy.h>
#include <Guid/EventGroup.h>
#include <Guid/NonDiscoverableDevice.h>
#include <Guid/TtyTerm.h>
@@ -703,6 +706,91 @@ HandleCapsules (

#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "

+/**
+ This functions checks the value of BootDiscoverPolicy variable and
+ connect devices of class specified by that variable. Then it refreshes
+ Boot order for newly discovered boot device.
+
+ @retval EFI_SUCCESS Devices connected succesfully or connection
+ not required.
+ @retval others Return values from GetVariable(), LocateProtocol()
+ and ConnectDeviceClass().
+--*/
+STATIC
+EFI_STATUS
+BootDiscoveryPolicyHandler (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 DiscoveryPolicy;
+ UINTN Size;
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+ EFI_GUID *Class;
+
+ Size = sizeof (DiscoveryPolicy);
+ Status = gRT->GetVariable (
+ BOOT_DISCOVERY_POLICY_VAR,
+ &gBootDiscoveryPolicyMgrFormsetGuid,
+ NULL,
+ &Size,
+ &DiscoveryPolicy
+ );
+ if (Status == EFI_NOT_FOUND) {
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 (PcdBootDiscoveryPolicy));
+ if (Status == EFI_NOT_FOUND) {
+ return EFI_SUCCESS;
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
+ return EFI_SUCCESS;
+ }
+
+ switch (DiscoveryPolicy) {
+ case BDP_CONNECT_NET:
+ Class = &gEfiBootManagerPolicyNetworkGuid;
+ break;
+ case BDP_CONNECT_ALL:
+ Class = &gEfiBootManagerPolicyConnectAllGuid;
+ break;
+ default:
+ DEBUG ((
+ DEBUG_INFO,
+ "%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery Policy\n",
+ __FUNCTION__,
+ DiscoveryPolicy
+ ));
+ return EFI_SUCCESS;
+ }
+
+ Status = gBS->LocateProtocol (
+ &gEfiBootManagerPolicyProtocolGuid,
+ NULL,
+ (VOID **)&BMPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
+ "Driver connect will be skipped.\n", __FUNCTION__));
+ return Status;
+ }
+
+ Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
+ if (EFI_ERROR (Status)){
+ DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));
+ return Status;
+ }
+
+ EfiBootManagerRefreshAllBootOption();
+
+ return EFI_SUCCESS;
+}
+
/**
Do the platform specific action after the console is ready
Possible things that can be done in PlatformBootManagerAfterConsole:
@@ -753,6 +841,12 @@ PlatformBootManagerAfterConsole (
}
}

+ //
+ // Connect device specified by BootDiscoverPolicy variable and
+ // refresh Boot order for newly discovered boot devices
+ //
+ BootDiscoveryPolicyHandler ();
+
//
// On ARM, there is currently no reason to use the phased capsule
// update approach where some capsules are dispatched before EndOfDxe
--
2.25.1

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[PATCH] ArmPkg: Enable boot discovery policy for ARM package.

Grzegorz Bernacki
 

This commit adds code which check BootDiscoveryPolicy variable and
calls Boot Policy Manager Protocol to connect device specified by
the variable. To enable that mechanism for platform
EfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy PCD must be
added to DSC file and BootDiscoveryPolicyUiLib should be added to
UiApp libraries.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 5 +
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c | 96 +++++++++++++++++++-
2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 353d7a967b..86751b45f8 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -65,11 +65,15 @@

[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy

[Guids]
+ gBootDiscoveryPolicyMgrFormsetGuid
gEdkiiNonDiscoverableEhciDeviceGuid
gEdkiiNonDiscoverableUhciDeviceGuid
gEdkiiNonDiscoverableXhciDeviceGuid
+ gEfiBootManagerPolicyNetworkGuid
+ gEfiBootManagerPolicyConnectAllGuid
gEfiFileInfoGuid
gEfiFileSystemInfoGuid
gEfiFileSystemVolumeLabelInfoIdGuid
@@ -79,6 +83,7 @@

[Protocols]
gEdkiiNonDiscoverableDeviceProtocolGuid
+ gEfiBootManagerPolicyProtocolGuid
gEfiDevicePathProtocolGuid
gEfiGraphicsOutputProtocolGuid
gEfiLoadedImageProtocolGuid
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 5ceb23d822..4332c45bb7 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -2,9 +2,10 @@
Implementation for PlatformBootManagerLib library class interfaces.

Copyright (C) 2015-2016, Red Hat, Inc.
- Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2021, Semihalf All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -19,6 +20,7 @@
#include <Library/UefiBootManagerLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/BootManagerPolicy.h>
#include <Protocol/DevicePath.h>
#include <Protocol/EsrtManagement.h>
#include <Protocol/GraphicsOutput.h>
@@ -27,6 +29,7 @@
#include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PlatformBootManager.h>
+#include <Guid/BootDiscoveryPolicy.h>
#include <Guid/EventGroup.h>
#include <Guid/NonDiscoverableDevice.h>
#include <Guid/TtyTerm.h>
@@ -703,6 +706,91 @@ HandleCapsules (

#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "

+/**
+ This functions checks the value of BootDiscoverPolicy variable and
+ connect devices of class specified by that variable. Then it refreshes
+ Boot order for newly discovered boot device.
+
+ @retval EFI_SUCCESS Devices connected succesfully or connection
+ not required.
+ @retval others Return values from GetVariable(), LocateProtocol()
+ and ConnectDeviceClass().
+--*/
+STATIC
+EFI_STATUS
+BootDiscoveryPolicyHandler (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 DiscoveryPolicy;
+ UINTN Size;
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+ EFI_GUID *Class;
+
+ Size = sizeof (DiscoveryPolicy);
+ Status = gRT->GetVariable (
+ BOOT_DISCOVERY_POLICY_VAR,
+ &gBootDiscoveryPolicyMgrFormsetGuid,
+ NULL,
+ &Size,
+ &DiscoveryPolicy
+ );
+ if (Status == EFI_NOT_FOUND) {
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32 (PcdBootDiscoveryPolicy));
+ if (Status == EFI_NOT_FOUND) {
+ return EFI_SUCCESS;
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
+ } else if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) {
+ return EFI_SUCCESS;
+ }
+
+ switch (DiscoveryPolicy) {
+ case BDP_CONNECT_NET:
+ Class = &gEfiBootManagerPolicyNetworkGuid;
+ break;
+ case BDP_CONNECT_ALL:
+ Class = &gEfiBootManagerPolicyConnectAllGuid;
+ break;
+ default:
+ DEBUG ((
+ DEBUG_INFO,
+ "%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery Policy\n",
+ __FUNCTION__,
+ DiscoveryPolicy
+ ));
+ return EFI_SUCCESS;
+ }
+
+ Status = gBS->LocateProtocol (
+ &gEfiBootManagerPolicyProtocolGuid,
+ NULL,
+ (VOID **)&BMPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
+ "Driver connect will be skipped.\n", __FUNCTION__));
+ return Status;
+ }
+
+ Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
+ if (EFI_ERROR (Status)){
+ DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));
+ return Status;
+ }
+
+ EfiBootManagerRefreshAllBootOption();
+
+ return EFI_SUCCESS;
+}
+
/**
Do the platform specific action after the console is ready
Possible things that can be done in PlatformBootManagerAfterConsole:
@@ -753,6 +841,12 @@ PlatformBootManagerAfterConsole (
}
}

+ //
+ // Connect device specified by BootDiscoverPolicy variable and
+ // refresh Boot order for newly discovered boot devices
+ //
+ BootDiscoveryPolicyHandler ();
+
//
// On ARM, there is currently no reason to use the phased capsule
// update approach where some capsules are dispatched before EndOfDxe
--
2.25.1

5301 - 5320 of 84035