Date   

Re: [edk2-platforms] [PATCH] IpmiFeaturePkg: Fix standalone package build

Nate DeSimone
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate DeSimone
Sent: Thursday, August 5, 2021 11:28 AM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; KARPAGAVINAYAGAM, MANICKAVASAKAM <manickavasakamk@ami.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH] IpmiFeaturePkg: Fix standalone package build

Building the IpmiFeaturePkg standalone
(not as part of a platform build) currently fails because the IpmiPlatformHookLib was added but the reference to the NULL implementation of that LibraryClass was miseed.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc | 1 +
1 file changed, 1 insertion(+)

diff --git a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
index 05a7d4f0af..a6eccb428b 100644
--- a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
+++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeat
+++ ure.dsc
@@ -48,6 +48,7 @@
# IPMI Feature Package
#####################################
IpmiCommandLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiCommandLib/IpmiCommandLib.inf
+
+ IpmiPlatformHookLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiPla
+ tformHookLibNull/IpmiPlatformHookLibNull.inf

[LibraryClasses.common.PEI_CORE,LibraryClasses.common.PEIM]
#######################################
--
2.27.0.windows.1


Re: [edk2-platforms] [PATCH] IpmiFeaturePkg: Fix standalone package build

Michael D Kinney
 

Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

Mike

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate DeSimone
Sent: Thursday, August 5, 2021 11:28 AM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; KARPAGAVINAYAGAM, MANICKAVASAKAM
<manickavasakamk@ami.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH] IpmiFeaturePkg: Fix standalone package build

Building the IpmiFeaturePkg standalone
(not as part of a platform build) currently
fails because the IpmiPlatformHookLib was added
but the reference to the NULL implementation of
that LibraryClass was miseed.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc | 1 +
1 file changed, 1 insertion(+)

diff --git a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
index 05a7d4f0af..a6eccb428b 100644
--- a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
+++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
@@ -48,6 +48,7 @@
# IPMI Feature Package
#####################################
IpmiCommandLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiCommandLib/IpmiCommandLib.inf
+ IpmiPlatformHookLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiPlatformHookLibNull/IpmiPlatformHookLibNull.inf

[LibraryClasses.common.PEI_CORE,LibraryClasses.common.PEIM]
#######################################
--
2.27.0.windows.1





Re: [Patch 0/3] Ext4Pkg: Add Ext4Pkg

Michael D Kinney
 

Hi Pedro,

1) Ext4Pkg/Ext4Dxe/Ext4Dxe.inf:

* To be consistent with other drivers, BASE_NAME should be changed from Ext4 to Ext4Dxe.
* For proper dependency checking in incremental builds, please add the .h files to the [Sources] section

Ext4Disk.h
Ext4Dxe.h

2) There are a number of code style issues that need to be addressed. Can you fix those for V2?

3) I did a quick pass to find the IA32 NOOPT VS2019 issues. With the following changes, I can get it to build. Do not know if I introduced any functional changes by mistake.

diff --git a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
index 10a82d40a0..f2db93f02c 100644
--- a/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
+++ b/Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
@@ -61,7 +61,7 @@ Ext4ReadInode (
Partition,
Inode,
Partition->InodeSize,
- Ext4BlockToByteOffset (Partition, InodeTableStart) + InodeOffset * Partition->InodeSize
+ Ext4BlockToByteOffset (Partition, InodeTableStart) + MultU64x32 (InodeOffset, Partition->InodeSize)
);

if (EFI_ERROR (Status)) {
diff --git a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
index 1cafdd64cd..65109809c0 100644
--- a/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
+++ b/Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
@@ -45,7 +45,7 @@ Ext4ReadBlocks (
IN EXT4_BLOCK_NR BlockNumber
)
{
- return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * Partition->BlockSize, BlockNumber * Partition->BlockSize);
+ return Ext4ReadDiskIo (Partition, Buffer, NumberBlocks * Partition->BlockSize, MultU64x32 (BlockNumber, Partition->BlockSize));
}

/**
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
index d790e70be1..8aa584df14 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
@@ -445,6 +445,6 @@ typedef struct {
typedef UINT64 EXT4_BLOCK_NR;
typedef UINT32 EXT4_INO_NR;

-#define EXT4_INODE_SIZE(ino) (((UINT64)ino->i_size_hi << 32) | ino->i_size_lo)
+#define EXT4_INODE_SIZE(ino) (LShiftU64 (ino->i_size_hi, 32) | ino->i_size_lo)

#endif
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
index f6875c919e..a055a139e1 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
@@ -244,7 +244,7 @@ Ext4MakeBlockNumberFromHalfs (
)
{
// High might have garbage if it's not a 64 bit filesystem
- return Ext4Is64Bit (Partition) ? Low | ((UINT64)High << 32) : Low;
+ return Ext4Is64Bit (Partition) ? (Low | LShiftU64 (High, 32)) : Low;
}

/**
@@ -297,7 +297,7 @@ Ext4BlockToByteOffset (
IN EXT4_BLOCK_NR Block
)
{
- return Partition->BlockSize * Block;
+ return MultU64x32 (Block, Partition->BlockSize);
}

/**
@@ -333,7 +333,7 @@ Ext4InodeSize (
CONST EXT4_INODE *Inode
)
{
- return ((UINT64)Inode->i_size_hi << 32) | Inode->i_size_lo;
+ return (LShiftU64 (Inode->i_size_hi, 32) | Inode->i_size_lo);
}

/**
diff --git a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
index 102b12d613..fc0185285e 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
+++ b/Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
@@ -111,6 +111,8 @@ [Sources]
Collation.c
Crc32c.c
Crc16.c
+ Ext4Disk.h
+ Ext4Dxe.h

[Packages]
MdePkg/MdePkg.dec
diff --git a/Features/Ext4Pkg/Ext4Dxe/Extents.c b/Features/Ext4Pkg/Ext4Dxe/Extents.c
index db4bf5aa3f..8c9b4a4c75 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Extents.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Extents.c
@@ -210,7 +210,7 @@ Ext4ExtentIdxLeafBlock (
IN EXT4_EXTENT_INDEX *Index
)
{
- return ((UINT64)Index->ei_leaf_hi << 32) | Index->ei_leaf_lo;
+ return LShiftU64(Index->ei_leaf_hi, 32) | Index->ei_leaf_lo;
}

STATIC UINTN GetExtentRequests = 0;
diff --git a/Features/Ext4Pkg/Ext4Dxe/File.c b/Features/Ext4Pkg/Ext4Dxe/File.c
index 10dda64b16..71d36d1990 100644
--- a/Features/Ext4Pkg/Ext4Dxe/File.c
+++ b/Features/Ext4Pkg/Ext4Dxe/File.c
@@ -487,8 +487,8 @@ Ext4GetFilesystemInfo (
Info->BlockSize = Part->BlockSize;
Info->Size = NeededLength;
Info->ReadOnly = Part->ReadOnly;
- Info->VolumeSize = TotalBlocks * Part->BlockSize;
- Info->FreeSpace = FreeBlocks * Part->BlockSize;
+ Info->VolumeSize = MultU64x32 (TotalBlocks, Part->BlockSize);
+ Info->FreeSpace = MultU64x32 (FreeBlocks, Part->BlockSize);

if (VolumeName != NULL) {
StrCpyS (Info->VolumeLabel, VolNameLength + 1, VolumeName);
diff --git a/Features/Ext4Pkg/Ext4Dxe/Inode.c b/Features/Ext4Pkg/Ext4Dxe/Inode.c
index 304bf0c4a9..2a9f534d7e 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Inode.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Inode.c
@@ -154,7 +154,7 @@ Ext4Read (
UINT64 ExtentOffset;
UINTN ExtentMayRead;

- ExtentStartBytes = (((UINT64)Extent.ee_start_hi << 32) | Extent.ee_start_lo) * Partition->BlockSize;
+ ExtentStartBytes = MultU64x32 (LShiftU64 (Extent.ee_start_hi, 32) | Extent.ee_start_lo, Partition->BlockSize);
ExtentLengthBytes = Extent.ee_len * Partition->BlockSize;
ExtentLogicalBytes = (UINT64)Extent.ee_block * Partition->BlockSize;
ExtentOffset = CurrentSeek - ExtentLogicalBytes;
@@ -276,17 +276,17 @@ Ext4FilePhysicalSpace (
Blocks = File->Inode->i_blocks;

if(HugeFile) {
- Blocks |= ((UINT64)File->Inode->i_osd2.data_linux.l_i_blocks_high) << 32;
+ Blocks |= LShiftU64 (File->Inode->i_osd2.data_linux.l_i_blocks_high, 32);

// If HUGE_FILE is enabled and EXT4_HUGE_FILE_FL is set in the inode's flags, each unit
// in i_blocks corresponds to an actual filesystem block
if(File->Inode->i_flags & EXT4_HUGE_FILE_FL) {
- return Blocks * File->Partition->BlockSize;
+ return MultU64x32 (Blocks, File->Partition->BlockSize);
}
}

// Else, each i_blocks unit corresponds to 512 bytes
- return Blocks * 512;
+ return MultU64x32 (Blocks, 512);
}

// Copied from EmbeddedPkg at my mentor's request.
@@ -368,7 +368,7 @@ EpochToEfiTime (
UINT32 Nanoseconds = 0; \
\
if (Ext4InodeHasField (Inode, Field ## _extra)) { \
- SecondsEpoch |= ((UINT64)(Inode->Field ## _extra & EXT4_EXTRA_TIMESTAMP_MASK)) << 32; \
+ SecondsEpoch |= LShiftU64 ((UINT64)(Inode->Field ## _extra & EXT4_EXTRA_TIMESTAMP_MASK), 32); \
Nanoseconds = Inode->Field ## _extra >> 2; \
} \
EpochToEfiTime ((UINTN)SecondsEpoch, Time); \
diff --git a/Features/Ext4Pkg/Ext4Dxe/Superblock.c b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
index 18d8295a1f..88d01b62a8 100644
--- a/Features/Ext4Pkg/Ext4Dxe/Superblock.c
+++ b/Features/Ext4Pkg/Ext4Dxe/Superblock.c
@@ -161,7 +161,7 @@ Ext4OpenSuperblock (

DEBUG ((EFI_D_INFO, "Read only = %u\n", Partition->ReadOnly));

- Partition->BlockSize = 1024 << Sb->s_log_block_size;
+ Partition->BlockSize = (UINT32)LShiftU64 (1024, Sb->s_log_block_size);

// The size of a block group can also be calculated as 8 * Partition->BlockSize
if(Sb->s_blocks_per_group != 8 * Partition->BlockSize) {
@@ -195,7 +195,7 @@ Ext4OpenSuperblock (
}

NrBlocks = (UINTN)DivU64x32Remainder (
- Partition->NumberBlockGroups * Partition->DescSize,
+ MultU64x32 (Partition->NumberBlockGroups, Partition->DescSize),
Partition->BlockSize,
&NrBlocksRem
);
diff --git a/Features/Ext4Pkg/Ext4Pkg.dsc b/Features/Ext4Pkg/Ext4Pkg.dsc
index 62cb4e69cf..57f279a4d9 100644
--- a/Features/Ext4Pkg/Ext4Pkg.dsc
+++ b/Features/Ext4Pkg/Ext4Pkg.dsc
@@ -20,6 +20,8 @@ [Defines]
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT

+!include MdePkg/MdeLibs.dsc.inc
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES




Thanks,

Mike

-----Original Message-----
From: Pedro Falcato <pedro.falcato@gmail.com>
Sent: Friday, July 30, 2021 9:17 AM
To: devel@edk2.groups.io
Cc: Pedro Falcato <pedro.falcato@gmail.com>; Leif Lindholm <leif@nuviainc.com>; Kinney, Michael D
<michael.d.kinney@intel.com>; Bret Barkelew <Bret.Barkelew@microsoft.com>
Subject: [Patch 0/3] Ext4Pkg: Add Ext4Pkg

This patch-set adds Ext4Pkg, a package designed to hold various drivers and
utilities related to the EXT4 filesystem.

Right now, it holds a single read-only UEFI EXT4 driver (Ext4Dxe), which consumes the
DISK_IO, BLOCK_IO and DISK_IO2 protocols and produce EFI_FILE_PROTOCOL and
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL; this driver allows the mounting of EXT4 partitions and
the reading of their contents.

Relevant RFC discussion, which includes a more in-depth walkthrough of EXT4 internals and
driver limitations is available at https://edk2.groups.io/g/devel/topic/84368561.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>

Pedro Falcato (3):
Ext4Pkg: Add Ext4Pkg.dec and Ext4Pkg.uni.
Ext4Pkg: Add Ext4Dxe driver.
Ext4Pkg: Add .DSC file.

Features/Ext4Pkg/Ext4Dxe/BlockGroup.c | 208 ++++++
Features/Ext4Pkg/Ext4Dxe/Collation.c | 157 +++++
Features/Ext4Pkg/Ext4Dxe/Crc16.c | 75 ++
Features/Ext4Pkg/Ext4Dxe/Crc32c.c | 84 +++
Features/Ext4Pkg/Ext4Dxe/Directory.c | 492 ++++++++++++++
Features/Ext4Pkg/Ext4Dxe/DiskUtil.c | 83 +++
Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h | 450 ++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c | 454 +++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h | 942 ++++++++++++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf | 147 ++++
Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.uni | 15 +
Features/Ext4Pkg/Ext4Dxe/Extents.c | 616 +++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/File.c | 583 ++++++++++++++++
Features/Ext4Pkg/Ext4Dxe/Inode.c | 468 +++++++++++++
Features/Ext4Pkg/Ext4Dxe/Partition.c | 120 ++++
Features/Ext4Pkg/Ext4Dxe/Superblock.c | 257 +++++++
Features/Ext4Pkg/Ext4Pkg.dec | 17 +
Features/Ext4Pkg/Ext4Pkg.dsc | 68 ++
Features/Ext4Pkg/Ext4Pkg.uni | 14 +
19 files changed, 5250 insertions(+)
create mode 100644 Features/Ext4Pkg/Ext4Dxe/BlockGroup.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Collation.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Crc16.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Crc32c.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Directory.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/DiskUtil.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Disk.h
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.h
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.inf
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Ext4Dxe.uni
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Extents.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/File.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Inode.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Partition.c
create mode 100644 Features/Ext4Pkg/Ext4Dxe/Superblock.c
create mode 100644 Features/Ext4Pkg/Ext4Pkg.dec
create mode 100644 Features/Ext4Pkg/Ext4Pkg.dsc
create mode 100644 Features/Ext4Pkg/Ext4Pkg.uni

--
2.32.0


[edk2-platforms] [PATCH] IpmiFeaturePkg: Fix standalone package build

Nate DeSimone
 

Building the IpmiFeaturePkg standalone
(not as part of a platform build) currently
fails because the IpmiPlatformHookLib was added
but the reference to the NULL implementation of
that LibraryClass was miseed.

Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc | 1 +
1 file changed, 1 insertion(+)

diff --git a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
index 05a7d4f0af..a6eccb428b 100644
--- a/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
+++ b/Features/Intel/OutOfBandManagement/IpmiFeaturePkg/Include/IpmiFeature.dsc
@@ -48,6 +48,7 @@
# IPMI Feature Package
#####################################
IpmiCommandLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiCommandLib/IpmiCommandLib.inf
+ IpmiPlatformHookLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiPlatformHookLibNull/IpmiPlatformHookLibNull.inf

[LibraryClasses.common.PEI_CORE,LibraryClasses.common.PEIM]
#######################################
--
2.27.0.windows.1


[PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

Jeremy Linton
 

Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".

As the RPI isn't really ECAM this is a bit more
involved because the MADT can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MADT, so we need an additional way to tell linux
what it needs to know about this platform.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/Raspberry=
Pi/AcpiTables/Pci.asl
index 34474f13ef..3e7fd0d5b7 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -123,6 +123,15 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI=
4PCIE", 2)
Name(_BBN, Zero) // PCI Base Bus Number
Name(_CCA, 0) // Mark the PCI noncoherent
=20
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux,pcie-quirk", "bcm2711" },
+ Package () { "linux,pcie-nomsi", 1 },
+ }
+ })
+
+
// Root Complex 0
Device (RP0) {
Name(_ADR, 0xF0000000) // Dev 0, Func 0
@@ -176,6 +185,18 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI=
4PCIE", 2)
2 // SANITIZED_PCIE_MMIO_LEN=
+ 1
,,,MMI1,,TypeTranslation
)
+
+ QWordMemory ( // Root port registers, not to be used if SMCC=
C is utilized
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable? is that righ=
t?
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
}) // end Name(RBUF)
=20
// Work around ASL's inability to add in a resource definition
--=20
2.13.7


[PATCH 0/1] RPi: Add Linux PCIe quirk

Jeremy Linton
 

Linux has been refusing to use the generic SMC
PCIe config method, so we need to add a bit of additional
linux specific information to support a new rpi4 quirk.

This patch depends on the general XHCI/PCIe SMC set.

Jeremy Linton (1):
Platform/RaspberryPi: Add linux quirk support

Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

--=20
2.13.7


[edk2-platforms][PATCH v1 4/4] MinPlatformPkg/AcpiPlatform: Remove unused BoardAcpiTableLib

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

Removes an unnecessary library dependency.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 1 -
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 1 -
2 files changed, 2 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h=
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
index bd11f9e98864..827d273cc48a 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
@@ -31,7 +31,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
-#include <Library/BoardAcpiTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/AslUpdateLib.h>
#include <Library/PciSegmentInfoLib.h>
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.i=
nf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 7c5173b16d7f..b301a6519cb0 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -42,7 +42,6 @@ [LibraryClasses]
HobLib
PciSegmentInfoLib
AslUpdateLib
- BoardAcpiTableLib
=20
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
--=20
2.28.0.windows.1


[edk2-platforms][PATCH v1 3/4] MinPlatformPkg/AcpiPlatform: Set X_GPE1_BLK GAS structure to zeroes

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3534

Updates the code to be compatible with a recent Firmware Test Suite
(FWTS) fix that improves adherence to the ACPI Specification.

Relevant FWTS commit:
https://git.launchpad.net/fwts/commit/?
id=3D4ad3e374bf98931c84adcf6e523982b5ebb83748

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c=
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 6919e3196143..fe57ec4f7bb7 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1321,7 +1321,8 @@ PlatformUpdateTables (
FadtHeader->XGpe0Blk.Address =3D PcdGet16 (PcdAcpiGpe0BlockAddres=
s);
FadtHeader->XGpe1Blk.Address =3D PcdGet16 (PcdAcpiGpe1BlockAddres=
s);
if (FadtHeader->XGpe1Blk.Address =3D=3D 0) {
- FadtHeader->XGpe1Blk.AccessSize =3D 0;
+ FadtHeader->XGpe1Blk.AddressSpaceId =3D 0;
+ FadtHeader->XGpe1Blk.AccessSize =3D 0;
}
=20
DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table ));
--=20
2.28.0.windows.1


[edk2-platforms][PATCH v1 2/4] MinPlatformPkg/AcpiPlatform: Use CreatorId and CreatorRevision in headers

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3533

Updates InitializeHeader() to fill in the CreatorId and
CreatorRevision values from PCDs instead of being hardcoded to zero.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c=
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2fd..6919e3196143 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -572,8 +572,8 @@ InitializeHeader (
);
=20
Header->OemRevision =3D OemRevision;
- Header->CreatorId =3D 0;
- Header->CreatorRevision =3D 0;
+ Header->CreatorId =3D PcdGet32 (PcdAcpiDefaultCreatorId);
+ Header->CreatorRevision =3D PcdGet32 (PcdAcpiDefaultCreatorRevision);
=20
return EFI_SUCCESS;
}
--=20
2.28.0.windows.1


[edk2-platforms][PATCH v1 1/4] MinPlatformPkg/AcpiPlatform: Use PCD for WSMT OEM revision

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3532

Updates the table to use the standard MdeModulePkg PCD
PcdAcpiDefaultOemRevision to set the OEM revision in WSMT.

This allows board packages to easily configure the OEM
revision value.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c | 4 +---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 1 +
2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c b/=
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c
index 6880f47fa6a0..1c60ed28a1c4 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c
@@ -18,8 +18,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// WSMT Definitions
//
=20
-#define EFI_ACPI_OEM_WSMT_REVISION 0x00000001
-
EFI_ACPI_WSMT_TABLE Wsmt =3D {
{
EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE,
@@ -37,7 +35,7 @@ EFI_ACPI_WSMT_TABLE Wsmt =3D {
{ ' ', ' ', ' ', ' ', ' ', ' ' },
=20
0,
- EFI_ACPI_OEM_WSMT_REVISION,
+ FixedPcdGet32 (PcdAcpiDefaultOemRevision),
0,
0
},
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.i=
nf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 5d9c8cab50d5..7c5173b16d7f 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -47,6 +47,7 @@ [LibraryClasses]
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
=20
--=20
2.28.0.windows.1


[edk2-platforms][PATCH v1 0/4] MinPlatformPkg: AcpiPlatform bug fixes and improvements

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3532
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3533
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3534

This patch series groups together several bug fixes and
improvements to AcpiPlatform.

Note that the following patch from a different series that is on
the mailing list is currently required for MinPlatformPkg to
build:
https://edk2.groups.io/g/devel/message/78711

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

Michael Kubacki (4):
MinPlatformPkg/AcpiPlatform: Use PCD for WSMT OEM revision
MinPlatformPkg/AcpiPlatform: Use CreatorId and CreatorRevision in
headers
MinPlatformPkg/AcpiPlatform: Set X_GPE1_BLK GAS structure to zeroes
MinPlatformPkg/AcpiPlatform: Remove unused BoardAcpiTableLib

Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 7 ++++-=
--
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c | 4 +---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 1 -
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 2 +-
4 files changed, 6 insertions(+), 8 deletions(-)

--=20
2.28.0.windows.1


[PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4

Jeremy Linton
 

The CM4 has a number of carrier boards with PCIe
slots. With the PCIe changes in place its quite
possible to setup a NVMe root device. Lets allow
people to boot from it.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++
2 files changed, 10 insertions(+)

diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RP=
i4/RPi4.dsc
index babcbb2f41..25c29a0fbf 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -754,6 +754,11 @@
}
=20
#
+ # NVMe boot devices
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RP=
i4/RPi4.fdf
index 3534cd3dc3..0c782d2f35 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.fdf
+++ b/Platform/RaspberryPi/RPi4/RPi4.fdf
@@ -283,6 +283,11 @@ READ_LOCK_STATUS =3D TRUE
INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
=20
#
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# SCSI Bus and Disk Driver
#
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
--=20
2.13.7


[PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Jeremy Linton
 

The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));

- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;

Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7


[PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Jeremy Linton
 

Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++=
++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Ra=
spberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
=20
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/Raspberry=
Pi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO=
_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_M=
MIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_M=
EM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) =
\
+ Device(Link_Name) { =
\
+ Name(_HID, EISAID("PNP0C0F")) =
\
+ Name(_UID, Unique_Id) =
\
+ Name(_PRS, ResourceTemplate() { =
\
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { ir=
q } \
+ }) =
\
+ Method (_CRS, 0) { Return (_PRS) } =
\
+ Method (_SRS, 1) { } =
\
+ Method (_DIS) { } =
\
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) =
\
+ Package (4) { =
\
+ Address, /* uses the same format as _ADR */ =
\
+ Pin, /* The PCI pin number of the device (0-INTA, 1-I=
NTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ =
\
+ Zero /* global system interrupt number (no used) */ =
\
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,=20
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right=
?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO=
_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN=
+ SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO=
_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN=
+ 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, M=
MIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe fir=
mware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))=
) {
+ // Create DWord-adressable fields from the Capabilities Buff=
er
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platfor=
m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--=20
2.13.7


[PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT

Jeremy Linton
 

Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--=
------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Ra=
spberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
=20
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/Raspberr=
yPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI"=
, 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL =3D=3D 4)
- include ("Xhci.asl")
-#endif
=20
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/Raspberr=
yPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
=20
#include <IndustryStandard/Bcm2711.h>
=20
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
=20
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
=20
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
=20
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
=20
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug =3D "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platfor=
m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL =3D=3D 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--=20
2.13.7


[PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu

Jeremy Linton
 

Arm has standardized a PCI SMC conduit that can be used
to access the PCI config space in a standardized way. This
functionality doesn't yet exist in many OS/Distro's. Lets
add another advanced config item that allows the user
to toggle between presenting the XHCI on the base RPi4
as a platform device, or presenting this newer PCIe
conduit. The CM4 doesn't have an attached XHCI controller
soldered to the PCIe, so we hide the menu and only allow
PCIe mode.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++=
++++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
8 files changed, 84 insertions(+)

diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platfor=
m/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 9e78cb47ad..87f6b4e7bb 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[];
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
STATIC UINT32 mModelFamily =3D 0;
STATIC UINT32 mModelInstalledMB =3D 0;
+STATIC UINT32 mModelRevision =3D 0;
=20
STATIC EFI_MAC_ADDRESS mMacAddress;
=20
@@ -271,6 +272,40 @@ SetupVariables (
ASSERT_EFI_ERROR (Status);
}
=20
+ if (mModelFamily >=3D 4) {
+ if (((mModelRevision >> 4) & 0xFF) =3D=3D 0x14) {
+ /*
+ * Enable PCIe by default on CM4
+ */
+ Status =3D PcdSet32S (PcdXhciPci, 2);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ Size =3D sizeof (UINT32);
+ Status =3D gRT->GetVariable (L"XhciPci",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status) || (Var32 =3D=3D 0)) {
+ /*
+ * Enable XHCI by default
+ */
+ Status =3D PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ /*=20
+ * Enable PCIe
+ */
+ Status =3D PcdSet32S (PcdXhciPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ } else {
+ /*=20
+ * Disable PCIe and XHCI
+ */
+ Status =3D PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ }
+
Size =3D sizeof (AssetTagVar);
Status =3D gRT->GetVariable (L"AssetTag",
&gConfigDxeFormSetGuid,
@@ -888,6 +923,13 @@ ConfigInitialize (
DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d M=
B\n", mModelInstalledMB));
}
=20
+ Status =3D mFwProtocol->GetModelRevision (&mModelRevision);
+ if (Status !=3D EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n",=
Status));
+ } else {
+ DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevi=
sion));
+ }
+
Status =3D SetupVariables ();
if (Status !=3D EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status));
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platf=
orm/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index 4bb2d08550..e6e22ad82e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -94,6 +94,7 @@
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
gRaspberryPiTokenSpaceGuid.PcdFanTemp
gRaspberryPiTokenSpaceGuid.PcdUartInUse
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci
=20
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Pl=
atform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 466fa852cb..5ec17072c3 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -57,6 +57,11 @@
#string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperat=
ure"
#string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
=20
+#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe"
+#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB =
platform device or PCIe bridge"
+#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
+#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system As=
set Tag"
=20
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Pl=
atform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index fa34eab809..18b3ec726e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -56,6 +56,11 @@ formset
name =3D FanTemp,
guid =3D CONFIGDXE_FORM_SET_GUID;
=20
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTI=
ME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name =3D XhciPci,
+ guid =3D CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute =3D EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTI=
ME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name =3D SystemTableMode,
@@ -212,6 +217,18 @@ formset
default =3D 60,
endnumeric;
endif;
+
+ suppressif ideqval XhciPci.Value =3D=3D 2;
+ grayoutif NOT ideqval SystemTableMode.Mode =3D=3D SYSTEM_TABLE=
_MODE_ACPI;
+ oneof varid =3D XhciPci.Value,
+ prompt =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
+ help =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
+ flags =3D NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUI=
RED,
+ option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), v=
alue =3D 0, flags =3D DEFAULT;
+ option text =3D STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), v=
alue =3D 1, flags =3D 0;
+ endoneof;
+ endif;
+ endif;
#endif
string varid =3D AssetTag.AssetTag,
prompt =3D STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/Raspber=
ryPi/Include/ConfigVars.h
index 142317985a..a5b32b5284 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -77,6 +77,10 @@ typedef struct {
} ADVANCED_FANTEMP_VARSTORE_DATA;
=20
typedef struct {
+ UINT32 Value;
+} ADVANCED_XHCIPCI_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RP=
i3/RPi3.dsc
index 1c8a5408e7..6ab5d1ae6d 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -520,6 +520,12 @@
=20
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspbe=
rryPiTokenSpaceGuid|0x0|0
=20
+ # Select XHCI/PCIe mode (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid=
|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RP=
i4/RPi4.dsc
index dcf9bb5f11..babcbb2f41 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -536,6 +536,14 @@
=20
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspbe=
rryPiTokenSpaceGuid|0x0|0
=20
+ # Select XHCI/PCIe mode
+ #
+ # 0 - XHCI Enabled (default on !cm4)
+ # 1 - PCIe Enabled
+ # 2 - PCIe Enabled (default on cm4)
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid=
|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/=
RaspberryPi.dec
index 2ca25ff9e6..797be59274 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -71,3 +71,4 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
--=20
2.13.7


[PATCH 0/5] RPi4: Enable ACPI PCIe conduit

Jeremy Linton
 

A new Arm standard DEN0115A specifies how
platforms that don't have standard ECAM can
use the firmware to handle config read/write
operations. This is mostly implemented in TFA
but UEFI needs to assure that there is a
description of the root complex in the ACPI
namespace.

This set adds that description based on
a new menu item which toggles between XHCI
platform description and PCIe via a BDS
menu selection on the RPi4. The CM4 is really
the platform that needs this as it has a PCIe
slot. On that platform PCIe is enabled by default.

Jeremy Linton (5):
Platform/RaspberryPi: Add XHCI/PCI selection menu
Platform/RaspberryPi: break XHCI into its own SSDT
Platform/RaspberryPi: Add PCIe SSDT
Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
Platform/RaspberryPi: Enable NVMe boot on cm4

Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 4 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 -
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++=
++++++
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 +--
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 56 +++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 ++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 +
Platform/RaspberryPi/RPi4/RPi4.dsc | 13 ++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +
Platform/RaspberryPi/RaspberryPi.dec | 1 +
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 ++-
15 files changed, 388 insertions(+), 28 deletions(-)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

--=20
2.13.7


[PATCH v2 13/13] MdePkg: Fix broken coding style in Acpi64.h

Chris Jones
 

Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Fix a coding style issue raised by EccCheck. This issue (error code
7008) has been fixed by moving a nested union out of its structure.

Also add Acpi64.h to the "IgnoreFiles" list to stop the CI flagging
naming errors present prior to ACPI 64.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---

Notes:
v2:
- Remove EFI_ACPI_6_4_GIC_STRUCTURE field name changes. [Liming]
- Add Acpi64.h to IgnoreFiles list in MdePkg.ci.yaml. [Liming]

MdePkg/Include/IndustryStandard/Acpi64.h | 27 +++++++++++---------
MdePkg/MdePkg.ci.yaml | 2 ++
2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h
index c905db93fabb6faa553dd49a9fed886437dd4daf..3a91302f8c0e71d4951d27aac35322073219c836 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -788,22 +788,25 @@ typedef struct {
} EFI_ACPI_6_4_DEVICE_HANDLE_PCI;

///
-/// Generic Initiator Affinity Structure
+/// Device Handle
///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT8 Reserved1;
- UINT8 DeviceHandleType;
- UINT32 ProximityDomain;
-
- union {
+typedef union {
EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;
EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;
- } DeviceHandle;
+} EFI_ACPI_6_4_DEVICE_HANDLE;

- UINT32 Flags;
- UINT8 Reserved2[4];
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT8 Reserved1;
+ UINT8 DeviceHandleType;
+ UINT32 ProximityDomain;
+ EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;
+ UINT32 Flags;
+ UINT8 Reserved2[4];
} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE;

///
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 15931eaccabff7334a8b839c438d4d9a907b4194..98eaea1c824863a89bf2e73b8312fe89881fb3c1 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -3,6 +3,7 @@
#
# Copyright (c) Microsoft Corporation
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
{
@@ -19,6 +20,7 @@
],
## Both file path and directory path are accepted.
"IgnoreFiles": [
+ "Include/IndustryStandard/Acpi64.h"
]
},
## options defined ci/Plugin/CompilerPlugin
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v2 07/13] MdePkg: Add flags and MinTransferSize to Generic Initiator

Chris Jones
 

Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.59, Section 5.2.27.1 & Section 5.2.27.4
- Mantis ID 1991 (https://mantis.uefi.org/mantis/view.php?id=1991)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
MdePkg/Include/IndustryStandard/Acpi64.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h
index b8be65c5e1c861b2a85b81f585ffdb40a178e368..ffa819d83a95ba55784a639b309b8bac8263be6a 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -783,7 +783,8 @@ typedef struct {
/// Generic Initiator Affinity Structure Flags. All other bits are reserved
/// and must be 0.
///
-#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
+#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED BIT0
+#define EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ARCHITECTURAL_TRANSACTIONS BIT1

///
/// System Locality Distance Information Table (SLIT).
@@ -2079,7 +2080,8 @@ typedef struct {
///
typedef struct {
UINT8 MemoryHierarchy:4;
- UINT8 Reserved:4;
+ UINT8 AccessAttributes:2;
+ UINT8 Reserved:2;
} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;

///
@@ -2091,7 +2093,8 @@ typedef struct {
UINT32 Length;
EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;
UINT8 DataType;
- UINT8 Reserved1[2];
+ UINT8 MinTransferSize;
+ UINT8 Reserved1;
UINT32 NumberOfInitiatorProximityDomains;
UINT32 NumberOfTargetProximityDomains;
UINT8 Reserved2[4];
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v2 12/13] MdePkg: Add Cache ID to PPTT

Chris Jones
 

Bugzilla: 3516 (https://bugzilla.tianocore.org/show_bug.cgi?id=3516)

Make changes to ACPI 6.4 header according to the latest specification:
- ACPI 6.4 January 2021, Table 5.137, Table 5.140, Table 5.141
- Mantis ID 2138 (https://mantis.uefi.org/mantis/view.php?id=2138)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
MdePkg/Include/IndustryStandard/Acpi64.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h
index 4faed17a9e99525f9e09f0eac884264ba31ca47d..c905db93fabb6faa553dd49a9fed886437dd4daf 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -2603,7 +2603,7 @@ typedef struct {
///
/// PPTT Revision (as defined in ACPI 6.4 spec.)
///
-#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
+#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03

///
/// PPTT types
@@ -2689,7 +2689,8 @@ typedef struct {
UINT32 CacheTypeValid:1;
UINT32 WritePolicyValid:1;
UINT32 LineSizeValid:1;
- UINT32 Reserved:25;
+ UINT32 CacheIdValid:1;
+ UINT32 Reserved:24;
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS;

///
@@ -2728,6 +2729,7 @@ typedef struct {
UINT8 Associativity;
EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;
UINT16 LineSize;
+ UINT32 CacheId;
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;

///
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")

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