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[edk2-platforms][PATCH v5 43/46] KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Update for new SPI PPI API
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates usage of gPchSpiPpiGuid to use the new interface that identifies SPI flash regions by GUID. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> --- Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.c | 4 ++-- Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.inf | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLib= SpiFlash/PeiSerialPortLibSpiFlash.c b/Platform/Intel/KabylakeOpenBoardPkg= /Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c index fc48bdc6fccb..fe8883a8af29 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlas= h/PeiSerialPortLibSpiFlash.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlas= h/PeiSerialPortLibSpiFlash.c @@ -98,7 +98,7 @@ SerialPortWrite ( LinearOffset =3D (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase= ) - FixedPcdGet32 (PcdFlashAreaBaseAddress)); Status =3D PchSpiPpi->FlashErase ( PchSpiPpi, - FlashRegionBios, + &gFlashRegionBiosGuid, LinearOffset, NvMessageAreaSize ); @@ -118,7 +118,7 @@ SerialPortWrite ( =20 Status =3D PchSpiPpi->FlashWrite ( PchSpiPpi, - FlashRegionBios, + &gFlashRegionBiosGuid, LinearOffset, BytesWritten, (UINT8 *) &Buffer[SourceBufferOffset] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLib= SpiFlash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/KabylakeOpenBoardP= kg/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf index b959cd1f4612..b8ae214f0920 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlas= h/PeiSerialPortLibSpiFlash.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlas= h/PeiSerialPortLibSpiFlash.inf @@ -43,6 +43,7 @@ [Ppis] gPchSpiPpiGuid =20 [Guids] + gFlashRegionBiosGuid gSpiFlashDebugHobGuid =20 [Pcd] --=20 2.28.0.windows.1
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[edk2-platforms][PATCH v5 32/46] MinPlatformPkg: Remove SpiFlashCommonLibNull
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 The library instance has moved to IntelSiliconPkg. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Liming Gao <gaoliming@...> Cc: Eric Dong <eric.dong@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> Reviewed-by: Chasel Chiu <chasel.chiu@...> --- Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFla= shCommonLibNull.c | 101 -------------------- Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFla= shCommonLibNull.inf | 29 ------ Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommonLib.h = | 98 ------------------- Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec = | 2 - Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc = | 4 - 5 files changed, 234 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLi= bNull/SpiFlashCommonLibNull.c b/Platform/Intel/MinPlatformPkg/Flash/Libra= ry/SpiFlashCommonLibNull/SpiFlashCommonLibNull.c deleted file mode 100644 index 403b16a1b421..000000000000 --- a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/S= piFlashCommonLibNull.c +++ /dev/null @@ -1,101 +0,0 @@ -/** @file - Null Library instance of SPI Flash Common Library Class - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include <Uefi.h> -#include <Library/DebugLib.h> - -/** - Enable block protection on the Serial Flash device. - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashLock ( - VOID - ) -{ - return EFI_SUCCESS; -} - -/** - Read NumBytes bytes of data from the address specified by - PAddress into Buffer. - - @param[in] Address The starting physical address of the rea= d. - @param[in,out] NumBytes On input, the number of bytes to read. O= n output, the number - of bytes actually read. - @param[out] Buffer The destination data buffer for the read= . - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashRead ( - IN UINTN Address, - IN OUT UINT32 *NumBytes, - OUT UINT8 *Buffer - ) -{ - ASSERT(FALSE); - return EFI_SUCCESS; -} - -/** - Write NumBytes bytes of data from Buffer to the address specified by - PAddresss. - - @param[in] Address The starting physical address of the w= rite. - @param[in,out] NumBytes On input, the number of bytes to write= . On output, - the actual number of bytes written. - @param[in] Buffer The source data buffer for the write. - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashWrite ( - IN UINTN Address, - IN OUT UINT32 *NumBytes, - IN UINT8 *Buffer - ) -{ - ASSERT(FALSE); - return EFI_SUCCESS; -} - -/** - Erase the block starting at Address. - - @param[in] Address The starting physical address of the block= to be erased. - This library assume that caller garantee t= hat the PAddress - is at the starting address of this block. - @param[in] NumBytes On input, the number of bytes of the logic= al block to be erased. - On output, the actual number of bytes eras= ed. - - @retval EFI_SUCCESS. Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashBlockErase ( - IN UINTN Address, - IN UINTN *NumBytes - ) -{ - ASSERT(FALSE); - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLi= bNull/SpiFlashCommonLibNull.inf b/Platform/Intel/MinPlatformPkg/Flash/Lib= rary/SpiFlashCommonLibNull/SpiFlashCommonLibNull.inf deleted file mode 100644 index 75ef1cb921df..000000000000 --- a/Platform/Intel/MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/S= piFlashCommonLibNull.inf +++ /dev/null @@ -1,29 +0,0 @@ -### @file -# NULL instance of Spi Flash Common Library Class -# -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D SpiFlashCommonLibNull - FILE_GUID =3D F35BBEE7-A681-443E-BB15-07AF9FABBDE= D - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D SpiFlashCommonLib -# -# The following information is for reference only and not required by th= e build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 -# - -[LibraryClasses] - -[Packages] - MdePkg/MdePkg.dec - -[Sources] - SpiFlashCommonLibNull.c diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommon= Lib.h b/Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommonLib.h deleted file mode 100644 index 0c5e72258c2d..000000000000 --- a/Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommonLib.h +++ /dev/null @@ -1,98 +0,0 @@ -/** @file - The header file includes the common header files, defines - internal structure and functions used by SpiFlashCommonLib. - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __SPI_FLASH_COMMON_LIB_H__ -#define __SPI_FLASH_COMMON_LIB_H__ - -#include <Uefi.h> -#include <Library/BaseLib.h> -#include <Library/PcdLib.h> -#include <Library/DebugLib.h> -#include <Library/BaseMemoryLib.h> -#include <Library/MemoryAllocationLib.h> -#include <Library/UefiDriverEntryPoint.h> -#include <Library/UefiBootServicesTableLib.h> - -#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size -/** - Enable block protection on the Serial Flash device. - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashLock ( - VOID - ); - -/** - Read NumBytes bytes of data from the address specified by - PAddress into Buffer. - - @param[in] Address The starting physical address of the rea= d. - @param[in,out] NumBytes On input, the number of bytes to read. O= n output, the number - of bytes actually read. - @param[out] Buffer The destination data buffer for the read= . - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashRead ( - IN UINTN Address, - IN OUT UINT32 *NumBytes, - OUT UINT8 *Buffer - ); - -/** - Write NumBytes bytes of data from Buffer to the address specified by - PAddresss. - - @param[in] Address The starting physical address of the w= rite. - @param[in,out] NumBytes On input, the number of bytes to write= . On output, - the actual number of bytes written. - @param[in] Buffer The source data buffer for the write. - - @retval EFI_SUCCESS Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashWrite ( - IN UINTN Address, - IN OUT UINT32 *NumBytes, - IN UINT8 *Buffer - ); - -/** - Erase the block starting at Address. - - @param[in] Address The starting physical address of the block= to be erased. - This library assume that caller garantee t= hat the PAddress - is at the starting address of this block. - @param[in] NumBytes On input, the number of bytes of the logic= al block to be erased. - On output, the actual number of bytes eras= ed. - - @retval EFI_SUCCESS. Opertion is successful. - @retval EFI_DEVICE_ERROR If there is any device errors. - -**/ -EFI_STATUS -EFIAPI -SpiFlashBlockErase ( - IN UINTN Address, - IN UINTN *NumBytes - ); - -#endif diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/= Intel/MinPlatformPkg/MinPlatformPkg.dec index bcb42f0ef9e6..3bcd7c854369 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -62,8 +62,6 @@ [LibraryClasses] SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h =20 - SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h - BoardInitLib|Include/Library/BoardInitLib.h MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h SecBoardInitLib|Include/Library/SecBoardInitLib.h diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc b/Platform/= Intel/MinPlatformPkg/MinPlatformPkg.dsc index d43131bf9cec..cf7870a66140 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc @@ -110,7 +110,6 @@ [LibraryClasses.common.DXE_DRIVER] TpmPlatformHierarchyLib|MinPlatformPkg/Tcg/Library/PeiDxeTpmPlatformHi= erarchyLib/PeiDxeTpmPlatformHierarchyLib.inf =20 [LibraryClasses.common.DXE_SMM_DRIVER] - SpiFlashCommonLib|MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/S= piFlashCommonLibNull.inf TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTes= tPointCheckLib.inf TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.= inf =20 @@ -119,7 +118,6 @@ [LibraryClasses.common.MM_STANDALONE] MemoryAllocationLib|StandaloneMmPkg/Library/StandaloneMmMemoryAllocati= onLib/StandaloneMmMemoryAllocationLib.inf MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Standal= oneMmServicesTableLib.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - SpiFlashCommonLib|MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/S= piFlashCommonLibNull.inf StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoi= nt/StandaloneMmDriverEntryPoint.inf VariableReadLib|MinPlatformPkg/Library/SmmVariableReadLib/StandaloneMm= VariableReadLib.inf VariableWriteLib|MinPlatformPkg/Library/SmmVariableWriteLib/Standalone= MmVariableWriteLib.inf @@ -162,8 +160,6 @@ [Components] MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLib= Null.inf MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootMa= nagerLib.inf =20 - MinPlatformPkg/Flash/Library/SpiFlashCommonLibNull/SpiFlashCommonLibNu= ll.inf - MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWra= pperHobProcessLib.inf MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWr= apperPlatformSecLib.inf --=20 2.28.0.windows.1
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[edk2-platforms][PATCH v5 23/46] TigerlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates TigerlakeOpenBoardPkg to use the SmmSpiFlashCommonLib instance in IntelSiliconPkg and the SpiFvbServiceSmm driver in IntelSiliconPkg. Cc: Sai Chaganty <rangasai.v.chaganty@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Heng Luo <heng.luo@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> --- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc | 7 = +++++-- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf | 2 = +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoard= Pkg.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg= .dsc index 1adf63403450..758b966fee81 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc @@ -173,7 +173,7 @@ [LibraryClasses.X64] !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc =20 [LibraryClasses.X64.DXE_SMM_DRIVER] - SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonL= ib/SmmSpiFlashCommonLib.inf + SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiF= lashCommonLib.inf !if $(TARGET) =3D=3D DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S= mmTestPointCheckLib.inf !endif @@ -297,6 +297,10 @@ [Components.X64] !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf =20 +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf +!endif + # # SmmAccess # @@ -326,7 +330,6 @@ [Components.X64] NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf } =20 - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf =20 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoard= Pkg.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg= .fdf index e3b2f048524c..b802c2167d06 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf @@ -434,7 +434,7 @@ [FV.FvOsBootUncompact] !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.= inf INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in= f -INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf +INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf =20 INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf --=20 2.28.0.windows.1
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Re: [RFC PATCH v4 00/27] Add AMD Secure Nested Paging (SEV-SNP) support
Brijesh Singh
On 7/28/21 9:22 PM, Yao, Jiewen wrote:
Hi BrijeshThank you Jiewen for your feedback. I will try to address the comments in next version. Patch-04:I don't know why we choose "Ovmf" from the LaunchSecretsBase PCD. I thought PCD's specific the Uefi typically contains the Ovmf name. Maybe we can fix the LaunchSecretsBase to match with the name. I will do that as a separate patch. Patch-05:For the SEV stuff, I will do it myself so that I can test it as well :) Patch-07:I will try to see if I can move that out as well. Patch-10:There are certain things which are applicable to SEV-ES and not for the SEV-SNP and vice versa. I am not oppose to create a generic helper e.g enum { AmdSev, AmdSevEs, AmdSevSnp, IntelTdx, IntelSgx, .. .. }; bool EncryptedGuestFeatureEnabled(enum type); But I think some of this can be done later as well. Patch-12:Yes, I can do it. Patch-18:I will try to consolidate it in AmdSev.c Patch-23:While launching the SEV-SNP guests, the hypervisor may need to provide some additional information during the guest boot. When booting under the EFI based BIOS, the EFI configuration table contains an entry for the confidential computing blob that contains the required information. The Linux kernel will lookup for this EFI table during the boot to locate the secrets and cpuid page. Is that generic concept? Or SEV specific thing?Its designed as a generic and the current only SEV-SNP provides it. Who is consumer?Any guest kernel (window or Linux) What is difference between ConfidentialComputingSecret and ConfidentialComputingBlob ? When to use which?The confidentialComputingSecrets contains the secrets keys where the CCBlob contains the information which maybe used during the boot. You can see some more about it on my kernel patches: https://lore.kernel.org/lkml/20210707181506.30489-26-brijesh.singh@amd.com/ I can understand how TDX use ConfidentialComputingSecret, but how do you expect TDX use ConfidentialComputingBlob (if it is a generic concept) ?I think in the case of TDX , the information needed during the boot is provided through the ACPI tables but in SEV-SNP those are provided throught the CCBlob. In the contianer environement there will be no EFI so in that case the Blob will be passed to the boot loader setup data. If required then TDX can use it to pass the boot information. thanks
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[edk2-platforms][PATCH v5 15/46] WhiskeylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> Reviewed-by: Chasel Chiu <chasel.chiu@...> --- Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDx= e.inf | 4 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapIncl= ude.fdf | 4 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei= MultiBoardInitPreMemLib.inf | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf = | 36 ++++++++++---------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Flash= MapInclude.fdf | 4 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = | 36 ++++++++++---------- 7 files changed, 45 insertions(+), 45 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf= b/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf index a9687d93dee1..0a807ad84f4d 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -36,8 +36,8 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES =20 [Sources] BiosInfo.c diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/= PolicyInitDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyI= nitDxe/PolicyInitDxe.inf index 3233375d6568..537d507ed7d6 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyI= nitDxe.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyI= nitDxe.inf @@ -47,8 +47,8 @@ [Packages] =20 [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/= FlashMapInclude.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Inc= lude/Fdf/FlashMapInclude.fdf index f7aa730ae7d2..5895eebc5a79 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMa= pInclude.fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMa= pInclude.fdf @@ -38,8 +38,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00170000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00490000 # Flash addr (0xFFDE0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00070000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00500000 # Flash addr (0xFFE50000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x00050000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00500000 # Flash addr (0xFFE50000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x00050000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x00550000 # Flash addr (0xFFEA0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D = 0x000EA000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D = 0x0063A000 # Flash addr (0xFFF8A000) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/Boar= dInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenB= oardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 2903bdacaebd..091d2118c7b3 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.inf @@ -293,7 +293,7 @@ [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =20 [FixedPcd] gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg= .fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf index 22fbfc99f0f0..8aea5aa475a0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf @@ -31,8 +31,8 @@ [FD.UpXtreme] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -43,21 +43,21 @@ [FD.UpXtreme] # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -158,8 +158,8 @@ [FD.UpXtreme] # FSP_S Section FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Inclu= de/Fdf/FlashMapInclude.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whisk= eylakeURvp/Include/Fdf/FlashMapInclude.fdf index e0db38194211..586e3488c2a7 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/= FlashMapInclude.fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/= FlashMapInclude.fdf @@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x00190000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x00320000 # Flash addr (0xFFB20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00170000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00540000 # Flash addr (0xFFD40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00070000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x005B0000 # Flash addr (0xFFDB0000) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Open= BoardPkg.fdf index 1ab8c137924e..f0601984338c 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg= .fdf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg= .fdf @@ -31,8 +31,8 @@ [FD.WhiskeylakeURvp] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -43,21 +43,21 @@ [FD.WhiskeylakeURvp] # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -153,8 +153,8 @@ [FD.WhiskeylakeURvp] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 --=20 2.28.0.windows.1
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[edk2-platforms][PATCH v5 11/46] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> Reviewed-by: Chasel Chiu <chasel.chiu@...> --- Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 +-- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapI= nclude.fdf | 4 +-- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf = | 36 ++++++++++---------- Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf | 4 +-- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b= /Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf index 9208aeda5d2a..6ca0ada751f6 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -36,8 +36,8 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES =20 [Sources] BiosInfo.c diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/F= df/FlashMapInclude.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR= vp/Include/Fdf/FlashMapInclude.fdf index d9959a79d0bb..7d2f4b2c0cb2 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flas= hMapInclude.fdf +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flas= hMapInclude.fdf @@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x00190000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x00320000 # Flash addr (0xFFB20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00170000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00490000 # Flash addr (0xFFC90000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000B0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00540000 # Flash addr (0xFFD40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00070000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x005B0000 # Flash addr (0xFFDB0000) diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoard= Pkg.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg= .fdf index 795cc0da75d8..6397d80d3895 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf @@ -31,8 +31,8 @@ [FD.CometlakeURvp] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -43,21 +43,21 @@ [FD.CometlakeURvp] # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvO= ffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -153,8 +153,8 @@ [FD.CometlakeURvp] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitD= xe/PolicyInitDxe.inf index 1d09b990b163..abb79c111e0b 100644 --- a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf +++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf @@ -47,8 +47,8 @@ [Packages] =20 [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType --=20 2.28.0.windows.1
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[edk2-platforms][PATCH v5 10/46] IntelSiliconPkg: Add MM SPI FVB services
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Adds a Traditional MM and Standalone MM SPI FVB Service driver to IntelSiliconPkg. These drivers produce the firmware volume block protocol for SPI flash devices compliant with the Intel Serial Flash Interface Compatibility Specification. Cc: Ray Ni <ray.ni@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> --- Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c = | 94 ++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceC= ommon.c | 903 ++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceM= m.c | 271 ++++++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceS= tandaloneMm.c | 32 + Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceT= raditionalMm.c | 32 + Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceC= ommon.h | 158 ++++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceM= m.h | 22 + Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceS= mm.inf | 68 ++ Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceS= tandaloneMm.inf | 67 ++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = | 11 + 10 files changed, 1658 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Fv= bInfo.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbIn= fo.c new file mode 100644 index 000000000000..7f2678fa9e5a --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/FvbInfo.c @@ -0,0 +1,94 @@ +/**@file + Defines data structure that is the volume header found. + These data is intent to decouple FVB driver with FV header. + +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiFvbServiceCommon.h" + +#define FIRMWARE_BLOCK_SIZE 0x10000 +#define FVB_MEDIA_BLOCK_SIZE FIRMWARE_BLOCK_SIZE + +#define NV_STORAGE_BASE_ADDRESS FixedPcdGet32(PcdFlashNvStorageVaria= bleBase) +#define SYSTEM_NV_BLOCK_NUM ((FixedPcdGet32(PcdFlashNvStorageVar= iableSize)+ FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet3= 2(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE) + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_FIRMWARE_VOLUME_HEADER FvbInfo; + EFI_FV_BLOCK_MAP_ENTRY End[1]; +} EFI_FVB2_MEDIA_INFO; + +// +// This data structure contains a template of all correct FV headers, wh= ich is used to restore +// Fv header if it's corrupted. +// +EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] =3D { + // + // Systen NvStorage FVB + // + { + NV_STORAGE_BASE_ADDRESS, + { + {0,}, //ZeroVector[16] + EFI_SYSTEM_NV_DATA_FV_GUID, + FVB_MEDIA_BLOCK_SIZE * SYSTEM_NV_BLOCK_NUM, + EFI_FVH_SIGNATURE, + 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for deta= ils on EFI_FVB_ATTRIBUTES_2 + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENT= RY), + 0, //CheckSum which will be calucated dynamically. + 0, //ExtHeaderOffset + {0,}, //Reserved[1] + 2, //Revision + { + { + SYSTEM_NV_BLOCK_NUM, + FVB_MEDIA_BLOCK_SIZE, + } + } + }, + { + { + 0, + 0 + } + } + } +}; + +EFI_STATUS +GetFvbInfo ( + IN EFI_PHYSICAL_ADDRESS FvBaseAddress, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ) +{ + UINTN Index; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + + for (Index =3D 0; Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI= _FVB2_MEDIA_INFO); Index++) { + if (mPlatformFvbMediaInfo[Index].BaseAddress =3D=3D FvBaseAddress) { + FvHeader =3D &mPlatformFvbMediaInfo[Index].FvbInfo; + + // + // Update the checksum value of FV header. + // + FvHeader->Checksum =3D CalculateCheckSum16 ( (UINT16 *) FvHeader, = FvHeader->HeaderLength); + + *FvbInfo =3D FvHeader; + + DEBUG ((DEBUG_INFO, "BaseAddr: 0x%lx \n", FvBaseAddress)); + DEBUG ((DEBUG_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength)); + DEBUG ((DEBUG_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLen= gth)); + DEBUG ((DEBUG_INFO, "Header Checksum: 0x%X\n", (*FvbInfo)->Checksu= m)); + DEBUG ((DEBUG_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)= ->BlockMap[0].NumBlocks)); + DEBUG ((DEBUG_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInf= o)->BlockMap[0].Length)); + DEBUG ((DEBUG_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)= ->BlockMap[1].NumBlocks)); + DEBUG ((DEBUG_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbI= nfo)->BlockMap[1].Length)); + + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceCommon.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbS= ervice/SpiFvbServiceCommon.c new file mode 100644 index 000000000000..dab818e98087 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceCommon.c @@ -0,0 +1,903 @@ +/** @file + Common driver source for several Serial Flash devices + which are compliant with the Intel(R) Serial Flash Interface Compatibi= lity Specification. + +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiFvbServiceCommon.h" + +// +// Global variable for this FVB driver which contains +// the private data of all firmware volume block instances +// +FVB_GLOBAL mFvbModuleGlobal; + +// +// This platform driver knows there are multiple FVs on FD. +// Now we only provide FVs on Variable region and MicorCode region for p= erformance issue. +// +FV_INFO mPlatformFvBaseAddress[] =3D { + {0, 0}, // {FixedPcdGet32(PcdFlashNvStorageVariableBase), FixedPcdGet3= 2(PcdFlashNvStorageVariableSize)}, + {0, 0}, // {FixedPcdGet32(PcdFlashMicrocodeFvBase), FixedPcdGet32(PcdF= lashMicrocodeFvSize)}, + {0, 0} +}; + +FV_INFO mPlatformDefaultBaseAddress[] =3D { + {0, 0}, // {FixedPcdGet32(PcdFlashNvStorageVariableBase), FixedPcdGet3= 2(PcdFlashNvStorageVariableSize)}, + {0, 0}, // {FixedPcdGet32(PcdFlashMicrocodeFvBase), FixedPcdGet32(PcdF= lashMicrocodeFvSize)}, + {0, 0} +}; + +FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate =3D { + { + { + HARDWARE_DEVICE_PATH, + HW_MEMMAP_DP, + { + (UINT8)(sizeof (MEMMAP_DEVICE_PATH)), + (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8) + } + }, + EfiMemoryMappedIO, + (EFI_PHYSICAL_ADDRESS) 0, + (EFI_PHYSICAL_ADDRESS) 0, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate =3D { + { + { + MEDIA_DEVICE_PATH, + MEDIA_PIWG_FW_VOL_DP, + { + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)), + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8) + } + }, + { 0 } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +// +// Template structure used when installing FVB protocol +// +EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mFvbProtocolTemplate =3D { + FvbProtocolGetAttributes, + FvbProtocolSetAttributes, + FvbProtocolGetPhysicalAddress, + FvbProtocolGetBlockSize, + FvbProtocolRead, + FvbProtocolWrite, + FvbProtocolEraseBlocks, + NULL +}; + +/** + Get the EFI_FVB_ATTRIBUTES_2 of a FV. + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTANCE. + + @return Attributes of the FV identified by FvbInstance. + +**/ +EFI_FVB_ATTRIBUTES_2 +FvbGetVolumeAttributes ( + IN EFI_FVB_INSTANCE *FvbInstance + ) +{ + return FvbInstance->FvHeader.Attributes; +} + +/** + Retrieves the starting address of an LBA in an FV. It also + return a few other attribut of the FV. + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTANCE. + @param[in] Lba The logical block address + @param[out] LbaAddress On output, contains the physical starting = address + of the Lba + @param[out] LbaLength On output, contains the length of the bloc= k + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in w= hich the + number of consecutive blocks starting with= Lba is + returned. All blocks in this range have a = size of + BlockSize + + @retval EFI_SUCCESS Successfully returns + @retval EFI_INVALID_PARAMETER Instance not found + +**/ +EFI_STATUS +FvbGetLbaAddress ( + IN EFI_FVB_INSTANCE *FvbInstance, + IN EFI_LBA Lba, + OUT UINTN *LbaAddress, + OUT UINTN *LbaLength, + OUT UINTN *NumOfBlocks + ) +{ + UINT32 NumBlocks; + UINT32 BlockLength; + UINTN Offset; + EFI_LBA StartLba; + EFI_LBA NextLba; + EFI_FV_BLOCK_MAP_ENTRY *BlockMap; + + StartLba =3D 0; + Offset =3D 0; + BlockMap =3D &(FvbInstance->FvHeader.BlockMap[0]); + + // + // Parse the blockmap of the FV to find which map entry the Lba belong= s to + // + while (TRUE) { + NumBlocks =3D BlockMap->NumBlocks; + BlockLength =3D BlockMap->Length; + + if ( NumBlocks =3D=3D 0 || BlockLength =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + NextLba =3D StartLba + NumBlocks; + + // + // The map entry found + // + if (Lba >=3D StartLba && Lba < NextLba) { + Offset =3D Offset + (UINTN)MultU64x32((Lba - StartLba), BlockLengt= h); + if (LbaAddress ) { + *LbaAddress =3D FvbInstance->FvBase + Offset; + } + + if (LbaLength ) { + *LbaLength =3D BlockLength; + } + + if (NumOfBlocks ) { + *NumOfBlocks =3D (UINTN)(NextLba - Lba); + } + return EFI_SUCCESS; + } + + StartLba =3D NextLba; + Offset =3D Offset + NumBlocks * BlockLength; + BlockMap++; + } +} + +/** + Reads specified number of bytes into a buffer from the specified block= . + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTA= NCE + @param[in] Lba The logical block address to be = read from + @param[in] BlockOffset Offset into the block at which t= o begin reading + @param[in] NumBytes Pointer that on input contains t= he total size of + the buffer. On output, it contai= ns the total number + of bytes read + @param[in] Buffer Pointer to a caller allocated bu= ffer that will be + used to hold the data read + + + @retval EFI_SUCCESS The firmware volume was read suc= cessfully and + contents are in Buffer + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA boun= dary. On output, + NumBytes contains the total numb= er of bytes returned + in Buffer + @retval EFI_ACCESS_DENIED The firmware volume is in the Re= adDisabled state + @retval EFI_DEVICE_ERROR The block device is not function= ing correctly and + could not be read + @retval EFI_INVALID_PARAMETER Instance not found, or NumBytes,= Buffer are NULL + +**/ +EFI_STATUS +FvbReadBlock ( + IN EFI_FVB_INSTANCE *FvbInstance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaLength; + EFI_STATUS Status; + BOOLEAN BadBufferSize =3D FALSE; + + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + if (*NumBytes =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + Status =3D FvbGetLbaAddress (FvbInstance, Lba, &LbaAddress, &LbaLength= , NULL); + if (EFI_ERROR(Status)) { + return Status; + } + + Attributes =3D FvbGetVolumeAttributes (FvbInstance); + + if ((Attributes & EFI_FVB2_READ_STATUS) =3D=3D 0) { + return EFI_ACCESS_DENIED; + } + + if (BlockOffset > LbaLength) { + return EFI_INVALID_PARAMETER; + } + + if (LbaLength < (*NumBytes + BlockOffset)) { + DEBUG ((DEBUG_INFO, + "FvReadBlock: Reducing Numbytes from 0x%x to 0x%x\n", + *NumBytes, + (UINT32)(LbaLength - BlockOffset)) + ); + *NumBytes =3D (UINT32) (LbaLength - BlockOffset); + BadBufferSize =3D TRUE; + } + + Status =3D SpiFlashRead (LbaAddress + BlockOffset, (UINT32 *)NumBytes,= Buffer); + + if (!EFI_ERROR (Status) && BadBufferSize) { + return EFI_BAD_BUFFER_SIZE; + } else { + return Status; + } +} + +/** + Writes specified number of bytes from the input buffer to the block. + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTANCE + @param[in] Lba The starting logical block index to = write to + @param[in] BlockOffset Offset into the block at which to be= gin writing + @param[in] NumBytes Pointer that on input contains the t= otal size of + the buffer. On output, it contains t= he total number + of bytes actually written + @param[in] Buffer Pointer to a caller allocated buffer= that contains + the source for the write + @retval EFI_SUCCESS The firmware volume was written succ= essfully + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA boundar= y. On output, + NumBytes contains the total number o= f bytes + actually written + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteD= isabled state + @retval EFI_DEVICE_ERROR The block device is not functioning = correctly and + could not be written + @retval EFI_INVALID_PARAMETER Instance not found, or NumBytes, Buf= fer are NULL + +**/ +EFI_STATUS +FvbWriteBlock ( + IN EFI_FVB_INSTANCE *FvbInstance, + IN EFI_LBA Lba, + IN UINTN BlockOffset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaLength; + EFI_STATUS Status; + BOOLEAN BadBufferSize =3D FALSE; + + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + if (*NumBytes =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + Status =3D FvbGetLbaAddress (FvbInstance, Lba, &LbaAddress, &LbaLength= , NULL); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Check if the FV is write enabled + // + Attributes =3D FvbGetVolumeAttributes (FvbInstance); + if ((Attributes & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + return EFI_ACCESS_DENIED; + } + + // + // Perform boundary checks and adjust NumBytes + // + if (BlockOffset > LbaLength) { + return EFI_INVALID_PARAMETER; + } + + if (LbaLength < (*NumBytes + BlockOffset)) { + DEBUG ((DEBUG_INFO, + "FvWriteBlock: Reducing Numbytes from 0x%x to 0x%x\n", + *NumBytes, + (UINT32)(LbaLength - BlockOffset)) + ); + *NumBytes =3D (UINT32) (LbaLength - BlockOffset); + BadBufferSize =3D TRUE; + } + + Status =3D SpiFlashWrite (LbaAddress + BlockOffset, (UINT32 *)NumBytes= , Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D SpiFlashLock (); + if (EFI_ERROR (Status)) { + return Status; + } + + WriteBackInvalidateDataCacheRange ((VOID *) (LbaAddress + BlockOffset)= , *NumBytes); + + if (!EFI_ERROR (Status) && BadBufferSize) { + return EFI_BAD_BUFFER_SIZE; + } else { + return Status; + } +} + + + +/** + Erases and initializes a firmware volume block. + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTANCE + @param[in] Lba The logical block index to be erased + + @retval EFI_SUCCESS The erase request was successfully com= pleted + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDis= abled state + @retval EFI_DEVICE_ERROR The block device is not functioning co= rrectly and + could not be written. Firmware device = may have been + partially erased + @retval EFI_INVALID_PARAMETER Instance not found + +**/ +EFI_STATUS +FvbEraseBlock ( + IN EFI_FVB_INSTANCE *FvbInstance, + IN EFI_LBA Lba + ) +{ + + EFI_FVB_ATTRIBUTES_2 Attributes; + UINTN LbaAddress; + UINTN LbaLength; + EFI_STATUS Status; + + // + // Check if the FV is write enabled + // + Attributes =3D FvbGetVolumeAttributes (FvbInstance); + + if( (Attributes & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + return EFI_ACCESS_DENIED; + } + + // + // Get the starting address of the block for erase. + // + Status =3D FvbGetLbaAddress (FvbInstance, Lba, &LbaAddress, &LbaLength= , NULL); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D SpiFlashBlockErase (LbaAddress, &LbaLength); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D SpiFlashLock (); + if (EFI_ERROR (Status)) { + return Status; + } + + WriteBackInvalidateDataCacheRange ((VOID *) LbaAddress, LbaLength); + + return Status; +} + +/** + Modifies the current settings of the firmware volume according to the + input parameter, and returns the new setting of the volume + + @param[in] FvbInstance The pointer to the EFI_FVB_INSTANCE. + @param[in] Attributes On input, it is a pointer to EFI_FVB= _ATTRIBUTES_2 + containing the desired firmware volu= me settings. + On successful return, it contains th= e new settings + of the firmware volume + + @retval EFI_SUCCESS Successfully returns + @retval EFI_ACCESS_DENIED The volume setting is locked and can= not be modified + @retval EFI_INVALID_PARAMETER Instance not found, or The attribute= s requested are + in conflict with the capabilities as= declared in the + firmware volume header + +**/ +EFI_STATUS +FvbSetVolumeAttributes ( + IN EFI_FVB_INSTANCE *FvbInstance, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 OldAttributes; + EFI_FVB_ATTRIBUTES_2 *AttribPtr; + EFI_FVB_ATTRIBUTES_2 UnchangedAttributes; + UINT32 Capabilities; + UINT32 OldStatus, NewStatus; + + AttribPtr =3D (EFI_FVB_ATTRIBUTES_2 *) &(FvbInstance->FvHeader.Att= ributes); + OldAttributes =3D *AttribPtr; + Capabilities =3D OldAttributes & EFI_FVB2_CAPABILITIES; + OldStatus =3D OldAttributes & EFI_FVB2_STATUS; + NewStatus =3D *Attributes & EFI_FVB2_STATUS; + + UnchangedAttributes =3D EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP | \ + EFI_FVB2_STICKY_WRITE | \ + EFI_FVB2_MEMORY_MAPPED | \ + EFI_FVB2_ERASE_POLARITY | \ + EFI_FVB2_READ_LOCK_CAP | \ + EFI_FVB2_WRITE_LOCK_CAP | \ + EFI_FVB2_ALIGNMENT; + + // + // Some attributes of FV is read only can *not* be set + // + if ((OldAttributes & UnchangedAttributes) ^ (*Attributes & UnchangedAt= tributes)) { + return EFI_INVALID_PARAMETER; + } + + // + // If firmware volume is locked, no status bit can be updated + // + if ( OldAttributes & EFI_FVB2_LOCK_STATUS ) { + if ( OldStatus ^ NewStatus ) { + return EFI_ACCESS_DENIED; + } + } + + // + // Test read disable + // + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_READ_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + + // + // Test read enable + // + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_READ_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + // + // Test write disable + // + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + + // + // Test write enable + // + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_WRITE_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + // + // Test lock + // + if ((Capabilities & EFI_FVB2_LOCK_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_LOCK_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + *AttribPtr =3D (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS)); + *AttribPtr =3D (*AttribPtr) | NewStatus; + *Attributes =3D *AttribPtr; + + return EFI_SUCCESS; +} + +/** + Check the integrity of firmware volume header + + @param[in] FvHeader A pointer to a firmware volume header + + @retval TRUE The firmware volume is consistent + @retval FALSE The firmware volume has corrupted. + +**/ +BOOLEAN +IsFvHeaderValid ( + IN EFI_PHYSICAL_ADDRESS FvBase, + IN CONST EFI_FIRMWARE_VOLUME_HEADER *FvHeader + ) +{ + if (FvBase =3D=3D PcdGet32(PcdFlashNvStorageVariableBase)) { + if (CompareMem (&FvHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid, = sizeof(EFI_GUID)) !=3D 0 ) { + return FALSE; + } + } else { + if (CompareMem (&FvHeader->FileSystemGuid, &gEfiFirmwareFileSystem2G= uid, sizeof(EFI_GUID)) !=3D 0 ) { + return FALSE; + } + } + if ( (FvHeader->Revision !=3D EFI_FVH_REVISION) || + (FvHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FvHeader->FvLength =3D=3D ((UINTN) -1)) || + ((FvHeader->HeaderLength & 0x01 ) !=3D0) ) { + return FALSE; + } + + if (CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength) = !=3D 0) { + return FALSE; + } + + return TRUE; +} + +// +// FVB protocol APIs +// + +/** + Retrieves the physical address of the device. + + @param[in] This A pointer to EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL. + @param[out] Address Output buffer containing the address. + + retval EFI_SUCCESS The function always return successfully. + +**/ +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + *Address =3D FvbInstance->FvBase; + + return EFI_SUCCESS; +} + +/** + Retrieve the size of a logical block + + @param[in] This Calling context + @param[in] Lba Indicates which block to return the size for. + @param[out] BlockSize A pointer to a caller allocated UINTN in which + the size of the block is returned + @param[out] NumOfBlocks A pointer to a caller allocated UINTN in which= the + number of consecutive blocks starting with Lba= is + returned. All blocks in this range have a size= of + BlockSize + + @retval EFI_SUCCESS The function always return successfully. + +**/ +EFI_STATUS +EFIAPI +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + DEBUG((DEBUG_INFO, + "FvbProtocolGetBlockSize: Lba: 0x%lx BlockSize: 0x%x NumOfBlocks: 0x= %x\n", + Lba, + BlockSize, + NumOfBlocks) + ); + + return FvbGetLbaAddress ( + FvbInstance, + Lba, + NULL, + BlockSize, + NumOfBlocks + ); +} + +/** + Retrieves Volume attributes. No polarity translations are done. + + @param[in] This Calling context + @param[out] Attributes Output buffer which contains attributes + + @retval EFI_SUCCESS The function always return successfully. + +**/ +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + *Attributes =3D FvbGetVolumeAttributes (FvbInstance); + + DEBUG ((DEBUG_INFO, + "FvbProtocolGetAttributes: This: 0x%x Attributes: 0x%x\n", + This, + *Attributes) + ); + + return EFI_SUCCESS; +} + +/** + Sets Volume attributes. No polarity translations are done. + + @param[in] This Calling context + @param[out] Attributes Output buffer which contains attributes + + @retval EFI_SUCCESS The function always return successfully. + +**/ +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_STATUS Status; + EFI_FVB_INSTANCE *FvbInstance; + + DEBUG((DEBUG_INFO, + "FvbProtocolSetAttributes: Before SET - This: 0x%x Attributes: 0x%x= \n", + This, + *Attributes) + ); + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + Status =3D FvbSetVolumeAttributes (FvbInstance, Attributes); + + DEBUG((DEBUG_INFO, + "FvbProtocolSetAttributes: After SET - This: 0x%x Attributes: 0x%x\= n", + This, + *Attributes) + ); + + return Status; +} + +/** + The EraseBlock() function erases one or more blocks as denoted by the + variable argument list. The entire parameter list of blocks must be ve= rified + prior to erasing any blocks. If a block is requested that does not ex= ist + within the associated firmware volume (it has a larger index than the = last + block of the firmware volume), the EraseBlock() function must return + EFI_INVALID_PARAMETER without modifying the contents of the firmware v= olume. + + @param[in] This Calling context + @param[in] ... Starting LBA followed by Number of Lba to eras= e. + a -1 to terminate the list. + + @retval EFI_SUCCESS The erase request was successfully completed + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled = state + @retval EFI_DEVICE_ERROR The block device is not functioning correctl= y and + could not be written. Firmware device may ha= ve been + partially erased + +**/ +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + UINTN NumOfBlocks; + VA_LIST Args; + EFI_LBA StartingLba; + UINTN NumOfLba; + EFI_STATUS Status; + + DEBUG((DEBUG_INFO, "FvbProtocolEraseBlocks: \n")); + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + NumOfBlocks =3D FvbInstance->NumOfBlocks; + + VA_START (Args, This); + + do { + StartingLba =3D VA_ARG (Args, EFI_LBA); + if ( StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR ) { + break; + } + + NumOfLba =3D VA_ARG (Args, UINT32); + + // + // Check input parameters + // + if (NumOfLba =3D=3D 0) { + VA_END (Args); + return EFI_INVALID_PARAMETER; + } + + if ( ( StartingLba + NumOfLba ) > NumOfBlocks ) { + return EFI_INVALID_PARAMETER; + } + } while ( 1 ); + + VA_END (Args); + + VA_START (Args, This); + do { + StartingLba =3D VA_ARG (Args, EFI_LBA); + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + break; + } + + NumOfLba =3D VA_ARG (Args, UINT32); + + while ( NumOfLba > 0 ) { + Status =3D FvbEraseBlock (FvbInstance, StartingLba); + if ( EFI_ERROR(Status)) { + VA_END (Args); + return Status; + } + StartingLba ++; + NumOfLba --; + } + + } while ( 1 ); + + VA_END (Args); + + return EFI_SUCCESS; +} + +/** + Writes data beginning at Lba:Offset from FV. The write terminates eith= er + when *NumBytes of data have been written, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + + @param[in] This Calling context + @param[in] Lba Block in which to begin write + @param[in] Offset Offset in the block at which to begin write + @param[in,out] NumBytes On input, indicates the requested write size= . On + output, indicates the actual number of bytes= written + @param[in] Buffer Buffer containing source data for the write. + + @retval EFI_SUCCESS The firmware volume was written successf= ully + @retval EFI_BAD_BUFFER_SIZE Write attempted across a LBA boundary. O= n output, + NumBytes contains the total number of by= tes + actually written + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisab= led state + @retval EFI_DEVICE_ERROR The block device is not functioning corr= ectly and + could not be written + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL + +**/ +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + + DEBUG((DEBUG_INFO, + "FvbProtocolWrite: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer: 0= x%x\n", + Lba, + Offset, + *NumBytes, + Buffer) + ); + + return FvbWriteBlock (FvbInstance, Lba, Offset, NumBytes, Buffer); +} + +/** + Reads data beginning at Lba:Offset from FV. The Read terminates either + when *NumBytes of data have been read, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + + @param[in] This Calling context + @param[in] Lba Block in which to begin write + @param[in] Offset Offset in the block at which to begin write + @param[in,out] NumBytes On input, indicates the requested write size= . On + output, indicates the actual number of bytes= written + @param[in] Buffer Buffer containing source data for the write. + + @retval EFI_SUCCESS The firmware volume was read successfull= y and + contents are in Buffer + @retval EFI_BAD_BUFFER_SIZE Read attempted across a LBA boundary. On= output, + NumBytes contains the total number of by= tes returned + in Buffer + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabl= ed state + @retval EFI_DEVICE_ERROR The block device is not functioning corr= ectly and + could not be read + @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL + +**/ +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + OUT UINT8 *Buffer + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + EFI_STATUS Status; + + FvbInstance =3D FVB_INSTANCE_FROM_THIS (This); + Status =3D FvbReadBlock (FvbInstance, Lba, Offset, NumBytes, Buffer); + DEBUG((DEBUG_INFO, + "FvbProtocolRead: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer: 0x= %x\n", + Lba, + Offset, + *NumBytes, + Buffer) + ); + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceMm.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServi= ce/SpiFvbServiceMm.c new file mode 100644 index 000000000000..42a0828c6fae --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceMm.c @@ -0,0 +1,271 @@ +/** @file + MM driver source for several Serial Flash devices + which are compliant with the Intel(R) Serial Flash Interface Compatibi= lity Specification. + + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> + Copyright (c) Microsoft Corporation.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiFvbServiceCommon.h" +#include <Library/MmServicesTableLib.h> +#include <Library/UefiDriverEntryPoint.h> +#include <Protocol/SmmFirmwareVolumeBlock.h> + +/** + The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol + for each FV in the system. + + @param[in] FvbInstance The pointer to a FW volume instance structur= e, + which contains the information about one FV. + + @retval VOID + +**/ +VOID +InstallFvbProtocol ( + IN EFI_FVB_INSTANCE *FvbInstance + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_STATUS Status; + EFI_HANDLE FvbHandle; + + ASSERT (FvbInstance !=3D NULL); + if (FvbInstance =3D=3D NULL) { + return; + } + + CopyMem (&FvbInstance->FvbProtocol, &mFvbProtocolTemplate, sizeof (EFI= _FIRMWARE_VOLUME_BLOCK_PROTOCOL)); + + FvHeader =3D &FvbInstance->FvHeader; + if (FvHeader =3D=3D NULL) { + return; + } + + // + // Set up the devicepath + // + DEBUG ((DEBUG_INFO, "FwBlockService.c: Setting up DevicePath for 0x%lx= :\n", FvbInstance->FvBase)); + if (FvHeader->ExtHeaderOffset =3D=3D 0) { + // + // FV does not contains extension header, then produce MEMMAP_DEVICE= _PATH + // + FvbInstance->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *) AllocateRun= timeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplat= e); + if (FvbInstance->DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for MEM= MAP_DEVICE_PATH failed\n")); + return; + } + ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)->MemMapDevPath.S= tartingAddress =3D FvbInstance->FvBase; + ((FV_MEMMAP_DEVICE_PATH *) FvbInstance->DevicePath)->MemMapDevPath.E= ndingAddress =3D FvbInstance->FvBase + FvHeader->FvLength - 1; + } else { + FvbInstance->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *) AllocateRun= timeCopyPool (sizeof (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate); + if (FvbInstance->DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "SpiFvbServiceSmm.c: Memory allocation for FV_= PIWG_DEVICE_PATH failed\n")); + return; + } + CopyGuid ( + &((FV_PIWG_DEVICE_PATH *)FvbInstance->DevicePath)->FvDevPath.FvNam= e, + (GUID *)(UINTN)(FvbInstance->FvBase + FvHeader->ExtHeaderOffset) + ); + } + + // + // LocateDevicePath fails so install a new interface and device path + // + FvbHandle =3D NULL; + + Status =3D gMmst->MmInstallProtocolInterface ( + &FvbHandle, + &gEfiSmmFirmwareVolumeBlockProtocolGuid, + EFI_NATIVE_INTERFACE, + &(FvbInstance->FvbProtocol) + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gMmst->MmInstallProtocolInterface ( + &FvbHandle, + &gEfiDevicePathProtocolGuid, + EFI_NATIVE_INTERFACE, + &(FvbInstance->DevicePath) + ); + ASSERT_EFI_ERROR (Status); +} + +/** + The function does the necessary initialization work for + Firmware Volume Block Driver. + +**/ +VOID +FvbInitialize ( + VOID + ) +{ + EFI_FVB_INSTANCE *FvbInstance; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry; + EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_STATUS Status; + UINTN BufferSize; + UINTN Idx; + UINT32 MaxLbaSize; + UINT32 BytesWritten; + UINTN BytesErased; + + mPlatformFvBaseAddress[0].FvBase =3D PcdGet32(PcdFlashNvStorageVariabl= eBase); + mPlatformFvBaseAddress[0].FvSize =3D PcdGet32(PcdFlashNvStorageVariabl= eSize); + mPlatformFvBaseAddress[1].FvBase =3D PcdGet32(PcdFlashMicrocodeFvBase)= ; + mPlatformFvBaseAddress[1].FvSize =3D PcdGet32(PcdFlashMicrocodeFvSize)= ; + mPlatformDefaultBaseAddress[0].FvBase =3D PcdGet32(PcdFlashNvStorageVa= riableBase); + mPlatformDefaultBaseAddress[0].FvSize =3D PcdGet32(PcdFlashNvStorageVa= riableSize); + mPlatformDefaultBaseAddress[1].FvBase =3D PcdGet32(PcdFlashMicrocodeFv= Base); + mPlatformDefaultBaseAddress[1].FvSize =3D PcdGet32(PcdFlashMicrocodeFv= Size); + + // + // We will only continue with FVB installation if the + // SPI is the active BIOS state + // + { + // + // Make sure all FVB are valid and/or fix if possible + // + for (Idx =3D 0;; Idx++) { + if (mPlatformFvBaseAddress[Idx].FvSize =3D=3D 0 && mPlatformFvBase= Address[Idx].FvBase =3D=3D 0) { + break; + } + + BaseAddress =3D mPlatformFvBaseAddress[Idx].FvBase; + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress; + + if (!IsFvHeaderValid (BaseAddress, FvHeader)) { + BytesWritten =3D 0; + BytesErased =3D 0; + DEBUG ((DEBUG_ERROR, "ERROR - The FV in 0x%x is invalid!\n", FvH= eader)); + Status =3D GetFvbInfo (BaseAddress, &FvHeader); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - Can't recovery FV header at 0x%x.= GetFvbInfo Status %r\n", BaseAddress, Status)); + continue; + } + DEBUG ((DEBUG_INFO, "Rewriting FV header at 0x%X with static dat= a\n", BaseAddress)); + // + // Spi erase + // + BytesErased =3D (UINTN) FvHeader->BlockMap->Length; + Status =3D SpiFlashBlockErase( (UINTN) BaseAddress, &BytesErased= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SpiFlashBlockErase Error %r\n", = Status)); + continue; + } + if (BytesErased !=3D FvHeader->BlockMap->Length) { + DEBUG ((DEBUG_WARN, "ERROR - BytesErased !=3D FvHeader->BlockM= ap->Length\n")); + DEBUG ((DEBUG_INFO, " BytesErased =3D 0x%X\n Length =3D 0x%X\n= ", BytesErased, FvHeader->BlockMap->Length)); + continue; + } + BytesWritten =3D FvHeader->HeaderLength; + Status =3D SpiFlashWrite ((UINTN)BaseAddress, &BytesWritten, (UI= NT8*)FvHeader); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SpiFlashWrite Error %r\n", Statu= s)); + continue; + } + if (BytesWritten !=3D FvHeader->HeaderLength) { + DEBUG ((DEBUG_WARN, "ERROR - BytesWritten !=3D HeaderLength\n"= )); + DEBUG ((DEBUG_INFO, " BytesWritten =3D 0x%X\n HeaderLength =3D= 0x%X\n", BytesWritten, FvHeader->HeaderLength)); + continue; + } + Status =3D SpiFlashLock (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SpiFlashLock Error %r\n", Status= )); + continue; + } + DEBUG ((DEBUG_INFO, "FV Header @ 0x%X restored with static data\= n", BaseAddress)); + // + // Clear cache for this range. + // + WriteBackInvalidateDataCacheRange ( (VOID *) (UINTN) BaseAddress= , FvHeader->BlockMap->Length); + } + } + + // + // Calculate the total size for all firmware volume block instances + // + BufferSize =3D 0; + for (Idx =3D 0; ; Idx++) { + if (mPlatformFvBaseAddress[Idx].FvSize =3D=3D 0 && mPlatformFvBase= Address[Idx].FvBase =3D=3D 0) { + break; + } + BaseAddress =3D mPlatformFvBaseAddress[Idx].FvBase; + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress; + + if (!IsFvHeaderValid (BaseAddress, FvHeader)) { + DEBUG ((DEBUG_WARN, "ERROR - The FV in 0x%x is invalid!\n", FvHe= ader)); + continue; + } + + BufferSize +=3D (FvHeader->HeaderLength + + sizeof (EFI_FVB_INSTANCE) - + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + ); + } + + mFvbModuleGlobal.FvbInstance =3D (EFI_FVB_INSTANCE *) AllocateRunti= meZeroPool (BufferSize); + if (mFvbModuleGlobal.FvbInstance =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + MaxLbaSize =3D 0; + FvbInstance =3D mFvbModuleGlobal.FvbInstance; + mFvbModuleGlobal.NumFv =3D 0; + + for (Idx =3D 0; ; Idx++) { + if (mPlatformFvBaseAddress[Idx].FvSize =3D=3D 0 && mPlatformFvBase= Address[Idx].FvBase =3D=3D 0) { + break; + } + BaseAddress =3D mPlatformFvBaseAddress[Idx].FvBase; + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress; + + if (!IsFvHeaderValid (BaseAddress, FvHeader)) { + DEBUG ((DEBUG_WARN, "ERROR - The FV in 0x%x is invalid!\n", FvHe= ader)); + continue; + } + + FvbInstance->Signature =3D FVB_INSTANCE_SIGNATURE; + CopyMem (&(FvbInstance->FvHeader), FvHeader, FvHeader->HeaderLengt= h); + + FvHeader =3D &(FvbInstance->FvHeader); + FvbInstance->FvBase =3D (UINTN)BaseAddress; + + // + // Process the block map for each FV + // + FvbInstance->NumOfBlocks =3D 0; + for (PtrBlockMapEntry =3D FvHeader->BlockMap; + PtrBlockMapEntry->NumBlocks !=3D 0; + PtrBlockMapEntry++) { + // + // Get the maximum size of a block. + // + if (MaxLbaSize < PtrBlockMapEntry->Length) { + MaxLbaSize =3D PtrBlockMapEntry->Length; + } + FvbInstance->NumOfBlocks +=3D PtrBlockMapEntry->NumBlocks; + } + + // + // Add a FVB Protocol Instance + // + InstallFvbProtocol (FvbInstance); + mFvbModuleGlobal.NumFv++; + + // + // Move on to the next FvbInstance + // + FvbInstance =3D (EFI_FVB_INSTANCE *) ((UINTN)((UINT8 *)FvbInstance= ) + + FvHeader->HeaderLength + + (sizeof (EFI_FVB_INSTANCE) -= sizeof (EFI_FIRMWARE_VOLUME_HEADER))); + + } + } +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceStandaloneMm.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/S= piFvbService/SpiFvbServiceStandaloneMm.c new file mode 100644 index 000000000000..252c818d6551 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceStandaloneMm.c @@ -0,0 +1,32 @@ +/** @file + MM driver source for several Serial Flash devices + which are compliant with the Intel(R) Serial Flash Interface Compatibi= lity Specification. + + Copyright (c) Microsoft Corporation.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiFvbServiceCommon.h" +#include "SpiFvbServiceMm.h" + +/** + The driver Standalone MM entry point. + + @param[in] ImageHandle Image handle of this driver. + @param[in] MmSystemTable A pointer to the MM system table. + + @retval EFI_SUCCESS This function always returns EFI_SUCCE= SS. + +**/ +EFI_STATUS +EFIAPI +SpiFvbStandaloneMmInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ) +{ + FvbInitialize (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceTraditionalMm.c b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/= SpiFvbService/SpiFvbServiceTraditionalMm.c new file mode 100644 index 000000000000..1c2dac70e3c6 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceTraditionalMm.c @@ -0,0 +1,32 @@ +/** @file + MM driver source for several Serial Flash devices + which are compliant with the Intel(R) Serial Flash Interface Compatibi= lity Specification. + + Copyright (c) Microsoft Corporation.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SpiFvbServiceCommon.h" +#include "SpiFvbServiceMm.h" + +/** + The driver Traditional MM entry point. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS This function always returns EFI_SUCCE= SS. + +**/ +EFI_STATUS +EFIAPI +SpiFvbTraditionalMmInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + FvbInitialize (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceCommon.h b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbS= ervice/SpiFvbServiceCommon.h new file mode 100644 index 000000000000..e9d69e985814 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceCommon.h @@ -0,0 +1,158 @@ +/** @file + Common source definitions used in serial flash drivers + +Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SPI_FVB_SERVICE_COMMON_H +#define _SPI_FVB_SERVICE_COMMON_H + +#include <Guid/EventGroup.h> +#include <Guid/FirmwareFileSystem2.h> +#include <Guid/SystemNvDataGuid.h> +#include <Protocol/DevicePath.h> +#include <Protocol/FirmwareVolumeBlock.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/IoLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/DevicePathLib.h> +#include <Library/HobLib.h> + +#include <Library/SpiFlashCommonLib.h> + +// +// Define two helper macro to extract the Capability field or Status fie= ld in FVB +// bit fields +// +#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP \ + ) + +#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | = EFI_FVB2_LOCK_STATUS) + +#define FVB_INSTANCE_SIGNATURE SIGNATURE_32('F','V','B','I') + +typedef struct { + UINT32 Signature; + UINTN FvBase; + UINTN NumOfBlocks; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FvbProtocol; + EFI_FIRMWARE_VOLUME_HEADER FvHeader; +} EFI_FVB_INSTANCE; + +typedef struct { + EFI_FVB_INSTANCE *FvbInstance; + UINT32 NumFv; +} FVB_GLOBAL; + +// +// Fvb Protocol instance data +// +#define FVB_INSTANCE_FROM_THIS(a) CR(a, EFI_FVB_INSTANCE, FvbProtocol, F= VB_INSTANCE_SIGNATURE) + +typedef struct { + MEDIA_FW_VOL_DEVICE_PATH FvDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} FV_PIWG_DEVICE_PATH; + +typedef struct { + MEMMAP_DEVICE_PATH MemMapDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} FV_MEMMAP_DEVICE_PATH; + +typedef struct { + UINT32 FvBase; + UINT32 FvSize; +} FV_INFO; + +// +// Protocol APIs +// +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + OUT UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ); + +BOOLEAN +IsFvHeaderValid ( + IN EFI_PHYSICAL_ADDRESS FvBase, + IN CONST EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ); + +EFI_STATUS +GetFvbInfo ( + IN EFI_PHYSICAL_ADDRESS FvBaseAddress, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ); + +extern FVB_GLOBAL mFvbModuleGlobal; +extern FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate; +extern FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate; +extern EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mFvbProtocolTemplate; +extern FV_INFO mPlatformFvBaseAddress[]; +extern FV_INFO mPlatformDefaultBaseAddress[]; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceMm.h b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbServi= ce/SpiFvbServiceMm.h new file mode 100644 index 000000000000..36af1130c8ee --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceMm.h @@ -0,0 +1,22 @@ +/** @file + Definitions common to MM implementation in this driver. + + Copyright (c) Microsoft Corporation.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SPI_FVB_SERVICE_MM_H_ +#define _SPI_FVB_SERVICE_MM_H_ + +/** + The function does the necessary initialization work for + Firmware Volume Block Driver. + +**/ +VOID +FvbInitialize ( + VOID + ); + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceSmm.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbSe= rvice/SpiFvbServiceSmm.inf new file mode 100644 index 000000000000..bf1306f00201 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceSmm.inf @@ -0,0 +1,68 @@ +### @file +# Component description file for the Serial Flash device Runtime driver. +# +# Copyright (c) 2017-2019, Intel Corporation. All rights reserved.<BR> +# Copyright (c) Microsoft Corporation.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SpiFvbServiceSmm + FILE_GUID =3D 68A10D85-6858-4402-B070-028B3EA2174= 7 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + PI_SPECIFICATION_VERSION =3D 1.10 + ENTRY_POINT =3D SpiFvbTraditionalMmInitialize + +# +# The following information is for reference only and not required by th= e build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + PcdLib + MemoryAllocationLib + CacheMaintenanceLib + BaseMemoryLib + DebugLib + BaseLib + UefiBootServicesTableLib + UefiDriverEntryPoint + SpiFlashCommonLib + MmServicesTableLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONS= UMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONS= UMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONS= UMES + +[Sources] + FvbInfo.c + SpiFvbServiceCommon.h + SpiFvbServiceCommon.c + SpiFvbServiceMm.h + SpiFvbServiceMm.c + SpiFvbServiceTraditionalMm.c + +[Protocols] + gEfiDevicePathProtocolGuid ## PRODUCES + gEfiSmmFirmwareVolumeBlockProtocolGuid ## PRODUCES + +[Guids] + gEfiFirmwareFileSystem2Guid ## CONSUMES + gEfiSystemNvDataFvGuid ## CONSUMES + +[Depex] + TRUE diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/Sp= iFvbServiceStandaloneMm.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Flash= /SpiFvbService/SpiFvbServiceStandaloneMm.inf new file mode 100644 index 000000000000..b66233968247 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbSer= viceStandaloneMm.inf @@ -0,0 +1,67 @@ +### @file +# Component description file for the Serial Flash device Standalone MM d= river. +# +# Copyright (c) 2017-2019, Intel Corporation. All rights reserved.<BR> +# Copyright (c) Microsoft Corporation.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SpiFvbServiceStandaloneMm + FILE_GUID =3D E6313655-8BD0-4EAB-B319-AD5E212CE6A= B + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D MM_STANDALONE + PI_SPECIFICATION_VERSION =3D 0x00010032 + ENTRY_POINT =3D SpiFvbStandaloneMmInitialize + +# +# The following information is for reference only and not required by th= e build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + CacheMaintenanceLib + DebugLib + MemoryAllocationLib + PcdLib + MmServicesTableLib + SpiFlashCommonLib + StandaloneMmDriverEntryPoint + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONS= UMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONS= UMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONS= UMES + +[Sources] + FvbInfo.c + SpiFvbServiceCommon.h + SpiFvbServiceCommon.c + SpiFvbServiceMm.h + SpiFvbServiceMm.c + SpiFvbServiceStandaloneMm.c + +[Protocols] + gEfiDevicePathProtocolGuid ## PRODUCES + gEfiSmmFirmwareVolumeBlockProtocolGuid ## PRODUCES + +[Guids] + gEfiFirmwareFileSystem2Guid ## CONSUMES + gEfiSystemNvDataFvGuid ## CONSUMES + +[Depex] + TRUE diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/= Intel/IntelSiliconPkg/IntelSiliconPkg.dsc index d4e15100bfde..1e826a080f28 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -40,6 +40,9 @@ [LibraryClasses] PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignment= Lib/PeiGetVtdPmrAlignmentLib.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasur= ementLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + SpiFlashCommonLib|IntelSiliconPkg/Library/SpiFlashCommonLibNull/SpiFla= shCommonLibNull.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiB= ootServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEnt= ryPoint.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf @@ -61,8 +64,14 @@ [LibraryClasses.common.DXE_DRIVER] =20 [LibraryClasses.common.DXE_SMM_DRIVER] MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAll= ocationLib.inf + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLi= b.inf SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTabl= eLib.inf =20 +[LibraryClasses.common.MM_STANDALONE] + MemoryAllocationLib|StandaloneMmPkg/Library/StandaloneMmMemoryAllocati= onLib/StandaloneMmMemoryAllocationLib.inf + MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Standal= oneMmServicesTableLib.inf + StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoi= nt/StandaloneMmDriverEntryPoint.inf + ########################################################################= ########################### # # Components Section - list of the modules and components that will be p= rocessed by compilation @@ -86,6 +95,8 @@ [Components] IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf IntelSiliconPkg/Feature/PcieSecurity/IntelPciDeviceSecurityDxe/IntelPc= iDeviceSecurityDxe.inf IntelSiliconPkg/Feature/PcieSecurity/SamplePlatformDevicePolicyDxe/Sam= plePlatformDevicePolicyDxe.inf + IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.= inf IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.inf IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf --=20 2.28.0.windows.1
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[edk2-platforms][PATCH v5 00/46] Consolidate SpiFlashCommonLib instances
Michael Kubacki
From: Michael Kubacki <michael.kubacki@...>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 SpiFlashCommonLib is duplicated in multiple places across the MinPlatform design in edk2-platforms. I'm planning to build some additional functionality on top of SpiFlashCommonLib and, ideally, this duplication will be consolidated into a single instance usable across all current lib= rary consumers. This patch series focuses on consolidating the various SpiFlashCommonLib instances as agreed upon in https://edk2.groups.io/g/devel/message/71701. Read the BZ for more general background around this series. I only have an UpXtreme board on hand so maintainers/reviewers of other board packages should test these changes on those boards. V5 changes: - Added build support for PurleyOpenBoardPkg and WhitleyOpenBoardPkg (added to edk2-platforms during the lifetime of this patch series). - Updated KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash to use the new SPI PPI interface that identifies SPI flash regions by GUID. - Added new Reviewed-by replies that came in to existing patches during v4. V4 changes: - Assigned new GUID values to the PCH SPI PPI and Protocols to differentiate from previous instances. This was done because the interface changed to identify SPI flash regions by GUID. V3 changes: - Added support to IntelSiliconPkg to identify flash regions by GUID as requested in v2 review feedback. V2 changes: - Rebased patch series on current edk2-platforms master (32183bdaa91) Note: Previous patch series only received a couple review comments after being on the mailing list for over 2 months. Please be respectful of contributors time and efforts and review in a timely manner. Cc: Agyeman Prince <prince.agyeman@...> Cc: Chasel Chiu <chasel.chiu@...> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...> Cc: Eric Dong <eric.dong@...> Cc: Heng Luo <heng.luo@...> Cc: Jeremy Soller <jeremy@...> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@...> Cc: Liming Gao <gaoliming@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> Signed-off-by: Michael Kubacki <michael.kubacki@...> Michael Kubacki (46): CometlakeOpenBoardPkg: Remove redundant IntelSiliconPkg.dec entry WhiskeylakeOpenBoardPkg: Remove redundant IntelSiliconPkg.dec entry CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Add missing GUID to INF IntelSiliconPkg: Add BIOS area base address and size PCDs IntelSiliconPkg: Add microcode FV PCDs IntelSiliconPkg: Add PCH SPI PPI IntelSiliconPkg: Add PCH SPI Protocol IntelSiliconPkg: Add SpiFlashCommonLib IntelSiliconPkg: Add SmmSpiFlashCommonLib IntelSiliconPkg: Add MM SPI FVB services CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs SimicsOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs TigerlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs WhiskeylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs CoffeelakeSiliconPkg: Use IntelSiliconPkg BIOS area and ucode PCDs KabylakeSiliconPkg: Use IntelSiliconPkg BIOS area and ucode PCDs SimicsIch10Pkg: Use IntelSiliconPkg BIOS area and ucode PCDs TigerlakeSiliconPkg: Use IntelSiliconPkg BIOS area and ucode PCDs CometlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib KabylakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib SimicsOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib TigerlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib WhiskeylakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib PurleyOpenBoardPkg: Use IntelSiliconPkg SpiFvbServiceSmm WhitleyOpenBoardPkg: UseIntelSiliconPkg SpiFvbServiceSmm MinPlatformPkg: Remove SpiFvbService modules CoffeelakeSiliconPkg: Remove SmmSpiFlashCommonLib KabylakeSiliconPkg: Remove SmmSpiFlashCommonLib SimicsIch10Pkg: Remove SmmSpiFlashCommonLib TigerlakeOpenBoardPkg: Remove SmmSpiFlashCommonLib MinPlatformPkg: Remove SpiFlashCommonLibNull PurleyOpenBoardPkg: Add SpiFlashCommonLib.h KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Add IntelSiliconPkg.dec CoffeelakeSiliconPkg: Remove PCH SPI PPI and Protocol from package KabylakeSiliconPkg: Remove PCH SPI PPI and Protocol from package SimicsIch10Pkg: Remove PCH SPI SMM Protocol from package TigerlakeSiliconPkg: Remove PCH SPI PPI and Protocol from package IntelSiliconPkg: Add flash region GUIDs IntelSiliconPkg: Identify flash regions by GUID CoffeelakeSiliconPkg/BasePchSpiCommonLib: Identify flash regions by GUID KabylakeSiliconPkg: Identify flash regions by GUID KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Update for new SPI PPI API KabylakeOpenBoardPkg/KabylakeRvp3: Add PeiSerialPortlibSpiFlash to build SimicsIch10Pkg/BasePchSpiCommonLib: Identify flash regions by GUID TigerlakeSiliconPkg/BasePchSpiCommonLib: Identify flash regions by GUID Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.c = | 4 +- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonL= ib/SpiCommon.c = | 144 ++++++++-- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiF= lashCommon.c = | 196 ------------- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiF= lashCommonSmmLib.c = | 54 ---- {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/FvbInfo.c = | 0 {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceCommon.c = | 4 +- {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceMm.c = | 8 +- {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.c = | 0 {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceTraditionalMm.c = | 0 Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFla= shCommonSmmLib.c =3D> Silicon/Intel/IntelSiliconPkg/Library/SmmSpiFlashCo= mmonLib/SmmSpiFlashCommonLib.c | 2 +- {Platform/Intel/TigerlakeOpenBoardPkg =3D> Silicon/Intel/IntelSiliconPkg= }/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c = | 7 +- {Platform/Intel/MinPlatformPkg/Flash =3D> Silicon/Intel/IntelSiliconPkg}= /Library/SpiFlashCommonLibNull/SpiFlashCommonLibNull.c = | 12 +- Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/SecureMemoryMapConfiguration.c= = | 106 ++++++- Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFla= shCommon.c = | 196 ------------- Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFla= shCommonSmmLib.c = | 54 ---- Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/= SpiCommon.c = | 140 +++++++-- Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon= .c = | 194 ------------- Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon= SmmLib.c = | 54 ---- Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommo= n.c = | 165 ++++++++--- Silicon/Intel/SimicsIch10Pkg/Spi/Smm/PchSpi.c = = | 4 +- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiComm= onLib/SpiCommon.c = | 176 ++++++++++-- Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = = | 4 +- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapI= nclude.fdf = | 4 +- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc = = | 7 +- Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf = = | 38 +-- Platform/Intel/CometlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPolicyUpdateLib.inf = | 2 +- Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf = = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclu= de.fdf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc = = | 7 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf = = | 40 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInc= lude.fdf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc = = | 9 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf = = | 40 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilic= onPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.inf = | 2 + Platform/Intel/MinPlatformPkg/Include/Library/SpiFlashCommonLib.h = = | 98 ------- Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec = = | 2 - Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc = = | 6 - Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc = = | 2 +- Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf = = | 2 +- Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc = = | 4 +- Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf = = | 5 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc = = | 6 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf = = | 2 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc = = | 8 +- Platform/Intel/TigerlakeOpenBoardPkg/BiosInfo/BiosInfo.inf = = | 8 +- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapI= nclude.fdf = | 4 +- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc = = | 7 +- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf = = | 40 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/BiosInfo/BiosInfo.inf = = | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib= /PeiPolicyUpdateLib.inf = | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDx= e.inf = | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapIncl= ude.fdf = | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei= MultiBoardInitPreMemLib.inf = | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc = = | 7 +- Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf = = | 38 +-- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Flash= MapInclude.fdf = | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = = | 7 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = = | 38 +-- {Silicon/Intel/CoffeelakeSiliconPkg/Pch =3D> Platform/Intel/WhitleyOpenB= oardPkg}/Include/Library/SpiFlashCommonLib.h = | 2 +- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc = = | 2 +- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf = = | 5 +- Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLib.inf = | 4 +- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCom= monLib.h = | 16 +- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf = = | 1 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonL= ib/BasePchSpiCommonLib.inf = | 13 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmS= piFlashCommonLib.inf = | 51 ---- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf = = | 1 + Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec = = | 8 - {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceCommon.h = | 0 {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceMm.h = | 0 {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceSmm.inf = | 6 +- {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg/Featur= e}/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.inf = | 6 +- Silicon/Intel/IntelSiliconPkg/Include/Guid/FlashRegion.h = = | 45 +++ Silicon/Intel/{SimicsIch10Pkg =3D> IntelSiliconPkg}/Include/Library/SpiF= lashCommonLib.h = | 2 +- Silicon/Intel/{CoffeelakeSiliconPkg/Pch =3D> IntelSiliconPkg}/Include/Pp= i/Spi.h = | 4 +- Silicon/Intel/{CoffeelakeSiliconPkg/Pch =3D> IntelSiliconPkg}/Include/Pr= otocol/Spi.h = | 39 +-- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = = | 37 +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = = | 17 ++ {Platform/Intel/TigerlakeOpenBoardPkg =3D> Silicon/Intel/IntelSiliconPkg= }/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf = | 24 +- {Platform/Intel/MinPlatformPkg/Flash =3D> Silicon/Intel/IntelSiliconPkg}= /Library/SpiFlashCommonLibNull/SpiFlashCommonLibNull.inf = | 3 +- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLib.inf = | 4 +- Silicon/Intel/KabylakeSiliconPkg/Hsti/Dxe/HstiSiliconDxe.inf = = | 12 +- Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h= = | 98 ------- Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.h = = | 26 -- Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol/Spi.h = = | 293 ------------------- Silicon/Intel/KabylakeSiliconPkg/Pch/IncludePrivate/Library/PchSpiCommon= Lib.h = | 20 +- Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf = = | 1 + Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpi= FlashCommonLib.inf = | 53 ---- Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib/= BasePchSpiCommonLib.inf = | 11 + Silicon/Intel/KabylakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf = = | 1 + Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec = = | 13 +- Silicon/Intel/SimicsIch10Pkg/Ich10Pkg.dec = = | 11 - Silicon/Intel/SimicsIch10Pkg/Include/Protocol/Spi.h = = | 295 ------------------- Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCommonLib.h = = | 46 +-- Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCom= monLib.inf = | 50 ---- Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/BasePchS= piCommonLib.inf = | 16 +- Silicon/Intel/SimicsIch10Pkg/Spi/Smm/PchSpiSmm.inf = = | 3 +- Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h = = | 301 -------------------- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/Spi= CommonLib.h = | 16 +- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiComm= onLib/BaseSpiCommonLib.inf = | 19 +- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf = = | 1 + Silicon/Intel/TigerlakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeTgl.inf = = | 1 + Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec = = | 8 - 105 files changed, 1101 insertions(+), 2480 deletions(-) delete mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpi= FlashCommonLib/SpiFlashCommon.c delete mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpi= FlashCommonLib/SpiFlashCommonSmmLib.c rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/FvbInfo.c (100%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceCommon.c (96%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceMm.c (94%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.c (100%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceTraditionalMm.c (100%) rename Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib= /SpiFlashCommonSmmLib.c =3D> Silicon/Intel/IntelSiliconPkg/Library/SmmSpi= FlashCommonLib/SmmSpiFlashCommonLib.c (90%) rename {Platform/Intel/TigerlakeOpenBoardPkg =3D> Silicon/Intel/IntelSil= iconPkg}/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c (93%) rename {Platform/Intel/MinPlatformPkg/Flash =3D> Silicon/Intel/IntelSili= conPkg}/Library/SpiFlashCommonLibNull/SpiFlashCommonLibNull.c (83%) delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFl= ashCommonLib/SpiFlashCommon.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFl= ashCommonLib/SpiFlashCommonSmmLib.c delete mode 100644 Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommo= nLib/SpiFlashCommon.c delete mode 100644 Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommo= nLib/SpiFlashCommonSmmLib.c delete mode 100644 Platform/Intel/MinPlatformPkg/Include/Library/SpiFlas= hCommonLib.h rename {Silicon/Intel/CoffeelakeSiliconPkg/Pch =3D> Platform/Intel/Whitl= eyOpenBoardPkg}/Include/Library/SpiFlashCommonLib.h (96%) delete mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpi= FlashCommonLib/SmmSpiFlashCommonLib.inf rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceCommon.h (100%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceMm.h (100%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceSmm.inf (88%) rename {Platform/Intel/MinPlatformPkg =3D> Silicon/Intel/IntelSiliconPkg= /Feature}/Flash/SpiFvbService/SpiFvbServiceStandaloneMm.inf (88%) create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Guid/FlashRegio= n.h rename Silicon/Intel/{SimicsIch10Pkg =3D> IntelSiliconPkg}/Include/Libra= ry/SpiFlashCommonLib.h (96%) rename Silicon/Intel/{CoffeelakeSiliconPkg/Pch =3D> IntelSiliconPkg}/Inc= lude/Ppi/Spi.h (85%) rename Silicon/Intel/{CoffeelakeSiliconPkg/Pch =3D> IntelSiliconPkg}/Inc= lude/Protocol/Spi.h (89%) rename {Platform/Intel/TigerlakeOpenBoardPkg =3D> Silicon/Intel/IntelSil= iconPkg}/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf (67%) rename {Platform/Intel/MinPlatformPkg/Flash =3D> Silicon/Intel/IntelSili= conPkg}/Library/SpiFlashCommonLibNull/SpiFlashCommonLibNull.inf (91%) delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/= SpiFlashCommonLib.h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Ppi/Spi.= h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Protocol= /Spi.h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Pch/Library/SmmSpiFl= ashCommonLib/SmmSpiFlashCommonLib.inf delete mode 100644 Silicon/Intel/SimicsIch10Pkg/Include/Protocol/Spi.h delete mode 100644 Silicon/Intel/SimicsIch10Pkg/Library/SmmSpiFlashCommo= nLib/SmmSpiFlashCommonLib.inf delete mode 100644 Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Sp= i.h --=20 2.28.0.windows.1
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Re: [PATCH v2 3/4] ArmPlatformPkg: retreive error source descriptors from MM
Sami Mujawar
Hi Omkar, Please find my response inline marked [SAMI]. Regards, Sami Mujawar On 10/07/2021 05:18 PM, Omkar Anand
Kulkarni wrote:
[SAMI] Should this patch be split into 2?Add a driver that retreives error source descriptors from MM and populates those into the HEST ACPI table. The error source descriptors that are available from the MM side are retreived using MM Communicate 2 protocol. The first call into the MM returns the size of MM Communicate buffer required to hold all error source descriptor info. The communication buffer of that size is then allocated and the second call into MM returns the error source descriptors in the communication buffer. The retreived error source descriptors are then appended to the HEST table. Co-authored-by: Thomas Abraham <thomas.abraham@...> Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...> --- ArmPlatformPkg/ArmPlatformPkg.dec | 7 + ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.inf | 44 +++ ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandaloneMm.inf | 51 ++++ ArmPlatformPkg/Drivers/HestMmErrorSources/HestMmErrorSourceCommon.h | 37 +++ ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.c | 308 +++++++++++++++++++ ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandaloneMm.c | 312 ++++++++++++++++++++
[SAMI] I feel there can be a simple way to do this, see the comments
below.
[SAMI] Does the Total size also include the size of
ErrSourceDescCount and ErrSourceDescSize?
[SAMI] Can the first 2 fields of this structure be moved to a structure called HEST_ERROR_SOURCE_DESC_HEADER? I think it may simplify computing of the size of HEST_ERROR_SOURCE_DESC_INFO.+ UINTN ErrSourceDescSize; [/SAMI] [SAMI] Can this definition be moved to MdePkg\Include\Protocol\MmCommunication.h, please ?+ // + // Array of error source descriptors that is ErrSourceDescSize in size. + // + UINT8 ErrSourceDescList[1]; +} HEST_ERROR_SOURCE_DESC_INFO; + +#endif // HEST_ERROR_SOURCE_DESCRIPTOR_H_ diff --git a/ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.c b/ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.c new file mode 100644 index 000000000000..acfb0fc9e838 --- /dev/null +++ b/ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.c @@ -0,0 +1,308 @@ +/** @file + Collects and appends the HEST error source descriptors from the MM drivers. + + The drivers entry point locates the MM Communication protocol and calls into + Standalone MM to get the HEST error sources length and count. It also + retrieves descriptor information. The information is then used to build the + HEST table using the HEST table generation protocol. + + This driver collects the secure error source descriptor information from the + MM drviers that implement HEST error source protocol. Instead of directly + communicating with the individual MM drivers, it calls into + HestErrorSourceStandaloneMM driver which is a gatway MM driver. This MM driver + in-turn communicates with individual MM drivers collecting the error source + descriptor information. + + Once all the error source descriptor information is retrieved the driver + appends the descriptors to HEST table using the HestDxe driver. + + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Protocol/MmCommunication2.h> +#include <Protocol/HestTable.h> +#include "HestMmErrorSourceCommon.h" + +#define MM_COMMUNICATE_HEADER_SIZE (OFFSET_OF (EFI_MM_COMMUNICATE_HEADER, Data))
[SAMI] Can you check if the third parameter to Communicate() is
correct, please?[SAMI] VOID and ) should be on a separate line. Can you check the other patches in this series as well, please?+ NULL + ); + + return Status; +} + +/** + Collect HEST error source descriptors from all Standalone MM drivers and + append them to the HEST table. + + Use MM Communication Protocol to communicate and collect the error source + descriptor information from Standalone MM. Check for the required buffer size + returned by the MM driver. Allocate buffer of adequate size and call again + into MM. + + @retval EFI_SUCCESS Successful to collect and append the error + source. + descriptors to HEST table. + @retval EFI_OUT_OF_RESOURCES Memory allocation failure. + @retval Other For any other error. +**/ +STATIC +EFI_STATUS +AppendMmErrorSources (VOID)
[SAMI] Would it be better to use AllocateZeroPool() ?
[SAMI] return EFI_NOT_FOUND ?
[SAMI] Can EFI_NOT_FOUND be returned here?
[SAMI] AllocateZeroPool() ?
[SAMI] Is check for HandleBuffer == NULL right here?
[SAMI] I think the error handling in this function and the error
return implementation in GetHestErrorSourceDescriptors() could be
improved. e.g. GetHestErrorSourceDescriptors() could first check for the SourceLength & SourceCount and if it is less than what is required, it returns EFI_BUFFER_TOO_SMALL. The next check would be to check ErrorSourcePtr and return EFI_INVALID_PARAMETER if it is NULL. [/SAMI]
[SAMI] Should the return code be EFI_BUFFER_TOO_SMALL? The
difference being, the caller can attempt to call again with a larger
buffer if EFI_BUFFER_TOO_SMALL is returned. CommBufferSize is declared as an OUT paramter, was the intent to return the required buffer size? [/SAMI]
[SAMI] return Status of last operation.
[SAMI] return Status of last operation.+}
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Re: [PATCH v2 2/4] ArmPlatformPkg: add definition for MM_HEST_ERROR_SOURCE_DESC_PROTOCOL
Sami Mujawar
Hi Omkar, Please find my response below marked [SAMI] Sami Mujawar On 10/07/2021 05:18 PM, Omkar Anand
Kulkarni wrote:
[SAMI] Not sure if a trailing underscore would be right to use for the name tag. Can MmHestErrorSourceDescProtocol be used as the name tag?Add the protocol definition of the MM_HEST_ERROR_SOURCE_DESC_PROTOCOL protocol. This protocol can be implemented by MM drivers to publish error source descriptors that have to be populated into HEST table. Co-authored-by: Thomas Abraham <thomas.abraham@...> Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...> --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/Include/Protocol/HestErrorSourceInfo.h | 64 ++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index e4afe5da8e11..4f062292663b 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -131,3 +131,4 @@ [Protocols.common] ## Arm Platform HEST table generation protocol gHestTableProtocolGuid = { 0x705bdcd9, 0x8c47, 0x457e, { 0xad, 0x0d, 0xf7, 0x86, 0xf3, 0x4a, 0x0d, 0x63 } } + gMmHestErrorSourceDescProtocolGuid = { 0x560bf236, 0xa4a8, 0x4d69, { 0xbc, 0xf6, 0xc2, 0x97, 0x24, 0x10, 0x9d, 0x91 } } diff --git a/ArmPlatformPkg/Include/Protocol/HestErrorSourceInfo.h b/ArmPlatformPkg/Include/Protocol/HestErrorSourceInfo.h new file mode 100644 index 000000000000..95afd4dffe9c --- /dev/null +++ b/ArmPlatformPkg/Include/Protocol/HestErrorSourceInfo.h @@ -0,0 +1,64 @@ +/** @file + MM protocol to get the secure error source descriptor information. + + MM Drivers must implement this protocol in order to publish secure side + error source descriptor information to OSPM through the HEST ACPI table. + + Copyright (c) 2020 - 2021, ARM Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef MM_HEST_ERROR_SOURCE_DESC_ +#define MM_HEST_ERROR_SOURCE_DESC_ + +#define MM_HEST_ERROR_SOURCE_DESC_PROTOCOL_GUID \ + { \ + 0x560bf236, 0xa4a8, 0x4d69, { 0xbc, 0xf6, 0xc2, 0x97, 0x24, 0x10, 0x9d, 0x91 } \ + } + +typedef struct MM_HEST_ERROR_SOURCE_DESC_PROTOCOL_ Also see https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/56_declarations_and_types#5-6-3-2-structure-declaration-with-forward-reference-or-self-reference
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Re: [edk2-platforms PATCH v6 0/4] Secure Boot default keys
Sunny Wang
Hi Ard and Maintainers,
toggle quoted messageShow quoted text
For this patchset, 1/4 - Intel Platforms: add SecureBootVariableLib class resolution 2/4 - ARM Silicon and Platforms: add SecureBootVariableLib class resolution 3/4 - RISC-V Platforms: add SecureBootVariableLib class resolution 4/4 - Platform/RaspberryPi: Enable default Secure Boot variables initialization Only Intel platform patch (1/4) hasn't got all Review-bys. I offline sent a reminder to Intel platform Maintainers. I think they may be busy with other things or need more time to review it. Therefore, how about we merge another three patches (2/4, 3/4, and 4/4) first? Best Regards, Sunny Wang
-----Original Message-----
From: Grzegorz Bernacki <gjb@...> Sent: Wednesday, July 14, 2021 8:31 PM To: devel@edk2.groups.io Cc: leif@...; ardb+tianocore@...; Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; Sunny Wang <Sunny.Wang@...>; mw@...; upstream@...; jiewen.yao@...; jian.j.wang@...; min.m.xu@...; lersek@...; Sami Mujawar <Sami.Mujawar@...>; afish@...; ray.ni@...; jordan.l.justen@...; rebecca@...; grehan@...; Thomas Abraham <thomas.abraham@...>; chasel.chiu@...; nathaniel.l.desimone@...; gaoliming@...; eric.dong@...; michael.d.kinney@...; zailiang.sun@...; yi.qian@...; graeme@...; rad@...; pete@...; Grzegorz Bernacki <gjb@...> Subject: [edk2-platforms PATCH v6 0/4] Secure Boot default keys This patchset is a consequence of "Secure Boot default keys" patchset in edk2. It adds SecureBootVariableLib class resolution for each platform which uses SecureBootConfigDxe and also enables Secure Boot variables initialization for RPi4. Previously these commits were part of edk2 patchset, but since number of commits increased in v5 version, it is now separate patchset. Changes related to both edk2 & edk-platform versions: Changes since v1: - change names: SecBootVariableLib => SecureBootVariableLib SecBootDefaultKeysDxe => SecureBootDefaultKeysDxe SecEnrollDefaultKeysApp => EnrollFromDefaultKeysApp - change name of function CheckSetupMode to GetSetupMode - remove ShellPkg dependecy from EnrollFromDefaultKeysApp - rebase to master Changes since v2: - fix coding style for functions headers in SecureBootVariableLib.h - add header to SecureBootDefaultKeys.fdf.inc - remove empty line spaces in SecureBootDefaultKeysDxe files - revert FAIL macro in EnrollFromDefaultKeysApp - remove functions duplicates and add SecureBootVariableLib to platforms which used it Changes since v3: - move SecureBootDefaultKeys.fdf.inc to ArmPlatformPkg - leave duplicate of CreateTimeBasedPayload in PlatformVarCleanupLib - fix typo in guid description Changes since v4: - reorder patches to make it bisectable - split commits related to more than one platform - move edk2-platform commits to separate patchset Changes since v5: - split SecureBootVariableLib into SecureBootVariableLib and SecureBootVariableProvisionLib Grzegorz Bernacki (4): Intel Platforms: add SecureBootVariableLib class resolution ARM Silicon and Platforms: add SecureBootVariableLib class resolution RISC-V Platforms: add SecureBootVariableLib class resolution Platform/RaspberryPi: Enable default Secure Boot variables initialization Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 2 ++ Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc | 2 ++ Platform/Intel/QuarkPlatformPkg/Quark.dsc | 2 ++ Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc | 2 ++ Platform/Intel/Vlv2TbltDevicePkg/PlatformPkgX64.dsc | 2 ++ Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++ Platform/RaspberryPi/RPi3/RPi3.dsc | 2 ++ Platform/RaspberryPi/RPi4/RPi4.dsc | 4 ++++ Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 ++ Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 5 +++++ Platform/RaspberryPi/RPi4/RPi4.fdf | 2 ++ 12 files changed, 29 insertions(+) -- 2.25.1 IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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Re: [staging/edk2-redfish-client PATCH v2 2/2] edk2: Update Maintainers.txt
Thanks Leif, I remove the description from the package name.
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Abner
-----Original Message-----
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Re: [edk2-platforms PATCH v5 1/2] Platform/RaspberryPi: Enable Boot Discovery Policy.
Ard Biesheuvel
On Tue, 3 Aug 2021 at 15:08, Pete Batard <pete@...> wrote:
... Thanks Pete. I did not want to assume that stakeholders like yourself are ok with such changes if they did not get involved in the discussion. I will merge these now.
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Re: [edk2-test][PATCH v1 1/1] uefi-sct/SctPkg: Update page alignment calculations
Samer El-Haj-Mahmoud
+Heinrich
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Re: Proposing a new area of the edk2-test repository
Samer El-Haj-Mahmoud
I would think just sending the code contribution patch is sufficient.
From: Nelson, Eric <eric.nelson@...>
Sent: Wednesday, July 28, 2021 3:05 PM To: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; Bret Barkelew <Bret.Barkelew@...>; devel@edk2.groups.io; G Edhaya Chandran <Edhaya.Chandran@...>; gaojie@...; Kinney, Michael D <michael.d.kinney@...> Subject: RE: Proposing a new area of the edk2-test repository
Adding ResumeOK.efi tool under /edk2-test/test-tools/TestToolsPkg would be great.
Should I propose this in the RFC and DEVEL mailing lists as a next step?
Thanks, __e
From: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
Interesting, thanks for sharing Bret. Some of those tests seem to be x64 specific (SMM tests), and some can be more generic like MorLockTestApp
Like I said earlier, I am not against adding test tools to edk2-test. That in fact is welcomed, especially if their usefulness in validating the solutions extend beyond specific implementations.
What would a good tree structure look like to accommodate misc tools? Today we have
/edk2-test/uefi-sct/SctPkg
How about something like this? /edk2-test/test-tools/TestToolsPkg or /edk2-test/ TestToolsPkg
The “ResumeOK” can be placed there
Any other ideas?
From: Bret Barkelew <Bret.Barkelew@...>
Fun fact! Mu also has a number of apps and things that we could work on moving to EDK2 if there were a suitable location. Right now, many of them are here: mu_plus/UefiTestingPkg at release/202102 · microsoft/mu_plus (github.com)
- Bret
From: Nelson, Eric via groups.io
I have created a few other internal apps that build under WinTestPkg, although ResumeOK.efi is the only one I have received permissions to release sources for at this time. And yes, they are primarily intended for validating Windows requirements. I had some issues with my apps, needing to use different libraries than MdeModulePkg, and found it easier to create my own package, and use the libs I want.
__e
From: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
+edk2 list
I am not against adding additional test tools to edk2-test. Just feel like there is a need to organize and have a strategy, rather than just use edk2-test as a dumping group of miscellaneous tools.
There is already a place for apps under https://github.com/tianocore/edk2/tree/master/MdeModulePkg/Application
We also have a number of EDK2 misc applications that use edk2-libc in https://github.com/tianocore/edk2-libc/tree/master/AppPkg/Applications
A couple of questions:
From: Nelson, Eric <eric.nelson@...>
Hi Edhay,
Do you have any more questions? What do you think of creating another directory in edk2-test, for other test apps, in addition to uefi-sct, such as ResumeOK.efi?
Thanks, __e
From: Nelson, Eric
Hi Edhay,
ResumeOK.efi is a tool I wrote from the HelloWorld example, that validates Windows resume from S4 requirements, specifically that the memory-map run-time memory regions don’t change, and secondly that PCI devices don’t disappear from the system, both conditions would cause Windows to fail to resume from S4.
You install the tool to the root of the ESP, and set it as the default/top entry in the boot manager, and launch it. (Disable Secure Boot.)
It runs warm, cold, and 60s ACPI RTC wake cycles, infinitely looking for errors.
ResumeOK.efi writes a file to the root of the ESP, ResumeOK.map, which contains the ACPI Facs->HardwareSignature, a list of the PCI devices in the system, and a copy of its memory map, from the first time it runs.
During each test pass, it runs a barrage of tests:
If any of the tests fail, then the new/missing PCI devices are listed (HW signature fail case), or the memory descriptor that changed, it’s location, and current and previous type and size.
I have received permission from Intel to *try* to release the source under Edk2-test.
I’ve included a 64-bit binary, if you want to give it a test drive.
Make sure Secure Boot is off. Also, it is required to manually delete any ResumeOK.map on the ESP, before beginning a new test pass.
The tool also supports a host of EFI Shell commands:
Resumeok.efi MEMMAP – displays Windows coalesced view of the current memory map ResumeOK.efi ROKMAP – displays Windows coalesced view of the memory saved in ResumeOK.map ResumeOK.efi RTDATA – displays an analysis of RT_Data pool usage ResumeOK.efi NORESET – run one test pass, but suppress automatic SX cycling
These are the files that build it:
Edk2\WinTestPkg\Application Edk2\WinTestPkg\WinTestPkg.dec Edk2\WinTestPkg\WinTestPkg.dsc Edk2\WinTestPkg\Application\ResumeOK Edk2\WinTestPkg\Application\ResumeOK\AcpiTbl.c Edk2\WinTestPkg\Application\ResumeOK\AcpiTbl.h Edk2\WinTestPkg\Application\ResumeOK\AppSupport.c Edk2\WinTestPkg\Application\ResumeOK\BitMap.c Edk2\WinTestPkg\Application\ResumeOK\BitMap.h Edk2\WinTestPkg\Application\ResumeOK\EfiFileLib.c Edk2\WinTestPkg\Application\ResumeOK\EfiFileLib.h Edk2\WinTestPkg\Application\ResumeOK\pci.c Edk2\WinTestPkg\Application\ResumeOK\Pci.h Edk2\WinTestPkg\Application\ResumeOK\ResumeOK.c Edk2\WinTestPkg\Application\ResumeOK\ResumeOK.h Edk2\WinTestPkg\Application\ResumeOK\ResumeOK.inf Edk2\WinTestPkg\Application\ResumeOK\ResumeOK.uni Edk2\WinTestPkg\Application\ResumeOK\ResumeOKExtra.uni Edk2\WinTestPkg\Application\ResumeOK\RtData.c Edk2\WinTestPkg\Application\ResumeOK\TimeBaseLib.c
Thanks, __e
From: G Edhaya Chandran <Edhaya.Chandran@...>
Hi Eric,
Thanks for reaching out to us. Can we get more details of the tool?
Is this tool already open sourced or could you send us the basic documentation pertaining to it.
With Warm Regards,
From: Nelson, Eric <eric.nelson@...>
Hello SCT maintainers,
I’m looking to release source to a UEFI validation tool that has been a big hit with platform BIOS validation teams, so it can help other PC vendors.
My coworker Michael Kinney suggested I reach out to you directly about the idea of creating a new top level directory in the edk2-test repro for other test apps, and I could be maintainer.
What do you think of creating another directory in edk2-test, for other test apps, in addition to uefi-sct?
Thanks! __e
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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Re: [edk2-platforms PATCH v5 1/2] Platform/RaspberryPi: Enable Boot Discovery Policy.
Hi Ard,
I thought the R-b from Sunny was enough. For what is worth, I briefly tested these changes for v4. Thus: On 2021.08.03 14:03, Ard Biesheuvel wrote: On Tue, 3 Aug 2021 at 15:00, Samer El-Haj-MahmoudReviewed-by: Pete Batard <pete@...> Tested-by: Pete Batard <pete@...>
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Re: [edk2-platforms PATCH v5 1/2] Platform/RaspberryPi: Enable Boot Discovery Policy.
Ard Biesheuvel
On Tue, 3 Aug 2021 at 15:00, Samer El-Haj-Mahmoud
<Samer.El-Haj-Mahmoud@...> wrote: I only see acks from Sunny though. This is why I asked Pete and Andrei to chime in as well. -----Original Message-----IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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Re: [edk2-platforms PATCH v5 1/2] Platform/RaspberryPi: Enable Boot Discovery Policy.
Samer El-Haj-Mahmoud
Ard,
toggle quoted messageShow quoted text
Now that the EDK2 changes are merged (aaecef38b9440a65809cbdaf9d97029f4eeb), I think these RPi specific changes are ready to be merged as well.
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Re: [staging/edk2-redfish-client PATCH v2 2/2] edk2: Update Maintainers.txt
Leif Lindholm
On Tue, Jul 20, 2021 at 11:53:58 +0800, Abner Chang wrote:
Add maintainer and reviewer to RedfishClinetPkg.My interpretation of the normal use of this field is that we can add a comment if the entry applies only to a subset of a package. This adds an entry for a whole new package, and as such should only state the name of the package. With everything from the : until the end of line dropped: Reviewed-by: Leif Lindholm <leif@...> / Leif +F: RedfishClientPkg/
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Re: [Patch V2 3/3] Maintainers.txt: Add GitHub IDs
Leif Lindholm
On Thu, Jul 08, 2021 at 12:50:47 -0700, Michael D Kinney wrote:
Cc: Andrew Fish <afish@...>Reviewed-by: Leif Lindholm <leif@...> Apologies for tardiness. ---
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