Date   

Re: [RFC PATCH] OvmfPkg/OvmfXen: set PcdAcpiS3Enable at initialization

Anthony PERARD
 

On Thu, Jul 08, 2021 at 12:05:49PM +0800, Gary Lin wrote:
There are several functions in OvmfPkg/Library using
QemuFwCfgS3Enabled() to detect the S3 support status. However, in
MdeModulePkg, PcdAcpiS3Enable is used to check S3 support. Since
InitializeXenPlatform() didn't set PcdAcpiS3Enable as
InitializePlatform() did, this made the inconsistency between
drivers/functions.

For example, S3SaveStateDxe checked PcdAcpiS3Enable and skipped
S3BootScript because the default value is FALSE. On the other hand,
PlatformBootManagerBeforeConsole() from OvmfPkg/Library called
QemuFwCfgS3Enabled() and found it returned TRUE, so it invoked
SaveS3BootScript(). However, S3SaveStateDxe skipped S3BootScript, so
SaveS3BootScript() asserted due to EFI_NOT_FOUND.

Setting PcdAcpiS3Enable at InitializeXenPlatform() "fixes" the crash
reported by my colleague. The other possible direction is to replace
QemuFwCfgS3Enabled() with PcdAcpiS3Enable. I'm not sure which one is
the right fix.
QemuFwCfgS3Enabled() should always return false as we don't enable
QEMU's fwcfg interface in most case when running a Xen guest. So I don't
expect "PcdAcpiS3Enable" to ever been set via this patch.

Now, maybe we want to set PcdAcpiS3Enable unconditionally but I don't
know if S3 support is going to work as expected with OVMF under Xen, I
never look at that.

What kind of guest are you trying to fix? When does the crash happen?

Thanks,

--
Anthony PERARD


Re: [edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables

Ard Biesheuvel
 

On Mon, 19 Jul 2021 at 11:31, Marcin Wojtas <mw@semihalf.com> wrote:

BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT.
Fix that for all platforms with the Marvell SoC's.
Can we fix the BBR instead? If ACPI itself does not require _STA, BBR
should not require it either.



Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 +++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 +++++++++++++++
5 files changed, 272 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
index 345c1e4dd6..88e38efeeb 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
index 91401c74c8..77d3aebaf1 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
index d26945d933..1ecbd0309c 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0101") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
index 8377b13763..d6619e367b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index d76a2a902b..536df8ab4b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0003") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
--
2.29.0


Re: [edk2-platforms PATCH 0/4] ACPI MDIO support for Marvell SoCs

Marcin Wojtas
 

Hi Ard,

pon., 19 lip 2021 o 09:28 Ard Biesheuvel <ardb@kernel.org> napisał(a):

On Fri, 16 Jul 2021 at 19:32, Ard Biesheuvel <ardb@kernel.org> wrote:

On Mon, 12 Jul 2021 at 13:17, Jon Nettleton <jon@solid-run.com> wrote:

On Mon, Jul 12, 2021 at 12:52 PM Marcin Wojtas <mw@semihalf.com> wrote:

Hi,

wt., 29 cze 2021 o 16:17 Marcin Wojtas <mw@semihalf.com> napisał(a):

Hi Leif,

pon., 14 cze 2021 o 23:55 Leif Lindholm <leif@nuviainc.com> napisał(a):

Hi Marcin,

On Sun, Jun 13, 2021 at 20:16:27 +0200, Marcin Wojtas wrote:
Hi,

The MDIO ACPI binding has been established and merged to the
Linux tree,
Congratulations! :)

Is FreeBSD expected to follow suit?
There's no driver yet, but once it's finally created I will make sure
it supports ACPI properly.


hence it is now possible to update the ACPI
description of the platforms that base on the Marvell SoCs.

For convenience, the code is exposed in the public github branch:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/acpi-mdio-r20210613
There is also MacchiatoBin firmware binary avaialable for testing:
https://drive.google.com/file/d/1eigP_aeM4wYQpEaLAlQzs3IN_w1-kQr0

I'm looking forward to the comments or remarks.
The patches themselves look straightforward enough.
I *would* prefer some tested-by, for these sources rather than the
binary, before merging though.
I have some our patches queued, that are blocked by this patchset. In
case no time is found for external testers - if this may help to get
it pushed through, please see below logs from the next-20210628 tag
and unchanged firmware. All network ports of MacchiatoBin and
CN913x-DB work properly, with full 1G/10G PHY support via X/MDIO
interfaces:

MacchiatoBin
# uname -a
Linux buildroot 5.13.0-rc7-next-20210628 #6 SMP PREEMPT Tue Jun 29
09:14:07 CEST 2021 aarch64 GNU/Linux
# dmesg | grep MRVL0101
[ 1.829659] mv88x3340 MRVL0101:00-mii:00: Firmware version 0.3.3.0
[ 1.839622] mv88x3340 MRVL0101:00-mii:08: Firmware version 0.3.3.0
[ 2.748351] mvpp2 MRVL0110:00 eth1: PHY [MRVL0101:00-mii:00] driver
[mv88x3340] (irq=POLL)
[ 2.767479] mvpp2 MRVL0110:01 eth2: PHY [MRVL0101:00-mii:08] driver
[mv88x3340] (irq=POLL)
# dmesg | grep MRVL0100
[ 2.919424] mvpp2 MRVL0110:01 eth3: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
# dmesg | grep mvpp2
[...]
[ 2.748351] mvpp2 MRVL0110:00 eth1: PHY [MRVL0101:00-mii:00] driver
[mv88x3340] (irq=POLL)
[ 2.756701] mvpp2 MRVL0110:00 eth1: configuring for phy/10gbase-r link mode
[ 2.767479] mvpp2 MRVL0110:01 eth2: PHY [MRVL0101:00-mii:08] driver
[mv88x3340] (irq=POLL)
[ 2.775834] mvpp2 MRVL0110:01 eth2: configuring for phy/10gbase-r link mode
[ 2.919424] mvpp2 MRVL0110:01 eth3: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.928285] mvpp2 MRVL0110:01 eth3: configuring for phy/sgmii link mode
[ 2.936351] mvpp2 MRVL0110:01 eth4: configuring for
inband/2500base-x link mode
[ 5.987259] mvpp2 MRVL0110:01 eth3: Link is Up - 1Gbps/Full - flow
control off
#

CN913x-DB
# uname -a
Linux buildroot 5.13.0-rc7-next-20210628 #6 SMP PREEMPT Tue Jun 29
09:14:07 CEST 2021 aarch64 GNU/Linux
# dmesg | grep MRVL0100
[ 2.621201] mvpp2 MRVL0110:00 eth2: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.741199] mvpp2 MRVL0110:00 eth3: PHY [MRVL0100:00-mii:01] driver
[Marvell 88E1510] (irq=POLL)
# dmesg | grep mvpp2
[...]
[ 2.544917] mvpp2 MRVL0110:00 eth1: configuring for
inband/10gbase-r link mode
[ 2.552480] mvpp2 MRVL0110:00 eth1: Link is Up - 10Gbps/Full - flow
control rx
[ 2.621201] mvpp2 MRVL0110:00 eth2: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.630060] mvpp2 MRVL0110:00 eth2: configuring for phy/rgmii-id link mode
[ 2.741199] mvpp2 MRVL0110:00 eth3: PHY [MRVL0100:00-mii:01] driver
[Marvell 88E1510] (irq=POLL)
[ 2.750056] mvpp2 MRVL0110:00 eth3: configuring for phy/rgmii-id link mode
[ 2.810169] mvpp2 MRVL0110:01 eth4: configuring for
inband/10gbase-r link mode
[ 2.817471] mvpp2 MRVL0110:01 eth4: Link is Up - 10Gbps/Full - flow
control rx
[ 5.693231] mvpp2 MRVL0110:00 eth2: Link is Up - 1Gbps/Full - flow
control off
[ 10.840942] mvpp2 MRVL0110:00 eth1: Link is Down
[ 10.864124] mvpp2 MRVL0110:01 eth4: Link is Down
#
Both platforms were have been additionally tested by Greg, do you have
any comments/objections to merging this patchset?

Thanks,
Marcin
You can add my Tested-by as well. Finally got time over the weekend
to verify on all my Marvell platforms this effects.
Thanks all. I will get to this shortly - apologies for the delay.
Pushed as bfabeef4c9a6..955187a12a8b

Thanks all.
Thanks a lot! I'd appreciate if you were able to take a look at our
new patchset I just submitted on top of the merged changes.

Best regards,
Marcin


[edk2-platforms PATCH 7/7] Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision

Marcin Wojtas
 

After the recent SystemReady ES compliance fixes, ACPI enhancements
and other improvements bump revision of the Marvell-based platforms
to "EDK2 SH 1.0".

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index 05e7f68191..d398d9432f 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -241,7 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0=
000=0D
=0D
[PcdsFixedAtBuild.common]=0D
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL_EFI"=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2 SH 1.0"=0D
gArmPlatformTokenSpaceGuid.PcdCoreCount|4=0D
=0D
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000=0D
@@ -381,6 +381,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302=0D
+ gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.0"=0D
=0D
# TRNG=0D
gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000=0D
--=20
2.29.0


[edk2-platforms PATCH 6/7] Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information

Marcin Wojtas
 

This patch updates 2 fields of the SMBIOS Type0 table.
The "Vendor" and the BiosVersion strings are set according to the
values of the newly introduced PCD's.

Note, that the gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
could not be used, as its format does match the required
by SMBIOS tables (CHAR8 *).

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Marvell.dec | 2 ++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 ++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +++---
3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index cdf8154d40..482a90da25 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -170,6 +170,8 @@
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035=0D
=0D
#Platform description=0D
+ gMarvellTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semih=
alf"|VOID*|0x50000104=0D
+ gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105=0D
gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100=
=0D
gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board=
"|VOID*|0x50000101=0D
gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x5000010=
3=0D
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in=
f b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
index 7722146292..582c0faf25 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -40,6 +40,8 @@
gMarvellTokenSpaceGuid.PcdProductPlatformName=0D
gMarvellTokenSpaceGuid.PcdProductSerial=0D
gMarvellTokenSpaceGuid.PcdProductVersion=0D
+ gMarvellTokenSpaceGuid.PcdFirmwareVendor=0D
+ gMarvellTokenSpaceGuid.PcdFirmwareVersion=0D
=0D
[Protocols]=0D
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED=0D
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c =
b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
index a99291e902..ed67a39cb1 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -77,9 +77,9 @@ STATIC SMBIOS_TABLE_TYPE0 mArmadaDefaultType0 =3D {
};=0D
=0D
STATIC CHAR8 CONST *mArmadaDefaultType0Strings[] =3D {=0D
- "EFI Development Kit II / Marvell\0", /* Vendor */=0D
- "EDK II\0", /* BiosVersion */=0D
- __DATE__"\0", /* BiosReleaseDate */=0D
+ (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVendor), /* Vendor */=0D
+ (CHAR8 CONST *)PcdGetPtr (PcdFirmwareVersion), /* BiosVersion */=0D
+ __DATE__"\0", /* BiosReleaseDate */=0D
NULL=0D
};=0D
=0D
--=20
2.29.0


[edk2-platforms PATCH 5/7] Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe

Marcin Wojtas
 

From: Grzegorz Bernacki <gjb@semihalf.com>

Since the beginning of the EDK2 port Marvell platfroms have been
using a dated EmbeddedPkg's MonotonicCounter driver. Switch
to the actively maintained MonotonicCounterRuntimeDxe, what
fixes ACS3.0 BS.GetNextMonotonicCount test case.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index c919d4bfab..05e7f68191 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -476,7 +476,7 @@
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
=0D
- EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf=0D
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim=
eDxe.inf=0D
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf=0D
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar=
mada7k8k/Armada7k8k.fdf
index e003623f15..bc7284652b 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -112,7 +112,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1=
b30c
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
- INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf=0D
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu=
ntimeDxe.inf=0D
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i=
nf=0D
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
--=20
2.29.0


[edk2-platforms PATCH 4/7] SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table

Marcin Wojtas
 

The DBG2 table is mandatory as per SBBR v1.2 specification.
Expose it via J25 jumper on the Armada 8040 MacchiatoBin
platform.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 +
Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 +++
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 +++++=
+++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 33 +++++=
++++
Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 -
7 files changed, 121 insertions(+), 2 deletions(-)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D=
bg2.h
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/D=
bg2.aslc

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Si=
licon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
index 7cf9ecfbfd..98e5cc8b6e 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
@@ -18,6 +18,7 @@
VERSION_STRING =3D 1.0=0D
=0D
[Sources]=0D
+ Armada80x0McBin/Dbg2.aslc=0D
Armada80x0McBin/Dsdt.asl=0D
Armada80x0McBin/Mcfg.aslc=0D
Fadt.aslc=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/M=
arvell/Armada7k8k/AcpiTables/AcpiHeader.h
index 90ab607845..9d83ba7837 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h
@@ -11,6 +11,8 @@
=0D
#include <IndustryStandard/Acpi.h>=0D
=0D
+#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP=
I_5_0_BYTE, Address }=0D
+=0D
#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}=0D
#define ACPI_OEM_REVISION 0=0D
#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h b=
/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h
new file mode 100644
index 0000000000..b8ac770ed5
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h
@@ -0,0 +1,9 @@
+/**=0D
+=0D
+ Copyright (C) 2021, Semihalf.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#define ARMADA80X0_MCBIN_DBG2_UART_REG_BASE 0xF2702100=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico=
n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
index dd33cb5e7b..b106790913 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h
@@ -22,6 +22,8 @@
#define CP_GIC_SPI_CP0_USB_H1 112=0D
#define CP_GIC_SPI_CP0_USB_H0 113=0D
#define CP_GIC_SPI_CP0_SATA_H0 114=0D
+#define CP_GIC_SPI_CP0_UART0 121=0D
+#define CP_GIC_SPI_CP0_UART1 122=0D
=0D
#define CP_GIC_SPI_CP1_PCI0 288=0D
#define CP_GIC_SPI_CP1_PCI1 289=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.asl=
c b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc
new file mode 100644
index 0000000000..1e6d99ee9e
--- /dev/null
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc
@@ -0,0 +1,74 @@
+/** @file=0D
+* Debug Port Table (DBG2)=0D
+*=0D
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.=0D
+* Copyright (c) 2021 ARM Ltd. All rights reserved.=0D
+* Copyright (c) 2021 Semihalf. All rights reserved.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+#include <IndustryStandard/Acpi.h>=0D
+#include <IndustryStandard/DebugPort2Table.h>=0D
+#include <Library/AcpiLib.h>=0D
+#include <Library/PcdLib.h>=0D
+=0D
+#include "AcpiHeader.h"=0D
+#include "Armada80x0McBin/Dbg2.h"=0D
+=0D
+#pragma pack(1)=0D
+=0D
+#define ARMADA7K8K_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2'=
, 0x00 }=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;=0D
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;=0D
+ UINT32 AddressSize;=0D
+ UINT8 NameSpaceString[10];=0D
+} DBG2_DEBUG_DEVICE_INFORMATION;=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;=0D
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;=0D
+} DBG2_TABLE;=0D
+=0D
+=0D
+STATIC DBG2_TABLE Dbg2 =3D {=0D
+ {=0D
+ __ACPI_HEADER (=0D
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,=0D
+ DBG2_TABLE,=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION=0D
+ ),=0D
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),=0D
+ 1 /* NumberOfDebugPorts */=0D
+ },=0D
+ {=0D
+ {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),=0D
+ 1, /* NumberofGenericAddressRegist=
ers */=0D
+ 10, /* NameSpaceStringLength */=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),=0D
+ 0, /* OemDataLength */=0D
+ 0, /* OemDataOffset */=0D
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB=
GP_SPEC,=0D
+ {=0D
+ EFI_ACPI_RESERVED_BYTE,=0D
+ EFI_ACPI_RESERVED_BYTE=0D
+ },=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)=0D
+ },=0D
+ MV_UART_AS32 (ARMADA80X0_MCBIN_DBG2_UART_REG_BASE), /* BaseAddress */=
=0D
+ SIZE_4KB, /* AddressSize */=
=0D
+ ARMADA7K8K_UART_STR, /* NameSpaceStrin=
g */=0D
+ }=0D
+};=0D
+=0D
+#pragma pack()=0D
+=0D
+// Reference the table being generated to prevent the optimizer from remov=
ing=0D
+// the data structure from the executable=0D
+VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl=
b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
index 1ecbd0309c..a7d1c76e07 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -8,6 +8,7 @@
=0D
**/=0D
=0D
+#include "Armada80x0McBin/Dbg2.h"=0D
#include "Armada80x0McBin/Pcie.h"=0D
#include "IcuInterrupts.h"=0D
=0D
@@ -246,6 +247,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA8K", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
Method (_STA) // _STA: D=
evice status=0D
{=0D
Return (0xF)=0D
@@ -272,6 +274,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
})=0D
}=0D
=0D
+ Device (COM2)=0D
+ {=0D
+ Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
+ Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: A=
ddress=0D
+ Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ ARMADA80X0_MCBIN_DBG2_UART_REG_BASE, // Address=
Base=0D
+ 0x00000100, // Address=
Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_UART1=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSe=
rialClockRate) },=0D
+ Package () { "reg-io-width", 1 },=0D
+ Package () { "reg-shift", 2 },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
Device (SMI0)=0D
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv=
ell/Armada7k8k/AcpiTables/Spcr.aslc
index 6efc175bdf..48e6699f52 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc
@@ -15,8 +15,6 @@
=0D
#include "AcpiHeader.h"=0D
=0D
-#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP=
I_5_0_BYTE, Address }=0D
-=0D
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D {=0D
__ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU=
RE,=0D
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,=0D
--=20
2.29.0


[edk2-platforms PATCH 3/7] Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table

Marcin Wojtas
 

The DBG2 table is mandatory as per SBBR v1.2 specification.
Introduce it via CP0_UART0 interface.

Note: in order to use it, DPR58 and DPR59 must be switched to
positions 2-3.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +-
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 +++++++++=
+++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 33 +++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 -
9 files changed, 124 insertions(+), 4 deletions(-)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.=
aslc

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell=
/Cn913xDb/Cn9130DbA.dsc.inc
index 33fb7ccc08..756d875f6c 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -32,8 +32,8 @@
gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64=0D
gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0=
x3, 0x3, 0x3, 0x3 }=0D
gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0=
x3, 0x1, 0x1, 0x1 }=0D
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0=
x1, 0x1, 0x3, 0x9 }=0D
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0=
x2, 0x2, 0x2, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0=
x1, 0x1, 0x3, 0xA }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0=
x2, 0x2, 0x2, 0x1 }=0D
gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0=
x1, 0x1, 0x1, 0x1 }=0D
gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0=
xE, 0xE, 0xE, 0xE }=0D
gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silico=
n/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
index 191a747585..2cd13aa2b6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
@@ -18,6 +18,7 @@
VERSION_STRING =3D 1.0=0D
=0D
[Sources]=0D
+ Cn913xDbA/Dbg2.aslc=0D
Cn913xDbA/Dsdt.asl=0D
Cn913xDbA/Mcfg.aslc=0D
Fadt.aslc=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silico=
n/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
index bbf1b5133a..0c9fb82682 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
@@ -19,6 +19,7 @@
=0D
[Sources]=0D
Cn9131DbA/Ssdt.asl=0D
+ Cn913xDbA/Dbg2.aslc=0D
Cn913xDbA/Dsdt.asl=0D
Cn913xDbA/Mcfg.aslc=0D
Fadt.aslc=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon=
/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
index 283867692e..b93799dd03 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -11,6 +11,8 @@
=0D
#include <IndustryStandard/Acpi.h>=0D
=0D
+#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP=
I_5_0_BYTE, Address }=0D
+=0D
#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}=0D
#define ACPI_OEM_REVISION 0=0D
#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h b/Sil=
icon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
new file mode 100644
index 0000000000..4584967016
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
@@ -0,0 +1,9 @@
+/**=0D
+=0D
+ Copyright (C) 2021, Semihalf.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#define CN913X_DBG2_UART_REG_BASE 0xF2702000=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Sili=
con/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
index 6befe2ae54..83006ebd8a 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -22,6 +22,8 @@
#define CP_GIC_SPI_CP0_USB_H1 112=0D
#define CP_GIC_SPI_CP0_USB_H0 113=0D
#define CP_GIC_SPI_CP0_SATA_H0 114=0D
+#define CP_GIC_SPI_CP0_UART0 121=0D
+#define CP_GIC_SPI_CP0_UART1 122=0D
=0D
#define CP_GIC_SPI_CP1_PCI0 288=0D
#define CP_GIC_SPI_CP1_PCI1 289=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc b/=
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
new file mode 100644
index 0000000000..bea55d0114
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc
@@ -0,0 +1,74 @@
+/** @file=0D
+* Debug Port Table (DBG2)=0D
+*=0D
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.=0D
+* Copyright (c) 2021 ARM Ltd. All rights reserved.=0D
+* Copyright (c) 2021 Semihalf. All rights reserved.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+#include <IndustryStandard/Acpi.h>=0D
+#include <IndustryStandard/DebugPort2Table.h>=0D
+#include <Library/AcpiLib.h>=0D
+#include <Library/PcdLib.h>=0D
+=0D
+#include "AcpiHeader.h"=0D
+#include "Cn913xDbA/Dbg2.h"=0D
+=0D
+#pragma pack(1)=0D
+=0D
+#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x=
00 }=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;=0D
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;=0D
+ UINT32 AddressSize;=0D
+ UINT8 NameSpaceString[10];=0D
+} DBG2_DEBUG_DEVICE_INFORMATION;=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;=0D
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;=0D
+} DBG2_TABLE;=0D
+=0D
+=0D
+STATIC DBG2_TABLE Dbg2 =3D {=0D
+ {=0D
+ __ACPI_HEADER (=0D
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,=0D
+ DBG2_TABLE,=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION=0D
+ ),=0D
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),=0D
+ 1 /* NumberOfDebugPorts */=0D
+ },=0D
+ {=0D
+ {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),=0D
+ 1, /* NumberofGenericAddressRegist=
ers */=0D
+ 10, /* NameSpaceStringLength */=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),=0D
+ 0, /* OemDataLength */=0D
+ 0, /* OemDataOffset */=0D
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB=
GP_SPEC,=0D
+ {=0D
+ EFI_ACPI_RESERVED_BYTE,=0D
+ EFI_ACPI_RESERVED_BYTE=0D
+ },=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)=0D
+ },=0D
+ MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */=
=0D
+ SIZE_4KB, /* AddressSize */=
=0D
+ CN913X_UART_STR, /* NameSpaceStrin=
g */=0D
+ }=0D
+};=0D
+=0D
+#pragma pack()=0D
+=0D
+// Reference the table being generated to prevent the optimizer from remov=
ing=0D
+// the data structure from the executable=0D
+VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S=
ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index 536df8ab4b..7335e443c6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -9,6 +9,7 @@
=0D
**/=0D
=0D
+#include "Cn913xDbA/Dbg2.h"=0D
#include "Cn913xDbA/Pcie.h"=0D
#include "IcuInterrupts.h"=0D
=0D
@@ -199,6 +200,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91=
30", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
Method (_STA) // _STA: D=
evice status=0D
{=0D
Return (0xF)=0D
@@ -225,6 +227,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
})=0D
}=0D
=0D
+ Device (COM2)=0D
+ {=0D
+ Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
+ Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A=
ddress=0D
+ Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CN913X_DBG2_UART_REG_BASE, // Address=
Base=0D
+ 0x00000100, // Address=
Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_UART0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSe=
rialClockRate) },=0D
+ Package () { "reg-io-width", 1 },=0D
+ Package () { "reg-shift", 2 },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
Device (SMI0)=0D
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Ma=
rvell/OcteonTx/AcpiTables/T91/Spcr.aslc
index 2a3415f0a6..2dda2def81 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
@@ -15,8 +15,6 @@
=0D
#include "AcpiHeader.h"=0D
=0D
-#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACP=
I_5_0_BYTE, Address }=0D
-=0D
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D {=0D
__ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU=
RE,=0D
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,=0D
--=20
2.29.0


[edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables

Marcin Wojtas
 

BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT.
Fix that for all platforms with the Marvell SoC's.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++=
+++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++=
++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 ++++++=
+++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 ++++++=
+++++++++
5 files changed, 272 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/=
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
index 345c1e4dd6..88e38efeeb 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA7K", 3)
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x000) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU1)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x001) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU2)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x100) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU3)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x101) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
=0D
Device (AHC0)=0D
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD=
A7K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD=
A7K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA7K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A=
ddress=0D
Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
{=0D
@@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D
@@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x00) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D
@@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA7K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment=0D
Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_PRT, Package () // _PRT: PCI Routing Table=0D
{=0D
Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/=
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
index 91401c74c8..77d3aebaf1 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA8K", 3)
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x000) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU1)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x001) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU2)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x100) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU3)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x101) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
=0D
Device (AHC0)=0D
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD=
A8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD=
A8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x02) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A=
ddress=0D
Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
{=0D
@@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D
@@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D
@@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x00) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D
@@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x01) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D
@@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment=0D
Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_PRT, Package () // _PRT: PCI Routing Table=0D
{=0D
Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl=
b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
index d26945d933..1ecbd0309c 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA8K", 3)
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x000) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU1)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x001) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU2)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x100) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU3)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x101) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
=0D
Device (AHC0)=0D
@@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD=
A8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA=
DA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x02) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A=
ddress=0D
Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
{=0D
@@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "MRVL0101") // _HID: H=
ardware ID=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D
@@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D
@@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x00) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D
@@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x01) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D
@@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM=
ADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment=0D
Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_PRT, Package () // _PRT: PCI Routing Table=0D
{=0D
Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S=
ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
index 8377b13763..d6619e367b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU =
", "CN9131", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU =
", "CN9131", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x02) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU =
", "CN9131", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S=
ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index d76a2a902b..536df8ab4b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91=
30", 3)
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x000) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU1)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x001) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU2)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x100) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
Device (CPU3)=0D
{=0D
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
Name (_UID, 0x101) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
}=0D
=0D
Device (AHC0)=0D
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913=
0", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CLS, Package (0x03) // _CLS: Class Code=0D
{=0D
0x01,=0D
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913=
0", 3)
Name (_HID, "MRVL0003") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91=
30", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x00) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
Name (_UID, 0x01) // _UID: Unique ID=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
=0D
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
{=0D
@@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
{=0D
Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A=
ddress=0D
Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
{=0D
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
{=0D
Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite,=0D
@@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D
@@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
{=0D
Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
Name (_UID, 0x00) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_CRS, ResourceTemplate ()=0D
{=0D
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D
@@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9=
130", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment=0D
Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
Name (_PRT, Package () // _PRT: PCI Routing Table=0D
{=0D
Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
--=20
2.29.0


[edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution

Marcin Wojtas
 

From: Grzegorz Bernacki <gjb@semihalf.com>

The latest changes in MdeModulePkg/Universal/BdsDxe require
VariablePolicyHelperLib resolution. Fix that for all platforms
based on the Marvell SoCs.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index 939fbf14d9..c919d4bfab 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -175,6 +175,7 @@
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl=
eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf=0D
DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa=
ult/DxeDtPlatformDtbLoaderLibDefault.inf=0D
+ VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var=
iablePolicyHelperLib.inf=0D
=0D
[LibraryClasses.common.UEFI_APPLICATION]=0D
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.=
inf=0D
@@ -197,6 +198,7 @@
!endif=0D
DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS=
erialPort.inf=0D
VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL=
ibRuntimeDxe.inf=0D
+ VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var=
iablePolicyHelperLib.inf=0D
=0D
[LibraryClasses.ARM, LibraryClasses.AARCH64]=0D
#=0D
@@ -563,7 +565,6 @@
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeas=
urementLibNull.inf=0D
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf=0D
- VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib=
/VariablePolicyHelperLib.inf=0D
}=0D
=0D
# UEFI application (Shell Embedded Boot Loader)=0D
--=20
2.29.0


[edk2-platforms PATCH 0/7] Marvell ACS improvements

Marcin Wojtas
 

Hi,

This new series comes with the remaining improvements that allow
the ACS3.0 test suite to pass the SBSA/FWTS/SCT to the
maximum non-HW related extent. Missing _STA methods
and DBG2 description are added to the ACPI tables.
Moreover all platforms start using the maintained
MonotonicCounterRuntimeDxe. Also a build fix is added
for the VariablePolicyHelperLib resolution, that is
required after the recent changes in edk2.
Last but not least the SMBIOS Type0 description
is updated with the actual EDK2 firmare vendor and version
strings.

More details can be found in the commit logs.
The patchest is publicly available in the github:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/marvell-acs-r20210719

Best regards,
Marcin


Grzegorz Bernacki (2):
Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution
Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe

Marcin Wojtas (5):
Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables
Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table
SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table
Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information
Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision

Silicon/Marvell/Marvell.dec | 2 +
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 8 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 +
Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 +
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 ++
Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 ++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +-
Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 105 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 -
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 89 +++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 -
24 files changed, 530 insertions(+), 13 deletions(-)
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h
create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc

--
2.29.0


Re: [PATCH v4 0/3] Enable Cloud Hypervisor support in edk2

Sami Mujawar
 

Hi Ard,

On 16/07/2021, 18:28, "Ard Biesheuvel" <ardb@kernel.org> wrote:

On Fri, 16 Jul 2021 at 19:25, Ard Biesheuvel <ardb@kernel.org> wrote:
>
> On Mon, 5 Jul 2021 at 12:06, Jianyong Wu <jianyong.wu@arm.com> wrote:
> >
> > Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that
> > runs on top of KVM. Cloud Hypervisor is implemented in Rust and is based
> > on the rust-vmm crates. See [1] to find more.
> >
> > To support UEFI, Cloud Hypervisor is introduced here.
> > There are 2 parts to be considered to do this enablement, that is:
> > 1. specific ACPI service implementation compared with qemu, there is no
> > device like Fw-cfg, so we have no elegant way to get the RSDP address.
> > A specific ACPI implementation is introduced here.
> >
> > 2. build configuration file for Cloud Hypervisor
> >
> > Change log:
> >
> > v3 to v4:
> > (1) remove Tpm support in dsc file
> > (2) refine Acpi table install code base on Sami's comments in v3
> >
> > v2 to v3:
> > (1) reuse qemu's memory initialization lib as they are in nearly the same
> > memory laout.
> > (2) split Acpi implemetation into PlatformHasAcpi and
> > InstallAcpiTable.
> > (3) remove lots of dependencies from qemu like "*Fwcfg*" lib.
> > (4) lots of code cleanup work to let it more approach to edk2 code
> > style.
> >
> > [1] https://github.com/cloud-hypervisor/cloud-hypervisor
> >
> > Jianyong Wu (3):
> > Acpi: reimplement PlatformHasAcpi for Cloud Hypervisor
> > Acpi: Install Acpi tables for Cloud hypervisor
> > ArmVirtCloudHv: support Cloud Hypervisor in edk2
> >
>
> Sami, any thoughts on this code?
>


... or did you already merge the entire series? (My mailbox is
overflowing a bit after 4 weeks of vacation :-))
[SAMI] I have merged this series.

Regards,

Sami Mujawar


>
> > ArmVirtPkg/ArmVirtPkg.dec | 6 +
> > ArmVirtPkg/ArmVirtCloudHv.dsc | 364 ++++++++++++++++++
> > ArmVirtPkg/ArmVirtCloudHv.fdf | 258 +++++++++++++
> > .../CloudHvAcpiPlatformDxe.inf | 47 +++
> > .../CloudHvHasAcpiDtDxe.inf | 43 +++
> > .../CloudHvAcpiPlatformDxe/CloudHvAcpi.c | 155 ++++++++
> > .../CloudHvHasAcpiDtDxe.c | 69 ++++
> > 7 files changed, 942 insertions(+)
> > create mode 100644 ArmVirtPkg/ArmVirtCloudHv.dsc
> > create mode 100644 ArmVirtPkg/ArmVirtCloudHv.fdf
> > create mode 100644 ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf
> > create mode 100644 ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf
> > create mode 100644 ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpi.c
> > create mode 100644 ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.c
> >
> > --
> > 2.17.1
> >

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Re: [PATCH v5 1/4] OvmfPkg/BaseMemEncryptLib: Support to issue unencrypted hypercall

Dov Murik
 

On 16/07/2021 15:29, Ashish Kalra wrote:
Hello Dov,

On Thu, Jul 15, 2021 at 11:58:17PM +0300, Dov Murik wrote:
Hi Ashish,

On 08/07/2021 17:07, Ashish Kalra wrote:
From: Ashish Kalra <ashish.kalra@amd.com>

By default all the SEV guest memory regions are considered encrypted,
if a guest changes the encryption attribute of the page (e.g mark a
page as decrypted) then notify hypervisor. Hypervisor will need to
track the unencrypted pages. The information will be used during
guest live migration, guest page migration and guest debugging.

This hypercall is used to notify hypervisor when the page's
encryption state changes.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Ashish Kalra <ashish.kalra@amd.com>
---
OvmfPkg/Include/Library/MemEncryptSevLib.h | 69 ++++++++++++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf | 1 +
OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c | 39 +++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c | 27 ++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/PeiDxeMemEncryptSevLibInternal.c | 51 +++++++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf | 1 +
OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c | 39 +++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c | 38 +++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/X64/AsmHelperStub.nasm | 33 ++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c | 54 +++++++++++++++
OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiDxeVirtualMemory.c | 22 ++++++-
11 files changed, 373 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/Library/MemEncryptSevLib.h
index 76d06c206c..c2b2a99a08 100644
--- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
+++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
@@ -90,6 +90,18 @@ MemEncryptSevIsEnabled (
VOID
);

+/**
+ Returns a boolean to indicate whether SEV live migration is enabled.
+
+ @retval TRUE SEV live migration is enabled
+ @retval FALSE SEV live migration is not enabled
+**/
+BOOLEAN
+EFIAPI
+MemEncryptSevLiveMigrationIsEnabled (
+ VOID
+ );
+
/**
This function clears memory encryption bit for the memory region specified by
BaseAddress and NumPages from the current page table context.
@@ -222,4 +234,61 @@ MemEncryptSevClearMmioPageEncMask (
IN UINTN NumPages
);

+/**
+ This hypercall is used to notify hypervisor when the page's encryption
+ state changes.
+
+ @param[in] PhysicalAddress The physical address that is the start address
+ of a memory region. The PhysicalAddress is
+ expected to be PAGE_SIZE aligned.
+ @param[in] Pages Number of pages in memory region.
+ @param[in] Status Encrypted(1) or Decrypted(0).
+
+@retval RETURN_SUCCESS Hypercall returned success.
+**/
+RETURN_STATUS
+EFIAPI
+SetMemoryEncDecHypercall3 (
+ IN UINTN PhysicalAddress,
+ IN UINTN Pages,
+ IN UINTN Status
+ );
+
+#define KVM_HC_MAP_GPA_RANGE 12
+#define KVM_MAP_GPA_RANGE_PAGE_SZ_4K 0
+#define KVM_MAP_GPA_RANGE_PAGE_SZ_2M BIT0
+#define KVM_MAP_GPA_RANGE_PAGE_SZ_1G BIT1
+#define KVM_MAP_GPA_RANGE_ENC_STAT(n) ((n) << 4)
+#define KVM_MAP_GPA_RANGE_ENCRYPTED KVM_MAP_GPA_RANGE_ENC_STAT(1)
+#define KVM_MAP_GPA_RANGE_DECRYPTED KVM_MAP_GPA_RANGE_ENC_STAT(0)
+
+#define KVM_FEATURE_MIGRATION_CONTROL BIT17
+
+/**
+ Figures out if we are running inside KVM HVM and
+ KVM HVM supports SEV Live Migration feature.
+
+ @retval TRUE SEV live migration is supported.
+ @retval FALSE SEV live migration is not supported.
+**/
+BOOLEAN
+EFIAPI
+KvmDetectSevLiveMigrationFeature(
+ VOID
+ );
+
+/**
+ Interface exposed by the ASM implementation of the core hypercall
+
+ @retval Hypercall returned status.
+**/
+UINTN
+EFIAPI
+SetMemoryEncDecHypercall3AsmStub (
+ IN UINTN HypercallNum,
+ IN UINTN PhysicalAddress,
+ IN UINTN Pages,
+ IN UINTN Attributes
+ );
+
#endif // _MEM_ENCRYPT_SEV_LIB_H_
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf b/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf
index f2e162d680..0c28afadee 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf
@@ -38,6 +38,7 @@
X64/PeiDxeVirtualMemory.c
X64/VirtualMemory.c
X64/VirtualMemory.h
+ X64/AsmHelperStub.nasm

[Sources.IA32]
Ia32/MemEncryptSevLib.c
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c b/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c
index 2816f859a0..ead754cd7b 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLibInternal.c
@@ -20,6 +20,8 @@
STATIC BOOLEAN mSevStatus = FALSE;
STATIC BOOLEAN mSevEsStatus = FALSE;
STATIC BOOLEAN mSevStatusChecked = FALSE;
+STATIC BOOLEAN mSevLiveMigrationStatus = FALSE;
+STATIC BOOLEAN mSevLiveMigrationStatusChecked = FALSE;

STATIC UINT64 mSevEncryptionMask = 0;
STATIC BOOLEAN mSevEncryptionMaskSaved = FALSE;
@@ -87,6 +89,24 @@ InternalMemEncryptSevStatus (
mSevStatusChecked = TRUE;
}

+/**
+ Figures out if we are running inside KVM HVM and
+ KVM HVM supports SEV Live Migration feature.
+**/
+STATIC
+VOID
+EFIAPI
+InternalDetectSevLiveMigrationFeature(
+ VOID
+ )
+{
+ if (KvmDetectSevLiveMigrationFeature()) {
+ mSevLiveMigrationStatus = TRUE;
+ }
+
+ mSevLiveMigrationStatusChecked = TRUE;
+}
+
/**
Returns a boolean to indicate whether SEV-ES is enabled.

@@ -125,6 +145,25 @@ MemEncryptSevIsEnabled (
return mSevStatus;
}

+/**
+ Returns a boolean to indicate whether SEV live migration is enabled.
+
+ @retval TRUE SEV live migration is enabled
+ @retval FALSE SEV live migration is not enabled
+**/
+BOOLEAN
+EFIAPI
+MemEncryptSevLiveMigrationIsEnabled (
+ VOID
+ )
+{
+ if (!mSevLiveMigrationStatusChecked) {
+ InternalDetectSevLiveMigrationFeature ();
+ }
+
+ return mSevLiveMigrationStatus;
+}
+
/**
Returns the SEV encryption mask.

diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
index be260e0d10..62392309fe 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
@@ -136,3 +136,30 @@ MemEncryptSevClearMmioPageEncMask (
//
return RETURN_UNSUPPORTED;
}
+
+/**
+ This hyercall is used to notify hypervisor when the page's encryption
+ state changes.
+
+ @param[in] PhysicalAddress The physical address that is the start address
+ of a memory region. The physical address is
+ expected to be PAGE_SIZE aligned.
+ @param[in] Pages Number of Pages in the memory region.
+ @param[in] Status Encrypted(1) or Decrypted(0).
+
+@retval RETURN_SUCCESS Hypercall returned success.
+**/
+RETURN_STATUS
+EFIAPI
+SetMemoryEncDecHypercall3 (
+ IN UINTN PhysicalAddress,
+ IN UINTN Pages,
+ IN UINTN Status
+ )
+{
+ //
+ // Memory encryption bit is not accessible in 32-bit mode
+ //
+ return RETURN_UNSUPPORTED;
+}
+
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiDxeMemEncryptSevLibInternal.c b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiDxeMemEncryptSevLibInternal.c
index b4a9f464e2..0c9f7e17ba 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiDxeMemEncryptSevLibInternal.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiDxeMemEncryptSevLibInternal.c
@@ -61,3 +61,54 @@ MemEncryptSevLocateInitialSmramSaveStateMapPages (

return RETURN_SUCCESS;
}
+
+/**
+ Figures out if we are running inside KVM HVM and
+ KVM HVM supports SEV Live Migration feature.
+
+ @retval TRUE SEV live migration is supported.
+ @retval FALSE SEV live migration is not supported.
+**/
+BOOLEAN
+EFIAPI
+KvmDetectSevLiveMigrationFeature(
+ VOID
+ )
+{
+ CHAR8 Signature[13];
+ UINT32 mKvmLeaf;
+ UINT32 RegEax, RegEbx, RegEcx, RegEdx;
+
+ Signature[12] = '\0';
+ for (mKvmLeaf = 0x40000000; mKvmLeaf < 0x40010000; mKvmLeaf += 0x100) {
+ AsmCpuid (mKvmLeaf,
Put the first argument on its own line.


+ NULL,
+ (UINT32 *) &Signature[0],
+ (UINT32 *) &Signature[4],
+ (UINT32 *) &Signature[8]);
+
+ if (AsciiStrCmp ((CHAR8 *) Signature, "KVMKVMKVM\0\0\0") == 0) {
I assume this will also match if Signature is "KVMKVMKVM\0YZ". I don't
know if that matters.
I don't understand what do you mean by "KVMKVMKVM\0YZ", this is
comparing for "KVMKVMKVM\0\0\0" ?
AsciiStrCmp will stop at the first '\0' char. So adding those three
'\0' at the end is pointless (the compiler will add one '\0' at the end
of a literal string).


Instead, you can use:

if (CompareMem (Signature, "KVMKVMKVM\0\0\0", 12) == 0)

and then you are sure to compare all 12 signature bytes.


I'm not sure this matters at all, maybe a simple:

if (AsciiStrCmp (Signature, "KVMKVMKVM") == 0)

is good enough. I see similar code to detect Xen in
OvmfPkg/XenPlatformPei/Xen.c .




+ DEBUG ((
+ DEBUG_INFO,
+ "%a: KVM Detected, signature = %s\n",
s/%s/%a/

(edk2 format strings are confusing.)

+ __FUNCTION__,
+ Signature
+ ));
+
+ RegEax = mKvmLeaf + 1;
+ RegEcx = 0;
+ AsmCpuid (mKvmLeaf + 1, &RegEax, &RegEbx, &RegEcx, &RegEdx);
+ if ((RegEax & KVM_FEATURE_MIGRATION_CONTROL) != 0) {
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: Live Migration feature supported\n",
I'd write: "%a: SEV Live Migration feature supported\n"
Ok.

+ __FUNCTION__
+ ));
+
+ return TRUE;
+ }
+ }
+ }
+
+ return FALSE;
+}
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
index 03a78c32df..3233ca7979 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLib.inf
@@ -38,6 +38,7 @@
X64/PeiDxeVirtualMemory.c
X64/VirtualMemory.c
X64/VirtualMemory.h
+ X64/AsmHelperStub.nasm

[Sources.IA32]
Ia32/MemEncryptSevLib.c
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c
index e2fd109d12..9db6c2ef71 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLibInternal.c
@@ -20,6 +20,8 @@
STATIC BOOLEAN mSevStatus = FALSE;
STATIC BOOLEAN mSevEsStatus = FALSE;
STATIC BOOLEAN mSevStatusChecked = FALSE;
+STATIC BOOLEAN mSevLiveMigrationStatus = FALSE;
+STATIC BOOLEAN mSevLiveMigrationStatusChecked = FALSE;

STATIC UINT64 mSevEncryptionMask = 0;
STATIC BOOLEAN mSevEncryptionMaskSaved = FALSE;
@@ -87,6 +89,24 @@ InternalMemEncryptSevStatus (
mSevStatusChecked = TRUE;
}

+/**
+ Figures out if we are running inside KVM HVM and
+ KVM HVM supports SEV Live Migration feature.
+**/
+STATIC
+VOID
+EFIAPI
+InternalDetectSevLiveMigrationFeature(
+ VOID
+ )
+{
+ if (KvmDetectSevLiveMigrationFeature()) {
+ mSevLiveMigrationStatus = TRUE;
+ }
+
+ mSevLiveMigrationStatusChecked = TRUE;
+}
+
/**
Returns a boolean to indicate whether SEV-ES is enabled.

@@ -125,6 +145,25 @@ MemEncryptSevIsEnabled (
return mSevStatus;
}

+/**
+ Returns a boolean to indicate whether SEV live migration is enabled.
+
+ @retval TRUE SEV live migration is enabled
+ @retval FALSE SEV live migration is not enabled
+**/
+BOOLEAN
+EFIAPI
+MemEncryptSevLiveMigrationIsEnabled (
+ VOID
+ )
+{
+ if (!mSevLiveMigrationStatusChecked) {
+ InternalDetectSevLiveMigrationFeature ();
+ }
+
+ return mSevLiveMigrationStatus;
+}
+
/**
Returns the SEV encryption mask.

diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
index 56d8f3f318..b926c7b786 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/SecMemEncryptSevLibInternal.c
@@ -100,6 +100,44 @@ MemEncryptSevIsEnabled (
return Msr.Bits.SevBit ? TRUE : FALSE;
}

+/**
+ Interface exposed by the ASM implementation of the core hypercall
+
+ @retval Hypercall returned status.
+**/
+UINTN
+EFIAPI
+SetMemoryEncDecHypercall3AsmStub (
+ IN UINTN HypercallNum,
+ IN UINTN PhysicalAddress,
+ IN UINTN Pages,
+ IN UINTN Attributes
+ )
+{
+ //
+ // Not used in SEC phase.
+ //
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Returns a boolean to indicate whether SEV live migration is enabled.
+
+ @retval TRUE SEV live migration is enabled
+ @retval FALSE SEV live migration is not enabled
+**/
+BOOLEAN
+EFIAPI
+MemEncryptSevLiveMigrationIsEnabled (
+ VOID
+ )
+{
+ //
+ // Not used in SEC phase.
+ //
+ return FALSE;
+}
+
/**
Returns the SEV encryption mask.

diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/AsmHelperStub.nasm b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/AsmHelperStub.nasm
new file mode 100644
index 0000000000..c7c11f77f1
--- /dev/null
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/AsmHelperStub.nasm
@@ -0,0 +1,33 @@
+/** @file
+
+ ASM helper stub to invoke hypercall
+
+ Copyright (c) 2021, AMD Incorporated. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DEFAULT REL
+SECTION .text
+
+; UINTN
+; EFIAPI
+; SetMemoryEncDecHypercall3AsmStub (
+; IN UINTN HypercallNum,
+; IN UINTN Arg1,
+; IN UINTN Arg2,
+; IN UINTN Arg3
+; );
+global ASM_PFX(SetMemoryEncDecHypercall3AsmStub)
+ASM_PFX(SetMemoryEncDecHypercall3AsmStub):
+ ; UEFI calling conventions require RBX to
+ ; be nonvolatile/callee-saved.
+ push rbx
+ mov rax, rcx ; Copy HypercallNumber to rax
+ mov rbx, rdx ; Copy Arg1 to the register expected by KVM
+ mov rcx, r8 ; Copy Arg2 to register expected by KVM
+ mov rdx, r9 ; Copy Arg2 to register expected by KVM
Comment: s/Arg2/Arg3/
Yes.
+ vmmcall ; Call VMMCALL
+ pop rbx
+ ret
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c
index a57e8fd37f..57447e69dc 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/MemEncryptSevLib.c
@@ -143,3 +143,57 @@ MemEncryptSevClearMmioPageEncMask (
);

}
+
+/**
+ This hyercall is used to notify hypervisor when the page's encryption
+ state changes.
+
+ @param[in] PhysicalAddress The physical address that is the start address
+ of a memory region. The physical address is
+ expected to be PAGE_SIZE aligned.
+ @param[in] Pages Number of Pages in the memory region.
+ @param[in] Status Encrypted(1) or Decrypted(0).
+
+@retval RETURN_SUCCESS Hypercall returned success.
or RETURN_UNSUPPORTED or RETURN_NO_MAPPING.
Ok.

+**/
+RETURN_STATUS
+EFIAPI
+SetMemoryEncDecHypercall3 (
+ IN UINTN PhysicalAddress,
+ IN UINTN Pages,
+ IN UINTN Status
Consider:

IN BOOL IsEncrypted

or:

IN MAP_RANGE_MODE EncMode

(it's not a Status in the EFI_STATUS sense that appears all around edk2).
Ok, i think i will prefer something like a MAP_RANGE_MODE.

+ )
+{
+ RETURN_STATUS Ret;
+ INTN Error;
+
Add assert for the expected alignment of PhysicalAddress, and then
you don't need to round it down when calling SetMemoryEncDecHypercall3AsmStub.
Cannot really use an assert here, as when the GCD map is being walked
and the c-bit being cleared from MMIO and NonExistent memory spaces, the
physical address range being passed may not be page-aligned, so adding
an assert here prevents booting. Hence, rounding it down when calling
SetMemoryEncDecHypercall3AsmStub below.
OK. So fix the comment above the function (which says: "The physical
address is expected to be PAGE_SIZE aligned.")



+ Ret = RETURN_UNSUPPORTED;
+
+ if (MemEncryptSevLiveMigrationIsEnabled ()) {
+ Ret = EFI_SUCCESS;
+ //
+ // The encryption bit is set/clear on the smallest page size, hence
+ // use the 4k page size in MAP_GPA_RANGE hypercall below.
+ // Also, the hypercall expects the guest physical address to be
+ // page-aligned.
+ //
+ Error = SetMemoryEncDecHypercall3AsmStub (
+ KVM_HC_MAP_GPA_RANGE,
+ (PhysicalAddress & (~(EFI_PAGE_SIZE-1))),
Simpler:

PhysicalAddress & ~EFI_PAGE_MASK

Ok.

+ Pages,
+ KVM_MAP_GPA_RANGE_PAGE_SZ_4K | KVM_MAP_GPA_RANGE_ENC_STAT(Status)
+ );
+
+ if (Error != 0) {
+ DEBUG ((DEBUG_ERROR,
+ "SetMemoryEncDecHypercall3 failed, Phys = %Lx, Pages = %Ld, Err = %Ld\n",
+ PhysicalAddress,
+ Pages,
+ (INT64)Error));
+
+ Ret = RETURN_NO_MAPPING;
+ }
+ }
+
+ return Ret;
+}
diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiDxeVirtualMemory.c b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiDxeVirtualMemory.c
index c696745f9d..0b1588a4c1 100644
--- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiDxeVirtualMemory.c
+++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/PeiDxeVirtualMemory.c
@@ -536,7 +536,6 @@ EnableReadOnlyPageWriteProtect (
AsmWriteCr0 (AsmReadCr0() | BIT16);
}

-
/**
This function either sets or clears memory encryption bit for the memory
region specified by PhysicalAddress and Length from the current page table
@@ -585,6 +584,9 @@ SetMemoryEncDec (
UINT64 AddressEncMask;
BOOLEAN IsWpEnabled;
RETURN_STATUS Status;
+ UINTN Size;
+ BOOLEAN CBitChanged;
+ PHYSICAL_ADDRESS OrigPhysicalAddress;

//
// Set PageMapLevel4Entry to suppress incorrect compiler/analyzer warnings.
@@ -636,6 +638,10 @@ SetMemoryEncDec (

Status = EFI_SUCCESS;

+ Size = Length;
+ CBitChanged = FALSE;
+ OrigPhysicalAddress = PhysicalAddress;
+
while (Length != 0)
{
//
@@ -695,6 +701,7 @@ SetMemoryEncDec (
));
PhysicalAddress += BIT30;
Length -= BIT30;
+ CBitChanged = TRUE;
} else {
//
// We must split the page
@@ -749,6 +756,7 @@ SetMemoryEncDec (
SetOrClearCBit (&PageDirectory2MEntry->Uint64, Mode);
PhysicalAddress += BIT21;
Length -= BIT21;
+ CBitChanged = TRUE;
} else {
//
// We must split up this page into 4K pages
@@ -791,6 +799,7 @@ SetMemoryEncDec (
SetOrClearCBit (&PageTableEntry->Uint64, Mode);
PhysicalAddress += EFI_PAGE_SIZE;
Length -= EFI_PAGE_SIZE;
+ CBitChanged = TRUE;
}
}
}
@@ -808,6 +817,17 @@ SetMemoryEncDec (
//
CpuFlushTlb();

+ //
+ // Notify Hypervisor on C-bit status
+ //
+ if (CBitChanged) {
+ Status = SetMemoryEncDecHypercall3 (
+ OrigPhysicalAddress,
+ EFI_SIZE_TO_PAGES(Size),
+ !Mode
Here you pass !Mode (which is 0 or 1) as the third argument to
SetMemoryEncDecHypercall3 .

But on patch 3/4 you pass KVM_MAP_GPA_RANGE_DECRYPTED (which is 0<<4);
but that hints that you expect either 0<<4 or 1<<4 as this third argument.
If this is the case, then here it should be:

(Mode == SetCBit) ? KVM_MAP_GPA_RANGE_ENCRYPTED : KVM_MAP_GPA_RANGE_DECRYPTED

If it's the other way around, then patch 3/4 needs to pass a simple 0 as
the third argument.
Yes, i need to pass a 0 (decrypted) as the third argument in that patch.
Even clearer than a literal 0 -- pass a ClearCBit as the third argument
(assuming you're changing the argument type to MAP_RANGE_MODE).


-Dov


Thanks,
Ashish



+ );
+ }
+
Done:
//
// Restore page table write protection, if any.


[edk2-test][PATCH v1 1/1] uefi-sct/SctPkg: Update page alignment calculations

Sunny Wang
 

This is to fix the SCT BS.AllocatePages failures (not found) with the
case that the Start address is not aligned to 64k.
For example,
The following is available memory region for testing:
0000000082012000-00000000EB6D9FFF 00000000000696C8
With the current page alignment calculation, we will get:
Start address is 0x82020000
PageNum is 0x696B8
In BS.AllocatePages, it will make the end address align with 64k,
so PageNum will be changed from 0x696B8 to 0x696C0. Therefore, the
end address will become 0xEB6E0000 which is larger than 0xEB6D9FFF,
so we get not found error in the end.

Therefore, the calculation for getting the PageNum should be updated
to PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)) so that we won't get a
wrong PageNum to allocate a memory with a size larger than available
space's size.

With this solution, the example above will get 0x696A8 as calculated
PageNum. Then, in BS.AllocatePages, the PageNum will be changed from
0x696A8 to 0x696B0. Therefore, the end address will become 0xEB6D0000
that is smaller than 0xEB6D9FFF, so we get not found error in the end.

I also tested this solution on two ARM platforms (NXP1046A and RPi4).

Cc: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Cc: G Edhaya Chandran <edhaya.chandran@arm.com>
Cc: Barton Gao <gaojie@byosoft.com.cn>
Signed-off-by: Sunny Wang <sunny.wang@arm.com>
---
.../MemoryAllocationServicesBBTestFunction.c | 110 +++++++++++-------
1 file changed, 66 insertions(+), 44 deletions(-)

diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocat=
ionServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-=
sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB=
oxTest/MemoryAllocationServicesBBTestFunction.c
index bf8cd3b3..cdfac992 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServ=
ices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServ=
ices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
@@ -2,6 +2,7 @@
=20
Copyright 2006 - 2013 Unified EFI, Inc.<BR>
Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2021, ARM Limited. All rights reserved.
=20
This program and the accompanying materials
are licensed and made available under the terms and conditions of the =
BSD License
@@ -24,7 +25,7 @@ Abstract:
=20
--*/
=20
-#include "SctLib.h"
+#include "SctLib.h"
#include "MemoryAllocationServicesBBTestMain.h"
=20
#define ALLOCATEPAGES_MEMORYTYPE_NUM 16
@@ -700,14 +701,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start;
=20
@@ -830,14 +834,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start;
=20
@@ -953,14 +960,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start + (SctLShiftU64 (PageNum/3, EFI_PAGE_SHIFT) & 0=
xFFFFFFFFFFFF0000);
=20
@@ -1076,14 +1086,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start + (SctLShiftU64 (PageNum * 2 / 3, EFI_PAGE_SHI=
FT) & 0xFFFFFFFFFFFF0000);
=20
@@ -1206,14 +1219,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start;
=20
@@ -1329,14 +1345,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start;
=20
@@ -1468,14 +1487,17 @@ BBTestAllocatePagesInterfaceTest (
PageNum =3D (UINTN)Descriptor.NumberOfPages;
Start =3D Descriptor.PhysicalStart;
=20
- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <=3D 0x10) {
+ //
+ // Calculate New Start address and PageNum with 64k alignment to
+ // cover the case that some memory types' alignment is more than
+ // 4k. If the available memory is less than 192k, the memory
+ // allocation call will be skipped.
+ //
+ if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) {
break;
}
- Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
- PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000);
+ Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000;
+ PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000));
=20
Memory =3D Start;
=20
@@ -1923,4 +1945,4 @@ BBTestFreePoolInterfaceTest (
=20
FreeMemoryMap ();
return EFI_SUCCESS;
-}
+}
--=20
2.31.0.windows.1


Re: [PATCH v1 1/1] ArmPlatformPkg/Scripts: Create add-symbol-file commands from UEFI console

Ard Biesheuvel
 

On Fri, 9 Jul 2021 at 11:03, PierreGondois <pierre.gondois@arm.com> wrote:

More formally:

Tested-by: Pierre Gondois <Pierre.Gondois@arm.com>
Merged as #1821

Thanks,



Re: [PATCH] OvmfPkg/OvmfXen: add QemuKernelLoaderFsDxe

Ard Biesheuvel
 

On Fri, 9 Jul 2021 at 05:24, Gary Lin <glin@suse.com> wrote:

Without QemuKernelLoaderFsDxe, QemuLoadKernelImage() couldn't download
the kernel, initrd, and kernel command line from QEMU's fw_cfg.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien@xen.org>
Cc: Jim Fehlig <jfehlig@suse.com>
Signed-off-by: Gary Lin <glin@suse.com>
I don't understand Xen on x86 well enough to decide whether we should
care about QEMU in the first place. Xen folks, please have a look.


---
OvmfPkg/OvmfXen.dsc | 1 +
OvmfPkg/OvmfXen.fdf | 1 +
2 files changed, 2 insertions(+)

diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc
index 3c1ca6bfd493..1a9c06c164a8 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -587,6 +587,7 @@ [Components]
NULL|OvmfPkg/Csm/LegacyBootMaintUiLib/LegacyBootMaintUiLib.inf
!endif
}
+ OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf
OvmfPkg/XenIoPvhDxe/XenIoPvhDxe.inf
OvmfPkg/XenIoPciDxe/XenIoPciDxe.inf
OvmfPkg/XenBusDxe/XenBusDxe.inf
diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf
index aeb9336fd5b7..8b5823555937 100644
--- a/OvmfPkg/OvmfXen.fdf
+++ b/OvmfPkg/OvmfXen.fdf
@@ -324,6 +324,7 @@ [FV.DXEFV]
INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
+INF OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
--
2.31.1


Re: [RFC PATCH] OvmfPkg/OvmfXen: set PcdAcpiS3Enable at initialization

Ard Biesheuvel
 

On Thu, 8 Jul 2021 at 06:05, Gary Lin <glin@suse.com> wrote:

There are several functions in OvmfPkg/Library using
QemuFwCfgS3Enabled() to detect the S3 support status. However, in
MdeModulePkg, PcdAcpiS3Enable is used to check S3 support. Since
InitializeXenPlatform() didn't set PcdAcpiS3Enable as
InitializePlatform() did, this made the inconsistency between
drivers/functions.

For example, S3SaveStateDxe checked PcdAcpiS3Enable and skipped
S3BootScript because the default value is FALSE. On the other hand,
PlatformBootManagerBeforeConsole() from OvmfPkg/Library called
QemuFwCfgS3Enabled() and found it returned TRUE, so it invoked
SaveS3BootScript(). However, S3SaveStateDxe skipped S3BootScript, so
SaveS3BootScript() asserted due to EFI_NOT_FOUND.

Setting PcdAcpiS3Enable at InitializeXenPlatform() "fixes" the crash
reported by my colleague. The other possible direction is to replace
QemuFwCfgS3Enabled() with PcdAcpiS3Enable. I'm not sure which one is
the right fix.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien@xen.org>
Cc: Jim Fehlig <jfehlig@suse.com>
Signed-off-by: Gary Lin <glin@suse.com>
This needs an ack from the Xen folks.

---
OvmfPkg/XenPlatformPei/Platform.c | 10 ++++++++++
OvmfPkg/XenPlatformPei/XenPlatformPei.inf | 3 +++
2 files changed, 13 insertions(+)

diff --git a/OvmfPkg/XenPlatformPei/Platform.c b/OvmfPkg/XenPlatformPei/Platform.c
index a811e72ee301..f7edc979486e 100644
--- a/OvmfPkg/XenPlatformPei/Platform.c
+++ b/OvmfPkg/XenPlatformPei/Platform.c
@@ -26,6 +26,8 @@
#include <Library/PciLib.h>
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
+#include <Library/QemuFwCfgLib.h>
+#include <Library/QemuFwCfgS3Lib.h>
#include <Library/ResourcePublicationLib.h>
#include <Guid/MemoryTypeInformation.h>
#include <Ppi/MasterBootMode.h>
@@ -423,6 +425,8 @@ InitializeXenPlatform (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
+ EFI_STATUS Status;
+
DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));

DebugDumpCmos ();
@@ -433,6 +437,12 @@ InitializeXenPlatform (
CpuDeadLoop ();
}

+ if (QemuFwCfgS3Enabled ()) {
+ DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
+ ASSERT_EFI_ERROR (Status);
+ }
+
XenConnect ();

BootModeInitialization ();
diff --git a/OvmfPkg/XenPlatformPei/XenPlatformPei.inf b/OvmfPkg/XenPlatformPei/XenPlatformPei.inf
index 597cb6fcd7ff..1e22c0b2e2aa 100644
--- a/OvmfPkg/XenPlatformPei/XenPlatformPei.inf
+++ b/OvmfPkg/XenPlatformPei/XenPlatformPei.inf
@@ -57,6 +57,8 @@ [LibraryClasses]
ResourcePublicationLib
PeiServicesLib
PeimEntryPoint
+ QemuFwCfgLib
+ QemuFwCfgS3Lib
MtrrLib
MemEncryptSevLib
PcdLib
@@ -79,6 +81,7 @@ [Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode
--
2.31.1


Re: [PATCH v5 4/4] OvmfPkg/AmdSevDxe: Add support for SEV live migration.

Dov Murik
 

Ashish,


On 08/07/2021 17:09, Ashish Kalra wrote:
From: Ashish Kalra <ashish.kalra@amd.com>

Check for SEV live migration feature support, if detected
setup a new UEFI enviroment variable to indicate OVMF
support for SEV live migration.

The new runtime UEFI environment variable is set via the
notification function registered for the
EFI_END_OF_DXE_EVENT_GROUP_GUID event in AmdSevDxe driver.

Why is this indirect notification needed? Why not simply call
gRT->SetVariable in AmdSevDxeEntryPoint (instead of calling CreateEventEx)?

If this is needed, please add a clarification (in the commit message and
before the CreateEventEx call).


Signed-off-by: Ashish Kalra <ashish.kalra@amd.com>
---
OvmfPkg/AmdSevDxe/AmdSevDxe.c | 59 ++++++++++++++++++++
OvmfPkg/AmdSevDxe/AmdSevDxe.inf | 4 ++
OvmfPkg/Include/Guid/MemEncryptLib.h | 20 +++++++
OvmfPkg/OvmfPkg.dec | 1 +
4 files changed, 84 insertions(+)

diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
index c66c4e9b92..45adf3249c 100644
--- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c
+++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
@@ -15,10 +15,49 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemEncryptSevLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Guid/MemEncryptLib.h>
+#include <Guid/EventGroup.h>
#include <Library/PcdLib.h>

+STATIC
+VOID
+EFIAPI
+AmdSevDxeOnEndOfDxe (
+ IN EFI_EVENT Event,
+ IN VOID *EventToSignal
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN SevLiveMigrationEnabled;
+
+ SevLiveMigrationEnabled = MemEncryptSevLiveMigrationIsEnabled();
+
+ if (SevLiveMigrationEnabled) {
+ Status = gRT->SetVariable (
+ L"SevLiveMigrationEnabled",
+ &gMemEncryptGuid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (BOOLEAN),
Should be:

sizeof SevLiveMigrationEnabled,



+ &SevLiveMigrationEnabled
+ );
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: Setting SevLiveMigrationEnabled variable, status = %lx\n",
+ __FUNCTION__,
+ Status
+ ));
+ }
+
+ DEBUG ((DEBUG_VERBOSE, "%a\n", __FUNCTION__));
Remove debug print.


+}
+
EFI_STATUS
EFIAPI
AmdSevDxeEntryPoint (
@@ -30,6 +69,7 @@ AmdSevDxeEntryPoint (
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap;
UINTN NumEntries;
UINTN Index;
+ EFI_EVENT Event;

//
// Do nothing when SEV is not enabled
@@ -130,5 +170,24 @@ AmdSevDxeEntryPoint (
}
}

+ //
+ // Register EFI_END_OF_DXE_EVENT_GROUP_GUID event.
+ // The notification function sets the runtime variable indicating OVMF
+ // support for SEV live migration.
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ AmdSevDxeOnEndOfDxe,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &Event
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a: CreateEventEx(): %r\n",
+ __FUNCTION__, Status));
+ }
+
return EFI_SUCCESS;
}
diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf
index 0676fcc5b6..f4e40ff412 100644
--- a/OvmfPkg/AmdSevDxe/AmdSevDxe.inf
+++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.inf
@@ -45,3 +45,7 @@

[Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
+
+[Guids]
+ gMemEncryptGuid
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES ## Event
diff --git a/OvmfPkg/Include/Guid/MemEncryptLib.h b/OvmfPkg/Include/Guid/MemEncryptLib.h
new file mode 100644
index 0000000000..4c046ba439
--- /dev/null
+++ b/OvmfPkg/Include/Guid/MemEncryptLib.h

Should the filename, GUID #define name, and global var name include
"AMD" or "SEV" in them? (and similarly in the corresponding Linux patch)

Or: maybe the new "SevLiveMigrationEnabled" variable can be set in the
confidential computing GUID? (not sure what are the guidelines for
creating or reusing GUIDs).



@@ -0,0 +1,20 @@
+/** @file
+
+ AMD Memory Encryption GUID, define a new GUID for defining
+ new UEFI enviroment variables assocaiated with SEV Memory Encryption.
typos: environment, associated


+
+ Copyright (c) 2020, AMD Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MEMENCRYPT_LIB_H__
+#define __MEMENCRYPT_LIB_H__
+
+#define MEMENCRYPT_GUID \
+{0x0cf29b71, 0x9e51, 0x433a, {0xa3, 0xb7, 0x81, 0xf3, 0xab, 0x16, 0xb8, 0x75}}
+
+extern EFI_GUID gMemEncryptGuid;
+
+#endif
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 6ae733f6e3..e452dc8494 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -122,6 +122,7 @@
gQemuKernelLoaderFsMediaGuid = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}
gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}
gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}
+ gMemEncryptGuid = {0x0cf29b71, 0x9e51, 0x433a, {0xa3, 0xb7, 0x81, 0xf3, 0xab, 0x16, 0xb8, 0x75}}

[Ppis]
# PPI whose presence in the PPI database signals that the TPM base address

-Dov


Re: [edk2-platforms PATCH 0/4] ACPI MDIO support for Marvell SoCs

Ard Biesheuvel
 

On Fri, 16 Jul 2021 at 19:32, Ard Biesheuvel <ardb@kernel.org> wrote:

On Mon, 12 Jul 2021 at 13:17, Jon Nettleton <jon@solid-run.com> wrote:

On Mon, Jul 12, 2021 at 12:52 PM Marcin Wojtas <mw@semihalf.com> wrote:

Hi,

wt., 29 cze 2021 o 16:17 Marcin Wojtas <mw@semihalf.com> napisał(a):

Hi Leif,

pon., 14 cze 2021 o 23:55 Leif Lindholm <leif@nuviainc.com> napisał(a):

Hi Marcin,

On Sun, Jun 13, 2021 at 20:16:27 +0200, Marcin Wojtas wrote:
Hi,

The MDIO ACPI binding has been established and merged to the
Linux tree,
Congratulations! :)

Is FreeBSD expected to follow suit?
There's no driver yet, but once it's finally created I will make sure
it supports ACPI properly.


hence it is now possible to update the ACPI
description of the platforms that base on the Marvell SoCs.

For convenience, the code is exposed in the public github branch:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/acpi-mdio-r20210613
There is also MacchiatoBin firmware binary avaialable for testing:
https://drive.google.com/file/d/1eigP_aeM4wYQpEaLAlQzs3IN_w1-kQr0

I'm looking forward to the comments or remarks.
The patches themselves look straightforward enough.
I *would* prefer some tested-by, for these sources rather than the
binary, before merging though.
I have some our patches queued, that are blocked by this patchset. In
case no time is found for external testers - if this may help to get
it pushed through, please see below logs from the next-20210628 tag
and unchanged firmware. All network ports of MacchiatoBin and
CN913x-DB work properly, with full 1G/10G PHY support via X/MDIO
interfaces:

MacchiatoBin
# uname -a
Linux buildroot 5.13.0-rc7-next-20210628 #6 SMP PREEMPT Tue Jun 29
09:14:07 CEST 2021 aarch64 GNU/Linux
# dmesg | grep MRVL0101
[ 1.829659] mv88x3340 MRVL0101:00-mii:00: Firmware version 0.3.3.0
[ 1.839622] mv88x3340 MRVL0101:00-mii:08: Firmware version 0.3.3.0
[ 2.748351] mvpp2 MRVL0110:00 eth1: PHY [MRVL0101:00-mii:00] driver
[mv88x3340] (irq=POLL)
[ 2.767479] mvpp2 MRVL0110:01 eth2: PHY [MRVL0101:00-mii:08] driver
[mv88x3340] (irq=POLL)
# dmesg | grep MRVL0100
[ 2.919424] mvpp2 MRVL0110:01 eth3: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
# dmesg | grep mvpp2
[...]
[ 2.748351] mvpp2 MRVL0110:00 eth1: PHY [MRVL0101:00-mii:00] driver
[mv88x3340] (irq=POLL)
[ 2.756701] mvpp2 MRVL0110:00 eth1: configuring for phy/10gbase-r link mode
[ 2.767479] mvpp2 MRVL0110:01 eth2: PHY [MRVL0101:00-mii:08] driver
[mv88x3340] (irq=POLL)
[ 2.775834] mvpp2 MRVL0110:01 eth2: configuring for phy/10gbase-r link mode
[ 2.919424] mvpp2 MRVL0110:01 eth3: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.928285] mvpp2 MRVL0110:01 eth3: configuring for phy/sgmii link mode
[ 2.936351] mvpp2 MRVL0110:01 eth4: configuring for
inband/2500base-x link mode
[ 5.987259] mvpp2 MRVL0110:01 eth3: Link is Up - 1Gbps/Full - flow
control off
#

CN913x-DB
# uname -a
Linux buildroot 5.13.0-rc7-next-20210628 #6 SMP PREEMPT Tue Jun 29
09:14:07 CEST 2021 aarch64 GNU/Linux
# dmesg | grep MRVL0100
[ 2.621201] mvpp2 MRVL0110:00 eth2: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.741199] mvpp2 MRVL0110:00 eth3: PHY [MRVL0100:00-mii:01] driver
[Marvell 88E1510] (irq=POLL)
# dmesg | grep mvpp2
[...]
[ 2.544917] mvpp2 MRVL0110:00 eth1: configuring for
inband/10gbase-r link mode
[ 2.552480] mvpp2 MRVL0110:00 eth1: Link is Up - 10Gbps/Full - flow
control rx
[ 2.621201] mvpp2 MRVL0110:00 eth2: PHY [MRVL0100:00-mii:00] driver
[Marvell 88E1510] (irq=POLL)
[ 2.630060] mvpp2 MRVL0110:00 eth2: configuring for phy/rgmii-id link mode
[ 2.741199] mvpp2 MRVL0110:00 eth3: PHY [MRVL0100:00-mii:01] driver
[Marvell 88E1510] (irq=POLL)
[ 2.750056] mvpp2 MRVL0110:00 eth3: configuring for phy/rgmii-id link mode
[ 2.810169] mvpp2 MRVL0110:01 eth4: configuring for
inband/10gbase-r link mode
[ 2.817471] mvpp2 MRVL0110:01 eth4: Link is Up - 10Gbps/Full - flow
control rx
[ 5.693231] mvpp2 MRVL0110:00 eth2: Link is Up - 1Gbps/Full - flow
control off
[ 10.840942] mvpp2 MRVL0110:00 eth1: Link is Down
[ 10.864124] mvpp2 MRVL0110:01 eth4: Link is Down
#
Both platforms were have been additionally tested by Greg, do you have
any comments/objections to merging this patchset?

Thanks,
Marcin
You can add my Tested-by as well. Finally got time over the weekend
to verify on all my Marvell platforms this effects.
Thanks all. I will get to this shortly - apologies for the delay.
Pushed as bfabeef4c9a6..955187a12a8b

Thanks all.


Re: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

Ashraf Ali S
 

Hi., Ray

BIOS boot to OS verified in Simics Successfully with the following changes.
1. SecCoreNative.inf with new GUID.
2. Removed IA32 resetvector code from SecCoreNative.
3. Removed the ResetVector Code from PlatformSecLib
4. Consumed the ResetVector Code from UefiCpuPkg/ResetVector

The reason for this change:
Currently SecCore and ResetVector are using the Same GUID (BFV guid), which will block the usage of both SecCore and UefiCpuPkg/ResetVector at a same time.

Advantage of this patch:
1. Provided the Backward compatibility by keeping the original SecCore
2. User can use both SecCoreNative and ResetVector at a same time.
3. User can choose to avoid resetvector code maintenance at the platform level.


Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, July 19, 2021 8:13 AM
To: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io
Cc: Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; Solanki, Digant H <digant.h.solanki@intel.com>; V, Sangeetha <sangeetha.v@intel.com>
Subject: RE: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

Ashraf,
What unit tests have you performed with this native SecCore?

Thanks,
Ray

-----Original Message-----
From: S, Ashraf Ali <ashraf.ali.s@intel.com>
Sent: Wednesday, July 14, 2021 5:48 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; Solanki, Digant H <digant.h.solanki@intel.com>; V, Sangeetha <sangeetha.v@intel.com>
Subject: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492

Currently SecCore.inf having the resetvector code under IA32. if the user wants to use both SecCore and UefiCpuPkg ResetVector it's not possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf)
are sharing the same GUID which is BFV. to overcome this issue we can create the Duplicate version of the SecCore.inf as SecCoreNative.inf which contains pure SecCore Native functionality without resetvector.
SecCoreNative.inf should have the Unique GUID so that it can be used along with UefiCpuPkg ResetVector in there implementation.

Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Cc: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
---
UefiCpuPkg/SecCore/SecCoreNative.inf | 80 ++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf

diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecCoreNative.inf
new file mode 100644
index 0000000000..f89a0e5f38
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCoreNative.inf
@@ -0,0 +1,80 @@
+## @file
+# SecCoreNative module that implements the SEC phase.
+#
+# This is the first module taking control after the reset vector.
+# The entry point function is _ModuleEntryPoint in PlatformSecLib.
+# The entry point function will start with protected mode, since the #
+the transistion to flat mode it done by the resetvector, enable #
+temporary memory and call into SecStartup().
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SecCore
+ MODULE_UNI_FILE = SecCore.uni
+ FILE_GUID = 43CA74CA-7D29-49A0-B3B9-20F84015B27D
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[Sources]
+ SecMain.c
+ SecMain.h
+ FindPeiCore.c
+ SecBist.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ PlatformSecLib
+ PcdLib
+ DebugAgentLib
+ UefiCpuLib
+ PeCoffGetEntryPointLib
+ PeCoffExtraActionLib
+ CpuExceptionHandlerLib
+ ReportStatusCodeLib
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+
+[Ppis]
+ ## SOMETIMES_CONSUMES
+ ## PRODUCES
+ gEfiSecPlatformInformationPpiGuid
+ ## SOMETIMES_CONSUMES
+ ## SOMETIMES_PRODUCES
+ gEfiSecPlatformInformation2PpiGuid
+ gEfiTemporaryRamDonePpiGuid ## PRODUCES
+ ## NOTIFY
+ ## SOMETIMES_CONSUMES
+ gPeiSecPerformancePpiGuid
+ gEfiPeiCoreFvLocationPpiGuid
+ ## CONSUMES
+ gRepublishSecPpiPpiGuid
+
+[Guids]
+ ## SOMETIMES_PRODUCES ## HOB
+ gEfiFirmwarePerformanceGuid
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes
+## CONSUMES
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ SecCoreExtra.uni
--
2.30.2.windows.1

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