Date   

[PATCH EDK2 v1 0/1] MdeModulePkg: Modify PCD default value

wenyi,xie
 

From: "wenyi.xie" <xiewenyi2@huawei.com>

Main Changes :
Change default value of PcdSrIovSystemPageSize to 0x10.

wenyi.xie (1):
MdeModulePkg: Modify PCD default value

MdeModulePkg/MdeModulePkg.dec | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--
2.20.1.windows.1


Re: [PATCH] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0

Chaganty, Rangasai V
 

Few comments:
1. Please pack the structures correctly using #pragma pack(1)/ #pragma pack() pairs.
2. What is the purpose of IGD_OPREGION_HEADER_MBOX2_VER_3_0 macro definition and assigning it to a value of BIT5.
3. Is the 3.0 version backward compatible to the one that is currently available? I am wondering if there are reasons to carry obsolete members in 3.0 version.

Regards,
Sai

-----Original Message-----
From: Solanki, Digant H <digant.h.solanki@intel.com>
Sent: Thursday, July 08, 2021 7:24 AM
To: devel@edk2.groups.io
Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>
Subject: [PATCH] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426

- There are many OpRegion fields obsoleted in MBOX1
- MBOX2 is re-purposed for Backlight related fields for dual LFP.
- Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3.

Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
---
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)

diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
new file mode 100644
index 0000000000..422a60bdbd
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion
+++ 30.h
@@ -0,0 +1,100 @@
+/** @file
+ IGD OpRegion definition from Intel Integrated Graphics Device
+OpRegion
+ Specification based on version 3.0.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _IGD_OPREGION_3_0_H_
+#define _IGD_OPREGION_3_0_H_
+
+#include "IgdOpRegion.h"
+
+#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5
+
+///
+/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size
+0x100 /// typedef struct {
+ UINT32 DRDY; ///< Offset 0x100 Driver Readiness
+ UINT32 CSTS; ///< Offset 0x104 Status
+ UINT32 CEVT; ///< Offset 0x108 Current Event
+ UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero
+ UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
+ UINT32 CPDL[8]; ///< Offset 0x140 obsolete
+ UINT32 CADL[8]; ///< Offset 0x160 obsolete
+ UINT32 NADL[8]; ///< Offset 0x180 obsolete
+ UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out
+ UINT32 TIDX; ///< Offset 0x1A4 obsolete
+ UINT32 CHPD; ///< Offset 0x1A8 obsolete
+ UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator
+ UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator
+ UINT32 SXSW; ///< Offset 0x1B4 obsolete
+ UINT32 EVTS; ///< Offset 0x1B8 obsolete
+ UINT32 CNOT; ///< Offset 0x1BC obsolete
+ UINT32 NRDY; ///< Offset 0x1C0 Driver Status
+ UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
+ UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1_VER_3_0;
+
+///
+/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size
+0x100 /// typedef struct {
+ UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1
+ UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2
+ UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1
+ UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2
+ UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1
+ UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2
+} IGD_OPREGION_MBOX2_VER_3_0;
+
+///
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support ///
+Offset 0x300, Size 0x100 /// typedef struct {
+ UINT32 ARDY; ///< Offset 0x300 obsolete
+ UINT32 ASLC; ///< Offset 0x304 obsolete
+ UINT32 TCHE; ///< Offset 0x308 obsolete
+ UINT32 ALSI; ///< Offset 0x30C obsolete
+ UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2.
+ UINT32 PFIT; ///< Offset 0x314 obsolete
+ UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2.
+ UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2.
+ UINT32 CPFM; ///< Offset 0x344 obsolete
+ UINT32 EPFM; ///< Offset 0x348 obsolete
+ UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete
+ UINT32 PFMB; ///< Offset 0x396 obsolete
+ UINT32 CCDV; ///< Offset 0x39A obsolete
+ UINT32 PCFT; ///< Offset 0x39E obsolete
+ UINT32 SROT; ///< Offset 0x3A2 obsolete
+ UINT32 IUER; ///< Offset 0x3A6 obsolete
+ UINT64 FDSS; ///< Offset 0x3AA obsolete
+ UINT32 FDSP; ///< Offset 0x3B2 obsolete
+ UINT32 STAT; ///< Offset 0x3B6 obsolete
+ UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.
+ UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.
+ UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh
+ UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters
+ UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero.
+} IGD_OPREGION_MBOX3_VER_3_0;
+
+///
+/// IGD OpRegion Structure
+///
+typedef struct {
+ IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
+ IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI
+Methods (Offset 0x100, Size 0x100)
+ IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight
+communication (Offset 0x200, Size 0x100)
+ IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
+ IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
+ IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
+} IGD_OPREGION_STRUCTURE_VER_3_0;
+#pragma pack()
+
+#endif
--
2.30.2.windows.1


Re: [edk2-platforms: PATCH] Platform/Intel: Correct CPU APIC IDs.

Chaganty, Rangasai V
 

The DEBUG error levels are set incorrectly in several places. Examples (please check other places too):
- Line 213, 215, 275 etc. - Should be changed DEBUG_INFO.

Also, please remove the comment in line 251,

Regards,
Sai

-----Original Message-----
From: Chen, TinaX Y <tinax.y.chen@intel.com>
Sent: Monday, July 12, 2021 10:58 PM
To: devel@edk2.groups.io
Cc: Lin, JackX <jackx.lin@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Huang, Jenny <jenny.huang@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chen, TinaX Y <tinax.y.chen@intel.com>
Subject: [edk2-platforms: PATCH] Platform/Intel: Correct CPU APIC IDs.

From: JackX <JackX.Lin@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3365

BIOS cannot find correct AcpiProcId in mApicIdMap because of there is no suitable map, that causes ACPI_BIOS_ERROR.
Remove mApicIdMap for determing AcpiProcId, uses normal countings instead.

Signed-off-by: JackX Lin <JackX.Lin@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Tinax Chen <tinax.y.chen@intel.com>
Cc: JackX Lin <JackX.Lin@intel.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 230 ++++++++++++++++++++++++++++++++++++++++++++++++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1 file changed, 48 insertions(+), 182 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2..5a717295e0 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1,14 +1,13 @@
/** @file ACPI Platform Driver -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "AcpiPlatform.h" -#define MAX_CPU_NUM (FixedPcdGet32(PcdMaxCpuThreadCount) * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuSocketCount)) #pragma pack(1) @@ -16,7 +15,6 @@ typedef struct {
UINT32 AcpiProcessorId; UINT32 ApicId; UINT32 Flags;- UINT32 SwProcApicId; UINT32 SocketNum; } EFI_CPU_ID_ORDER_MAP; @@ -58,138 +56,17 @@ BOOLEAN mX2ApicEnabled;
EFI_MP_SERVICES_PROTOCOL *mMpService; BOOLEAN mCpuOrderSorted;-EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM];-UINTN mNumberOfCPUs = 0;+EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable = NULL;+UINTN mNumberOfCpus = 0; UINTN mNumberOfEnabledCPUs = 0; -// following are possible APICID Map for SKX-static const UINT32 ApicIdMapA[] = { //for SKUs have number of core > 16- //it is 14 + 14 + 14 + 14 format- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x00000010, 0x00000011,- 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017, 0x00000018, 0x00000019,- 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x00000020, 0x00000021, 0x00000022, 0x00000023,- 0x00000024, 0x00000025, 0x00000026, 0x00000027, 0x00000028, 0x00000029, 0x0000002A, 0x0000002B,- 0x0000002C, 0x0000002D, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035,- 0x00000036, 0x00000037, 0x00000038, 0x00000039, 0x0000003A, 0x0000003B, 0x0000003C, 0x0000003D-};--static const UINT32 ApicIdMapB[] = { //for SKUs have number of cores <= 16 use 32 ID space- //it is 16+16 format- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,- 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017,- 0x00000018, 0x00000019, 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x0000001E, 0x0000001F,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF-};---static const UINT32 ApicIdMapC[] = { //for SKUs have number of cores <= 16 use 64 ID space- //it is 16+0+16+0 format- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,- 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000026, 0x00000027,- 0x00000028, 0x00000029, 0x0000002A, 0x0000002B, 0x0000002C, 0x0000002D, 0x0000002E, 0x0000002F,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF-};--static const UINT32 ApicIdMapD[] = { //for SKUs have number of cores <= 8 use 16 ID space- //it is 16 format- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF-};--const UINT32 *mApicIdMap = NULL;- /**- This function detect the APICID map and update ApicID Map pointer-- @param None-- @retval VOID--**/-VOID DetectApicIdMap(VOID)-{- UINTN CoreCount;-- CoreCount = 0;-- if(mApicIdMap != NULL) {- return; //aleady initialized- }-- mApicIdMap = ApicIdMapA; // default to > 16C SKUs-- CoreCount = mNumberOfEnabledCPUs / 2;- DEBUG ((DEBUG_INFO, "CoreCount - %d\n", CoreCount));-- //DEBUG((EFI_D_ERROR, ":: Default to use Map A @ %08X FusedCoreCount: %02d, sktlevel: %d\n",mApicIdMap, FusedCoreCount, mNumOfBitShift));- // Dont assert for single core, single thread system.- //ASSERT (CoreCount != 0);-- if(CoreCount <= 16) {-- if(mNumOfBitShift == 4) {- mApicIdMap = ApicIdMapD;- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));- }-- if(mNumOfBitShift == 5) {- mApicIdMap = ApicIdMapB;- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));- }-- if(mNumOfBitShift == 6) {- mApicIdMap = ApicIdMapC;- //DEBUG((EFI_D_ERROR, ":: Use Map C @ %08X\n",mApicIdMap));- }-- }-- return;-}--/**- This function return the CoreThreadId of ApicId from ACPI ApicId Map array+ This function searches mCpuApicIdOrderTable to find the BSP ApicId, and returns a number where the BSP is. @param ApicId - @retval Index of ACPI ApicId Map array-+ @return Where the BSP is. **/-UINT32-GetIndexFromApicId (- UINT32 ApicId- )-{- UINT32 CoreThreadId;- UINT32 i;-- ASSERT (mApicIdMap != NULL);-- CoreThreadId = ApicId & ((1 << mNumOfBitShift) - 1);-- for(i = 0; i < (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)); i++) {- if(mApicIdMap[i] == CoreThreadId) {- break;- }- }-- ASSERT (i <= (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)));-- return i;-}- UINT32 ApicId2SwProcApicId ( UINT32 ApicId@@ -197,7 +74,7 @@ ApicId2SwProcApicId (
{ UINT32 Index; - for (Index = 0; Index < MAX_CPU_NUM; Index++) {+ for (Index = 0; Index < mNumberOfCpus; Index++) { if ((mCpuApicIdOrderTable[Index].Flags == 1) && (mCpuApicIdOrderTable[Index].ApicId == ApicId)) { return Index; }@@ -214,13 +91,12 @@ DebugDisplayReOrderTable(
{ UINT32 Index; - DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\n"));- for (Index=0; Index<MAX_CPU_NUM; Index++) {- DEBUG ((EFI_D_ERROR, " %02d 0x%02X 0x%02X %d 0x%02X %d\n",+ DEBUG ((DEBUG_ERROR, "Index AcpiProcId ApicId Flags Skt\n"));+ for (Index = 0; Index < mNumberOfCpus; Index++) {+ DEBUG ((DEBUG_ERROR, " %02d 0x%02X 0x%02X %d %d\n", Index, mCpuApicIdOrderTable[Index].AcpiProcessorId, mCpuApicIdOrderTable[Index].ApicId, mCpuApicIdOrderTable[Index].Flags,- mCpuApicIdOrderTable[Index].SwProcApicId, mCpuApicIdOrderTable[Index].SocketNum)); } }@@ -292,9 +168,8 @@ SortCpuLocalApicInTable (
if(!mCpuOrderSorted) { - Index = 0; - for (CurrProcessor = 0; CurrProcessor < mNumberOfCPUs; CurrProcessor++) {+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++, Index++) { Status = mMpService->GetProcessorInfo ( mMpService, CurrProcessor,@@ -302,20 +177,12 @@ SortCpuLocalApicInTable (
); if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {- if(ProcessorInfoBuffer.ProcessorId & 1) { //is 2nd thread- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[(Index - 1) + MAX_CPU_NUM / 2];- } else { //is primary thread CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Index];- Index++;- } CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0); CpuIdMapPtr->SocketNum = (UINT32)ProcessorInfoBuffer.Location.Package;- CpuIdMapPtr->AcpiProcessorId = (CpuIdMapPtr->SocketNum * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + GetIndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;- CpuIdMapPtr->SwProcApicId = ((UINT32)(ProcessorInfoBuffer.Location.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.ProcessorId) & CoreThreadMask));- if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it starts from base 0 and contiguous+ CpuIdMapPtr->AcpiProcessorId = Index; //may not necessory!!!!!- } //update processorbitMask if (CpuIdMapPtr->Flags == 1) {@@ -323,7 +190,6 @@ SortCpuLocalApicInTable (
if(mForceX2ApicId) { CpuIdMapPtr->SocketNum &= 0x7; CpuIdMapPtr->AcpiProcessorId &= 0xFF; //keep lower 8bit due to use Proc obj in dsdt- CpuIdMapPtr->SwProcApicId &= 0xFF; } } } else { //not enabled@@ -331,13 +197,12 @@ SortCpuLocalApicInTable (
CpuIdMapPtr->ApicId = (UINT32)-1; CpuIdMapPtr->Flags = 0; CpuIdMapPtr->AcpiProcessorId = (UINT32)-1;- CpuIdMapPtr->SwProcApicId = (UINT32)-1; CpuIdMapPtr->SocketNum = (UINT32)-1; } //end if PROC ENABLE } //end for CurrentProcessor //keep for debug purpose- DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));+ DEBUG (( DEBUG_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift)); DebugDisplayReOrderTable(); //make sure 1st entry is BSP@@ -346,14 +211,14 @@ SortCpuLocalApicInTable (
} else { BspApicId = (*(volatile UINT32 *)(UINTN)0xFEE00020) >> 24; }- DEBUG ((EFI_D_INFO, "BspApicId - 0x%x\n", BspApicId));+ DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", BspApicId)); if(mCpuApicIdOrderTable[0].ApicId != BspApicId) { //check to see if 1st entry is BSP, if not swap it Index = ApicId2SwProcApicId(BspApicId); - if(MAX_CPU_NUM <= Index) {- DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));+ if(mNumberOfCpus <= Index) {+ DEBUG ((DEBUG_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n")); return EFI_INVALID_PARAMETER; } @@ -362,9 +227,6 @@ SortCpuLocalApicInTable (
mCpuApicIdOrderTable[0].ApicId = TempVal; mCpuApicIdOrderTable[Index].Flags = mCpuApicIdOrderTable[0].Flags; mCpuApicIdOrderTable[0].Flags = 1;- TempVal = mCpuApicIdOrderTable[Index].SwProcApicId;- mCpuApicIdOrderTable[Index].SwProcApicId = mCpuApicIdOrderTable[0].SwProcApicId;- mCpuApicIdOrderTable[0].SwProcApicId = TempVal; //swap AcpiProcId TempVal = mCpuApicIdOrderTable[Index].AcpiProcessorId; mCpuApicIdOrderTable[Index].AcpiProcessorId = mCpuApicIdOrderTable[0].AcpiProcessorId;@@ -373,27 +235,24 @@ SortCpuLocalApicInTable (
} //Make sure no holes between enabled threads- for(CurrProcessor = 0; CurrProcessor < MAX_CPU_NUM; CurrProcessor++) {+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) { if(mCpuApicIdOrderTable[CurrProcessor].Flags == 0) { //make sure disabled entry has ProcId set to FFs mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32)-1; mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (UINT32)-1;- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = (UINT32)-1; - for(Index = CurrProcessor+1; Index < MAX_CPU_NUM; Index++) {+ for (Index = CurrProcessor+1; Index < mNumberOfCpus; Index++) { if(mCpuApicIdOrderTable[Index].Flags == 1) { //move enabled entry up mCpuApicIdOrderTable[CurrProcessor].Flags = 1; mCpuApicIdOrderTable[CurrProcessor].ApicId = mCpuApicIdOrderTable[Index].ApicId; mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = mCpuApicIdOrderTable[Index].AcpiProcessorId;- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = mCpuApicIdOrderTable[Index].SwProcApicId; mCpuApicIdOrderTable[CurrProcessor].SocketNum = mCpuApicIdOrderTable[Index].SocketNum; //disable moved entry mCpuApicIdOrderTable[Index].Flags = 0; mCpuApicIdOrderTable[Index].ApicId = (UINT32)-1; mCpuApicIdOrderTable[Index].AcpiProcessorId = (UINT32)-1;- mCpuApicIdOrderTable[Index].SwProcApicId = (UINT32)-1; break; } }@@ -401,7 +260,7 @@ SortCpuLocalApicInTable (
} //keep for debug purpose- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));+ DEBUG ((DEBUG_ERROR, "APIC ID Order Table ReOrdered\n")); DebugDisplayReOrderTable(); mCpuOrderSorted = TRUE;@@ -871,18 +730,22 @@ InstallMadtFromScratch (
NewMadtTable = NULL; MaxMadtStructCount = 0; - DetectApicIdMap();+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));+ if (mCpuApicIdOrderTable == NULL) {+ DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structure pointer array\n"));+ return EFI_OUT_OF_RESOURCES;+ } // Call for Local APIC ID Reorder Status = SortCpuLocalApicInTable (); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status)); goto Done; } MaxMadtStructCount = (UINT32) (- MAX_CPU_NUM + // processor local APIC structures- MAX_CPU_NUM + // processor local x2APIC structures+ mNumberOfCpus + // processor local APIC structures+ mNumberOfCpus + // processor local x2APIC structures 1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures 2 + // interrupt source override structures 1 + // local APIC NMI structures@@ -906,11 +769,11 @@ InstallMadtFromScratch (
// Status = InitializeMadtHeader (&MadtTableHeader); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "InitializeMadtHeader failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "InitializeMadtHeader failed: %r\n", Status)); goto Done; } - DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCPUs));+ DEBUG ((DEBUG_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus)); // // Build Processor Local APIC Structures and Processor Local X2APIC Structures@@ -923,7 +786,7 @@ InstallMadtFromScratch (
ProcLocalX2ApicStruct.Reserved[0] = 0; ProcLocalX2ApicStruct.Reserved[1] = 0; - for (Index = 0; Index < MAX_CPU_NUM; Index++) {+ for (Index = 0; Index < mNumberOfCpus; Index++) { // // If x2APIC mode is not enabled, and if it is possible to express the // APIC ID as a UINT8, use a processor local APIC structure. Otherwise,@@ -953,7 +816,7 @@ InstallMadtFromScratch (
); } if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status)); goto Done; } }@@ -978,7 +841,7 @@ InstallMadtFromScratch (
&MadtStructs[MadtStructsIndex++] ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status)); goto Done; } }@@ -1000,7 +863,7 @@ InstallMadtFromScratch (
&MadtStructs[MadtStructsIndex++] ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status)); goto Done; } }@@ -1026,7 +889,7 @@ InstallMadtFromScratch (
&MadtStructs[MadtStructsIndex++] ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status)); goto Done; } @@ -1045,7 +908,7 @@ InstallMadtFromScratch (
&MadtStructs[MadtStructsIndex++] ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status)); goto Done; } @@ -1065,7 +928,7 @@ InstallMadtFromScratch (
&MadtStructs[MadtStructsIndex++] ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status)); goto Done; } @@ -1105,7 +968,7 @@ InstallMadtFromScratch (
(UINT8 **)&NewMadtTable ); if (EFI_ERROR (Status)) {- DEBUG ((EFI_D_ERROR, "BuildAcpiTable failed: %r\n", Status));+ DEBUG ((DEBUG_ERROR, "BuildAcpiTable failed: %r\n", Status)); goto Done; } @@ -1136,6 +999,10 @@ Done:
FreePool (NewMadtTable); } + if (mCpuApicIdOrderTable != NULL) {+ FreePool (mCpuApicIdOrderTable);+ }+ return Status; } @@ -1324,9 +1191,9 @@ PlatformUpdateTables (
FadtHeader->XGpe1Blk.AccessSize = 0; } - DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table ));- DEBUG(( EFI_D_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch ));- DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));+ DEBUG ((DEBUG_ERROR, "ACPI FADT table @ address 0x%x\n", Table));+ DEBUG ((DEBUG_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch));+ DEBUG ((DEBUG_ERROR, " Flags 0x%x\n", FadtHeader->Flags)); break; case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:@@ -1346,8 +1213,8 @@ PlatformUpdateTables (
HpetBlockId.Bits.VendorId = HpetCapabilities.Bits.VendorId; HpetTable->EventTimerBlockId = HpetBlockId.Uint32; HpetTable->MainCounterMinimumClockTickInPeriodicMode = (UINT16)HpetCapabilities.Bits.CounterClockPeriod;- DEBUG(( EFI_D_ERROR, "ACPI HPET table @ address 0x%x\n", Table ));- DEBUG(( EFI_D_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress) ));+ DEBUG ((DEBUG_ERROR, "ACPI HPET table @ address 0x%x\n", Table));+ DEBUG ((DEBUG_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress))); break; case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:@@ -1526,7 +1393,6 @@ InstallAcpiPlatform (
EFI_STATUS Status; EFI_EVENT EndOfDxeEvent; - Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService); ASSERT_EFI_ERROR (Status); @@ -1551,11 +1417,11 @@ InstallAcpiPlatform (
// mMpService->GetNumberOfProcessors ( mMpService,- &mNumberOfCPUs,+ &mNumberOfCpus, &mNumberOfEnabledCPUs );- ASSERT (mNumberOfCPUs <= MAX_CPU_NUM && mNumberOfEnabledCPUs >= 1);- DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs));++ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus)); DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs)); DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));--
2.26.2.windows.1


A gdb pretty print for CHAR16 question. Need some gdb help.

Andrew Fish
 

I’ve been watching the Le Tour replays and playing around with gdb scripts. I was trying to figure out how to do stuff I know how to do in lldb. 

For lldb I have Pretty Printer and for CHAR16 things like this:

CHAR16 gChar    = L'X';
CHAR16 gStr[]   = L"1234567890\x23f3"; 
CHAR16 *gStrPtr = gStr;      

For lldb I get:
L’X’
L”1234567890
(CHAR16 *)L”1234567890

The default for gdb is:
(gdb) p /r gChar
$8 = 88
(gdb) p /r gStr
$9 = {49, 50, 51, 52, 53, 54, 55, 56, 57, 48, 9203, 0}
(gdb) p /r gStrPtr
$10 = (CHAR16 *) 0x100008030 <gStr>

I’ve figured out how to teach GDB to pretty print CHAR16, but I can’t figure out how to hook CHAR16 * or CHAR16 {}?

This is what I’ve got (vs what gdb does for char):
$1 = 88 'X'
$2 = L'X'

 

$3 = "1234567890"
$4 = {L'1', L'2', L'3', L'4', L'5', L'6', L'7', L'8', L'9', L'0', L'⏳', L'\x00'}

 

$5 = 0x100008058 <Str> "1234567890"
$6 = (CHAR16 *) 0x100008030 <gStr>

This is the script...
$ cat CHAR16.py
import gdb

from gdb.printing import register_pretty_printer
from gdb.printing import RegexpCollectionPrettyPrinter


class CHAR16_PrettyPrinter(object):

    def __init__(self, val):
        self.val = val

    def to_string(self):
        if int(self.val) < 0x20:
            return f"L'\\x{int(self.val):02x}'"
        else:
            return f"L'{chr(self.val):s}'"


def build_pretty_printer():
    pp = RegexpCollectionPrettyPrinter("EFI")
    pp.add_printer('CHAR16', '^CHAR16$', CHAR16_PrettyPrinter)
    return pp


register_pretty_printer(None, build_pretty_printer(), replace=True)

$ cat CHAR16.c
#include <stdio.h>

///
/// 2-byte Character.  Unless otherwise specified all strings are stored in the
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
///
typedef unsigned short      CHAR16;

CHAR16 gChar    = L'X';
CHAR16 gChar2   = L'\x23f3';
CHAR16 gStr[]   = L"1234567890\x23f3"; 
CHAR16 *gStrPtr = gStr;      

char Char       = 'X';
char Str[]      = "1234567890";
char *StrPtr    = Str;

int
main(int argc, char **argv)
{
  printf ("hello world!\n");
  return 0;
}

$ cat CHAR16.sh
gcc -fshort-wchar -g CHAR16.c
gdb  -ex "source CHAR16.py" -ex "p Char" -ex "p gChar" -ex "shell echo ' '" -ex "p Str" -ex "p gStr" -ex "shell echo ' '" -ex "p StrPtr" -ex "p gStrPtr”

Given the above example you should be able to experiment with just the code in this email to figure out how to get CHAR16 working. No edk2 or EFI knowledge required, in case you have a friend who is good with gdb pretty print?

If you have CHAR16.sh, CHAR16.c, and CHAR16.py you can just run ./CHAR16.sh and it will print out the results for char and CHAR16 if you modify the CHAR16.py gdb Python script it will show you the results. 

Thanks,

Andrew Fish




Re: BaseCryptLib in ARM incorrectly marked as a DXE_DRIVER

Andrew Fish
 

Arti,

Can you be a little more specific? Which INF file? How is it used? Sorry I don’t know a lot about this library. 

The different INF files pull in different allocation strategies for the common library code. 

SysCall/BaseMemAllocation.c

The most important line in the INF is:

LIBRARY_CLASS = BaseCryptLib|DXE_RUNTIME_DRIVER

or

LIBRARY_CLASS = BaseCryptLib|DXE_DRIVER DXE_CORE UEFI_APPLICATION UEFI_DRIVER

The list after the | is what module types this library can be linked into. I don’t remember what issue a wrong MODULE_TYPE for a library would cause. I think the LIBRARY_CLASS list may override the MODULE_TYPE in terms of how this library gets consumed. 

Thanks,

Andrew Fish

On Jul 14, 2021, at 1:34 PM, Arti Gupta via groups.io <arti.gupta@...> wrote:

Hello,
 
I am seeing that the BaseCryptLib in ARM is declared as a DXE_DRIVER instead of a DXE_RUNTIME_DRIVER, however it has a RuntimeMemAllocation.c which registers for the virtualaddresschange event so that tells me that the lib is expected to live in runtime. Is this bug known? What are the next steps for getting this fixed?
 
Thanks,
Arti


Re: [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Michael D Kinney
 

pushed:

e235a2ee42..bfabeef4c9

Mike

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@intel.com>
Sent: Wednesday, July 14, 2021 8:28 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>; mikuback@linux.microsoft.com; Kinney, Michael D
<michael.d.kinney@intel.com>
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>
Subject: RE: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Acked-by: Michael D Kinney <michael.d.kinney@intel.com>


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Wednesday, July 14, 2021 8:14 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>; mikuback@linux.microsoft.com
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>; Yao, Jiewen
<jiewen.yao@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Wednesday, June 16, 2021 8:41 AM
To: devel@edk2.groups.io; mikuback@linux.microsoft.com
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add
TPM platform hier disable support

Thank you, Michael.

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
Kubacki
Sent: Wednesday, June 16, 2021 4:57 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg:
Add
TPM platform hier disable support

It's been a week and I haven't seen any feedback. Please review when
possible.

Thanks,
Michael

On 6/7/2021 12:05 PM, Michael Kubacki wrote:
From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3411

This patch series adds support in TpmPlatformHierarchyLib to either
randomize the platform auth (current behavior) or disable the
platform auth (new behavior) based on a new PCD introduced to
MinPlatformPkg: PcdRandomizePlatformHierarchy.

Some platforms that would like to adopt MinPlatformPkg prefer to
disable the platform hierarchy as opposed to the randomization
approach.

Minor changes are included to eliminate code duplication in impacted
code.

V2 changes:
1. Update code that randomizes the platform auth in Tcg2PlatformPei
to use the TpmPlatformHierarchyLib interface for platform
hierarchy configuration.
2. Remove pre-existing redundant code in Tcg2PlatformPei.
3. Add a PCD to allow the platform integrator to choose how to
configure the TPM platform hierarchy.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeremiah Cox <jerecox@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

Michael Kubacki (4):
MinPlatformPkg: Add TpmPlatformHierarchyLib to Components in DSC
MinPlatformPkg/TpmPlatformHierarchyLib: Add PEI support
MinPlatformPkg/Tcg2PlatformPei: Use TpmPlatformHierarchyLib
MinPlatformPkg/TpmPlatformHierarchyLib: Add disable support

Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} | 72
+++++++++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
| 130 +-------------------
Platform/Intel/MinPlatformPkg/Include/Library/TpmPlatformHierarchyLib.h
| 4 +-
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
| 1 +
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
| 4 +-
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} | 22
++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
| 2 +
7 files changed, 85 insertions(+), 150 deletions(-)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} (70%)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} (66%)









Re: [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Michael D Kinney
 

Acked-by: Michael D Kinney <michael.d.kinney@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Wednesday, July 14, 2021 8:14 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>; mikuback@linux.microsoft.com
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>; Yao, Jiewen
<jiewen.yao@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Wednesday, June 16, 2021 8:41 AM
To: devel@edk2.groups.io; mikuback@linux.microsoft.com
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add
TPM platform hier disable support

Thank you, Michael.

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
Kubacki
Sent: Wednesday, June 16, 2021 4:57 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg:
Add
TPM platform hier disable support

It's been a week and I haven't seen any feedback. Please review when
possible.

Thanks,
Michael

On 6/7/2021 12:05 PM, Michael Kubacki wrote:
From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3411

This patch series adds support in TpmPlatformHierarchyLib to either
randomize the platform auth (current behavior) or disable the
platform auth (new behavior) based on a new PCD introduced to
MinPlatformPkg: PcdRandomizePlatformHierarchy.

Some platforms that would like to adopt MinPlatformPkg prefer to
disable the platform hierarchy as opposed to the randomization
approach.

Minor changes are included to eliminate code duplication in impacted
code.

V2 changes:
1. Update code that randomizes the platform auth in Tcg2PlatformPei
to use the TpmPlatformHierarchyLib interface for platform
hierarchy configuration.
2. Remove pre-existing redundant code in Tcg2PlatformPei.
3. Add a PCD to allow the platform integrator to choose how to
configure the TPM platform hierarchy.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeremiah Cox <jerecox@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

Michael Kubacki (4):
MinPlatformPkg: Add TpmPlatformHierarchyLib to Components in DSC
MinPlatformPkg/TpmPlatformHierarchyLib: Add PEI support
MinPlatformPkg/Tcg2PlatformPei: Use TpmPlatformHierarchyLib
MinPlatformPkg/TpmPlatformHierarchyLib: Add disable support

Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} | 72
+++++++++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
| 130 +-------------------
Platform/Intel/MinPlatformPkg/Include/Library/TpmPlatformHierarchyLib.h
| 4 +-
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
| 1 +
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
| 4 +-
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} | 22
++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
| 2 +
7 files changed, 85 insertions(+), 150 deletions(-)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} (70%)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} (66%)









ARMPkg: BaseCryptLib incorrectly marked as a DXE_DRIVER instead of DXE_RUNTIME_DRIVER

Arti Gupta <arti.gupta@...>
 

Hello,

 

I am seeing that the BaseCryptLib in ARM is declared as a DXE_DRIVER instead of a DXE_RUNTIME_DRIVER, however it has a RuntimeMemAllocation.c which registers for the virtualaddresschange event so that tells me that the lib is expected to live in runtime

 

Thanks,
Arti


BaseCryptLib in ARM incorrectly marked as a DXE_DRIVER

Arti Gupta <arti.gupta@...>
 

Hello,

 

I am seeing that the BaseCryptLib in ARM is declared as a DXE_DRIVER instead of a DXE_RUNTIME_DRIVER, however it has a RuntimeMemAllocation.c which registers for the virtualaddresschange event so that tells me that the lib is expected to live in runtime. Is this bug known? What are the next steps for getting this fixed?

 

Thanks,
Arti


Re: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation

Sunil V L <sunilvl@...>
 

On Tue, Jul 13, 2021 at 05:27:30PM +0800, Daniel Schaefer wrote:
Looks good. I compared it with existing R_RISCV_PCREL_LO12_I and looked at
the differences.
Thanks Daniel.

This one doesn't do use mRiscVPass1GotFixup.
I assume this is an optimization that's not possible here?
GOT fixup is required only for load to avoid the indirection for symbol
resolution.

Thanks
Sunil

Haven't tested that it works but since it works for Pete:

Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>

Thanks!

On 7/10/21 2:31 PM, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459

This patch adds support for R_RISCV_PCREL_LO12_S relocation type.
The logic is same as existing R_RISCV_PCREL_LO12_I relocation
except the difference between load vs store instruction formats.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 55 +++++++++++++++++++++++++
1 file changed, 55 insertions(+)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 3d7e20aaff..0bb3ead228 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -557,6 +557,60 @@ WriteSectionRiscV64 (
Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
break;
+ case R_RISCV_PCREL_LO12_S:
+ if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
+ int i;
+ Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
+
+ Value = ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5);
+ Value = (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5)));
+
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
+ Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
+ if(-2048 > (INT32)Value) {
+ i = (((INT32)Value * -1) / 4096);
+ Value2 -= i;
+ Value += 4096 * i;
+ if(-2048 > (INT32)Value) {
+ Value2 -= 1;
+ Value += 4096;
+ }
+ }
+ else if( 2047 < (INT32)Value) {
+ i = (Value / 4096);
+ Value2 += i;
+ Value -= 4096 * i;
+ if(2047 < (INT32)Value) {
+ Value2 += 1;
+ Value -= 4096;
+ }
+ }
+
+ // Update the IMM of SD instruction
+ //
+ // |31 25|24 20|19 15|14 12 |11 7|6 0|
+ // |-------------------------------------------|-------|
+ // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode|
+ // ---------------------------------------------------
+
+ // First Zero out current IMM
+ *(UINT32 *)Targ &= ~0xfe000f80;
+
+ // Update with new IMM
+ *(UINT32 *)Targ |= (RV_X(Value, 5, 7) << 25);
+ *(UINT32 *)Targ |= (RV_X(Value, 0, 5) << 7);
+
+ // Update previous instruction
+ *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
+ }
+ mRiscVPass1Sym = NULL;
+ mRiscVPass1Targ = NULL;
+ mRiscVPass1SymSecIndex = 0;
+ break;
+
case R_RISCV_PCREL_LO12_I:
if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
int i;
@@ -1587,6 +1641,7 @@ WriteRelocations64 (
case R_RISCV_PCREL_HI20:
case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_LO12_I:
+ case R_RISCV_PCREL_LO12_S:
break;
default:


Re: [PATCH v6 00/11] Secure Boot default keys

Yao, Jiewen
 

Thank you very much Grzegorz.

SecurityPkg: Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Grzegorz
Bernacki
Sent: Wednesday, July 14, 2021 8:30 PM
To: devel@edk2.groups.io
Cc: leif@nuviainc.com; ardb+tianocore@kernel.org; Samer.El-Haj-
Mahmoud@arm.com; sunny.Wang@arm.com; mw@semihalf.com;
upstream@semihalf.com; Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J
<jian.j.wang@intel.com>; Xu, Min M <min.m.xu@intel.com>;
lersek@redhat.com; sami.mujawar@arm.com; afish@apple.com; Ni, Ray
<ray.ni@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>;
rebecca@bsdio.com; grehan@freebsd.org; thomas.abraham@arm.com; Chiu,
Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; gaoliming@byosoft.com.cn; Dong, Eric
<eric.dong@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Sun,
Zailiang <zailiang.sun@intel.com>; Qian, Yi <yi.qian@intel.com>;
graeme@nuviainc.com; rad@semihalf.com; pete@akeo.ie; Grzegorz Bernacki
<gjb@semihalf.com>
Subject: [edk2-devel] [PATCH v6 00/11] Secure Boot default keys

This patchset adds support for initialization of default
Secure Boot variables based on keys content embedded in
flash binary. This feature is active only if Secure Boot
is enabled and DEFAULT_KEY is defined. The patchset
consist also application to enroll keys from default
variables and secure boot menu change to allow user
to reset key content to default values.
Discussion on design can be found at:
https://edk2.groups.io/g/rfc/topic/82139806#600

Built with:
GCC
- RISC-V (U500, U540) [requires fixes in dsc to build]
- Intel (Vlv2TbltDevicePkg (X64/IA32), Quark, MinPlatformPkg,
EmulatorPkg (X64), Bhyve, OvmfPkg (X64/IA32))
- ARM (Sgi75,SbsaQemu,DeveloperBox, RPi3/RPi4)

RISC-V, Quark, Vlv2TbltDevicePkg, Bhyve requires additional fixes to be built,
will be post on edk2 maillist later

VS2019
- Intel (OvmfPkgX64)

Test with:
GCC5/RPi4
VS2019/OvmfX64 (requires changes to enable feature)

Tests:
1. Try to enroll key in incorrect format.
2. Enroll with only PKDefault keys specified.
3. Enroll with all keys specified.
4. Enroll when keys are enrolled.
5. Reset keys values.
6. Running signed & unsigned app after enrollment.

Changes since v1:
- change names:
SecBootVariableLib => SecureBootVariableLib
SecBootDefaultKeysDxe => SecureBootDefaultKeysDxe
SecEnrollDefaultKeysApp => EnrollFromDefaultKeysApp
- change name of function CheckSetupMode to GetSetupMode
- remove ShellPkg dependecy from EnrollFromDefaultKeysApp
- rebase to master

Changes since v2:
- fix coding style for functions headers in SecureBootVariableLib.h
- add header to SecureBootDefaultKeys.fdf.inc
- remove empty line spaces in SecureBootDefaultKeysDxe files
- revert FAIL macro in EnrollFromDefaultKeysApp
- remove functions duplicates and add SecureBootVariableLib
to platforms which used it

Changes since v3:
- move SecureBootDefaultKeys.fdf.inc to ArmPlatformPkg
- leave duplicate of CreateTimeBasedPayload in PlatformVarCleanupLib
- fix typo in guid description

Changes since v4:
- reorder patches to make it bisectable
- split commits related to more than one platform
- move edk2-platform commits to separate patchset

Changes since v5:
- split SecureBootVariableLib into SecureBootVariableLib and
SecureBootVariableProvisionLib

Grzegorz Bernacki (11):
SecurityPkg: Create SecureBootVariableLib.
SecurityPkg: Create library for enrolling Secure Boot variables.
ArmVirtPkg: add SecureBootVariableLib class resolution
OvmfPkg: add SecureBootVariableLib class resolution
EmulatorPkg: add SecureBootVariableLib class resolution
SecurityPkg: Remove duplicated functions from SecureBootConfigDxe.
ArmPlatformPkg: Create include file for default key content.
SecurityPkg: Add SecureBootDefaultKeysDxe driver
SecurityPkg: Add EnrollFromDefaultKeys application.
SecurityPkg: Add new modules to Security package.
SecurityPkg: Add option to reset secure boot keys.

SecurityPkg/SecurityPkg.dec | 14 +
ArmVirtPkg/ArmVirt.dsc.inc | 2 +
EmulatorPkg/EmulatorPkg.dsc | 2 +
OvmfPkg/Bhyve/BhyveX64.dsc | 2 +
OvmfPkg/OvmfPkgIa32.dsc | 2 +
OvmfPkg/OvmfPkgIa32X64.dsc | 2 +
OvmfPkg/OvmfPkgX64.dsc | 2 +
SecurityPkg/SecurityPkg.dsc | 5 +
SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf
| 48 ++
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
| 80 +++

SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.inf | 80 +++

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx
e.inf | 3 +

SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.inf | 46 ++
SecurityPkg/Include/Library/SecureBootVariableLib.h | 153
++++++
SecurityPkg/Include/Library/SecureBootVariableProvisionLib.h |
134 +++++

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigNv
Data.h | 2 +

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfig.vfr
| 6 +
SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.c
| 110 +++++
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c
| 511 ++++++++++++++++++++

SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.c | 491 +++++++++++++++++++

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigIm
pl.c | 344 ++++++-------

SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.c | 69 +++
ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc | 70
+++
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.uni
| 17 +

SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.uni | 16 +

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigStri
ngs.uni | 4 +

SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.uni | 16 +
27 files changed, 2043 insertions(+), 188 deletions(-)
create mode 100644
SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf
create mode 100644
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
create mode 100644
SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.inf
create mode 100644
SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.inf
create mode 100644 SecurityPkg/Include/Library/SecureBootVariableLib.h
create mode 100644
SecurityPkg/Include/Library/SecureBootVariableProvisionLib.h
create mode 100644
SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.c
create mode 100644
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.c
create mode 100644
SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.c
create mode 100644
SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.c
create mode 100644 ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc
create mode 100644
SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.uni
create mode 100644
SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisi
onLib.uni
create mode 100644
SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefa
ultKeysDxe.uni

--
2.25.1





Re: [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add TPM platform hier disable support

Yao, Jiewen
 

Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Wednesday, June 16, 2021 8:41 AM
To: devel@edk2.groups.io; mikuback@linux.microsoft.com
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg: Add
TPM platform hier disable support

Thank you, Michael.

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael
Kubacki
Sent: Wednesday, June 16, 2021 4:57 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Dong, Eric <eric.dong@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
Jeremiah Cox <jerecox@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v2 0/4] MinPlatformPkg:
Add
TPM platform hier disable support

It's been a week and I haven't seen any feedback. Please review when
possible.

Thanks,
Michael

On 6/7/2021 12:05 PM, Michael Kubacki wrote:
From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3411

This patch series adds support in TpmPlatformHierarchyLib to either
randomize the platform auth (current behavior) or disable the
platform auth (new behavior) based on a new PCD introduced to
MinPlatformPkg: PcdRandomizePlatformHierarchy.

Some platforms that would like to adopt MinPlatformPkg prefer to
disable the platform hierarchy as opposed to the randomization
approach.

Minor changes are included to eliminate code duplication in impacted
code.

V2 changes:
1. Update code that randomizes the platform auth in Tcg2PlatformPei
to use the TpmPlatformHierarchyLib interface for platform
hierarchy configuration.
2. Remove pre-existing redundant code in Tcg2PlatformPei.
3. Add a PCD to allow the platform integrator to choose how to
configure the TPM platform hierarchy.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeremiah Cox <jerecox@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>

Michael Kubacki (4):
MinPlatformPkg: Add TpmPlatformHierarchyLib to Components in DSC
MinPlatformPkg/TpmPlatformHierarchyLib: Add PEI support
MinPlatformPkg/Tcg2PlatformPei: Use TpmPlatformHierarchyLib
MinPlatformPkg/TpmPlatformHierarchyLib: Add disable support

Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} | 72
+++++++++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.c
| 130 +-------------------
Platform/Intel/MinPlatformPkg/Include/Library/TpmPlatformHierarchyLib.h
| 4 +-
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
| 1 +
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
| 4 +-
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} | 22
++--
Platform/Intel/MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
| 2 +
7 files changed, 85 insertions(+), 150 deletions(-)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.c =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c} (70%)
rename
Platform/Intel/MinPlatformPkg/Tcg/Library/{TpmPlatformHierarchyLib/TpmPlat
formHierarchyLib.inf =>
PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf} (66%)






Re: [edk2-platforms] [PATCH V1 00/17] Add IceLake-SP and CooperLake Support to MinPlatform

Nate DeSimone
 

The series has been pushed as b313d285~..e235a2ee

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate DeSimone
Sent: Monday, July 12, 2021 5:41 PM
To: devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@intel.com>; Abbas, Mohamed <mohamed.abbas@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Michael Kubacki <Michael.Kubacki@microsoft.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH V1 00/17] Add IceLake-SP and CooperLake Support to MinPlatform

This patch series adds WhitleyOpenBoardPkg and WhitleySiliconPkg
to edk2-platforms. These platforms along with the corresponding
FSP and microcode binaries support the 3rd Generation Xeon
Scalable processors formerly known as IceLake-SP and CooperLake.

There are still some issues to be worked out. WhitleySiliconPkg
has multiple DEC files that need to be mered together. And the
WhitleyOpenBoardPkg DSC files need to be adjusted to conform to
the MinPlatform *OpenBoardPkg guidelines. Additionally, there
are non-standard build flags that replicate functionality
provided by already existing FixedAtBuild PCDs. For example,
FSP_MODE instead of PcdFspModeSelection. These issues will
be addressed in future patch series.

Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Co-authored-by: Isaac Oram <isaac.w.oram@intel.com>
Co-authored-by: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael Kubacki <Michael.Kubacki@microsoft.com>

Nate DeSimone (17):
WhitleySiliconPkg: Add DEC and DSC files
WhitleySiliconPkg: Add Includes and Libraries
WhitleySiliconPkg: Add Cpu Includes
WhitleySiliconPkg: Add Me Includes
WhitleySiliconPkg: Add PCH Register Includes
WhitleySiliconPkg: Add PCH Includes
WhitleySiliconPkg: Add PCH Libraries
WhitleySiliconPkg: Add Security Includes
WhitleySiliconPkg: Add SiliconPolicyInit
WhitleyOpenBoardPkg: Add Includes and Libraries
WhitleyOpenBoardPkg: Add Platform Modules
WhitleyOpenBoardPkg: Add Feature Modules
WhitleyOpenBoardPkg: Add UBA Modules
WhitleyOpenBoardPkg: Add build scripts and package metadata
Platform/Intel: Add WhitleyOpenBoardPkg to build_bios.py
Readme.md: Add WhitleyOpenBoardPkg
Maintainers.txt: Add WhitleyOpenBoardPkg and WhitleySiliconPkg

Maintainers.txt | 12 +
Platform/Intel/Readme.md | 14 +
.../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c | 104 +
.../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h | 67 +
.../WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf | 70 +
.../CooperCityRvp/build_board.py | 111 +
.../CooperCityRvp/build_config.cfg | 36 +
.../Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c | 704 ++
.../PlatformCpuPolicy/PlatformCpuPolicy.inf | 81 +
.../WhitleyOpenBoardPkg/DynamicExPcd.dsc | 19 +
.../Pci/Dxe/PciHostBridge/PciHostBridge.c | 1634 ++++
.../Pci/Dxe/PciHostBridge/PciHostBridge.h | 300 +
.../Pci/Dxe/PciHostBridge/PciHostBridge.inf | 69 +
.../Dxe/PciHostBridge/PciHostBridgeSupport.c | 127 +
.../Pci/Dxe/PciHostBridge/PciHostResource.h | 62 +
.../Pci/Dxe/PciHostBridge/PciRebalance.c | 1356 +++
.../Pci/Dxe/PciHostBridge/PciRebalance.h | 158 +
.../Pci/Dxe/PciHostBridge/PciRebalanceIo.c | 218 +
.../Dxe/PciHostBridge/PciRebalanceMmio32.c | 163 +
.../Dxe/PciHostBridge/PciRebalanceMmio64.c | 204 +
.../Pci/Dxe/PciHostBridge/PciRootBridge.h | 573 ++
.../Pci/Dxe/PciHostBridge/PciRootBridgeIo.c | 1664 ++++
.../Dxe/PciPlatform/PciIovPlatformPolicy.c | 99 +
.../Dxe/PciPlatform/PciIovPlatformPolicy.h | 53 +
.../Pci/Dxe/PciPlatform/PciPlatform.c | 541 ++
.../Pci/Dxe/PciPlatform/PciPlatform.h | 209 +
.../Pci/Dxe/PciPlatform/PciPlatform.inf | 87 +
.../Pci/Dxe/PciPlatform/PciPlatformHooks.c | 939 ++
.../Pci/Dxe/PciPlatform/PciPlatformHooks.h | 31 +
.../Pci/Dxe/PciPlatform/PciSupportLib.c | 108 +
.../Pci/Dxe/PciPlatform/PciSupportLib.h | 46 +
.../Pei/PlatformVariableInitPei.c | 274 +
.../Pei/PlatformVariableInitPei.h | 41 +
.../Pei/PlatformVariableInitPei.inf | 58 +
.../WhitleyOpenBoardPkg/FspFlashOffsets.fdf | 21 +
.../Include/Dsc/CoreDxeInclude.dsc | 135 +
...blePerformanceMonitoringInfrastructure.dsc | 40 +
.../Include/Dsc/EnableRichDebugMessages.dsc | 50 +
.../Include/Fdf/CommonNvStorageFtwWorking.fdf | 20 +
.../Include/Fdf/CommonSpiFvHeaderInfo.fdf | 24 +
...anceMonitoringInfrastructurePostMemory.fdf | 14 +
...manceMonitoringInfrastructurePreMemory.fdf | 11 +
.../Include/Fdf/NvStorage512K.fdf | 46 +
.../Include/GpioInitData.h | 26 +
.../Include/Guid/PlatformVariableCommon.h | 33 +
.../Include/Guid/SetupVariable.h | 720 ++
.../Include/Guid/UbaCfgHob.h | 74 +
.../WhitleyOpenBoardPkg/Include/IoApic.h | 23 +
.../Include/Library/MultiPlatSupportLib.h | 67 +
.../Include/Library/PeiPlatformHooklib.h | 17 +
.../Include/Library/PlatformClocksLib.h | 87 +
.../Include/Library/PlatformOpromPolicyLib.h | 83 +
.../Library/PlatformSetupVariableSyncLib.h | 60 +
.../Include/Library/PlatformVariableHookLib.h | 47 +
.../Include/Library/ReadFfsLib.h | 58 +
.../Include/Library/SetupLib.h | 134 +
.../Include/Library/UbaAcpiUpdateLib.h | 38 +
.../Include/Library/UbaBoardSioInfoLib.h | 47 +
.../Include/Library/UbaClkGenUpdateLib.h | 49 +
.../Include/Library/UbaClocksConfigLib.h | 51 +
.../Include/Library/UbaGpioInitLib.h | 26 +
.../Include/Library/UbaGpioPlatformConfig.h | 259 +
.../Include/Library/UbaGpioUpdateLib.h | 51 +
.../Library/UbaHsioPtssTableConfigLib.h | 52 +
.../Include/Library/UbaIioConfigLib.h | 227 +
.../Library/UbaIioPortBifurcationInitLib.h | 47 +
.../Include/Library/UbaOpromUpdateLib.h | 115 +
.../Include/Library/UbaPcdUpdateLib.h | 44 +
.../Include/Library/UbaPchEarlyUpdateLib.h | 63 +
.../Library/UbaPcieBifurcationUpdateLib.h | 130 +
.../Include/Library/UbaPlatLib.h | 25 +
.../Include/Library/UbaSlotUpdateLib.h | 124 +
.../Include/Library/UbaSoftStrapUpdateLib.h | 57 +
.../Include/Library/UbaSystemBoardInfoLib.h | 36 +
.../Library/UbaSystemConfigUpdateLib.h | 42 +
.../Include/Library/UbaUsbOcUpdateLib.h | 51 +
.../Include/OnboardNicStructs.h | 98 +
.../Include/PchSetupVariable.h | 10 +
.../Include/PchSetupVariableLbg.h | 372 +
.../WhitleyOpenBoardPkg/Include/PlatDevData.h | 183 +
.../Include/PlatPirqData.h | 36 +
.../Include/Ppi/ExReportStatusCodeHandler.h | 38 +
.../Include/Ppi/SmbusPolicy.h | 29 +
.../Include/Ppi/UbaCfgDb.h | 144 +
.../Include/Protocol/LegacyBios.h | 1550 +++
.../Include/Protocol/LegacyBiosPlatform.h | 752 ++
.../Include/Protocol/PciIovPlatform.h | 72 +
.../Include/Protocol/PlatformType.h | 48 +
.../Include/Protocol/UbaCfgDb.h | 114 +
.../Include/Protocol/UbaDevsUpdateProtocol.h | 86 +
.../Include/Protocol/UbaMakerProtocol.h | 22 +
.../WhitleyOpenBoardPkg/Include/SetupTable.h | 25 +
.../WhitleyOpenBoardPkg/Include/SioRegs.h | 251 +
.../WhitleyOpenBoardPkg/Include/SystemBoard.h | 75 +
.../WhitleyOpenBoardPkg/Include/UbaKti.h | 29 +
.../BoardAcpiLib/DxeBoardAcpiTableLib.c | 37 +
.../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 44 +
.../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 54 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 51 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 48 +
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 138 +
.../Library/BoardInitLib/BoardInitDxeLib.c | 299 +
.../Library/BoardInitLib/BoardInitDxeLib.inf | 72 +
.../Library/BoardInitLib/BoardInitDxeLib.uni | 29 +
.../Library/BoardInitLib/BoardInitPreMemLib.c | 450 +
.../BoardInitLib/BoardInitPreMemLib.inf | 66 +
.../MultiPlatSupportLib/MultiPlatSupport.h | 48 +
.../MultiPlatSupportLib/MultiPlatSupportLib.c | 255 +
.../MultiPlatSupportLib.inf | 49 +
.../FspWrapperHobProcessLib.c | 722 ++
.../PeiFspWrapperHobProcessLib.inf | 99 +
.../PeiPlatformHookLib/PeiPlatformHooklib.c | 43 +
.../PeiPlatformHookLib/PeiPlatformHooklib.inf | 34 +
.../Library/PeiReportFvLib/PeiReportFvLib.c | 270 +
.../Library/PeiReportFvLib/PeiReportFvLib.inf | 65 +
.../PeiUbaGpioPlatformConfigLib.c | 518 +
.../Library/PeiUbaPlatLib/PeiUbaPlatLib.inf | 60 +
.../PeiUbaPlatLib/PeiUbaUsbOcUpdateLib.c | 61 +
.../PeiUbaPlatLib/UbaBoardSioInfoLib.c | 54 +
.../PeiUbaPlatLib/UbaClkGenUpdateLib.c | 134 +
.../PeiUbaPlatLib/UbaClocksConfigLib.c | 59 +
.../Library/PeiUbaPlatLib/UbaGpioUpdateLib.c | 68 +
.../PeiUbaPlatLib/UbaHsioPtssTableConfigLib.c | 58 +
.../PeiUbaPlatLib/UbaIioConfigLibPei.c | 219 +
.../UbaIioPortBifurcationInitLib.c | 55 +
.../Library/PeiUbaPlatLib/UbaPcdUpdateLib.c | 69 +
.../PeiUbaPlatLib/UbaPchEarlyUpdateLib.c | 108 +
.../PeiUbaPlatLib/UbaPchPcieBifurcationLib.c | 57 +
.../PeiUbaPlatLib/UbaSlotUpdateLibPei.c | 156 +
.../PeiUbaPlatLib/UbaSoftStrapUpdateLib.c | 95 +
.../PlatformClocksLib/Pei/PlatformClocksLib.c | 347 +
.../Pei/PlatformClocksLib.inf | 40 +
.../PlatformCmosAccessLib.c | 73 +
.../PlatformCmosAccessLib.inf | 45 +
.../Library/PlatformHooksLib/PlatformHooks.c | 203 +
.../PlatformHooksLib/PlatformHooksLib.inf | 28 +
.../PlatformOpromPolicyLibNull.c | 88 +
.../PlatformOpromPolicyLibNull.inf | 29 +
.../PlatformSetupVariableSyncLibNull.c | 81 +
.../PlatformSetupVariableSyncLibNull.inf | 28 +
.../PlatformVariableHookLibNull.c | 55 +
.../PlatformVariableHookLibNull.inf | 24 +
.../Library/ReadFfsLib/ReadFfsLib.c | 446 +
.../Library/ReadFfsLib/ReadFfsLib.inf | 34 +
.../Library/SerialPortLib/Ns16550.h | 46 +
.../Library/SerialPortLib/SerialPortLib.c | 1023 ++
.../Library/SerialPortLib/SerialPortLib.inf | 55 +
.../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 867 ++
.../SetCacheMtrrLib/SetCacheMtrrLib.inf | 55 +
.../PchPolicyUpdateUsb.c | 152 +
.../SiliconPolicyUpdateLib.c | 778 ++
.../SiliconPolicyUpdateLib.inf | 64 +
.../SiliconPolicyUpdateLibFsp.c | 770 ++
.../SiliconPolicyUpdateLibFsp.inf | 68 +
.../SmmSpiFlashCommonLib.inf | 57 +
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 237 +
.../SpiFlashCommonSmmLib.c | 55 +
.../DxeTcg2PhysicalPresenceLib.c | 41 +
.../DxeTcg2PhysicalPresenceLib.inf | 29 +
.../Library/UbaGpioInitLib/UbaGpioInitLib.c | 145 +
.../Library/UbaGpioInitLib/UbaGpioInitLib.inf | 46 +
.../Dxe/PlatformType/PlatformType.inf | 58 +
.../Platform/Dxe/PlatformType/PlatformTypes.c | 364 +
.../Platform/Dxe/PlatformType/PlatformTypes.h | 58 +
.../Platform/Dxe/S3NvramSave/S3NvramSave.c | 157 +
.../Platform/Dxe/S3NvramSave/S3NvramSave.h | 40 +
.../Platform/Dxe/S3NvramSave/S3NvramSave.inf | 52 +
.../Platform/Pei/DummyPchSpi/DummyPchSpi.inf | 43 +
.../Platform/Pei/DummyPchSpi/PchSpi.c | 383 +
.../EmulationPlatformInit.c | 124 +
.../EmulationPlatformInit.inf | 46 +
.../Platform/Pei/PlatformInfo/PlatformInfo.c | 761 ++
.../Platform/Pei/PlatformInfo/PlatformInfo.h | 89 +
.../Pei/PlatformInfo/PlatformInfo.inf | 63 +
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 781 ++
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 931 ++
.../Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 827 ++
.../WhitleyOpenBoardPkg/PlatformPkgConfig.dsc | 45 +
.../WhitleyOpenBoardPkg/StructurePcd.dsc | 8553 +++++++++++++++++
.../WhitleyOpenBoardPkg/StructurePcdCpx.dsc | 3796 ++++++++
.../Uba/BoardInit/Dxe/BoardInitDxe.c | 87 +
.../Uba/BoardInit/Dxe/BoardInitDxe.h | 30 +
.../Uba/BoardInit/Dxe/BoardInitDxe.inf | 70 +
.../Uba/BoardInit/Pei/BoardInitPei.c | 48 +
.../Uba/BoardInit/Pei/BoardInitPei.h | 20 +
.../Uba/BoardInit/Pei/BoardInitPei.inf | 55 +
.../Uba/CfgDb/Dxe/CfgDbDxe.c | 518 +
.../Uba/CfgDb/Dxe/CfgDbDxe.h | 32 +
.../Uba/CfgDb/Dxe/CfgDbDxe.inf | 54 +
.../Uba/CfgDb/Pei/CfgDbPei.c | 803 ++
.../Uba/CfgDb/Pei/CfgDbPei.h | 33 +
.../Uba/CfgDb/Pei/CfgDbPei.inf | 54 +
.../WhitleyOpenBoardPkg/Uba/UbaCommon.dsc | 29 +
.../WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf | 16 +
.../Uba/UbaDxeRpBoards.fdf | 22 +
.../SystemBoardInfoDxe/SystemBoardInfoDxe.c | 206 +
.../SystemBoardInfoDxe/SystemBoardInfoDxe.h | 33 +
.../SystemBoardInfoDxe/SystemBoardInfoDxe.inf | 45 +
.../SystemConfigUpdateDxe.c | 94 +
.../SystemConfigUpdateDxe.h | 30 +
.../SystemConfigUpdateDxe.inf | 48 +
.../Uba/UbaMain/Common/Pei/BoardInfo.c | 69 +
.../Uba/UbaMain/Common/Pei/Clockgen.c | 27 +
.../Uba/UbaMain/Common/Pei/ClocksConfig.c | 177 +
.../UbaMain/Common/Pei/GpioPlatformConfig.c | 166 +
.../UbaMain/Common/Pei/HsioPtssTableConfig.c | 460 +
.../Common/Pei/IioBifurcationSlotTable.h | 156 +
.../UbaMain/Common/Pei/IioPortBifurcation.c | 913 ++
.../Common/Pei/IioPortBifurcationVer1.c | 1356 +++
.../UbaMain/Common/Pei/PchHsioPtssTables.h | 51 +
.../Common/Pei/PchLbgHsioPtssTablesBx.c | 44 +
.../Common/Pei/PchLbgHsioPtssTablesBx.h | 18 +
.../Common/Pei/PchLbgHsioPtssTablesBx_Ext.c | 44 +
.../Common/Pei/PchLbgHsioPtssTablesBx_Ext.h | 20 +
.../Common/Pei/PchLbgHsioPtssTablesSx.c | 27 +
.../Common/Pei/PchLbgHsioPtssTablesSx.h | 21 +
.../Common/Pei/PchLbgHsioPtssTablesSx_Ext.c | 44 +
.../Common/Pei/PchLbgHsioPtssTablesSx_Ext.h | 21 +
.../Common/Pei/PeiCommonBoardInitLib.c | 75 +
.../Common/Pei/PeiCommonBoardInitLib.h | 55 +
.../Common/Pei/PeiCommonBoardInitLib.inf | 76 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 107 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 161 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +
.../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 108 +
.../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 +
.../SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 124 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 +
.../TypeCooperCityRP/Pei/AcpiTablePcds.c | 51 +
.../UbaMain/TypeCooperCityRP/Pei/GpioTable.c | 297 +
.../TypeCooperCityRP/Pei/IioBifurInit.c | 393 +
.../UbaMain/TypeCooperCityRP/Pei/KtiEparam.c | 241 +
.../UbaMain/TypeCooperCityRP/Pei/PcdData.c | 259 +
.../TypeCooperCityRP/Pei/PchEarlyUpdate.c | 81 +
.../TypeCooperCityRP/Pei/PeiBoardInit.h | 96 +
.../TypeCooperCityRP/Pei/PeiBoardInitLib.c | 224 +
.../TypeCooperCityRP/Pei/PeiBoardInitLib.inf | 163 +
.../UbaMain/TypeCooperCityRP/Pei/SlotTable.c | 164 +
.../TypeCooperCityRP/Pei/SoftStrapFixup.c | 110 +
.../Uba/UbaMain/TypeCooperCityRP/Pei/UsbOC.c | 123 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 99 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 118 +
.../Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 47 +
.../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 115 +
.../Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 +
.../SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 47 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 127 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +
.../Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 +
.../TypeWilsonCityRP/Pei/AcpiTablePcds.c | 53 +
.../UbaMain/TypeWilsonCityRP/Pei/GpioTable.c | 287 +
.../TypeWilsonCityRP/Pei/IioBifurInit.c | 387 +
.../UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c | 107 +
.../UbaMain/TypeWilsonCityRP/Pei/PcdData.c | 274 +
.../TypeWilsonCityRP/Pei/PchEarlyUpdate.c | 92 +
.../TypeWilsonCityRP/Pei/PeiBoardInit.h | 77 +
.../TypeWilsonCityRP/Pei/PeiBoardInitLib.c | 156 +
.../TypeWilsonCityRP/Pei/PeiBoardInitLib.inf | 166 +
.../UbaMain/TypeWilsonCityRP/Pei/SlotTable.c | 171 +
.../TypeWilsonCityRP/Pei/SoftStrapFixup.c | 120 +
.../Uba/UbaMain/TypeWilsonCityRP/Pei/UsbOC.c | 126 +
.../Intel/WhitleyOpenBoardPkg/Uba/UbaPei.fdf | 24 +
.../WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 44 +
.../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.c | 43 +
.../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.h | 20 +
.../Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.inf | 50 +
.../ExSerialStatusCodeWorker.c | 194 +
.../ExStatusCodeHandlerPei.c | 111 +
.../ExStatusCodeHandlerPei.h | 85 +
.../ExStatusCodeHandlerPei.inf | 61 +
.../ExReportStatusCodeRouterPei.c | 301 +
.../ExReportStatusCodeRouterPei.h | 104 +
.../ExReportStatusCodeRouterPei.inf | 51 +
.../PeiInterposerToSvidMap.c | 136 +
.../PeiInterposerToSvidMap.inf | 53 +
.../WilsonCityRvp/build_board.py | 111 +
.../WilsonCityRvp/build_config.cfg | 36 +
Platform/Intel/build.cfg | 2 +
Platform/Intel/build_bios.py | 28 +-
Readme.md | 2 +
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 541 ++
.../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 101 +
.../Cpu/Include/CpuDataStruct.h | 27 +
.../Cpu/Include/CpuPolicyPeiDxeCommon.h | 58 +
.../Cpu/Include/Guid/CpuNvramData.h | 34 +
.../Cpu/Include/Library/CpuConfigLib.h | 30 +
.../Cpu/Include/Library/CpuEarlyDataLib.h | 41 +
.../Cpu/Include/Library/CpuPpmLib.h | 16 +
.../Cpu/Include/PpmPolicyPeiDxeCommon.h | 320 +
.../Cpu/Include/ProcessorPpmSetup.h | 14 +
.../Cpu/Include/Protocol/CpuPolicyProtocol.h | 31 +
.../Cpu/Include/Protocol/PpmPolicyProtocol.h | 16 +
.../Include/BackCompatible.h | 19 +
.../Include/ConfigBlock/TraceHubConfig.h | 65 +
.../Include/ConfigBlock/Usb2PhyConfig.h | 63 +
.../Include/ConfigBlock/UsbConfig.h | 85 +
.../WhitleySiliconPkg/Include/Cpu/CpuIds.h | 18 +
.../Include/CpuAndRevisionDefines.h | 283 +
.../Include/EmulationConfiguration.h | 22 +
.../Intel/WhitleySiliconPkg/Include/Fpga.h | 17 +
.../WhitleySiliconPkg/Include/GpioConfig.h | 288 +
.../Include/Guid/EmulationDfxVariable.h | 25 +
.../Include/Guid/FpgaSocketVariable.h | 39 +
.../Include/Guid/MemBootHealthGuid.h | 71 +
.../Include/Guid/MemoryMapData.h | 197 +
.../Include/Guid/PartialMirrorGuid.h | 61 +
.../Include/Guid/PlatformInfo.h | 150 +
.../Guid/SiliconPolicyInitLibInterface.h | 78 +
.../Include/Guid/SocketCommonRcVariable.h | 57 +
.../Include/Guid/SocketIioVariable.h | 444 +
.../Include/Guid/SocketMemoryVariable.h | 477 +
.../Include/Guid/SocketMpLinkVariable.h | 320 +
.../Include/Guid/SocketPciResourceData.h | 60 +
.../Guid/SocketPowermanagementVariable.h | 300 +
.../Guid/SocketProcessorCoreVariable.h | 143 +
.../Include/Guid/SocketVariable.h | 36 +
.../Include/Guid/StatusCodeDataTypeExDebug.h | 50 +
.../WhitleySiliconPkg/Include/IioConfig.h | 398 +
.../Include/IioPlatformData.h | 204 +
.../Intel/WhitleySiliconPkg/Include/IioRegs.h | 179 +
.../Include/IioSetupDefinitions.h | 60 +
.../Include/IioUniversalData.h | 166 +
.../WhitleySiliconPkg/Include/ImonVrSvid.h | 26 +
.../Include/KtiSetupDefinitions.h | 22 +
.../Include/Library/CompressedVariableLib.h | 35 +
.../Library/EmulationConfigurationLib.h | 34 +
.../Include/Library/MemTypeLib.h | 32 +
.../Include/Library/MemVrSvidMapLib.h | 66 +
.../Include/Library/PchInfoLib.h | 22 +
.../Include/Library/PlatformHooksLib.h | 17 +
.../Include/Library/SemaphoreLib.h | 326 +
.../Intel/WhitleySiliconPkg/Include/MaxCore.h | 20 +
.../WhitleySiliconPkg/Include/MaxSocket.h | 20 +
.../WhitleySiliconPkg/Include/MaxThread.h | 20 +
.../WhitleySiliconPkg/Include/MemCommon.h | 41 +
.../Include/Memory/Ddr4SpdRegisters.h | 38 +
.../Include/Memory/ProcSmbChipCommon.h | 28 +
.../WhitleySiliconPkg/Include/Platform.h | 266 +
.../Include/PlatformInfoTypes.h | 106 +
.../Include/Ppi/DynamicSiLibraryPpi.h | 474 +
.../Include/Ppi/MemoryPolicyPpi.h | 2112 ++++
.../Include/Ppi/RasImcS3Data.h | 53 +
.../Include/Ppi/UpiPolicyPpi.h | 39 +
.../Protocol/DynamicSiLibraryProtocol.h | 252 +
.../Protocol/DynamicSiLibrarySmmProtocol.h | 60 +
.../Include/Protocol/GlobalNvsArea.h | 212 +
.../Include/Protocol/IioUds.h | 47 +
.../Include/Protocol/PciCallback.h | 85 +
.../WhitleySiliconPkg/Include/RcVersion.h | 23 +
.../Include/ScratchpadList.h | 49 +
.../Include/SiliconUpdUpdate.h | 53 +
.../WhitleySiliconPkg/Include/SystemInfoVar.h | 93 +
.../Include/UncoreCommonIncludes.h | 111 +
.../WhitleySiliconPkg/Include/Upi/KtiDisc.h | 36 +
.../WhitleySiliconPkg/Include/Upi/KtiHost.h | 304 +
.../WhitleySiliconPkg/Include/Upi/KtiSi.h | 32 +
.../Include/UsraAccessType.h | 291 +
.../Core/Include/DataTypes.h | 36 +
.../BaseMemoryCoreLib/Core/Include/MemHost.h | 1051 ++
.../Core/Include/MemHostChipCommon.h | 190 +
.../BaseMemoryCoreLib/Core/Include/MemRegs.h | 25 +
.../Core/Include/MrcCommonTypes.h | 28 +
.../Core/Include/NGNDimmPlatformCfgData.h | 22 +
.../BaseMemoryCoreLib/Core/Include/SysHost.h | 193 +
.../Core/Include/SysHostChipCommon.h | 101 +
.../BaseMemoryCoreLib/Platform/MemDefaults.h | 28 +
.../BaseMemoryCoreLib/Platform/PlatformHost.h | 35 +
.../FspWrapperPlatformLib.c | 243 +
.../FspWrapperPlatformLib.inf | 71 +
.../Library/SetupLib/PeiSetupLib.c | 259 +
.../Library/SetupLib/PeiSetupLib.inf | 55 +
.../Library/SetupLib/SetupLib.c | 253 +
.../Library/SetupLib/SetupLib.inf | 59 +
.../Library/SetupLib/SetupLibNull.c | 159 +
.../Library/SetupLib/SetupLibNull.inf | 46 +
.../SiliconPolicyInitLibShim.c | 104 +
.../SiliconPolicyInitLibShim.inf | 38 +
.../SiliconWorkaroundLibNull.c | 38 +
.../SiliconWorkaroundLibNull.inf | 50 +
.../Me/MeSps.4/Include/Library/SpsPeiLib.h | 22 +
.../WhitleySiliconPkg/MrcCommonConfig.dsc | 71 +
.../SouthClusterLbg/Include/GpioPinsSklH.h | 300 +
.../SouthClusterLbg/Include/Library/GpioLib.h | 1016 ++
.../Include/Library/PchMultiPchBase.h | 37 +
.../Include/Library/PchPcieRpLib.h | 145 +
.../Pch/SouthClusterLbg/Include/PchAccess.h | 629 ++
.../Pch/SouthClusterLbg/Include/PchLimits.h | 108 +
.../SouthClusterLbg/Include/PchPolicyCommon.h | 2161 +++++
.../Include/PchReservedResources.h | 82 +
.../Pch/SouthClusterLbg/Include/PcieRegs.h | 288 +
.../Include/Ppi/PchHsioPtssTable.h | 31 +
.../Include/Ppi/PchPcieDeviceTable.h | 126 +
.../SouthClusterLbg/Include/Ppi/PchPolicy.h | 23 +
.../SouthClusterLbg/Include/Ppi/PchReset.h | 95 +
.../Pch/SouthClusterLbg/Include/Ppi/Spi.h | 28 +
.../Include/Private/Library/PchSpiCommonLib.h | 458 +
.../Include/Protocol/PchReset.h | 114 +
.../SouthClusterLbg/Include/Protocol/Spi.h | 305 +
.../Include/Register/PchRegsDci.h | 44 +
.../Include/Register/PchRegsDmi.h | 302 +
.../Include/Register/PchRegsEva.h | 124 +
.../Include/Register/PchRegsFia.h | 106 +
.../Include/Register/PchRegsGpio.h | 531 +
.../Include/Register/PchRegsHda.h | 271 +
.../Include/Register/PchRegsHsio.h | 190 +
.../Include/Register/PchRegsItss.h | 90 +
.../Include/Register/PchRegsLan.h | 156 +
.../Include/Register/PchRegsLpc.h | 490 +
.../Include/Register/PchRegsP2sb.h | 132 +
.../Include/Register/PchRegsPcie.h | 620 ++
.../Include/Register/PchRegsPcr.h | 177 +
.../Include/Register/PchRegsPmc.h | 731 ++
.../Include/Register/PchRegsPsf.h | 304 +
.../Include/Register/PchRegsPsth.h | 66 +
.../Include/Register/PchRegsSata.h | 713 ++
.../Include/Register/PchRegsSmbus.h | 157 +
.../Include/Register/PchRegsSpi.h | 354 +
.../Include/Register/PchRegsThermal.h | 113 +
.../Include/Register/PchRegsTraceHub.h | 147 +
.../Include/Register/PchRegsUsb.h | 529 +
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 224 +
.../Product/Whitley/SiliconPkg10nmPcds.dsc | 99 +
.../SecurityIp/SecurityIpMkTme1v0_Inputs.h | 25 +
.../SecurityIp/SecurityIpMkTme1v0_Outputs.h | 18 +
.../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 39 +
.../SecurityIp/SecurityIpSgxTem1v0_Outputs.h | 22 +
.../Guid/SecurityIp/SecurityIpTdx1v0_Inputs.h | 13 +
.../SecurityIp/SecurityIpTdx1v0_Outputs.h | 11 +
.../Include/Guid/SecurityPolicy_Flat.h | 22 +
.../Intel/WhitleySiliconPkg/SiliconPkg.dec | 1004 ++
.../SiliconPolicyInit/SiliconPolicyInitLate.c | 52 +
.../SiliconPolicyInitLate.inf | 49 +
.../SiliconPolicyInitPreAndPostMem.c | 63 +
.../SiliconPolicyInitPreAndPostMem.inf | 48 +
.../WhitleySiliconPkg/WhitleySiliconPkg.dec | 65 +
437 files changed, 86801 insertions(+), 12 deletions(-)
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_board.py
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/DynamicExPcd.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostResource.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalanceIo.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalanceMmio32.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalanceMmio64.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRootBridge.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciIovPlatformPolicy.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciIovPlatformPolicy.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatformHooks.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatformHooks.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciSupportLib.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciSupportLib.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/FspFlashOffsets.fdf
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create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaUpdatePcds/Pei/UpdatePcdsPei.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExSerialStatusCodeWorker.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
create mode 100644 Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuDataStruct.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Guid/CpuNvramData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuConfigLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuEarlyDataLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Library/CpuPpmLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/PpmPolicyPeiDxeCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/ProcessorPpmSetup.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Cpu/Include/Protocol/PpmPolicyProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/BackCompatible.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/TraceHubConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/Usb2PhyConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ConfigBlock/UsbConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Cpu/CpuIds.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/CpuAndRevisionDefines.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/EmulationConfiguration.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Fpga.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/GpioConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/EmulationDfxVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/FpgaSocketVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemBootHealthGuid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PartialMirrorGuid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/PlatformInfo.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SiliconPolicyInitLibInterface.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketCommonRcVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMpLinkVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketVariable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Guid/StatusCodeDataTypeExDebug.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioPlatformData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/IioUniversalData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ImonVrSvid.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/KtiSetupDefinitions.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/CompressedVariableLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/EmulationConfigurationLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemTypeLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/MemVrSvidMapLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/PchInfoLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/PlatformHooksLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Library/SemaphoreLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxCore.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxSocket.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MaxThread.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/MemCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/Ddr4SpdRegisters.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Memory/ProcSmbChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Platform.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/DynamicSiLibraryPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibraryProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/DynamicSiLibrarySmmProtocol.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/GlobalNvsArea.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/IioUds.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Protocol/PciCallback.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/RcVersion.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/ScratchpadList.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SiliconUpdUpdate.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/SystemInfoVar.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiDisc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiSi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Include/UsraAccessType.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/NGNDimmPlatformCfgData.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/MemDefaults.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/PeiSetupLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SetupLib/SetupLibNull.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Me/MeSps.4/Include/Library/SpsPeiLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/MrcCommonConfig.dsc
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/GpioPinsSklH.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/GpioLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMultiPchBase.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchPcieRpLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchAccess.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchLimits.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchReservedResources.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PcieRegs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchHsioPtssTable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPcieDeviceTable.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchPolicy.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/PchReset.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Ppi/Spi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/PchReset.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDci.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsDmi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsEva.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsFia.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsGpio.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHda.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsHsio.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsItss.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLan.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsP2sb.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcie.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPcr.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPmc.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsf.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsPsth.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSata.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSmbus.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsSpi.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsThermal.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsTraceHub.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Register/PchRegsUsb.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpMkTme1v0_Inputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpMkTme1v0_Outputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpTdx1v0_Inputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpTdx1v0_Outputs.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy_Flat.h
create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitLate.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitLate.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitPreAndPostMem.c
create mode 100644 Silicon/Intel/WhitleySiliconPkg/SiliconPolicyInit/SiliconPolicyInitPreAndPostMem.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/WhitleySiliconPkg.dec

--
2.27.0.windows.1


Re: [PATCH] UefiPayloadPkg: Add FV Guid for DXEFV and PLDFV

Guo Dong
 

Signed-off-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Zhiguang Liu
Sent: Tuesday, July 13, 2021 11:25 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] [PATCH] UefiPayloadPkg: Add FV Guid for DXEFV and
PLDFV

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
1 file changed, 2 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf
b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 2d51fdbacb..041fed842c 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -34,6 +34,7 @@ FV = PLDFV



##########################################################
######################

[FV.PLDFV]

+FvNameGuid = 96E75986-6FDD-491E-9FD5-35E21AC45B45

BlockSize = $(FD_BLOCK_SIZE)

FvAlignment = 16

ERASE_POLARITY = 1

@@ -62,6 +63,7 @@ FILE FV_IMAGE = 4E35FD93-9C72-4c15-8C4B-
E77F1DB2D793 {

##########################################################
######################



[FV.DXEFV]

+FvNameGuid = 8063C21A-8E58-4576-95CE-089E87975D23

BlockSize = $(FD_BLOCK_SIZE)

FvForceRebase = FALSE

FvAlignment = 16

--
2.30.0.windows.2



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Re: [PATCH v1 2/2] Platform/NXP: Modify duplicated GUID in ConfigurationManagerDxe

Sami Mujawar
 

Hi Pierre,

Thank you for this patch. This fix looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar


Re: [PATCH v1 1/2] Platform/ARM/Juno: Modify duplicated GUID in SmbiosPlatformDxe

Sami Mujawar
 

Hi Pierre,

Thank you for this patch. This update looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar


Re: [PATCH edk2-platforms v1 1/1] Platform/ARM: FVP: Fix variable usage in GetArmNameSpaceObject()

Sami Mujawar
 

Pushed as 8cb431b46a08..564a6a340892

Thanks.

Regards,

Sami Mujawar

On 13/07/2021, 18:05, "Sami Mujawar" <sami.mujawar@arm.com> wrote:

Hi Joey,

Thank you for this patch. This patch looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 01/07/2021 01:24 PM, Joey Gouly wrote:
> Building with Clang showed that `RootComplexCount` and
> `DeviceIdMappingArrayCount` were unused. Use the
> variables where they were intended to be used.
>
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> ---
>
> The changes can be seen at https://github.com/jgouly/edk2-platforms/tree/1766_vexpress_count_v1
>
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index e99fbb654f5109321e32905af3763233dffdbc3e..776dec999eb1ef47910835987fa4dae1b69c52fd 100644
> --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -924,7 +924,7 @@ GetArmNameSpaceObject (
> CmObjectId,
> &PlatformRepo->RootComplexInfo,
> sizeof (PlatformRepo->RootComplexInfo),
> - 1,
> + RootComplexCount,
> CmObject
> );
> break;
> @@ -935,7 +935,7 @@ GetArmNameSpaceObject (
> CmObjectId,
> PlatformRepo->DeviceIdMapping,
> sizeof (PlatformRepo->DeviceIdMapping),
> - ARRAY_SIZE (PlatformRepo->DeviceIdMapping),
> + DeviceIdMappingArrayCount,
> Token,
> GetDeviceIdMappingArray,
> CmObject


Re: [PATCH v1 1/1] Add MemoryFence implementation for RiscV64

Abner Chang
 

Reviewed-by: Abner Chang <abner.chang@hpe.com>

-----Original Message-----
From: Schaefer, Daniel
Sent: Sunday, May 16, 2021 2:13 AM
To: devel@edk2.groups.io
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
Michael D Kinney <michael.d.kinney@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Zhiguang Liu <zhiguang.liu@intel.com>; Leif
Lindholm <leif@nuviainc.com>
Subject: [PATCH v1 1/1] Add MemoryFence implementation for RiscV64

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33
++++++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea..b7ab5f632366 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -399,6 +399,7 @@
RiscV64/DisableInterrupts.c

RiscV64/EnableInterrupts.c

RiscV64/CpuPause.c

+ RiscV64/MemoryFence.S | GCC

RiscV64/RiscVSetJumpLongJump.S | GCC

RiscV64/RiscVCpuBreakpoint.S | GCC

RiscV64/RiscVCpuPause.S | GCC

diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
new file mode 100644
index 000000000000..283df9356a9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
@@ -0,0 +1,33 @@
+##------------------------------------------------------------------------------

+#

+# MemoryFence() for RiscV64

+

+# Copyright (c) 2021, Hewlett Packard Enterprise Development. All rights
reserved.

+#

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##------------------------------------------------------------------------------

+

+.text

+.p2align 2

+

+ASM_GLOBAL ASM_PFX(MemoryFence)

+

+

+#/**

+# Used to serialize load and store operations.

+#

+# All loads and stores that proceed calls to this function are guaranteed to
be

+# globally visible when this function returns.

+#

+#**/

+#VOID

+#EFIAPI

+#MemoryFence (

+# VOID

+# );

+#

+ASM_PFX(MemoryFence):

+ // Fence on all memory and I/O

+ fence

+ ret

--
2.30.1


Re: [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp and strncpy to libfdt_env.h

Abner Chang
 

Hi Leif and Ard,
Please help to review this and merge it if you have no comments on this patch.

Thanks
Abner

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Abner Chang
Sent: Wednesday, May 19, 2021 11:30 PM
To: Schaefer, Daniel <daniel.schaefer@hpe.com>; devel@edk2.groups.io
Cc: Leif Lindholm <leif@nuviainc.com>; Ard Biesheuvel
<ard.biesheuvel@arm.com>; Anup Patel <anup.patel@wdc.com>
Subject: Re: [edk2-devel] [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp
and strncpy to libfdt_env.h

Reviewed-by: Abner Chang <abner.chang@hpe.com>

-----Original Message-----
From: Schaefer, Daniel
Sent: Wednesday, May 19, 2021 10:58 PM
To: devel@edk2.groups.io
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
Leif
Lindholm <leif@nuviainc.com>; Ard Biesheuvel
<ard.biesheuvel@arm.com>;
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v1 1/1] EmbeddedPkg/libfdt: Add strmp and strncpy to
libfdt_env.h

OpenSBI has started using those in v0.9. See:
https://github.com/riscv/opensbi/blob/v0.9/lib/utils/fdt/fdt_domain.c

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
EmbeddedPkg/Include/libfdt_env.h | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/EmbeddedPkg/Include/libfdt_env.h
b/EmbeddedPkg/Include/libfdt_env.h
index 7feff52bc0fb..c35ac739703c 100644
--- a/EmbeddedPkg/Include/libfdt_env.h
+++ b/EmbeddedPkg/Include/libfdt_env.h
@@ -76,8 +76,16 @@ static inline size_t strnlen (const char* str, size_t
strsz ) {
return AsciiStrnLenS (str, strsz);

}



+static inline size_t strcmp (const char* str1, const char* str2) {

+ return AsciiStrCmp (str1, str2);

+}

+

static inline size_t strncmp (const char* str1, const char* str2, size_t strsz )
{

return AsciiStrnCmp (str1, str2, strsz);

}



+static inline size_t strncpy (char* dest, const char* source, size_t
dest_max) {

+ return AsciiStrCpyS (dest, dest_max, source);

+}

+

#endif /* _LIBFDT_ENV_H */

--
2.30.1




Re: [edk2-platforms PATCH v1 1/1] Platform/SiFive: Add VariablePolicyHelperLib to the dsc files

Abner Chang
 

Reviewed-by: Abner Chang <abner.chang@hpe.com>

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Takuto Naito
Sent: Tuesday, July 13, 2021 11:25 PM
To: devel@edk2.groups.io
Cc: Takuto Naito <naitaku@gmail.com>; Chang, Abner (HPS SW/FW
Technologist) <abner.chang@hpe.com>; Gilbert Chen
<gilbert.chen@hpe.com>; Schaefer, Daniel <daniel.schaefer@hpe.com>
Subject: [edk2-devel] [edk2-platforms PATCH v1 1/1] Platform/SiFive: Add
VariablePolicyHelperLib to the dsc files

REF:INVALID URI REMOVED.
cgi?id=3489__;!!NpxR!28wVbfpiJVaHlDPAeFb0ytViSTrcY-
e9p8QDrO0p4DRra6hFiM30xb3yR7kxe5Y$

Fix build error of U540 and U500 caused by BdsDxe.
The edk2 patch
MdeModulePkg/BdsDxe: Update BdsEntry to use Variable Policy
requires VariablePolicyHelperLib, but U500.dsc and U540.dsc
didn't have it in the LibraryClasses section.

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Takuto Naito <naitaku@gmail.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 1 +
.../SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 +
2 files changed, 2 insertions(+)

diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index b91823ceeb..2031265806 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -99,6 +99,7 @@
SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf

UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBoo
tManagerLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Va
riablePolicyHelperLib.inf

# RISC-V Platform Library
TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d
sc
b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.
dsc
index 0eafe29880..0262b2a909 100644
---
a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d
sc
+++
b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.
dsc
@@ -99,6 +99,7 @@
SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf

UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBoo
tManagerLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Va
riablePolicyHelperLib.inf

# RISC-V Platform Library
TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
--
2.32.0




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