Date   

Re: [PATCH] OvmfPkg/Bhyve: clean up TPM_ENABLE remnants

Michael D Kinney
 

Hi Laszlo,

I am trying the following configuration that is very conservative:

actions:
queue:
method: rebase
rebase_fallback: none
name: default

The auto rebase only attempts a strict rebase. If that attempt at a strict rebase fails
then it will show that there is a conflict that the developer must take care of.

I believe any combination of 2 PRs that have overlapping diff stat should fail
a strict rebase. The following link describes the method and rebase_fallback
settings in the queue command.

https://docs.mergify.io/actions/queue/#id2

I would be more concerned if we used a method of merge or a rebase_fallback of
merge.

Are there examples you can think of where the diff stat overlap and the strict
rebase will succeed?

Another option to consider is to define an additional 'auto-rebase' label that is
off by default to enable the auto rebase feature. By default the PR must be synced
with head when submitted. Only if a maintainer sets the 'auto-rebase' label will
an auto-rebase be attempted.

I also want to make it easy for non-maintainers to submit PRs and get CI test results.
So auto rebase may be useful for that use case. Perhaps the 'auto-rebase' label
can be considered when the 'push' label is also set.

Thanks,

Mike

-----Original Message-----
From: Laszlo Ersek <lersek@redhat.com>
Sent: Tuesday, June 22, 2021 8:17 AM
To: Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; spbrogan@outlook.com; ardb@kernel.org
Cc: Peter Grehan <grehan@freebsd.org>; Ard Biesheuvel <ardb+tianocore@kernel.org>; Justen, Jordan L
<jordan.l.justen@intel.com>; Sean Brogan <sean.brogan@microsoft.com>; Rebecca Cran <rebecca@bsdio.com>
Subject: Re: [edk2-devel] [PATCH] OvmfPkg/Bhyve: clean up TPM_ENABLE remnants

On 06/17/21 23:53, Kinney, Michael D wrote:
Hi Sean,

Mergify had added a queue feature to handle the rebases automatically and make sure
CI passes in the order that the PRs are being applied to the base branch.
I'm opposed to *unconditional* auto-rebase.

On one hand, it is indeed unreasonable to require a human to manually
rebase a "ShellPkg/Application/AcpiViewApp" series just because a series
for "SecurityPkg/FvReportPei" was merged a bit earlier. In other words,
merge requests for unrelated modules should not block each other.

On the other hand, auto-rebase is a bad idea if both series modify at
least one module in common (especially if both series modify at least
one *file* in common). In case there is a contextual conflict, even if
the conflict can be auto-resolved, and even if that resolution
*compiles*, it has to be reviewed by a human first.

I regularly use the git-range-diff command for this.

At Red Hat we've seen obscure bugs due to silent mis-merges (not in edk2
-- in different packages); such issues are difficult to debug.

Bisectability helps for sure, but only if the community treats
bisectability with high priority in the first place. (That is, if every
contributor builds their patch set at every stage, before submitting it
for review.)

Can we restrict the auto-rebase feature to such merge requests whose
cumulative diffstats do not intersect?

Thanks,
Laszlo


Re: [PATCH v1 0/5] EDK2 Code First: PI Specification: Update EFI_MM_COMMUNICATE_HEADER

Laszlo Ersek
 

On 06/18/21 11:37, Marvin Häuser wrote:
On 16.06.21 22:58, Kun Qin wrote:
On 06/16/2021 00:02, Marvin Häuser wrote:
2) Is it feasible yet with the current set of supported compilers to
support flexible arrays?
My impression is that flexible arrays are already supported (as seen
in UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h).
Please correct me if I am wrong.

Would you mind letting me know why this is applicable here? We are
trying to seek ideas on how to catch developer mistakes caused by this
change. So any input is appreciated.
Huh, interesting. Last time I tried I was told about incompatibilities
with MSVC, but I know some have been dropped since then (2005 and 2008
if I recall correctly?), so that'd be great to allow globally.
I too am surprised to see
"UnitTestFrameworkPkg/PrivateInclude/UnitTestFrameworkTypes.h". The
flexible array member is a C99 feature, and I didn't even know that we
disallowed it for the sake of particular VS toolchains -- I thought we
had a more general reason than just "not supported by VS versions X and Y".

The behavior of OFFSET_OF() would be interesting -- the OFFSET_OF()
macro definition for non-gcc / non-clang:

#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))

borders on undefined behavior as far as I can tell, so its behavior is
totally up to the compiler. It works thus far okay on Visual Studio, but
I couldn't say if it extended correctly to flexible array members.

Thanks
Laszlo

I feel
like if the structure is modified anyway, it should probably get a
trailing flexible array over the 1-sized hack. What do you think?


Re: [PATCH] OvmfPkg/Bhyve: clean up TPM_ENABLE remnants

Laszlo Ersek
 

On 06/17/21 23:53, Kinney, Michael D wrote:
Hi Sean,

Mergify had added a queue feature to handle the rebases automatically and make sure
CI passes in the order that the PRs are being applied to the base branch.
I'm opposed to *unconditional* auto-rebase.

On one hand, it is indeed unreasonable to require a human to manually
rebase a "ShellPkg/Application/AcpiViewApp" series just because a series
for "SecurityPkg/FvReportPei" was merged a bit earlier. In other words,
merge requests for unrelated modules should not block each other.

On the other hand, auto-rebase is a bad idea if both series modify at
least one module in common (especially if both series modify at least
one *file* in common). In case there is a contextual conflict, even if
the conflict can be auto-resolved, and even if that resolution
*compiles*, it has to be reviewed by a human first.

I regularly use the git-range-diff command for this.

At Red Hat we've seen obscure bugs due to silent mis-merges (not in edk2
-- in different packages); such issues are difficult to debug.

Bisectability helps for sure, but only if the community treats
bisectability with high priority in the first place. (That is, if every
contributor builds their patch set at every stage, before submitting it
for review.)

Can we restrict the auto-rebase feature to such merge requests whose
cumulative diffstats do not intersect?

Thanks,
Laszlo


Re: [edk2-platforms][PATCH V1 1/4] Silicon/ARM/NeoverseN1Soc: Add mem regions to support multi-chip usecase

Sami Mujawar
 

Hi Khasim,

I think this patch needs to be split. Also the commit message and the
code changes look out of place. Can you fix this, please?

From what I can see this patch includes the following changes:

- Fixes the missing function documentation. Thank you for that, but this
should be a separate patch.

- Defines new PCDs and configures the memory map.

Other than that one minor suggestion marked inline as [SAMI].

Regards,

Sami Mujawar


On 02/06/2021 01:46 PM, Khasim Mohammed via groups.io wrote:
This patch adds resource descriptor for multi-chip usecase and
introduces corresponding PCD definitions.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 30 ++++++-
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 28 ++++---
Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 10 +--
Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c | 18 ++---
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 43 ++++++++--
Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 84 +++++++++++++++++---
6 files changed, 172 insertions(+), 41 deletions(-)

diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index 54b793a937ff..8789795bbae3 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -1,5 +1,7 @@
+## @file
+# Describes the entire platform configuration.
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -33,8 +35,8 @@ [PcdsFixedAtBuild]
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000008
- gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000009
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000A
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000B
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000C
@@ -44,3 +46,25 @@ [PcdsFixedAtBuild]
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012
+
+ # CCIX
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027
+
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 166c9e044483..8e2154aadf47 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -1,6 +1,7 @@
## @file
+# Platform Library for N1Sdp.
#
-# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -29,13 +30,17 @@ [Sources.AARCH64]
AArch64/Helper.S | GCC

[FixedPcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
@@ -45,7 +50,12 @@ [FixedPcd]
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize

- gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress

[Guids]
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
index 097160c7e2d1..309a5c627845 100644
--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/

#ifndef NEOVERSEN1SOC_PLATFORM_H_
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 9332939f63eb..ac88415fd24c 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -1,10 +1,10 @@
/** @file
-* PCI Host Bridge Library instance for ARM Neoverse N1 platform
-*
-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ PCI Host Bridge Library instance for ARM Neoverse N1 platform
+
+ Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/

#include <PiDxe.h>
@@ -96,7 +96,7 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
/**
Return all the root bridge instances in an array.

- @param Count Return the count of root bridge instances.
+ @param Count Return the count of root bridge instances.

@return All the root bridge instances in an array.
The array should be passed into PciHostBridgeFreeRootBridges()
@@ -115,8 +115,8 @@ PciHostBridgeGetRootBridges (
/**
Free the root bridge instances array returned from PciHostBridgeGetRootBridges().

- @param Bridges The root bridge instances array.
- @param Count The count of the array.
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
**/
VOID
EFIAPI
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
index f722080e566b..d5ec0ff30d10 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/

#include <Library/ArmPlatformLib.h>
@@ -17,6 +17,12 @@ STATIC ARM_CORE_INFO mCoreInfoTable[] = {
{ 0x1, 0x1 } // Cluster 1, Core 1
};

+/**
+ Return the current Boot Mode.
+
+ This function returns the boot reason on the platform.
+
+**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
@@ -25,6 +31,15 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}

+/**
+ Initialize controllers that must be setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+ @param[in] MpId Processor ID
+
+**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
@@ -33,6 +48,15 @@ ArmPlatformInitialize (
return RETURN_SUCCESS;
}

+/**
+ Populate the Platform core information.
+
+ This function populates the ARM_MP_CORE_INFO_PPI with information about the cores.
+
+ @param[out] CoreCount Number of cores
+ @param[out] ArmCoreTable Table containing information about the cores
+
+**/
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
@@ -56,6 +80,15 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
}
};

+/**
+ Return the Platform specific PPIs
+
+ This function exposes the N1Sdp Specific PPIs.
+
+ @param[out] PpiListSize Size in Bytes of the Platform PPI List
+ @param[out] PpiList Platform PPI List
+
+**/
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index f9b3d037537d..ebdcf437599a 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -1,9 +1,9 @@
/** @file
-*
-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+
+ Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
**/

#include <Library/ArmPlatformLib.h>
@@ -13,7 +13,7 @@
#include <NeoverseN1Soc.h>

// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19

/**
Returns the Virtual Memory Map of the platform.
@@ -21,21 +21,23 @@
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
on your platform.

- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
- a Physical-to-Virtual Memory mapping. This array
- must be ended by a zero-filled entry.
+ @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing
+ a Physical-to-Virtual Memory mapping. This array
+ must be ended by a zero-filled entry.
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
)
{
- UINTN Index = 0;
+ UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT64 DramBlock2Size;
+ UINT64 RemoteDdrSize;

+ Index = 0;
PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
@@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap (
FixedPcdGet64 (PcdDramBlock2Base),
DramBlock2Size);

+ if (PlatInfo->MultichipMode == 1) {
+ RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * 1024UL * 1024UL * 1024UL);
[SAMI] Can SIZE_1GB be used instead of 1024UL*...?
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBase),
+ PcdGet64 (PcdSystemMemorySize)
+ );
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base),
+ RemoteDdrSize
+ );
+ }
+
ASSERT (VirtualMemoryMap != NULL);
Index = 0;

@@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

+ // CCIX RC Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixRootPortConfigBaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX ECAM Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdCcixBusMax) -
+ FixedPcdGet32 (PcdCcixBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX MMIO32 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixMmio32Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // CCIX MMIO64 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdCcixMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// SubSystem Pheripherals - UART0
VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE;
VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE;
@@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

+ if (PlatInfo->MultichipMode == 1) {
+ //Remote DDR (2GB)
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
+
+ //Remote DDR
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) +
+ PcdGet64 (PcdDramBlock2Base);
+ VirtualMemoryTable[Index].Length = RemoteDdrSize;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
+ }
+
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH] OvmfPkg/Bhyve: Remove Xen remnants

Laszlo Ersek
 

On 06/12/21 23:07, Rebecca Cran wrote:
Several Xen remnants were left over from adapting the Ovmf code for
Bhyve. Remove them.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
---
OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h | 7 -------
OvmfPkg/Bhyve/BhyveX64.dsc | 1 -
OvmfPkg/Bhyve/PlatformPei/Platform.h | 17 -----------------
3 files changed, 25 deletions(-)

diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h b/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h
index 994ee2c7cd..87c9bdafba 100644
--- a/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h
+++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h
@@ -18,7 +18,6 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
-#include <Library/XenPlatformLib.h>
#include <IndustryStandard/Acpi.h>

typedef struct {
@@ -46,12 +45,6 @@ BhyveInstallAcpiTable(
OUT UINTN *TableKey
);

-EFI_STATUS
-EFIAPI
-InstallXenTables (
- IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol
- );
-
EFI_STATUS
EFIAPI
InstallAcpiTables (
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index d8792812ab..25420d8261 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -219,7 +219,6 @@
S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
- XenPlatformLib|OvmfPkg/Library/XenPlatformLib/XenPlatformLib.inf


!if $(TPM_ENABLE) == TRUE
diff --git a/OvmfPkg/Bhyve/PlatformPei/Platform.h b/OvmfPkg/Bhyve/PlatformPei/Platform.h
index 8239ca05ac..e0327202a5 100644
--- a/OvmfPkg/Bhyve/PlatformPei/Platform.h
+++ b/OvmfPkg/Bhyve/PlatformPei/Platform.h
@@ -98,28 +98,11 @@ InstallClearCacheCallback (
VOID
);

-EFI_STATUS
-InitializeXen (
- VOID
- );
-
-BOOLEAN
-XenDetect (
- VOID
- );
-
VOID
AmdSevInitialize (
VOID
);

-extern BOOLEAN mXen;
-
-VOID
-XenPublishRamRegions (
- VOID
- );
-
extern EFI_BOOT_MODE mBootMode;

extern BOOLEAN mS3Supported;
(1) If we go for simple "xen" matches in source code, this looks mostly
okay, although I see two comments that could be fixed up additionally, in
- PlatformPei/Platform.c
- SmbiosPlatformDxe/SmbiosPlatformDxe.c

(pathnames relative to OvmfPkg/Bhyve)


(2) I hinted at a larger possible cleanup in commit e43cca74ad02
("OvmfPkg/Bhyve: make "PcdPciDisableBusEnumeration" Fixed-at-Build",
2021-06-04).

If you locate "PcdPciDisableBusEnumeration" instances under
OvmfPkg/Bhyve, and substitute constant TRUE for them, a bunch of already
dead code in OvmfPkg/Bhyve/AcpiPlatformDxe is *shown dead* too, and you
can excise it.

That does not make this patch wrong, of course.

Thanks
Laszlo


Re: [edk2-platforms][PATCH V1 2/4] Platform/ARM/N1Sdp: Introduce platform DXE driver

Sami Mujawar
 

Hi Khasim,

I can see that some changes to the PlatformDxe are in the last patch of
this series. Do they belong here?

Other than that, please find my response inline marked [SAMI].

Regards,

Sami Mujawar


On 02/06/2021 01:46 PM, Khasim Mohammed via groups.io wrote:
Add an initial platform DXE driver and support for ramdisk devices.

Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf | 44 +++++++++++++++++
Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c | 51 ++++++++++++++++++++
2 files changed, 95 insertions(+)

diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 000000000000..925bde4063cc
--- /dev/null
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,44 @@
+## @file
+# Platform DXE driver for N1Sdp
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 11fc8b5a-377d-47a8-aee9-0093d3d3407f
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmN1SdpEntryPoint
+
+[Sources.common]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
+
+[LibraryClasses]
+ HobLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiRamDiskProtocolGuid
+
+[FeaturePcd]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported
+
+[FixedPcd]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize
+
+[Depex]
+ gEfiRamDiskProtocolGuid
diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 000000000000..e0b89556d40d
--- /dev/null
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/RamDisk.h>
+
+/**
+ Entrypoint of Platform Dxe Driver
+
+ @param ImageHandle[in] The firmware allocated handle for the EFI image.
+ @param SystemTable[in] A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+**/
+EFI_STATUS
+EFIAPI
+ArmN1SdpEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_RAM_DISK_PROTOCOL *RamDisk;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = EFI_UNSUPPORTED;
+ if (FeaturePcdGet (PcdRamDiskSupported)) {
+ Status = gBS->LocateProtocol (&gEfiRamDiskProtocolGuid, NULL, (VOID**) &RamDisk);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Couldn't find the RAM Disk protocol - %r\n", __FUNCTION__, Status));
+ return Status;
+ }
+
+ Status = RamDisk->Register (
+ (UINTN)PcdGet32(PcdRamDiskBase),
+ (UINTN)PcdGet32(PcdRamDiskSize),
[SAMI] Space needed between PcdGet32 and opening bracket. Please check
at other places in this patch series.
+ &gEfiVirtualCdGuid,
+ NULL,
+ &DevicePath);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to register RAM Disk - %r\n", __FUNCTION__, Status));
+ }
+ }
+ return Status;
+}
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH v1 1/1] ArmPlatformPkg/Scripts: Create add-symbol-file commands from UEFI console

PierreGondois
 

Hello,
I tested this patch on the ArmVExpress-FVP-AArch64 platform with DS-5,
Regards,
Pierre


Re: [edk2-platforms][PATCH V1 3/4] Platform/ARM/N1Sdp: Enable N1Sdp platform specific configurations

Sami Mujawar
 

Hi Khasim,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar


On 02/06/2021 01:47 PM, Khasim Mohammed via groups.io wrote:
This patch updates the fdf file and introduces component
description and configuration files for N1Sdp.

Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 90 ++++++++++++++++++++
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 28 +++++-
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 13 ++-
3 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
new file mode 100644
index 000000000000..4b730d728eaf
--- /dev/null
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -0,0 +1,90 @@
+## @file
+# Describes the N1Sdp configuration.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = N1SdpPlatform
+ PACKAGE_GUID = 29aacb23-61e8-4fe2-8a06-793537cd26e9
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+
+[LibraryClasses]
+ ArmPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+
+[Guids.common]
+ gArmN1SdpTokenSpaceGuid = { 0xd8f1624a, 0x98c1, 0x4f64, { 0xa6, 0x41, 0x19, 0x5e, 0xb5, 0x3b, 0x26, 0x0f } }
+
+[PcdsFixedAtBuild]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
+
+ # External memory
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
+
+[PcdsFeatureFlag.common]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000003
+
+[PcdsFixedAtBuild.common]
+ # CoreSight Debug and Trace components
+ # CoreSight ETMs
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0Base|0x402040000|UINT64|0x0000002D
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0MaxBase|0x402040FFF|UINT64|0x0000002E
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1Base|0x402140000|UINT64|0x0000002F
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1MaxBase|0x402140FFF|UINT64|0x00000030
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2Base|0x403040000|UINT64|0x00000031
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2MaxBase|0x403040FFF|UINT64|0x00000032
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3Base|0x403140000|UINT64|0x00000033
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3MaxBase|0x403140FFF|UINT64|0x00000034
+
+ # CoreSight TMC (ETRs/ETFs/ETBs)
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0Base|0x400410000|UINT64|0x00000035
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0MaxBase|0x400410FFF|UINT64|0x00000036
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1Base|0x400420000|UINT64|0x00000037
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1MaxBase|0x400420FFF|UINT64|0x00000038
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2Base|0x400010000|UINT64|0x00000039
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2MaxBase|0x400010FFF|UINT64|0x0000003A
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrBase|0x400120000|UINT64|0x00000043
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrMaxBase|0x400120FFF|UINT64|0x00000044
+
+ # CoreSight Dynamic Funnel(s)
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0Base|0x4000B0000|UINT64|0x0000003B
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0MaxBase|0x4000B0FFF|UINT64|0x0000003C
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1Base|0x4000A0000|UINT64|0x0000003D
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1MaxBase|0x4000A0FFF|UINT64|0x0000003E
+
+ # CoreSight Dynamic Replicator(s)
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorBase|0x400110000|UINT64|0x0000003F
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorMaxBase|0x400110FFF|UINT64|0x00000040
+
+ # CoreSight TPIU
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuBase|0x400130000|UINT64|0x00000041
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase|0x400130FFF|UINT64|0x00000042
+
+ # CoreSight STM and STM Stimulus
+ gArmN1SdpTokenSpaceGuid.PcdCsStmBase|0x400800000|UINT64|0x00000045
+ gArmN1SdpTokenSpaceGuid.PcdCsStmMaxBase|0x400800FFF|UINT64|0x00000046
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusBase|0x4D000000|UINT32|0x00000047
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusSize|0x1000000|UINT32|0x00000048
+
+ # CoreSight Components' Size
+ #
+ # Newton TRMs specify the size for these coresight components as 64K.
+ # The actual size is just 4K though 64K is reserved. Access to the
+ # unmapped reserved region results in a DECERR response.
+ #
+ gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 61e7a909f80d..abfcbe534550 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -1,8 +1,11 @@
+## @file
+# Component description file specific for N1Sdp
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
+##

################################################################################
#
@@ -33,6 +36,9 @@ [LibraryClasses.common]
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf

+ # Ramdisk Support
[SAMI] Mismatched comment ?
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+
[LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -71,6 +77,9 @@ [LibraryClasses.common.DXE_DRIVER]
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+!endif

[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -82,11 +91,16 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, Libr
################################################################################

[PcdsFeatureFlag.common]
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSupported|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE

[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdVFPEnabled|1

+ # RAM Disk
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000
+ gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000
+
# Stacks for MPCores in Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
@@ -99,6 +113,9 @@ [PcdsFixedAtBuild.common]
# Secondary DDR memory
gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0x8080000000

+ # External memory
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000
+
# GIC Base Addresses
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
@@ -198,6 +215,9 @@ [Components.common]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}

+ # Platform driver
+ Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
+
# Human Interface Support
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

@@ -236,6 +256,9 @@ [Components.common]
# SATA Controller
MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

+ # NVMe boot devices
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
# Usb Support
MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
@@ -244,3 +267,6 @@ [Components.common]
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ # RAM Disk
+ MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
index c4e1f7b4b8fc..6b097438adaf 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
@@ -1,8 +1,10 @@
+## @file
+# FDF file of N1Sdp
#
-# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+##

################################################################################
#
@@ -109,6 +111,9 @@ [FV.FvMain]
# SATA Controller
INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

+ # NVMe boot devices
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
# Usb Support
INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
@@ -137,10 +142,14 @@ [FV.FvMain]

# FV FileSystem
INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+ INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf

# UEFI applications
INF ShellPkg/Application/Shell/Shell.inf

+ # Platform driver
+ INF Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
+
# Bds
INF MdeModulePkg/Application/UiApp/UiApp.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [edk2-platforms][PATCH V1 4/4] Platform/ARM/N1Sdp: Configuration Manager for N1Sdp

Sami Mujawar
 

Hi Khasim,

This patch really needs to be split as it is too large to review. Also,
some changes don't look relevant to the commit message or the subject of
the patch, e.g PlatformDxe changes.

Other than that, please find my response inline marked [SAMI].

Regards,

Sami Mujawar


On 02/06/2021 01:47 PM, Khasim Mohammed via groups.io wrote:
The dynamic tables framework utilizes the configuration manager
protocol to get the platform specific information required for
building the firmware tables.

The configuration manager is a platform specific component that
collates the platform hardware information and builds an abstract
platform configuration repository. The configuration manager also
implements the configuration manager protocol which returns the
hardware information requested by the table generators.

This patch implements the configuration manager for N1SDP
platform. It enables support for generating the following
ACPI tables:
1. FACP
2. DSDT
3. GTDT
4. APIC
5. SPCR
6. DBG2
7. PPTT
8. IORT
9. MCFG
10. SSDT - PCI
11. SSDT - REMOTE PCI

Also added :
ACPI bindings for CoreSight components.
Support for Arm CMN-600 PMU
HMAT table and expose CCIX memory as EFI_MEMORY_SP

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Signed-off-by: anukou01 <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
---
Platform/ARM/N1Sdp/N1SdpPlatform.dec | 10 +
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 5 +
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc | 16 +
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 10 +
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 9 +
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf | 167 ++
Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf | 4 +
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 307 +++
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h | 92 +
Platform/ARM/N1Sdp/Include/N1SdpAcpiHeader.h | 35 +
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 2197 ++++++++++++++++++++
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c | 103 +
Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c | 1 +
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl | 477 +++++
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl | 247 +++
Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl | 156 ++
16 files changed, 3836 insertions(+)

diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
index 4b730d728eaf..a6f982c7af3f 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -22,17 +22,22 @@ [Defines]
#
################################################################################
[Includes.common]
+ Include # Root include for the package

[LibraryClasses]
ArmPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf

[Guids.common]
gArmN1SdpTokenSpaceGuid = { 0xd8f1624a, 0x98c1, 0x4f64, { 0xa6, 0x41, 0x19, 0x5e, 0xb5, 0x3b, 0x26, 0x0f } }
+ gN1SdpAcpiTableFileGuid = { 0x9af67d31, 0x7de8, 0x4a71, { 0xa9, 0xa8, 0xa5, 0x97, 0xa2, 0x76, 0x59, 0xce } }
[SAMI] I don't think the gN1SdpAcpiTableFileGuid would be needed when
Dynamic Tables Framework is used. Can you explain why this is added
here, please?
[/SAMI]

[PcdsFixedAtBuild]
gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002

+ # PCIe
+ gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
+
# External memory
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029

@@ -88,3 +93,8 @@ [PcdsFixedAtBuild.common]
# unmapped reserved region results in a DECERR response.
#
gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049
+
+ # Remote Chip PCIe
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index 8789795bbae3..eea2d58402e6 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -68,3 +68,8 @@ [PcdsFixedAtBuild]
gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027

gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029
+
+ # Remote Chip PCIe
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B
+ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
new file mode 100644
index 000000000000..bcd4bf334dad
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
@@ -0,0 +1,16 @@
+## @file
+# dsc include file for Configuration Manager
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+[BuildOptions]
+
+[Components.common]
+ # Configuration Manager
+ Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index abfcbe534550..14769659ddf5 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -27,6 +27,9 @@ [Defines]
!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
!include MdePkg/MdeLibs.dsc.inc

+!include DynamicTablesPkg/DynamicTables.dsc.inc
+!include Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
+
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
@@ -156,6 +159,9 @@ [PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdCoreCount|2
gArmPlatformTokenSpaceGuid.PcdClusterCount|2

+ # ACPI Table Version
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
# Runtime Variable storage
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
@@ -215,6 +221,10 @@ [Components.common]
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}

+ # ACPI Support
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
# Platform driver
Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf

diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
index 6b097438adaf..6ede2b7fc894 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
@@ -94,6 +94,15 @@ [FV.FvMain]
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

+ # ACPI Support
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ # Configuration Manager
+ INF Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+
+ # Dynamic Table fdf
+ !include DynamicTablesPkg/DynamicTables.fdf.inc
+
# Human Interface Support
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
new file mode 100644
index 000000000000..52207e7f7d26
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -0,0 +1,167 @@
+## @file
+# Configuration Manager Dxe
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ConfigurationManagerDxe
+ FILE_GUID = 6f9c3b47-6f7d-44b6-87e5-4b7f44a60147
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ConfigurationManagerDxeInitialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ AslTables/Dsdt.asl
+ AslTables/SsdtPci.asl
+ AslTables/SsdtRemotePci.asl
+ ConfigurationManager.c
+ ConfigurationManager.h
+ Hmat.c
+ Platform.h
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/N1Sdp/N1SdpPlatform.dec
+ Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+
+[LibraryClasses]
+ ArmPlatformLib
+ PrintLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+
+[Protocols]
+ gEdkiiConfigurationManagerProtocolGuid
+
+[FixedPcd]
+ # PL011 Serial Debug UART
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ # SBSA Generic Watchdog
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+
+ gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
+
+ gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
+ gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ #PCIe
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+
+ # CCIX
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+
+ # Coresight
+ gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf0MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf1MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtf2MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm0MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm1MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm2MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3Base
+ gArmN1SdpTokenSpaceGuid.PcdCsEtm3MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrBase
+ gArmN1SdpTokenSpaceGuid.PcdCsEtrMaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0Base
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel0MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1Base
+ gArmN1SdpTokenSpaceGuid.PcdCsFunnel1MaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorBase
+ gArmN1SdpTokenSpaceGuid.PcdCsReplicatorMaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsStmBase
+ gArmN1SdpTokenSpaceGuid.PcdCsStmMaxBase
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusBase
+ gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusSize
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuBase
+ gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
+
+ # Remote PCIe
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
+ gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
+
+[Depex]
+ TRUE
diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
index 925bde4063cc..55325327298b 100644
--- a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf
@@ -27,9 +27,13 @@ [Packages]
Platform/ARM/N1Sdp/N1SdpPlatform.dec

[LibraryClasses]
+ AcpiLib
[SAMI] I may be missing somthing here, where is AcpiLib used in this module?
HobLib
UefiDriverEntryPoint

+[Guids]
+ gN1SdpAcpiTableFileGuid
[SAMI] Is this needed here?
[/SAMI]
+
[Protocols]
gEfiRamDiskProtocolGuid

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
new file mode 100644
index 000000000000..52e7680cd34d
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -0,0 +1,307 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#ifndef CONFIGURATION_MANAGER_H_
+#define CONFIGURATION_MANAGER_H_
+
+/** C array containing the compiled AML template.
+ This symbol is defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 dsdt_aml_code[];
+extern CHAR8 ssdtpci_aml_code[];
+extern CHAR8 ssdtremotepci_aml_code[];
+
+/** The configuration manager version.
+*/
+#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0)
+
+/** The OEM ID
+*/
+#define CFG_MGR_OEM_ID { 'A', 'R', 'M', 'L', 'T', 'D' }
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&N1sdpRepositoryInfo + \
+ OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field))
+
+/** A helper macro that constructs the MPID based on the
+ Aff0, Aff1, Aff2, Aff3 values
+*/
+#define GET_MPID3(Aff3, Aff2, Aff1, Aff0) \
+ (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0))
+
+/** A helper macro for populating the GIC CPU information
+*/
+#define GICC_ENTRY( \
+ CPUInterfaceNumber, \
+ Mpidr, \
+ PmuIrq, \
+ VGicIrq, \
+ GicRedistBase, \
+ EnergyEfficiency, \
+ SpeIrq, \
+ ProximityDomain, \
+ ClockDomain \
+ ) { \
+ CPUInterfaceNumber, /* UINT32 CPUInterfaceNumber */ \
+ CPUInterfaceNumber, /* UINT32 AcpiProcessorUid */ \
+ EFI_ACPI_6_2_GIC_ENABLED, /* UINT32 Flags */ \
+ 0, /* UINT32 ParkingProtocolVersion */ \
+ PmuIrq, /* UINT32 PerformanceInterruptGsiv */ \
+ 0, /* UINT64 ParkedAddress */ \
+ FixedPcdGet64 ( \
+ PcdGicInterruptInterfaceBase \
+ ), /* UINT64 PhysicalBaseAddress */ \
+ 0, /* UINT64 GICV */ \
+ 0, /* UINT64 GICH */ \
+ VGicIrq, /* UINT32 VGICMaintenanceInterrupt */ \
+ GicRedistBase, /* UINT64 GICRBaseAddress */ \
+ Mpidr, /* UINT64 MPIDR */ \
+ EnergyEfficiency, /* UINT8 ProcessorPowerEfficiencyClass*/ \
+ SpeIrq, /* UINT16 SpeOverflowInterrupt */ \
+ ProximityDomain, /* UINT32 ProximityDomain */ \
+ ClockDomain, /* UINT32 ClockDomain */ \
+ EFI_ACPI_6_3_GICC_ENABLED,/* UINT32 Flags */ \
+ }
+
+/** A helper macro for populating the Processor Hierarchy Node flags
+*/
+#define PROC_NODE_FLAGS( \
+ PhysicalPackage, \
+ AcpiProcessorIdValid, \
+ ProcessorIsThread, \
+ NodeIsLeaf, \
+ IdenticalImplementation \
+ ) \
+ ( \
+ PhysicalPackage | \
+ (AcpiProcessorIdValid << 1) | \
+ (ProcessorIsThread << 2) | \
+ (NodeIsLeaf << 3) | \
+ (IdenticalImplementation << 4) \
+ )
+
+/** A helper macro for populating the Cache Type Structure's attributes
+*/
+#define CACHE_ATTRIBUTES( \
+ AllocationType, \
+ CacheType, \
+ WritePolicy \
+ ) \
+ ( \
+ AllocationType | \
+ (CacheType << 2) | \
+ (WritePolicy << 4) \
+ )
+
+/** A function that prepares Configuration Manager Objects for returning.
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object.
+ @param [out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ );
+
+/** The number of CPUs
+*/
+#define PLAT_CPU_COUNT 4
+
+/** The number of ACPI tables to install
+*/
+#define PLAT_ACPI_TABLE_COUNT 13
+
+/** The number of platform generic timer blocks
+*/
+#define PLAT_GTBLOCK_COUNT 1
+
+/** The number of timer frames per generic timer block
+*/
+#define PLAT_GTFRAME_COUNT 2
+
+/** The number of Processor Hierarchy Nodes
+ - one package node
+ - two cluster nodes
+ - two cores in cluster 0
+ - two cores in cluster 1
+*/
+#define PLAT_PROC_HIERARCHY_NODE_COUNT 7
+
+/** The number of unique cache structures:
+ - cluster L3 unified cache
+ - core L1 instruction cache
+ - core L1 data cache
+ - core L2 cache
+ - slc unified cache
+*/
+#define PLAT_CACHE_COUNT 5
+
+/** The number of resources private to the cluster
+ - L3 cache
+*/
+#define CLUSTER_RESOURCE_COUNT 1
+
+/** The number of resources private to 'core instance
+ - L1 data cache
+ - L1 instruction cache
+*/
+#define CORE_RESOURCE_COUNT 2
+
+/** The number of resources private to SoC
+ - slc cache
+*/
+#define SOC_RESOURCE_COUNT 1
+
+/** Number of memory affinity entries
+*/
+#define LOCAL_DDR_REGION1 0
+#define LOCAL_DDR_REGION2 1
+#define REMOTE_DDR_REGION1 2
+#define REMOTE_DDR_REGION2 3
+#define DDR_REGION_COUNT 4
+
+enum {
+ ITS_SMMU_CCIX = 0,
+ ITS_SMMU_PCIE,
+ ITS_CCIX,
+ ITS_PCIE,
+ ITS_MASTER_CHIP_MAX,
+ ITS_REMOTE_SMMU_PCIE = ITS_MASTER_CHIP_MAX,
+ ITS_REMOTE_PCIE,
+ ITS_MAX
+};
[SAMI] Enums should be typedefed. Same comment for the other enums
defined in this file.
[/SAMI]
+
+enum {
+ SMMUV3INFO_PCIE = 0,
+ SMMUV3INFO_CCIX,
+ SMMUV3INFO_MASTER_CHIP_MAX,
+ SMMUV3INFO_REMOTE_PCIE = SMMUV3INFO_MASTER_CHIP_MAX,
+ SMMUV3INFO_MAX
+};
+
+enum {
+ ROOT_PCIE = 0,
+ ROOT_PCIE_CCIX,
+ ROOT_PCIE_MASTER_CHIP_MAX,
+ ROOT_REMOTE_PCIE = ROOT_PCIE_MASTER_CHIP_MAX,
+ ROOT_PCIE_MAX
+};
+
+enum {
+ DEVICEIDMAPPING_SMMU_PCIE = 0,
+ DEVICEIDMAPPING_SMMU_CCIX,
+ DEVICEIDMAPPING_PCIE,
+ DEVICEIDMAPPING_MASTER_CHIP_MAX,
+ DEVICEIDMAPPING_REMOTE_SMMU_PCIE = DEVICEIDMAPPING_MASTER_CHIP_MAX,
+ DEVICEIDMAPPING_REMOTE_PCIE,
+ DEVICEIDMAPPING_MAX,
+};
+
+/** A structure describing the platform configuration
+ manager repository information
+*/
+typedef struct PlatformRepositoryInfo {
+ /// Configuration Manager Information
+ CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo;
+
+ /// List of ACPI tables
+ CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+
+ /// Boot architecture information
+ CM_ARM_BOOT_ARCH_INFO BootArchInfo;
+
+ /// Fixed feature flag information
+ CM_ARM_FIXED_FEATURE_FLAGS FixedFeatureFlags;
+
+ /// Power management profile information
+ CM_ARM_POWER_MANAGEMENT_PROFILE_INFO PmProfileInfo;
+
+ /// GIC CPU interface information
+ CM_ARM_GICC_INFO GicCInfo[PLAT_CPU_COUNT * 2];
+
+ /// GIC distributor information
+ CM_ARM_GICD_INFO GicDInfo;
+
+ /// GIC Redistributor information
+ CM_ARM_GIC_REDIST_INFO GicRedistInfo[2];
+
+ /// GIC ITS information
+ CM_ARM_GIC_ITS_INFO GicItsInfo[ITS_MAX];
+
+ /// Generic timer information
+ CM_ARM_GENERIC_TIMER_INFO GenericTimerInfo;
+
+ /// Generic timer block information
+ CM_ARM_GTBLOCK_INFO GTBlockInfo[PLAT_GTBLOCK_COUNT];
+
+ /// Generic timer frame information
+ CM_ARM_GTBLOCK_TIMER_FRAME_INFO GTBlock0TimerInfo[PLAT_GTFRAME_COUNT];
+
+ /// Watchdog information
+ CM_ARM_GENERIC_WATCHDOG_INFO Watchdog;
+
+ /** Serial port information for the
+ serial port console redirection port
+ */
+ CM_ARM_SERIAL_PORT_INFO SpcrSerialPort;
+
+ /// Serial port information for the DBG2 UART port
+ CM_ARM_SERIAL_PORT_INFO DbgSerialPort;
+
+ // Processor topology information
+ CM_ARM_PROC_HIERARCHY_INFO ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT * 2];
+
+ // Cache information
+ CM_ARM_CACHE_INFO CacheInfo[PLAT_CACHE_COUNT];
+
+ // Cluster private resources
+ CM_ARM_OBJ_REF ClusterResources[CLUSTER_RESOURCE_COUNT];
+
+ // Core private resources
+ CM_ARM_OBJ_REF CoreResources[CORE_RESOURCE_COUNT];
+
+ // SoC Resources
+ CM_ARM_OBJ_REF SocResources[SOC_RESOURCE_COUNT];
+
+ /// ITS Group node
+ CM_ARM_ITS_GROUP_NODE ItsGroupInfo[ITS_MAX];
+
+ /// ITS Identifier array
+ CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[ITS_MAX];
+
+ /// SMMUv3 node
+ CM_ARM_SMMUV3_NODE SmmuV3Info[SMMUV3INFO_MAX];
+
+ /// PCI Root complex node
+ CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[ROOT_PCIE_MAX];
+
+ /// Array of DeviceID mapping
+ CM_ARM_ID_MAPPING DeviceIdMapping[DEVICEIDMAPPING_MAX][2];
+
+ /// PCI configuration space information
+ CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[ROOT_PCIE_MAX];
+
+ /// Memory Affinity Info
+ CM_ARM_MEMORY_AFFINITY_INFO MemAffInfo[DDR_REGION_COUNT];
+
+} EDKII_PLATFORM_REPOSITORY_INFO;
+
+#endif // CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h
new file mode 100644
index 000000000000..a4a1d8504ffc
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h
@@ -0,0 +1,92 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_H_
+#define PLATFORM_H_
+
+#define ENABLE_MEM_MAPPED_TIMER
+
+#ifdef ENABLE_MEM_MAPPED_TIMER
+// REFCLK CNTControl
+#define N1Sdp_SYSTEM_TIMER_BASE_ADDRESS 0x2A430000
[SAMI] Macro names should all be in capital letters. Same comment for
other macros defined and used in this patch series.
[/SAMI]
+// REFCLK CNTRead
+#define N1Sdp_CNT_READ_BASE_ADDRESS 0x2A800000
+#else
+#define N1Sdp_SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#define N1Sdp_CNT_READ_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+// GT Block Timer
+// AP_REFCLK CNTCTL
+#define N1Sdp_GT_BLOCK_CTL_BASE 0x2A810000
+#define N1Sdp_TIMER_FRAMES_COUNT 2
+
+// GT Block Timer Frames
+// AP_REFCLK_S CNTBase0
+#define N1Sdp_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000
+#define N1Sdp_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
+#define N1Sdp_GT_BLOCK_FRAME0_GSIV 92
+
+// AP_REFCLK_NS CNTBase1
+#define N1Sdp_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000
+#define N1Sdp_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
+#define N1Sdp_GT_BLOCK_FRAME1_GSIV 91
+
+#define GTDT_TIMER_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_SAVE_CONTEXT \
+ EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_LOSE_CONTEXT 0
+
+#define N1Sdp_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | \
+ GTDT_TIMER_ACTIVE_LOW | \
+ GTDT_TIMER_LEVEL_TRIGGERED)
+
+// GT Block Timer Flags
+#define GTX_TIMER_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED 0
+#define GTX_TIMER_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH 0
+
+#define N1Sdp_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | \
+ GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE 0
+#define GTX_TIMER_SAVE_CONTEXT \
+ EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT 0
+
+#define N1Sdp_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | \
+ GTX_TIMER_SECURE)
+#define N1Sdp_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | \
+ GTX_TIMER_NON_SECURE)
+
+// Watchdog
+#define SBSA_WATCHDOG_EDGE_TRIGGERED \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
+#define SBSA_WATCHDOG_ACTIVE_LOW \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH 0
+#define SBSA_WATCHDOG_SECURE \
+ EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE 0
+
+#define N1Sdp_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | \
+ SBSA_WATCHDOG_ACTIVE_HIGH | \
+ SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+#endif // PLATFORM_H_
diff --git a/Platform/ARM/N1Sdp/Include/N1SdpAcpiHeader.h b/Platform/ARM/N1Sdp/Include/N1SdpAcpiHeader.h
new file mode 100644
index 000000000000..e0ea26893810
--- /dev/null
+++ b/Platform/ARM/N1Sdp/Include/N1SdpAcpiHeader.h
@@ -0,0 +1,35 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef N1Sdp_ACPI_HEADER_
+#define N1Sdp_ACPI_HEADER_
[SAMI] File include guard must be in all capital letters.
[/SAMI]
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','N','1','S','D','P') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION 0x20181101
+#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#endif /* N1Sdp_ACPI_HEADER_ */
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
new file mode 100644
index 000000000000..fb264ba783af
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -0,0 +1,2197 @@
+/** @file
+ Configuration Manager Dxe
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <NeoverseN1Soc.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManager.h"
+#include "N1SdpAcpiHeader.h"
+#include "Platform.h"
+
+extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
+
+/** The platform configuration repository information.
+*/
+STATIC
+EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
+ // Configuration Manager information
+ { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID },
+
+ // ACPI Table List
+ {
+ // FADT Table
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
+ NULL
+ },
+ // GTDT Table
+ {
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
+ NULL
+ },
+ // MADT Table
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
+ NULL
+ },
+ // SPCR Table
+ {
+ EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
+ NULL
+ },
+ // DSDT Table
+ {
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)dsdt_aml_code
+ },
+ // DBG2 Table
+ {
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
+ NULL
+ },
+ // PPTT Table
+ {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
+ NULL
+ },
+ // IORT Table
+ {
+ EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
+ NULL
+ },
+ // PCI MCFG Table
+ {
+ EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
+ NULL,
+ SIGNATURE_64 ('A','R','M','N','1','S','D','P'),
+ 0x20181101
+ },
+ // SSDT table describing the PCI root complex
+ {
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
+ },
+ // SRAT Table
+ {
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSrat),
+ NULL
+ },
+ // HMAT Table
+ {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdRaw),
+ (EFI_ACPI_DESCRIPTION_HEADER*)&Hmat
+ },
+ // SSDT table describing the Remote Chip PCI root complex
+ {
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)ssdtremotepci_aml_code
+ },
+ },
+
+ // Boot architecture information
+ { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags
+
+ // Fixed feature flag information
+ { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags
+
+ // Power management profile information
+ { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile
+
+ /* GIC CPU Interface information
+ GICC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase,
+ EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain)
+ */
+ {
+ GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+ GICC_ENTRY (4, GET_MPID3 (0x1, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 1, 0),
+ GICC_ENTRY (5, GET_MPID3 (0x1, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 1, 0),
+ GICC_ENTRY (6, GET_MPID3 (0x1, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 1, 0),
+ GICC_ENTRY (7, GET_MPID3 (0x1, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 1, 0),
+ },
+
+ // GIC Distributor Info
+ {
+ FixedPcdGet64 (PcdGicDistributorBase), // UINT64 PhysicalBaseAddress
+ 0, // UINT32 SystemVectorBase
+ 3 // UINT8 GicVersion
+ },
+
+ // GIC Re-Distributor Info
+ {
+ {
+ // UINT64 DiscoveryRangeBaseAddress
+ FixedPcdGet64 (PcdGicRedistributorsBase),
+ // UINT32 DiscoveryRangeLength
+ SIZE_1MB
+ },
+ {
+ // UINT64 DiscoveryRangeBaseAddress
+ FixedPcdGet64 (PcdGicRedistributorsBase) + (1ULL << 42),
+ // UINT32 DiscoveryRangeLength
+ SIZE_1MB
+ },
+ },
+
+ // GIC ITS
+ {
+ // GIC ITS - CCIX TCU
+ {
+ // The GIC ITS ID.
+ 0,
+ // The physical address for the Interrupt Translation Service
+ 0x30040000,
+ //Proximity Domain
+ 0
+ },
+ // GIC ITS - PCIe TCU
+ {
+ // The GIC ITS ID.
+ 1,
+ // The physical address for the Interrupt Translation Service
+ 0x30060000,
+ //Proximity Domain
+ 0
+ },
+ // GIC ITS - CCIX RC
+ {
+ // The GIC ITS ID.
+ 2,
+ // The physical address for the Interrupt Translation Service
+ 0x30080000,
+ //Proximity Domain
+ 0
+ },
+ // GIC ITS - PCIe RC
+ {
+ // The GIC ITS ID.
+ 3,
+ // The physical address for the Interrupt Translation Service
+ 0x300A0000,
+ //Proximity Domain
+ 0
+ },
+ //Remote chip GIC ITS - PCIe TCU
+ {
+ ITS_REMOTE_SMMU_PCIE,
+ 0x40030060000,
+ 1
+ },
+ //Remote chip GIC ITS - PCIe RC
+ {
+ ITS_REMOTE_PCIE,
+ 0x400300a0000,
+ 1
+ },
+ },
+
+ // Generic Timer Info
+ {
+ // The physical base address for the counter control frame
+ N1Sdp_SYSTEM_TIMER_BASE_ADDRESS,
+ // The physical base address for the counter read frame
+ N1Sdp_CNT_READ_BASE_ADDRESS,
+ // The secure PL1 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum),
+ // The secure PL1 timer flags
+ N1Sdp_GTDT_GTIMER_FLAGS,
+ // The non-secure PL1 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerIntrNum),
+ // The non-secure PL1 timer flags
+ N1Sdp_GTDT_GTIMER_FLAGS,
+ // The virtual timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),
+ // The virtual timer flags
+ N1Sdp_GTDT_GTIMER_FLAGS,
+ // The non-secure PL2 timer interrupt
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum),
+ // The non-secure PL2 timer flags
+ N1Sdp_GTDT_GTIMER_FLAGS
+ },
+
+ // Generic Timer Block Information
+ {
+ {
+ // The physical base address for the GT Block Timer structure
+ N1Sdp_GT_BLOCK_CTL_BASE,
+ // The number of timer frames implemented in the GT Block
+ N1Sdp_TIMER_FRAMES_COUNT,
+ // Reference token for the GT Block timer frame list
+ REFERENCE_TOKEN (GTBlock0TimerInfo)
+ }
+ },
+
+ // GT Block Timer Frames
+ {
+ // Frame 0
+ {
+ 0, // UINT8 FrameNumber
+ N1Sdp_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 PhysicalAddressCntBase
+ N1Sdp_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base
+ N1Sdp_GT_BLOCK_FRAME0_GSIV, // UINT32 PhysicalTimerGSIV
+ N1Sdp_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags
+ 0, // UINT32 VirtualTimerGSIV
+ 0, // UINT32 VirtualTimerFlags
+ N1Sdp_GTX_COMMON_FLAGS_NS // UINT32 CommonFlags
+ },
+ // Frame 1
+ {
+ 1, // UINT8 FrameNumber
+ N1Sdp_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 PhysicalAddressCntBase
+ N1Sdp_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 PhysicalAddressCntEL0Base
+ N1Sdp_GT_BLOCK_FRAME1_GSIV, // UINT32 PhysicalTimerGSIV
+ N1Sdp_GTX_TIMER_FLAGS, // UINT32 PhysicalTimerFlags
+ 0, // UINT32 VirtualTimerGSIV
+ 0, // UINT32 VirtualTimerFlags
+ N1Sdp_GTX_COMMON_FLAGS_S // UINT32 CommonFlags
+ },
+ },
+
+ // Watchdog Info
+ {
+ // The physical base address of the SBSA Watchdog control frame
+ FixedPcdGet64 (PcdGenericWatchdogControlBase),
+ // The physical base address of the SBSA Watchdog refresh frame
+ FixedPcdGet64 (PcdGenericWatchdogRefreshBase),
+ // The watchdog interrupt
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ // The watchdog flags
+ N1Sdp_SBSA_WATCHDOG_FLAGS
+ },
+
+ // SPCR Serial Port
+ {
+ FixedPcdGet64 (PcdSerialRegisterBase), // BaseAddress
+ FixedPcdGet32 (PL011UartInterrupt), // Interrupt
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+ FixedPcdGet32 (PL011UartClkInHz), // Clock
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype
+ },
+
+ // Debug Serial Port
+ {
+ FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress
+ 0, // Interrupt -unused
+ FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate
+ FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype
+ },
+
+ // Processor Hierarchy Nodes
+ {
+ // Package
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ CM_NULL_TOKEN,
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ SOC_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (SocResources)
+ },
+ // Cluster0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster0 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[0]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster0 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[1]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster1 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[2]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster1 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[3]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Slave chip hierarchy
+ // Package
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[7]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ CM_NULL_TOKEN,
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ SOC_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (SocResources)
+ },
+ // Cluster0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[8]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[7]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[9]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[7]), // -> Package
+ // CM_OBJECT_TOKEN GicCToken
+ CM_NULL_TOKEN,
+ // UINT32 NoOfPrivateResources
+ CLUSTER_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (ClusterResources)
+ },
+ // Cluster0 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[10]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[8]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[4]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster0 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[11]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[8]), // -> 'cluster in Cluster0
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[5]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster1 - Cpu0
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[10]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[9]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[6]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ // Cluster1 - Cpu1
+ {
+ // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (ProcHierarchyInfo[11]),
+ // UINT32 Flags
+ PROC_NODE_FLAGS (
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+ ),
+ // CM_OBJECT_TOKEN ParentToken
+ REFERENCE_TOKEN (ProcHierarchyInfo[9]), // -> 'cluster in Cluster1
+ // CM_OBJECT_TOKEN GicCToken
+ REFERENCE_TOKEN (GicCInfo[7]),
+ // UINT32 NoOfPrivateResources
+ CORE_RESOURCE_COUNT,
+ // CM_OBJECT_TOKEN PrivateResourcesArrayToken
+ REFERENCE_TOKEN (CoreResources)
+ },
+ },
+
+ // Cache information
+ {
+ // 'cluster's L3 cache
+ {
+ REFERENCE_TOKEN (CacheInfo[0]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_1MB, // UINT32 Size
+ 2048, // UINT32 NumberOfSets
+ 8, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // 'core's L1 instruction cache
+ {
+ REFERENCE_TOKEN (CacheInfo[1]), // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_64KB, // UINT32 Size
+ 256, // UINT32 NumberOfSets
+ 4, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // 'core's L1 data cache
+ {
+ REFERENCE_TOKEN (CacheInfo[2]), // CM_OBJECT_TOKEN Token
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_64KB, // UINT32 Size
+ 256, // UINT32 NumberOfSets
+ 4, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // cores's L2 cache
+ {
+ REFERENCE_TOKEN (CacheInfo[3]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_1MB, // UINT32 Size
+ 2048, // UINT32 NumberOfSets
+ 8, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ // slc cache
+ {
+ REFERENCE_TOKEN (CacheInfo[4]), // CM_OBJECT_TOKEN Token
+ CM_NULL_TOKEN, // CM_OBJECT_TOKEN NextLevelOfCacheToken
+ SIZE_8MB, // UINT32 Size
+ 8192, // UINT32 NumberOfSets
+ 16, // UINT32 Associativity
+ CACHE_ATTRIBUTES ( // UINT8 Attributes
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+ ),
+ 64 // UINT16 LineSize
+ },
+ },
+
+ // Resources private to the 'cluster (shared among cores) in Cluster
+ {
+ { REFERENCE_TOKEN (CacheInfo[0]) } // -> 'cluster's L3 cache in Cluster
+ },
+
+ // Resources private to each individual 'core instance in Cluster
+ {
+ { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster
+ { REFERENCE_TOKEN (CacheInfo[2]) } // -> 'core's L1 D-cache in Cluster
+ },
+
+ // Resources private to the SoC
+ {
+ { REFERENCE_TOKEN (CacheInfo[4]) }, // -> slc for SoC
+ },
+
+ // ITS group node
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_CCIX]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_SMMU_CCIX])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_PCIE]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_SMMU_PCIE])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_CCIX]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_CCIX])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_PCIE]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_PCIE])
+ },
+ //Remote Chip ITS
+ {
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_SMMU_PCIE]),
+ 1,
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_REMOTE_SMMU_PCIE])
+ },
+ {
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_PCIE]),
+ 1,
+ REFERENCE_TOKEN (ItsIdentifierArray[ITS_REMOTE_PCIE])
+ },
+ },
+
+ // ITS identifier array
+ {
+ {
+ // The ITS Identifier - 0
+ ITS_SMMU_CCIX
+ },
+ {
+ // The ITS Identifier - 1
+ ITS_SMMU_PCIE
+ },
+ {
+ // The ITS Identifier - 2
+ ITS_CCIX
+ },
+ {
+ // The ITS Identifier - 3
+ ITS_PCIE
+ },
+ {
+ // The ITS Identifier - 4
+ ITS_REMOTE_SMMU_PCIE
+ },
+ {
+ // The ITS Identifier - 5
+ ITS_REMOTE_PCIE
+ }
+ },
+
+ {
+ // SMMUv3 Node
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_PCIE]),
+ // Number of ID mappings
+ 2,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_SMMU_PCIE][0]),
+ // SMMU Base Address
+ 0x4F400000,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 0x10B,
+ // PRI Interrupt if SPI based
+ 0,
+ // GERR interrupt if GSIV based
+ 0x10D,
+ // Sync interrupt if GSIV based
+ 0x10C,
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping
+ 1
+ },
+ // SMMUv3 Node
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_CCIX]),
+ // Number of ID mappings
+ 2,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_SMMU_CCIX][0]),
+ // SMMU Base Address
+ 0x4F000000,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 0x104,
+ // PRI Interrupt if SPI based
+ 0,
+ // GERR interrupt if GSIV based
+ 0x106,
+ // Sync interrupt if GSIV based
+ 0x105,
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping
+ 1
+ },
+ //Remote Chip SMMU V3 setting
+ {
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_REMOTE_PCIE]),
+ 2,
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]),
+ 0x4004f400000,
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ 0,
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ 747,
+ 0,
+ 749,
+ 748,
+ 0,
+ 1
+ }
+ },
+
+ {
+ // Root Complex node info
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (RootComplexInfo[0]),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_PCIE][0]),
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+ // PCI segment number
+ 0,
+ // Memory address size limit
+ 42
+ },
+ // Root Complex node info
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (RootComplexInfo[1]),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_PCIE][1]),
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+ // PCI segment number
+ 1,
+ // Memory address size limit
+ 42
+ },
+ //Remote Chip Root Complex node Info
+ {
+ REFERENCE_TOKEN (RootComplexInfo[ROOT_REMOTE_PCIE]),
+ 1,
+ REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]),
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ 0,
+ 0,
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+ 2,
+ 42
+ }
+ },
+
+ // Array of Device ID mappings
+ {
+ // DeviceIdMapping[0][0] - [0][1]
+ {
+ // Mapping SMMUv3 -> ITS Group
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_PCIE]),
+ // Flags
+ 0
+ },
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x00000001,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_PCIE]),
+ // Flags
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ // DeviceIdMapping[1][0] - [1][1]
+ {
+ // Mapping SMMUv3 -> ITS Group
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_CCIX]),
+ // Flags
+ 0
+ },
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x00000001,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_CCIX]),
+ // Flags
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ // DeviceIdMapping[2][0] - [2][1]
+ {
+ // Mapping for RootComplex -> SMMUv3
+ // Device ID mapping for Root complex node
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_PCIE]),
+ // Flags
+ 0
+ },
+ // Device ID mapping for Root complex node
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_CCIX]),
+ // Flags
+ 0
+ }
+ },
+ // Mapping of Remote Chip SMMUv3 -> ITS Group
+ {
+ {
+ 0x0,
+ 0x0000ffff,
+ 0x0,
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_PCIE]),
+ 0
+ },
+ {
+ 0x0,
+ 0x00000001,
+ 0x0,
+ REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_SMMU_PCIE]),
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ // Mapping for Remote Chip RootComplex -> SMMUv3
+ {
+ {
+ 0x0,
+ 0x0000ffff,
+ 0x0,
+ REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_REMOTE_PCIE]),
+ 0
+ }
+ },
+ },
+
+ // PCI Configuration Space Info
+ {
+ // PCIe ECAM
+ {
+ 0x70000000, // Base Address
+ 0x0, // Segment Group Number
+ 0x0, // Start Bus Number
+ 17 // End Bus Number
+ },
+ // CCIX ECAM
+ {
+ 0x68000000, // Base Address
+ 0x1, // Segment Group Number
+ 0x0, // Start Bus Number
+ 17 // End Bus Number
+ },
+ //Remote Chip PCIe ECAM
+ {
+ 0x40070000000, // Base Address
+ 0x2, // Segment Group Number
+ 0x0, // Start Bus Number
+ 17 // End Bus Number
+ }
+ },
+
+ // Memory Affinity Info
+ {
+ {
+ // Proximity domain to which memory range belongs
+ 0,
+ //Base Address
+ 0x80000000,
+ //Length
+ 0x80000000,
+ //Flags
+ EFI_ACPI_6_3_MEMORY_ENABLED
+ },
+ {
+ // Proximity domain to which memory range belongs
+ 0,
+ //Base Address
+ 0x8080000000,
+ //Length is updated dynamically from SRAM
+ 0,
+ //Flags
+ EFI_ACPI_6_3_MEMORY_ENABLED
+ }
+ }
+
+};
+
+/** A helper function for returning the Configuration Manager Objects.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+ @retval EFI_SUCCESS Success.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObject (
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ CmObjectDesc->ObjectId = CmObjectId;
+ CmObjectDesc->Size = ObjectSize;
+ CmObjectDesc->Data = (VOID*)Object;
+ CmObjectDesc->Count = ObjectCount;
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ CmObjectId,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return EFI_SUCCESS;
+}
+
+/** A helper function for returning the Configuration Manager Objects that
+ match the token.
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Object Pointer to the Object(s).
+ @param [in] ObjectSize Total size of the Object(s).
+ @param [in] ObjectCount Number of Objects.
+ @param [in] Token A token identifying the object.
+ @param [in] HandlerProc A handler function to search the object
+ referenced by the token.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObjectRefByToken (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN VOID * Object,
+ IN CONST UINTN ObjectSize,
+ IN CONST UINTN ObjectCount,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN CONST CM_OBJECT_HANDLER_PROC HandlerProc,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ EFI_STATUS Status;
+ CmObjectDesc->ObjectId = CmObjectId;
+ if (Token == CM_NULL_TOKEN) {
+ CmObjectDesc->Size = ObjectSize;
+ CmObjectDesc->Data = (VOID*)Object;
+ CmObjectDesc->Count = ObjectCount;
+ Status = EFI_SUCCESS;
+ } else {
+ Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ (VOID*)Token,
+ CmObjectId,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return Status;
+}
+
+/** A helper function for returning Configuration Manager Object(s) referenced
+ by token when the entire platform repository is in scope and the
+ CM_NULL_TOKEN value is not allowed.
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token identifying the object.
+ @param [in] HandlerProc A handler function to search the object(s)
+ referenced by the token.
+ @param [in, out] CmObjectDesc Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObjectSearchPlatformRepo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN CONST CM_OBJECT_HANDLER_PROC HandlerProc,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObjectDesc
+ )
+{
+ EFI_STATUS Status;
+ CmObjectDesc->ObjectId = CmObjectId;
+ if (Token == CM_NULL_TOKEN) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: CM_NULL_TOKEN value is not allowed when searching"
+ " the entire platform repository.\n"
+ ));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+ CmObjectId,
+ (VOID*)Token,
+ CmObjectDesc->Data,
+ CmObjectDesc->Size,
+ CmObjectDesc->Count
+ ));
+ return Status;
+}
+
+/** Initialize the Platform Configuration Repository.
+ @param [in] PlatformRepo Pointer to the Configuration Manager Protocol.
+ @retval EFI_SUCCESS Success
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+InitializePlatformRepository (
+ IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatformRepo
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/** Return a GT Block timer frame info list.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGTBlockTimerFrameInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) {
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo);
+ CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->GTBlock0TimerInfo);
+ return EFI_SUCCESS;
+}
+
+/** Return an ITS identifier array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsIdentifierArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]);
+ CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return an ITS group info.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsGroupInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsGroupInfo);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]);
+ CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return a device Id mapping array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetDeviceIdMappingArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Count;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n"));
+
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[2][0]) {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[2][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[2][1]) {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[2][1]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]) {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]) {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->Data = (VOID*)Token;
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Count = Count;
+ CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING);
+
+ return EFI_SUCCESS;
+}
+
+/** Return GIC CPU Interface Info.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Object ID of the CM object requested
+ @param [in] SearchToken A unique token for identifying the requested
+ CM_ARM_GICC_INFO object.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGicCInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN SearchToken,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
+ UINT32 TotalObjCount;
+ UINT32 ObjIndex;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+
+ if (PlatInfo->MultichipMode)
[SAMI] Use curly braces for if-else. Also, the if statment does not
evaluate a boolean expression as MultichipMode is UINT8. Same comment
for other places in this patch series.
[/SAMI]
+ TotalObjCount = PLAT_CPU_COUNT * 2;
+ else
+ TotalObjCount = PLAT_CPU_COUNT;
+
+ for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
+ if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]);
+ CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return a list of Configuration Manager object references pointed to by the
+ given input token.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Object ID of the CM object requested
+ @param [in] SearchToken A unique token for identifying the requested
+ CM_ARM_OBJ_REF list.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetCmObjRefs (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN SearchToken,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->ClusterResources) {
+ CmObject->Size = sizeof (PlatformRepo->ClusterResources);
+ CmObject->Data = (VOID*)&PlatformRepo->ClusterResources;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->ClusterResources);
+ return EFI_SUCCESS;
+ }
+ if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CoreResources) {
+ CmObject->Size = sizeof (PlatformRepo->CoreResources);
+ CmObject->Data = (VOID*)&PlatformRepo->CoreResources;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->CoreResources);
+ return EFI_SUCCESS;
+ }
+ if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->SocResources) {
+ CmObject->Size = sizeof (PlatformRepo->SocResources);
+ CmObject->Data = (VOID*)&PlatformRepo->SocResources;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->SocResources);
+ return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return a standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
+ UINT32 AcpiTableCount;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ PlatformRepo = This->PlatRepoInfo;
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+ AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
+ if (!PlatInfo->MultichipMode)
+ AcpiTableCount -= 1;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EStdObjCfgMgrInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->CmInfo,
+ sizeof (PlatformRepo->CmInfo),
+ 1,
+ CmObject
+ );
+ break;
+ case EStdObjAcpiTableList:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->CmAcpiTableList,
+ sizeof (PlatformRepo->CmAcpiTableList),
+ AcpiTableCount,
+ CmObject
+ );
+ break;
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }
+
+ return Status;
+}
+
+/** Return an ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
[SAMI] Align consistently.
[/SAMI]
+ UINT32 GicRedistCount;
+ UINT32 GicCpuCount;
+ UINT32 ProcHierarchyInfoCount;
+ UINT32 GicItsInfoCount;
+ UINT32 ItsGroupInfoCount;
+ UINT32 ItsIdentifierArrayCount;
+ UINT32 SmmuV3InfoCount;
+ UINT32 DeviceIdMappingCount;
+ UINT32 RootComplexInfoCount;
+ UINT32 PciConfigInfoCount;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ PlatformRepo = This->PlatRepoInfo;
+
+ // Probe for multi chip information
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+ if (PlatInfo->MultichipMode) {
+ GicRedistCount = 2;
+ GicCpuCount = PLAT_CPU_COUNT * 2;
+ ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT * 2;
+ GicItsInfoCount = ITS_MAX;
+ ItsGroupInfoCount = ITS_MAX;
+ ItsIdentifierArrayCount = ITS_MAX;
+ SmmuV3InfoCount = SMMUV3INFO_MAX;
+ DeviceIdMappingCount = DEVICEIDMAPPING_MAX;
+ RootComplexInfoCount = ROOT_PCIE_MAX;
+ PciConfigInfoCount = ROOT_PCIE_MAX;
+ } else {
+ GicRedistCount = 1;
+ GicCpuCount = PLAT_CPU_COUNT;
+ ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT;
+ GicItsInfoCount = ITS_MASTER_CHIP_MAX;
+ ItsGroupInfoCount = ITS_MASTER_CHIP_MAX;
+ ItsIdentifierArrayCount = ITS_MASTER_CHIP_MAX;
+ SmmuV3InfoCount = SMMUV3INFO_MASTER_CHIP_MAX;
+ DeviceIdMappingCount = DEVICEIDMAPPING_MASTER_CHIP_MAX;
+ RootComplexInfoCount = ROOT_PCIE_MASTER_CHIP_MAX;
+ PciConfigInfoCount = ROOT_PCIE_MASTER_CHIP_MAX;
+ }
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EArmObjBootArchInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->BootArchInfo,
+ sizeof (PlatformRepo->BootArchInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjFixedFeatureFlags:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->FixedFeatureFlags,
+ sizeof (PlatformRepo->FixedFeatureFlags),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjPowerManagementProfileInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->PmProfileInfo,
+ sizeof (PlatformRepo->PmProfileInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGenericTimerInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->GenericTimerInfo,
+ sizeof (PlatformRepo->GenericTimerInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjPlatformGenericWatchdogInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->Watchdog,
+ sizeof (PlatformRepo->Watchdog),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjPlatformGTBlockInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->GTBlockInfo,
+ sizeof (PlatformRepo->GTBlockInfo),
+ ARRAY_SIZE (PlatformRepo->GTBlockInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjGTBlockTimerFrameInfo:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->GTBlock0TimerInfo,
+ sizeof (PlatformRepo->GTBlock0TimerInfo),
+ ARRAY_SIZE (PlatformRepo->GTBlock0TimerInfo),
+ Token,
+ GetGTBlockTimerFrameInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicCInfo:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->GicCInfo,
+ sizeof (PlatformRepo->GicCInfo),
+ GicCpuCount,
+ Token,
+ GetGicCInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicDInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->GicDInfo,
+ sizeof (PlatformRepo->GicDInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicRedistributorInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->GicRedistInfo,
+ sizeof (PlatformRepo->GicRedistInfo),
+ GicRedistCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjSerialConsolePortInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->SpcrSerialPort,
+ sizeof (PlatformRepo->SpcrSerialPort),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjSerialDebugPortInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->DbgSerialPort,
+ sizeof (PlatformRepo->DbgSerialPort),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicItsInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->GicItsInfo,
+ sizeof (PlatformRepo->GicItsInfo),
+ GicItsInfoCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjSmmuV3:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->SmmuV3Info,
+ sizeof (PlatformRepo->SmmuV3Info),
+ SmmuV3InfoCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjItsGroup:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsGroupInfo,
+ sizeof (PlatformRepo->ItsGroupInfo),
+ ItsGroupInfoCount,
+ Token,
+ GetItsGroupInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicItsIdentifierArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsIdentifierArray,
+ sizeof (PlatformRepo->ItsIdentifierArray),
+ ItsIdentifierArrayCount,
+ Token,
+ GetItsIdentifierArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjRootComplex:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->RootComplexInfo,
+ sizeof (PlatformRepo->RootComplexInfo),
+ RootComplexInfoCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjIdMappingArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->DeviceIdMapping,
+ sizeof (PlatformRepo->DeviceIdMapping),
+ DeviceIdMappingCount,
+ Token,
+ GetDeviceIdMappingArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjProcHierarchyInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->ProcHierarchyInfo,
+ sizeof (PlatformRepo->ProcHierarchyInfo),
+ ProcHierarchyInfoCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjCacheInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->CacheInfo,
+ sizeof (PlatformRepo->CacheInfo),
+ ARRAY_SIZE (PlatformRepo->CacheInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjCmRef:
+ Status = HandleCmObjectSearchPlatformRepo (
+ This,
+ CmObjectId,
+ Token,
+ GetCmObjRefs,
+ CmObject
+ );
+ break;
+
+ case EArmObjPciConfigSpaceInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->PciConfigInfo,
+ sizeof (PlatformRepo->PciConfigInfo),
+ PciConfigInfoCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjMemoryAffinityInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->MemAffInfo,
+ sizeof (PlatformRepo->MemAffInfo),
+ ARRAY_SIZE (PlatformRepo->MemAffInfo),
+ CmObject
+ );
+ break;
+
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_INFO,
+ "INFO: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }//switch
+
+ return Status;
+}
+
+/** Return an OEM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetOemNameSpaceObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ default: {
+ Status = EFI_NOT_FOUND;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Object 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }
+
+ return Status;
+}
+
+/** The GetObject function defines the interface implemented by the
+ Configuration Manager Protocol for returning the Configuration
+ Manager Objects.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+N1sdpPlatformGetObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (GET_CM_NAMESPACE_ID (CmObjectId)) {
+ case EObjNameSpaceStandard:
+ Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ case EObjNameSpaceArm:
+ Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ case EObjNameSpaceOem:
+ Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject);
+ break;
+ default: {
+ Status = EFI_INVALID_PARAMETER;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n",
+ CmObjectId,
+ Status
+ ));
+ break;
+ }
+ }
+
+ return Status;
+}
+
+/** The SetObject function defines the interface implemented by the
+ Configuration Manager Protocol for updating the Configuration
+ Manager Objects.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the Object.
+
+ @retval EFI_UNSUPPORTED This operation is not supported.
+**/
+EFI_STATUS
+EFIAPI
+N1sdpPlatformSetObject (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/** A structure describing the configuration manager protocol interface.
+*/
+STATIC
+CONST
+EDKII_CONFIGURATION_MANAGER_PROTOCOL N1sdpPlatformConfigManagerProtocol = {
+ CREATE_REVISION(1,0),
+ N1sdpPlatformGetObject,
+ N1sdpPlatformSetObject,
+ &N1sdpRepositoryInfo
+};
+
+/**
+ Entrypoint of Configuration Manager Dxe.
+
+ @param ImageHandle
+ @param SystemTable
+
+ @return EFI_SUCCESS
+ @return EFI_LOAD_ERROR
+ @return EFI_OUT_OF_RESOURCES
+**/
+EFI_STATUS
+EFIAPI
+ConfigurationManagerDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+ NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
+ UINT64 Dram2Size;
+ UINT64 RemoteDdrSize;
+
+ RemoteDdrSize = 0;
+
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+ Dram2Size = ((PlatInfo->LocalDdrSize - 2) * 1024UL * 1024UL * 1024UL);
[SAMI] Can SIZE_1GB be used here instead of 1024UL *...?
[/SAMI]
+
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2]. \
+ Length = Dram2Size;
+
+ if (PlatInfo->MultichipMode == 1) {
+ RemoteDdrSize = ((PlatInfo->RemoteDdrSize -2) * 1024UL * 1024UL * 1024UL);
+
+ // Update Remote DDR Region1
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+ ProximityDomain = 1;
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+ BaseAddress = FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBase);
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+ Length = FixedPcdGet64 (PcdSystemMemorySize);
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+ Flags = EFI_ACPI_6_3_MEMORY_ENABLED;
+
+ // Update Remote DDR Region2
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+ ProximityDomain = 1;
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+ BaseAddress = FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base);
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+ Length = RemoteDdrSize;
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+ Flags = EFI_ACPI_6_3_MEMORY_ENABLED;
+ }
+
[SAMI] The code clock above is initialising the platform info
repository. Can this be moved to InitializePlatformRepositor() ?
[/SAMI]
+ // Initialize the Platform Configuration Repository before installing the
+ // Configuration Manager Protocol
+ Status = InitializePlatformRepository (
+ N1sdpPlatformConfigManagerProtocol.PlatRepoInfo
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Failed to initialize the Platform Configuration Repository." \
+ " Status = %r\n",
+ Status
+ ));
+ }
+
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gEdkiiConfigurationManagerProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ (VOID*)&N1sdpPlatformConfigManagerProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: Failed to get Install Configuration Manager Protocol." \
+ " Status = %r\n",
+ Status
+ ));
+ goto error_handler;
+ }
+
+error_handler:
+ return Status;
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c
new file mode 100644
index 000000000000..52fc3108a2c5
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c
@@ -0,0 +1,103 @@
+/** @file
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include "N1SdpAcpiHeader.h"
+
+//
+// Heterogeneous Memory Attribute Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyStruct;
+ UINT32 InitiatorProximityDomainList[1];
+ UINT32 TargetProximityDomainList[2];
+ UINT16 LatencyEntry[1][2];
+} EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Memory[2];
+ EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE LatencyInfo;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {0x00, 0x00, 0x00, 0x00},
+ },
+
+ // Memory Attribute Structure
+ {
+ {
+ EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, // Type
+ {0x00, 0x00}, // Reserved
+ 40, // Length
+ {.InitiatorProximityDomainValid = 1}, // Flags
+ {0x00, 0x00}, // Reserved1
+ 0, // InitiatorProximityDomain
+ 0, // MemoryProximityDomain
+ { 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ }, // Reserved2
+ },
+ {
+ EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, // Type
+ {0x00, 0x00}, // Reserved
+ 40, // Length
+ {.InitiatorProximityDomainValid = 1}, // Flags
+ {0x00, 0x00}, // Reserved1
+ 0, // InitiatorProximityDomain
+ 1, // MemoryProximityDomain
+ { 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ }, // Reserved2
+ },
+ },
+
+ // System Locality Latency Structure (LatencyInfo)
+ {
+ // LatencyStruct
+ {
+ EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, // Type
+ {0x00, 0x00}, // Reserved
+ sizeof (EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE), // Length
+ {.MemoryHierarchy = 0}, // Flags
+ 0, // DataType - Access latency
+ {0x00, 0x00}, // Reserved1
+ 1, // NumberOfInitiatorProximityDomains
+ 2, // NumberOfTargetProximityDomains
+ {0x00, 0x00, 0x00, 0x00}, // Reserved2
+ 1000, // EntryBaseUnit - 1000ps = 1ns
+ },
+ // InitiatorProximityDomainList
+ { 0 },
+ // TargetProximityDomainList
+ { 0, 1 },
+ // LatencyEntry
+ {
+ {119, 200},
+ },
+ },
+};
diff --git a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
index e0b89556d40d..a5ebeb71efa8 100644
--- a/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.c
@@ -6,6 +6,7 @@

**/

+#include <Library/AcpiLib.h>
[SAMI] Is this needed here in this file?
[SAMI]
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/RamDisk.h>
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
new file mode 100644
index 000000000000..0d7dde1a73ae
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
@@ -0,0 +1,477 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "N1SdpAcpiHeader.h"
+#include "NeoverseN1Soc.h"
+
+#define ACPI_GRAPH_REV 0
+#define ACPI_GRAPH_UUID "ab02a46b-74c7-45a2-bd68-f7d344ef2153"
+
+#define CORESIGHT_GRAPH_UUID "3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"
+
+#define CS_LINK_MASTER 1
+#define CS_LINK_SLAVE 0
+
+#define DSD_CS_GRAPH_BEGIN(_nports) \
+ Package () { \
+ 1, \
+ ToUUID(CORESIGHT_GRAPH_UUID), \
+ _nports,
+
+#define DSD_CS_GRAPH_END \
+ }
+
+#define DSD_GRAPH_BEGIN(_nports) \
+ ToUUID(ACPI_GRAPH_UUID), \
+ Package() { \
+ ACPI_GRAPH_REV, \
+ 1, \
+ DSD_CS_GRAPH_BEGIN(_nports)
+
+#define DSD_GRAPH_END \
+ DSD_CS_GRAPH_END \
+ }
+
+#define DSD_PORTS_BEGIN(_nports) \
+ Name (_DSD, Package () { \
+ DSD_GRAPH_BEGIN(_nports)
+
+#define DSD_PORTS_END \
+ DSD_GRAPH_END \
+ })
+
+#define CS_PORT(_port, _rport, _rphandle, _dir) \
+ Package () { _port, _rport, _rphandle, _dir}
+
+#define CS_INPUT_PORT(_port, _rport, _rphandle) \
+ CS_PORT(_port, _rport, _rphandle, CS_LINK_SLAVE)
+
+#define CS_OUTPUT_PORT(_port, _rport, _rphandle) \
+ CS_PORT(_port, _rport, _rphandle, CS_LINK_MASTER)
+
+DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) {
+ Scope(_SB) {
+ Device(CP00) { // Ares-0: Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name(_STA, 0xF)
+ Device(ETM0) { // ETM on Cluster0 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETM0
+ }
+
+ Device(CP01) { // Ares-1: Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name(_STA, 0xF)
+ Device(ETM1) { // ETM on Cluster0 CPU1
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 1, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETM1
+ }
+
+ Device(CP02) { // Ares-2: Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name(_STA, 0xF)
+ Device(ETM2) { // ETM on Cluster1 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm2Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm2MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETM2
+ }
+
+ Device(CP03) { // Ares-3: Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name(_STA, 0xF)
+ Device(ETM3) { // ETM on Cluster0 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm3Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm3MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 1, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETM3
+ }
+
+ Device(ETF0) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 0, \_SB_.FUN),
+ CS_INPUT_PORT(0, 0, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETF0
+
+ Device(ETF1) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 1, \_SB_.FUN),
+ CS_INPUT_PORT(0, 0, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETF1
+
+ Device(ETF2) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf2Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf2MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 5, \_SB_.MFUN),
+ CS_INPUT_PORT(0, 0, \_SB_.STM0)
+ DSD_PORTS_END
+ } // ETF2
+
+ Device(FUN) {
+ Name(_HID, "ARMHC9FF")
+ Name(_CID, "ARMHC9FF")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsFunnel0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsFunnel0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.MFUN),
+ CS_INPUT_PORT(0, 0, \_SB_.ETF0),
+ CS_INPUT_PORT(1, 0, \_SB_.ETF1)
+ DSD_PORTS_END
+ } // FUN
+
+ Device(STM0) {
+ Name(_HID, "ARMHC502") // STM
+ Name(_CID, "ARMHC502")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsStmBase), // Min Base Address
+ FixedPcdGet64 (PcdCsStmMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ Memory32Fixed(ReadWrite,
+ FixedPcdGet32 (PcdCsStmStimulusBase),
+ FixedPcdGet32 (PcdCsStmStimulusSize))
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF2)
+ DSD_PORTS_END
+ }
+
+ Device(MFUN) { // Master Funnel
+ Name(_HID, "ARMHC9FF") // Funnel
+ Name(_CID, "ARMHC9FF") // Funnel
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsFunnel1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsFunnel1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.REP),
+ CS_INPUT_PORT(0, 0, \_SB_.FUN),
+ CS_INPUT_PORT(5, 0, \_SB_.ETF2)
+ DSD_PORTS_END
+ } // MFUN
+
+ Device(REP) {
+ Name(_HID, "ARMHC98D") // Replicator
+ Name(_CID, "ARMHC98D") // Replicator
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsReplicatorBase), // Min Base Address
+ FixedPcdGet64 (PcdCsReplicatorMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.TPIU),
+ CS_OUTPUT_PORT(1, 0, \_SB_.ETR),
+ CS_INPUT_PORT(0, 0, \_SB_.MFUN)
+ DSD_PORTS_END
+ } // REP
+
+ Device(TPIU) {
+ Name(_HID, "ARMHC979") // TPIU
+ Name(_CID, "ARMHC979") // TPIU
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsTpiuBase), // Min Base Address
+ FixedPcdGet64 (PcdCsTpiuMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_INPUT_PORT(0, 0, \_SB_.REP)
+ DSD_PORTS_END
+ } // TPIU
+
+ Device(ETR) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CCA, 0) // The ETR on this platform is not coherent
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtrBase), // Min Base Address
+ FixedPcdGet64 (PcdCsEtrMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ Name(_DSD, Package() {
+ DSD_GRAPH_BEGIN(1)
+ CS_INPUT_PORT(0, 1, \_SB_.REP)
+ DSD_GRAPH_END,
+
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package() {
+ Package(2) {"arm,scatter-gather", 1}
+ }
+ })
+
+ } // ETR
+
+ Device(SFN0) { // Static Funnel 0
+ Name(_HID, "ARMHC9FE") // Funnel
+ Name(_CID, "ARMHC9FE") // Funnel
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF0),
+ CS_INPUT_PORT(0, 0, \_SB_.CP00.ETM0),
+ CS_INPUT_PORT(1, 0, \_SB_.CP01.ETM1)
+ DSD_PORTS_END
+ } // SFN0
+
+ Device(SFN1) { // Static Funnel 1
+ Name(_HID, "ARMHC9FE") // Funnel
+ Name(_CID, "ARMHC9FE") // Funnel
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF1),
+ CS_INPUT_PORT(0, 0, \_SB_.CP02.ETM2),
+ CS_INPUT_PORT(1, 0, \_SB_.CP03.ETM3)
+ DSD_PORTS_END
+ } // SFN1
+
+ Device(CMN6) {
+ Name(_HID, "ARMHC600")
+
+ Name(_CRS, ResourceTemplate () {
+ // Region location is platform specific
+ // Other name(s) of this region: PERIPHBASE
+ QWordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x00000000,
+ 0x50000000,
+ 0x5FFFFFFF,
+ 0x00000000,
+ 0x10000000,
+ ,
+ ,
+ CFGR
+ )
+
+ // Sub-region location is platform specific
+ // Other name(s) of this region: ROOTNODEBASE
+ QWordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x00000000,
+ 0x50D00000,
+ 0x50D03FFF,
+ 0x00000000,
+ 0x00004000,
+ ,
+ ,
+ ROOT
+ )
+
+ // CMN600_INTREQPMU_DTC0
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 78 }
+ })
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
new file mode 100644
index 000000000000..50f8fdf11416
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
@@ -0,0 +1,247 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "N1SdpAcpiHeader.h"
+
+/*
+ See ACPI 6.1 Section 6.2.13
+
+ There are two ways that _PRT can be used.
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+/*
+ See Reference [1] 6.1.1
+ "High word-Device #, Low word-Function #. (for example, device 3,
+ function 2 is 0x00030002). To refer to all the functions on a device #,
+ use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+ EFI_ACPI_ARM_OEM_REVISION)
+{
+ Scope (_SB) {
+
+ // PCI Root Complex
+ LNK_DEVICE(1, LNKA, 201)
+ LNK_DEVICE(2, LNKB, 202)
+ LNK_DEVICE(3, LNKC, 203)
+ LNK_DEVICE(4, LNKD, 204)
+ LNK_DEVICE(5, LNKE, 233)
+ LNK_DEVICE(6, LNKF, 234)
+ LNK_DEVICE(7, LNKG, 235)
+ LNK_DEVICE(8, LNKH, 236)
+
+ // PCI Root Complex
+ Device(PCI0) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPcieBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPcieBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdPcieBusCount) // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPcieMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPcieMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPcieMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPcieMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPcieMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdPcieMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPcieMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPcieIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPcieIoTranslation), // Translate
+ FixedPcdGet32 (PcdPcieIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+
+ // CCIX Root Complex
+ Device(PCI1) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, 1) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 1
+ Device (RP1) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKE), // INTA
+ ROOT_PRT_ENTRY(1, LNKF), // INTB
+ ROOT_PRT_ENTRY(2, LNKG), // INTC
+ ROOT_PRT_ENTRY(3, LNKH), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdCcixBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdCcixBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdCcixBusCount) // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdCcixMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixMmio32Translation), // Translate
+ FixedPcdGet32 (PcdCcixMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCcixMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdCcixMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdCcixMmio64Translation), // Translate
+ FixedPcdGet64 (PcdCcixMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixIoBase), // Min Base Address
+ FixedPcdGet32 (PcdCcixIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixIoTranslation), // Translate
+ FixedPcdGet32 (PcdCcixIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+
+ }
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
new file mode 100644
index 000000000000..1efb755a67dd
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
@@ -0,0 +1,156 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "N1SdpAcpiHeader.h"
+
+/*
+ See ACPI 6.1 Section 6.2.13
+
+ There are two ways that _PRT can be used.
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+/*
+ See Reference [1] 6.1.1
+ "High word-Device #, Low word-Function #. (for example, device 3,
+ function 2 is 0x00030002). To refer to all the functions on a device #,
+ use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+ EFI_ACPI_ARM_OEM_REVISION)
+{
+ Scope (_SB) {
+
+ // Remote PCI Root Complex
+ LNK_DEVICE(9, LNKI, 681)
+ LNK_DEVICE(10, LNKJ, 682)
+ LNK_DEVICE(11, LNKK, 683)
+ LNK_DEVICE(12, LNKL, 684)
+
+ //Remote PCIe root complex
+ Device(PCI2) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, 2) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Remote Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKI), // INTA
+ ROOT_PRT_ENTRY(1, LNKJ), // INTB
+ ROOT_PRT_ENTRY(2, LNKK), // INTC
+ ROOT_PRT_ENTRY(3, LNKL), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPcieBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPcieBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdPcieBusCount) // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPcieMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdRemotePcieMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPcieMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPcieMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPcieMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdRemotePcieMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPcieMmio64Size) // Length
+ )
+
+ QWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPcieIoMaxBase), // Max Base Address
+ FixedPcdGet64 (PcdRemotePcieIoTranslation), // Translate
+ FixedPcdGet32 (PcdPcieIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+ }
+}
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Initialize the fixed previous shadow stack token.

Laszlo Ersek
 

On 06/22/21 16:05, Laszlo Ersek wrote:
On 06/13/21 06:36, Sheng Wei wrote:
The fixed previous shadow stack token should be initialized as UINT64.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192
(4) Please open a new BZ ticket for this issue. (It's OK to add the
previous ticket number, 3192, to the "See Also" field of the new ticket,
and to make a new comment on the old ticket as well.)

BZ#3192 was moved to RESOLVED|FIXED state in March, and commit
0930e7ff6428 has been part of two stable tags since; namely
edk2-stable202102 and edk2-stable202105. At this point, BZ#3192 should
no longer be modified; the issue needs to be tracked by a new ticket.

Thanks
Laszlo



Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index 661c1ba294..ca3f5ff91a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -202,7 +202,7 @@ InitShadowStack (
// Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.
//
InterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
- *(UINT32 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
+ *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
mCetInterruptSsp = InterruptSsp - sizeof(UINT64);

mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);
(1) Please add the following line to the commit message:

Fixes: 0930e7ff64281017762c8c055bab38925944c724

(2) The subject line is quite confusing; how about:

UefiCpuPkg/PiSmmCpuDxeSmm: initialize shadow stack token as UINT64

(3) Commit 0930e7ff6428 ("UefiCpuPkg/CpuExceptionHandlerLib: Clear CET
shadow stack token busy bit", 2021-03-02) was reviewed by Jiewen and
Ray; I'd like to ask them to review this fix as well.

Thanks
Laszlo


Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Initialize the fixed previous shadow stack token.

Laszlo Ersek
 

On 06/13/21 06:36, Sheng Wei wrote:
The fixed previous shadow stack token should be initialized as UINT64.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index 661c1ba294..ca3f5ff91a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -202,7 +202,7 @@ InitShadowStack (
// Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.
//
InterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
- *(UINT32 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
+ *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
mCetInterruptSsp = InterruptSsp - sizeof(UINT64);

mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);
(1) Please add the following line to the commit message:

Fixes: 0930e7ff64281017762c8c055bab38925944c724

(2) The subject line is quite confusing; how about:

UefiCpuPkg/PiSmmCpuDxeSmm: initialize shadow stack token as UINT64

(3) Commit 0930e7ff6428 ("UefiCpuPkg/CpuExceptionHandlerLib: Clear CET
shadow stack token busy bit", 2021-03-02) was reviewed by Jiewen and
Ray; I'd like to ask them to review this fix as well.

Thanks
Laszlo


Re: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Laszlo Ersek
 

On 06/22/21 15:34, Laszlo Ersek wrote:
Hi,

On 06/11/21 08:37, Xu, Min M wrote:
In today's TianoCore Design Meeting we reviewed the Overview Section (from slide 1 to 20). Thanks much for the valuable feedbacks and comments. The meeting minutes will be sent out soon.

To address the concerns of the *one binary* solution in previous discussion, we propose 2 Configurations for TDVF to upstream. (slide 6 - 8)



Config-A:

* Merge the *basic* TDVF feature to existing OvmfX64Pkg.dsc. (Align with existing SEV)
* Threat model: VMM is NOT out of TCB. (We don't make things worse.)
* The OvmfX64Pkg.dsc includes SEV/TDX/normal OVMF basic boot capability. The final binary can run on SEV/TDX/normal OVMF
* No changes to existing OvmfPkgX64 image layout.
* No need to add additional security features if they do not exist today
* No need to remove features if they exist today.
* RTMR is not supported
* PEI phase is NOT skipped in either Td or Non-Td
(so this is "Config-A / Option B", per slide 9 in the v0.9 slide deck)




Config-B:

* Add a standalone IntelTdx.dsc to a TDX specific directory for a *full* feature TDVF. (Align with existing SEV)
* Threat model: VMM is out of TCB. (We need necessary change to prevent attack from VMM)
* IntelTdx.dsc includes TDX/normal OVMF basic boot capability. The final binary can run on TDX/normal OVMF
* It might eventually merge with AmdSev.dsc, but NOT at this point of time. And we don't know when it will happen. We need sync with AMD in the community, after both of us think the solutions are mature to merge.
* Need to add necessary security feature as mandatory requirement, such as RTMR based Trusted Boot support
* Need to remove unnecessary attack surfaces, such as network stack.
After reading the above, and checking slides 6 through 10 of the v0.9
slide deck:

- I prefer Config-B (IntelTdx.dsc).
I should clarify: the relevant part of my preference is not that
"IntelTdx.dsc" contain the *complete* TDVF feature set. The relevant
part (for me) is that "OvmfPkgX64.dsc" *not* be over-complicated for the
sake of TDX, even considering only the "basic" TDVF feature set. It's
fine to implement TDX in two stages ("basic" and "complete"); my point
is that even "basic" should not over-complicate "OvmfPkgX64.dsc".

Thanks
Laszlo



This is in accordance with what I wrote earlier about "OvmfPkgX64.dsc"
maintainability and regressions.

Additionally (given that a full-featured TDVF is the ultimate goal), I
see the advance from "Config-A / option B" to "Config-B" a lot less
*incremental* than the step from "OvmfPkgX64.dsc" to "AmdSev.dsc" was.

Put differently, I think that any TDX work targeted at "OvmfPkgX64.dsc"
is going to prove less useful for the final "IntelTdx.dsc" than how
reusable SEV work from "OvmfPkgX64.dsc" did for "AmdSev.dsc".

Put yet differently, I'm concerned that a part of the TDX work for
"OvmfPkgX64.dsc" might be a waste, with an eye towards the ultimate TDVF
feature set ("IntelTdx.dsc").


- I could (very cautiously) live with "Config-A / option B" as the
initial approach. However, we'de have to be ready to make the full split
(the switch-over to "IntelTdx.dsc") at *any point* during development,
in case something turns out to be too intrusive. (And yes, "too
intrusive" is subjective.)

By this I mean that any particular patch towards "Config-A / option B"
could cause me to ask, "please create IntelTdx.dsc now". Note that the
later we make the switch the more painful it could be (= the more
invested in "OvmfPkgX64.dsc" we could be, at that point).

For example, as I stated earlier, "OvmfPkg/AcpiPlatformDxe" is a driver
where I'd like to see zero changes, for either SEV or TDX. If the TD
Mailbox location has to be reported to the OS via the MADT, and QEMU
cannot (or must not) populate that field in the MADT, then a separate,
TDX-specific edk2 driver should locate the MADT (installed technically
by "OvmfPkg/AcpiPlatformDxe", earlier), and update the field.

Thanks,
Laszlo

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Min Xu
Sent: Friday, June 11, 2021 6:30 AM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>; rfc@edk2.groups.io
Cc: jejb@linux.ibm.com; Laszlo Ersek <lersek@redhat.com>; Brijesh Singh <brijesh.singh@amd.com>; Tom Lendacky <thomas.lendacky@amd.com>; erdemaktas@google.com; cho@microsoft.com; bret.barkelew@microsoft.com; Jon Lange <jlange@microsoft.com>; Karen Noel <knoel@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Nathaniel McCallum <npmccallum@redhat.com>; Dr. David Alan Gilbert <dgilbert@redhat.com>; Ademar de Souza Reis Jr. <areis@redhat.com>
Subject: Re: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Hi, All
Thanks much for the valuable comments and discussion about the design.
We have updated the slides (v0.9) in below link. If some comments or concerns are not answered/addressed in the new slides, please don't hesitate to tell us. We do want to answer/address all the comments/concerns. But to be honest it is a rather complicated one and we appreciate your feedbacks.
https://edk2.groups.io/g/devel/files/Designs/2021/0611/TDVF_Design_Review%28v0.9%29.pptx

Thanks much!

Xu Min


From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> On Behalf Of Yao, Jiewen
Sent: Thursday, June 3, 2021 9:51 PM
To: rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Cc: jejb@linux.ibm.com<mailto:jejb@linux.ibm.com>; Laszlo Ersek <lersek@redhat.com<mailto:lersek@redhat.com>>; Brijesh Singh <brijesh.singh@amd.com<mailto:brijesh.singh@amd.com>>; Tom Lendacky <thomas.lendacky@amd.com<mailto:thomas.lendacky@amd.com>>; erdemaktas@google.com<mailto:erdemaktas@google.com>; cho@microsoft.com<mailto:cho@microsoft.com>; bret.barkelew@microsoft.com<mailto:bret.barkelew@microsoft.com>; Jon Lange <jlange@microsoft.com<mailto:jlange@microsoft.com>>; Karen Noel <knoel@redhat.com<mailto:knoel@redhat.com>>; Paolo Bonzini <pbonzini@redhat.com<mailto:pbonzini@redhat.com>>; Nathaniel McCallum <npmccallum@redhat.com<mailto:npmccallum@redhat.com>>; Dr. David Alan Gilbert <dgilbert@redhat.com<mailto:dgilbert@redhat.com>>; Ademar de Souza Reis Jr. <areis@redhat.com<mailto:areis@redhat.com>>
Subject: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Hi, All
We plan to do a design review for TDVF in OVMF package.


The TDVF Design slides for TinaoCore Design Review Meeting (Jun 11) is now available in blow link: https://edk2.groups.io/g/devel/files/Designs/2021/0611.

The Bugzilla is https://bugzilla.tianocore.org/show_bug.cgi?id=3429



You can have an offline review first. You comments will be warmly welcomed and we will continuously update the slides based on the feedbacks.



Thank you

Yao Jiewen







Re: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Laszlo Ersek
 

Hi,

On 06/11/21 08:37, Xu, Min M wrote:
In today's TianoCore Design Meeting we reviewed the Overview Section (from slide 1 to 20). Thanks much for the valuable feedbacks and comments. The meeting minutes will be sent out soon.

To address the concerns of the *one binary* solution in previous discussion, we propose 2 Configurations for TDVF to upstream. (slide 6 - 8)



Config-A:

* Merge the *basic* TDVF feature to existing OvmfX64Pkg.dsc. (Align with existing SEV)
* Threat model: VMM is NOT out of TCB. (We don't make things worse.)
* The OvmfX64Pkg.dsc includes SEV/TDX/normal OVMF basic boot capability. The final binary can run on SEV/TDX/normal OVMF
* No changes to existing OvmfPkgX64 image layout.
* No need to add additional security features if they do not exist today
* No need to remove features if they exist today.
* RTMR is not supported
* PEI phase is NOT skipped in either Td or Non-Td
(so this is "Config-A / Option B", per slide 9 in the v0.9 slide deck)




Config-B:

* Add a standalone IntelTdx.dsc to a TDX specific directory for a *full* feature TDVF. (Align with existing SEV)
* Threat model: VMM is out of TCB. (We need necessary change to prevent attack from VMM)
* IntelTdx.dsc includes TDX/normal OVMF basic boot capability. The final binary can run on TDX/normal OVMF
* It might eventually merge with AmdSev.dsc, but NOT at this point of time. And we don't know when it will happen. We need sync with AMD in the community, after both of us think the solutions are mature to merge.
* Need to add necessary security feature as mandatory requirement, such as RTMR based Trusted Boot support
* Need to remove unnecessary attack surfaces, such as network stack.
After reading the above, and checking slides 6 through 10 of the v0.9
slide deck:

- I prefer Config-B (IntelTdx.dsc).

This is in accordance with what I wrote earlier about "OvmfPkgX64.dsc"
maintainability and regressions.

Additionally (given that a full-featured TDVF is the ultimate goal), I
see the advance from "Config-A / option B" to "Config-B" a lot less
*incremental* than the step from "OvmfPkgX64.dsc" to "AmdSev.dsc" was.

Put differently, I think that any TDX work targeted at "OvmfPkgX64.dsc"
is going to prove less useful for the final "IntelTdx.dsc" than how
reusable SEV work from "OvmfPkgX64.dsc" did for "AmdSev.dsc".

Put yet differently, I'm concerned that a part of the TDX work for
"OvmfPkgX64.dsc" might be a waste, with an eye towards the ultimate TDVF
feature set ("IntelTdx.dsc").


- I could (very cautiously) live with "Config-A / option B" as the
initial approach. However, we'de have to be ready to make the full split
(the switch-over to "IntelTdx.dsc") at *any point* during development,
in case something turns out to be too intrusive. (And yes, "too
intrusive" is subjective.)

By this I mean that any particular patch towards "Config-A / option B"
could cause me to ask, "please create IntelTdx.dsc now". Note that the
later we make the switch the more painful it could be (= the more
invested in "OvmfPkgX64.dsc" we could be, at that point).

For example, as I stated earlier, "OvmfPkg/AcpiPlatformDxe" is a driver
where I'd like to see zero changes, for either SEV or TDX. If the TD
Mailbox location has to be reported to the OS via the MADT, and QEMU
cannot (or must not) populate that field in the MADT, then a separate,
TDX-specific edk2 driver should locate the MADT (installed technically
by "OvmfPkg/AcpiPlatformDxe", earlier), and update the field.

Thanks,
Laszlo

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Min Xu
Sent: Friday, June 11, 2021 6:30 AM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>; rfc@edk2.groups.io
Cc: jejb@linux.ibm.com; Laszlo Ersek <lersek@redhat.com>; Brijesh Singh <brijesh.singh@amd.com>; Tom Lendacky <thomas.lendacky@amd.com>; erdemaktas@google.com; cho@microsoft.com; bret.barkelew@microsoft.com; Jon Lange <jlange@microsoft.com>; Karen Noel <knoel@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Nathaniel McCallum <npmccallum@redhat.com>; Dr. David Alan Gilbert <dgilbert@redhat.com>; Ademar de Souza Reis Jr. <areis@redhat.com>
Subject: Re: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Hi, All
Thanks much for the valuable comments and discussion about the design.
We have updated the slides (v0.9) in below link. If some comments or concerns are not answered/addressed in the new slides, please don't hesitate to tell us. We do want to answer/address all the comments/concerns. But to be honest it is a rather complicated one and we appreciate your feedbacks.
https://edk2.groups.io/g/devel/files/Designs/2021/0611/TDVF_Design_Review%28v0.9%29.pptx

Thanks much!

Xu Min


From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> On Behalf Of Yao, Jiewen
Sent: Thursday, June 3, 2021 9:51 PM
To: rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Cc: jejb@linux.ibm.com<mailto:jejb@linux.ibm.com>; Laszlo Ersek <lersek@redhat.com<mailto:lersek@redhat.com>>; Brijesh Singh <brijesh.singh@amd.com<mailto:brijesh.singh@amd.com>>; Tom Lendacky <thomas.lendacky@amd.com<mailto:thomas.lendacky@amd.com>>; erdemaktas@google.com<mailto:erdemaktas@google.com>; cho@microsoft.com<mailto:cho@microsoft.com>; bret.barkelew@microsoft.com<mailto:bret.barkelew@microsoft.com>; Jon Lange <jlange@microsoft.com<mailto:jlange@microsoft.com>>; Karen Noel <knoel@redhat.com<mailto:knoel@redhat.com>>; Paolo Bonzini <pbonzini@redhat.com<mailto:pbonzini@redhat.com>>; Nathaniel McCallum <npmccallum@redhat.com<mailto:npmccallum@redhat.com>>; Dr. David Alan Gilbert <dgilbert@redhat.com<mailto:dgilbert@redhat.com>>; Ademar de Souza Reis Jr. <areis@redhat.com<mailto:areis@redhat.com>>
Subject: [edk2-rfc] [edk2-devel] RFC: design review for TDVF in OVMF

Hi, All
We plan to do a design review for TDVF in OVMF package.


The TDVF Design slides for TinaoCore Design Review Meeting (Jun 11) is now available in blow link: https://edk2.groups.io/g/devel/files/Designs/2021/0611.

The Bugzilla is https://bugzilla.tianocore.org/show_bug.cgi?id=3429



You can have an offline review first. You comments will be warmly welcomed and we will continuously update the slides based on the feedbacks.



Thank you

Yao Jiewen







[PATCH edk2-Platform v1 1/1] Hisilicon:Fix header file issues

wenyi,xie
 

EDK2 has removed header file ArmLibPrivate.h, so need to
use ArmLib.h instead. A new file OemMiscLib.h is added
to EDK2, its name is same with the header file in
Hisilicon\Include and it will being included first. So
some undefined issue occured and need to change the order
of header files.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
---
Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 2 +-
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +-
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h | 13 -------------
Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 2 +-
Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 2 +-
10 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
index 1f992024acc2..f1b21ae80f3c 100644
--- a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
+++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf
@@ -20,12 +20,12 @@
EarlyConfigPeimD03.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec

ArmPkg/ArmPkg.dec
Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
PeimEntryPoint
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
index ab14597d8b75..728b33e85030 100644
--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
@@ -21,11 +21,11 @@
BoardFeature2PHi1610Strings.uni

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
BaseMemoryLib
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
index d471102199ee..8a605b417be8 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -21,11 +21,11 @@
OemMiscLibD05.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
BaseMemoryLib
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
index 59373a968523..1121550b40c4 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
@@ -21,12 +21,12 @@
OemMiscLibD06.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Platform/Hisilicon/D06/D06.dec
Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
BaseMemoryLib
diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
index 99eea93b7988..2c3c1ff51408 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
@@ -21,12 +21,12 @@
ProcessorSubClass.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec

Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
UefiDriverEntryPoint
diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
index 9c795b5fd401..99cc8fc4c14e 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
@@ -48,11 +48,11 @@
./Type09/MiscSystemSlotDesignationFunction.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Hisilicon/HisiliconNonOsi.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
PcdLib
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
index 25d301f210ba..921dae6dd80a 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
@@ -21,10 +21,10 @@
PcieInitLib.c

[Packages]
+ Silicon/Hisilicon/HisiPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
- Silicon/Hisilicon/HisiPkg.dec

[LibraryClasses]
UefiDriverEntryPoint
diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
index 3ce180d21df3..3a51199e924b 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
+++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h
@@ -68,19 +68,6 @@ typedef union {
UINT16 Data;
}CACHE_CONFIGURATION;

-//
-// Processor Status
-//
-typedef union {
- struct {
- UINT8 CpuStatus :3; // Indicates the status of the processor.
- UINT8 Reserved1 :3; // Reserved for future use. Should be set to zero.
- UINT8 SocketPopulated :1; // Indicates if the processor socket is populated or not.
- UINT8 Reserved2 :1; // Reserved for future use. Should be set to zero.
- } Bits;
- UINT8 Data;
-}PROCESSOR_STATUS_DATA;
-
//
// Processor Characteristics
//
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
index a0ad31a990db..0cb9a6e31e65 100644
--- a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h
@@ -13,7 +13,7 @@
#define _PPTT_H_

#include <IndustryStandard/Acpi.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
+#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
index 30ba5fff65ce..7d8228503dba 100644
--- a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
+++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
@@ -14,7 +14,7 @@

#include <PlatformArch.h>
#include <IndustryStandard/Acpi.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
+#include <Library/ArmLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
--
2.20.1.windows.1


[PATCH edk2-Platform v1 0/1] Hisilicon:Fix header file issues

wenyi,xie
 

Main Changes :
1.Replace ArmLibPrivate.h with ArmLib.h
2.Cahnge order of dec in some inf file since there are same name header files
3.Remove redundant declaration of union PROCESSOR_STATUS_DATA

Wenyi Xie (1):
Hisilicon:Fix header file issues

Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 2 +-
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 2 +-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +-
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf | 2 +-
Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +-
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.h | 13 -------------
Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 2 +-
Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 2 +-
10 files changed, 9 insertions(+), 22 deletions(-)

--
2.20.1.windows.1


Re: Possibly incorrect size in memory profile structure

Marvin Häuser
 

Ahhh, I see it. The size does to describe the data structure that is existent at that point in time, but the one that is created by MemoryProfileCopyData() later, and the alignment is applied because it ends up as a flat structure array. Makes sense, thank you a lot!

Best regards,
Marvin

On 22.06.21 12:20, Zeng, Star wrote:
Not sure I can understand your question correctly. But try best to recall and comment since not on it for long time. 😊

[2], [3] and [4] are all for interior storage management by MEMORY_PROFILE_DRIVER_INFO_DATA, MEMORY_PROFILE_DRIVER_INFO_DATA.PdbString points to the PDB string.

Exterior storage are managed by ProfileProtocolGetData() and MemoryProfileCopyData() from interior storage, 8B alignment are for exterior storage, PDB string is at the end of MEMORY_PROFILE_DRIVER_INFO structure.


Thanks,
Star
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Marvin Häuser
Sent: 2021年6月19日 18:56
To: Zeng, Star <star.zeng@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io
Subject: [edk2-devel] Possibly incorrect size in memory profile structure

Good day,

I have a question regarding a part of the memory profiling code. Namely this piece of code [1] introduced storing the PDB file name among the driver information. This is implement by a string pointer in the "MEMORY_PROFILE_DRIVER_INFO_DATA" structure (which embeds the "MEMORY_PROFILE_DRIVER_INFO" structure [2]). The length of the embedded "MEMORY_PROFILE_DRIVER_INFO" instance is set to the header size plus the 8B-aligned size of the PDB name [3], albeit its storage is not used for the PDB file name, and the storage that is used instead is not aligned by 8B [4]. Ominously, the interior structure does have a comment that indicates it is (or was) supposed to hold the PDB file name at some point [5].

I do not see that concept being used, and instead see the previously described way of storage, so I believe the aligned size is a forgotten piece from a refactoring. I imagine early on, the interior structure was supposed to hold the PDB name, and the alignment was needed to satisfy the following data's requirements. However, the change to the exterior storage should make this superfluous, and the specified size seems to be incorrect in all cases.

Can you please give this a quick look and help me determine whether this is a bug? Thank you for your time!

Best regards,
Marvin

[1]
https://github.com/tianocore/edk2/commit/1d60fe96422206d37e1d74198bb11b2cf6195157#diff-b42ade68f10fa42dfa25570f0f9a165db4b974877c98d8845e384a40252ec220R407-R428

[2]
https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L25

[3]
https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L417

[4]
https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L404

[5]
https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Include/Guid/MemoryProfile.h#L59




Re: [PATCH v3 2/8] Platforms: add SecureBootVariableLib class resolution

Grzegorz Bernacki
 

Hi Laszlo,

I think I revert all the changes in all these files. I modified them
because I moved CreateTimeBasedPayload() to SecureBootVariableLib
library, but it created incorrect dependency on SecurityPkg from
MdeModulePkg. Anyway it needs another solution please check
https://edk2.groups.io/g/devel/message/76800 for details.
thanks,
greg

wt., 22 cze 2021 o 13:11 Laszlo Ersek <lersek@redhat.com> napisał(a):


Hi Grzegorz,

On 06/14/21 11:43, Grzegorz Bernacki wrote:
Update platform files to add SecureBootVariableLib for each
platform which uses SecureBootConfigDxe.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
ArmVirtPkg/ArmVirtQemu.dsc | 3 +++
ArmVirtPkg/ArmVirtQemuKernel.dsc | 3 +++
EmulatorPkg/EmulatorPkg.dsc | 1 +
OvmfPkg/Bhyve/BhyveX64.dsc | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 1 +
OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
OvmfPkg/OvmfPkgX64.dsc | 1 +
7 files changed, 11 insertions(+)
please split this patch in three (one patch per package), and assign
according subject lines to those patches as well.

I had some difficulties determining what I should look at in this patch
set at all (the subject in particular is unhelpful).

Thanks,
Laszlo



diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 7ef5e7297b..c9cb0ff4ae 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -82,6 +82,9 @@
PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf

+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
+!endif
!if $(TPM2_ENABLE) == TRUE
Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index a542fcb157..97b36e895e 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -81,6 +81,9 @@
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf

+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
+!endif
[LibraryClasses.common.DXE_DRIVER]
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index 20e5468398..966cc7af01 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -132,6 +132,7 @@
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index d8792812ab..f9c8131309 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -198,6 +198,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Bhyve/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index f53efeae79..9225966541 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -204,6 +204,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index b3662e17f2..5d53327edb 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -208,6 +208,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 0a237a9058..509acf7926 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -208,6 +208,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif


Re: [PATCH 1/1] MdeModulePkg: Add BootDiscoveryPolicyUiLib.

Wu, Hao A
 

-----Original Message-----
From: Grzegorz Bernacki <gjb@semihalf.com>
Sent: Tuesday, June 22, 2021 4:52 PM
To: devel@edk2.groups.io
Cc: leif@nuviainc.com; ardb+tianocore@kernel.org; Samer.El-Haj-
Mahmoud@arm.com; sunny.Wang@arm.com; mw@semihalf.com;
upstream@semihalf.com; pete@akeo.ie; Wang, Jian J <jian.j.wang@intel.com>;
Wu, Hao A <hao.a.wu@intel.com>; Bi, Dandan <dandan.bi@intel.com>; Dong,
Eric <eric.dong@intel.com>; Grzegorz Bernacki <gjb@semihalf.com>
Subject: [PATCH 1/1] MdeModulePkg: Add BootDiscoveryPolicyUiLib.

This library extends Boot Maintenance Menu and allows to select Boot
Discovery Policy. When choice is made BootDiscoveryPolicy variable is set.
Platform code can use this variable to decide which class of device shall be
connected.

(Adding Ray and Zhichao)

Hello Ray and Zhichao,

Could you help to review this patch? Thanks in advance.

Best Regards,
Hao Wu



Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
MdeModulePkg/MdeModulePkg.dec | 6 +
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf
| 52 +++++++
MdeModulePkg/Include/Guid/BootDiscoveryPolicy.h | 22
+++
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.c
| 160 ++++++++++++++++++++

MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.uni
| 18 +++

MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibStri
ngs.uni | 29 ++++

MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibVfr.
Vfr | 44 ++++++
7 files changed, 331 insertions(+)
create mode 100644
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.inf
create mode 100644 MdeModulePkg/Include/Guid/BootDiscoveryPolicy.h
create mode 100644
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.c
create mode 100644
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.uni
create mode 100644
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibStri
ngs.uni
create mode 100644
MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibVfr.
Vfr

diff --git a/MdeModulePkg/MdeModulePkg.dec
b/MdeModulePkg/MdeModulePkg.dec index 10602a8f79..1e65ad2dd7 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -422,6 +422,9 @@
## Include/UniversalPayload/ExtraData.h
gUniversalPayloadExtraDataGuid = {0x15a5baf6, 0x1c91, 0x467d, {0x9d, 0xfb,
0x31, 0x9d, 0x17, 0x8d, 0x4b, 0xb4}}

+ ## GUID used for Boot Discovery Policy FormSet guid and related variables.
+ gBootDiscoveryPolicyMgrFormsetGuid = { 0x5b6f7107, 0xbb3c, 0x4660, {
+ 0x92, 0xcd, 0x54, 0x26, 0x90, 0x28, 0x0b, 0xbd } }
+
[Ppis]
## Include/Ppi/AtaController.h
gPeiAtaControllerPpiGuid = { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0, 0x7a,
0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }}
@@ -1597,6 +1600,9 @@
# @Prompt Console Output Row of Text Setup

gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|25|UINT32|0x40000
00e

+ ## Specify the Boot Discovery Policy settings
+
gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy|0|UINT32|0x4000
0
+ 00f
+
[PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]

gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20|UINT3
2|0x0001004c

diff --git
a/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.i
nf
b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.i
nf
new file mode 100644
index 0000000000..1fb4d43caa
--- /dev/null
+++ b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyU
+++ iLib.inf
@@ -0,0 +1,52 @@
+## @file
+# Library for BDS phase to use Boot Discovery Policy # # Copyright
+(c) 2021, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2021,
+Semihalf All rights reserved.<BR> # SPDX-License-Identifier:
+BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BootDiscoveryPolicyUiLib
+ MODULE_UNI_FILE = BootDiscoveryPolicyUiLib.uni
+ FILE_GUID = BE73105A-B13D-4B57-A41A-463DBD15FE10
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|DXE_DRIVER UEFI_APPLICATION
+ CONSTRUCTOR = BootDiscoveryPolicyUiLibConstructor
+ DESTRUCTOR = BootDiscoveryPolicyUiLibDestructor
+#
+# The following information is for reference only and not required by the build
tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
+#
+
+[Sources]
+ BootDiscoveryPolicyUiLib.c
+ BootDiscoveryPolicyUiLibStrings.uni
+ BootDiscoveryPolicyUiLibVfr.Vfr
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ DevicePathLib
+ BaseLib
+ UefiRuntimeServicesTableLib
+ UefiBootServicesTableLib
+ DebugLib
+ HiiLib
+ UefiLib
+ BaseMemoryLib
+
+[Guids]
+ gBootDiscoveryPolicyMgrFormsetGuid
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy ## PRODUCES
+
+[Depex]
+ gEfiHiiDatabaseProtocolGuid AND gPcdProtocolGuid
diff --git a/MdeModulePkg/Include/Guid/BootDiscoveryPolicy.h
b/MdeModulePkg/Include/Guid/BootDiscoveryPolicy.h
new file mode 100644
index 0000000000..8eb0968a16
--- /dev/null
+++ b/MdeModulePkg/Include/Guid/BootDiscoveryPolicy.h
@@ -0,0 +1,22 @@
+/** @file
+ Definition for structure & defines exported by Boot Discovery Policy
+UI
+
+ Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> Copyright (c)
+ 2021, Semihalf All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOOT_DISCOVERY_POLICY_UI_LIB_H_ #define
+_BOOT_DISCOVERY_POLICY_UI_LIB_H_
+
+#define BDP_CONNECT_MINIMAL 0 /* Do not connect any additional devices
*/
+#define BDP_CONNECT_NET 1
+#define BDP_CONNECT_ALL 2
+
+#define BOOT_DISCOVERY_POLICY_MGR_FORMSET_GUID { 0x5b6f7107,
0xbb3c,
+0x4660, { 0x92, 0xcd, 0x54, 0x26, 0x90, 0x28, 0x0b, 0xbd } }
+
+#define BOOT_DISCOVERY_POLICY_VAR L"BootDiscoveryPolicy"
+
+#endif
diff --git
a/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.
c
b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.
c
new file mode 100644
index 0000000000..6814d0bb8f
--- /dev/null
+++ b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyU
+++ iLib.c
@@ -0,0 +1,160 @@
+/** @file
+ Boot Discovery Policy UI for Boot Maintenance menu.
+
+ Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> Copyright (c)
+ 2021, Semihalf All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Guid/BootDiscoveryPolicy.h>
+#include <Library/UefiDriverEntryPoint.h> #include
+<Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Include/Library/PcdLib.h>
+
+///
+/// HII specific Vendor Device Path definition.
+///
+typedef struct {
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} HII_VENDOR_DEVICE_PATH;
+
+extern unsigned char BootDiscoveryPolicyUiLibVfrBin[];
+
+EFI_HII_HANDLE mBPHiiHandle = NULL;
+EFI_HANDLE mBPDriverHandle = NULL;
+
+STATIC HII_VENDOR_DEVICE_PATH mVendorDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ {
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)
+ }
+ },
+ BOOT_DISCOVERY_POLICY_MGR_FORMSET_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ (UINT8)(END_DEVICE_PATH_LENGTH),
+ (UINT8)((END_DEVICE_PATH_LENGTH) >> 8)
+ }
+ }
+};
+
+/**
+
+ Initialize Boot Maintenance Menu library.
+
+ @param ImageHandle The image handle.
+ @param SystemTable The system table.
+
+ @retval EFI_SUCCESS Install Boot manager menu success.
+ @retval Other Return error status.gBPDisplayLibGuid
+
+**/
+EFI_STATUS
+EFIAPI
+BootDiscoveryPolicyUiLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Size;
+ UINT32 BootDiscoveryPolicy;
+
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (
+ BOOT_DISCOVERY_POLICY_VAR,
+ &gBootDiscoveryPolicyMgrFormsetGuid,
+ NULL,
+ &Size,
+ &BootDiscoveryPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, PcdGet32
(PcdBootDiscoveryPolicy));
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mBPDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mVendorDevicePath,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Publish our HII data
+ //
+ mBPHiiHandle = HiiAddPackages (
+ &gBootDiscoveryPolicyMgrFormsetGuid,
+ mBPDriverHandle,
+ BootDiscoveryPolicyUiLibVfrBin,
+ BootDiscoveryPolicyUiLibStrings,
+ NULL
+ );
+ if (mBPHiiHandle == NULL) {
+ gBS->UninstallMultipleProtocolInterfaces (
+ mBPDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mVendorDevicePath,
+ NULL
+ );
+
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Destructor of Boot Maintenance menu library.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The destructor completed successfully.
+ @retval Other value The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BootDiscoveryPolicyUiLibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+
+ if (mBPDriverHandle != NULL) {
+ gBS->UninstallProtocolInterface (
+ mBPDriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mVendorDevicePath
+ );
+ mBPDriverHandle = NULL;
+ }
+
+ if (mBPHiiHandle != NULL) {
+ HiiRemovePackages (mBPHiiHandle);
+ mBPHiiHandle = NULL;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git
a/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.
uni
b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLib.
uni
new file mode 100644
index 0000000000..eea3ca6c8d
--- /dev/null
+++ b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyU
+++ iLib.uni
@@ -0,0 +1,18 @@
+// /** @file
+// Boot Discovery Policy UI module.
+//
+// Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> // Copyright
+(c) 2021, Semihalf All rights reserved.<BR> // //
+SPDX-License-Identifier: BSD-2-Clause-Patent // // **/
+
+
+#string STR_MODULE_ABSTRACT
+#language en-US "Boot Discovery Policy UI module."
+
+#string STR_MODULE_DESCRIPTION
+#language en-US "Boot Discovery Policy UI module."
+
+
diff --git
a/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibS
trings.uni
b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibS
trings.uni
new file mode 100644
index 0000000000..736011c9bb
--- /dev/null
+++ b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyU
+++ iLibStrings.uni
@@ -0,0 +1,29 @@
+// *++
+//
+// Copyright (c) 2021, ARM Ltd. All rights reserved.<BR> // Copyright
+(c) 2021, Semihalf All rights reserved.<BR> //
+SPDX-License-Identifier: BSD-2-Clause-Patent // // Module Name:
+//
+// BootDiscoveryPolicyUiLibStrings.uni
+//
+// Abstract:
+//
+// String definitions for Boot Discovery Policy UI.
+//
+// --*/
+
+/=#
+
+
+#langdef en-US "English"
+
+#string STR_FORM_BDP_MAIN_TITLE #language en-US "Boot Discovery
Policy"
+
+#string STR_FORM_BDP_CONN_MIN #language en-US "Minimal"
+
+#string STR_FORM_BDP_CONN_NET #language en-US "Connect Network
Devices"
+
+#string STR_FORM_BDP_CONN_ALL #language en-US "Connect All
Devices"
+
diff --git
a/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibV
fr.Vfr
b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyUiLibV
fr.Vfr
new file mode 100644
index 0000000000..0de87ec34f
--- /dev/null
+++ b/MdeModulePkg/Library/BootDiscoveryPolicyUiLib/BootDiscoveryPolicyU
+++ iLibVfr.Vfr
@@ -0,0 +1,44 @@
+///** @file
+//
+// Formset for Boot Discovery Policy UI // // Copyright (c) 2021, ARM
+Ltd. All rights reserved.<BR> // Copyright (c) 2021, Semihalf All
+rights reserved.<BR> // // SPDX-License-Identifier:
+BSD-2-Clause-Patent // //**/
+
+#include <Uefi/UefiMultiPhase.h>
+#include "Guid/BootDiscoveryPolicy.h"
+#include <Guid/HiiBootMaintenanceFormset.h>
+
+typedef struct {
+ UINT32 BootDiscoveryPolicy;
+} BOOT_DISCOVERY_POLICY_VARSTORE_DATA;
+
+formset
+ guid = BOOT_DISCOVERY_POLICY_MGR_FORMSET_GUID,
+ title = STRING_TOKEN(STR_FORM_BDP_MAIN_TITLE),
+ help = STRING_TOKEN(STR_FORM_BDP_MAIN_TITLE),
+ classguid = EFI_IFR_BOOT_MAINTENANCE_GUID,
+
+ efivarstore BOOT_DISCOVERY_POLICY_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = BootDiscoveryPolicy,
+ guid = BOOT_DISCOVERY_POLICY_MGR_FORMSET_GUID;
+
+ form formid = 0x0001,
+ title = STRING_TOKEN(STR_FORM_BDP_MAIN_TITLE);
+
+ oneof varid = BootDiscoveryPolicy.BootDiscoveryPolicy,
+ prompt = STRING_TOKEN(STR_FORM_BDP_MAIN_TITLE),
+ help = STRING_TOKEN(STR_FORM_BDP_MAIN_TITLE),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_FORM_BDP_CONN_MIN), value =
BDP_CONNECT_MINIMAL, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_FORM_BDP_CONN_NET), value =
BDP_CONNECT_NET, flags = 0;
+ option text = STRING_TOKEN(STR_FORM_BDP_CONN_ALL), value =
+ BDP_CONNECT_ALL, flags = 0; endoneof;
+
+ endform;
+endformset;
--
2.25.1


Re: [PATCH v3 2/8] Platforms: add SecureBootVariableLib class resolution

Laszlo Ersek
 

Hi Grzegorz,

On 06/14/21 11:43, Grzegorz Bernacki wrote:
Update platform files to add SecureBootVariableLib for each
platform which uses SecureBootConfigDxe.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
ArmVirtPkg/ArmVirtQemu.dsc | 3 +++
ArmVirtPkg/ArmVirtQemuKernel.dsc | 3 +++
EmulatorPkg/EmulatorPkg.dsc | 1 +
OvmfPkg/Bhyve/BhyveX64.dsc | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 1 +
OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
OvmfPkg/OvmfPkgX64.dsc | 1 +
7 files changed, 11 insertions(+)
please split this patch in three (one patch per package), and assign
according subject lines to those patches as well.

I had some difficulties determining what I should look at in this patch
set at all (the subject in particular is unhelpful).

Thanks,
Laszlo



diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index 7ef5e7297b..c9cb0ff4ae 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -82,6 +82,9 @@
PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf

+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
+!endif
!if $(TPM2_ENABLE) == TRUE
Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTcg2PhysicalPresenceLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index a542fcb157..97b36e895e 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -81,6 +81,9 @@
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf

+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
+!endif
[LibraryClasses.common.DXE_DRIVER]
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc
index 20e5468398..966cc7af01 100644
--- a/EmulatorPkg/EmulatorPkg.dsc
+++ b/EmulatorPkg/EmulatorPkg.dsc
@@ -132,6 +132,7 @@
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index d8792812ab..f9c8131309 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -198,6 +198,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Bhyve/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index f53efeae79..9225966541 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -204,6 +204,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index b3662e17f2..5d53327edb 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -208,6 +208,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 0a237a9058..509acf7926 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -208,6 +208,7 @@
!if $(SECURE_BOOT_ENABLE) == TRUE
PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
!else
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
!endif


Re: [PATCH RESEND v1 0/2] ArmVirtPkg: Enable PCIe support for Kvmtool

Laszlo Ersek
 

On 06/21/21 15:43, Alexandru Elisei wrote:
Hi Pierre,

On 6/15/21 4:21 PM, PierreGondois via groups.io wrote:
From: Pierre Gondois <Pierre.Gondois@arm.com>

PCIe support has been added to the Kvmtool virtual machine
manager. Therefore, add a PciHostBridgeUtilityLib and enable
PCIe support for Kvmtool firmware.

The patches were re-send as the devel@edk2.groups.io was not included.

The patches can be seen at: https://github.com/PierreARM/edk2/tree/1413_Enable_ArmVirt_Pci_v1
The results of the CI can be seen at: https://github.com/tianocore/edk2/pull/1718
Tested the patches with the latest version of the kvmtool PCI Express support [1],
and everything worked as expected. A summary of the tests that I ran can be found
at [1]. So you can add for the entire series:

Tested-by: Alexandru Elisei <alexandru.elisei@arm.com>

One thing of note is that applying patch #2 of this series on top of 11b1c1d4b98b
("SecurityPkg: TcgStorageOpalLib: Initialize SupportedAttributes parameter")
failed.
If there is a conflict that needs to be resolved, then Pierre, can you
please repost?

Otherwise: Sami, can you please merge the series with Ard's and Alex's tags?

Thanks!
Laszlo


However, building from your repo went fine, and the binary that I used for
testing was built from your repo.

[1] https://lore.kernel.org/kvm/20210621092128.11313-1-alexandru.elisei@arm.com/

Thanks,

Alex


Sami Mujawar (2):
ArmVirtPkg: Add PCIe host bridge utility lib for ArmVirtPkg
ArmVirtPkg: Enable PCIe support for Kvmtool

ArmVirtPkg/ArmVirtKvmTool.dsc | 35 ++-
ArmVirtPkg/ArmVirtKvmTool.fdf | 11 +-
.../ArmVirtPciHostBridgeUtilityLib.c | 219 ++++++++++++++++++
.../ArmVirtPciHostBridgeUtilityLib.inf | 39 ++++
4 files changed, 301 insertions(+), 3 deletions(-)
create mode 100644 ArmVirtPkg/Library/ArmVirtPciHostBridgeUtilityLib/ArmVirtPciHostBridgeUtilityLib.c
create mode 100644 ArmVirtPkg/Library/ArmVirtPciHostBridgeUtilityLib/ArmVirtPciHostBridgeUtilityLib.inf



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