Date   

[PATCH 04/12] UefiPayloadPkg: Update the function definition of HobConstructor

Zhiguang Liu
 

Update the function defination of HobConstructor to align the Phit Hob
structure.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c | 26 +++++++++++++-----=
--------
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 5 +----
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 16 ++++++++--------
3 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c b/UefiPayloadP=
kg/Library/PayloadEntryHobLib/Hob.c
index 23a749edf1..768c3db770 100644
--- a/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c
+++ b/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c
@@ -39,14 +39,14 @@ GetHobList (
/**=0D
Build a Handoff Information Table HOB=0D
=0D
- This function initialize a HOB region from EfiMemoryBegin with length=0D
- EfiMemoryLength. And EfiFreeMemoryBottom and EfiFreeMemoryTop should=0D
+ This function initialize a HOB region from EfiMemoryBegin to=0D
+ EfiMemoryTop. And EfiFreeMemoryBottom and EfiFreeMemoryTop should=0D
be inside the HOB region.=0D
=0D
- @param[in] EfiMemoryBegin Total memory start address=0D
- @param[in] EfiMemoryLength Total memory length reported in handoff =
HOB.=0D
- @param[in] EfiFreeMemoryBottom Free memory start address=0D
- @param[in] EfiFreeMemoryTop Free memory end address.=0D
+ @param[in] EfiMemoryBottom Total memory start address=0D
+ @param[in] EfiMemoryTop Total memory end address.=0D
+ @param[in] EfiFreeMemoryBottom Free memory start address=0D
+ @param[in] EfiFreeMemoryTop Free memory end address.=0D
=0D
@return The pointer to the handoff HOB table.=0D
=0D
@@ -54,8 +54,8 @@ GetHobList (
EFI_HOB_HANDOFF_INFO_TABLE*=0D
EFIAPI=0D
HobConstructor (=0D
- IN VOID *EfiMemoryBegin,=0D
- IN UINTN EfiMemoryLength,=0D
+ IN VOID *EfiMemoryBottom,=0D
+ IN VOID *EfiMemoryTop,=0D
IN VOID *EfiFreeMemoryBottom,=0D
IN VOID *EfiFreeMemoryTop=0D
)=0D
@@ -77,11 +77,11 @@ HobConstructor (
Hob->Version =3D EFI_HOB_HANDOFF_TABLE_VERSION;=0D
Hob->BootMode =3D BOOT_WITH_FULL_CONFIGURATION;=0D
=0D
- Hob->EfiMemoryTop =3D (UINTN)EfiMemoryBegin + EfiMemoryLength;=0D
- Hob->EfiMemoryBottom =3D (UINTN)EfiMemoryBegin;=0D
- Hob->EfiFreeMemoryTop =3D (UINTN)EfiFreeMemoryTop;=0D
- Hob->EfiFreeMemoryBottom =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(HobEnd+1);=0D
- Hob->EfiEndOfHobList =3D (EFI_PHYSICAL_ADDRESS)(UINTN)HobEnd;=0D
+ Hob->EfiMemoryTop =3D (EFI_PHYSICAL_ADDRESS) EfiMemoryTop;=0D
+ Hob->EfiMemoryBottom =3D (EFI_PHYSICAL_ADDRESS) EfiMemoryBottom;=0D
+ Hob->EfiFreeMemoryTop =3D (EFI_PHYSICAL_ADDRESS) EfiFreeMemoryTop;=0D
+ Hob->EfiFreeMemoryBottom =3D (EFI_PHYSICAL_ADDRESS) (UINTN) (HobEnd+1);=
=0D
+ Hob->EfiEndOfHobList =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HobEnd;=0D
=0D
mHobList =3D Hob;=0D
return Hob;=0D
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c b/UefiPaylo=
adPkg/UefiPayloadEntry/UefiPayloadEntry.c
index 8c6f7e326f..4308936d63 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -382,7 +382,6 @@ PayloadEntry (
PHYSICAL_ADDRESS DxeCoreEntryPoint;=0D
EFI_HOB_HANDOFF_INFO_TABLE *HandoffHobTable;=0D
UINTN MemBase;=0D
- UINTN MemSize;=0D
UINTN HobMemBase;=0D
UINTN HobMemTop;=0D
EFI_PEI_HOB_POINTERS Hob;=0D
@@ -401,9 +400,7 @@ PayloadEntry (
HobMemBase =3D ALIGN_VALUE (MemBase + PcdGet32 (PcdPayloadFdMemSize), SI=
ZE_1MB);=0D
HobMemTop =3D HobMemBase + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize=
);=0D
=0D
- // DXE core assumes the memory below HOB region could be used, so includ=
e the FV region memory into HOB range.=0D
- MemSize =3D HobMemTop - MemBase;=0D
- HandoffHobTable =3D HobConstructor ((VOID *)MemBase, MemSize, (VOID *)Ho=
bMemBase, (VOID *)HobMemTop);=0D
+ HobConstructor ((VOID *)MemBase, (VOID *)HobMemTop, (VOID *)HobMemBase, =
(VOID *)HobMemTop);=0D
=0D
// Build HOB based on information from Bootloader=0D
Status =3D BuildHobFromBl ();=0D
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h b/UefiPaylo=
adPkg/UefiPayloadEntry/UefiPayloadEntry.h
index a4c9da128e..e9c3ec3073 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
@@ -83,14 +83,14 @@ UpdateStackHob (
/**=0D
Build a Handoff Information Table HOB=0D
=0D
- This function initialize a HOB region from EfiMemoryBegin with length=0D
- EfiMemoryLength. And EfiFreeMemoryBottom and EfiFreeMemoryTop should=0D
+ This function initialize a HOB region from EfiMemoryBegin to=0D
+ EfiMemoryTop. And EfiFreeMemoryBottom and EfiFreeMemoryTop should=0D
be inside the HOB region.=0D
=0D
- @param[in] EfiMemoryBegin Total memory start address=0D
- @param[in] EfiMemoryLength Total memory length reported in handoff =
HOB.=0D
- @param[in] EfiFreeMemoryBottom Free memory start address=0D
- @param[in] EfiFreeMemoryTop Free memory end address.=0D
+ @param[in] EfiMemoryBottom Total memory start address=0D
+ @param[in] EfiMemoryTop Total memory end address.=0D
+ @param[in] EfiFreeMemoryBottom Free memory start address=0D
+ @param[in] EfiFreeMemoryTop Free memory end address.=0D
=0D
@return The pointer to the handoff HOB table.=0D
=0D
@@ -98,8 +98,8 @@ UpdateStackHob (
EFI_HOB_HANDOFF_INFO_TABLE*=0D
EFIAPI=0D
HobConstructor (=0D
- IN VOID *EfiMemoryBegin,=0D
- IN UINTN EfiMemoryLength,=0D
+ IN VOID *EfiMemoryBottom,=0D
+ IN VOID *EfiMemoryTop,=0D
IN VOID *EfiFreeMemoryBottom,=0D
IN VOID *EfiFreeMemoryTop=0D
);=0D
--=20
2.16.2.windows.1


[PATCH 03/12] UefiPayloadPkg: Add a separate PlatformHookLib for Universal Payload

Zhiguang Liu
 

Add a new separate PlatformHookLib for Universal Payload to consume Guid
Hob gUniversalPayloadSerialPortInfoGuid to get serial port information

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c =
| 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf=
| 41 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 123 insertions(+)

diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/Platfor=
mHookLib.c b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/Platfor=
mHookLib.c
new file mode 100644
index 0000000000..6705f29505
--- /dev/null
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLi=
b.c
@@ -0,0 +1,82 @@
+/** @file=0D
+ Platform Hook Library instance for UART device.=0D
+=0D
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Base.h>=0D
+#include <PiDxe.h>=0D
+#include <UniversalPayload/SerialPortInfo.h>=0D
+#include <Library/PlatformHookLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <Library/HobLib.h>=0D
+=0D
+/**=0D
+ Performs platform specific initialization required for the CPU to access=
=0D
+ the hardware associated with a SerialPortLib instance. This function do=
es=0D
+ not initialize the serial port hardware itself. Instead, it initializes=
=0D
+ hardware devices that are required for the CPU to access the serial port=
=0D
+ hardware. This function may be called more than once.=0D
+=0D
+ @retval RETURN_SUCCESS The platform specific initialization succee=
ded.=0D
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could =
not be completed.=0D
+=0D
+**/=0D
+RETURN_STATUS=0D
+EFIAPI=0D
+PlatformHookSerialPortInitialize (=0D
+ VOID=0D
+ )=0D
+{=0D
+ RETURN_STATUS Status;=0D
+ UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *SerialPortInfo;=0D
+ UINT8 *GuidHob;=0D
+ UNIVERSAL_PAYLOAD_GENERIC_HEADER *GenericHeader;=0D
+=0D
+ GuidHob =3D GetFirstGuidHob (&gUniversalPayloadSerialPortInfoGuid);=0D
+ if (GuidHob =3D=3D NULL) {=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ GenericHeader =3D (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DATA=
(GuidHob);=0D
+ if ((sizeof (UNIVERSAL_PAYLOAD_GENERIC_HEADER) > GET_GUID_HOB_DATA_SIZE =
(GuidHob)) || (GenericHeader->Length > GET_GUID_HOB_DATA_SIZE (GuidHob))) {=
=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ if (GenericHeader->Revision =3D=3D UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_RE=
VISION) {=0D
+ SerialPortInfo =3D (UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *) GET_GUID_HOB=
_DATA (GuidHob);=0D
+ if (GenericHeader->Length < UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD (UN=
IVERSAL_PAYLOAD_SERIAL_PORT_INFO, RegisterBase)) {=0D
+ //=0D
+ // Return if can't find the Serial Port Info Hob with enough length=
=0D
+ //=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ Status =3D PcdSetBoolS (PcdSerialUseMmio, SerialPortInfo->UseMmio);=0D
+ if (RETURN_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ Status =3D PcdSet64S (PcdSerialRegisterBase, SerialPortInfo->RegisterB=
ase);=0D
+ if (RETURN_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ Status =3D PcdSet32S (PcdSerialRegisterStride, SerialPortInfo->Registe=
rStride);=0D
+ if (RETURN_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ Status =3D PcdSet32S (PcdSerialBaudRate, SerialPortInfo->BaudRate);=0D
+ if (RETURN_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ Status =3D PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate=
);=0D
+ if (RETURN_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ return RETURN_SUCCESS;=0D
+ }=0D
+=0D
+ return EFI_NOT_FOUND;=0D
+}=0D
diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/Platfor=
mHookLib.inf b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/Platf=
ormHookLib.inf
new file mode 100644
index 0000000000..41e05ddf54
--- /dev/null
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLi=
b.inf
@@ -0,0 +1,41 @@
+## @file=0D
+# Platform Hook Library instance for UART device for Universal Payload.=0D
+#=0D
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PlatformHookLib=0D
+ FILE_GUID =3D 807E05AB-9411-429F-97F0-FE425BF6B094=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D PlatformHookLib=0D
+ CONSTRUCTOR =3D PlatformHookSerialPortInitialize=0D
+=0D
+[Sources]=0D
+ PlatformHookLib.c=0D
+=0D
+[LibraryClasses]=0D
+ PcdLib=0D
+ BaseLib=0D
+ HobLib=0D
+ DxeHobListLib=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ UefiPayloadPkg/UefiPayloadPkg.dec=0D
+=0D
+[Guids]=0D
+ gUniversalPayloadSerialPortInfoGuid=0D
+=0D
+[Pcd]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES=0D
--=20
2.16.2.windows.1


[PATCH 02/12] MdeModulePkg: Add new structure for the Universal Payload Serial Port Info

Zhiguang Liu
 

Add Universal Payload Serial Port Info definition header file according to
Universal Payload's documentation as below:
https://universalpayload.github.io/documentation/

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h | 30 ++++++++++++++=
++++++++++++++++
MdeModulePkg/MdeModulePkg.dec | 3 +++
2 files changed, 33 insertions(+)

diff --git a/MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h b/MdeMo=
dulePkg/Include/UniversalPayload/SerialPortInfo.h
new file mode 100644
index 0000000000..87181f7634
--- /dev/null
+++ b/MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h
@@ -0,0 +1,30 @@
+/** @file=0D
+ This file defines the structure for serial port info.=0D
+=0D
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+ @par Revision Reference:=0D
+ - Universal Payload Specification 0.75 (https://universalpayload.githu=
b.io/documentation/)=0D
+**/=0D
+=0D
+#ifndef UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_H_=0D
+#define UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_H_=0D
+=0D
+#include <UniversalPayload/UniversalPayload.h>=0D
+=0D
+#pragma pack(1)=0D
+typedef struct {=0D
+ UNIVERSAL_PAYLOAD_GENERIC_HEADER Header;=0D
+ BOOLEAN UseMmio;=0D
+ UINT8 RegisterStride;=0D
+ UINT32 BaudRate;=0D
+ EFI_PHYSICAL_ADDRESS RegisterBase;=0D
+} UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO;=0D
+#pragma pack()=0D
+=0D
+#define UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_REVISION 1=0D
+=0D
+extern GUID gUniversalPayloadSerialPortInfoGuid;=0D
+=0D
+#endif // UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_H_=0D
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 10602a8f79..ad84421cf3 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -422,6 +422,9 @@
## Include/UniversalPayload/ExtraData.h=0D
gUniversalPayloadExtraDataGuid =3D {0x15a5baf6, 0x1c91, 0x467d, {0x9d, 0=
xfb, 0x31, 0x9d, 0x17, 0x8d, 0x4b, 0xb4}}=0D
=0D
+ ## Include/UniversalPayload/SerialPortInfo.h=0D
+ gUniversalPayloadSerialPortInfoGuid =3D { 0xaa7e190d, 0xbe21, 0x4409, { =
0x8e, 0x67, 0xa2, 0xcd, 0xf, 0x61, 0xe1, 0x70 } }=0D
+=0D
[Ppis]=0D
## Include/Ppi/AtaController.h=0D
gPeiAtaControllerPpiGuid =3D { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0,=
0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }}=0D
--=20
2.16.2.windows.1


[PATCH 01/12] UefiPayloadPkg: Add HobLib for UniversalPayload

Zhiguang Liu
 

For payload entry, use PayloadEntryHobLib as HobLib and payload entry
should initialize hob base.
For DxeCore, use new added DxeHobLib as HobLib, and DxeCore will
initialize hob base.
For Dxe Driver, use new added DxeHobLib as HobLib, and use DxeHobListLib
to initialize hob base.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Include/Library/DxeHobListLib.h | 27 +++=
++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf | 40 +++=
+++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.uni | 17 +++=
++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/HobLib.c | 597 +++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c | 66 +++=
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf | 35 +++=
++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c | 20 +++=
+++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf | 28 +++=
+++++++++++++++++++++++++
UefiPayloadPkg/Library/{HobLib =3D> PayloadEntryHobLib}/Hob.c | 2 +-
UefiPayloadPkg/Library/{HobLib =3D> PayloadEntryHobLib}/HobLib.inf | 2 +-
UefiPayloadPkg/UefiPayloadPkg.dsc | 15 +++=
++++++++----
11 files changed, 843 insertions(+), 6 deletions(-)

diff --git a/UefiPayloadPkg/Include/Library/DxeHobListLib.h b/UefiPayloadPk=
g/Include/Library/DxeHobListLib.h
new file mode 100644
index 0000000000..7e9b23f6d7
--- /dev/null
+++ b/UefiPayloadPkg/Include/Library/DxeHobListLib.h
@@ -0,0 +1,27 @@
+/** @file=0D
+ Provides a service to retrieve a pointer to the start of HOB list.=0D
+ Only available to DXE module types.=0D
+=0D
+ This library does not contain any functions or macros. It simply export=
s a global=0D
+ pointer to the start of HOB list as defined in the Platform Initializati=
on Driver=0D
+ Execution Environment Core Interface Specification. The library constru=
ctor must=0D
+ initialize this global pointer to the start of HOB list, so it is availa=
ble at the=0D
+ module's entry point. Since there is overhead in looking up the pointer=
to the start=0D
+ of HOB list, only those modules that actually require access to the HOB =
list=0D
+ should use this library.=0D
+=0D
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef __DXE_HOB_LIST_LIB_H__=0D
+#define __DXE_HOB_LIST_LIB_H__=0D
+=0D
+///=0D
+/// Cache copy of the start of HOB list=0D
+///=0D
+extern VOID *gHobList;=0D
+=0D
+#endif=0D
+=0D
diff --git a/UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf b/UefiPayloadPk=
g/Library/DxeHobLib/DxeHobLib.inf
new file mode 100644
index 0000000000..a146befd25
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf
@@ -0,0 +1,40 @@
+## @file=0D
+# Instance of HOB Library using HOB list from EFI Configuration Table.=0D
+#=0D
+# HOB Library implementation that retrieves the HOB List=0D
+# from the System Configuration Table in the EFI System Table.=0D
+#=0D
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D DxeHobLib=0D
+ MODULE_UNI_FILE =3D DxeHobLib.uni=0D
+ FILE_GUID =3D 1a15b8b3-3e8a-4698-87b9-65aad9993b52=
=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER =
SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER=0D
+=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D
+#=0D
+=0D
+[Sources]=0D
+ HobLib.c=0D
+=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ UefiPayloadPkg/UefiPayloadPkg.dec=0D
+=0D
+=0D
+[LibraryClasses]=0D
+ BaseMemoryLib=0D
+ DebugLib=0D
+ UefiLib=0D
+ DxeHobListLib=0D
diff --git a/UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.uni b/UefiPayloadPk=
g/Library/DxeHobLib/DxeHobLib.uni
new file mode 100644
index 0000000000..f1a18b7984
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.uni
@@ -0,0 +1,17 @@
+// /** @file=0D
+// Instance of HOB Library using HOB list from EFI Configuration Table.=0D
+//=0D
+// HOB Library implementation that retrieves the HOB List=0D
+// from the System Configuration Table in the EFI System Table.=0D
+//=0D
+// Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+//=0D
+// SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+//=0D
+// **/=0D
+=0D
+=0D
+#string STR_MODULE_ABSTRACT #language en-US "Instance of HOB L=
ibrary using HOB list from EFI Configuration Table"=0D
+=0D
+#string STR_MODULE_DESCRIPTION #language en-US "The HOB Library i=
mplementation that retrieves the HOB List from the System Configuration Tab=
le in the EFI System Table."=0D
+=0D
diff --git a/UefiPayloadPkg/Library/DxeHobLib/HobLib.c b/UefiPayloadPkg/Lib=
rary/DxeHobLib/HobLib.c
new file mode 100644
index 0000000000..8a2e773c59
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobLib/HobLib.c
@@ -0,0 +1,597 @@
+/** @file=0D
+ HOB Library implementation for Payload Phase.=0D
+=0D
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <PiDxe.h>=0D
+=0D
+#include <Library/HobLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DxeHobListLib.h>=0D
+=0D
+/**=0D
+ Returns the pointer to the HOB list.=0D
+=0D
+ This function returns the pointer to first HOB in the list.=0D
+ For PEI phase, the PEI service GetHobList() can be used to retrieve the =
pointer=0D
+ to the HOB list. For the DXE phase, the HOB list pointer can be retriev=
ed through=0D
+ the EFI System Table by looking up theHOB list GUID in the System Config=
uration Table.=0D
+ Since the System Configuration Table does not exist that the time the DX=
E Core is=0D
+ launched, the DXE Core uses a global variable from the DXE Core Entry Po=
int Library=0D
+ to manage the pointer to the HOB list.=0D
+=0D
+ If the pointer to the HOB list is NULL, then ASSERT().=0D
+=0D
+ @return The pointer to the HOB list.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+GetHobList (=0D
+ VOID=0D
+ )=0D
+{=0D
+ ASSERT (gHobList !=3D NULL);=0D
+ return gHobList;=0D
+}=0D
+=0D
+/**=0D
+ Returns the next instance of a HOB type from the starting HOB.=0D
+=0D
+ This function searches the first instance of a HOB type from the startin=
g HOB pointer.=0D
+ If there does not exist such HOB type from the starting HOB pointer, it =
will return NULL.=0D
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the s=
tarting HOB pointer=0D
+ unconditionally: it returns HobStart back if HobStart itself meets the r=
equirement;=0D
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current Ho=
bStart.=0D
+=0D
+ If HobStart is NULL, then ASSERT().=0D
+=0D
+ @param Type The HOB type to return.=0D
+ @param HobStart The starting HOB pointer to search from.=0D
+=0D
+ @return The next instance of a HOB type from the starting HOB.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+GetNextHob (=0D
+ IN UINT16 Type,=0D
+ IN CONST VOID *HobStart=0D
+ )=0D
+{=0D
+ EFI_PEI_HOB_POINTERS Hob;=0D
+=0D
+ ASSERT (HobStart !=3D NULL);=0D
+=0D
+ Hob.Raw =3D (UINT8 *) HobStart;=0D
+ //=0D
+ // Parse the HOB list until end of list or matching type is found.=0D
+ //=0D
+ while (!END_OF_HOB_LIST (Hob)) {=0D
+ if (Hob.Header->HobType =3D=3D Type) {=0D
+ return Hob.Raw;=0D
+ }=0D
+ Hob.Raw =3D GET_NEXT_HOB (Hob);=0D
+ }=0D
+ return NULL;=0D
+}=0D
+=0D
+/**=0D
+ Returns the first instance of a HOB type among the whole HOB list.=0D
+=0D
+ This function searches the first instance of a HOB type among the whole =
HOB list.=0D
+ If there does not exist such HOB type in the HOB list, it will return NU=
LL.=0D
+=0D
+ If the pointer to the HOB list is NULL, then ASSERT().=0D
+=0D
+ @param Type The HOB type to return.=0D
+=0D
+ @return The next instance of a HOB type from the starting HOB.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+GetFirstHob (=0D
+ IN UINT16 Type=0D
+ )=0D
+{=0D
+ VOID *HobList;=0D
+=0D
+ HobList =3D GetHobList ();=0D
+ return GetNextHob (Type, HobList);=0D
+}=0D
+=0D
+/**=0D
+ Returns the next instance of the matched GUID HOB from the starting HOB.=
=0D
+=0D
+ This function searches the first instance of a HOB from the starting HOB=
pointer.=0D
+ Such HOB should satisfy two conditions:=0D
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION, and its GUID Name equals to=
the input Guid.=0D
+ If such a HOB from the starting HOB pointer does not exist, it will retu=
rn NULL.=0D
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_S=
IZE ()=0D
+ to extract the data section and its size information, respectively.=0D
+ In contrast with macro GET_NEXT_HOB(), this function does not skip the s=
tarting HOB pointer=0D
+ unconditionally: it returns HobStart back if HobStart itself meets the r=
equirement;=0D
+ caller is required to use GET_NEXT_HOB() if it wishes to skip current Ho=
bStart.=0D
+=0D
+ If Guid is NULL, then ASSERT().=0D
+ If HobStart is NULL, then ASSERT().=0D
+=0D
+ @param Guid The GUID to match with in the HOB list.=0D
+ @param HobStart A pointer to a Guid.=0D
+=0D
+ @return The next instance of the matched GUID HOB from the starting HOB.=
=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+GetNextGuidHob (=0D
+ IN CONST EFI_GUID *Guid,=0D
+ IN CONST VOID *HobStart=0D
+ )=0D
+{=0D
+ EFI_PEI_HOB_POINTERS GuidHob;=0D
+=0D
+ GuidHob.Raw =3D (UINT8 *) HobStart;=0D
+ while ((GuidHob.Raw =3D GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob=
.Raw)) !=3D NULL) {=0D
+ if (CompareGuid (Guid, &GuidHob.Guid->Name)) {=0D
+ break;=0D
+ }=0D
+ GuidHob.Raw =3D GET_NEXT_HOB (GuidHob);=0D
+ }=0D
+ return GuidHob.Raw;=0D
+}=0D
+=0D
+/**=0D
+ Returns the first instance of the matched GUID HOB among the whole HOB l=
ist.=0D
+=0D
+ This function searches the first instance of a HOB among the whole HOB l=
ist.=0D
+ Such HOB should satisfy two conditions:=0D
+ its HOB type is EFI_HOB_TYPE_GUID_EXTENSION and its GUID Name equals to =
the input Guid.=0D
+ If such a HOB from the starting HOB pointer does not exist, it will retu=
rn NULL.=0D
+ Caller is required to apply GET_GUID_HOB_DATA () and GET_GUID_HOB_DATA_S=
IZE ()=0D
+ to extract the data section and its size information, respectively.=0D
+=0D
+ If the pointer to the HOB list is NULL, then ASSERT().=0D
+ If Guid is NULL, then ASSERT().=0D
+=0D
+ @param Guid The GUID to match with in the HOB list.=0D
+=0D
+ @return The first instance of the matched GUID HOB among the whole HOB l=
ist.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+GetFirstGuidHob (=0D
+ IN CONST EFI_GUID *Guid=0D
+ )=0D
+{=0D
+ VOID *HobList;=0D
+=0D
+ HobList =3D GetHobList ();=0D
+ return GetNextGuidHob (Guid, HobList);=0D
+}=0D
+=0D
+/**=0D
+ Get the system boot mode from the HOB list.=0D
+=0D
+ This function returns the system boot mode information from the=0D
+ PHIT HOB in HOB list.=0D
+=0D
+ If the pointer to the HOB list is NULL, then ASSERT().=0D
+=0D
+ @param VOID=0D
+=0D
+ @return The Boot Mode.=0D
+=0D
+**/=0D
+EFI_BOOT_MODE=0D
+EFIAPI=0D
+GetBootModeHob (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;=0D
+=0D
+ HandOffHob =3D (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();=0D
+=0D
+ return HandOffHob->BootMode;=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB for a loaded PE32 module.=0D
+=0D
+ This function builds a HOB for a loaded PE32 module.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If ModuleName is NULL, then ASSERT().=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param ModuleName The GUID File Name of the module.=0D
+ @param MemoryAllocationModule The 64 bit physical address of the modul=
e.=0D
+ @param ModuleLength The length of the module in bytes.=0D
+ @param EntryPoint The 64 bit physical address of the modul=
e entry point.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildModuleHob (=0D
+ IN CONST EFI_GUID *ModuleName,=0D
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,=0D
+ IN UINT64 ModuleLength,=0D
+ IN EFI_PHYSICAL_ADDRESS EntryPoint=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB that describes a chunk of system memory with Owner GUID.=0D
+=0D
+ This function builds a HOB that describes a chunk of system memory.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase=
.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param ResourceType The type of resource described by this HOB.=
=0D
+ @param ResourceAttribute The resource attributes of the memory descri=
bed by this HOB.=0D
+ @param PhysicalStart The 64 bit physical address of memory descri=
bed by this HOB.=0D
+ @param NumberOfBytes The length of the memory described by this H=
OB in bytes.=0D
+ @param OwnerGUID GUID for the owner of this resource.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildResourceDescriptorWithOwnerHob (=0D
+ IN EFI_RESOURCE_TYPE ResourceType,=0D
+ IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,=0D
+ IN EFI_PHYSICAL_ADDRESS PhysicalStart,=0D
+ IN UINT64 NumberOfBytes,=0D
+ IN EFI_GUID *OwnerGUID=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB that describes a chunk of system memory.=0D
+=0D
+ This function builds a HOB that describes a chunk of system memory.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param ResourceType The type of resource described by this HOB.=
=0D
+ @param ResourceAttribute The resource attributes of the memory descri=
bed by this HOB.=0D
+ @param PhysicalStart The 64 bit physical address of memory descri=
bed by this HOB.=0D
+ @param NumberOfBytes The length of the memory described by this H=
OB in bytes.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildResourceDescriptorHob (=0D
+ IN EFI_RESOURCE_TYPE ResourceType,=0D
+ IN EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute,=0D
+ IN EFI_PHYSICAL_ADDRESS PhysicalStart,=0D
+ IN UINT64 NumberOfBytes=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a customized HOB tagged with a GUID for identification and return=
s=0D
+ the start address of GUID HOB data.=0D
+=0D
+ This function builds a customized HOB tagged with a GUID for identificat=
ion=0D
+ and returns the start address of GUID HOB data so that caller can fill t=
he customized data.=0D
+ The HOB Header and Name field is already stripped.=0D
+ It can only be invoked during PEI phase.=0D
+ For DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If Guid is NULL, then ASSERT().=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().=0D
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0x=
FFF8.=0D
+=0D
+ @param Guid The GUID to tag the customized HOB.=0D
+ @param DataLength The size of the data payload for the GUID HOB.=0D
+=0D
+ @retval NULL The GUID HOB could not be allocated.=0D
+ @retval others The start address of GUID HOB data.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+BuildGuidHob (=0D
+ IN CONST EFI_GUID *Guid,=0D
+ IN UINTN DataLength=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+ return NULL;=0D
+}=0D
+=0D
+/**=0D
+ Builds a customized HOB tagged with a GUID for identification, copies th=
e input data to the HOB=0D
+ data field, and returns the start address of the GUID HOB data.=0D
+=0D
+ This function builds a customized HOB tagged with a GUID for identificat=
ion and copies the input=0D
+ data to the HOB data field and returns the start address of the GUID HOB=
data. It can only be=0D
+ invoked during PEI phase; for DXE phase, it will ASSERT() because PEI HO=
B is read-only for DXE phase.=0D
+ The HOB Header and Name field is already stripped.=0D
+ It can only be invoked during PEI phase.=0D
+ For DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If Guid is NULL, then ASSERT().=0D
+ If Data is NULL and DataLength > 0, then ASSERT().=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+ If DataLength > (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)), then ASSERT().=0D
+ HobLength is UINT16 and multiples of 8 bytes, so the max HobLength is 0x=
FFF8.=0D
+=0D
+ @param Guid The GUID to tag the customized HOB.=0D
+ @param Data The data to be copied into the data field of the G=
UID HOB.=0D
+ @param DataLength The size of the data payload for the GUID HOB.=0D
+=0D
+ @retval NULL The GUID HOB could not be allocated.=0D
+ @retval others The start address of GUID HOB data.=0D
+=0D
+**/=0D
+VOID *=0D
+EFIAPI=0D
+BuildGuidDataHob (=0D
+ IN CONST EFI_GUID *Guid,=0D
+ IN VOID *Data,=0D
+ IN UINTN DataLength=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+ return NULL;=0D
+}=0D
+=0D
+/**=0D
+ Builds a Firmware Volume HOB.=0D
+=0D
+ This function builds a Firmware Volume HOB.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+ If the FvImage buffer is not at its required alignment, then ASSERT().=0D
+=0D
+ @param BaseAddress The base address of the Firmware Volume.=0D
+ @param Length The size of the Firmware Volume in bytes.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildFvHob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a EFI_HOB_TYPE_FV2 HOB.=0D
+=0D
+ This function builds a EFI_HOB_TYPE_FV2 HOB.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+ If the FvImage buffer is not at its required alignment, then ASSERT().=0D
+=0D
+ @param BaseAddress The base address of the Firmware Volume.=0D
+ @param Length The size of the Firmware Volume in bytes.=0D
+ @param FvName The name of the Firmware Volume.=0D
+ @param FileName The name of the file.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildFv2Hob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length,=0D
+ IN CONST EFI_GUID *FvName,=0D
+ IN CONST EFI_GUID *FileName=0D
+ )=0D
+{=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a EFI_HOB_TYPE_FV3 HOB.=0D
+=0D
+ This function builds a EFI_HOB_TYPE_FV3 HOB.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase=
.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+ If the FvImage buffer is not at its required alignment, then ASSERT().=0D
+=0D
+ @param BaseAddress The base address of the Firmware Volume.=0D
+ @param Length The size of the Firmware Volume in bytes.=
=0D
+ @param AuthenticationStatus The authentication status.=0D
+ @param ExtractedFv TRUE if the FV was extracted as a file wit=
hin=0D
+ another firmware volume. FALSE otherwise.=
=0D
+ @param FvName The name of the Firmware Volume.=0D
+ Valid only if IsExtractedFv is TRUE.=0D
+ @param FileName The name of the file.=0D
+ Valid only if IsExtractedFv is TRUE.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildFv3Hob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length,=0D
+ IN UINT32 AuthenticationStatus,=0D
+ IN BOOLEAN ExtractedFv,=0D
+ IN CONST EFI_GUID *FvName, OPTIONAL=0D
+ IN CONST EFI_GUID *FileName OPTIONAL=0D
+ )=0D
+{=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a Capsule Volume HOB.=0D
+=0D
+ This function builds a Capsule Volume HOB.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If the platform does not support Capsule Volume HOBs, then ASSERT().=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param BaseAddress The base address of the Capsule Volume.=0D
+ @param Length The size of the Capsule Volume in bytes.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildCvHob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB for the CPU.=0D
+=0D
+ This function builds a HOB for the CPU.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param SizeOfMemorySpace The maximum physical memory addressability o=
f the processor.=0D
+ @param SizeOfIoSpace The maximum physical I/O addressability of t=
he processor.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildCpuHob (=0D
+ IN UINT8 SizeOfMemorySpace,=0D
+ IN UINT8 SizeOfIoSpace=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB for the Stack.=0D
+=0D
+ This function builds a HOB for the stack.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param BaseAddress The 64 bit physical address of the Stack.=0D
+ @param Length The length of the stack in bytes.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildStackHob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB for the BSP store.=0D
+=0D
+ This function builds a HOB for BSP store.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param BaseAddress The 64 bit physical address of the BSP.=0D
+ @param Length The length of the BSP store in bytes.=0D
+ @param MemoryType Type of memory allocated by this HOB.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildBspStoreHob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length,=0D
+ IN EFI_MEMORY_TYPE MemoryType=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
+=0D
+/**=0D
+ Builds a HOB for the memory allocation.=0D
+=0D
+ This function builds a HOB for the memory allocation.=0D
+ It can only be invoked during PEI phase;=0D
+ for DXE phase, it will ASSERT() because PEI HOB is read-only for DXE pha=
se.=0D
+=0D
+ If there is no additional space for HOB creation, then ASSERT().=0D
+=0D
+ @param BaseAddress The 64 bit physical address of the memory.=0D
+ @param Length The length of the memory allocation in bytes.=0D
+ @param MemoryType Type of memory allocated by this HOB.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+BuildMemoryAllocationHob (=0D
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D
+ IN UINT64 Length,=0D
+ IN EFI_MEMORY_TYPE MemoryType=0D
+ )=0D
+{=0D
+ //=0D
+ // PEI HOB is read only for DXE phase=0D
+ //=0D
+ ASSERT (FALSE);=0D
+}=0D
diff --git a/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c b/UefiPay=
loadPkg/Library/DxeHobListLib/DxeHobListLib.c
new file mode 100644
index 0000000000..8bb31b3f9c
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c
@@ -0,0 +1,66 @@
+/** @file=0D
+ This library retrieve the EFI_BOOT_SERVICES pointer from EFI system tabl=
e in=0D
+ library's constructor.=0D
+=0D
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+VOID *gHobList =3D NULL;=0D
+=0D
+/**=0D
+ Local implementation of GUID comparasion that doesn't depend on DebugLib=
::ASSERT().=0D
+=0D
+ This function compares Guid1 to Guid2. If the GUIDs are identical then =
TRUE is returned.=0D
+ If there are any bit differences in the two GUIDs, then FALSE is returne=
d.=0D
+=0D
+ @param Guid1 A pointer to a 128 bit GUID.=0D
+ @param Guid2 A pointer to a 128 bit GUID.=0D
+=0D
+ @retval TRUE Guid1 and Guid2 are identical.=0D
+ @retval FALSE Guid1 and Guid2 are not identical.=0D
+**/=0D
+BOOLEAN=0D
+LocalCompareGuid (=0D
+ IN CONST GUID *Guid1,=0D
+ IN CONST GUID *Guid2=0D
+ )=0D
+{=0D
+ UINT64 *Left;=0D
+ UINT64 *Right;=0D
+=0D
+ Left =3D (UINT64 *) Guid1;=0D
+ Right =3D (UINT64 *) Guid2;=0D
+=0D
+ return (BOOLEAN) (Left[0] =3D=3D Right[0] && Left[1] =3D=3D Right[1]);=0D
+}=0D
+=0D
+/**=0D
+ @param ImageHandle The firmware allocated handle for the EFI image.=0D
+ @param SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+DxeHobListLibConstructor (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ UINTN Index;=0D
+=0D
+ for (Index =3D 0; Index < SystemTable->NumberOfTableEntries; Index++) {=
=0D
+ if (LocalCompareGuid (&gEfiHobListGuid, &SystemTable->ConfigurationTab=
le[Index].VendorGuid)) {=0D
+ gHobList =3D SystemTable->ConfigurationTable[Index].VendorTable;=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+ }=0D
+=0D
+ return EFI_NOT_FOUND;=0D
+}=0D
diff --git a/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf b/UefiP=
ayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
new file mode 100644
index 0000000000..1115949556
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
@@ -0,0 +1,35 @@
+## @file=0D
+# UEFI Boot Services Table Library implementation.=0D
+#=0D
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D UefiPayloadInitHobLib=0D
+ FILE_GUID =3D ff5c7a21-ab7a-4366-8616-11c6e53247b6=
=0D
+ MODULE_TYPE =3D UEFI_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D DxeHobListLib|DXE_DRIVER DXE_RUNTIME=
_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE=0D
+=0D
+ CONSTRUCTOR =3D DxeHobListLibConstructor=0D
+=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D
+#=0D
+=0D
+[Sources]=0D
+ DxeHobListLib.c=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ UefiPayloadPkg/UefiPayloadPkg.dec=0D
+=0D
+[Guids]=0D
+ gEfiHobListGuid ## CONSUMES=0D
+=0D
+=0D
diff --git a/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c b=
/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c
new file mode 100644
index 0000000000..92d3e17ef0
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c
@@ -0,0 +1,20 @@
+/** @file=0D
+ This library retrieve the EFI_BOOT_SERVICES pointer from EFI system tabl=
e in=0D
+ library's constructor.=0D
+=0D
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+DxeHobListLibNullConstructor (=0D
+ VOID=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
diff --git a/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf=
b/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf
new file mode 100644
index 0000000000..f17e5ebdbd
--- /dev/null
+++ b/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf
@@ -0,0 +1,28 @@
+## @file=0D
+# UEFI Boot Services Table Library implementation.=0D
+#=0D
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D DxeHobListLibNull=0D
+ MODULE_TYPE =3D BASE=0D
+ FILE_GUID =3D 060876c2-0e4e-4c63-8996-6af3710cfa64=
=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D DxeHobListLib=0D
+ CONSTRUCTOR =3D DxeHobListLibNullConstructor=0D
+=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D
+#=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+=0D
+[Sources]=0D
+ DxeHobListLibNull.c=0D
diff --git a/UefiPayloadPkg/Library/HobLib/Hob.c b/UefiPayloadPkg/Library/P=
ayloadEntryHobLib/Hob.c
similarity index 96%
rename from UefiPayloadPkg/Library/HobLib/Hob.c
rename to UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c
index c0b4cc0b0f..23a749edf1 100644
--- a/UefiPayloadPkg/Library/HobLib/Hob.c
+++ b/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c
@@ -1,7 +1,7 @@
/** @file=0D
=0D
Copyright (c) 2010, Apple Inc. All rights reserved.<BR>=0D
- Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
diff --git a/UefiPayloadPkg/Library/HobLib/HobLib.inf b/UefiPayloadPkg/Libr=
ary/PayloadEntryHobLib/HobLib.inf
similarity index 87%
rename from UefiPayloadPkg/Library/HobLib/HobLib.inf
rename to UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf
index 030e22a810..cbb4f02efc 100644
--- a/UefiPayloadPkg/Library/HobLib/HobLib.inf
+++ b/UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf
@@ -1,6 +1,6 @@
#/** @file=0D
#=0D
-# Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.<BR>=
=0D
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload=
Pkg.dsc
index 21b360256b..d8277efccd 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -27,6 +27,7 @@
=0D
DEFINE SOURCE_DEBUG_ENABLE =3D FALSE=0D
DEFINE PS2_KEYBOARD_ENABLE =3D FALSE=0D
+ DEFINE UNIVERSAL_PAYLOAD =3D FALSE=0D
=0D
#=0D
# SBL: UEFI payload for Slim Bootloader=0D
@@ -146,6 +147,13 @@
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC=
offGetEntryPointLib.inf=0D
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain=
tenanceLib.inf=0D
SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf=0D
+ DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf=0D
+=0D
+!if $(UNIVERSAL_PAYLOAD) =3D=3D TRUE=0D
+ HobLib|UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf=0D
+!else=0D
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
+!endif=0D
=0D
#=0D
# UEFI & PI=0D
@@ -221,10 +229,12 @@
VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var=
iablePolicyHelperLib.inf=0D
=0D
[LibraryClasses.common.SEC]=0D
- HobLib|UefiPayloadPkg/Library/HobLib/HobLib.inf=0D
+ HobLib|UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf=0D
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D
+ DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull=
.inf=0D
=0D
[LibraryClasses.common.DXE_CORE]=0D
+ DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull=
.inf=0D
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf=0D
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC=
oreMemoryAllocationLib.inf=0D
@@ -238,7 +248,6 @@
=0D
[LibraryClasses.common.DXE_DRIVER]=0D
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt=
ractGuidedSectionLib.inf=0D
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor=
tStatusCodeLib.inf=0D
@@ -251,7 +260,6 @@
=0D
[LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R=
untimeDxeReportStatusCodeLib.inf=0D
VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL=
ibRuntimeDxe.inf=0D
@@ -260,7 +268,6 @@
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor=
tStatusCodeLib.inf=0D
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
=0D
##########################################################################=
######=0D
#=0D
--=20
2.16.2.windows.1


[PATCH 00/12] Enable Universal Payload in UefiPayloadPkg

Zhiguang Liu
 

This whole patch set will enable some basic feature of Universal Payload
in UefiPayloadPkg.

Zhiguang Liu (12):
UefiPayloadPkg: Add HobLib for UniversalPayload
MdeModulePkg: Add new structure for the Universal Payload Serial Port
Info
UefiPayloadPkg: Add a separate PlatformHookLib for Universal Payload
UefiPayloaPkg: Update the function definition of HobConstructor
UefiPayloadPkg: Create separate Payload Entry for UniversalPayload
UefiPayloadPkg: Get and enter DxeCore for Universal Payload
UefiPayloadPkg: Fix up UPL Pcd database
UefiPayloadPkg: Include UniversalPayLoad modules in UefiPayloadPkg.dsc
UefiPayloadPkg: Remove assert when reserve MMIO/IO resource for
devices
UefiPayloadPkg: Add macro to disable some drivers
UefiPayloadPkg: Add PcdInstallAcpiSdtProtocol feature in
UefiPayloadPkg
UefiPayloadPkg: Add PcdResetOnMemoryTypeInformationChange in
UefiPayloadPkg

MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h | 30 ++++++++++++++++++++++++++++++
MdeModulePkg/MdeModulePkg.dec | 3 +++
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 20 +++++++++++---------
UefiPayloadPkg/Include/Library/DxeHobListLib.h | 27 +++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf | 40 ++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.uni | 17 +++++++++++++++++
UefiPayloadPkg/Library/DxeHobLib/HobLib.c | 597 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf | 35 +++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c | 20 ++++++++++++++++++++
UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf | 28 ++++++++++++++++++++++++++++
UefiPayloadPkg/Library/{HobLib => PayloadEntryHobLib}/Hob.c | 28 ++++++++++++++--------------
UefiPayloadPkg/Library/{HobLib => PayloadEntryHobLib}/HobLib.inf | 2 +-
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf | 41 +++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/UefiPayloadEntry/LoadDxeCore.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 5 +----
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 406 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c | 4 ++--
UefiPayloadPkg/UefiPayloadPkg.dec | 2 ++
UefiPayloadPkg/UefiPayloadPkg.dsc | 52 +++++++++++++++++++++++++++++++++++++++++++---------
UefiPayloadPkg/UefiPayloadPkg.fdf | 10 +++++++++-
24 files changed, 1697 insertions(+), 53 deletions(-)
create mode 100644 MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h
create mode 100644 UefiPayloadPkg/Include/Library/DxeHobListLib.h
create mode 100644 UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf
create mode 100644 UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.uni
create mode 100644 UefiPayloadPkg/Library/DxeHobLib/HobLib.c
create mode 100644 UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c
create mode 100644 UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
create mode 100644 UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c
create mode 100644 UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.inf
rename UefiPayloadPkg/Library/{HobLib => PayloadEntryHobLib}/Hob.c (92%)
rename UefiPayloadPkg/Library/{HobLib => PayloadEntryHobLib}/HobLib.inf (87%)
create mode 100644 UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
create mode 100644 UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
create mode 100644 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
create mode 100644 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf

--
2.16.2.windows.1


Re: OvmfPkgIa32X64.dsc is broken: OvmfPkg/Sec/SecMain.inf NOT found in DSC file; Is it really a binary module?

Lendacky, Thomas
 

On 6/16/21 11:15 PM, Rebecca Cran via groups.io wrote:
Is OvmfPkg/OvmfPkgIa32X64.dsc still supposed to work after the recent
changes in OvmfPkg? I realized it's currently broken.


bcran@photon:~/src/uefi/edk2> build -p OvmfPkg/OvmfPkgIa32X64.dsc -a X64
You need to also have "-a IA32" when building this version of the DSC.

Thanks,
Tom


Event: TianoCore Design Meeting - APAC/NAMO - 06/25/2021 #cal-reminder

devel@edk2.groups.io Calendar <noreply@...>
 

Reminder: TianoCore Design Meeting - APAC/NAMO

When:
06/25/2021
9:30am to 10:30am
(UTC+08:00) Asia/Shanghai

Where:
Microsoft Teams

Organizer: Ray Ni ray.ni@...

View Event

Description:

TOPIC

  1. NA

For more info, see here: https://www.tianocore.org/design-meeting/


Microsoft Teams meeting

Join on your computer or mobile app

Click here to join the meeting

Join with a video conferencing device

teams@...

Video Conference ID: 119 715 416 0

Alternate VTC dialing instructions

Learn More | Meeting options


Possibly incorrect size in memory profile structure

Marvin Häuser
 

Good day,

I have a question regarding a part of the memory profiling code. Namely this piece of code [1] introduced storing the PDB file name among the driver information. This is implement by a string pointer in the "MEMORY_PROFILE_DRIVER_INFO_DATA" structure (which embeds the "MEMORY_PROFILE_DRIVER_INFO" structure [2]). The length of the embedded "MEMORY_PROFILE_DRIVER_INFO" instance is set to the header size plus the 8B-aligned size of the PDB name [3], albeit its storage is not used for the PDB file name, and the storage that is used instead is not aligned by 8B [4]. Ominously, the interior structure does have a comment that indicates it is (or was) supposed to hold the PDB file name at some point [5].

I do not see that concept being used, and instead see the previously described way of storage, so I believe the aligned size is a forgotten piece from a refactoring. I imagine early on, the interior structure was supposed to hold the PDB name, and the alignment was needed to satisfy the following data's requirements. However, the change to the exterior storage should make this superfluous, and the specified size seems to be incorrect in all cases.

Can you please give this a quick look and help me determine whether this is a bug? Thank you for your time!

Best regards,
Marvin

[1] https://github.com/tianocore/edk2/commit/1d60fe96422206d37e1d74198bb11b2cf6195157#diff-b42ade68f10fa42dfa25570f0f9a165db4b974877c98d8845e384a40252ec220R407-R428

[2] https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L25

[3] https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L417

[4] https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Core/Dxe/Mem/MemoryProfileRecord.c#L404

[5] https://github.com/tianocore/edk2/blob/a63914d3f603580e5aeceb5edbafe56688210141/MdeModulePkg/Include/Guid/MemoryProfile.h#L59


Re: [EXTERNAL] 回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

manickavasakam karpagavinayagam
 

Ray :

 

Regarding the OPROM skipping :

 

Current edk2\MdeModulePkg\Bus\Pci\PciBusDxe\PciEnumeratorSupport.c PciSearchDevice()->UpdatePciInfo() doesn’t consider Specific Type Flag to skip the device OPROM (do not probe option ROM Bar)

Also, in GetOpRomInfo() also doesn’t have a check to skip the device bar. Because of the current implementation, there is no other way other than overriding PCIBUS Driver.

 

Please correct me if the understanding is wrong.

 

Regarding the Device enumeration skipping :

 

As you said if modification done to return error status after PreprocessController () change will work for the devices that needs to be skipped after probing.

But if we want to skip the device before probing itself then edk2\MdeModulePkg\Bus\Pci\PciBusDxe\PciLib.c PreprocessController() won’t work.

 

Thank you

 

-Manic

 

From: Ni, Ray <ray.ni@...>
Sent: Friday, June 18, 2021 2:11 AM
To: devel@edk2.groups.io; Manickavasakam Karpagavinayagam <manickavasakamk@...>; Kinney, Michael D <michael.d.kinney@...>; gaoliming <gaoliming@...>
Cc: Harikrishna Doppalapudi <Harikrishnad@...>
Subject: RE: [EXTERNAL]
回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

To skip loading an option rom for certain devices, can you use IncompatiblePciDevice->CheckDevice()?

Table

Description automatically generated

 

For skipping enumerating a certain device, we could change PciBus to skip enumerating if gPciPlatformProtocol->PlatformPrepController() returns error status for that device. Do you think this solution is feasible to you?

 

Thanks,

Ray

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of manickavasakam karpagavinayagam
Sent: Friday, June 18, 2021 12:41 AM
To: Kinney, Michael D <michael.d.kinney@...>; devel@edk2.groups.io; gaoliming <gaoliming@...>; Ni, Ray <ray.ni@...>
Cc: DOPPALAPUDI, HARIKRISHNA <harikrishnad@...>
Subject: Re: [EXTERNAL]
回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

Mike :

 

During PCI Bus enumeration, we need to skip SPI Controller (because of a silicon sighting) or else any SET variable asserts.

Also, need to skip a specific MLX card UEFI OPROM or else will see CPU exception.

 

We checked the PCIBUS driver code flow and there is no generic hooks to skip enumerating a device and to override the OPROM contents.

 

To avoid overriding the PCIBUS driver with platform instance, we can have PciBus Hooks at various places in PCIBUS driver to skip the device from enumeration, overriding the OPROM contents etc..

 

Ex : MdeModulePkg\Bus\Pci\PciBusDxe\PciLib.c PciScanBus()

 

        for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {

    TempReservedBusNum = 0;

    for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {

 

      //

      // Check to see whether a pci device is present

      //

      Status = PciDevicePresent (

                PciRootBridgeIo,

                &Pci,

                StartBusNumber,

                Device,

                Func

                );

 

      if (EFI_ERROR (Status) && Func == 0) {

        //

        // go to next device if there is no Function 0

        //

        break;

      }

 

      if (EFI_ERROR (Status)) {

        continue;

      }

 

     

      Status = PciOemPlatformHooks(&Pci, isPciSkipDevice, &Pci, &StartBusNumber, &Device, &Func);

      if(EFI_ERROR(Status))

      {

          if(Status==EFI_UNSUPPORTED){

              Status=EFI_SUCCESS;

          } else ASSERT_EFI_ERROR(Status);

      }

      else

      {

          DEBUG((DEBUG_INFO,"Device @ [B%X|D%X|F%X], VID=%X, DID=%X SKIPPED from enumeration.\n\n",

                  StartBusNumber, Device, Func,

                  Pci.Hdr.VendorId,Pci.Hdr.DeviceId));

          continue;

      }

     

      //

      // Get the PCI device information

      //

      Status = PciSearchDevice (

                Bridge,

                &Pci,

                StartBusNumber,

                Device,

                Func,

                &PciDevice

                );

 

      if (EFI_ERROR (Status)) {

        continue;

      }

 

Thank you

 

-Manic

 

From: Kinney, Michael D <michael.d.kinney@...>
Sent: Thursday, June 17, 2021 11:19 AM
To: devel@edk2.groups.io; Manickavasakam Karpagavinayagam <manickavasakamk@...>; gaoliming <gaoliming@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Cc: Harikrishna Doppalapudi <Harikrishnad@...>
Subject: RE: [EXTERNAL]
回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

Has the reason for the PciBusDxe override been discussed with the PciBusDxe maintainer?

 

What feature would need to be added to PciBusDxe to accommodate the use case?

 

Mike

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of manickavasakam karpagavinayagam
Sent: Thursday, June 17, 2021 7:56 AM
To: gaoliming <gaoliming@...>; devel@edk2.groups.io
Cc: DOPPALAPUDI, HARIKRISHNA <harikrishnad@...>
Subject: Re: [EXTERNAL]
回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

Liming :

 

Below email is the cover letter and this patch series has two changes. Sure next time, will add more comments in the cover letter also.

Please refer the attached email and it has information about the PCIBUS override changes. PCIBUS override is done based on the platform sighting and it can’t be generic.

 

Thank you

 

-Manic

 

From: gaoliming <gaoliming@...>
Sent: Wednesday, June 16, 2021 10:56 PM
To: devel@edk2.groups.io; Manickavasakam Karpagavinayagam <manickavasakamk@...>
Subject: [EXTERNAL]
回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

 

**CAUTION: The e-mail below is from an external source. Please exercise caution before opening attachments, clicking links, or following guidance.**

 

Please follow https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format to update the commit message format.

 

And, for the override PciBus module, can you give more detail why need to override PciBus? Is it possible to update Edk2 MdeModulePkg PciBus to meet the platform requirement?

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 manickavasakam karpagavinayagam
发送时间: 2021617 7:05
收件人: devel@edk2.groups.io
主题: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

Add BoardTiogaPass packages to support TiogaPass Platform Enabled Network, ISCSI,IPMI, SMBIOS, Performance Measurement
Remove AST2500 UEFI option ROM driver from PurleyOpenBoardPkg

AST2500 UEFI option ROM move to edk2-non-osi ASpeedGopBinPkg Update copyright headers

 

manickavasakam karpagavinayagam (2):

  PurleyOpenBoardPkg : Support for TiogaPass Platform

  PurleyOpenBoardPkg : Override generic PciBus Driver with Platform

    specific instance of PciBus driver.

 

.../IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c |    8 +-

.../Acpi/BoardAcpiDxe/AmlOffsetTable.c        |  453 +-

.../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c      |    3 +

.../BoardTiogaPass/CoreDxeInclude.dsc         |  168 +

.../BoardTiogaPass/CoreUefiBootInclude.fdf    |   82 +

.../BoardTiogaPass/GitEdk2MinTiogaPass.bat    |   93 +

.../BasePlatformHookLib/BasePlatformHookLib.c |  389 +

.../BasePlatformHookLib.inf                   |   36 +

.../BoardAcpiLib/DxeBoardAcpiTableLib.c       |   36 +

.../BoardAcpiLib/DxeBoardAcpiTableLib.inf     |   40 +

.../BoardAcpiLib/DxeTiogaPassAcpiTableLib.c   |   53 +

.../BoardAcpiLib/SmmBoardAcpiEnableLib.c      |   62 +

.../BoardAcpiLib/SmmBoardAcpiEnableLib.inf    |   41 +

.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c    |  120 +

.../BoardAcpiLib/SmmTiogaPassAcpiEnableLib.c  |   37 +

.../Library/BoardInitLib/AllLanesEparam.c     |   44 +

.../Library/BoardInitLib/GpioTable.c          |  296 +

.../Library/BoardInitLib/IioBifur.c           |   70 +

.../BoardInitLib/PeiBoardInitPostMemLib.c     |   46 +

.../BoardInitLib/PeiBoardInitPostMemLib.inf   |   37 +

.../BoardInitLib/PeiBoardInitPreMemLib.c      |  112 +

.../BoardInitLib/PeiBoardInitPreMemLib.inf    |   69 +

.../Library/BoardInitLib/PeiTiogaPassDetect.c |   28 +

.../BoardInitLib/PeiTiogaPassInitLib.h        |   18 +

.../BoardInitLib/PeiTiogaPassInitPostMemLib.c |   86 +

.../BoardInitLib/PeiTiogaPassInitPreMemLib.c  |  638 ++

.../Library/BoardInitLib/UsbOC.c              |   46 +

.../Library/PeiReportFvLib/PeiReportFvLib.c   |  138 +

.../Library/PeiReportFvLib/PeiReportFvLib.inf |   51 +

.../BoardTiogaPass/OpenBoardPkg.dsc           |  245 +

.../BoardTiogaPass/OpenBoardPkg.fdf           |  600 ++

.../BoardTiogaPass/PlatformPkgBuildOption.dsc |   84 +

.../BoardTiogaPass/PlatformPkgConfig.dsc      |   58 +

.../BoardTiogaPass/PlatformPkgPcd.dsc         |  392 ++

.../BoardTiogaPass/StructureConfig.dsc        | 6236 +++++++++++++++++

.../BoardTiogaPass/__init__.py                |    0

.../PurleyOpenBoardPkg/BoardTiogaPass/bld.bat |  139 +

.../BoardTiogaPass/build_board.py             |  195 +

.../BoardTiogaPass/build_config.cfg           |   34 +

.../BoardTiogaPass/logo.txt                   |   10 +

.../BoardTiogaPass/postbuild.bat              |   96 +

.../BoardTiogaPass/prebuild.bat               |  213 +

.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf    |   10 +-

.../IpmiPlatformHookLib.inf                   |    6 +-

.../Include/Guid/PchRcVariable.h              |    6 +

.../Include/Guid/SetupVariable.h              |   15 +-

.../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec |    1 +

.../Bus/Pci/PciBusDxe/ComponentName.c         |  170 +

.../Bus/Pci/PciBusDxe/ComponentName.h         |  146 +

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c   |  460 ++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  396 ++

.../Bus/Pci/PciBusDxe/PciBusDxe.inf           |  112 +

.../Bus/Pci/PciBusDxe/PciBusDxe.uni           |   16 +

.../Bus/Pci/PciBusDxe/PciBusDxeExtra.uni      |   14 +

.../Bus/Pci/PciBusDxe/PciCommand.c            |  267 +

.../Bus/Pci/PciBusDxe/PciCommand.h            |  232 +

.../Bus/Pci/PciBusDxe/PciDeviceSupport.c      | 1056 +++

.../Bus/Pci/PciBusDxe/PciDeviceSupport.h      |  266 +

.../Bus/Pci/PciBusDxe/PciDriverOverride.c     |  188 +

.../Bus/Pci/PciBusDxe/PciDriverOverride.h     |   83 +

.../Bus/Pci/PciBusDxe/PciEnumerator.c         | 2210 ++++++

.../Bus/Pci/PciBusDxe/PciEnumerator.h         |  515 ++

.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c  | 2885 ++++++++  .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.h  |  480 ++

.../Bus/Pci/PciBusDxe/PciHotPlugSupport.c     |  484 ++

.../Bus/Pci/PciBusDxe/PciHotPlugSupport.h     |  205 +

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c    | 2087 ++++++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h    |  660 ++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c   | 1809 +++++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h   |  179 +

.../Bus/Pci/PciBusDxe/PciOptionRomSupport.c   |  776 ++

.../Bus/Pci/PciBusDxe/PciOptionRomSupport.h   |  136 +

.../Bus/Pci/PciBusDxe/PciPowerManagement.c    |   82 +

.../Bus/Pci/PciBusDxe/PciPowerManagement.h    |   28 +

.../Bus/Pci/PciBusDxe/PciResourceSupport.c    | 2292 ++++++

.../Bus/Pci/PciBusDxe/PciResourceSupport.h    |  456 ++

.../Bus/Pci/PciBusDxe/PciRomTable.c           |  135 +

.../Bus/Pci/PciBusDxe/PciRomTable.h           |   48 +

Platform/Intel/build.cfg                      |    2 +

Platform/Intel/build_bios.py                  |    3 +-

80 files changed, 30278 insertions(+), 240 deletions(-)  create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPass.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformHookLib/BasePlatformHookLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformHookLib/BasePlatformHookLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeTiogaPassAcpiTableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmTiogaPassAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/AllLanesEparam.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/GpioTable.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/IioBifur.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPostMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPostMemLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPreMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPreMemLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassDetect.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitLib.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitPostMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitPreMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/UsbOC.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib/PeiReportFvLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib/PeiReportFvLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOption.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/__init__.py

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.uni

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxeExtra.uni

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h

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Re: [PATCH v2 1/1] ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h

Leif Lindholm
 

Agh. *Actually* cc Wenyi.

On Fri, Jun 18, 2021 at 16:53:38 +0100, Leif Lindholm wrote:
+Wenyi

On Mon, Jun 14, 2021 at 12:57:49 -0600, Rebecca Cran wrote:
Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pushed as a63914d3f603. Thanks!

I will note that this change breaks Silicon/Hisilicon/Hi1616 and
Silicon/Hisilicon/Hi1620, which use some of the macros moved by this
patch.
However, I am unable to build these anyway with recent iasl/gcc.

Wenyi: can you have a look at making these platforms build?
This will now also involve dropping use of
Library/ArmLib/ArmLibPrivate.h.

/
Leif

---
ArmPkg/Include/IndustryStandard/ArmCache.h | 112 ++++++++++++++++++
ArmPkg/Include/Library/ArmLib.h | 36 +++++-
ArmPkg/Library/ArmLib/ArmLibPrivate.h | 123 --------------------
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c | 2 +-
7 files changed, 148 insertions(+), 131 deletions(-)

diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h
new file mode 100644
index 000000000000..f9de46b5bffd
--- /dev/null
+++ b/ArmPkg/Include/IndustryStandard/ArmCache.h
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_CACHE_H_
+#define ARM_CACHE_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// The ARM Architecture Reference Manual for ARMv8-A defines up
+// to 7 levels of cache, L1 through L7.
+#define MAX_ARM_CACHE_LEVEL 7
+
+/// Defines the structure of the CSSELR (Cache Size Selection) register
+typedef union {
+ struct {
+ UINT32 InD :1; ///< Instruction not Data bit
+ UINT32 Level :3; ///< Cache level (zero based)
+ UINT32 TnD :1; ///< Allocation not Data bit
+ UINT32 Reserved :27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CSSELR_DATA;
+
+/// The cache type values for the InD field of the CSSELR register
+typedef enum
+{
+ /// Select the data or unified cache
+ CsselrCacheTypeDataOrUnified = 0,
+ /// Select the instruction cache
+ CsselrCacheTypeInstruction,
+ CsselrCacheTypeMax
+} CSSELR_CACHE_TYPE;
+
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register
+typedef union {
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :10; ///< Associativity - 1
+ UINT64 NumSets :15; ///< Number of sets in the cache -1
+ UINT64 Unknown :4; ///< Reserved, UNKNOWN
+ UINT64 Reserved :32; ///< Reserved, RES0
+ } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :21; ///< Associativity - 1
+ UINT64 Reserved1 :8; ///< Reserved, RES0
+ UINT64 NumSets :24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 :8; ///< Reserved, RES0
+ } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
+ struct {
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
+ } BitsCcidxAA32;
+ UINT64 Data; ///< The entire 64-bit value
+} CCSIDR_DATA;
+
+/// Defines the structure of the AARCH32 CCSIDR2 register.
+typedef union {
+ struct {
+ UINT32 NumSets :24; ///< Number of sets in the cache - 1
+ UINT32 Reserved :8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CCSIDR2_DATA;
+
+/** Defines the structure of the CLIDR (Cache Level ID) register.
+ *
+ * The lower 32 bits are the same for both AARCH32 and AARCH64
+ * so we can use the same structure for both.
+**/
+typedef union {
+ struct {
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CLIDR_DATA;
+
+/// The cache types reported in the CLIDR register.
+typedef enum {
+ /// No cache is present
+ ClidrCacheTypeNone = 0,
+ /// There is only an instruction cache
+ ClidrCacheTypeInstructionOnly,
+ /// There is only a data cache
+ ClidrCacheTypeDataOnly,
+ /// There are separate data and instruction caches
+ ClidrCacheTypeSeparate,
+ /// There is a unified cache
+ ClidrCacheTypeUnified,
+ ClidrCacheTypeMax
+} CLIDR_CACHE_TYPE;
+
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+
+#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5c232d779c83..79ea755777a9 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -2,7 +2,7 @@

Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -109,9 +109,37 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)

-// The ARM Architecture Reference Manual for ARMv8-A defines up
-// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+/** Reads the CCSIDR register for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value.
+
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+ Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the CCSIDR2 for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value
+
+ @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+ @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
+ VOID
+ );

UINTN
EFIAPI
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index 5db83d620bfc..668aefd6a088 100644
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -52,101 +52,6 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)

-
-/// Defines the structure of the CSSELR (Cache Size Selection) register
-typedef union {
- struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CSSELR_DATA;
-
-/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
- /// Select the data or unified cache
- CsselrCacheTypeDataOrUnified = 0,
- /// Select the instruction cache
- CsselrCacheTypeInstruction,
- CsselrCacheTypeMax
-} CSSELR_CACHE_TYPE;
-
-/// Defines the structure of the CCSIDR (Current Cache Size ID) register
-typedef union {
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
- } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
- } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
- struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
- } BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
-} CCSIDR_DATA;
-
-/// Defines the structure of the AARCH32 CCSIDR2 register.
-typedef union {
- struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CCSIDR2_DATA;
-
-/** Defines the structure of the CLIDR (Cache Level ID) register.
- *
- * The lower 32 bits are the same for both AARCH32 and AARCH64
- * so we can use the same structure for both.
-**/
-typedef union {
- struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CLIDR_DATA;
-
-/// The cache types reported in the CLIDR register.
-typedef enum {
- /// No cache is present
- ClidrCacheTypeNone = 0,
- /// There is only an instruction cache
- ClidrCacheTypeInstructionOnly,
- /// There is only a data cache
- ClidrCacheTypeDataOnly,
- /// There are separate data and instruction caches
- ClidrCacheTypeSeparate,
- /// There is a unified cache
- ClidrCacheTypeUnified,
- ClidrCacheTypeMax
-} CLIDR_CACHE_TYPE;
-
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
-
VOID
CPSRMaskInsert (
IN UINT32 Mask,
@@ -158,32 +63,4 @@ CPSRRead (
VOID
);

-/** Reads the CCSIDR register for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value.
-
- @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
- Returns the contents of the CCSIDR register in AARCH32 mode.
-**/
-UINTN
-ReadCCSIDR (
- IN UINT32 CSSELR
- );
-
-/** Reads the CCSIDR2 for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value
-
- @return The contents of the CCSIDR2 register for the specified cache.
-**/
-UINT32
-ReadCCSIDR2 (
- IN UINT32 CSSELR
- );
-
-UINT32
-ReadCLIDR (
- VOID
- );
-
#endif // ARM_LIB_PRIVATE_H_
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 0cb56c53975e..fb484086a457 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -10,11 +10,11 @@

#include <Uefi.h>
#include <Protocol/Smbios.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmSmcLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
index ddd774b16f83..6fbb95afb215 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
index c78bd41a7e06..7616fca425fd 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
index bccb21cfbb41..292f10bf97eb 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
@@ -8,10 +8,10 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>

--
2.26.2


Re: [PATCH v2 1/1] ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h

Leif Lindholm
 

+Wenyi

On Mon, Jun 14, 2021 at 12:57:49 -0600, Rebecca Cran wrote:
Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Pushed as a63914d3f603. Thanks!

I will note that this change breaks Silicon/Hisilicon/Hi1616 and
Silicon/Hisilicon/Hi1620, which use some of the macros moved by this
patch.
However, I am unable to build these anyway with recent iasl/gcc.

Wenyi: can you have a look at making these platforms build?
This will now also involve dropping use of
Library/ArmLib/ArmLibPrivate.h.

/
Leif

---
ArmPkg/Include/IndustryStandard/ArmCache.h | 112 ++++++++++++++++++
ArmPkg/Include/Library/ArmLib.h | 36 +++++-
ArmPkg/Library/ArmLib/ArmLibPrivate.h | 123 --------------------
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c | 2 +-
7 files changed, 148 insertions(+), 131 deletions(-)

diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h
new file mode 100644
index 000000000000..f9de46b5bffd
--- /dev/null
+++ b/ArmPkg/Include/IndustryStandard/ArmCache.h
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_CACHE_H_
+#define ARM_CACHE_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// The ARM Architecture Reference Manual for ARMv8-A defines up
+// to 7 levels of cache, L1 through L7.
+#define MAX_ARM_CACHE_LEVEL 7
+
+/// Defines the structure of the CSSELR (Cache Size Selection) register
+typedef union {
+ struct {
+ UINT32 InD :1; ///< Instruction not Data bit
+ UINT32 Level :3; ///< Cache level (zero based)
+ UINT32 TnD :1; ///< Allocation not Data bit
+ UINT32 Reserved :27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CSSELR_DATA;
+
+/// The cache type values for the InD field of the CSSELR register
+typedef enum
+{
+ /// Select the data or unified cache
+ CsselrCacheTypeDataOrUnified = 0,
+ /// Select the instruction cache
+ CsselrCacheTypeInstruction,
+ CsselrCacheTypeMax
+} CSSELR_CACHE_TYPE;
+
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register
+typedef union {
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :10; ///< Associativity - 1
+ UINT64 NumSets :15; ///< Number of sets in the cache -1
+ UINT64 Unknown :4; ///< Reserved, UNKNOWN
+ UINT64 Reserved :32; ///< Reserved, RES0
+ } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :21; ///< Associativity - 1
+ UINT64 Reserved1 :8; ///< Reserved, RES0
+ UINT64 NumSets :24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 :8; ///< Reserved, RES0
+ } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
+ struct {
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
+ } BitsCcidxAA32;
+ UINT64 Data; ///< The entire 64-bit value
+} CCSIDR_DATA;
+
+/// Defines the structure of the AARCH32 CCSIDR2 register.
+typedef union {
+ struct {
+ UINT32 NumSets :24; ///< Number of sets in the cache - 1
+ UINT32 Reserved :8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CCSIDR2_DATA;
+
+/** Defines the structure of the CLIDR (Cache Level ID) register.
+ *
+ * The lower 32 bits are the same for both AARCH32 and AARCH64
+ * so we can use the same structure for both.
+**/
+typedef union {
+ struct {
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CLIDR_DATA;
+
+/// The cache types reported in the CLIDR register.
+typedef enum {
+ /// No cache is present
+ ClidrCacheTypeNone = 0,
+ /// There is only an instruction cache
+ ClidrCacheTypeInstructionOnly,
+ /// There is only a data cache
+ ClidrCacheTypeDataOnly,
+ /// There are separate data and instruction caches
+ ClidrCacheTypeSeparate,
+ /// There is a unified cache
+ ClidrCacheTypeUnified,
+ ClidrCacheTypeMax
+} CLIDR_CACHE_TYPE;
+
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+
+#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5c232d779c83..79ea755777a9 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -2,7 +2,7 @@

Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -109,9 +109,37 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)

-// The ARM Architecture Reference Manual for ARMv8-A defines up
-// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+/** Reads the CCSIDR register for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value.
+
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+ Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the CCSIDR2 for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value
+
+ @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+ @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
+ VOID
+ );

UINTN
EFIAPI
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index 5db83d620bfc..668aefd6a088 100644
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -52,101 +52,6 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)

-
-/// Defines the structure of the CSSELR (Cache Size Selection) register
-typedef union {
- struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CSSELR_DATA;
-
-/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
- /// Select the data or unified cache
- CsselrCacheTypeDataOrUnified = 0,
- /// Select the instruction cache
- CsselrCacheTypeInstruction,
- CsselrCacheTypeMax
-} CSSELR_CACHE_TYPE;
-
-/// Defines the structure of the CCSIDR (Current Cache Size ID) register
-typedef union {
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
- } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
- } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
- struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
- } BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
-} CCSIDR_DATA;
-
-/// Defines the structure of the AARCH32 CCSIDR2 register.
-typedef union {
- struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CCSIDR2_DATA;
-
-/** Defines the structure of the CLIDR (Cache Level ID) register.
- *
- * The lower 32 bits are the same for both AARCH32 and AARCH64
- * so we can use the same structure for both.
-**/
-typedef union {
- struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CLIDR_DATA;
-
-/// The cache types reported in the CLIDR register.
-typedef enum {
- /// No cache is present
- ClidrCacheTypeNone = 0,
- /// There is only an instruction cache
- ClidrCacheTypeInstructionOnly,
- /// There is only a data cache
- ClidrCacheTypeDataOnly,
- /// There are separate data and instruction caches
- ClidrCacheTypeSeparate,
- /// There is a unified cache
- ClidrCacheTypeUnified,
- ClidrCacheTypeMax
-} CLIDR_CACHE_TYPE;
-
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
-
VOID
CPSRMaskInsert (
IN UINT32 Mask,
@@ -158,32 +63,4 @@ CPSRRead (
VOID
);

-/** Reads the CCSIDR register for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value.
-
- @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
- Returns the contents of the CCSIDR register in AARCH32 mode.
-**/
-UINTN
-ReadCCSIDR (
- IN UINT32 CSSELR
- );
-
-/** Reads the CCSIDR2 for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value
-
- @return The contents of the CCSIDR2 register for the specified cache.
-**/
-UINT32
-ReadCCSIDR2 (
- IN UINT32 CSSELR
- );
-
-UINT32
-ReadCLIDR (
- VOID
- );
-
#endif // ARM_LIB_PRIVATE_H_
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 0cb56c53975e..fb484086a457 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -10,11 +10,11 @@

#include <Uefi.h>
#include <Protocol/Smbios.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmSmcLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
index ddd774b16f83..6fbb95afb215 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
index c78bd41a7e06..7616fca425fd 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
index bccb21cfbb41..292f10bf97eb 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
@@ -8,10 +8,10 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>

--
2.26.2


Re: [EXTERNAL] 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure Defintions to resolve the IPMI build error

manickavasakam karpagavinayagam
 

Liming :

Add Signed-off-by information and created/sent a new PATCH V3 [edk2][PATCH V3] MdePkg : Add IPMI Macro and Structure Defintions to resolve build errors

Thank you

-Manic

-----Original Message-----
From: gaoliming <gaoliming@byosoft.com.cn>
Sent: Thursday, June 17, 2021 9:06 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>; devel@edk2.groups.io
Cc: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com; Felix Polyudov <Felixp@ami.com>; Harikrishna Doppalapudi <Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff <zacharyb@ami.com>
Subject: 回复: [EXTERNAL] 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure Defintions to resolve the IPMI build error

Manic:
The patch content is good. But, the commit message misses Signed-off-by: Contributor Name <contributor@email.server>

And, please run BaseTools\Scripts\PatchCheck.py to check the commit message format.

Thanks
Liming
-----邮件原件-----
发件人: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
发送时间: 2021年6月18日 1:42
收件人: gaoliming <gaoliming@byosoft.com.cn>; devel@edk2.groups.io
抄送: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com; Felix
Polyudov <Felixp@ami.com>; Harikrishna Doppalapudi
<Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff
<zacharyb@ami.com>
主题: RE: [EXTERNAL] 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and
Structure Defintions to resolve the IPMI build error

Liming :

Thank you for the review comments. Created [edk2] [PATCH V2] MdePkg :
Add IPMI Macro and Structure Defintions to resolve build errors and
sent for review.

-Manic

-----Original Message-----
From: gaoliming <gaoliming@byosoft.com.cn>
Sent: Wednesday, June 16, 2021 10:51 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>;
devel@edk2.groups.io
Cc: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com; Felix
Polyudov <Felixp@ami.com>; Harikrishna Doppalapudi
<Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff
<zacharyb@ami.com>
Subject: [EXTERNAL] 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and
Structure Defintions to resolve the IPMI build error


**CAUTION: The e-mail below is from an external source. Please
exercise caution before opening attachments, clicking links, or
following guidance.**

Manickavasakam:
Please update this patch. It also includes
0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch.

The patch should only include the code changes in MdePkg.

Thanks
Liming
-----邮件原件-----
发件人: gaoliming <gaoliming@byosoft.com.cn>
发送时间: 2021年6月17日 10:50
收件人: 'manickavasakam karpagavinayagam'
<manickavasakamk@ami.com>; 'devel@edk2.groups.io'
<devel@edk2.groups.io>
抄送: 'isaac.w.oram@intel.com' <isaac.w.oram@intel.com>;
'nathaniel.l.desimone@intel.com' <nathaniel.l.desimone@intel.com>;
'Felixp@ami.com' <Felixp@ami.com>; 'Harikrishnad@ami.com'
<Harikrishnad@ami.com>; 'manishj@ami.com' <manishj@ami.com>;
'zacharyb@ami.com' <zacharyb@ami.com>
主题: 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure
Defintions to resolve the IPMI build error



-----邮件原件-----
发件人: manickavasakam karpagavinayagam
<manickavasakamk@ami.com>
发送时间: 2021年6月12日 5:50
收件人: devel@edk2.groups.io
抄送: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com;
Felixp@ami.com; Harikrishnad@ami.com; manishj@ami.com;
zacharyb@ami.com; manickavasakamk@ami.com;
gaoliming@byosoft.com.cn
主题: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure
Defintions
to resolve the IPMI build error

Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
EFI_IPMI_MSG_GET_BMC_EXEC_RSP and
macros EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCE
D_UPDATE_MODE
when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg

MdePkg : Rename IPMI Macro and Structure Defintions

Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE
---

Notes:
V1 :
- Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
- EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
- IPMI_BMC_IN_FORCED_UPDATE_MODE

0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch |
61
++++++++++++++++++++
MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
|
4 ++
MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
|
18 ++++++
3 files changed, 83 insertions(+)

diff --git
a/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
new file mode 100644
index 0000000000..16d149e2d8
--- /dev/null
+++
b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patc
+++ h
@@ -0,0 +1,61 @@
+From c5e221cfe5d815883f39b71667b6e8f644a27390 Mon Sep 17
00:00:00
2001
+From: manickavasakam karpagavinayagam
<manickavasakamk@ami.com>
+Date: Thu, 10 Jun 2021 14:59:22 -0400
+Subject: [edk2][PATCH] MdePkg : Add IPMI Macro and Structure
+Defintions
to resolve
+ the IPMI build error
+
+Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
+EFI_IPMI_MSG_GET_BMC_EXEC_RSP and macros
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
+EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORC
ED_UPDATE_MODE
+when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg
+---
+ MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h | 4 ++++
+MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h | 19
+++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+index 79db55523d..d7cdd3a865 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+@@ -186,6 +186,10 @@ typedef struct {
+ UINT8 ParameterData[0];
+ } IPMI_SET_BOOT_OPTIONS_REQUEST;
+
++typedef struct {
++ UINT8 CompletionCode:8;
++} IPMI_SET_BOOT_OPTIONS_RESPONSE;
++
+ //
+ // Definitions for Get System Boot options command // diff
+--git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+index 2d892dbd5a..1c692cc792 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+@@ -17,4 +17,23 @@
+ // All Firmware commands and their structure definitions to
+follow
here
+ //
+
++/*------------------------------------------------------------------
++--
++----
---------------
-
++ Definitions for Get BMC Execution Context
++--------------------------------------------------------------------
++--
++----
--------------*
/
++#define EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT 0x23
++
++//
++// Constants and Structure definitions for "Get Device ID"
++command to
follow here
++//
++typedef struct {
++ UINT8 CurrentExecutionContext;
++ UINT8 PartitionPointer;
++} EFI_IPMI_MSG_GET_BMC_EXEC_RSP;
++
++//
++// Current Execution Context responses //
++#define EFI_FIRMWARE_BMC_IN_FULL_RUNTIME 0x10
++#define EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE 0x11
++
+ #endif
+--
+2.25.0.windows.1
+
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 79db55523d..d7cdd3a865 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -186,6 +186,10 @@ typedef struct {
UINT8 ParameterData[0];

} IPMI_SET_BOOT_OPTIONS_REQUEST;



+typedef struct {

+ UINT8 CompletionCode:8;

+} IPMI_SET_BOOT_OPTIONS_RESPONSE;

+

//

// Definitions for Get System Boot options command

//

diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index 2d892dbd5a..c4cbe2349b 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -17,4 +17,22 @@
// All Firmware commands and their structure definitions to
follow here

//



+//
----------------------------------------------------------------------
------
------------

+// Definitions for Get BMC Execution Context

+//
----------------------------------------------------------------------
------
------------

+#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23

+

+//

+// Constants and Structure definitions for "Get Device ID"
+command to
follow here

+//

+typedef struct {

+ UINT8 CurrentExecutionContext;

+ UINT8 PartitionPointer;

+} IPMI_MSG_GET_BMC_EXEC_RSP;

+

+//

+// Current Execution Context responses

+//

+#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11

+

#endif

--
2.25.0.windows.1


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you are
on notice that any distribution of this message, in any form, is
strictly
prohibited. Please promptly notify the sender by reply e-mail or
by telephone at 770-246-8600, and then delete or destroy all
copies of the transmission.

-The information contained in this message may be confidential and
proprietary to American Megatrends (AMI). This communication is
intended to be read only by the individual or entity to whom it is
addressed or by their designee. If the reader of this message is not
the intended recipient, you are on notice that any distribution of
this message, in any form, is strictly prohibited. Please promptly
notify the sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.

-The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify the sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.


[edk2][PATCH V3] MdePkg : Add IPMI Macro and Structure Defintions to resolve build errors

manickavasakam karpagavinayagam
 

Build error reported for missing structures IPMI_SET_BOOT_OPTIONS_RESPONSE, EFI_IPMI_MSG_GET_BMC_EXEC_RSP and
macros EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE
when using edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg

MdePkg : Rename IPMI Macro and Structure Defintions

Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE

Notes:
V1 :
Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE

V2:

Remove 0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch

V3:

Add Signed-off-by information

Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
---
.../IndustryStandard/IpmiNetFnChassis.h | 4 ++++
.../IndustryStandard/IpmiNetFnFirmware.h | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 79db55523d..d7cdd3a865 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -186,6 +186,10 @@ typedef struct {
UINT8 ParameterData[0];
} IPMI_SET_BOOT_OPTIONS_REQUEST;

+typedef struct {
+ UINT8 CompletionCode:8;
+} IPMI_SET_BOOT_OPTIONS_RESPONSE;
+
//
// Definitions for Get System Boot options command
//
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index 2d892dbd5a..c4cbe2349b 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -17,4 +17,22 @@
// All Firmware commands and their structure definitions to follow here
//

+// ----------------------------------------------------------------------------------------
+// Definitions for Get BMC Execution Context
+// ----------------------------------------------------------------------------------------
+#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23
+
+//
+// Constants and Structure definitions for "Get Device ID" command to follow here
+//
+typedef struct {
+ UINT8 CurrentExecutionContext;
+ UINT8 PartitionPointer;
+} IPMI_MSG_GET_BMC_EXEC_RSP;
+
+//
+// Current Execution Context responses
+//
+#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11
+
#endif
--
2.25.0.windows.1


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[PATCH V2 4/4] Platform/NXP/LS1046aFrwyPkg: Add OEM specific DSDT generator

Vikas Singh
 

This patch adds platform specific DSDT generator
and Clk dsdt properties for LS1046AFRWY platform.

Reviewed-by: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl =
| 60 +++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl =
| 15 +++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf =
| 39 ++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtG=
enerator.c | 138 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h =
| 23 ++++
Platform/NXP/LS1046aFrwyPkg/Include/Platform.h =
| 6 +-
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc =
| 1 +
7 files changed, 281 insertions(+), 1 deletion(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl b/P=
latform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
new file mode 100644
index 0000000000..58541c3019
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
@@ -0,0 +1,60 @@
+/** @file=0D
+* DSDT : Dynamic Clock ACPI Information=0D
+*=0D
+* Copyright 2021 NXP=0D
+* Copyright 2021 Puresoftware Ltd.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+=0D
+Scope(_SB)=0D
+{=0D
+ Device(PCLK) {=0D
+ Name(_HID, "NXP0017")=0D
+ Name(CLK, 0) // Maximum Platform Clock (Hz)=0D
+ Name(CCLK, 0) // Maximum CPU Core Clock (MHz)=0D
+ Name(AVBL, 0)=0D
+ OperationRegion(RCWS, SystemMemory, DCFG_BASE, DCFG_LEN)=0D
+ Method(_REG,2) {=0D
+ if (Arg0 =3D=3D "RCWS") {=0D
+ Store(Arg1, AVBL)=0D
+ }=0D
+ }=0D
+ Field (RCWS, ByteAcc, NoLock, Preserve) {=0D
+ /* The below table provides the func of diff bits in 512 bits RCW da=
ta:=0D
+ SYS_PLL_CFG : 0-1 bits=0D
+ SYS_PLL_RAT : 2-6 bits=0D
+ SYSCLK_FREQ : 472-481 bits etc.=0D
+ Refer LS1046ARM for more info.=0D
+ For LS1046 RCWSRs are read as RCW[0:31] .=0D
+ */=0D
+ offset(0x100),=0D
+ RESV, 1,=0D
+ PRAT, 5,=0D
+ PCFG, 2,=0D
+ offset(0x103),=0D
+ CPRT, 6, // Cluster Group PLL Multiplier ratio=0D
+ offset(0x13B),=0D
+ HFRQ, 8, // Higher 8 bits of SYSCLK_FREQ=0D
+ RESX, 6,=0D
+ LFRQ, 2 // Lower bits of SYSCLK_FREQ=0D
+ }=0D
+=0D
+ Method(_INI, 0, NotSerialized) {=0D
+ /* Calculating Platform Clock */=0D
+ Local0 =3D (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ=0D
+ Multiply(Local0, 500000, Local0)=0D
+ Multiply(Local0, PRAT, Local0)=0D
+ Divide(Local0, 3, , Local0)=0D
+ Store(Local0, CLK)=0D
+=0D
+ /* Calculating Maximum Core Clock */=0D
+ Local0 =3D (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ=0D
+ Multiply(Local0, 500000, Local0)=0D
+ Divide(Local0, 3, , Local0)=0D
+ Divide(Local0, 1000000, , Local0) //Just the MHz part of SYSCLK.=0D
+ Multiply(Local0, CPRT, CCLK) // PLL_Ratio * SYSCLK, Max freq of clus=
ter=0D
+ }=0D
+ } // end of device PCLK=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl b/=
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..19f3f1c0e8
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
@@ -0,0 +1,15 @@
+/** @file=0D
+ Differentiated System Description Table Fields (DSDT)=0D
+=0D
+ Copyright 2021 NXP=0D
+ Copyright 2021 Puresoftware Ltd.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "Platform.h"=0D
+=0D
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "NXP ", "LS1046 ", EFI_ACPI_=
ARM_OEM_REVISION) {=0D
+ include ("Clk.asl")=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdt=
Lib.inf b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib=
.inf
new file mode 100644
index 0000000000..ed5f9dd442
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
@@ -0,0 +1,39 @@
+## @file=0D
+# Raw Table Generator=0D
+#=0D
+# Copyright 2021 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010019=0D
+ BASE_NAME =3D PlatformAcpiDsdtLib=0D
+ FILE_GUID =3D A97F70AC-3BB4-4596-B4D2-9F948EC12D17=0D
+ VERSION_STRING =3D 1.0=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ LIBRARY_CLASS =3D NULL|DXE_DRIVER=0D
+ CONSTRUCTOR =3D AcpiDsdtLibConstructor=0D
+ DESTRUCTOR =3D AcpiDsdtLibDestructor=0D
+=0D
+[Sources]=0D
+ PlatformAcpiDsdtLib/RawDsdtGenerator.c=0D
+ Dsdt/Dsdt.asl=0D
+=0D
+[Packages]=0D
+ DynamicTablesPkg/DynamicTablesPkg.dec=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec=0D
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+=0D
+[Pcd]=0D
+=0D
+[Protocols]=0D
+=0D
+[Guids]=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdt=
Lib/RawDsdtGenerator.c b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Plat=
formAcpiDsdtLib/RawDsdtGenerator.c
new file mode 100644
index 0000000000..7d886396ca
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/Raw=
DsdtGenerator.c
@@ -0,0 +1,138 @@
+/** @file=0D
+ Raw DSDT Table Generator=0D
+=0D
+ Copyright 2021 NXP=0D
+ Copyright 2021 Puresoftware Ltd.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/AcpiLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Protocol/AcpiTable.h>=0D
+=0D
+// Module specific include files.=0D
+#include <AcpiTableGenerator.h>=0D
+#include <ConfigurationManagerObject.h>=0D
+#include <ConfigurationManagerHelper.h>=0D
+#include <Library/TableHelperLib.h>=0D
+#include <Protocol/ConfigurationManagerProtocol.h>=0D
+=0D
+#include "PlatformAcpiLib.h"=0D
+=0D
+/** Construct the ACPI table using the ACPI table data provided.=0D
+ This function invokes the Configuration Manager protocol interface=0D
+ to get the required hardware information for generating the ACPI=0D
+ table.=0D
+ If this function allocates any resources then they must be freed=0D
+ in the FreeXXXXTableResources function.=0D
+ @param [in] This Pointer to the table generator.=0D
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.=0D
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager=0D
+ Protocol Interface.=0D
+ @param [out] Table Pointer to the constructed ACPI Table.=0D
+ @retval EFI_SUCCESS Table generated successfully.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+EFIAPI=0D
+BuildRawDsdtTable (=0D
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,=0D
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,=0D
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,=
=0D
+ OUT EFI_ACPI_DESCRIPTION_HEADER ** CONST Table=0D
+ )=0D
+{=0D
+ ASSERT (This !=3D NULL);=0D
+ ASSERT (AcpiTableInfo !=3D NULL);=0D
+ ASSERT (CfgMgrProtocol !=3D NULL);=0D
+ ASSERT (Table !=3D NULL);=0D
+ ASSERT (AcpiTableInfo->TableGeneratorId =3D=3D This->GeneratorID);=0D
+=0D
+ if (AcpiTableInfo->AcpiTableData =3D=3D NULL) {=0D
+ // Add the dsdt aml code here.=0D
+ *Table =3D (EFI_ACPI_DESCRIPTION_HEADER *)&dsdt_aml_code;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+/** This macro defines the Raw Generator revision.=0D
+*/=0D
+#define DSDT_GENERATOR_REVISION CREATE_REVISION (1, 0)=0D
+=0D
+/** The interface for the Raw Table Generator.=0D
+*/=0D
+STATIC=0D
+CONST=0D
+ACPI_TABLE_GENERATOR RawDsdtGenerator =3D {=0D
+ // Generator ID=0D
+ CREATE_OEM_ACPI_TABLE_GEN_ID (PlatAcpiTableIdDsdt),=0D
+ // Generator Description=0D
+ L"ACPI.OEM.RAW.DSDT.GENERATOR",=0D
+ // ACPI Table Signature - Unused=0D
+ 0,=0D
+ // ACPI Table Revision - Unused=0D
+ 0,=0D
+ // Minimum ACPI Table Revision - Unused=0D
+ 0,=0D
+ // Creator ID=0D
+ TABLE_GENERATOR_CREATOR_ID_ARM,=0D
+ // Creator Revision=0D
+ DSDT_GENERATOR_REVISION,=0D
+ // Build Table function=0D
+ BuildRawDsdtTable,=0D
+ // No additional resources are allocated by the generator.=0D
+ // Hence the Free Resource function is not required.=0D
+ NULL,=0D
+ // Extended build function not needed=0D
+ NULL,=0D
+ // Extended build function not implemented by the generator.=0D
+ // Hence extended free resource function is not required.=0D
+ NULL=0D
+};=0D
+=0D
+/** Register the Generator with the ACPI Table Factory.=0D
+ @param [in] ImageHandle The handle to the image.=0D
+ @param [in] SystemTable Pointer to the System Table.=0D
+ @retval EFI_SUCCESS The Generator is registered.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+ @retval EFI_ALREADY_STARTED The Generator for the Table ID=0D
+ is already registered.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+AcpiDsdtLibConstructor (=0D
+ IN CONST EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE * CONST SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ Status =3D RegisterAcpiTableGenerator (&RawDsdtGenerator);=0D
+ DEBUG ((DEBUG_INFO, "OEM: Register DSDT Generator. Status =3D %r\n", Sta=
tus));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
+=0D
+/** Deregister the Generator from the ACPI Table Factory.=0D
+ @param [in] ImageHandle The handle to the image.=0D
+ @param [in] SystemTable Pointer to the System Table.=0D
+ @retval EFI_SUCCESS The Generator is deregistered.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+ @retval EFI_NOT_FOUND The Generator is not registered.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+AcpiDsdtLibDestructor (=0D
+ IN CONST EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE * CONST SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ Status =3D DeregisterAcpiTableGenerator (&RawDsdtGenerator);=0D
+ DEBUG ((DEBUG_INFO, "OEM: Deregister DSDT Generator. Status =3D %r\n", S=
tatus));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.=
h b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
new file mode 100644
index 0000000000..e5f907a7d4
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
@@ -0,0 +1,23 @@
+/** @file=0D
+ * Acpi lib headers=0D
+ *=0D
+ * Copyright 2021 NXP=0D
+ * Copyright 2021 Puresoftware Ltd=0D
+ *=0D
+ * SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+ *=0D
+**/=0D
+=0D
+=0D
+#ifndef LS1046AFRWY_PLATFORM_ACPI_LIB_H=0D
+#define LS1046AFRWY_PLATFORM_ACPI_LIB_H=0D
+=0D
+#include <PlatformAcpiTableGenerator.h>=0D
+=0D
+/** C array containing the compiled AML template.=0D
+ These symbols are defined in the auto generated C file=0D
+ containing the AML bytecode array.=0D
+*/=0D
+extern CHAR8 dsdt_aml_code[];=0D
+=0D
+#endif=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/=
LS1046aFrwyPkg/Include/Platform.h
index 3c68d65cd3..0483bf2dc8 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -17,6 +17,10 @@
// Soc defines=0D
#define PLAT_SOC_NAME "LS1046AFRWY"=0D
=0D
+// PCLK : Dynamic Clock=0D
+#define DCFG_BASE 0x1EE0000 /* Device configuration da=
ta Base Address */=0D
+#define DCFG_LEN 0xFFF /* Device configuration da=
ta length */=0D
+=0D
// Gic=0D
#define GIC_VERSION 2=0D
#define GICD_BASE 0x1410000=0D
@@ -59,7 +63,7 @@
#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')=0D
=0D
// Specify the OEM defined tables=0D
-#define OEM_ACPI_TABLES 0=0D
+#define OEM_ACPI_TABLES 1 // Added DSDT=0D
=0D
#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0=0D
#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 20111e6037..7041d15da5 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -65,6 +65,7 @@
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibA=
rm.inf=0D
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibA=
rm.inf=0D
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibA=
rm.inf=0D
+ NULL|Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsd=
tLib.inf=0D
}=0D
!endif=0D
=0D
--=20
2.25.1


[PATCH V2 3/4] NXP/LS1046aFrwyPkg: Enable ConfigurationManager on LS1046AFRWY

Vikas Singh
 

This patch enables the use of ConfigurationManager (CM) and
its services to leverage the Dynamic ACPI support for NXP's
LS1046aFrwy platform.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/LS1046aFrwyPkg/Include/Platform.h | 152 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 28 ++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 11 ++
4 files changed, 204 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/=
LS1046aFrwyPkg/Include/Platform.h
new file mode 100644
index 0000000000..3c68d65cd3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -0,0 +1,152 @@
+/** @file=0D
+ * Platform headers=0D
+ *=0D
+ * Copyright 2021 NXP=0D
+ * Copyright 2021 Puresoftware Ltd=0D
+ *=0D
+ * SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+ *=0D
+**/=0D
+=0D
+=0D
+#ifndef LS1046AFRWY_PLATFORM_H=0D
+#define LS1046AFRWY_PLATFORM_H=0D
+=0D
+#define EFI_ACPI_ARM_OEM_REVISION 0x00000000=0D
+=0D
+// Soc defines=0D
+#define PLAT_SOC_NAME "LS1046AFRWY"=0D
+=0D
+// Gic=0D
+#define GIC_VERSION 2=0D
+#define GICD_BASE 0x1410000=0D
+#define GICC_BASE 0x142f000=0D
+#define GICH_BASE 0x1440000=0D
+#define GICV_BASE 0x1460000=0D
+=0D
+// UART=0D
+#define UART0_BASE 0x21C0500=0D
+#define UART0_IT 86=0D
+#define UART0_LENGTH 0x100=0D
+#define SPCR_FLOW_CONTROL_NONE 0=0D
+=0D
+// Timer=0D
+#define TIMER_BLOCK_COUNT 1=0D
+#define TIMER_FRAME_COUNT 4=0D
+#define TIMER_WATCHDOG_COUNT 1=0D
+#define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase=0D
+#define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase=0D
+#define TIMER_SEC_IT 29=0D
+#define TIMER_NON_SEC_IT 30=0D
+#define TIMER_VIRT_IT 27=0D
+#define TIMER_HYP_IT 26=0D
+#define TIMER_FRAME0_IT 78=0D
+#define TIMER_FRAME1_IT 79=0D
+#define TIMER_FRAME2_IT 92=0D
+=0D
+// Mcfg=0D
+#define LS1046A_PCI_SEG0_CONFIG_BASE 0x4000000000=0D
+#define LS1046A_PCI_SEG0 0x0=0D
+#define LS1046A_PCI_SEG_BUSNUM_MIN 0x0=0D
+#define LS1046A_PCI_SEG_BUSNUM_MAX 0xff=0D
+#define LS1046A_PCI_SEG1_CONFIG_BASE 0x4800000000=0D
+#define LS1046A_PCI_SEG2_CONFIG_BASE 0x5000000000=0D
+#define LS1046A_PCI_SEG1 0x1=0D
+#define LS1046A_PCI_SEG2 0x2=0D
+=0D
+// Platform specific info needed by Configuration Manager=0D
+=0D
+#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')=0D
+=0D
+// Specify the OEM defined tables=0D
+#define OEM_ACPI_TABLES 0=0D
+=0D
+#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0=0D
+#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE=0D
+#define PLAT_PCI_SEG1 LS1046A_PCI_SEG1=0D
+#define PLAT_PCI_SEG_BUSNUM_MIN LS1046A_PCI_SEG_BUSNUM_MIN=0D
+#define PLAT_PCI_SEG_BUSNUM_MAX LS1046A_PCI_SEG_BUSNUM_MAX=0D
+#define PLAT_PCI_SEG2_CONFIG_BASE LS1046A_PCI_SEG2_CONFIG_BASE=0D
+#define PLAT_PCI_SEG2 LS1046A_PCI_SEG2=0D
+=0D
+#define PLAT_GIC_VERSION GIC_VERSION=0D
+#define PLAT_GICD_BASE GICD_BASE=0D
+#define PLAT_GICI_BASE GICI_BASE=0D
+#define PLAT_GICR_BASE GICR_BASE=0D
+#define PLAT_GICR_LEN GICR_LEN=0D
+#define PLAT_GICC_BASE GICC_BASE=0D
+#define PLAT_GICH_BASE GICH_BASE=0D
+#define PLAT_GICV_BASE GICV_BASE=0D
+=0D
+#define PLAT_CPU_COUNT 4=0D
+#define PLAT_GTBLOCK_COUNT 0=0D
+#define PLAT_GTFRAME_COUNT 0=0D
+#define PLAT_PCI_CONFG_COUNT 2=0D
+=0D
+#define PLAT_WATCHDOG_COUNT 0=0D
+#define PLAT_GIC_REDISTRIBUTOR_COUNT 0=0D
+#define PLAT_GIC_ITS_COUNT 0=0D
+=0D
+/* GIC CPU Interface information=0D
+ GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency=
)=0D
+ */=0D
+#define PLAT_GIC_CPU_INTERFACE { \=0D
+ GICC_ENTRY (0, GET_MPID (0, 0), 138, 0x19, 0), \=0D
+ GICC_ENTRY (1, GET_MPID (0, 1), 139, 0x19, 0), \=0D
+ GICC_ENTRY (2, GET_MPID (0, 2), 127, 0x19, 0), \=0D
+ GICC_ENTRY (3, GET_MPID (0, 3), 129, 0x19, 0), \=0D
+}=0D
+=0D
+#define PLAT_WATCHDOG_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_TIMER_BLOCK_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_TIMER_FRAME_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_DISTRIBUTOR_INFO \=0D
+ { \=0D
+ PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \=0D
+ 0, /* UINT32 SystemVectorBase */ \=0D
+ PLAT_GIC_VERSION /* UINT8 GicVersion */ \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_REDISTRIBUTOR_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_ITS_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_MCFG_INFO \=0D
+ { \=0D
+ { \=0D
+ PLAT_PCI_SEG1_CONFIG_BASE, \=0D
+ PLAT_PCI_SEG1, \=0D
+ PLAT_PCI_SEG_BUSNUM_MIN, \=0D
+ PLAT_PCI_SEG_BUSNUM_MAX, \=0D
+ }, \=0D
+ { \=0D
+ PLAT_PCI_SEG2_CONFIG_BASE, \=0D
+ PLAT_PCI_SEG2, \=0D
+ PLAT_PCI_SEG_BUSNUM_MIN, \=0D
+ PLAT_PCI_SEG_BUSNUM_MAX, \=0D
+ } \=0D
+ } \=0D
+=0D
+#define PLAT_SPCR_INFO =
\=0D
+ { =
\=0D
+ UART0_BASE, =
\=0D
+ UART0_IT, =
\=0D
+ 115200, =
\=0D
+ 0, =
\=0D
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 =
\=0D
+ } =
\=0D
+=0D
+#endif // LS1046AFRWY_PLATFORM_H=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 67cf15cbe4..20111e6037 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -3,6 +3,7 @@
# LS1046AFRWY Board package.=0D
#=0D
# Copyright 2019-2020 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -22,10 +23,18 @@
OUTPUT_DIRECTORY =3D Build/LS1046aFrwyPkg=0D
FLASH_DEFINITION =3D Platform/NXP/LS1046aFrwyPkg/LS1046aFr=
wyPkg.fdf=0D
=0D
+ # This flag controls the dynamic acpi generation=0D
+ #=0D
+ DEFINE DYNAMIC_ACPI_ENABLE =3D TRUE=0D
+=0D
!include Silicon/NXP/NxpQoriqLs.dsc.inc=0D
!include MdePkg/MdeLibs.dsc.inc=0D
!include Silicon/NXP/LS1046A/LS1046A.dsc.inc=0D
=0D
+!if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ !include DynamicTablesPkg/DynamicTables.dsc.inc=0D
+!endif=0D
+=0D
[LibraryClasses.common]=0D
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPla=
tformLib.inf=0D
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal=
TimeClockLib.inf=0D
@@ -46,4 +55,23 @@
=0D
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf=0D
=0D
+ #=0D
+ # Dynamic Table Factory=0D
+ !if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ DynamicTablesPkg/Drivers/DynamicTableFactoryDxe/DynamicTableFactoryDxe=
.inf {=0D
+ <LibraryClasses>=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/AcpiFadtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiGtdtLibArm/AcpiGtdtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibA=
rm.inf=0D
+ }=0D
+ !endif=0D
+=0D
+ #=0D
+ # Acpi Support=0D
+ #=0D
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D
+=0D
##=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 34c4e5a025..f3cac033bc 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -3,6 +3,7 @@
# FLASH layout file for LS1046a board.=0D
#=0D
# Copyright 2019-2020 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -99,6 +100,18 @@ READ_LOCK_STATUS =3D TRUE
INF MdeModulePkg/Universal/Metronome/Metronome.inf=0D
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D
=0D
+=0D
+ #=0D
+ # Acpi Support=0D
+ #=0D
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D
+=0D
+ !if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ INF Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Confi=
gurationManagerDxe.inf=0D
+ !include DynamicTablesPkg/DynamicTables.fdf.inc=0D
+ !endif=0D
+=0D
#=0D
# Multiple Console IO support=0D
#=0D
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10=
46A.dsc.inc
index 7004533ed5..caebb321d0 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -2,6 +2,7 @@
# LS1046A Soc package.=0D
#=0D
# Copyright 2017-2020 NXP=0D
+# Copyright 2021-2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -48,4 +49,14 @@
[Components.common]=0D
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf=0D
=0D
+#=0D
+# Configuration Manager=0D
+!if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configurati=
onManagerDxe.inf {=0D
+ <BuildOptions>=0D
+ *_*_*_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Platform/NXP/LS1046aFrwyPkg/=
Include=0D
+ *_*_*_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Silicon/NXP/Chassis2/Include=
=0D
+ }=0D
+!endif=0D
+=0D
##=0D
--=20
2.25.1


[PATCH V2 2/4] Silicon/NXP: Add support of SVR handling for LS1046A SoC

Vikas Singh
 

This patch adds a generic method to get Silicon Version Register (SVR)
on LS1046A SoC. This method will be generic for all platfroms based
on LS1046A SoC, like - LS1046AFRWY, LS1046ARDB.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10=
46A/Library/SocLib/SocLib.c
index 8fa6a7dd00..003f5bd82f 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -2,6 +2,7 @@
SoC specific Library containg functions to initialize various SoC compon=
ents=0D
=0D
Copyright 2017-2020 NXP=0D
+ Copyright 2021 Puresoftware Ltd=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -64,6 +65,21 @@ SocGetClock (
return ReturnValue;=0D
}=0D
=0D
+/**=0D
+ Function to get SoC's System Version Register(SVR)=0D
+ **/=0D
+UINT32=0D
+SocGetSvr (=0D
+ VOID=0D
+ )=0D
+{=0D
+ LS1046A_DEVICE_CONFIG *Dcfg;=0D
+=0D
+ Dcfg =3D (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;=0D
+=0D
+ return DcfgRead32 ((UINTN)&Dcfg->Svr);=0D
+}=0D
+=0D
/**=0D
Function to select pins depending upon pcd using supplemental=0D
configuration unit(SCFG) extended RCW controlled pinmux control=0D
--=20
2.25.1


[PATCH V2 1/4] Platform/NXP: Make SoC version log in ConfigurationManager generic

Vikas Singh
 

This patch replaces the logic in ConfigurationManager to print platform
name based on platform ID with a simple #define PLAT_SOC_NAME defined in
platform headers.
This also removes duplication of the SVR_LX2160A, SVR_SOC_VER, SVR_MAJOR
and SVR_MINOR macro definitions between SoC headers and platform headers.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configuration=
Manager.c | 11 ++++-------
Platform/NXP/LX2160aRdbPkg/Include/Platform.h =
| 8 ++------
Silicon/NXP/LX2160A/LX2160A.dsc.inc =
| 3 ++-
3 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/C=
onfigurationManager.c b/Platform/NXP/ConfigurationManagerPkg/ConfigurationM=
anagerDxe/ConfigurationManager.c
index 80ce8412c4..39376d900b 100644
--- a/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configur=
ationManager.c
+++ b/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configur=
ationManager.c
@@ -2,7 +2,7 @@
Configuration Manager Dxe=0D
=0D
Copyright 2020 NXP=0D
- Copyright 2020 Puresoftware Ltd=0D
+ Copyright 2020-2021 Puresoftware Ltd=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -25,6 +25,7 @@
*/=0D
#include "ConfigurationManager.h"=0D
#include <Library/SocLib.h>=0D
+#include <Chassis.h>=0D
=0D
/** The platform configuration repository information.=0D
*/=0D
@@ -170,12 +171,8 @@ InitializePlatformRepository (
PlatformRepo =3D This->PlatRepoInfo;=0D
=0D
Svr =3D SocGetSvr ();=0D
- if (SVR_SOC_VER(Svr) =3D=3D SVR_LX2160A) {=0D
- PlatformRepo->FslBoardRevision =3D SVR_MAJOR(Svr);=0D
- DEBUG ((DEBUG_INFO, "Fsl : SoC LX2160A Rev =3D 0x%x\n", PlatformRepo->=
FslBoardRevision));=0D
- } else {=0D
- DEBUG ((DEBUG_INFO, "Fsl : SoC Unknown Rev =3D 0x%x\n", PlatformRepo->=
FslBoardRevision));=0D
- }=0D
+ PlatformRepo->FslBoardRevision =3D SVR_MAJOR(Svr);=0D
+ DEBUG ((DEBUG_INFO, "Fsl : SoC =3D %s Rev =3D 0x%x\n", PLAT_SOC_NAME, Pl=
atformRepo->FslBoardRevision));=0D
=0D
return EFI_SUCCESS;=0D
}=0D
diff --git a/Platform/NXP/LX2160aRdbPkg/Include/Platform.h b/Platform/NXP/L=
X2160aRdbPkg/Include/Platform.h
index 76a41d4369..f2e831f033 100644
--- a/Platform/NXP/LX2160aRdbPkg/Include/Platform.h
+++ b/Platform/NXP/LX2160aRdbPkg/Include/Platform.h
@@ -2,7 +2,7 @@
* Platform headers=0D
*=0D
* Copyright 2020 NXP=0D
- * Copyright 2020 Puresoftware Ltd=0D
+ * Copyright 2020-2021 Puresoftware Ltd=0D
*=0D
* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
*=0D
@@ -15,11 +15,7 @@
#define EFI_ACPI_ARM_OEM_REVISION 0x00000000=0D
=0D
// Soc defines=0D
-#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)=0D
-#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)=0D
-#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)=0D
-=0D
-#define SVR_LX2160A 0x873600=0D
+#define PLAT_SOC_NAME "LX2160ARDB"=0D
=0D
// PCLK=0D
#define DCFG_BASE 0x1E00000=0D
diff --git a/Silicon/NXP/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/LX2160A/LX21=
60A.dsc.inc
index ea7e54fa89..15a06bea1f 100644
--- a/Silicon/NXP/LX2160A/LX2160A.dsc.inc
+++ b/Silicon/NXP/LX2160A/LX2160A.dsc.inc
@@ -2,7 +2,7 @@
# LX2160A Soc package.=0D
#=0D
# Copyright 2018-2020 NXP=0D
-# Copyright 2020 Puresoftware Ltd=0D
+# Copyright 2020-2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -70,6 +70,7 @@
Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configurati=
onManagerDxe.inf {=0D
<BuildOptions>=0D
*_*_*_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Platform/NXP/LX2160aRdbPkg/I=
nclude=0D
+ *_*_*_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Silicon/NXP/Chassis3V2/Inclu=
de=0D
}=0D
!endif=0D
=0D
--=20
2.25.1


[PATCH V2 0/4] Enable Dynamic ACPI for LS1046AFRWY

Vikas Singh
 

This patch series basically aims to extend the Dynamic ACPI
framework towards NXP's LS1046AFRWY platform.

In continuation to https://edk2.groups.io/g/devel/message/71709

The change set in the series is in below order -

(1)Introducing a new platform specific macro "PLAT_SOC_NAME"
This macro will be consumed by Configuration Manager(CM).
Platforms who extends CM services for themselves must notify
their SoC details to CM using this macro only.
Additionally also update the lx2160ardb platform header with
PLAT_SOC_NAME, this will be consumed by CM.

(2)Introduced a function to get SoC's System Version Register(SVR)
This function will fetch SVR details for LS1046A SoC based platforms.
In current patch series, this function will be used by LS1046aFrwyPkg.

(3)Extending Configuration Manager (CM) and its services to leverage
the Dynamic ACPI support for NXP's LS1046aFrwy platform.

(4)Introduced an OEM specific firmware acpi table generator
Also add Dsdt.asl as a place holder having only platform's clock
related dsdt properties for now and will accommodate other IP specific
dsdt tables(acpi properties) for LS1046AFRWY in future patch series.

Vikas Singh (4):
Platform/NXP: Make SoC version log in ConfigurationManager generic
Silicon/NXP: Add support of SVR handling for LS1046A SoC
NXP/LS1046aFrwyPkg: Enable ConfigurationManager on LS1046AFRWY
Platform/NXP/LS1046aFrwyPkg: Add OEM specific DSDT generator

Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c | 11 +-
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl | 60 ++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl | 15 ++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf | 39 +++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c | 138 +++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h | 23 +++
Platform/NXP/LS1046aFrwyPkg/Include/Platform.h | 156 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 29 ++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
Platform/NXP/LX2160aRdbPkg/Include/Platform.h | 8 +-
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 11 ++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 16 ++
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 3 +-
13 files changed, 508 insertions(+), 14 deletions(-)
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Include/Platform.h

--
2.25.1


[edk2-platforms][PATCH v3 41/41] TigerlakeSiliconPkg/BasePchSpiCommonLib: Identify flash regions by GUID

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307

Updates the library to identify flash regions by GUID and internally
map the GUID entries to values specific to TigerlakeSiliconPkg.

Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiComm=
onLib/SpiCommon.c | 176 +++++++++++++++++---
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/Spi=
CommonLib.h | 16 +-
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiComm=
onLib/BaseSpiCommonLib.inf | 18 +-
3 files changed, 177 insertions(+), 33 deletions(-)

diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate=
/BaseSpiCommonLib/SpiCommon.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock=
/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
index 954b349e7c8a..5f372a5b58cb 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSp=
iCommonLib/SpiCommon.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSp=
iCommonLib/SpiCommon.c
@@ -2,9 +2,12 @@
PCH SPI Common Driver implements the SPI Host Controller Compatibility=
Interface.
=20
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi/UefiBaseType.h>
+#include <Guid/FlashRegion.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
@@ -21,6 +24,125 @@
#include <Library/PchPciBdfLib.h>
#include <Library/SpiAccessLib.h>
=20
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbe,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionMicrocodePatch,
+ FlashRegionEc,
+ FlashRegionDeviceExpansion,
+ FlashRegionIe,
+ FlashRegion10GbeA,
+ FlashRegion10GbeB,
+ FlashRegionAll =3D 16,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+typedef struct {
+ EFI_GUID *Guid;
+ FLASH_REGION_TYPE Type;
+} FLASH_REGION_MAPPING;
+
+FLASH_REGION_MAPPING mFlashRegionTypes[] =3D {
+ {
+ &gFlashRegionDescriptorGuid,
+ FlashRegionDescriptor
+ },
+ {
+ &gFlashRegionBiosGuid,
+ FlashRegionBios
+ },
+ {
+ &gFlashRegionMeGuid,
+ FlashRegionMe
+ },
+ {
+ &gFlashRegionGbeGuid,
+ FlashRegionGbe
+ },
+ {
+ &gFlashRegionPlatformDataGuid,
+ FlashRegionPlatformData
+ },
+ {
+ &gFlashRegionDerGuid,
+ FlashRegionDer
+ },
+ {
+ &gFlashRegionSecondaryBiosGuid,
+ FlashRegionSecondaryBios
+ },
+ {
+ &gFlashRegionMicrocodePatchGuid,
+ FlashRegionMicrocodePatch
+ },
+ {
+ &gFlashRegionEcGuid,
+ FlashRegionEc
+ },
+ {
+ &gFlashRegionDeviceExpansionGuid,
+ FlashRegionDeviceExpansion
+ },
+ {
+ &gFlashRegionIeGuid,
+ FlashRegionIe
+ },
+ {
+ &gFlashRegion10GbeAGuid,
+ FlashRegion10GbeA
+ },
+ {
+ &gFlashRegion10GbeBGuid,
+ FlashRegion10GbeB
+ },
+ {
+ &gFlashRegionAllGuid,
+ FlashRegionAll
+ },
+ {
+ &gFlashRegionMaxGuid,
+ FlashRegionMax
+ }
+};
+
+/**
+ Returns the type of a flash region given its GUID.
+
+ @param[in] FlashRegionGuid Pointer to the flash region GUID.
+ @param[out] FlashRegionType Pointer to a buffer that will be set t=
o the flash region type value.
+
+ @retval EFI_SUCCESS The flash region type was found =
for the given flash region GUID.
+ @retval EFI_INVALID_PARAMETER A pointer argument passed to the=
function is NULL.
+ @retval EFI_NOT_FOUND The flash region type was not fo=
und for the given flash region GUID.
+
+**/
+EFI_STATUS
+GetFlashRegionType (
+ IN EFI_GUID *FlashRegionGuid,
+ OUT FLASH_REGION_TYPE *FlashRegionType
+ )
+{
+ UINTN Index;
+
+ if (FlashRegionGuid =3D=3D NULL || FlashRegionType =3D=3D NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ for (Index =3D 0; Index < ARRAY_SIZE (mFlashRegionTypes); Index++) {
+ if (CompareGuid (mFlashRegionTypes[Index].Guid, FlashRegionGuid)) {
+ *FlashRegionType =3D mFlashRegionTypes[Index].Type;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
/**
Initialize an SPI protocol instance.
=20
@@ -179,7 +301,7 @@ SpiProtocolConstructor (
ASSERT (SpiInstance->CpuStrapBaseAddr !=3D 0);
=20
if (SpiInstance->CpuStrapBaseAddr !=3D 0x300) {
- Status =3D SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashR=
egionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
+ Status =3D SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), &gFlas=
hRegionAllGuid, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
ASSERT_EFI_ERROR (Status);
Mdtba =3D (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_=
MDTBA) << N_FLASH_UMAP1_MDTBA_REPR);
DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));
@@ -312,7 +434,7 @@ WaitForSpiCycleComplete (
This function sends the programmed SPI command to the slave device.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] SpiRegionType The SPI Region type for flash cycle wh=
ich is listed in the Descriptor
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] FlashCycleType The Flash SPI cycle type list in HSFC =
(Hardware Sequencing Flash Control Register) register
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@@ -327,7 +449,7 @@ STATIC
EFI_STATUS
SendSpiCmd (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN FLASH_CYCLE_TYPE FlashCycleType,
IN UINT32 Address,
IN UINT32 ByteCount,
@@ -413,7 +535,7 @@ SendSpiCmd (
}
}
=20
- Status =3D SpiProtocolGetRegionAddress (This, FlashRegionType, &Hardwa=
reSpiAddr, &FlashRegionSize);
+ Status =3D SpiProtocolGetRegionAddress (This, FlashRegionGuid, &Hardwa=
reSpiAddr, &FlashRegionSize);
if (EFI_ERROR (Status)) {
goto SendSpiCmdEnd;
}
@@ -626,7 +748,7 @@ SendSpiCmd (
Read data from the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[out] Buffer The Pointer to caller-allocated buffer=
containing the dada received.
@@ -640,7 +762,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashRead (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
OUT UINT8 *Buffer
@@ -653,7 +775,7 @@ SpiProtocolFlashRead (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleRead,
Address,
ByteCount,
@@ -666,7 +788,7 @@ SpiProtocolFlashRead (
Write data to the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[in] Buffer Pointer to caller-allocated buffer con=
taining the data sent during the SPI cycle.
@@ -679,7 +801,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashWrite (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
IN UINT8 *Buffer
@@ -692,7 +814,7 @@ SpiProtocolFlashWrite (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleWrite,
Address,
ByteCount,
@@ -705,7 +827,7 @@ SpiProtocolFlashWrite (
Erase some area on the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
=20
@@ -717,7 +839,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashErase (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount
)
@@ -729,7 +851,7 @@ SpiProtocolFlashErase (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleErase,
Address,
ByteCount,
@@ -790,7 +912,7 @@ SpiProtocolFlashReadSfdp (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadSfdp,
FlashAddress,
ByteCount,
@@ -849,7 +971,7 @@ SpiProtocolFlashReadJedecId (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadJedecId,
Address,
ByteCount,
@@ -890,7 +1012,7 @@ SpiProtocolFlashWriteStatus (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleWriteStatus,
0,
ByteCount,
@@ -931,7 +1053,7 @@ SpiProtocolFlashReadStatus (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadStatus,
0,
ByteCount,
@@ -944,7 +1066,7 @@ SpiProtocolFlashReadStatus (
Get the SPI region base and size, based on the enum type
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for for the base=
address which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for the base add=
ress which corresponds to the type in the descriptor.
@param[out] BaseAddress The Flash Linear Address for the Regio=
n 'n' Base
@param[out] RegionSize The size for the Region 'n'
=20
@@ -956,17 +1078,23 @@ EFI_STATUS
EFIAPI
SpiProtocolGetRegionAddress (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
OUT UINT32 *BaseAddress,
OUT UINT32 *RegionSize
)
{
- SPI_INSTANCE *SpiInstance;
- UINTN PchSpiBar0;
- UINT32 ReadValue;
+ EFI_STATUS Status;
+ FLASH_REGION_TYPE FlashRegionType;
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
=20
SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);
=20
+ Status =3D GetFlashRegionType (FlashRegionGuid, &FlashRegionType);
+ if (EFI_ERROR (Status)) {
+ return EFI_INVALID_PARAMETER;
+ }
if (FlashRegionType >=3D FlashRegionMax) {
return EFI_INVALID_PARAMETER;
}
@@ -1047,7 +1175,7 @@ SpiProtocolReadPchSoftStrap (
//
Status =3D SendSpiCmd (
This,
- FlashRegionDescriptor,
+ &gFlashRegionDescriptorGuid,
FlashCycleRead,
StrapFlashAddr,
ByteCount,
@@ -1105,7 +1233,7 @@ SpiProtocolReadCpuSoftStrap (
//
Status =3D SendSpiCmd (
This,
- FlashRegionDescriptor,
+ &gFlashRegionDescriptorGuid,
FlashCycleRead,
StrapFlashAddr,
ByteCount,
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate=
/Library/SpiCommonLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/I=
ncludePrivate/Library/SpiCommonLib.h
index 3290f7712280..3038ae749ef2 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Librar=
y/SpiCommonLib.h
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Librar=
y/SpiCommonLib.h
@@ -146,7 +146,7 @@ IsSpiFlashWriteGranted (
Read data from the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[out] Buffer The Pointer to caller-allocated buffer=
containing the dada received.
@@ -160,7 +160,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashRead (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
OUT UINT8 *Buffer
@@ -170,7 +170,7 @@ SpiProtocolFlashRead (
Write data to the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[in] Buffer Pointer to caller-allocated buffer con=
taining the data sent during the SPI cycle.
@@ -183,7 +183,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashWrite (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
IN UINT8 *Buffer
@@ -193,7 +193,7 @@ SpiProtocolFlashWrite (
Erase some area on the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
=20
@@ -205,7 +205,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashErase (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount
);
@@ -298,7 +298,7 @@ SpiProtocolFlashReadStatus (
Get the SPI region base and size, based on the enum type
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for for the base=
address which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for the base add=
ress which corresponds to the type in the descriptor.
@param[out] BaseAddress The Flash Linear Address for the Regio=
n 'n' Base
@param[out] RegionSize The size for the Region 'n'
=20
@@ -310,7 +310,7 @@ EFI_STATUS
EFIAPI
SpiProtocolGetRegionAddress (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
OUT UINT32 *BaseAddress,
OUT UINT32 *RegionSize
);
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate=
/BaseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/TigerlakeSiliconPk=
g/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
index 2686dff41e25..4981276e13e8 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSp=
iCommonLib/BaseSpiCommonLib.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSp=
iCommonLib/BaseSpiCommonLib.inf
@@ -2,6 +2,7 @@
# Component description file for the PchSpiCommonLib
#
# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -29,4 +30,19 @@ [LibraryClasses]
PchPciBdfLib
SpiAccessLib
=20
-[Pcd]
+[Guids]
+ gFlashRegionDescriptorGuid
+ gFlashRegionBiosGuid
+ gFlashRegionMeGuid
+ gFlashRegionGbeGuid
+ gFlashRegionPlatformDataGuid
+ gFlashRegionDerGuid
+ gFlashRegionSecondaryBiosGuid
+ gFlashRegionMicrocodePatchGuid
+ gFlashRegionEcGuid
+ gFlashRegionDeviceExpansionGuid
+ gFlashRegionIeGuid
+ gFlashRegion10GbeAGuid
+ gFlashRegion10GbeBGuid
+ gFlashRegionAllGuid
+ gFlashRegionMaxGuid
--=20
2.28.0.windows.1


[edk2-platforms][PATCH v3 40/41] SimicsIch10Pkg/BasePchSpiCommonLib: Identify flash regions by GUID

Michael Kubacki
 

From: Michael Kubacki <michael.kubacki@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307

Updates the library to identify flash regions by GUID and internally
map the GUID entries to values specific to SimicsIch10Pkg.

Cc: Agyeman Prince <prince.agyeman@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommo=
n.c | 139 ++++++++++++++++----
Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCommonLib.h =
| 20 +--
Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/BasePchS=
piCommonLib.inf | 11 ++
3 files changed, 137 insertions(+), 33 deletions(-)

diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommon=
Lib/SpiCommon.c b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiC=
ommonLib/SpiCommon.c
index fc2a8be76b6a..04dbd921c091 100644
--- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Spi=
Common.c
+++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Spi=
Common.c
@@ -2,11 +2,13 @@
PCH SPI Common Driver implements the SPI Host Controller Compatibility=
Interface.
=20
Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+ Copyright (c) Microsoft Corporation.<BR>
=20
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
=20
#include <Uefi/UefiBaseType.h>
+#include <Guid/FlashRegion.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
@@ -16,6 +18,90 @@
#include <IncludePrivate/Library/PchSpiCommonLib.h>
#include <Register/X58Ich10.h>
=20
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbe,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+typedef struct {
+ EFI_GUID *Guid;
+ FLASH_REGION_TYPE Type;
+} FLASH_REGION_MAPPING;
+
+FLASH_REGION_MAPPING mFlashRegionTypes[] =3D {
+ {
+ &gFlashRegionDescriptorGuid,
+ FlashRegionDescriptor
+ },
+ {
+ &gFlashRegionBiosGuid,
+ FlashRegionBios
+ },
+ {
+ &gFlashRegionMeGuid,
+ FlashRegionMe
+ },
+ {
+ &gFlashRegionGbeGuid,
+ FlashRegionGbe
+ },
+ {
+ &gFlashRegionPlatformDataGuid,
+ FlashRegionPlatformData
+ },
+ {
+ &gFlashRegionDerGuid,
+ FlashRegionDer
+ },
+ {
+ &gFlashRegionAllGuid,
+ FlashRegionAll
+ },
+ {
+ &gFlashRegionMaxGuid,
+ FlashRegionMax
+ }
+};
+
+/**
+ Returns the type of a flash region given its GUID.
+
+ @param[in] FlashRegionGuid Pointer to the flash region GUID.
+ @param[out] FlashRegionType Pointer to a buffer that will be set t=
o the flash region type value.
+
+ @retval EFI_SUCCESS The flash region type was found =
for the given flash region GUID.
+ @retval EFI_INVALID_PARAMETER A pointer argument passed to the=
function is NULL.
+ @retval EFI_NOT_FOUND The flash region type was not fo=
und for the given flash region GUID.
+
+**/
+EFI_STATUS
+GetFlashRegionType (
+ IN EFI_GUID *FlashRegionGuid,
+ OUT FLASH_REGION_TYPE *FlashRegionType
+ )
+{
+ UINTN Index;
+
+ if (FlashRegionGuid =3D=3D NULL || FlashRegionType =3D=3D NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ for (Index =3D 0; Index < ARRAY_SIZE (mFlashRegionTypes); Index++) {
+ if (CompareGuid (mFlashRegionTypes[Index].Guid, FlashRegionGuid)) {
+ *FlashRegionType =3D mFlashRegionTypes[Index].Type;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
/**
Initialize an SPI protocol instance.
=20
@@ -145,7 +231,7 @@ PchPmTimerStallRuntimeSafe (
Read data from the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[out] Buffer The Pointer to caller-allocated buffer=
containing the dada received.
@@ -159,7 +245,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashRead (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
OUT UINT8 *Buffer
@@ -172,7 +258,7 @@ SpiProtocolFlashRead (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleRead,
Address,
ByteCount,
@@ -185,7 +271,7 @@ SpiProtocolFlashRead (
Write data to the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[in] Buffer Pointer to caller-allocated buffer con=
taining the data sent during the SPI cycle.
@@ -198,7 +284,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashWrite (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
IN UINT8 *Buffer
@@ -211,7 +297,7 @@ SpiProtocolFlashWrite (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleWrite,
Address,
ByteCount,
@@ -224,7 +310,7 @@ SpiProtocolFlashWrite (
Erase some area on the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
=20
@@ -236,7 +322,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashErase (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount
)
@@ -248,7 +334,7 @@ SpiProtocolFlashErase (
//
Status =3D SendSpiCmd (
This,
- FlashRegionType,
+ FlashRegionGuid,
FlashCycleErase,
Address,
ByteCount,
@@ -303,7 +389,7 @@ SpiProtocolFlashReadSfdp (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadSfdp,
FlashAddress,
ByteCount,
@@ -356,7 +442,7 @@ SpiProtocolFlashReadJedecId (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadJedecId,
Address,
ByteCount,
@@ -391,7 +477,7 @@ SpiProtocolFlashWriteStatus (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleWriteStatus,
0,
ByteCount,
@@ -426,7 +512,7 @@ SpiProtocolFlashReadStatus (
//
Status =3D SendSpiCmd (
This,
- FlashRegionAll,
+ &gFlashRegionAllGuid,
FlashCycleReadStatus,
0,
ByteCount,
@@ -439,7 +525,7 @@ SpiProtocolFlashReadStatus (
Get the SPI region base and size, based on the enum type
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for for the base=
address which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for the base add=
ress which corresponds to the type in the descriptor.
@param[out] BaseAddress The Flash Linear Address for the Regio=
n 'n' Base
@param[out] RegionSize The size for the Region 'n'
=20
@@ -451,17 +537,24 @@ EFI_STATUS
EFIAPI
SpiProtocolGetRegionAddress (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
OUT UINT32 *BaseAddress,
OUT UINT32 *RegionSize
)
{
- SPI_INSTANCE *SpiInstance;
- UINTN PchSpiBar0;
- UINT32 ReadValue;
+ EFI_STATUS Status;
+ FLASH_REGION_TYPE FlashRegionType;
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
=20
SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);
=20
+ Status =3D GetFlashRegionType (FlashRegionGuid, &FlashRegionType);
+ if (EFI_ERROR (Status)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
if (FlashRegionType >=3D FlashRegionMax) {
return EFI_INVALID_PARAMETER;
}
@@ -542,7 +635,7 @@ SpiProtocolReadPchSoftStrap (
//
Status =3D SendSpiCmd (
This,
- FlashRegionDescriptor,
+ &gFlashRegionDescriptorGuid,
FlashCycleRead,
StrapFlashAddr,
ByteCount,
@@ -600,7 +693,7 @@ SpiProtocolReadCpuSoftStrap (
//
Status =3D SendSpiCmd (
This,
- FlashRegionDescriptor,
+ &gFlashRegionDescriptorGuid,
FlashCycleRead,
StrapFlashAddr,
ByteCount,
@@ -613,7 +706,7 @@ SpiProtocolReadCpuSoftStrap (
This function sends the programmed SPI command to the slave device.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] SpiRegionType The SPI Region type for flash cycle wh=
ich is listed in the Descriptor
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] FlashCycleType The Flash SPI cycle type list in HSFC =
(Hardware Sequencing Flash Control Register) register
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@@ -627,7 +720,7 @@ SpiProtocolReadCpuSoftStrap (
EFI_STATUS
SendSpiCmd (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN FLASH_CYCLE_TYPE FlashCycleType,
IN UINT32 Address,
IN UINT32 ByteCount,
@@ -682,7 +775,7 @@ SendSpiCmd (
goto SendSpiCmdEnd;
}
=20
- Status =3D SpiProtocolGetRegionAddress (This, FlashRegionType, &Hardwa=
reSpiAddr, &FlashRegionSize);
+ Status =3D SpiProtocolGetRegionAddress (This, FlashRegionGuid, &Hardwa=
reSpiAddr, &FlashRegionSize);
if (EFI_ERROR (Status)) {
goto SendSpiCmdEnd;
}
diff --git a/Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCo=
mmonLib.h b/Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCom=
monLib.h
index 2c8162ac8170..603e141e2058 100644
--- a/Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCommonLib=
.h
+++ b/Silicon/Intel/SimicsIch10Pkg/IncludePrivate/Library/PchSpiCommonLib=
.h
@@ -135,7 +135,7 @@ ReleaseSpiBar0 (
Read data from the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[out] Buffer The Pointer to caller-allocated buffer=
containing the dada received.
@@ -149,7 +149,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashRead (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
OUT UINT8 *Buffer
@@ -159,7 +159,7 @@ SpiProtocolFlashRead (
Write data to the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@param[in] Buffer Pointer to caller-allocated buffer con=
taining the data sent during the SPI cycle.
@@ -172,7 +172,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashWrite (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount,
IN UINT8 *Buffer
@@ -182,7 +182,7 @@ SpiProtocolFlashWrite (
Erase some area on the flash part.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for flash cycle =
which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
=20
@@ -194,7 +194,7 @@ EFI_STATUS
EFIAPI
SpiProtocolFlashErase (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN UINT32 Address,
IN UINT32 ByteCount
);
@@ -287,7 +287,7 @@ SpiProtocolFlashReadStatus (
Get the SPI region base and size, based on the enum type
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] FlashRegionType The Flash Region type for for the base=
address which is listed in the Descriptor.
+ @param[in] FlashRegionGuid The Flash Region GUID for the base add=
ress which corresponds to the type in the descriptor.
@param[out] BaseAddress The Flash Linear Address for the Regio=
n 'n' Base
@param[out] RegionSize The size for the Region 'n'
=20
@@ -299,7 +299,7 @@ EFI_STATUS
EFIAPI
SpiProtocolGetRegionAddress (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
OUT UINT32 *BaseAddress,
OUT UINT32 *RegionSize
);
@@ -354,7 +354,7 @@ SpiProtocolReadCpuSoftStrap (
This function sends the programmed SPI command to the slave device.
=20
@param[in] This Pointer to the PCH_SPI_PROTOCOL instan=
ce.
- @param[in] SpiRegionType The SPI Region type for flash cycle wh=
ich is listed in the Descriptor
+ @param[in] FlashRegionGuid The Flash Region GUID for flash cycle =
which corresponds to the type in the descriptor.
@param[in] FlashCycleType The Flash SPI cycle type list in HSFC =
(Hardware Sequencing Flash Control Register) register
@param[in] Address The Flash Linear Address must fall wit=
hin a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of=
the SPI cycle.
@@ -368,7 +368,7 @@ SpiProtocolReadCpuSoftStrap (
EFI_STATUS
SendSpiCmd (
IN PCH_SPI_PROTOCOL *This,
- IN FLASH_REGION_TYPE FlashRegionType,
+ IN EFI_GUID *FlashRegionGuid,
IN FLASH_CYCLE_TYPE FlashCycleType,
IN UINT32 Address,
IN UINT32 ByteCount,
diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommon=
Lib/BasePchSpiCommonLib.inf b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate=
/BasePchSpiCommonLib/BasePchSpiCommonLib.inf
index b5aa13c1c56d..3a64005b5690 100644
--- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Bas=
ePchSpiCommonLib.inf
+++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Bas=
ePchSpiCommonLib.inf
@@ -2,6 +2,7 @@
# Component description file for the PchSpiCommonLib
#
# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+# Copyright (c) Microsoft Corporation.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -30,3 +31,13 @@ [LibraryClasses]
[Pcd]
gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Guids]
+ gFlashRegionDescriptorGuid
+ gFlashRegionBiosGuid
+ gFlashRegionMeGuid
+ gFlashRegionGbeGuid
+ gFlashRegionPlatformDataGuid
+ gFlashRegionDerGuid
+ gFlashRegionAllGuid
+ gFlashRegionMaxGuid
--=20
2.28.0.windows.1

5941 - 5960 of 82645