Date   

[PATCH v2 7/8] DynamicTablesPkg: Update ArmNameSpaceObjects for IORT Rev E.b

Sami Mujawar
 

Bugzilla: 3458 - Add support IORT Rev E.b specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.b,
Feb 2021 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E and Rev E.a:
- increments the IORT table revision to 3.
- updates the node definition to add an 'Identifier' field.
- adds definition of node type 6 - Reserved Memory Range node.
- adds definition for Memory Range Descriptors.
- adds flag to indicate PRI support for root complexes.
- adds flag to indicate if the root complex supports forwarding
of PASID information on translated transactions to the SMMU.

Therefore, update the Arm namespace objects to:
- add Identifier field to IORT nodes.
- introduce enums to represent RMR nodes and Memory Range
descriptors.
- add definition of node type 6 - Reserved Memory Range node.
- add definition for Memory Range Descriptors.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- No code change since v1. Re-sending with v2 series. [SAMI]

DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 58 ++++++++++++++++++++
1 file changed, 58 insertions(+)

diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index 19dcae13b2191e5f0b03ea85edec1191d2a406bf..98143cb5df127273cdd75452170fa651372b3896 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -58,6 +58,8 @@ typedef enum ArmObjectID {
EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info
EArmObjCmn600Info, ///< 36 - CMN-600 Info
+ EArmObjRmr, ///< 37 - Reserved Memory Range Node
+ EArmObjMemoryRangeDescriptor, ///< 38 - Memory Range Descriptor
EArmObjMax
} EARM_OBJECT_ID;

@@ -466,6 +468,9 @@ typedef struct CmArmItsGroupNode {
UINT32 ItsIdCount;
/// Reference token for the ITS identifier array
CM_OBJECT_TOKEN ItsIdToken;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_ITS_GROUP_NODE;

/** A structure that describes the
@@ -497,6 +502,9 @@ typedef struct CmArmNamedComponentNode {
the entry in the namespace for this object.
*/
CHAR8* ObjectName;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_NAMED_COMPONENT_NODE;

/** A structure that describes the
@@ -525,6 +533,9 @@ typedef struct CmArmRootComplexNode {
UINT32 PciSegmentNumber;
/// Memory address size limit
UINT8 MemoryAddressSize;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_ROOT_COMPLEX_NODE;

/** A structure that describes the
@@ -567,6 +578,9 @@ typedef struct CmArmSmmuV1SmmuV2Node {
UINT32 SMMU_NSgCfgIrpt;
/// SMMU_NSgCfgIrpt interrupt flags
UINT32 SMMU_NSgCfgIrptFlags;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_SMMUV1_SMMUV2_NODE;

/** A structure that describes the
@@ -603,6 +617,9 @@ typedef struct CmArmSmmuV3Node {
UINT32 ProximityDomain;
/// Index into the array of ID mapping
UINT32 DeviceIdMappingIndex;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_SMMUV3_NODE;

/** A structure that describes the
@@ -627,6 +644,9 @@ typedef struct CmArmPmcgNode {

/// Reference token for the IORT node associated with this node
CM_OBJECT_TOKEN ReferenceToken;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
} CM_ARM_PMCG_NODE;

/** A structure that describes the
@@ -878,6 +898,44 @@ typedef struct CmArmCmn600Info {
CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
} CM_ARM_CMN_600_INFO;

+/** A structure that describes the
+ RMR node for the Platform.
+
+ ID: EArmObjRmr
+*/
+typedef struct CmArmRmrNode {
+ /// An unique token used to identify this object
+ CM_OBJECT_TOKEN Token;
+ /// Number of ID mappings
+ UINT32 IdMappingCount;
+ /// Reference token for the ID mapping array
+ CM_OBJECT_TOKEN IdMappingToken;
+
+ /// Reserved Memory Range flags.
+ UINT32 Flags;
+
+ /// Memory range descriptor count.
+ UINT32 MemRangeDescCount;
+ /// Reference token for the Memory Range descriptor array
+ CM_OBJECT_TOKEN MemRangeDescToken;
+
+ /// Unique identifier for this node.
+ UINT32 Identifier;
+} CM_ARM_RMR_NODE;
+
+/** A structure that describes the
+ Memory Range descriptor.
+
+ ID: EArmObjMemoryRangeDescriptor
+*/
+typedef struct CmArmRmrDescriptor {
+ /// Base address.
+ UINT64 BaseAddress;
+
+ /// Length.
+ UINT64 Length;
+} CM_ARM_MEMORY_RANGE_DESCRIPTOR;
+
#pragma pack()

#endif // ARM_NAMESPACE_OBJECTS_H_
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 4/8] ShellPkg: Acpiview: IORT parser update for IORT Rev E.b spec

Sami Mujawar
 

Bugzilla: 3458 - Add support IORT Rev E.b specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table, Platform Design Document, Revision E.b,
Feb 2021 (https://developer.arm.com/documentation/den0049/)
introduces the following updates, collectively including the
updates and errata fixes to Rev E and Rev E.a:
- increments the IORT table revision to 3.
- updates the node definition to add an 'Identifier' field.
- adds definition of node type 6 - Reserved Memory Range node.
- adds definition for Memory Range Descriptors.
- adds flag to indicate PRI support for root complexes.
- adds flag to indicate if the root complex supports forwarding
of PASID information on translated transactions to the SMMU.

Therefore, update the IORT parser to:
- parse the Identifier field.
- parse Reserved Memory Range node.
- parse Memory Range Descriptors.
- add validations to check that the physical range base
and size of the Memory Range Descriptor is 64KB aligned.
- add validation to check that the ID mapping count is
set to 1.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- No code change since v1. Re-sending with v2 series. [SAMI]

ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c | 196 +++++++++++++++++++-
1 file changed, 191 insertions(+), 5 deletions(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
index fcecaff5134256497bda87241f339076897c3ece..1507dd3a4d79e61024b0c5526e21ffdacb782251 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
@@ -5,10 +5,12 @@
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
- - IO Remapping Table, Platform Design Document, Revision D, March 2018
+ - IO Remapping Table, Platform Design Document, Revision E.b, Feb 2021
+ (https://developer.arm.com/documentation/den0049/)

@par Glossary:
- Ref - Reference
+ - Desc - Descriptor
**/

#include <IndustryStandard/IoRemappingTable.h>
@@ -36,6 +38,9 @@ STATIC CONST UINT32* PmuInterruptOffset;

STATIC CONST UINT32* ItsCount;

+STATIC CONST UINT32* RmrMemDescCount;
+STATIC CONST UINT32* RmrMemDescOffset;
+
/**
This function validates the ID Mapping array count for the ITS node.

@@ -100,6 +105,72 @@ ValidateItsIdArrayReference (
}
}

+/**
+ This function validates that the address or length is 64K aligned.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+Validate64KAlignment (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ )
+{
+ UINT64 Address;
+ Address = *(UINT64*)Ptr;
+ if ((Address & (SIZE_64KB - 1)) != 0) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Value must be 64K aligned.");
+ }
+}
+
+/**
+ This function validates that the RMR memory range descriptor count.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateRmrMemDescCount (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ )
+{
+ if (*(UINT32*)Ptr == 0) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Memory Range Descriptor count must be >=1.");
+ }
+}
+
+/**
+ This function validates the ID Mapping array count for the Reserved
+ Memory Range (RMR) node.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateRmrIdMappingCount (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ )
+{
+ if (*(UINT32*)Ptr != 1) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: IORT ID Mapping count must be set to 1.");
+ }
+}
+
/**
Helper Macro for populating the IORT Node header in the ACPI_PARSER array.

@@ -113,7 +184,7 @@ ValidateItsIdArrayReference (
{ L"Type", 1, 0, L"%d", NULL, (VOID**)&IortNodeType, NULL, NULL }, \
{ L"Length", 2, 1, L"%d", NULL, (VOID**)&IortNodeLength, NULL, NULL }, \
{ L"Revision", 1, 3, L"%d", NULL, NULL, NULL, NULL }, \
- { L"Reserved", 4, 4, L"0x%x", NULL, NULL, NULL, NULL }, \
+ { L"Identifier", 4, 4, L"0x%x", NULL, NULL, NULL, NULL }, \
{ L"Number of ID mappings", 4, 8, L"%d", NULL, \
(VOID**)&IortIdMappingCount, ValidateIdMappingCount, NULL }, \
{ L"Reference to ID Array", 4, 12, L"0x%x", NULL, \
@@ -253,6 +324,29 @@ STATIC CONST ACPI_PARSER IortNodePmcgParser[] = {
{L"Page 1 Base Address", 8, 32, L"0x%lx", NULL, NULL, NULL, NULL}
};

+/**
+ An ACPI_PARSER array describing the IORT RMR node.
+**/
+STATIC CONST ACPI_PARSER IortNodeRmrParser[] = {
+ PARSE_IORT_NODE_HEADER (ValidateRmrIdMappingCount, NULL),
+ {L"Flags", 4, 16, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"Memory Range Desc count", 4, 20, L"%d", NULL,
+ (VOID**)&RmrMemDescCount, ValidateRmrMemDescCount, NULL},
+ {L"Memory Range Desc Ref", 4, 24, L"0x%x", NULL,
+ (VOID**)&RmrMemDescOffset, NULL, NULL}
+};
+
+/**
+ An ACPI_PARSER array describing the IORT RMR Memory Range Descriptor.
+**/
+STATIC CONST ACPI_PARSER IortNodeRmrMemRangeDescParser[] = {
+ {L"Physical Range offset", 8, 0, L"0x%lx", NULL, NULL, Validate64KAlignment,
+ NULL},
+ {L"Physical Range length", 8, 8, L"0x%lx", NULL, NULL, Validate64KAlignment,
+ NULL},
+ {L"Reserved", 4, 16, L"0x%x", NULL, NULL, NULL, NULL}
+};
+
/**
This function parses the IORT Node Id Mapping array.

@@ -601,9 +695,93 @@ DumpIortNodePmcg (
);
}

+/**
+ This function parses the IORT RMR Node Memory Range Descriptor array.
+
+ @param [in] Ptr Pointer to the start of the Memory Range Descriptor
+ array.
+ @param [in] Length Length of the buffer.
+ @param [in] DescCount Memory Range Descriptor count.
+**/
+STATIC
+VOID
+DumpIortNodeRmrMemRangeDesc (
+ IN UINT8* Ptr,
+ IN UINT32 Length,
+ IN UINT32 DescCount
+ )
+{
+ UINT32 Index;
+ UINT32 Offset;
+ CHAR8 Buffer[40]; // Used for AsciiName param of ParseAcpi
+
+ Index = 0;
+ Offset = 0;
+
+ while ((Index < DescCount) &&
+ (Offset < Length)) {
+ AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "Mem range Descriptor [%d]",
+ Index
+ );
+ Offset += ParseAcpi (
+ TRUE,
+ 4,
+ Buffer,
+ Ptr + Offset,
+ Length - Offset,
+ PARSER_PARAMS (IortNodeRmrMemRangeDescParser)
+ );
+ Index++;
+ }
+}
+
+/**
+ This function parses the IORT RMR node.
+
+ @param [in] Ptr Pointer to the start of the buffer.
+ @param [in] Length Length of the buffer.
+ @param [in] MappingCount The ID Mapping count.
+ @param [in] MappingOffset The offset of the ID Mapping array
+ from the start of the IORT table.
+**/
+STATIC
+VOID
+DumpIortNodeRmr (
+ IN UINT8* Ptr,
+ IN UINT16 Length,
+ IN UINT32 MappingCount,
+ IN UINT32 MappingOffset
+)
+{
+ ParseAcpi (
+ TRUE,
+ 2,
+ "RMR Node",
+ Ptr,
+ Length,
+ PARSER_PARAMS (IortNodeRmrParser)
+ );
+
+ DumpIortNodeIdMappings (
+ Ptr + MappingOffset,
+ Length - MappingOffset,
+ MappingCount
+ );
+
+ DumpIortNodeRmrMemRangeDesc (
+ Ptr + (*RmrMemDescOffset),
+ Length - (*RmrMemDescOffset),
+ *RmrMemDescCount
+ );
+}
+
/**
This function parses the ACPI IORT table.
- When trace is enabled this function parses the IORT table and traces the ACPI fields.
+ When trace is enabled this function parses the IORT table and traces the ACPI
+ fields.

This function also parses the following nodes:
- ITS Group
@@ -612,6 +790,7 @@ DumpIortNodePmcg (
- SMMUv1/2
- SMMUv3
- PMCG
+ - RMR

This function also performs validation of the ACPI table fields.

@@ -753,9 +932,16 @@ ParseAcpiIort (
*IortNodeLength,
*IortIdMappingCount,
*IortIdMappingOffset
- );
+ );
+ break;
+ case EFI_ACPI_IORT_TYPE_RMR:
+ DumpIortNodeRmr (
+ NodePtr,
+ *IortNodeLength,
+ *IortIdMappingCount,
+ *IortIdMappingOffset
+ );
break;
-
default:
IncrementErrorCount ();
Print (L"ERROR: Unsupported IORT Node type = %d\n", *IortNodeType);
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 5/8] DynamicTablesPkg: IORT set reference to Id array only if present

Sami Mujawar
 

The IORT table generator is setting up a reference to ID array for
nodes even when the ID Mapping count is zero. This is not an issue as an
OS would only access the ID Reference if the ID mapping count is not zero.

However, it would be good to set the reference to ID array to zero when
the ID Mapping count is zero rather than populating it with an incorrect
value.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- No code change since v1. Re-sending with v2 series. [SAMI]

DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c | 29 +++++++++++---------
1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c
index 349caa8006bc34ca789cb3e321a0f87c0cd4ff0d..bdf839eab25e2b84b40c50da38f2bf961cdc5f42 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c
@@ -1,7 +1,7 @@
/** @file
IORT Table Generator

- Copyright (c) 2017 - 2020, ARM Limited. All rights reserved.
+ Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
@@ -870,9 +870,9 @@ AddNamedComponentNodes (
NcNode->Node.NumIdMappings = NodeList->IdMappingCount;

ObjectNameLength = AsciiStrLen (NodeList->ObjectName) + 1;
- NcNode->Node.IdReference =
- (UINT32)(sizeof (EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE) +
- (ALIGN_VALUE (ObjectNameLength, 4)));
+ NcNode->Node.IdReference = (NodeList->IdMappingCount == 0) ?
+ 0 : ((UINT32)(sizeof (EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE) +
+ (ALIGN_VALUE (ObjectNameLength, 4))));

// Named Component specific data
NcNode->Flags = NodeList->Flags;
@@ -990,7 +990,8 @@ AddRootComplexNodes (
RcNode->Node.Revision = 1;
RcNode->Node.Reserved = EFI_ACPI_RESERVED_DWORD;
RcNode->Node.NumIdMappings = NodeList->IdMappingCount;
- RcNode->Node.IdReference = sizeof (EFI_ACPI_6_0_IO_REMAPPING_RC_NODE);
+ RcNode->Node.IdReference = (NodeList->IdMappingCount == 0) ?
+ 0 : sizeof (EFI_ACPI_6_0_IO_REMAPPING_RC_NODE);

// Root Complex specific data
RcNode->CacheCoherent = NodeList->CacheCoherent;
@@ -1160,11 +1161,12 @@ AddSmmuV1V2Nodes (
SmmuNode->Node.Revision = 0;
SmmuNode->Node.Reserved = EFI_ACPI_RESERVED_DWORD;
SmmuNode->Node.NumIdMappings = NodeList->IdMappingCount;
- SmmuNode->Node.IdReference = sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE) +
- (NodeList->ContextInterruptCount *
- sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT)) +
- (NodeList->PmuInterruptCount *
- sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT));
+ SmmuNode->Node.IdReference = (NodeList->IdMappingCount == 0) ?
+ 0 : (sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE) +
+ (NodeList->ContextInterruptCount *
+ sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT)) +
+ (NodeList->PmuInterruptCount *
+ sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT)));

// SMMU v1/v2 specific data
SmmuNode->Base = NodeList->BaseAddress;
@@ -1319,8 +1321,8 @@ AddSmmuV3Nodes (
SmmuV3Node->Node.Revision = 2;
SmmuV3Node->Node.Reserved = EFI_ACPI_RESERVED_DWORD;
SmmuV3Node->Node.NumIdMappings = NodeList->IdMappingCount;
- SmmuV3Node->Node.IdReference =
- sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE);
+ SmmuV3Node->Node.IdReference = (NodeList->IdMappingCount == 0) ?
+ 0 : sizeof (EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE);

// SMMUv3 specific data
SmmuV3Node->Base = NodeList->BaseAddress;
@@ -1438,7 +1440,8 @@ AddPmcgNodes (
PmcgNode->Node.Revision = 1;
PmcgNode->Node.Reserved = EFI_ACPI_RESERVED_DWORD;
PmcgNode->Node.NumIdMappings = NodeList->IdMappingCount;
- PmcgNode->Node.IdReference = sizeof (EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE);
+ PmcgNode->Node.IdReference = (NodeList->IdMappingCount == 0) ?
+ 0 : sizeof (EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE);

// PMCG specific data
PmcgNode->Base = NodeList->BaseAddress;
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 1/8] MdePkg: Fix IORT header file include guard

Sami Mujawar
 

According to section 5.3.5, EDK II C Coding Standards Specification
(https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification)
the header file guard names must not be prefixed with underscores as
they are reserved for compiler implementation.

Therefore, fix the header file include guard as per the specification
guidelines.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- No code change since v1. Re-sending with v2 series. [SAMI]

MdePkg/Include/IndustryStandard/IoRemappingTable.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
index 90504e3a6715be7facc6450c6ff0e1eab92cd3c7..731217441438a00dd5ff0bedf2010598d48d6dbf 100644
--- a/MdePkg/Include/IndustryStandard/IoRemappingTable.h
+++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -9,8 +9,8 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

-#ifndef __IO_REMAPPING_TABLE_H__
-#define __IO_REMAPPING_TABLE_H__
+#ifndef IO_REMAPPING_TABLE_H_
+#define IO_REMAPPING_TABLE_H_

#include <IndustryStandard/Acpi.h>

--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 3/8] ShellPkg: Acpiview: Abbreviate field names to preserve alignment

Sami Mujawar
 

Some field names in the IORT table parser were longer than the
OUTPUT_FIELD_COLUMN_WIDTH plus indentation, resulting in loss of
the output print alignment. Therefore, abbreviate the field names.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- No code change since v1. Re-sending with v2 series. [SAMI]

ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
index f7447947b2308d35d4d2890373778f0fd2f97f9e..fcecaff5134256497bda87241f339076897c3ece 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c
@@ -1,11 +1,14 @@
/** @file
IORT table parser

- Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.
+ Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
- - IO Remapping Table, Platform Design Document, Revision D, March 2018
+ - IO Remapping Table, Platform Design Document, Revision D, March 2018
+
+ @par Glossary:
+ - Ref - Reference
**/

#include <IndustryStandard/IoRemappingTable.h>
@@ -144,15 +147,15 @@ STATIC CONST ACPI_PARSER IortNodeSmmuV1V2Parser[] = {
{L"Span", 8, 24, L"0x%lx", NULL, NULL, NULL, NULL},
{L"Model", 4, 32, L"%d", NULL, NULL, NULL, NULL},
{L"Flags", 4, 36, L"0x%x", NULL, NULL, NULL, NULL},
- {L"Reference to Global Interrupt Array", 4, 40, L"0x%x", NULL, NULL, NULL,
+ {L"Global Interrupt Array Ref", 4, 40, L"0x%x", NULL, NULL, NULL,
NULL},
{L"Number of context interrupts", 4, 44, L"%d", NULL,
(VOID**)&InterruptContextCount, NULL, NULL},
- {L"Reference to Context Interrupt Array", 4, 48, L"0x%x", NULL,
+ {L"Context Interrupt Array Ref", 4, 48, L"0x%x", NULL,
(VOID**)&InterruptContextOffset, NULL, NULL},
{L"Number of PMU Interrupts", 4, 52, L"%d", NULL,
(VOID**)&PmuInterruptCount, NULL, NULL},
- {L"Reference to PMU Interrupt Array", 4, 56, L"0x%x", NULL,
+ {L"PMU Interrupt Array Ref", 4, 56, L"0x%x", NULL,
(VOID**)&PmuInterruptOffset, NULL, NULL},

// Interrupt Array
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 0/8] IORT Rev E.b specification updates

Sami Mujawar
 

Bugzilla: 3458 - Add support IORT Rev E.b specification updates
(https://bugzilla.tianocore.org/show_bug.cgi?id=3458)

The IO Remapping Table (IORT) specification has been updated to
rev E.b. The following updates are introduced including the errata
to rev E and E.a:
- increments the IORT table revision to 3.
- updates the node definition to add an 'Identifier' field.
- adds definition of node type 6 - Reserved Memory Range node.
- adds definition for Memory Range Descriptors.
- adds flag to indicate PRI support for root complexes.
- adds flag to indicate if the root complex supports forwarding
of PASID information on translated transactions to the SMMU.

The v1 patch series:
- Updates the IORT header file to match the Rev E.b specification.
- Add support to parse IORT Rev E.b tables
- Add support to generate IORT Rev E.b compliant ACPI tables
using Dynamic Tables Framework.

This v2 patch series includes all changes from v1 patch series
except the following 2 patches have been modified to set the
EFI_ACPI_IO_REMAPPING_TABLE_REVISION macro to Rev 0 as setting
to Rev 3 will break existing platforms, the problem being that
the Identifier field in the IORT nodes would not be unique.
- MdePkg: IORT header update for IORT Rev E.b spec
- DynamicTablesPkg: IORT generator updates for Rev E.b spec

The changes can be seen at:
https://github.com/samimujawar/edk2/tree/1527_iort_rev_eb_v2

Sami Mujawar (8):
MdePkg: Fix IORT header file include guard
MdePkg: IORT header update for IORT Rev E.b spec
ShellPkg: Acpiview: Abbreviate field names to preserve alignment
ShellPkg: Acpiview: IORT parser update for IORT Rev E.b spec
DynamicTablesPkg: IORT set reference to Id array only if present
DynamicTablesPkg: IORT set reference to interrupt array if present
DynamicTablesPkg: Update ArmNameSpaceObjects for IORT Rev E.b
DynamicTablesPkg: IORT generator updates for Rev E.b spec

DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 58 ++
DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.c | 772 ++++++++++++++++++--
DynamicTablesPkg/Library/Acpi/Arm/AcpiIortLibArm/IortGenerator.h | 5 +-
MdePkg/Include/IndustryStandard/IoRemappingTable.h | 71 +-
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c | 207 +++++-
5 files changed, 1013 insertions(+), 100 deletions(-)

--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 3/3] OvmfPkg/X86QemuLoadImageLib: State fw_cfg dependency in file header

Dov Murik
 

Make it clear that X86QemuLoadImageLib relies on fw_cfg; prepare the
ground to add a warning about the incompatibility with boot verification
process.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>
Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
---
OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf | 3 +++
OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c | 3 +++
2 files changed, 6 insertions(+)

diff --git a/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf b/=
OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf
index e1615badd2ba..c7ec041cb706 100644
--- a/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf
+++ b/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf
@@ -2,6 +2,9 @@
# X86 specific implementation of QemuLoadImageLib library class interface=
=0D
# with support for loading mixed mode images and non-EFI stub images=0D
#=0D
+# Note that this implementation reads the cmdline (and possibly kernel, s=
etup=0D
+# data, and initrd in the legacy boot mode) from fw_cfg directly.=0D
+#=0D
# Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
diff --git a/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c b/Ov=
mfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c
index 1177582ab051..dc9018f4333b 100644
--- a/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c
+++ b/OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c
@@ -2,6 +2,9 @@
X86 specific implementation of QemuLoadImageLib library class interface=
=0D
with support for loading mixed mode images and non-EFI stub images=0D
=0D
+ Note that this implementation reads the cmdline (and possibly kernel, se=
tup=0D
+ data, and initrd in the legacy boot mode) from fw_cfg directly.=0D
+=0D
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>=0D
=0D
--=20
2.25.1


[PATCH v2 2/3] OvmfPkg/GenericQemuLoadImageLib: Read cmdline from QemuKernelLoaderFs

Dov Murik
 

Remove the QemuFwCfgLib interface used to read the QEMU cmdline
(-append argument) and the initrd size. Instead, use the synthetic
filesystem QemuKernelLoaderFs which has three files: "kernel", "initrd",
and "cmdline".

Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
---
OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf | 2 =
+-
OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c | 145 =
++++++++++++++++++--
2 files changed, 133 insertions(+), 14 deletions(-)

diff --git a/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLi=
b.inf b/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
index b262cb926a4d..f462fd6922cf 100644
--- a/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
+++ b/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
@@ -27,12 +27,12 @@ [LibraryClasses]
DebugLib=0D
MemoryAllocationLib=0D
PrintLib=0D
- QemuFwCfgLib=0D
UefiBootServicesTableLib=0D
=0D
[Protocols]=0D
gEfiDevicePathProtocolGuid=0D
gEfiLoadedImageProtocolGuid=0D
+ gEfiSimpleFileSystemProtocolGuid=0D
=0D
[Guids]=0D
gQemuKernelLoaderFsMediaGuid=0D
diff --git a/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLi=
b.c b/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c
index 114db7e8441f..f520456e3b24 100644
--- a/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c
+++ b/OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c
@@ -11,9 +11,9 @@
#include <Base.h>=0D
#include <Guid/QemuKernelLoaderFsMedia.h>=0D
#include <Library/DebugLib.h>=0D
+#include <Library/FileHandleLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
#include <Library/PrintLib.h>=0D
-#include <Library/QemuFwCfgLib.h>=0D
#include <Library/QemuLoadImageLib.h>=0D
#include <Library/UefiBootServicesTableLib.h>=0D
#include <Protocol/DevicePath.h>=0D
@@ -30,6 +30,11 @@ typedef struct {
KERNEL_FILE_DEVPATH FileNode;=0D
EFI_DEVICE_PATH_PROTOCOL EndNode;=0D
} KERNEL_VENMEDIA_FILE_DEVPATH;=0D
+=0D
+typedef struct {=0D
+ VENDOR_DEVICE_PATH VenMediaNode;=0D
+ EFI_DEVICE_PATH_PROTOCOL EndNode;=0D
+} SINGLE_VENMEDIA_NODE_DEVPATH;=0D
#pragma pack ()=0D
=0D
STATIC CONST KERNEL_VENMEDIA_FILE_DEVPATH mKernelDevicePath =3D {=0D
@@ -51,6 +56,78 @@ STATIC CONST KERNEL_VENMEDIA_FILE_DEVPATH mKernelDeviceP=
ath =3D {
}=0D
};=0D
=0D
+STATIC CONST SINGLE_VENMEDIA_NODE_DEVPATH mQemuKernelLoaderFileSystemDevic=
ePath =3D {=0D
+ {=0D
+ {=0D
+ MEDIA_DEVICE_PATH, MEDIA_VENDOR_DP,=0D
+ { sizeof (VENDOR_DEVICE_PATH) }=0D
+ },=0D
+ QEMU_KERNEL_LOADER_FS_MEDIA_GUID=0D
+ }, {=0D
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,=0D
+ { sizeof (EFI_DEVICE_PATH_PROTOCOL) }=0D
+ }=0D
+};=0D
+=0D
+STATIC=0D
+EFI_STATUS=0D
+GetQemuKernelLoaderBlobSize (=0D
+ IN EFI_FILE_HANDLE Root,=0D
+ IN CHAR16 *FileName,=0D
+ OUT UINTN *Size=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_FILE_HANDLE FileHandle;=0D
+ UINT64 FileSize;=0D
+=0D
+ Status =3D Root->Open (Root, &FileHandle, FileName, EFI_FILE_MODE_READ, =
0);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ Status =3D FileHandleGetSize (FileHandle, &FileSize);=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseFile;=0D
+ }=0D
+ *Size =3D FileSize;=0D
+ Status =3D EFI_SUCCESS;=0D
+CloseFile:=0D
+ FileHandle->Close (FileHandle);=0D
+ return Status;=0D
+}=0D
+=0D
+STATIC=0D
+EFI_STATUS=0D
+ReadWholeQemuKernelLoaderBlob (=0D
+ IN EFI_FILE_HANDLE Root,=0D
+ IN CHAR16 *FileName,=0D
+ IN UINTN Size,=0D
+ OUT VOID *Buffer=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_FILE_HANDLE FileHandle;=0D
+ UINTN ReadSize;=0D
+=0D
+ Status =3D Root->Open (Root, &FileHandle, FileName, EFI_FILE_MODE_READ, =
0);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ ReadSize =3D Size;=0D
+ Status =3D FileHandle->Read (FileHandle, &ReadSize, Buffer);=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseFile;=0D
+ }=0D
+ if (ReadSize !=3D Size) {=0D
+ Status =3D EFI_PROTOCOL_ERROR;=0D
+ goto CloseFile;=0D
+ }=0D
+ Status =3D EFI_SUCCESS;=0D
+CloseFile:=0D
+ FileHandle->Close (FileHandle);=0D
+ return Status;=0D
+}=0D
+=0D
/**=0D
Download the kernel, the initial ramdisk, and the kernel command line fr=
om=0D
QEMU's fw_cfg. The kernel will be instructed via its command line to loa=
d=0D
@@ -76,12 +153,16 @@ QemuLoadKernelImage (
OUT EFI_HANDLE *ImageHandle=0D
)=0D
{=0D
- EFI_STATUS Status;=0D
- EFI_HANDLE KernelImageHandle;=0D
- EFI_LOADED_IMAGE_PROTOCOL *KernelLoadedImage;=0D
- UINTN CommandLineSize;=0D
- CHAR8 *CommandLine;=0D
- UINTN InitrdSize;=0D
+ EFI_STATUS Status;=0D
+ EFI_HANDLE KernelImageHandle;=0D
+ EFI_LOADED_IMAGE_PROTOCOL *KernelLoadedImage;=0D
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathNode;=0D
+ EFI_HANDLE FsVolumeHandle;=0D
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FsProtocol;=0D
+ EFI_FILE_HANDLE Root;=0D
+ UINTN CommandLineSize;=0D
+ CHAR8 *CommandLine;=0D
+ UINTN InitrdSize;=0D
=0D
//=0D
// Load the image. This should call back into the QEMU EFI loader file s=
ystem.=0D
@@ -124,8 +205,38 @@ QemuLoadKernelImage (
);=0D
ASSERT_EFI_ERROR (Status);=0D
=0D
- QemuFwCfgSelectItem (QemuFwCfgItemCommandLineSize);=0D
- CommandLineSize =3D (UINTN)QemuFwCfgRead32 ();=0D
+ //=0D
+ // Open the Qemu Kernel Loader abstract filesystem (volume) which will b=
e=0D
+ // used to read the "initrd" and "cmdline" synthetic files.=0D
+ //=0D
+ DevicePathNode =3D (EFI_DEVICE_PATH_PROTOCOL *)&mQemuKernelLoaderFileSys=
temDevicePath;=0D
+ Status =3D gBS->LocateDevicePath (=0D
+ &gEfiSimpleFileSystemProtocolGuid,=0D
+ &DevicePathNode,=0D
+ &FsVolumeHandle=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D gBS->HandleProtocol (=0D
+ FsVolumeHandle,=0D
+ &gEfiSimpleFileSystemProtocolGuid,=0D
+ (VOID **)&FsProtocol=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D FsProtocol->OpenVolume (FsVolumeHandle, &Root);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D GetQemuKernelLoaderBlobSize (Root, L"cmdline", &CommandLineSi=
ze);=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseRoot;=0D
+ }=0D
=0D
if (CommandLineSize =3D=3D 0) {=0D
KernelLoadedImage->LoadOptionsSize =3D 0;=0D
@@ -136,8 +247,11 @@ QemuLoadKernelImage (
goto UnloadImage;=0D
}=0D
=0D
- QemuFwCfgSelectItem (QemuFwCfgItemCommandLineData);=0D
- QemuFwCfgReadBytes (CommandLineSize, CommandLine);=0D
+ Status =3D ReadWholeQemuKernelLoaderBlob (Root, L"cmdline", CommandLin=
eSize,=0D
+ CommandLine);=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto FreeCommandLine;=0D
+ }=0D
=0D
//=0D
// Verify NUL-termination of the command line.=0D
@@ -155,8 +269,10 @@ QemuLoadKernelImage (
KernelLoadedImage->LoadOptionsSize =3D (UINT32)((CommandLineSize - 1) =
* 2);=0D
}=0D
=0D
- QemuFwCfgSelectItem (QemuFwCfgItemInitrdSize);=0D
- InitrdSize =3D (UINTN)QemuFwCfgRead32 ();=0D
+ Status =3D GetQemuKernelLoaderBlobSize (Root, L"initrd", &InitrdSize);=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto FreeCommandLine;=0D
+ }=0D
=0D
if (InitrdSize > 0) {=0D
//=0D
@@ -193,6 +309,7 @@ QemuLoadKernelImage (
}=0D
=0D
*ImageHandle =3D KernelImageHandle;=0D
+ Root->Close (Root);=0D
return EFI_SUCCESS;=0D
=0D
FreeCommandLine:=0D
@@ -201,6 +318,8 @@ FreeCommandLine:
}=0D
UnloadImage:=0D
gBS->UnloadImage (KernelImageHandle);=0D
+CloseRoot:=0D
+ Root->Close (Root);=0D
=0D
return Status;=0D
}=0D
--=20
2.25.1


[PATCH v2 1/3] Revert "OvmfPkg/QemuKernelLoaderFsDxe: don't expose kernel command line"

Dov Murik
 

This reverts commit efc52d67e1573ce174d301b52fa1577d552c8441.

Manually fixed conflicts in:
OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c

Note that besides re-exposing the kernel command line as a file in the
synthetic filesystem, we also revert back to AllocatePool instead of
AllocatePages.

Signed-off-by: Dov Murik <dovmurik@linux.ibm.com>
---
OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c b/OvmfPk=
g/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c
index b09ff6a3590d..c7ddd86f5c75 100644
--- a/OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c
+++ b/OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c
@@ -33,6 +33,7 @@
typedef enum {=0D
KernelBlobTypeKernel,=0D
KernelBlobTypeInitrd,=0D
+ KernelBlobTypeCommandLine,=0D
KernelBlobTypeMax=0D
} KERNEL_BLOB_TYPE;=0D
=0D
@@ -59,6 +60,11 @@ STATIC KERNEL_BLOB mKernelBlob[KernelBlobTypeMax] =3D {
{=0D
{ QemuFwCfgItemInitrdSize, QemuFwCfgItemInitrdData, },=0D
}=0D
+ }, {=0D
+ L"cmdline",=0D
+ {=0D
+ { QemuFwCfgItemCommandLineSize, QemuFwCfgItemCommandLineData, },=0D
+ }=0D
}=0D
};=0D
=0D
@@ -948,7 +954,7 @@ FetchBlob (
//=0D
// Read blob.=0D
//=0D
- Blob->Data =3D AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Blob->Size));=0D
+ Blob->Data =3D AllocatePool (Blob->Size);=0D
if (Blob->Data =3D=3D NULL) {=0D
DEBUG ((DEBUG_ERROR, "%a: failed to allocate %Ld bytes for \"%s\"\n",=
=0D
__FUNCTION__, (INT64)Blob->Size, Blob->Name));=0D
@@ -1083,8 +1089,7 @@ FreeBlobs:
while (BlobType > 0) {=0D
CurrentBlob =3D &mKernelBlob[--BlobType];=0D
if (CurrentBlob->Data !=3D NULL) {=0D
- FreePages (CurrentBlob->Data,=0D
- EFI_SIZE_TO_PAGES ((UINTN)CurrentBlob->Size));=0D
+ FreePool (CurrentBlob->Data);=0D
CurrentBlob->Size =3D 0;=0D
CurrentBlob->Data =3D NULL;=0D
}=0D
--=20
2.25.1


[PATCH v2 0/3] OvmfPkg: Use QemuKernelLoaderFs to read cmdline/initrd

Dov Murik
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3457

In order to support measured SEV boot with kernel/initrd/cmdline, we'd
like to have one place that reads those blobs; in the future we'll add
the measurement and verification in that place.

We already have a synthetic filesystem (QemuKernelLoaderFs) which holds
three files: "kernel", "initrd", and "cmdline". The kernel is indeed
read from this filesystem in LoadImage; but the cmdline (and the length
of initrd) are read from QemuFwCfgLib items.

This patch series modifies GenericQemuLoadImageLib to read cmdline (and
the initrd size) from the QemuKernelLoaderFs synthetic filesystem, thus
removing the dependency on QemuFwCfgLib.

Note that X86QemuLoadImageLib is not modified, because it contains a
QemuLoadLegacyImage() which reads other items of the QemuFwCfg which are
not available in QemuKernelLoaderFs. Since we don't want to support the
legacy boot path in the future measured SEV boot, we leave
X86QemuLoadImageLib as-is (except for a comment addition in patch 3) and
will force use for GenericQemuLoadImageLib in the measured SEV boot
implementation.

Relevant discussion threads start in:
https://edk2.groups.io/g/devel/message/76069

To test this on x86_64, I forced the use of GenericQemuLoadImageLib
using the following local patch:


diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 0a237a905866..46442b543bcf 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -404,7 +404,7 @@ [LibraryClasses.common.DXE_DRIVER]
PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf
- QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf
+ QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf # XXX don't commit this or someone will be mad
!if $(TPM_ENABLE) == TRUE
Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibTcg/Tpm12DeviceLibTcg.inf
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.inf


I tested boot with QEMU and OVMF with the following QEMU arguments:

-kernel a
-kernel a -initrd b
-kernel a -cmdline c
-kernel a -initrd b -cmdline c

(and also without -kernel)


Code is at
https://github.com/confidential-containers-demo/edk2/tree/use-synthetic-fs-for-cmdline-v2

v2 changes:

- Add comment to header of X86QemuLoadImageLib.inf
- Clearer function names in GenericQemuLoadImageLib.c
- Fix coding style issues

v1: https://edk2.groups.io/g/devel/message/76265


Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Tobin Feldman-Fitzthum <tobin@linux.ibm.com>

Dov Murik (3):
Revert "OvmfPkg/QemuKernelLoaderFsDxe: don't expose kernel command
line"
OvmfPkg/GenericQemuLoadImageLib: Read cmdline from QemuKernelLoaderFs
OvmfPkg/X86QemuLoadImageLib: State fw_cfg dependency in file header

OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf | 2 +-
OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf | 3 +
OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c | 145 ++++++++++++++++++--
OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.c | 3 +
OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c | 11 +-
5 files changed, 147 insertions(+), 17 deletions(-)

--
2.25.1


Recommended VSCode Extensions and Settings

Nate DeSimone
 

Hi Everyone,

 

I have compiled a list of recommended extensions and settings for using Visual Studio Code to develop EDK II code. I have posted them on the wiki: https://github.com/tianocore/tianocore.github.io/wiki/Nate's-Recommended-VSCode-Extensions-and-Settings

 

Feel free to add to the list if there is something you believe to be missing.

 

Nate


[PATCH v3] BaseTools GenFw: Add support for RISCV GOT/PLT relocations

Sunil V L <sunilvl@...>
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682=
710

Changes in v3:
- Added the comments to address Liming's feedback.

Changes in v2:
- Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: Daniel Schaefer <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 58 ++++++++++++++++++++++---
1 file changed, 52 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G=
enFw/Elf64Convert.c
index d097db8632..310ad38f90 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D
STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D
STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D
+STATIC INT32 mRiscVPass1Offset;=0D
+STATIC INT32 mRiscVPass1GotFixup;=0D
=0D
//=0D
// Initialization Function=0D
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
break;=0D
=0D
case R_RISCV_32:=0D
- *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a=
ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D
+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D
break;=0D
=0D
case R_RISCV_64:=0D
- *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections=
Offset[Sym->st_shndx];=0D
+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D
break;=0D
=0D
case R_RISCV_HI20:=0D
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
mRiscVPass1SymSecIndex =3D 0;=0D
break;=0D
=0D
+ case R_RISCV_GOT_HI20:=0D
+ Value =3D (Sym->st_value - Rel->r_offset);=0D
+ mRiscVPass1Offset =3D RV_X(Value, 0, 12);=0D
+ Value =3D RV_X(Value, 12, 20);=0D
+ *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));=0D
+=0D
+ mRiscVPass1Targ =3D Targ;=0D
+ mRiscVPass1Sym =3D SymShdr;=0D
+ mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D
+ mRiscVPass1GotFixup =3D 1;=0D
+ break;=0D
+=0D
case R_RISCV_PCREL_HI20:=0D
mRiscVPass1Targ =3D Targ;=0D
mRiscVPass1Sym =3D SymShdr;=0D
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas=
s1SymSecIndex !=3D 0) {=0D
int i;=0D
Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D
- Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D
- if(Value & (RISCV_IMM_REACH/2)) {=0D
- Value |=3D ~(RISCV_IMM_REACH-1);=0D
+=0D
+ if(mRiscVPass1GotFixup) {=0D
+ Value =3D (UINT32)(mRiscVPass1Offset);=0D
+ } else {=0D
+ Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D
+ if(Value & (RISCV_IMM_REACH/2)) {=0D
+ Value |=3D ~(RISCV_IMM_REACH-1);=0D
+ }=0D
}=0D
Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff=
set[mRiscVPass1SymSecIndex];=0D
+=0D
if(-2048 > (INT32)Value) {=0D
i =3D (((INT32)Value * -1) / 4096);=0D
Value2 -=3D i;=0D
@@ -569,12 +589,35 @@ WriteSectionRiscV64 (
}=0D
}=0D
=0D
- *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar=
g, 0, 20));=0D
+ if(mRiscVPass1GotFixup) {=0D
+ *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)=0D
+ | (RV_X(*(UINT32*)Targ, 0, 20));=0D
+ // Convert LD instruction to ADDI=0D
+ //=0D
+ // |31 20|19 15|14 12|11 7|6 0|=0D
+ // |-----------------------------------------|=0D
+ // |imm[11:0] | rs1 | 011 | rd | 0000011 | LD=0D
+ // -----------------------------------------=0D
+=0D
+ // |-----------------------------------------|=0D
+ // |imm[11:0] | rs1 | 000 | rd | 0010011 | ADDI=0D
+ // -----------------------------------------=0D
+=0D
+ // To convert, let's first reset bits 12-14 and 0-6 using ~0x707f=
=0D
+ // Then modify the opcode to ADDI (0010011)=0D
+ // All other fields will remain same.=0D
+=0D
+ *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);=0D
+ } else {=0D
+ *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T=
arg, 0, 20));=0D
+ }=0D
*(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U=
INT32 *)mRiscVPass1Targ, 0, 12));=0D
}=0D
mRiscVPass1Sym =3D NULL;=0D
mRiscVPass1Targ =3D NULL;=0D
mRiscVPass1SymSecIndex =3D 0;=0D
+ mRiscVPass1Offset =3D 0;=0D
+ mRiscVPass1GotFixup =3D 0;=0D
break;=0D
=0D
case R_RISCV_ADD64:=0D
@@ -586,6 +629,7 @@ WriteSectionRiscV64 (
case R_RISCV_GPREL_I:=0D
case R_RISCV_GPREL_S:=0D
case R_RISCV_CALL:=0D
+ case R_RISCV_CALL_PLT:=0D
case R_RISCV_RVC_BRANCH:=0D
case R_RISCV_RVC_JUMP:=0D
case R_RISCV_RELAX:=0D
@@ -1528,6 +1572,7 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:=0D
case R_RISCV_GPREL_S:=0D
case R_RISCV_CALL:=0D
+ case R_RISCV_CALL_PLT:=0D
case R_RISCV_RVC_BRANCH:=0D
case R_RISCV_RVC_JUMP:=0D
case R_RISCV_RELAX:=0D
@@ -1537,6 +1582,7 @@ WriteRelocations64 (
case R_RISCV_SET16:=0D
case R_RISCV_SET32:=0D
case R_RISCV_PCREL_HI20:=0D
+ case R_RISCV_GOT_HI20:=0D
case R_RISCV_PCREL_LO12_I:=0D
break;=0D
=0D
--=20
2.25.1


Re: 回复: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations

Sunil V L <sunilvl@...>
 

Hi Liming,
Thank you very much for the review.

On Thu, Jun 17, 2021 at 09:43:21AM +0800, gaoliming wrote:
Sunil:
I add my comments below.

Thanks
Liming
-----邮件原件-----
发件人: Sunil V L <sunilvl@ventanamicro.com>
发送时间: 2021年6月11日 22:05
收件人: devel@edk2.groups.io
抄送: Sunil V L <sunilvl@ventanamicro.com>; Abner Chang
<abner.chang@hpe.com>; Daniel Schaefer <daniel.schaefer@hpe.com>; Bob
Feng <bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
Yuwei Chen <yuwei.chen@intel.com>; Heinrich Schuchardt
<xypron.glpk@gmx.de>
主题: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT
relocations

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-8466
82710

Changes in v2:
- Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>
Tested-By format is invalid. Its format is same Reviewed-by.
Sure. Will fix it.


Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 44
+++++++++++++++++++++----
1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
STATIC UINT8 *mRiscVPass1Targ = NULL;

STATIC Elf_Shdr *mRiscVPass1Sym = NULL;

STATIC Elf64_Half mRiscVPass1SymSecIndex = 0;

+STATIC INT32 mRiscVPass1Offset;

+STATIC INT32 mRiscVPass1GotFixup;



//

// Initialization Function

@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
break;



case R_RISCV_32:

- *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) -
SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);

+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;

break;



case R_RISCV_64:

- *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr +
mCoffSectionsOffset[Sym->st_shndx];

+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;

break;



case R_RISCV_HI20:

@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
mRiscVPass1SymSecIndex = 0;

break;



+ case R_RISCV_GOT_HI20:

+ Value = (Sym->st_value - Rel->r_offset);

+ mRiscVPass1Offset = RV_X(Value, 0, 12);

+ Value = RV_X(Value, 12, 20);

+ *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));

+

+ mRiscVPass1Targ = Targ;

+ mRiscVPass1Sym = SymShdr;

+ mRiscVPass1SymSecIndex = Sym->st_shndx;

+ mRiscVPass1GotFixup = 1;

+ break;

+

case R_RISCV_PCREL_HI20:

mRiscVPass1Targ = Targ;

mRiscVPass1Sym = SymShdr;

@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL &&
mRiscVPass1SymSecIndex != 0) {

int i;

Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));

- Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));

- if(Value & (RISCV_IMM_REACH/2)) {

- Value |= ~(RISCV_IMM_REACH-1);

+

+ if(mRiscVPass1GotFixup) {

+ Value = (UINT32)(mRiscVPass1Offset);

+ } else {

+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));

+ if(Value & (RISCV_IMM_REACH/2)) {

+ Value |= ~(RISCV_IMM_REACH-1);

+ }

}

Value = Value - (UINT32)mRiscVPass1Sym->sh_addr +
mCoffSectionsOffset[mRiscVPass1SymSecIndex];

+

if(-2048 > (INT32)Value) {

i = (((INT32)Value * -1) / 4096);

Value2 -= i;

@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
}

}



- *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
(RV_X(*(UINT32*)Targ,
0, 20));

+ if(mRiscVPass1GotFixup) {

+ *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)

+ | (RV_X(*(UINT32*)Targ, 0, 20));

+ /* Convert LD instruction to ADDI */

+ *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
Can you add the comments for the hard value 0x707f and 0x13?
Sure. Will add.

Thanks
Sunil

Thanks
Liming

+ } else {

+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
(RV_X(*(UINT32*)Targ, 0, 20));

+ }

*(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) |
(RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));

}

mRiscVPass1Sym = NULL;

mRiscVPass1Targ = NULL;

mRiscVPass1SymSecIndex = 0;

+ mRiscVPass1Offset = 0;

+ mRiscVPass1GotFixup = 0;

break;



case R_RISCV_ADD64:

@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
case R_RISCV_GPREL_I:

case R_RISCV_GPREL_S:

case R_RISCV_CALL:

+ case R_RISCV_CALL_PLT:

case R_RISCV_RVC_BRANCH:

case R_RISCV_RVC_JUMP:

case R_RISCV_RELAX:

@@ -1528,6 +1558,7 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:

case R_RISCV_GPREL_S:

case R_RISCV_CALL:

+ case R_RISCV_CALL_PLT:

case R_RISCV_RVC_BRANCH:

case R_RISCV_RVC_JUMP:

case R_RISCV_RELAX:

@@ -1537,6 +1568,7 @@ WriteRelocations64 (
case R_RISCV_SET16:

case R_RISCV_SET32:

case R_RISCV_PCREL_HI20:

+ case R_RISCV_GOT_HI20:

case R_RISCV_PCREL_LO12_I:

break;



--
2.25.1







Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations

Sunil V L <sunilvl@...>
 

Hi Pete,
Thank you very much!.
On Wed, Jun 16, 2021 at 01:35:27PM +0100, Pete Batard wrote:
Sunil, Daniel, thanks for the patch.

I confirm that this addresses the 0x13 and 0x14 relocation issues that I was
seeing.

However, this patch appears to introduces new R_RISCV_PCREL_LO12_S
relocation errors that I was not seeing previously, so I still can't manage
to get a successful compilation.
It is not introduced by the patch but looks like one more new relocation
type is added by the latest tool chain you are using. Please raise a new
bug and I will add the support for it in next patch.

Thanks!
Sunil

Especially the stream of 0x13 and 0x14 relocation errors I was getting at
https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true
has now switched to (tested on up to date Ubuntu with latest EDK2):

-------------------------------------------------------------------------
"GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi]
Error 2
-------------------------------------------------------------------------

So, in effect, some of the earlier relocation errors appear to have morphed
into 0x19/R_RISCV_PCREL_LO12_S ones...

I can open a new bug for this issue if you prefer.

Regards,

/Pete

On 2021.06.15 03:26, Daniel Schaefer wrote:
Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other
concern.
This patch lets us build the RISC-V platforms using modern toolchains
that are provided directly by the distributions, rather than building
your own from source.

Thanks,
Daniel
------------------------------------------------------------------------
*From:* Sunil V L <sunilvl@ventanamicro.com>
*Sent:* Friday, June 11, 2021 22:08
*To:* devel@edk2.groups.io <devel@edk2.groups.io>
*Cc:* Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng
<bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei
Chen <yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>
*Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV
GOT/PLT relocations
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
<https://bugzilla.tianocore.org/show_bug.cgi?id=3096>

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
<https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710>

Changes in v2:
   - Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
  1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
  STATIC UINT8       *mRiscVPass1Targ = NULL;
  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
+STATIC INT32       mRiscVPass1Offset;
+STATIC INT32       mRiscVPass1GotFixup;
  //
  // Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
      break;
    case R_RISCV_32:
-    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_64:
-    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
      mRiscVPass1SymSecIndex = 0;
      break;
+  case R_RISCV_GOT_HI20:
+    Value = (Sym->st_value - Rel->r_offset);
+    mRiscVPass1Offset = RV_X(Value, 0, 12);
+    Value = RV_X(Value, 12, 20);
+    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+    mRiscVPass1Targ = Targ;
+    mRiscVPass1Sym = SymShdr;
+    mRiscVPass1SymSecIndex = Sym->st_shndx;
+    mRiscVPass1GotFixup = 1;
+    break;
+
    case R_RISCV_PCREL_HI20:
      mRiscVPass1Targ = Targ;
      mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
        int i;
        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
-      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
-      if(Value & (RISCV_IMM_REACH/2)) {
-        Value |= ~(RISCV_IMM_REACH-1);
+
+      if(mRiscVPass1GotFixup) {
+        Value = (UINT32)(mRiscVPass1Offset);
+      } else {
+        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+        if(Value & (RISCV_IMM_REACH/2)) {
+          Value |= ~(RISCV_IMM_REACH-1);
+        }
        }
        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
        if(-2048 > (INT32)Value) {
          i = (((INT32)Value * -1) / 4096);
          Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
          }
        }
-      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      if(mRiscVPass1GotFixup) {
+        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+                            | (RV_X(*(UINT32*)Targ, 0, 20));
+        /* Convert LD instruction to ADDI */
+        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+      } else {
+        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      }
        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
      }
      mRiscVPass1Sym = NULL;
      mRiscVPass1Targ = NULL;
      mRiscVPass1SymSecIndex = 0;
+    mRiscVPass1Offset = 0;
+    mRiscVPass1GotFixup = 0;
      break;
    case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
    case R_RISCV_GPREL_I:
    case R_RISCV_GPREL_S:
    case R_RISCV_CALL:
+  case R_RISCV_CALL_PLT:
    case R_RISCV_RVC_BRANCH:
    case R_RISCV_RVC_JUMP:
    case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
              case R_RISCV_GPREL_I:
              case R_RISCV_GPREL_S:
              case R_RISCV_CALL:
+            case R_RISCV_CALL_PLT:
              case R_RISCV_RVC_BRANCH:
              case R_RISCV_RVC_JUMP:
              case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
              case R_RISCV_SET16:
              case R_RISCV_SET32:
              case R_RISCV_PCREL_HI20:
+            case R_RISCV_GOT_HI20:
              case R_RISCV_PCREL_LO12_I:
                break;
--
2.25.1


OvmfPkgIa32X64.dsc is broken: OvmfPkg/Sec/SecMain.inf NOT found in DSC file; Is it really a binary module?

Rebecca Cran
 

Is OvmfPkg/OvmfPkgIa32X64.dsc still supposed to work after the recent changes in OvmfPkg? I realized it's currently broken.


bcran@photon:~/src/uefi/edk2> build -p OvmfPkg/OvmfPkgIa32X64.dsc -a X64 -t GCC5 -b RELEASE
Build environment: Linux-5.12.9-1-default-x86_64-with-glibc2.2.5
Build start time: 22:11:28, Jun.16 2021

WORKSPACE        = /home/bcran/src/uefi/edk2
EDK_TOOLS_PATH   = /home/bcran/src/uefi/edk2/BaseTools
CONF_PATH        = /home/bcran/src/uefi/edk2/Conf
PYTHON_COMMAND   = /usr/bin/python3.8


Processing meta-data
.Architecture(s)  = X64
Build target     = RELEASE
Toolchain        = GCC5

Active Platform          = /home/bcran/src/uefi/edk2/OvmfPkg/OvmfPkgIa32X64.dsc


build.py...
 : error F001: Module /home/bcran/src/uefi/edk2/OvmfPkg/Sec/SecMain.inf NOT found in DSC file; Is it really a binary module?



- Failed -
Build end time: 22:11:29, Jun.16 2021
Build total time: 00:00:01


--
Rebecca Cran


Re: [PATCH] MdePkg/Include: Smbios Specification 3.4.0 changes

Thotala, Gopi
 

These changes were requested in smbios spec version 3.4.0.

 

From smbios specs 3.4.0 table 51 – BIT 5&6.  This field is moved from specific MemoryArrayLocationCXLFlexbus10AddonCard to generic MemoryArrayLocationCXLAddonCard to address both CXL1.0 and 2.0 CXL revisions.(including backward compatible, not specific to CXL1.0)

 

From smbios specs 3.4.0 table 79.  The memory technology name changed from MemoryTechnologyIntelPersistentMemory to MemoryTechnologyIntelOptanePersistentMemory.

 

Attached smbios specs here for reference.

 

 

From: gaoliming <gaoliming@...>
Sent: Wednesday, June 16, 2021 7:10 PM
To: devel@edk2.groups.io; Thotala, Gopi <gopi.thotala@...>; 'Rebecca Cran' <rebecca@...>
Subject: 回复: [edk2-devel] [PATCH] MdePkg/Include: Smbios Specification 3.4.0 changes

 

Gopi:

 Could you let me know why changes below field name?

 

MemoryArrayLocationCXLFlexbus10AddonCard è MemoryArrayLocationCXLAddonCard

MemoryTechnologyIntelPersistentMemory è MemoryTechnologyIntelOptanePersistentMemory

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Thotala, Gopi
发送时间: 2021614 23:40
收件人: Rebecca Cran <rebecca@...>; devel@edk2.groups.io
主题: Re: [edk2-devel] [PATCH] MdePkg/Include: Smbios Specification 3.4.0 changes

 

Attached V2 patch after typo correction.

 

Thanks

Gopi

 

From: Rebecca Cran <rebecca@...>
Sent: Sunday, June 13, 2021 9:34 AM
To: devel@edk2.groups.io; Thotala, Gopi <gopi.thotala@...>
Subject: Re: [edk2-devel] [PATCH] MdePkg/Include: Smbios Specification 3.4.0 changes

 

There’s a typo of ‘persistent’ in: 

 

// Optane DC Presistent Memory in SMBIOS spec 3.4.0

 

Rebecca Cran

 

 

On Jun 2, 2021, at 10:46 AM, Thotala, Gopi <gopi.thotala@...> wrote:



Initial patch submitted for review.

<MdePkg-Include-Smbios-Specification-3.4.0-changes.patch>

 

 


Re: [PATCH] BaseTools: Remove check for Split.exe in toolset.bat

Bob Feng
 

Reviewed-by: Bob Feng <bob.c.feng@intel.com>

-----Original Message-----
From: gaoliming <gaoliming@byosoft.com.cn>
Sent: Thursday, June 17, 2021 9:36 AM
To: devel@edk2.groups.io; rebecca@bsdio.com; Feng, Bob C <bob.c.feng@intel.com>; Chen, Christine <yuwei.chen@intel.com>
Subject: 回复: [edk2-devel] [PATCH] BaseTools: Remove check for Split.exe in toolset.bat

Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Rebecca Cran
发送时间: 2021年6月13日 11:35
收件人: Bob Feng <bob.c.feng@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Yuwei Chen <yuwei.chen@intel.com>
抄送: Rebecca Cran <rebecca@bsdio.com>; devel@edk2.groups.io
主题: [edk2-devel] [PATCH] BaseTools: Remove check for Split.exe in
toolset.bat

Split is now a Python tool, so BaseTools\Bin\Win32\Split.exe no longer
exists. Remove the check for it from toolsetup.bat to prevent the
erroneous claim that the binary C tools are missing.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
---
BaseTools/toolsetup.bat | 1 -
1 file changed, 1 deletion(-)

diff --git a/BaseTools/toolsetup.bat b/BaseTools/toolsetup.bat index
4b5256ab6e..a766a69f08 100755
--- a/BaseTools/toolsetup.bat
+++ b/BaseTools/toolsetup.bat
@@ -299,7 +299,6 @@ IF NOT EXIST "%EDK_TOOLS_BIN%\GenFfs.exe" goto
check_c_tools IF NOT EXIST "%EDK_TOOLS_BIN%\GenFv.exe" goto
check_c_tools

IF NOT EXIST "%EDK_TOOLS_BIN%\GenFw.exe" goto check_c_tools

IF NOT EXIST "%EDK_TOOLS_BIN%\GenSec.exe" goto check_c_tools

-IF NOT EXIST "%EDK_TOOLS_BIN%\Split.exe" goto check_c_tools

IF NOT EXIST "%EDK_TOOLS_BIN%\TianoCompress.exe" goto check_c_tools

IF NOT EXIST "%EDK_TOOLS_BIN%\VfrCompile.exe" goto check_c_tools

IF NOT EXIST "%EDK_TOOLS_BIN%\VolInfo.exe" goto check_c_tools

--
2.32.0




-=-=-=-=-=-=
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#76441):
https://edk2.groups.io/g/devel/message/76441
Mute This Topic: https://groups.io/mt/83503018/4905953
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub
[gaoliming@byosoft.com.cn]
-=-=-=-=-=-=


回复: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

gaoliming
 

 

Please follow https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format to update the commit message format.

 

And, for the override PciBus module, can you give more detail why need to override PciBus? Is it possible to update Edk2 MdeModulePkg PciBus to meet the platform requirement?

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 manickavasakam karpagavinayagam
发送时间: 2021617 7:05
收件人: devel@edk2.groups.io
主题: [edk2-devel] [edk2-platforms] [PATCH V1 0/2] Support for TiogaPass Platform and Override generic PciBus Driver with

 

Add BoardTiogaPass packages to support TiogaPass Platform Enabled Network, ISCSI,IPMI, SMBIOS, Performance Measurement
Remove AST2500 UEFI option ROM driver from PurleyOpenBoardPkg

AST2500 UEFI option ROM move to edk2-non-osi ASpeedGopBinPkg Update copyright headers

 

manickavasakam karpagavinayagam (2):

  PurleyOpenBoardPkg : Support for TiogaPass Platform

  PurleyOpenBoardPkg : Override generic PciBus Driver with Platform

    specific instance of PciBus driver.

 

.../IpmiFeaturePkg/GenericIpmi/Dxe/IpmiInit.c |    8 +-

.../Acpi/BoardAcpiDxe/AmlOffsetTable.c        |  453 +-

.../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c      |    3 +

.../BoardTiogaPass/CoreDxeInclude.dsc         |  168 +

.../BoardTiogaPass/CoreUefiBootInclude.fdf    |   82 +

.../BoardTiogaPass/GitEdk2MinTiogaPass.bat    |   93 +

.../BasePlatformHookLib/BasePlatformHookLib.c |  389 +

.../BasePlatformHookLib.inf                   |   36 +

.../BoardAcpiLib/DxeBoardAcpiTableLib.c       |   36 +

.../BoardAcpiLib/DxeBoardAcpiTableLib.inf     |   40 +

.../BoardAcpiLib/DxeTiogaPassAcpiTableLib.c   |   53 +

.../BoardAcpiLib/SmmBoardAcpiEnableLib.c      |   62 +

.../BoardAcpiLib/SmmBoardAcpiEnableLib.inf    |   41 +

.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c    |  120 +

.../BoardAcpiLib/SmmTiogaPassAcpiEnableLib.c  |   37 +

.../Library/BoardInitLib/AllLanesEparam.c     |   44 +

.../Library/BoardInitLib/GpioTable.c          |  296 +

.../Library/BoardInitLib/IioBifur.c           |   70 +

.../BoardInitLib/PeiBoardInitPostMemLib.c     |   46 +

.../BoardInitLib/PeiBoardInitPostMemLib.inf   |   37 +

.../BoardInitLib/PeiBoardInitPreMemLib.c      |  112 +

.../BoardInitLib/PeiBoardInitPreMemLib.inf    |   69 +

.../Library/BoardInitLib/PeiTiogaPassDetect.c |   28 +

.../BoardInitLib/PeiTiogaPassInitLib.h        |   18 +

.../BoardInitLib/PeiTiogaPassInitPostMemLib.c |   86 +

.../BoardInitLib/PeiTiogaPassInitPreMemLib.c  |  638 ++

.../Library/BoardInitLib/UsbOC.c              |   46 +

.../Library/PeiReportFvLib/PeiReportFvLib.c   |  138 +

.../Library/PeiReportFvLib/PeiReportFvLib.inf |   51 +

.../BoardTiogaPass/OpenBoardPkg.dsc           |  245 +

.../BoardTiogaPass/OpenBoardPkg.fdf           |  600 ++

.../BoardTiogaPass/PlatformPkgBuildOption.dsc |   84 +

.../BoardTiogaPass/PlatformPkgConfig.dsc      |   58 +

.../BoardTiogaPass/PlatformPkgPcd.dsc         |  392 ++

.../BoardTiogaPass/StructureConfig.dsc        | 6236 +++++++++++++++++

.../BoardTiogaPass/__init__.py                |    0

.../PurleyOpenBoardPkg/BoardTiogaPass/bld.bat |  139 +

.../BoardTiogaPass/build_board.py             |  195 +

.../BoardTiogaPass/build_config.cfg           |   34 +

.../BoardTiogaPass/logo.txt                   |   10 +

.../BoardTiogaPass/postbuild.bat              |   96 +

.../BoardTiogaPass/prebuild.bat               |  213 +

.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf    |   10 +-

.../IpmiPlatformHookLib.inf                   |    6 +-

.../Include/Guid/PchRcVariable.h              |    6 +

.../Include/Guid/SetupVariable.h              |   15 +-

.../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec |    1 +

.../Bus/Pci/PciBusDxe/ComponentName.c         |  170 +

.../Bus/Pci/PciBusDxe/ComponentName.h         |  146 +

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c   |  460 ++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h   |  396 ++

.../Bus/Pci/PciBusDxe/PciBusDxe.inf           |  112 +

.../Bus/Pci/PciBusDxe/PciBusDxe.uni           |   16 +

.../Bus/Pci/PciBusDxe/PciBusDxeExtra.uni      |   14 +

.../Bus/Pci/PciBusDxe/PciCommand.c            |  267 +

.../Bus/Pci/PciBusDxe/PciCommand.h            |  232 +

.../Bus/Pci/PciBusDxe/PciDeviceSupport.c      | 1056 +++

.../Bus/Pci/PciBusDxe/PciDeviceSupport.h      |  266 +

.../Bus/Pci/PciBusDxe/PciDriverOverride.c     |  188 +

.../Bus/Pci/PciBusDxe/PciDriverOverride.h     |   83 +

.../Bus/Pci/PciBusDxe/PciEnumerator.c         | 2210 ++++++

.../Bus/Pci/PciBusDxe/PciEnumerator.h         |  515 ++

.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c  | 2885 ++++++++  .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.h  |  480 ++

.../Bus/Pci/PciBusDxe/PciHotPlugSupport.c     |  484 ++

.../Bus/Pci/PciBusDxe/PciHotPlugSupport.h     |  205 +

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c    | 2087 ++++++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h    |  660 ++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c   | 1809 +++++

.../MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h   |  179 +

.../Bus/Pci/PciBusDxe/PciOptionRomSupport.c   |  776 ++

.../Bus/Pci/PciBusDxe/PciOptionRomSupport.h   |  136 +

.../Bus/Pci/PciBusDxe/PciPowerManagement.c    |   82 +

.../Bus/Pci/PciBusDxe/PciPowerManagement.h    |   28 +

.../Bus/Pci/PciBusDxe/PciResourceSupport.c    | 2292 ++++++

.../Bus/Pci/PciBusDxe/PciResourceSupport.h    |  456 ++

.../Bus/Pci/PciBusDxe/PciRomTable.c           |  135 +

.../Bus/Pci/PciBusDxe/PciRomTable.h           |   48 +

Platform/Intel/build.cfg                      |    2 +

Platform/Intel/build_bios.py                  |    3 +-

80 files changed, 30278 insertions(+), 240 deletions(-)  create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/GitEdk2MinTiogaPass.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformHookLib/BasePlatformHookLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BasePlatformHookLib/BasePlatformHookLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/DxeTiogaPassAcpiTableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardAcpiLib/SmmTiogaPassAcpiEnableLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/AllLanesEparam.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/GpioTable.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/IioBifur.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPostMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPostMemLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPreMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiBoardInitPreMemLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassDetect.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitLib.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitPostMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/PeiTiogaPassInitPreMemLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/BoardInitLib/UsbOC.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib/PeiReportFvLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/Library/PeiReportFvLib/PeiReportFvLib.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgBuildOption.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgConfig.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/PlatformPkgPcd.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/StructureConfig.dsc

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/__init__.py

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/bld.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_board.py

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/logo.txt

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/postbuild.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/prebuild.bat

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/ComponentName.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.uni

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxeExtra.uni

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciDriverOverride.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciPowerManagement.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.c

create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Override/MdeModulePkg/Bus/Pci/PciBusDxe/PciRomTable.h


回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure Defintions to resolve the IPMI build error

gaoliming
 

Manickavasakam:
Please update this patch. It also includes
0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch.

The patch should only include the code changes in MdePkg.

Thanks
Liming
-----邮件原件-----
发件人: gaoliming <gaoliming@byosoft.com.cn>
发送时间: 2021年6月17日 10:50
收件人: 'manickavasakam karpagavinayagam'
<manickavasakamk@ami.com>; 'devel@edk2.groups.io'
<devel@edk2.groups.io>
抄送: 'isaac.w.oram@intel.com' <isaac.w.oram@intel.com>;
'nathaniel.l.desimone@intel.com' <nathaniel.l.desimone@intel.com>;
'Felixp@ami.com' <Felixp@ami.com>; 'Harikrishnad@ami.com'
<Harikrishnad@ami.com>; 'manishj@ami.com' <manishj@ami.com>;
'zacharyb@ami.com' <zacharyb@ami.com>
主题: 回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure
Defintions to resolve the IPMI build error



-----邮件原件-----
发件人: manickavasakam karpagavinayagam
<manickavasakamk@ami.com>
发送时间: 2021年6月12日 5:50
收件人: devel@edk2.groups.io
抄送: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com;
Felixp@ami.com; Harikrishnad@ami.com; manishj@ami.com;
zacharyb@ami.com; manickavasakamk@ami.com;
gaoliming@byosoft.com.cn
主题: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure
Defintions
to resolve the IPMI build error

Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
EFI_IPMI_MSG_GET_BMC_EXEC_RSP and macros
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCE
D_UPDATE_MODE
when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg

MdePkg : Rename IPMI Macro and Structure Defintions

Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE
---

Notes:
V1 :
- Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
- EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
- IPMI_BMC_IN_FORCED_UPDATE_MODE

0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch | 61
++++++++++++++++++++
MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h |
4 ++
MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
|
18 ++++++
3 files changed, 83 insertions(+)

diff --git
a/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
new file mode 100644
index 0000000000..16d149e2d8
--- /dev/null
+++ b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
@@ -0,0 +1,61 @@
+From c5e221cfe5d815883f39b71667b6e8f644a27390 Mon Sep 17
00:00:00
2001
+From: manickavasakam karpagavinayagam
<manickavasakamk@ami.com>
+Date: Thu, 10 Jun 2021 14:59:22 -0400
+Subject: [edk2][PATCH] MdePkg : Add IPMI Macro and Structure Defintions
to resolve
+ the IPMI build error
+
+Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
+EFI_IPMI_MSG_GET_BMC_EXEC_RSP and macros
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
+EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORC
ED_UPDATE_MODE
+when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg
+---
+ MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h | 4 ++++
+ MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h | 19
+++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+index 79db55523d..d7cdd3a865 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+@@ -186,6 +186,10 @@ typedef struct {
+ UINT8 ParameterData[0];
+ } IPMI_SET_BOOT_OPTIONS_REQUEST;
+
++typedef struct {
++ UINT8 CompletionCode:8;
++} IPMI_SET_BOOT_OPTIONS_RESPONSE;
++
+ //
+ // Definitions for Get System Boot options command
+ //
+diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+index 2d892dbd5a..1c692cc792 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+@@ -17,4 +17,23 @@
+ // All Firmware commands and their structure definitions to follow
here
+ //
+
++/*------------------------------------------------------------------------
---------------
-
++ Definitions for Get BMC Execution Context
++--------------------------------------------------------------------------
--------------*
/
++#define EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT 0x23
++
++//
++// Constants and Structure definitions for "Get Device ID" command to
follow here
++//
++typedef struct {
++ UINT8 CurrentExecutionContext;
++ UINT8 PartitionPointer;
++} EFI_IPMI_MSG_GET_BMC_EXEC_RSP;
++
++//
++// Current Execution Context responses
++//
++#define EFI_FIRMWARE_BMC_IN_FULL_RUNTIME 0x10
++#define EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE 0x11
++
+ #endif
+--
+2.25.0.windows.1
+
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 79db55523d..d7cdd3a865 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -186,6 +186,10 @@ typedef struct {
UINT8 ParameterData[0];

} IPMI_SET_BOOT_OPTIONS_REQUEST;



+typedef struct {

+ UINT8 CompletionCode:8;

+} IPMI_SET_BOOT_OPTIONS_RESPONSE;

+

//

// Definitions for Get System Boot options command

//

diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index 2d892dbd5a..c4cbe2349b 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -17,4 +17,22 @@
// All Firmware commands and their structure definitions to follow here

//



+//
----------------------------------------------------------------------------
------------

+// Definitions for Get BMC Execution Context

+//
----------------------------------------------------------------------------
------------

+#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23

+

+//

+// Constants and Structure definitions for "Get Device ID" command to
follow here

+//

+typedef struct {

+ UINT8 CurrentExecutionContext;

+ UINT8 PartitionPointer;

+} IPMI_MSG_GET_BMC_EXEC_RSP;

+

+//

+// Current Execution Context responses

+//

+#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11

+

#endif

--
2.25.0.windows.1


Please consider the environment before printing this email.

The information contained in this message may be confidential and
proprietary to American Megatrends (AMI). This communication is
intended
to be read only by the individual or entity to whom it is addressed or
by their
designee. If the reader of this message is not the intended recipient,
you are
on notice that any distribution of this message, in any form, is
strictly
prohibited. Please promptly notify the sender by reply e-mail or by
telephone at 770-246-8600, and then delete or destroy all copies of the
transmission.


回复: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure Defintions to resolve the IPMI build error

gaoliming
 

-----邮件原件-----
发件人: manickavasakam karpagavinayagam <manickavasakamk@ami.com>
发送时间: 2021年6月12日 5:50
收件人: devel@edk2.groups.io
抄送: isaac.w.oram@intel.com; nathaniel.l.desimone@intel.com;
Felixp@ami.com; Harikrishnad@ami.com; manishj@ami.com;
zacharyb@ami.com; manickavasakamk@ami.com;
gaoliming@byosoft.com.cn
主题: [edk2][PATCH V1] MdePkg : Add IPMI Macro and Structure Defintions
to resolve the IPMI build error

Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
EFI_IPMI_MSG_GET_BMC_EXEC_RSP and macros
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORCE
D_UPDATE_MODE
when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg

MdePkg : Rename IPMI Macro and Structure Defintions

Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
IPMI_BMC_IN_FORCED_UPDATE_MODE
---

Notes:
V1 :
- Rename the EFI_IPMI_MSG_GET_BMC_EXEC_RSPB,
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
- EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE to
IPMI_MSG_GET_BMC_EXEC_RSPB,IPMI_GET_BMC_EXECUTION_CONTEXT
- IPMI_BMC_IN_FORCED_UPDATE_MODE

0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch | 61
++++++++++++++++++++
MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h |
4 ++
MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h |
18 ++++++
3 files changed, 83 insertions(+)

diff --git
a/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
new file mode 100644
index 0000000000..16d149e2d8
--- /dev/null
+++ b/0001-MdePkg-Add-IPMI-Macro-and-Structure-Defintions-to-re.patch
@@ -0,0 +1,61 @@
+From c5e221cfe5d815883f39b71667b6e8f644a27390 Mon Sep 17 00:00:00
2001
+From: manickavasakam karpagavinayagam <manickavasakamk@ami.com>
+Date: Thu, 10 Jun 2021 14:59:22 -0400
+Subject: [edk2][PATCH] MdePkg : Add IPMI Macro and Structure Defintions
to resolve
+ the IPMI build error
+
+Build error reported for missing structures
IPMI_SET_BOOT_OPTIONS_RESPONSE,
+EFI_IPMI_MSG_GET_BMC_EXEC_RSP and macros
EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT
+EFI_FIRMWARE_BMC_IN_FULL_RUNTIME/EFI_FIRMWARE_BMC_IN_FORC
ED_UPDATE_MODE
+when using
edk2-platforms\Features\Intel\OutOfBandManagement\IpmiFeaturePkg
+---
+ MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h | 4 ++++
+ MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h | 19
+++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+
+diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+index 79db55523d..d7cdd3a865 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+@@ -186,6 +186,10 @@ typedef struct {
+ UINT8 ParameterData[0];
+ } IPMI_SET_BOOT_OPTIONS_REQUEST;
+
++typedef struct {
++ UINT8 CompletionCode:8;
++} IPMI_SET_BOOT_OPTIONS_RESPONSE;
++
+ //
+ // Definitions for Get System Boot options command
+ //
+diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+index 2d892dbd5a..1c692cc792 100644
+--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
++++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+@@ -17,4 +17,23 @@
+ // All Firmware commands and their structure definitions to follow here
+ //
+
++/*------------------------------------------------------------------------
---------------
-
++ Definitions for Get BMC Execution Context
++--------------------------------------------------------------------------
--------------*
/
++#define EFI_FIRMWARE_GET_BMC_EXECUTION_CONTEXT 0x23
++
++//
++// Constants and Structure definitions for "Get Device ID" command to
follow here
++//
++typedef struct {
++ UINT8 CurrentExecutionContext;
++ UINT8 PartitionPointer;
++} EFI_IPMI_MSG_GET_BMC_EXEC_RSP;
++
++//
++// Current Execution Context responses
++//
++#define EFI_FIRMWARE_BMC_IN_FULL_RUNTIME 0x10
++#define EFI_FIRMWARE_BMC_IN_FORCED_UPDATE_MODE 0x11
++
+ #endif
+--
+2.25.0.windows.1
+
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 79db55523d..d7cdd3a865 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -186,6 +186,10 @@ typedef struct {
UINT8 ParameterData[0];

} IPMI_SET_BOOT_OPTIONS_REQUEST;



+typedef struct {

+ UINT8 CompletionCode:8;

+} IPMI_SET_BOOT_OPTIONS_RESPONSE;

+

//

// Definitions for Get System Boot options command

//

diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index 2d892dbd5a..c4cbe2349b 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -17,4 +17,22 @@
// All Firmware commands and their structure definitions to follow here

//



+//
----------------------------------------------------------------------------
------------

+// Definitions for Get BMC Execution Context

+//
----------------------------------------------------------------------------
------------

+#define IPMI_GET_BMC_EXECUTION_CONTEXT 0x23

+

+//

+// Constants and Structure definitions for "Get Device ID" command to
follow here

+//

+typedef struct {

+ UINT8 CurrentExecutionContext;

+ UINT8 PartitionPointer;

+} IPMI_MSG_GET_BMC_EXEC_RSP;

+

+//

+// Current Execution Context responses

+//

+#define IPMI_BMC_IN_FORCED_UPDATE_MODE 0x11

+

#endif

--
2.25.0.windows.1


Please consider the environment before printing this email.

The information contained in this message may be confidential and
proprietary to American Megatrends (AMI). This communication is intended
to be read only by the individual or entity to whom it is addressed or by
their
designee. If the reader of this message is not the intended recipient, you
are
on notice that any distribution of this message, in any form, is strictly
prohibited. Please promptly notify the sender by reply e-mail or by
telephone at 770-246-8600, and then delete or destroy all copies of the
transmission.

7681 - 7700 of 84265