Date   

Re: [PATCH 1/1] BaseTools GenFw: Keep read only alloc section as text section when convert ELF

Bob Feng
 

Reviewed-by: Bob Feng <bob.c.feng@intel.com>

-----Original Message-----
From: Liming Gao <gaoliming@byosoft.com.cn>
Sent: Wednesday, June 9, 2021 6:06 PM
To: devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: [PATCH 1/1] BaseTools GenFw: Keep read only alloc section as text section when convert ELF

This is the fix of the regression issue at c6b872c6.
Based on ELF spec, readonly alloc section is .rodata section. It is requried.
This fix is to add back original check logic for ELF section. Now, the readonly alloc section and execute alloc section are regarded as .text section.

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
With this fix, previous fix commit ec1cffd9 is not required. But, the checker added by commit ec1cffd9 is correct for ACPI data conversion. So, I don't plan to revert it.

BaseTools/Source/C/GenFw/Elf32Convert.c | 3 ++- BaseTools/Source/C/GenFw/Elf64Convert.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 314f8233234d..d917a444c82d 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -238,7 +238,8 @@ IsTextShdr (
Elf_Shdr *Shdr
)
{
- return (BOOLEAN) ((Shdr->sh_flags & (SHF_EXECINSTR | SHF_ALLOC)) == (SHF_EXECINSTR | SHF_ALLOC));
+ return (BOOLEAN) (((Shdr->sh_flags & (SHF_EXECINSTR | SHF_ALLOC)) == (SHF_EXECINSTR | SHF_ALLOC)) ||
+ ((Shdr->sh_flags & (SHF_WRITE | SHF_ALLOC)) ==
+ SHF_ALLOC));
}

STATIC
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 8b09db7b690b..33031ec8f6e7 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -246,7 +246,8 @@ IsTextShdr (
Elf_Shdr *Shdr
)
{
- return (BOOLEAN) ((Shdr->sh_flags & (SHF_EXECINSTR | SHF_ALLOC)) == (SHF_EXECINSTR | SHF_ALLOC));
+ return (BOOLEAN) (((Shdr->sh_flags & (SHF_EXECINSTR | SHF_ALLOC)) == (SHF_EXECINSTR | SHF_ALLOC)) ||
+ ((Shdr->sh_flags & (SHF_WRITE | SHF_ALLOC)) ==
+ SHF_ALLOC));
}

STATIC
--
2.27.0.windows.1


回复: [edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - 06/15/2021 #cal-reminder

gaoliming
 

Hi, all

 The following issues will be discussed in this week TianoCore Bug Triage meeting.

 

3458

EDK2

Code

unassigned@...

UNCO

Add support IORT Rev E.b specification updates

16:28:58

sami.mujawar@...

3457

EDK2

Code

unassigned@...

UNCO

Support measured AMD SEV boot with kernel/initrd/cmdline

Mon 03:31

dovmurik@...

3456

EDK2 Pla

BoardMod

unassigned@...

UNCO

RngLib not found error when the CAPSULE_ENABLE defined.

Sun 09:19

jiaoxf95@...

3315

EDK2

Code

mhaeuser@...

UNCO

DxeCore: Unloading image pre-CpuDxe may dereference NULL

Sat 09:30

mhaeuser@...

3455

EDK2

Code

sachin.agrawal@...

UNCO

RSA PSS API had better enforce SaltSize to be same as DigestSize

Sat 07:35

jiewen.yao@...

3454

EDK2

Code

unassigned@...

UNCO

Spellcheck plugin finds fewer files when run on Linux

Sat 01:06

sean.brogan@...

3445

EDK2

Code

unassigned@...

UNCO

Update node to at least 12 to support cspell

Fri 23:58

kun.qin@...

3453

EDK2

Code

unassigned@...

UNCO

ipxe Boot throws exception when accessing SNP Interfaces

Fri 08:35

sivaramann@...

3447

Tianocor

Code

zhiguang.liu@...

UNCO

Create header files and multiple Hobs for Universal Payload

Thu 22:05

zhiguang.liu@...

3449

EDK2

Code

unassigned@...

UNCO

VariablePolicy needs to replace VariableLock.

Thu 17:33

klautner@...

3448

Tianocor

Code

unassigned@...

UNCO

EDK II platform for Cherry Trail

Thu 13:22

nicklas.frahm@...

3446

Tianocor

Code

unassigned@...

UNCO

TianoCore missing support for Specification 2.8 Items

Thu 12:44

kevin.davis@...

3444

EDK2 Pla

OptionRo

unassigned@...

UNCO

FtdiUsbSerialDriverDxe doesn't properly initialize

Wed 14:38

jack.tay.little@...

3442

EDK2

Code

unassigned@...

UNCO

The value of TPM_RC_BAD_TAG is wrong

Wed 06:21

nicolas.iooss.2010_tianocor...

3441

EDK2

Code

zhiguang.liu@...

UNCO

Device path has wrong FV path if the boot manager menu is from different FV

2021-06-09

zhiguang.liu@...

3402

EDK2

Code

unassigned@...

UNCO

it will take too long time(about 40s) to save IIO Configuration SETUP value on EGS CRB board.

2021-06-09

shengfengx.xue@...

3440

EDK2

Code

unassigned@...

UNCO

Add MM Configuration PPI definition to MdePkg

2021-06-09

kun.qin@...

 

Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 devel@edk2.groups.io Calendar
发送时间: 2021615 9:30
收件人: devel@edk2.groups.io
主题: [edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - 06/15/2021 #cal-reminder

 

Reminder: TianoCore Bug Triage - APAC / NAMO

When:
06/15/2021
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles

Where:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTUyZTg2NjgtNDhlNS00ODVlLTllYTUtYzg1OTNjNjdiZjFh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%22b286b53a-1218-4db3-bfc9-3d4c5aa7669e%22%7d

Organizer: Liming Gao gaoliming@...

View Event

Description:

TianoCore Bug Triage - APAC / NAMO

Hosted by Liming Gao

 

________________________________________________________________________________

Microsoft Teams meeting

Join on your computer or mobile app

Click here to join the meeting

Join with a video conferencing device

teams@...

Video Conference ID: 116 062 094 0

Alternate VTC dialing instructions

Or call in (audio only)

+1 916-245-6934,,77463821#   United States, Sacramento

Phone Conference ID: 774 638 21#

Find a local number | Reset PIN

Learn More | Meeting options


Re: [PATCH 0/4] Prepare bhyve's OVMF for GPU-Passthrough

Peter Grehan
 

Hi Corvin,

GPU-Passthrough for bhyve requires a few patches to work properly.
These patches will allow GPU-Passthrough for bhyve.
It will work for dedicated AMD GPUs and integrated Intel GPUs.
I have no issue with adding USB support or fixing the PCI32 base: that either codifies existing behaviour or adds functionality.

However, flipping the switch over to bus enumeration being in EFI is a policy change in how bhyve has always worked - can that be discussed on the freebsd-virtualization first ?

later,

Peter.


Re: [edk2-platforms PATCH 0/4] ACPI MDIO support for Marvell SoCs

Jon Nettleton
 

On Mon, Jun 14, 2021 at 11:55 PM Leif Lindholm <leif@nuviainc.com> wrote:

Hi Marcin,

On Sun, Jun 13, 2021 at 20:16:27 +0200, Marcin Wojtas wrote:
Hi,

The MDIO ACPI binding has been established and merged to the
Linux tree,
Congratulations! :)

Is FreeBSD expected to follow suit?

hence it is now possible to update the ACPI
description of the platforms that base on the Marvell SoCs.

For convenience, the code is exposed in the public github branch:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/acpi-mdio-r20210613
There is also MacchiatoBin firmware binary avaialable for testing:
https://drive.google.com/file/d/1eigP_aeM4wYQpEaLAlQzs3IN_w1-kQr0

I'm looking forward to the comments or remarks.
The patches themselves look straightforward enough.
I *would* prefer some tested-by, for these sources rather than the
binary, before merging though.
I will get the ACPI changes from Marcin and put a Tested-By on
from SolidRun's side.

Jon


Best Regards,

Leif

Best regards,
Marcin

Marcin Wojtas (4):
SolidRun/Armada80x0McBin: Add ACPI MDIO description
Marvell/Cn913xDb: Add ACPI MDIO description
Marvell/Armada70x0Db: Add ACPI MDIO description
Marvell/Armada80x0Db: Add ACPI MDIO description

Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 24 +++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 38 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 53 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 24 +++++++++
5 files changed, 140 insertions(+)

--
2.29.0


Re: [PATCH] MdeModulePkg: Fix device path when the boot manager menu is from different FV

Wu, Hao A
 

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Wednesday, June 9, 2021 5:37 PM
To: devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>;
Gao, Zhichao <zhichao.gao@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: [PATCH] MdeModulePkg: Fix device path when the boot manager
menu is from different FV

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3441

When the boot manager menu is from different FV, the current logic still use
the
device path of the FV as the module links to this library

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 28 +++-------------
------------
1 file changed, 3 insertions(+), 25 deletions(-)

diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
index bef41ae102..95d185b639 100644
--- a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
+++ b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
@@ -2405,13 +2405,9 @@ BmRegisterBootManagerMenu (
CHAR16 *Description;

UINTN DescriptionLength;

EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;

- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;

UINTN HandleCount;

EFI_HANDLE *Handles;

UINTN Index;

- VOID *Data;

- UINTN DataSize;



DevicePath = NULL;

Description = NULL;

@@ -2437,22 +2433,17 @@ BmRegisterBootManagerMenu (
}



if (DevicePath == NULL) {

- Data = NULL;

- Status = GetSectionFromAnyFv (

+ Status = GetFileDevicePathFromAnyFv (

PcdGetPtr (PcdBootManagerMenuFile),

EFI_SECTION_PE32,

0,

- (VOID **) &Data,

- &DataSize

+ &DevicePath

);

- if (Data != NULL) {

- FreePool (Data);

- }

if (EFI_ERROR (Status)) {

DEBUG ((EFI_D_WARN, "[Bds]BootManagerMenu FFS section can not be
found, skip its boot option registration\n"));

return EFI_NOT_FOUND;

}

-

+ ASSERT (DevicePath != NULL);

//

// Get BootManagerMenu application's description from EFI User
Interface Section.

//

@@ -2466,19 +2457,6 @@ BmRegisterBootManagerMenu (
if (EFI_ERROR (Status)) {

Description = NULL;

}

-

- EfiInitializeFwVolDevicepathNode (&FileNode, PcdGetPtr
(PcdBootManagerMenuFile));

- Status = gBS->HandleProtocol (

- gImageHandle,

- &gEfiLoadedImageProtocolGuid,

- (VOID **) &LoadedImage

- );

- ASSERT_EFI_ERROR (Status);

- DevicePath = AppendDevicePathNode (

- DevicePathFromHandle (LoadedImage->DeviceHandle),

- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode

- );

- ASSERT (DevicePath != NULL);

}

Acked-by: Hao A Wu <hao.a.wu@intel.com>

Best Regards,
Hao Wu





Status = EfiBootManagerInitializeLoadOption (

--
2.30.0.windows.2


Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations

Daniel Schaefer
 

Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other concern.
This patch lets us build the RISC-V platforms using modern toolchains that are provided directly by the distributions, rather than building your own from source.

Thanks,
Daniel


From: Sunil V L <sunilvl@...>
Sent: Friday, June 11, 2021 22:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; Schaefer, Daniel <daniel.schaefer@...>; Bob Feng <bob.c.feng@...>; Liming Gao <gaoliming@...>; Yuwei Chen <yuwei.chen@...>; Heinrich Schuchardt <xypron.glpk@...>
Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations
 
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
>
> This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
> relocations generated by PIE enabled compiler. This also needed
> changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
> https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
>
> Changes in v2:
>   - Addressed Daniel's comment on formatting
>
> Testing:
> 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
> 2) Debian 10.2.0 and booted QEMU virt model.
> 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.
>
> Signed-off-by: Sunil V L <sunilvl@...>
>
> Acked-by: Abner Chang <abner.chang@...>
> Reviewed-by: Daniel Schaefer <daniel.schaefer@...>
> Tested-by: <daniel.schaefer@...>
>
> Cc: Bob Feng <bob.c.feng@...>
> Cc: Liming Gao <gaoliming@...>
> Cc: Yuwei Chen <yuwei.chen@...>
> Cc: Heinrich Schuchardt <xypron.glpk@...>
> ---
>  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
>  1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
> index d097db8632..d684318269 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
>  STATIC UINT8       *mRiscVPass1Targ = NULL;
>  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
>  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
> +STATIC INT32       mRiscVPass1Offset;
> +STATIC INT32       mRiscVPass1GotFixup;

>  //
>  // Initialization Function
> @@ -479,11 +481,11 @@ WriteSectionRiscV64 (
>      break;

>    case R_RISCV_32:
> -    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
>      break;

>    case R_RISCV_64:
> -    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
>      break;

>    case R_RISCV_HI20:
> @@ -533,6 +535,18 @@ WriteSectionRiscV64 (
>      mRiscVPass1SymSecIndex = 0;
>      break;

> +  case R_RISCV_GOT_HI20:
> +    Value = (Sym->st_value - Rel->r_offset);
> +    mRiscVPass1Offset = RV_X(Value, 0, 12);
> +    Value = RV_X(Value, 12, 20);
> +    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
> +
> +    mRiscVPass1Targ = Targ;
> +    mRiscVPass1Sym = SymShdr;
> +    mRiscVPass1SymSecIndex = Sym->st_shndx;
> +    mRiscVPass1GotFixup = 1;
> +    break;
> +
>    case R_RISCV_PCREL_HI20:
>      mRiscVPass1Targ = Targ;
>      mRiscVPass1Sym = SymShdr;
> @@ -545,11 +559,17 @@ WriteSectionRiscV64 (
>      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
>        int i;
>        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
> -      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> -      if(Value & (RISCV_IMM_REACH/2)) {
> -        Value |= ~(RISCV_IMM_REACH-1);
> +
> +      if(mRiscVPass1GotFixup) {
> +        Value = (UINT32)(mRiscVPass1Offset);
> +      } else {
> +        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> +        if(Value & (RISCV_IMM_REACH/2)) {
> +          Value |= ~(RISCV_IMM_REACH-1);
> +        }
>        }
>        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
> +
>        if(-2048 > (INT32)Value) {
>          i = (((INT32)Value * -1) / 4096);
>          Value2 -= i;
> @@ -569,12 +589,21 @@ WriteSectionRiscV64 (
>          }
>        }

> -      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      if(mRiscVPass1GotFixup) {
> +        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
> +                            | (RV_X(*(UINT32*)Targ, 0, 20));
> +        /* Convert LD instruction to ADDI */
> +        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
> +      } else {
> +        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      }
>        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
>      }
>      mRiscVPass1Sym = NULL;
>      mRiscVPass1Targ = NULL;
>      mRiscVPass1SymSecIndex = 0;
> +    mRiscVPass1Offset = 0;
> +    mRiscVPass1GotFixup = 0;
>      break;

>    case R_RISCV_ADD64:
> @@ -586,6 +615,7 @@ WriteSectionRiscV64 (
>    case R_RISCV_GPREL_I:
>    case R_RISCV_GPREL_S:
>    case R_RISCV_CALL:
> +  case R_RISCV_CALL_PLT:
>    case R_RISCV_RVC_BRANCH:
>    case R_RISCV_RVC_JUMP:
>    case R_RISCV_RELAX:
> @@ -1528,6 +1558,7 @@ WriteRelocations64 (
>              case R_RISCV_GPREL_I:
>              case R_RISCV_GPREL_S:
>              case R_RISCV_CALL:
> +            case R_RISCV_CALL_PLT:
>              case R_RISCV_RVC_BRANCH:
>              case R_RISCV_RVC_JUMP:
>              case R_RISCV_RELAX:
> @@ -1537,6 +1568,7 @@ WriteRelocations64 (
>              case R_RISCV_SET16:
>              case R_RISCV_SET32:
>              case R_RISCV_PCREL_HI20:
> +            case R_RISCV_GOT_HI20:
>              case R_RISCV_PCREL_LO12_I:
>                break;

> --
> 2.25.1
>


Event: TianoCore Bug Triage - APAC / NAMO - 06/15/2021 #cal-reminder

devel@edk2.groups.io Calendar <noreply@...>
 

Reminder: TianoCore Bug Triage - APAC / NAMO

When:
06/15/2021
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles

Where:
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTUyZTg2NjgtNDhlNS00ODVlLTllYTUtYzg1OTNjNjdiZjFh%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%22b286b53a-1218-4db3-bfc9-3d4c5aa7669e%22%7d

Organizer: Liming Gao gaoliming@...

View Event

Description:

TianoCore Bug Triage - APAC / NAMO

Hosted by Liming Gao

 

________________________________________________________________________________

Microsoft Teams meeting

Join on your computer or mobile app

Click here to join the meeting

Join with a video conferencing device

teams@...

Video Conference ID: 116 062 094 0

Alternate VTC dialing instructions

Or call in (audio only)

+1 916-245-6934,,77463821#   United States, Sacramento

Phone Conference ID: 774 638 21#

Find a local number | Reset PIN

Learn More | Meeting options


Re: [PATCH v3 3/8] SecurityPkg: Create include file for default key content.

Yao, Jiewen
 

Hi
I am not sure why we hardcode 3 items for each.

Can we move this fdf to platform pkg, instead of security pkg ?

Thank you
Yao Jiewen

-----Original Message-----
From: Grzegorz Bernacki <gjb@semihalf.com>
Sent: Monday, June 14, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: leif@nuviainc.com; ardb+tianocore@kernel.org; Samer.El-Haj-
Mahmoud@arm.com; sunny.Wang@arm.com; mw@semihalf.com;
upstream@semihalf.com; Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J
<jian.j.wang@intel.com>; Xu, Min M <min.m.xu@intel.com>;
lersek@redhat.com; sami.mujawar@arm.com; afish@apple.com; Ni, Ray
<ray.ni@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>;
rebecca@bsdio.com; grehan@freebsd.org; thomas.abraham@arm.com; Chiu,
Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
<nathaniel.l.desimone@intel.com>; gaoliming@byosoft.com.cn; Dong, Eric
<eric.dong@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Sun,
Zailiang <zailiang.sun@intel.com>; Qian, Yi <yi.qian@intel.com>;
graeme@nuviainc.com; rad@semihalf.com; pete@akeo.ie; Grzegorz Bernacki
<gjb@semihalf.com>
Subject: [PATCH v3 3/8] SecurityPkg: Create include file for default key content.

This commits add file which can be included by platform Flash
Description File. It allows to specify certificate files, which
will be embedded into binary file. The content of these files
can be used to initialize Secure Boot default keys and databases.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
---
SecurityPkg/SecureBootDefaultKeys.fdf.inc | 70 ++++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 SecurityPkg/SecureBootDefaultKeys.fdf.inc

diff --git a/SecurityPkg/SecureBootDefaultKeys.fdf.inc
b/SecurityPkg/SecureBootDefaultKeys.fdf.inc
new file mode 100644
index 0000000000..bf4f2d42de
--- /dev/null
+++ b/SecurityPkg/SecureBootDefaultKeys.fdf.inc
@@ -0,0 +1,70 @@
+## @file
+# FDF include file which allows to embed Secure Boot keys
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.
+# Copyright (c) 2021, Semihalf. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+!if $(DEFAULT_KEYS) == TRUE
+ FILE FREEFORM = 85254ea7-4759-4fc4-82d4-5eed5fb0a4a0 {
+ !ifdef $(PK_DEFAULT_FILE)
+ SECTION RAW = $(PK_DEFAULT_FILE)
+ !endif
+ SECTION UI = "PK Default"
+ }
+
+ FILE FREEFORM = 6f64916e-9f7a-4c35-b952-cd041efb05a3 {
+ !ifdef $(KEK_DEFAULT_FILE1)
+ SECTION RAW = $(KEK_DEFAULT_FILE1)
+ !endif
+ !ifdef $(KEK_DEFAULT_FILE2)
+ SECTION RAW = $(KEK_DEFAULT_FILE2)
+ !endif
+ !ifdef $(KEK_DEFAULT_FILE3)
+ SECTION RAW = $(KEK_DEFAULT_FILE3)
+ !endif
+ SECTION UI = "KEK Default"
+ }
+
+ FILE FREEFORM = c491d352-7623-4843-accc-2791a7574421 {
+ !ifdef $(DB_DEFAULT_FILE1)
+ SECTION RAW = $(DB_DEFAULT_FILE1)
+ !endif
+ !ifdef $(DB_DEFAULT_FILE2)
+ SECTION RAW = $(DB_DEFAULT_FILE2)
+ !endif
+ !ifdef $(DB_DEFAULT_FILE3)
+ SECTION RAW = $(DB_DEFAULT_FILE3)
+ !endif
+ SECTION UI = "DB Default"
+ }
+
+ FILE FREEFORM = 36c513ee-a338-4976-a0fb-6ddba3dafe87 {
+ !ifdef $(DBT_DEFAULT_FILE1)
+ SECTION RAW = $(DBT_DEFAULT_FILE1)
+ !endif
+ !ifdef $(DBT_DEFAULT_FILE2)
+ SECTION RAW = $(DBT_DEFAULT_FILE2)
+ !endif
+ !ifdef $(DBT_DEFAULT_FILE3)
+ SECTION RAW = $(DBT_DEFAULT_FILE3)
+ !endif
+ SECTION UI = "DBT Default"
+ }
+
+ FILE FREEFORM = 5740766a-718e-4dc0-9935-c36f7d3f884f {
+ !ifdef $(DBX_DEFAULT_FILE1)
+ SECTION RAW = $(DBX_DEFAULT_FILE1)
+ !endif
+ !ifdef $(DBX_DEFAULT_FILE2)
+ SECTION RAW = $(DBX_DEFAULT_FILE2)
+ !endif
+ !ifdef $(DBX_DEFAULT_FILE3)
+ SECTION RAW = $(DBX_DEFAULT_FILE3)
+ !endif
+ SECTION UI = "DBX Default"
+ }
+
+!endif
--
2.25.1


Re: [Patch V2] BaseTools: Enable the flag to treat dynamic pcd as dynamicEx

Bob Feng
 

Add Mike Turner for review.

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Bob Feng
Sent: Tuesday, June 8, 2021 10:50 AM
To: devel@edk2.groups.io
Cc: Liming Gao <gaoliming@byosoft.com.cn>; Chen, Christine <yuwei.chen@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Subject: [edk2-devel] [Patch V2] BaseTools: Enable the flag to treat dynamic pcd as dynamicEx

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1688

In order to support binary build, build tool add a flag to convert type of Dynamic Pcd to DynamicEx Pcd

User can append -D PCD_DYNAMIC_AS_DYNAMICEX to build command to enable this function.
Also, user can add "PCD_DYNAMIC_AS_DYNAMICEX = TRUE/FALSE"
to the defines section of Dsc file to enable this function.

PCD_DYNAMIC_AS_DYNAMICEX is a new reserved key word for this function.

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> ---Correct Liming's email address.
BaseTools/Source/Python/Common/DataType.py | 1 +
.../Python/Workspace/BuildClassObject.py | 153 ++++++++----------
.../Source/Python/Workspace/DecBuildData.py | 15 +-
.../Source/Python/Workspace/DscBuildData.py | 19 +--
.../Source/Python/Workspace/InfBuildData.py | 15 +-
5 files changed, 73 insertions(+), 130 deletions(-)

diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
index fb88f20cc4..4e9c9e34af 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -402,10 +402,11 @@ TAB_DSC_DEFINES_DSC_SPECIFICATION = 'DSC_SPECIFICATION'
TAB_DSC_DEFINES_OUTPUT_DIRECTORY = 'OUTPUT_DIRECTORY' TAB_DSC_DEFINES_SUPPORTED_ARCHITECTURES = 'SUPPORTED_ARCHITECTURES' TAB_DSC_DEFINES_BUILD_TARGETS = 'BUILD_TARGETS' TAB_DSC_DEFINES_SKUID_IDENTIFIER = 'SKUID_IDENTIFIER' TAB_DSC_DEFINES_PCD_INFO_GENERATION = 'PCD_INFO_GENERATION'+TAB_DSC_DEFINES_PCD_DYNAMIC_AS_DYNAMICEX = 'PCD_DYNAMIC_AS_DYNAMICEX' TAB_DSC_DEFINES_PCD_VAR_CHECK_GENERATION = 'PCD_VAR_CHECK_GENERATION' TAB_DSC_DEFINES_FLASH_DEFINITION = 'FLASH_DEFINITION' TAB_DSC_DEFINES_BUILD_NUMBER = 'BUILD_NUMBER' TAB_DSC_DEFINES_MAKEFILE_NAME = 'MAKEFILE_NAME' TAB_DSC_DEFINES_BS_BASE_ADDRESS = 'BsBaseAddress'diff --git a/BaseTools/Source/Python/Workspace/BuildClassObject.py b/BaseTools/Source/Python/Workspace/BuildClassObject.py
index ebb65fc2fe..88a1d1582c 100644
--- a/BaseTools/Source/Python/Workspace/BuildClassObject.py
+++ b/BaseTools/Source/Python/Workspace/BuildClassObject.py
@@ -10,11 +10,13 @@ from Common.DataType import * import collections import re from collections import OrderedDict from Common.Misc import CopyDict,ArrayIndex import copy+from CommonDataClass.DataClass import * import Common.EdkLogger as EdkLogger+import Common.GlobalData as GlobalData from Common.BuildToolError import OPTION_VALUE_INVALID from Common.caching import cached_property StructPattern = re.compile(r'[_a-zA-Z][0-9A-Za-z_\[\]]*$') ## PcdClassObject@@ -396,10 +398,71 @@ class StructurePcd(PcdClassObject):
new_pcd.ValueChain = {item for item in self.ValueChain} return new_pcd LibraryClassObject = namedtuple('LibraryClassObject', ['LibraryClass','SupModList']) +class BuildData(object):+ # dict used to convert PCD type in database to string used by build tool++ _PCD_TYPE_STRING_ = {+ MODEL_PCD_FIXED_AT_BUILD : TAB_PCDS_FIXED_AT_BUILD,+ MODEL_PCD_PATCHABLE_IN_MODULE : TAB_PCDS_PATCHABLE_IN_MODULE,+ MODEL_PCD_FEATURE_FLAG : TAB_PCDS_FEATURE_FLAG,+ MODEL_PCD_DYNAMIC : TAB_PCDS_DYNAMIC,+ MODEL_PCD_DYNAMIC_DEFAULT : TAB_PCDS_DYNAMIC,+ MODEL_PCD_DYNAMIC_HII : TAB_PCDS_DYNAMIC_HII,+ MODEL_PCD_DYNAMIC_VPD : TAB_PCDS_DYNAMIC_VPD,+ MODEL_PCD_DYNAMIC_EX : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_EX_DEFAULT : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_EX_HII : TAB_PCDS_DYNAMIC_EX_HII,+ MODEL_PCD_DYNAMIC_EX_VPD : TAB_PCDS_DYNAMIC_EX_VPD,+ }++ def UpdatePcdTypeDict(self):+ if GlobalData.gCommandLineDefines.get(TAB_DSC_DEFINES_PCD_DYNAMIC_AS_DYNAMICEX,"FALSE").upper() == "TRUE":+ self._PCD_TYPE_STRING_ = {+ MODEL_PCD_FIXED_AT_BUILD : TAB_PCDS_FIXED_AT_BUILD,+ MODEL_PCD_PATCHABLE_IN_MODULE : TAB_PCDS_PATCHABLE_IN_MODULE,+ MODEL_PCD_FEATURE_FLAG : TAB_PCDS_FEATURE_FLAG,+ MODEL_PCD_DYNAMIC : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_DEFAULT : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_HII : TAB_PCDS_DYNAMIC_EX_HII,+ MODEL_PCD_DYNAMIC_VPD : TAB_PCDS_DYNAMIC_EX_VPD,+ MODEL_PCD_DYNAMIC_EX : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_EX_DEFAULT : TAB_PCDS_DYNAMIC_EX,+ MODEL_PCD_DYNAMIC_EX_HII : TAB_PCDS_DYNAMIC_EX_HII,+ MODEL_PCD_DYNAMIC_EX_VPD : TAB_PCDS_DYNAMIC_EX_VPD,+ }++ ## Convert the class to a string+ #+ # Convert member MetaFile of the class to a string+ #+ # @retval string Formatted String+ #+ def __str__(self):+ return str(self.MetaFile)++ ## Override __eq__ function+ #+ # Check whether ModuleBuildClassObjects are the same+ #+ # @retval False The two ModuleBuildClassObjects are different+ # @retval True The two ModuleBuildClassObjects are the same+ #+ def __eq__(self, Other):+ return self.MetaFile == Other++ ## Override __hash__ function+ #+ # Use MetaFile as key in hash table+ #+ # @retval string Key for hash table+ #+ def __hash__(self):+ return hash(self.MetaFile)+ ## ModuleBuildClassObject # # This Class defines ModuleBuildClass # # @param object: Inherited from object class@@ -440,11 +503,11 @@ LibraryClassObject = namedtuple('LibraryClassObject', ['LibraryClass','SupModLis
# { [(PcdCName, PcdGuidCName)] : PcdClassObject} # @var BuildOptions: To store value for BuildOptions, it is a set structure as # { [BuildOptionKey] : BuildOptionValue} # @var Depex: To store value for Depex #-class ModuleBuildClassObject(object):+class ModuleBuildClassObject(BuildData): def __init__(self): self.AutoGenVersion = 0 self.MetaFile = '' self.BaseName = '' self.ModuleType = ''@@ -474,38 +537,10 @@ class ModuleBuildClassObject(object):
self.BuildOptions = {} self.Depex = {} self.StrPcdSet = [] self.StrPcdOverallValue = {} - ## Convert the class to a string- #- # Convert member MetaFile of the class to a string- #- # @retval string Formatted String- #- def __str__(self):- return str(self.MetaFile)-- ## Override __eq__ function- #- # Check whether ModuleBuildClassObjects are the same- #- # @retval False The two ModuleBuildClassObjects are different- # @retval True The two ModuleBuildClassObjects are the same- #- def __eq__(self, Other):- return self.MetaFile == Other-- ## Override __hash__ function- #- # Use MetaFile as key in hash table- #- # @retval string Key for hash table- #- def __hash__(self):- return hash(self.MetaFile)- ## PackageBuildClassObject # # This Class defines PackageBuildClass # # @param object: Inherited from object class@@ -525,11 +560,11 @@ class ModuleBuildClassObject(object):
# @var LibraryClasses: To store value for LibraryClasses, it is a set structure as # { [LibraryClassName] : LibraryClassInfFile } # @var Pcds: To store value for Pcds, it is a set structure as # { [(PcdCName, PcdGuidCName)] : PcdClassObject} #-class PackageBuildClassObject(object):+class PackageBuildClassObject(BuildData): def __init__(self): self.MetaFile = '' self.PackageName = '' self.Guid = '' self.Version = ''@@ -539,38 +574,10 @@ class PackageBuildClassObject(object):
self.Guids = {} self.Includes = [] self.LibraryClasses = {} self.Pcds = {} - ## Convert the class to a string- #- # Convert member MetaFile of the class to a string- #- # @retval string Formatted String- #- def __str__(self):- return str(self.MetaFile)-- ## Override __eq__ function- #- # Check whether PackageBuildClassObjects are the same- #- # @retval False The two PackageBuildClassObjects are different- # @retval True The two PackageBuildClassObjects are the same- #- def __eq__(self, Other):- return self.MetaFile == Other-- ## Override __hash__ function- #- # Use MetaFile as key in hash table- #- # @retval string Key for hash table- #- def __hash__(self):- return hash(self.MetaFile)- ## PlatformBuildClassObject # # This Class defines PlatformBuildClass # # @param object: Inherited from object class@@ -595,11 +602,11 @@ class PackageBuildClassObject(object):
# @var Pcds: To store value for Pcds, it is a set structure as # { [(PcdCName, PcdGuidCName)] : PcdClassObject } # @var BuildOptions: To store value for BuildOptions, it is a set structure as # { [BuildOptionKey] : BuildOptionValue } #-class PlatformBuildClassObject(object):+class PlatformBuildClassObject(BuildData): def __init__(self): self.MetaFile = '' self.PlatformName = '' self.Guid = '' self.Version = ''@@ -614,33 +621,5 @@ class PlatformBuildClassObject(object):
self.LibraryInstances = [] self.LibraryClasses = {} self.Libraries = {} self.Pcds = {} self.BuildOptions = {}-- ## Convert the class to a string- #- # Convert member MetaFile of the class to a string- #- # @retval string Formatted String- #- def __str__(self):- return str(self.MetaFile)-- ## Override __eq__ function- #- # Check whether PlatformBuildClassObjects are the same- #- # @retval False The two PlatformBuildClassObjects are different- # @retval True The two PlatformBuildClassObjects are the same- #- def __eq__(self, Other):- return self.MetaFile == Other-- ## Override __hash__ function- #- # Use MetaFile as key in hash table- #- # @retval string Key for hash table- #- def __hash__(self):- return hash(self.MetaFile)diff --git a/BaseTools/Source/Python/Workspace/DecBuildData.py b/BaseTools/Source/Python/Workspace/DecBuildData.py
index 30826a3cea..da7a52c5d0 100644
--- a/BaseTools/Source/Python/Workspace/DecBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DecBuildData.py
@@ -19,24 +19,10 @@ from re import compile
# # This class is used to retrieve information stored in database and convert them # into PackageBuildClassObject form for easier use for AutoGen. # class DecBuildData(PackageBuildClassObject):- # dict used to convert PCD type in database to string used by build tool- _PCD_TYPE_STRING_ = {- MODEL_PCD_FIXED_AT_BUILD : TAB_PCDS_FIXED_AT_BUILD,- MODEL_PCD_PATCHABLE_IN_MODULE : TAB_PCDS_PATCHABLE_IN_MODULE,- MODEL_PCD_FEATURE_FLAG : TAB_PCDS_FEATURE_FLAG,- MODEL_PCD_DYNAMIC : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_DEFAULT : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_HII : TAB_PCDS_DYNAMIC_HII,- MODEL_PCD_DYNAMIC_VPD : TAB_PCDS_DYNAMIC_VPD,- MODEL_PCD_DYNAMIC_EX : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_DEFAULT : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_HII : TAB_PCDS_DYNAMIC_EX_HII,- MODEL_PCD_DYNAMIC_EX_VPD : TAB_PCDS_DYNAMIC_EX_VPD,- } # dict used to convert part of [Defines] to members of DecBuildData directly _PROPERTY_ = { # # Required Fields@@ -66,10 +52,11 @@ class DecBuildData(PackageBuildClassObject):
self._Bdb = BuildDataBase self._Arch = Arch self._Target = Target self._Toolchain = Toolchain self._Clear()+ self.UpdatePcdTypeDict() ## XXX[key] = value def __setitem__(self, key, value): self.__dict__[self._PROPERTY_[key]] = value diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py b/BaseTools/Source/Python/Workspace/DscBuildData.py
index 5f07d3e75c..4d5b1ad4d9 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -177,24 +177,10 @@ def GetDependencyList(FileStack, SearchPathList):
DependencyList = list(DependencySet) # remove duplicate ones return DependencyList class DscBuildData(PlatformBuildClassObject):- # dict used to convert PCD type in database to string used by build tool- _PCD_TYPE_STRING_ = {- MODEL_PCD_FIXED_AT_BUILD : TAB_PCDS_FIXED_AT_BUILD,- MODEL_PCD_PATCHABLE_IN_MODULE : TAB_PCDS_PATCHABLE_IN_MODULE,- MODEL_PCD_FEATURE_FLAG : TAB_PCDS_FEATURE_FLAG,- MODEL_PCD_DYNAMIC : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_DEFAULT : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_HII : TAB_PCDS_DYNAMIC_HII,- MODEL_PCD_DYNAMIC_VPD : TAB_PCDS_DYNAMIC_VPD,- MODEL_PCD_DYNAMIC_EX : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_DEFAULT : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_HII : TAB_PCDS_DYNAMIC_EX_HII,- MODEL_PCD_DYNAMIC_EX_VPD : TAB_PCDS_DYNAMIC_EX_VPD,- } # dict used to convert part of [Defines] to members of DscBuildData directly _PROPERTY_ = { # # Required Fields@@ -240,11 +226,11 @@ class DscBuildData(PlatformBuildClassObject):
self._ToolChainFamily = None self._Clear() self.WorkspaceDir = os.getenv("WORKSPACE") if os.getenv("WORKSPACE") else "" self.DefaultStores = None self.SkuIdMgr = SkuClass(self.SkuName, self.SkuIds)-+ self.UpdatePcdTypeDict() @property def OutputPath(self): if os.getenv("WORKSPACE"): return os.path.join(os.getenv("WORKSPACE"), self.OutputDirectory, self._Target + "_" + self._Toolchain, PcdValueInitName) else:@@ -409,10 +395,13 @@ class DscBuildData(PlatformBuildClassObject):
try: uuid.UUID(Record[2]) except: EdkLogger.error("build", FORMAT_INVALID, "Invalid GUID format for VPD_TOOL_GUID", File=self.MetaFile) self._VpdToolGuid = Record[2]+ elif Name == TAB_DSC_DEFINES_PCD_DYNAMIC_AS_DYNAMICEX:+ if TAB_DSC_DEFINES_PCD_DYNAMIC_AS_DYNAMICEX not in gCommandLineDefines:+ gCommandLineDefines[TAB_DSC_DEFINES_PCD_DYNAMIC_AS_DYNAMICEX] = Record[2].strip() elif Name in self: self[Name] = Record[2] # set _Header to non-None in order to avoid database re-querying self._Header = 'DUMMY' diff --git a/BaseTools/Source/Python/Workspace/InfBuildData.py b/BaseTools/Source/Python/Workspace/InfBuildData.py
index 7675b0ea00..45b8ef4716 100644
--- a/BaseTools/Source/Python/Workspace/InfBuildData.py
+++ b/BaseTools/Source/Python/Workspace/InfBuildData.py
@@ -57,24 +57,10 @@ def _PpiValue(CName, PackageList, Inffile = None):
# # This class is used to retrieve information stored in database and convert them # into ModuleBuildClassObject form for easier use for AutoGen. # class InfBuildData(ModuleBuildClassObject):- # dict used to convert PCD type in database to string used by build tool- _PCD_TYPE_STRING_ = {- MODEL_PCD_FIXED_AT_BUILD : TAB_PCDS_FIXED_AT_BUILD,- MODEL_PCD_PATCHABLE_IN_MODULE : TAB_PCDS_PATCHABLE_IN_MODULE,- MODEL_PCD_FEATURE_FLAG : TAB_PCDS_FEATURE_FLAG,- MODEL_PCD_DYNAMIC : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_DEFAULT : TAB_PCDS_DYNAMIC,- MODEL_PCD_DYNAMIC_HII : TAB_PCDS_DYNAMIC_HII,- MODEL_PCD_DYNAMIC_VPD : TAB_PCDS_DYNAMIC_VPD,- MODEL_PCD_DYNAMIC_EX : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_DEFAULT : TAB_PCDS_DYNAMIC_EX,- MODEL_PCD_DYNAMIC_EX_HII : TAB_PCDS_DYNAMIC_EX_HII,- MODEL_PCD_DYNAMIC_EX_VPD : TAB_PCDS_DYNAMIC_EX_VPD,- } # dict used to convert part of [Defines] to members of InfBuildData directly _PROPERTY_ = { # # Required Fields@@ -152,10 +138,11 @@ class InfBuildData(ModuleBuildClassObject):
self._GuidsUsedByPcd = OrderedDict() self._GuidComments = None self._PcdComments = None self._BuildOptions = None self._DependencyFileList = None+ self.UpdatePcdTypeDict() self.LibInstances = [] self.ReferenceModules = set() def SetReferenceModule(self,Module): self.ReferenceModules.add(Module)--
2.29.1.windows.1



-=-=-=-=-=-=
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#76176): https://edk2.groups.io/g/devel/message/76176
Mute This Topic: https://groups.io/mt/83388055/1768742
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [bob.c.feng@intel.com] -=-=-=-=-=-=


Re: [PATCH v1 1/1] CryptoPkg: BaseCryptLib: Update Salt length requirement for RSA-PSS scheme.

Yao, Jiewen
 

Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

-----Original Message-----
From: Agrawal, Sachin <sachin.agrawal@intel.com>
Sent: Monday, June 14, 2021 11:31 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>;
Lu, XiaoyuX <xiaoyux.lu@intel.com>; Jiang, Guomin <guomin.jiang@intel.com>
Subject: [PATCH v1 1/1] CryptoPkg: BaseCryptLib: Update Salt length
requirement for RSA-PSS scheme.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3455

Enforce salt length to be equal to digest length for RSA-PSS
encoding scheme.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>

Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
---
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c | 4 ++--
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssNull.c | 2 +-
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c | 4 ++--
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSignNull.c | 2 +-
CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssNull.c | 2 +-
CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssSignNull.c | 2 +-
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c | 10 +++++++++-
CryptoPkg/Include/Library/BaseCryptLib.h | 4 ++--
CryptoPkg/Private/Protocol/Crypto.h | 4 ++--
9 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
index 0b2960f06c4c..37075ea65a0d 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
@@ -50,7 +50,7 @@ GetEvpMD (
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
@@ -97,7 +97,7 @@ RsaPssVerify (
if (Signature == NULL || SigSize == 0 || SigSize > INT_MAX) {
return FALSE;
}
- if (SaltLen < DigestLen) {
+ if (SaltLen != DigestLen) {
return FALSE;
}

diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssNull.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssNull.c
index 69c6889fbc4b..cc325c92911c 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssNull.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssNull.c
@@ -15,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
index ece765f9ae0a..06187ff4baa7 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
@@ -59,7 +59,7 @@ GetEvpMD (
If Message is NULL, then return FALSE.
If MsgSize is zero or > INT_MAX, then return FALSE.
If DigestLen is NOT 32, 48 or 64, return FALSE.
- If SaltLen is < DigestLen, then return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
If SigSize is large enough but Signature is NULL, then return FALSE.
If this interface is not supported, then return FALSE.

@@ -120,7 +120,7 @@ RsaPssSign (
return FALSE;
}

- if (SaltLen < DigestLen) {
+ if (SaltLen != DigestLen) {
return FALSE;
}

diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSignNull.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSignNull.c
index 4ed2dfce992a..911b97252182 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSignNull.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSignNull.c
@@ -24,7 +24,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
If Message is NULL, then return FALSE.
If MsgSize is zero or > INT_MAX, then return FALSE.
If DigestLen is NOT 32, 48 or 64, return FALSE.
- If SaltLen is < DigestLen, then return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
If SigSize is large enough but Signature is NULL, then return FALSE.
If this interface is not supported, then return FALSE.

diff --git a/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssNull.c
b/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssNull.c
index 69c6889fbc4b..cc325c92911c 100644
--- a/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssNull.c
+++ b/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssNull.c
@@ -15,7 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
diff --git a/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssSignNull.c
b/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssSignNull.c
index 4ed2dfce992a..911b97252182 100644
--- a/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssSignNull.c
+++ b/CryptoPkg/Library/BaseCryptLibNull/Pk/CryptRsaPssSignNull.c
@@ -24,7 +24,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
If Message is NULL, then return FALSE.
If MsgSize is zero or > INT_MAX, then return FALSE.
If DigestLen is NOT 32, 48 or 64, return FALSE.
- If SaltLen is < DigestLen, then return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
If SigSize is large enough but Signature is NULL, then return FALSE.
If this interface is not supported, then return FALSE.

diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c
b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c
index af99ed7f5b42..fcb59137805b 100644
--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c
+++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/CryptLib.c
@@ -1556,7 +1556,7 @@ RsaPkcs1Verify (
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
@@ -1592,6 +1592,14 @@ RsaPssVerify (
If the Signature buffer is too small to hold the contents of signature, FALSE
is returned and SigSize is set to the required buffer size to obtain the signature.

+ If RsaContext is NULL, then return FALSE.
+ If Message is NULL, then return FALSE.
+ If MsgSize is zero or > INT_MAX, then return FALSE.
+ If DigestLen is NOT 32, 48 or 64, return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
+ If SigSize is large enough but Signature is NULL, then return FALSE.
+ If this interface is not supported, then return FALSE.
+
@param[in] RsaContext Pointer to RSA context for signature generation.
@param[in] Message Pointer to octet message to be signed.
@param[in] MsgSize Size of the message in bytes.
diff --git a/CryptoPkg/Include/Library/BaseCryptLib.h
b/CryptoPkg/Include/Library/BaseCryptLib.h
index 8c7d5922ef96..630ccb5e7500 100644
--- a/CryptoPkg/Include/Library/BaseCryptLib.h
+++ b/CryptoPkg/Include/Library/BaseCryptLib.h
@@ -1376,7 +1376,7 @@ RsaPkcs1Verify (
If Message is NULL, then return FALSE.
If MsgSize is zero or > INT_MAX, then return FALSE.
If DigestLen is NOT 32, 48 or 64, return FALSE.
- If SaltLen is < DigestLen, then return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
If SigSize is large enough but Signature is NULL, then return FALSE.
If this interface is not supported, then return FALSE.

@@ -1411,7 +1411,7 @@ RsaPssSign (
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
diff --git a/CryptoPkg/Private/Protocol/Crypto.h
b/CryptoPkg/Private/Protocol/Crypto.h
index e304302c9445..498f8e387dba 100644
--- a/CryptoPkg/Private/Protocol/Crypto.h
+++ b/CryptoPkg/Private/Protocol/Crypto.h
@@ -3421,7 +3421,7 @@ EFI_STATUS
If Message is NULL, then return FALSE.
If MsgSize is zero or > INT_MAX, then return FALSE.
If DigestLen is NOT 32, 48 or 64, return FALSE.
- If SaltLen is < DigestLen, then return FALSE.
+ If SaltLen is not equal to DigestLen, then return FALSE.
If SigSize is large enough but Signature is NULL, then return FALSE.
If this interface is not supported, then return FALSE.

@@ -3456,7 +3456,7 @@ BOOLEAN
Verifies the RSA signature with RSASSA-PSS signature scheme defined in RFC
8017.
Implementation determines salt length automatically from the signature
encoding.
Mask generation function is the same as the message digest algorithm.
- Salt length should atleast be equal to digest length.
+ Salt length should be equal to digest length.

@param[in] RsaContext Pointer to RSA context for signature verification.
@param[in] Message Pointer to octet message to be verified.
--
2.14.3.windows.1


Re: [PATCH v1 3/5] MdeModulePkg: MemoryProfileInfo: Updated MessageLength calculation

Wu, Hao A
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kun Qin
Sent: Saturday, June 12, 2021 5:30 AM
To: Wu, Hao A <hao.a.wu@intel.com>; devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>
Subject: Re: [edk2-devel] [PATCH v1 3/5] MdeModulePkg: MemoryProfileInfo:
Updated MessageLength calculation

Hi Hao,

Thanks for pointing out the missing place. Will update this accordingly.

This patch series needs a PI spec update, I thought I should mark all changes
with BZ#### before the spec update is taken. But I can drop them for the next
patch version.

Thanks a lot.
Please also help to check my other comments sent previously for other patches in the series.

Best Regards,
Hao Wu



Regards,
Kun

On 06/11/2021 00:46, Wu, Hao A wrote:
-----Original Message-----
From: Kun Qin <kuqin12@gmail.com>
Sent: Thursday, June 10, 2021 9:43 AM
To: devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A
<hao.a.wu@intel.com>
Subject: [PATCH v1 3/5] MdeModulePkg: MemoryProfileInfo: Updated
MessageLength calculation

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3398

This change replaced the calculation of communication buffer size
from explicitly adding the size of each member with the OFFSET macro
function.
This will make the structure field defition change transparent to consumers.

I think there is one missing place in function GetSmramProfileData():

MinimalSizeNeeded = sizeof (EFI_GUID) +
sizeof (UINTN) +
MAX (sizeof (SMRAM_PROFILE_PARAMETER_GET_PROFILE_INFO),
MAX (sizeof
(SMRAM_PROFILE_PARAMETER_GET_PROFILE_DATA_BY_OFFSET),
sizeof
(SMRAM_PROFILE_PARAMETER_RECORDING_STATE)));

More inline comments below:



Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
---
MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.c | 20
+++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)

diff --git
a/MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.c
b/MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.c
index 191c31068545..39ed8b2e0484 100644
--- a/MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.c
+++
b/MdeModulePkg/Application/MemoryProfileInfo/MemoryProfileInfo.c
@@ -1190,7 +1190,9 @@ GetSmramProfileData (
CommRecordingState->Header.ReturnStatus = (UINT64)-1;
CommRecordingState->RecordingState =
MEMORY_PROFILE_RECORDING_DISABLE;

- CommSize = sizeof (EFI_GUID) + sizeof (UINTN) + CommHeader-
MessageLength;
+ // BZ3398: Make MessageLength the same size in
EFI_MM_COMMUNICATE_HEADER for both IA32 and X64.
+ // The CommHeader->MessageLength contains a definitive value, thus
UINTN cast is safe here.

Please help to drop the explicit mention of BZ3398 in the comment.
How about using:
//
// The CommHeader->MessageLength contains a definitive value, thus
UINTN cast is safe here.
//

There are 4 more similar cases below.

Best Regards,
Hao Wu


+ CommSize = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) +
+ (UINTN)CommHeader->MessageLength;
Status = SmmCommunication->Communicate (SmmCommunication,
CommBuffer, &CommSize);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "SmramProfile: SmmCommunication - %r\n",
Status)); @@ -1213,7 +1215,9 @@ GetSmramProfileData (
CommRecordingState->Header.ReturnStatus = (UINT64)-1;
CommRecordingState->RecordingState =
MEMORY_PROFILE_RECORDING_DISABLE;

- CommSize = sizeof (EFI_GUID) + sizeof (UINTN) + CommHeader-
MessageLength;
+ // BZ3398: Make MessageLength the same size in
EFI_MM_COMMUNICATE_HEADER for both IA32 and X64.
+ // The CommHeader->MessageLength contains a definitive value,
+ thus
UINTN cast is safe here.
+ CommSize = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) +
+ (UINTN)CommHeader->MessageLength;
SmmCommunication->Communicate (SmmCommunication, CommBuffer,
&CommSize);
}

@@ -1230,7 +1234,9 @@ GetSmramProfileData (
CommGetProfileInfo->Header.ReturnStatus = (UINT64)-1;
CommGetProfileInfo->ProfileSize = 0;

- CommSize = sizeof (EFI_GUID) + sizeof (UINTN) + CommHeader-
MessageLength;
+ // BZ3398: Make MessageLength the same size in
EFI_MM_COMMUNICATE_HEADER for both IA32 and X64.
+ // The CommHeader->MessageLength contains a definitive value, thus
UINTN cast is safe here.
+ CommSize = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) +
+ (UINTN)CommHeader->MessageLength;
Status = SmmCommunication->Communicate (SmmCommunication,
CommBuffer, &CommSize);
ASSERT_EFI_ERROR (Status);

@@ -1261,7 +1267,9 @@ GetSmramProfileData (
CommGetProfileData->Header.DataLength = sizeof
(*CommGetProfileData);
CommGetProfileData->Header.ReturnStatus = (UINT64)-1;

- CommSize = sizeof (EFI_GUID) + sizeof (UINTN) + CommHeader-
MessageLength;
+ // BZ3398: Make MessageLength the same size in
EFI_MM_COMMUNICATE_HEADER for both IA32 and X64.
+ // The CommHeader->MessageLength contains a definitive value, thus
UINTN cast is safe here.
+ CommSize = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) +
+ (UINTN)CommHeader->MessageLength;
Buffer = (UINT8 *) CommHeader + CommSize;
Size -= CommSize;

@@ -1320,7 +1328,9 @@ GetSmramProfileData (
CommRecordingState->Header.ReturnStatus = (UINT64)-1;
CommRecordingState->RecordingState =
MEMORY_PROFILE_RECORDING_ENABLE;

- CommSize = sizeof (EFI_GUID) + sizeof (UINTN) + CommHeader-
MessageLength;
+ // BZ3398: Make MessageLength the same size in
EFI_MM_COMMUNICATE_HEADER for both IA32 and X64.
+ // The CommHeader->MessageLength contains a definitive value,
+ thus
UINTN cast is safe here.
+ CommSize = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) +
+ (UINTN)CommHeader->MessageLength;
SmmCommunication->Communicate (SmmCommunication, CommBuffer,
&CommSize);
}

--
2.31.1.windows.1



Re: [edk2-platforms PATCH 0/4] ACPI MDIO support for Marvell SoCs

Leif Lindholm
 

Hi Marcin,

On Sun, Jun 13, 2021 at 20:16:27 +0200, Marcin Wojtas wrote:
Hi,

The MDIO ACPI binding has been established and merged to the
Linux tree,
Congratulations! :)

Is FreeBSD expected to follow suit?

hence it is now possible to update the ACPI
description of the platforms that base on the Marvell SoCs.

For convenience, the code is exposed in the public github branch:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/acpi-mdio-r20210613
There is also MacchiatoBin firmware binary avaialable for testing:
https://drive.google.com/file/d/1eigP_aeM4wYQpEaLAlQzs3IN_w1-kQr0

I'm looking forward to the comments or remarks.
The patches themselves look straightforward enough.
I *would* prefer some tested-by, for these sources rather than the
binary, before merging though.

Best Regards,

Leif

Best regards,
Marcin

Marcin Wojtas (4):
SolidRun/Armada80x0McBin: Add ACPI MDIO description
Marvell/Cn913xDb: Add ACPI MDIO description
Marvell/Armada70x0Db: Add ACPI MDIO description
Marvell/Armada80x0Db: Add ACPI MDIO description

Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 24 +++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 38 ++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 53 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 1 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 24 +++++++++
5 files changed, 140 insertions(+)

--
2.29.0


Re: [PATCH V1 4/4] Platform/NXP/LS1046aFrwyPkg: Add OEM specific DSDT generator

Leif Lindholm
 

On Fri, Jun 11, 2021 at 21:22:00 +0530, Vikas Singh wrote:
This patch adds platform specific DSDT generator
and Clk dsdt properties for LS1046AFRWY platform.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl | 60 +++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl | 15 +++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf | 39 ++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c | 138 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h | 23 ++++
Platform/NXP/LS1046aFrwyPkg/Include/Platform.h | 6 +-
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 1 +
7 files changed, 281 insertions(+), 1 deletion(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
new file mode 100644
index 0000000000..58541c3019
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
@@ -0,0 +1,60 @@
+/** @file
+* DSDT : Dynamic Clock ACPI Information
+*
+* Copyright 2021 NXP
+* Copyright 2021 Puresoftware Ltd.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+Scope(_SB)
+{
+ Device(PCLK) {
+ Name(_HID, "NXP0017")
+ Name(CLK, 0) // Maximum Platform Clock (Hz)
+ Name(CCLK, 0) // Maximum CPU Core Clock (MHz)
+ Name(AVBL, 0)
+ OperationRegion(RCWS, SystemMemory, DCFG_BASE, DCFG_LEN)
+ Method(_REG,2) {
+ if (Arg0 == "RCWS") {
+ Store(Arg1, AVBL)
+ }
+ }
+ Field (RCWS, ByteAcc, NoLock, Preserve) {
+ /* The below table provides the func of diff bits in 512 bits RCW data:
+ SYS_PLL_CFG : 0-1 bits
+ SYS_PLL_RAT : 2-6 bits
+ SYSCLK_FREQ : 472-481 bits etc.
+ Refer LS1046ARM for more info.
+ For LS1046 RCWSRs are read as RCW[0:31] .
+ */
+ offset(0x100),
+ RESV, 1,
+ PRAT, 5,
+ PCFG, 2,
+ offset(0x103),
+ CPRT, 6, // Cluster Group PLL Multiplier ratio
+ offset(0x13B),
+ HFRQ, 8, // Higher 8 bits of SYSCLK_FREQ
+ RESX, 6,
+ LFRQ, 2 // Lower bits of SYSCLK_FREQ
+ }
+
+ Method(_INI, 0, NotSerialized) {
+ /* Calculating Platform Clock */
+ Local0 = (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ
+ Multiply(Local0, 500000, Local0)
+ Multiply(Local0, PRAT, Local0)
+ Divide(Local0, 3, , Local0)
+ Store(Local0, CLK)
+
+ /* Calculating Maximum Core Clock */
+ Local0 = (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ
+ Multiply(Local0, 500000, Local0)
+ Divide(Local0, 3, , Local0)
+ Divide(Local0, 1000000, , Local0) //Just the MHz part of SYSCLK.
+ Multiply(Local0, CPRT, CCLK) // PLL_Ratio * SYSCLK, Max freq of cluster
+ }
+ } // end of device PCLK
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..19f3f1c0e8
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
@@ -0,0 +1,15 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright 2021 NXP
+ Copyright 2021 Puresoftware Ltd.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "NXP ", "LS1046 ", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Clk.asl")
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
new file mode 100644
index 0000000000..ed5f9dd442
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
@@ -0,0 +1,39 @@
+## @file
+# Raw Table Generator
+#
+# Copyright 2021 NXP
+# Copyright 2021 Puresoftware Ltd
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PlatformAcpiDsdtLib
+ FILE_GUID = A97F70AC-3BB4-4596-B4D2-9F948EC12D17
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = NULL|DXE_DRIVER
+ CONSTRUCTOR = AcpiDsdtLibConstructor
+ DESTRUCTOR = AcpiDsdtLibDestructor
+
+[Sources]
+ PlatformAcpiDsdtLib/RawDsdtGenerator.c
+ Dsdt/Dsdt.asl
+
+[Packages]
+ DynamicTablesPkg/DynamicTablesPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerPkg.dec
+
+[LibraryClasses]
+ BaseLib
+
+[Pcd]
+
+[Protocols]
+
+[Guids]
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c
new file mode 100644
index 0000000000..7d886396ca
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/RawDsdtGenerator.c
@@ -0,0 +1,138 @@
+/** @file
+ Raw DSDT Table Generator
+
+ Copyright 2021 NXP
+ Copyright 2021 Puresoftware Ltd.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/AcpiTable.h>
+
+// Module specific include files.
+#include <AcpiTableGenerator.h>
+#include <ConfigurationManagerObject.h>
+#include <ConfigurationManagerHelper.h>
+#include <Library/TableHelperLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "PlatformAcpiLib.h"
+
+/** Construct the ACPI table using the ACPI table data provided.
+ This function invokes the Configuration Manager protocol interface
+ to get the required hardware information for generating the ACPI
+ table.
+ If this function allocates any resources then they must be freed
+ in the FreeXXXXTableResources function.
+ @param [in] This Pointer to the table generator.
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [out] Table Pointer to the constructed ACPI Table.
+ @retval EFI_SUCCESS Table generated successfully.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+BuildRawDsdtTable (
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ OUT EFI_ACPI_DESCRIPTION_HEADER ** CONST Table
+ )
+{
+ ASSERT (This != NULL);
+ ASSERT (AcpiTableInfo != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (Table != NULL);
+ ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+
+ if (AcpiTableInfo->AcpiTableData == NULL) {
+ // Add the dsdt aml code here.
+ *Table = (EFI_ACPI_DESCRIPTION_HEADER *)&dsdt_aml_code;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/** This macro defines the Raw Generator revision.
+*/
+#define DSDT_GENERATOR_REVISION CREATE_REVISION (1, 0)
+
+/** The interface for the Raw Table Generator.
+*/
+STATIC
+CONST
+ACPI_TABLE_GENERATOR RawDsdtGenerator = {
+ // Generator ID
+ CREATE_OEM_ACPI_TABLE_GEN_ID (PlatAcpiTableIdDsdt),
+ // Generator Description
+ L"ACPI.OEM.RAW.DSDT.GENERATOR",
+ // ACPI Table Signature - Unused
+ 0,
+ // ACPI Table Revision - Unused
+ 0,
+ // Minimum ACPI Table Revision - Unused
+ 0,
+ // Creator ID
+ TABLE_GENERATOR_CREATOR_ID_ARM,
+ // Creator Revision
+ DSDT_GENERATOR_REVISION,
+ // Build Table function
+ BuildRawDsdtTable,
+ // No additional resources are allocated by the generator.
+ // Hence the Free Resource function is not required.
+ NULL,
+ // Extended build function not needed
+ NULL,
+ // Extended build function not implemented by the generator.
+ // Hence extended free resource function is not required.
+ NULL
+};
+
+/** Register the Generator with the ACPI Table Factory.
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+ @retval EFI_SUCCESS The Generator is registered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_ALREADY_STARTED The Generator for the Table ID
+ is already registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiDsdtLibConstructor (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * CONST SystemTable
+ )
+{
+ EFI_STATUS Status;
+ Status = RegisterAcpiTableGenerator (&RawDsdtGenerator);
+ DEBUG ((DEBUG_INFO, "OEM: Register DSDT Generator. Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+/** Deregister the Generator from the ACPI Table Factory.
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+ @retval EFI_SUCCESS The Generator is deregistered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The Generator is not registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiDsdtLibDestructor (
+ IN CONST EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * CONST SystemTable
+ )
+{
+ EFI_STATUS Status;
+ Status = DeregisterAcpiTableGenerator (&RawDsdtGenerator);
+ DEBUG ((DEBUG_INFO, "OEM: Deregister DSDT Generator. Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
new file mode 100644
index 0000000000..e5f907a7d4
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
@@ -0,0 +1,23 @@
+/** @file
+ * Acpi lib headers
+ *
+ * Copyright 2021 NXP
+ * Copyright 2021 Puresoftware Ltd
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+**/
+
+
+#ifndef LS1046AFRWY_PLATFORM_ACPI_LIB_H
+#define LS1046AFRWY_PLATFORM_ACPI_LIB_H
+
+#include <PlatformAcpiTableGenerator.h>
+
+/** C array containing the compiled AML template.
+ These symbols are defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 dsdt_aml_code[];
+
+#endif
diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
index 19e879ec6d..b21e875f20 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -20,6 +20,10 @@
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)

+// PCLK : Dynamic Clock
+#define DCFG_BASE 0x1EE0000 /* Device configuration data Base Address */
+#define DCFG_LEN 0xFFF /* Device configuration data length */
+

// Gic
#define GIC_VERSION 2
#define GICD_BASE 0x1410000
@@ -62,7 +66,7 @@
#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')

// Specify the OEM defined tables
-#define OEM_ACPI_TABLES 0
+#define OEM_ACPI_TABLES 1 // Added DSDT
Drop the comment.
With that:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>



#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0
#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 20111e6037..7041d15da5 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -65,6 +65,7 @@
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibArm.inf
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibArm.inf
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibArm.inf
+ NULL|Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
}
!endif

--
2.25.1


Re: [PATCH V1 3/4] Platform/NXP/LS1046aFrwyPkg: Extend Dynamic ACPI support

Leif Lindholm
 

On Fri, Jun 11, 2021 at 21:21:59 +0530, Vikas Singh wrote:
This patch set extends Configuration Manager (CM) and
its services to leverage the Dynamic ACPI support for
NXP's LS1046aFrwy platform.
This patch does not touch ConfigurationManager.
Please describe what this patch does.

My guess is it's along the lines of:
This set enables use of the ConfigurationManager framework for the
LS1046aFrwy platform.

Refer-https://edk2.groups.io/g/devel/message/71710
That is a 1326-line patch set.
What is this reference supposed to tell me?

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/LS1046aFrwyPkg/Include/Platform.h | 155 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 28 ++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 10 ++
4 files changed, 206 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
new file mode 100644
index 0000000000..19e879ec6d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -0,0 +1,155 @@
+/** @file
+ * Platform headers
+ *
+ * Copyright 2021 NXP
+ * Copyright 2021 Puresoftware Ltd
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+**/
+
+
+#ifndef LS1046AFRWY_PLATFORM_H
+#define LS1046AFRWY_PLATFORM_H
+
+#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
+
+// Soc defines
+#define PLAT_SOC_NAME "LS1046AFRWY"
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
We already have three identical copies of these three macros:
Platform/NXP/LX2160aRdbPkg/Include/Platform.h
Silicon/NXP/Chassis2/Include/Chassis.h
Silicon/NXP/Chassis3V2/Include/Chassis.h

Could they be defined once, in a single common header, rather than
adding a fourth one?

+
+// Gic
+#define GIC_VERSION 2
+#define GICD_BASE 0x1410000
+#define GICC_BASE 0x142f000
+#define GICH_BASE 0x1440000
+#define GICV_BASE 0x1460000
+
+// UART
+#define UART0_BASE 0x21C0500
+#define UART0_IT 86
These (GIC and UART) definitions duplicate things already described in
Silicon/NXP/LS1046A/LS1046A.dsc.inc

/
Leif

+#define UART0_LENGTH 0x100
+#define SPCR_FLOW_CONTROL_NONE 0
+
+// Timer
+#define TIMER_BLOCK_COUNT 1
+#define TIMER_FRAME_COUNT 4
+#define TIMER_WATCHDOG_COUNT 1
+#define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase
+#define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase
+#define TIMER_SEC_IT 29
+#define TIMER_NON_SEC_IT 30
+#define TIMER_VIRT_IT 27
+#define TIMER_HYP_IT 26
+#define TIMER_FRAME0_IT 78
+#define TIMER_FRAME1_IT 79
+#define TIMER_FRAME2_IT 92
+
+// Mcfg
+#define LS1046A_PCI_SEG0_CONFIG_BASE 0x4000000000
+#define LS1046A_PCI_SEG0 0x0
+#define LS1046A_PCI_SEG_BUSNUM_MIN 0x0
+#define LS1046A_PCI_SEG_BUSNUM_MAX 0xff
+#define LS1046A_PCI_SEG1_CONFIG_BASE 0x4800000000
+#define LS1046A_PCI_SEG2_CONFIG_BASE 0x5000000000
+#define LS1046A_PCI_SEG1 0x1
+#define LS1046A_PCI_SEG2 0x2
+
+// Platform specific info needed by Configuration Manager
+
+#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')
+
+// Specify the OEM defined tables
+#define OEM_ACPI_TABLES 0
+
+#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0
+#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE
+#define PLAT_PCI_SEG1 LS1046A_PCI_SEG1
+#define PLAT_PCI_SEG_BUSNUM_MIN LS1046A_PCI_SEG_BUSNUM_MIN
+#define PLAT_PCI_SEG_BUSNUM_MAX LS1046A_PCI_SEG_BUSNUM_MAX
+#define PLAT_PCI_SEG2_CONFIG_BASE LS1046A_PCI_SEG2_CONFIG_BASE
+#define PLAT_PCI_SEG2 LS1046A_PCI_SEG2
+
+#define PLAT_GIC_VERSION GIC_VERSION
+#define PLAT_GICD_BASE GICD_BASE
+#define PLAT_GICI_BASE GICI_BASE
+#define PLAT_GICR_BASE GICR_BASE
+#define PLAT_GICR_LEN GICR_LEN
+#define PLAT_GICC_BASE GICC_BASE
+#define PLAT_GICH_BASE GICH_BASE
+#define PLAT_GICV_BASE GICV_BASE
+
+#define PLAT_CPU_COUNT 4
+#define PLAT_GTBLOCK_COUNT 0
+#define PLAT_GTFRAME_COUNT 0
+#define PLAT_PCI_CONFG_COUNT 2
+
+#define PLAT_WATCHDOG_COUNT 0
+#define PLAT_GIC_REDISTRIBUTOR_COUNT 0
+#define PLAT_GIC_ITS_COUNT 0
+
+/* GIC CPU Interface information
+ GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency)
+ */
+#define PLAT_GIC_CPU_INTERFACE { \
+ GICC_ENTRY (0, GET_MPID (0, 0), 138, 0x19, 0), \
+ GICC_ENTRY (1, GET_MPID (0, 1), 139, 0x19, 0), \
+ GICC_ENTRY (2, GET_MPID (0, 2), 127, 0x19, 0), \
+ GICC_ENTRY (3, GET_MPID (0, 3), 129, 0x19, 0), \
+}
+
+#define PLAT_WATCHDOG_INFO \
+ { \
+ } \
+
+#define PLAT_TIMER_BLOCK_INFO \
+ { \
+ } \
+
+#define PLAT_TIMER_FRAME_INFO \
+ { \
+ } \
+
+#define PLAT_GIC_DISTRIBUTOR_INFO \
+ { \
+ PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \
+ 0, /* UINT32 SystemVectorBase */ \
+ PLAT_GIC_VERSION /* UINT8 GicVersion */ \
+ } \
+
+#define PLAT_GIC_REDISTRIBUTOR_INFO \
+ { \
+ } \
+
+#define PLAT_GIC_ITS_INFO \
+ { \
+ } \
+
+#define PLAT_MCFG_INFO \
+ { \
+ { \
+ PLAT_PCI_SEG1_CONFIG_BASE, \
+ PLAT_PCI_SEG1, \
+ PLAT_PCI_SEG_BUSNUM_MIN, \
+ PLAT_PCI_SEG_BUSNUM_MAX, \
+ }, \
+ { \
+ PLAT_PCI_SEG2_CONFIG_BASE, \
+ PLAT_PCI_SEG2, \
+ PLAT_PCI_SEG_BUSNUM_MIN, \
+ PLAT_PCI_SEG_BUSNUM_MAX, \
+ } \
+ } \
+
+#define PLAT_SPCR_INFO \
+ { \
+ UART0_BASE, \
+ UART0_IT, \
+ 115200, \
+ 0, \
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 \
+ } \
+
+#endif // LS1046AFRWY_PLATFORM_H
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 67cf15cbe4..20111e6037 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -3,6 +3,7 @@
# LS1046AFRWY Board package.
#
# Copyright 2019-2020 NXP
+# Copyright 2021 Puresoftware Ltd
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,10 +23,18 @@
OUTPUT_DIRECTORY = Build/LS1046aFrwyPkg
FLASH_DEFINITION = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf

+ # This flag controls the dynamic acpi generation
+ #
+ DEFINE DYNAMIC_ACPI_ENABLE = TRUE
+
!include Silicon/NXP/NxpQoriqLs.dsc.inc
!include MdePkg/MdeLibs.dsc.inc
!include Silicon/NXP/LS1046A/LS1046A.dsc.inc

+!if $(DYNAMIC_ACPI_ENABLE) == TRUE
+ !include DynamicTablesPkg/DynamicTables.dsc.inc
+!endif
+
[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
@@ -46,4 +55,23 @@

Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf

+ #
+ # Dynamic Table Factory
+ !if $(DYNAMIC_ACPI_ENABLE) == TRUE
+ DynamicTablesPkg/Drivers/DynamicTableFactoryDxe/DynamicTableFactoryDxe.inf {
+ <LibraryClasses>
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/AcpiFadtLibArm.inf
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiGtdtLibArm/AcpiGtdtLibArm.inf
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibArm.inf
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibArm.inf
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibArm.inf
+ }
+ !endif
+
+ #
+ # Acpi Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 34c4e5a025..f3cac033bc 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -3,6 +3,7 @@
# FLASH layout file for LS1046a board.
#
# Copyright 2019-2020 NXP
+# Copyright 2021 Puresoftware Ltd
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -99,6 +100,18 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Metronome/Metronome.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+
+ #
+ # Acpi Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ !if $(DYNAMIC_ACPI_ENABLE) == TRUE
+ INF Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+ !include DynamicTablesPkg/DynamicTables.fdf.inc
+ !endif
+
#
# Multiple Console IO support
#
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 7004533ed5..98f999edfd 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -2,6 +2,7 @@
# LS1046A Soc package.
#
# Copyright 2017-2020 NXP
+# Copyright 2021 Puresoftware Ltd
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -48,4 +49,13 @@
[Components.common]
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf

+#
+# Configuration Manager
+!if $(DYNAMIC_ACPI_ENABLE) == TRUE
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManagerDxe.inf {
+ <BuildOptions>
+ *_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Platform/NXP/LS1046aFrwyPkg/Include
+ }
+!endif
+
##
--
2.25.1


Re: [PATCH V1 2/4] Silicon/NXP: Add support of SVR handling for LS1046FRWY

Leif Lindholm
 

On Fri, Jun 11, 2021 at 21:21:58 +0530, Vikas Singh wrote:
This change set intend to add a generic method to get
Does it intend to add, or does it add?

/
Leif

access to SoC's Silicon Version Register (SVR) and its
handling for LS1046aFrwy platform.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 8fa6a7dd00..003f5bd82f 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -2,6 +2,7 @@
SoC specific Library containg functions to initialize various SoC components

Copyright 2017-2020 NXP
+ Copyright 2021 Puresoftware Ltd

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -64,6 +65,21 @@ SocGetClock (
return ReturnValue;
}

+/**
+ Function to get SoC's System Version Register(SVR)
+ **/
+UINT32
+SocGetSvr (
+ VOID
+ )
+{
+ LS1046A_DEVICE_CONFIG *Dcfg;
+
+ Dcfg = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+
+ return DcfgRead32 ((UINTN)&Dcfg->Svr);
+}
+
/**
Function to select pins depending upon pcd using supplemental
configuration unit(SCFG) extended RCW controlled pinmux control
--
2.25.1


Re: [PATCH V1 1/4] Platform/NXP: Add generic log in CM to print SoC version

Leif Lindholm
 

On Fri, Jun 11, 2021 at 21:21:57 +0530, Vikas Singh wrote:
Summary -
1.Configuration Manager(CM) is a common implementation
and should not evaluate the SoC version using macro's
However CM must directly consume SoC ver string from
platfrom who is extending CM services for ACPI table
generation.
This tells me nothing about what this patch does.

2.Platforms who extends CM services for themselves must
notify their SoC details to CM.
Neither does this.

3.This patch will update the lx2160ardb platform header
also with PLAT_SOC_NAME, this will be consumed by CM.
And this sound like it should be a separate patch.

*However* when I look at the code, this does look like a single
change. And what is descibed as point 3 is the actual change in the patch.
Moreover, this patch addresses a historic horror, in that SVR_LX2160A
was defined both in the platform header and in the SoC header (which
I'm not saying you had necessarily noticed, but I am suggesting it is
added to the message).

If I wrote this commit message, I would start with a slightly tweaked
subject line:

Platform/NXP: Make SoC version log in ConfigurationManager generic

(CM is not a recognised abbreviation, so should be printed expanded)

As for the body, I would say something like:

This patch replaces the logic in ConfigurationManager to print
platform name based on platform ID with a simple #define.
This also removes a duplication of the SVR_LX2160A definition between
SoC and platform headers.

No comments on the code itself.

/
Leif

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c | 10 +++-------
Platform/NXP/LX2160aRdbPkg/Include/Platform.h | 5 ++---
2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c
index 80ce8412c4..dc1a7f5f85 100644
--- a/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/ConfigurationManager.c
@@ -2,7 +2,7 @@
Configuration Manager Dxe

Copyright 2020 NXP
- Copyright 2020 Puresoftware Ltd
+ Copyright 2020-2021 Puresoftware Ltd

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -170,12 +170,8 @@ InitializePlatformRepository (
PlatformRepo = This->PlatRepoInfo;

Svr = SocGetSvr ();
- if (SVR_SOC_VER(Svr) == SVR_LX2160A) {
- PlatformRepo->FslBoardRevision = SVR_MAJOR(Svr);
- DEBUG ((DEBUG_INFO, "Fsl : SoC LX2160A Rev = 0x%x\n", PlatformRepo->FslBoardRevision));
- } else {
- DEBUG ((DEBUG_INFO, "Fsl : SoC Unknown Rev = 0x%x\n", PlatformRepo->FslBoardRevision));
- }
+ PlatformRepo->FslBoardRevision = SVR_MAJOR(Svr);
+ DEBUG ((DEBUG_INFO, "Fsl : SoC = %s Rev = 0x%x\n", PLAT_SOC_NAME, PlatformRepo->FslBoardRevision));

return EFI_SUCCESS;
}
diff --git a/Platform/NXP/LX2160aRdbPkg/Include/Platform.h b/Platform/NXP/LX2160aRdbPkg/Include/Platform.h
index 76a41d4369..c18faf28cd 100644
--- a/Platform/NXP/LX2160aRdbPkg/Include/Platform.h
+++ b/Platform/NXP/LX2160aRdbPkg/Include/Platform.h
@@ -2,7 +2,7 @@
* Platform headers
*
* Copyright 2020 NXP
- * Copyright 2020 Puresoftware Ltd
+ * Copyright 2020-2021 Puresoftware Ltd
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -15,12 +15,11 @@
#define EFI_ACPI_ARM_OEM_REVISION 0x00000000

// Soc defines
+#define PLAT_SOC_NAME "LX2160ARDB"
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)

-#define SVR_LX2160A 0x873600
-
// PCLK
#define DCFG_BASE 0x1E00000
#define DCFG_LEN 0x1FFFF
--
2.25.1


[PATCH v2 1/1] ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h

Rebecca Cran
 

Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
ArmPkg/Include/IndustryStandard/ArmCache.h | 112 ++++++++++++++++++
ArmPkg/Include/Library/ArmLib.h | 36 +++++-
ArmPkg/Library/ArmLib/ArmLibPrivate.h | 123 --------------------
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 2 +-
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c | 2 +-
7 files changed, 148 insertions(+), 131 deletions(-)

diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h
new file mode 100644
index 000000000000..f9de46b5bffd
--- /dev/null
+++ b/ArmPkg/Include/IndustryStandard/ArmCache.h
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_CACHE_H_
+#define ARM_CACHE_H_
+
+#include <Uefi/UefiBaseType.h>
+
+// The ARM Architecture Reference Manual for ARMv8-A defines up
+// to 7 levels of cache, L1 through L7.
+#define MAX_ARM_CACHE_LEVEL 7
+
+/// Defines the structure of the CSSELR (Cache Size Selection) register
+typedef union {
+ struct {
+ UINT32 InD :1; ///< Instruction not Data bit
+ UINT32 Level :3; ///< Cache level (zero based)
+ UINT32 TnD :1; ///< Allocation not Data bit
+ UINT32 Reserved :27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CSSELR_DATA;
+
+/// The cache type values for the InD field of the CSSELR register
+typedef enum
+{
+ /// Select the data or unified cache
+ CsselrCacheTypeDataOrUnified = 0,
+ /// Select the instruction cache
+ CsselrCacheTypeInstruction,
+ CsselrCacheTypeMax
+} CSSELR_CACHE_TYPE;
+
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register
+typedef union {
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :10; ///< Associativity - 1
+ UINT64 NumSets :15; ///< Number of sets in the cache -1
+ UINT64 Unknown :4; ///< Reserved, UNKNOWN
+ UINT64 Reserved :32; ///< Reserved, RES0
+ } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :21; ///< Associativity - 1
+ UINT64 Reserved1 :8; ///< Reserved, RES0
+ UINT64 NumSets :24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 :8; ///< Reserved, RES0
+ } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
+ struct {
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
+ } BitsCcidxAA32;
+ UINT64 Data; ///< The entire 64-bit value
+} CCSIDR_DATA;
+
+/// Defines the structure of the AARCH32 CCSIDR2 register.
+typedef union {
+ struct {
+ UINT32 NumSets :24; ///< Number of sets in the cache - 1
+ UINT32 Reserved :8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CCSIDR2_DATA;
+
+/** Defines the structure of the CLIDR (Cache Level ID) register.
+ *
+ * The lower 32 bits are the same for both AARCH32 and AARCH64
+ * so we can use the same structure for both.
+**/
+typedef union {
+ struct {
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CLIDR_DATA;
+
+/// The cache types reported in the CLIDR register.
+typedef enum {
+ /// No cache is present
+ ClidrCacheTypeNone = 0,
+ /// There is only an instruction cache
+ ClidrCacheTypeInstructionOnly,
+ /// There is only a data cache
+ ClidrCacheTypeDataOnly,
+ /// There are separate data and instruction caches
+ ClidrCacheTypeSeparate,
+ /// There is a unified cache
+ ClidrCacheTypeUnified,
+ ClidrCacheTypeMax
+} CLIDR_CACHE_TYPE;
+
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+
+#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5c232d779c83..79ea755777a9 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -2,7 +2,7 @@

Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -109,9 +109,37 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)

-// The ARM Architecture Reference Manual for ARMv8-A defines up
-// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+/** Reads the CCSIDR register for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value.
+
+ @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
+ Returns the contents of the CCSIDR register in AARCH32 mode.
+**/
+UINTN
+ReadCCSIDR (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the CCSIDR2 for the specified cache.
+
+ @param CSSELR The CSSELR cache selection register value
+
+ @return The contents of the CCSIDR2 register for the specified cache.
+**/
+UINT32
+ReadCCSIDR2 (
+ IN UINT32 CSSELR
+ );
+
+/** Reads the Cache Level ID (CLIDR) register.
+
+ @return The contents of the CLIDR_EL1 register.
+**/
+UINT32
+ReadCLIDR (
+ VOID
+ );

UINTN
EFIAPI
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index 5db83d620bfc..668aefd6a088 100644
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -52,101 +52,6 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)

-
-/// Defines the structure of the CSSELR (Cache Size Selection) register
-typedef union {
- struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CSSELR_DATA;
-
-/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
- /// Select the data or unified cache
- CsselrCacheTypeDataOrUnified = 0,
- /// Select the instruction cache
- CsselrCacheTypeInstruction,
- CsselrCacheTypeMax
-} CSSELR_CACHE_TYPE;
-
-/// Defines the structure of the CCSIDR (Current Cache Size ID) register
-typedef union {
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
- } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
- struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
- } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
- struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
- } BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
-} CCSIDR_DATA;
-
-/// Defines the structure of the AARCH32 CCSIDR2 register.
-typedef union {
- struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CCSIDR2_DATA;
-
-/** Defines the structure of the CLIDR (Cache Level ID) register.
- *
- * The lower 32 bits are the same for both AARCH32 and AARCH64
- * so we can use the same structure for both.
-**/
-typedef union {
- struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
-} CLIDR_DATA;
-
-/// The cache types reported in the CLIDR register.
-typedef enum {
- /// No cache is present
- ClidrCacheTypeNone = 0,
- /// There is only an instruction cache
- ClidrCacheTypeInstructionOnly,
- /// There is only a data cache
- ClidrCacheTypeDataOnly,
- /// There are separate data and instruction caches
- ClidrCacheTypeSeparate,
- /// There is a unified cache
- ClidrCacheTypeUnified,
- ClidrCacheTypeMax
-} CLIDR_CACHE_TYPE;
-
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
-
VOID
CPSRMaskInsert (
IN UINT32 Mask,
@@ -158,32 +63,4 @@ CPSRRead (
VOID
);

-/** Reads the CCSIDR register for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value.
-
- @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
- Returns the contents of the CCSIDR register in AARCH32 mode.
-**/
-UINTN
-ReadCCSIDR (
- IN UINT32 CSSELR
- );
-
-/** Reads the CCSIDR2 for the specified cache.
-
- @param CSSELR The CSSELR cache selection register value
-
- @return The contents of the CCSIDR2 register for the specified cache.
-**/
-UINT32
-ReadCCSIDR2 (
- IN UINT32 CSSELR
- );
-
-UINT32
-ReadCLIDR (
- VOID
- );
-
#endif // ARM_LIB_PRIVATE_H_
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 0cb56c53975e..fb484086a457 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -10,11 +10,11 @@

#include <Uefi.h>
#include <Protocol/Smbios.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
#include <Library/ArmSmcLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
index ddd774b16f83..6fbb95afb215 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
index c78bd41a7e06..7616fca425fd 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
@@ -8,8 +8,8 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>

#include "SmbiosProcessor.h"

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
index bccb21cfbb41..292f10bf97eb 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
@@ -8,10 +8,10 @@
**/

#include <Uefi.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/ArmStdSmc.h>
#include <IndustryStandard/SmBios.h>
#include <Library/ArmLib.h>
-#include <Library/ArmLib/ArmLibPrivate.h>
#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>

--
2.26.2


Re: [PATCH v1 1/4] StandaloneMmPkg: Core: Spelling error in comment

Kun Qin
 

Hi Ard,

Sorry for the confusion and thanks for providing the r-b tag.

This should be fixed in v2 patches: https://edk2.groups.io/g/devel/message/76479

Regards,
Kun

On 06/12/2021 01:22, Ard Biesheuvel wrote:
On Sat, 12 Jun 2021 at 05:44, Kun Qin <kuqin12@gmail.com> wrote:

From: Sean Brogan <sean.brogan@microsoft.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

This change fixed a misspelling that was not caught by spell check.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Hello Kun Qin,
When you send patches to the list that were authored by someone else,
you should add your own signoff, and add it last. (The signoff means
that you attest that the patch is contributed under terms that are
compatible with the open source licenses we support. The signoff has
nothing to do with recognizing authorship, so even if someone else did
most of the work, if that person is not involved in contributing these
changes, their name does not need to appear in the Git log.)
Sean is the author, which will be reflected in the git log anyway, so
his signoff does not have any significance here, as he is not the one
sending the patch to the public mailing list.
Usually, I would fix up minor issues like these when merging the
changes, but adding a signoff on someone else's behalf is the one
thing I can never do.
So please fix this up, and then you can add
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
to the entire series.
Thanks,

---
StandaloneMmPkg/Core/Dispatcher.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/StandaloneMmPkg/Core/Dispatcher.c b/StandaloneMmPkg/Core/Dispatcher.c
index dbd5332fa9d3..7e4bf5e94025 100644
--- a/StandaloneMmPkg/Core/Dispatcher.c
+++ b/StandaloneMmPkg/Core/Dispatcher.c
@@ -4,7 +4,7 @@
Step #1 - When a FV protocol is added to the system every driver in the FV
is added to the mDiscoveredList. The Before, and After Depex are
pre-processed as drivers are added to the mDiscoveredList. If an Apriori
- file exists in the FV those drivers are addeded to the
+ file exists in the FV those drivers are added to the
mScheduledQueue. The mFwVolList is used to make sure a
FV is only processed once.

--
2.31.1.windows.1


[PATCH v2 4/4] Azurepipeline: SpellCheck: Enforce Node dependency to use version 14.x

Kun Qin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

Per update from Cspell tool, the minimal requirement of Cspell 5.x
regarding Node is 12 and above. This has caused multple Cspell failures
during CI build validation:
"Failed to process "**.c" TypeError: text.matchAll(...) is not a function
or its return value is not iterable"

This change updates the lowest required node version to 14.x to support
Cspell functionalities.

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
---

Notes:
v2:
- Added reviewed-by tag [Ard]

.azurepipelines/templates/spell-check-prereq-steps.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.azurepipelines/templates/spell-check-prereq-steps.yml b/.azurepipelines/templates/spell-check-prereq-steps.yml
index e1570d4f2aac..98ee3cfa6bc6 100644
--- a/.azurepipelines/templates/spell-check-prereq-steps.yml
+++ b/.azurepipelines/templates/spell-check-prereq-steps.yml
@@ -13,7 +13,7 @@ parameters:
steps:
- task: NodeTool@0
inputs:
- versionSpec: '10.x'
+ versionSpec: '14.x'
#checkLatest: false # Optional
condition: and(gt(variables.pkg_count, 0), succeeded())

--
2.31.1.windows.1


[PATCH v2 3/4] ArmPkg: SpellCheck: Update valid acronyms in ExtendedWords

Kun Qin
 

From: Sean Brogan <sean.brogan@microsoft.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3445

Spellcheck was not covering all specified files due to CSpell v5 and
Node v10 incompatibility of current CI pipeline configuration.

This change updates ExtendedWords for ArmPkg with valid acronyms to avoid
potential spell errors.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>

Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
---

Notes:
v2:
- Moved Kun's signed-off tag to the last
- Added reviewed-by tag [Ard]

ArmPkg/ArmPkg.ci.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/ArmPkg/ArmPkg.ci.yaml b/ArmPkg/ArmPkg.ci.yaml
index d91c03f2acb8..a0d6a75fe881 100644
--- a/ArmPkg/ArmPkg.ci.yaml
+++ b/ArmPkg/ArmPkg.ci.yaml
@@ -94,13 +94,18 @@
"ackintid",
"actlr",
"aeabi",
+ "asedis",
"ashldi",
"ashrdi",
+ "baddr",
"ccidx",
"ccsidr",
"clidr",
"clrex",
"clzsi",
+ "cnthctl",
+ "cortexa",
+ "cpacr",
"cpuactlr",
"csselr",
"ctzsi",
@@ -116,6 +121,7 @@
"divdi",
"divsi",
"dmdepkg",
+ "dpref",
"drsub",
"fcmpeq",
"fcmpge",
@@ -125,17 +131,25 @@
"ffreestanding",
"frsub",
"hisilicon",
+ "iccabpr",
"iccbpr",
"icciar",
"iccicr",
"icciidr",
+ "iccpir",
"iccpmr",
+ "iccrpr",
+ "icdabr",
"icdicer",
"icdicfr",
+ "icdicpr",
"icdictr",
+ "icdiidr",
"icdiser",
"icdisr",
+ "icdppisr",
"icdsgir",
+ "icdspr",
"icenabler",
"intid",
"ipriority",
@@ -160,6 +174,7 @@
"lshrdi",
"moddi",
"modsi",
+ "mpcore",
"mpidr",
"muldi",
"mullu",
@@ -168,6 +183,9 @@
"nsasedis",
"nuvia",
"oldit",
+ "pcten",
+ "plpis",
+ "procno",
"readc",
"revsh",
"rfedb",
@@ -189,6 +207,7 @@
"smmlsr",
"sourcery",
"srsdb",
+ "ssacr",
"stmdb",
"stmia",
"strbt",
--
2.31.1.windows.1

5741 - 5760 of 82167