Date   

Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Laszlo Ersek
 

On 05/14/21 17:44, Marvin Häuser wrote:
On 14.05.21 17:23, Lendacky, Thomas wrote:
On 5/14/21 10:04 AM, Marvin Häuser wrote:
+      // Check to be sure that the "allocate below" behavior hasn't
changed.
+      // This will also catch a failed allocation, as "-1" is
returned on
+      // failure.
+      //
+      if (CpuMpData->SevEsAPResetStackStart >=
CpuMpData->WakeupBuffer) {
+        DEBUG ((DEBUG_ERROR,
+          "SEV-ES AP reset stack is not below wakeup buffer\n"));
+
+        ASSERT (FALSE);
Should the ASSERT not only catch the broken "allocate below" behaviour,
i.e. not trigger on failed allocation?
I think it's best to trigger on a failed allocation as well rather than
continuing and allowing a page fault or some other problem to occur.
Well, it should handle the error in a safe way, i.e. the deadloop below.
To not ASSERT on plausible conditions is a common design guideline in
most low-level projects including Linux kernel.

Best regards,
Marvin

Thanks,
Tom

+        CpuDeadLoop ();
"DEBUG + ASSERT(FALSE) + CpuDeadLoop()" is a pattern in edk2.

In RELEASE builds, it will lead to a CpuDeadLoop(). That's the main goal
-- don't continue execution if the condition controlling the whole block
fired.

In DEBUG and NOOPT builds, the pattern will lead to a debug message
(usually at the "error" level), followed by an assertion failure. The
error message of the assertion failure is irrelevant ("FALSE"). The
point of adding ASSERT ahead of CpuDeadLoop() is that the way ASSERT
hangs execution is customizable, via "PcdDebugPropertyMask", unlike
CpuDeadLoop(). In many cases, ASSERT() uses CpuDeadLoop() itself, so the
effect is the same -- the explicit CpuDeadLoop is not reached. In other
configs, ASSERT() can raise a debug exception (CpuBreakpoint()).

The required part of the pattern is CpuDeadLoop(); the DEBUG message
makes it more debugging-friendly, and the ASSERT(), with the tweakable
"hang method", makes it even more debugging-friendly.

Thanks
Laszlo


[PATCH v1 1/1] Add MemoryFence implementation for RiscV64

Daniel Schaefer
 

Cc: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33 ++++++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea..b7ab5f632366 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -399,6 +399,7 @@
RiscV64/DisableInterrupts.c
RiscV64/EnableInterrupts.c
RiscV64/CpuPause.c
+ RiscV64/MemoryFence.S | GCC
RiscV64/RiscVSetJumpLongJump.S | GCC
RiscV64/RiscVCpuBreakpoint.S | GCC
RiscV64/RiscVCpuPause.S | GCC
diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
new file mode 100644
index 000000000000..283df9356a9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
@@ -0,0 +1,33 @@
+##------------------------------------------------------------------------------
+#
+# MemoryFence() for RiscV64
+
+# Copyright (c) 2021, Hewlett Packard Enterprise Development. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+ASM_GLOBAL ASM_PFX(MemoryFence)
+
+
+#/**
+# Used to serialize load and store operations.
+#
+# All loads and stores that proceed calls to this function are guaranteed to be
+# globally visible when this function returns.
+#
+#**/
+#VOID
+#EFIAPI
+#MemoryFence (
+# VOID
+# );
+#
+ASM_PFX(MemoryFence):
+ // Fence on all memory and I/O
+ fence
+ ret
--
2.30.1


Re: [PATCH v1 3/3] CryptoPkg/BaseCryptLib: Fix possible uninitialized use

Sergei Dmitrouk <sergei@...>
 

Hello Jiewen,

I get the error only for GCC49 and not for GCC5 toolchain. CI uses GCC5.

So I compared build commands and this seems to depend on LTO. Adding `-flto`
impedes compiler's ability to detect such simple issues.

I've found relevant bug report, there is even fix suggestion from last month:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90844

Regards,
Sergei

On Sat, May 15, 2021 at 12:30:44AM +0000, Yao, Jiewen wrote:
Hi Sergei
Thank you very much for the fix.
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

I am a little surprised why it is not caught before. It is an obvious logic issue.

Do you think we can do anything on CI, to catch it during pre-check-in in the future?
I just feel it is burden to make it post-check-in fix.


Thank you
Yao Jiewen

-----Original Message-----
From: Sergei Dmitrouk <sergei@posteo.net>
Sent: Friday, May 14, 2021 8:17 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>;
Lu, XiaoyuX <xiaoyux.lu@intel.com>; Jiang, Guomin <guomin.jiang@intel.com>
Subject: [PATCH v1 3/3] CryptoPkg/BaseCryptLib: Fix possible uninitialized use

`Result` can be used uninitialized in both functions after following
either first or second `goto` statement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
---
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c | 1 +
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c | 1 +
2 files changed, 2 insertions(+)

diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
index 4009d37d5f91..0b2960f06c4c 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
@@ -82,6 +82,7 @@ RsaPssVerify (
EVP_PKEY_CTX *KeyCtx;
CONST EVP_MD *HashAlg;

+ Result = FALSE;
EvpRsaKey = NULL;
EvpVerifyCtx = NULL;
KeyCtx = NULL;
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
index b66b6f7296ad..ece765f9ae0a 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
@@ -97,6 +97,7 @@ RsaPssSign (
EVP_PKEY_CTX *KeyCtx;
CONST EVP_MD *HashAlg;

+ Result = FALSE;
EvpRsaKey = NULL;
EvpVerifyCtx = NULL;
KeyCtx = NULL;
--
2.17.6


Re: [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

Nate DeSimone
 

The series has been pushed as 26737930~..eeaa7b7

Thanks,
Nate

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate DeSimone
Sent: Tuesday, May 11, 2021 2:48 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Abbas, Mohamed <mohamed.abbas@intel.com>; Michael Kubacki <michael.kubacki@microsoft.com>; Bobroff, Zachary <zacharyb@ami.com>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@ami.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

This patch series revives the PurleyOpenBoardPkg. The package has been
upgraded to support the newest MinPlatformPkg and the new advanced
feature architecture. Build issues with the newest EDK II have been
fixed. Finally, I believe most (if not all) MinPlatform Architecture
violations have been fixed. The build system has been converted from
the legacy .bat scripts to the new Python build infrastructure.

For silicon code, I have consolidated PurleyRcPkg, PurleySktPkg,
and LewisburgPkg into a single PurleyRefreshSiliconPkg for consistency
with the other MinPlatform board port's silicon packages. In addition,
the silicon code has been upgraded to a newer version with support
for the 2nd Generation Xeon Scalable "Cascade Lake" processors.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Nate DeSimone (18):
PurleyRefreshSiliconPkg: Add DEC and DSC files.
PurleyRefreshSiliconPkg/Pch: Add Register Header Files
PurleyRefreshSiliconPkg/Pch: Add Public Header Files
PurleyRefreshSiliconPkg/Pch: Add Private Header Files
PurleyRefreshSiliconPkg/Pch: Add libraries
PurleyRefreshSiliconPkg/Pch: Add ACPI tables
PurleyRefreshSiliconPkg: Add Uncore files
PurleyOpenBoardPkg: Add includes and libraries
PurleyOpenBoardPkg: Add modules
PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PlatformPciTree_WFP.asi
PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PCxx.asi files
PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add ASL files
PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe
PurleyOpenBoardPkg: Add MtOlympus build files
PurleyOpenBoardPkg: Add StructureConfig.dsc
PurleyOpenBoardPkg: Add BoardMtOlympus
Readme.md: Add PurleyOpenBoardPkg
Maintainers.txt: Add PurleyOpenBoardPkg and PurleyRefreshSiliconPkg

Maintainers.txt | 10 +
.../Acpi/BoardAcpiDxe/AmlOffsetTable.c | 290 +
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 547 ++
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.h | 82 +
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 71 +
.../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c | 516 ++
.../Acpi/BoardAcpiDxe/Dsdt.inf | 29 +
.../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 19 +
.../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi | 227 +
.../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl | 77 +
.../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 134 +
.../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 256 +
.../Dsdt/IioPcieHotPlugGpeHandler.asl | 842 ++
.../Dsdt/IioPcieRootPortHotPlug.asl | 686 ++
.../Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 32 +
.../Acpi/BoardAcpiDxe/Dsdt/Mother.asi | 202 +
.../Acpi/BoardAcpiDxe/Dsdt/Os.asi | 145 +
.../Acpi/BoardAcpiDxe/Dsdt/PC00.asi | 385 +
.../Acpi/BoardAcpiDxe/Dsdt/PC01.asi | 255 +
.../Acpi/BoardAcpiDxe/Dsdt/PC02.asi | 255 +
.../Acpi/BoardAcpiDxe/Dsdt/PC03.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC04.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC05.asi | 233 +
.../Acpi/BoardAcpiDxe/Dsdt/PC06.asi | 328 +
.../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/PC07.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC08.asi | 262 +
.../Acpi/BoardAcpiDxe/Dsdt/PC09.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC10.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC11.asi | 231 +
.../Acpi/BoardAcpiDxe/Dsdt/PC12.asi | 324 +
.../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/PC13.asi | 256 +
.../Acpi/BoardAcpiDxe/Dsdt/PC14.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC15.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC16.asi | 231 +
.../Acpi/BoardAcpiDxe/Dsdt/PC17.asi | 231 +
.../Acpi/BoardAcpiDxe/Dsdt/PC18.asi | 342 +
.../Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/PC19.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC20.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC21.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC22.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC23.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC24.asi | 231 +
.../Acpi/BoardAcpiDxe/Dsdt/PC25.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC26.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC27.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC28.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC29.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC30.asi | 256 +
.../Acpi/BoardAcpiDxe/Dsdt/PC31.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC32.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC33.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC34.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC35.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC36.asi | 257 +
.../Acpi/BoardAcpiDxe/Dsdt/PC37.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC38.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC39.asi | 260 +
.../Acpi/BoardAcpiDxe/Dsdt/PC40.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC41.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC42.asi | 290 +
.../Acpi/BoardAcpiDxe/Dsdt/PC43.asi | 259 +
.../Acpi/BoardAcpiDxe/Dsdt/PC44.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC45.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC46.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/PC47.asi | 232 +
.../Acpi/BoardAcpiDxe/Dsdt/Pch.asi | 10 +
.../Acpi/BoardAcpiDxe/Dsdt/PchApic.asi | 17 +
.../Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi | 91 +
.../Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi | 92 +
.../Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl | 17 +
.../Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi | 22 +
.../Acpi/BoardAcpiDxe/Dsdt/PchSata.asi | 807 ++
.../Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi | 329 +
.../Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi | 312 +
.../Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi | 455 +
.../Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi | 644 ++
.../Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi | 14 +
.../Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi | 16 +
.../Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi | 355 +
.../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 79 +
.../Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi | 78 +
.../BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi | 8070 +++++++++++++++++
.../Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi | 9 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi | 33 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi | 175 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi | 125 +
.../Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi | 98 +
.../Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl | 189 +
.../BoardMtOlympus/GitEdk2MinMtOlympus.bat | 74 +
.../BasePlatformHookLib/BasePlatformHookLib.c | 292 +
.../BasePlatformHookLib.inf | 36 +
.../BoardAcpiLib/DxeBoardAcpiTableLib.c | 35 +
.../BoardAcpiLib/DxeBoardAcpiTableLib.inf | 40 +
.../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 52 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 61 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 41 +
.../BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c | 36 +
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 119 +
.../Library/BoardInitLib/AllLanesEparam.c | 43 +
.../Library/BoardInitLib/GpioTable.c | 296 +
.../Library/BoardInitLib/IioBifur.c | 88 +
.../BoardInitLib/PeiBoardInitPostMemLib.c | 45 +
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 37 +
.../BoardInitLib/PeiBoardInitPreMemLib.c | 111 +
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 69 +
.../Library/BoardInitLib/PeiMtOlympusDetect.c | 27 +
.../BoardInitLib/PeiMtOlympusInitLib.h | 17 +
.../BoardInitLib/PeiMtOlympusInitPostMemLib.c | 85 +
.../BoardInitLib/PeiMtOlympusInitPreMemLib.c | 614 ++
.../Library/BoardInitLib/UsbOC.c | 45 +
.../BoardMtOlympus/OpenBoardPkg.dsc | 221 +
.../BoardMtOlympus/OpenBoardPkg.fdf | 589 ++
.../BoardMtOlympus/PlatformPkgBuildOption.dsc | 81 +
.../BoardMtOlympus/PlatformPkgConfig.dsc | 58 +
.../BoardMtOlympus/PlatformPkgPcd.dsc | 389 +
.../BoardMtOlympus/StructureConfig.dsc | 6203 +++++++++++++
.../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 138 +
.../BoardMtOlympus/build_board.py | 177 +
.../BoardMtOlympus/build_config.cfg | 32 +
.../BoardMtOlympus/logo.txt | 11 +
.../BoardMtOlympus/postbuild.bat | 95 +
.../BoardMtOlympus/prebuild.bat | 197 +
.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c | 362 +
.../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf | 40 +
.../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c | 485 +
.../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h | 208 +
.../IpmiPlatformHookLib/IpmiPlatformHookLib.c | 39 +
.../IpmiPlatformHookLib.inf | 28 +
.../Include/Acpi/GlobalNvs.asi | 282 +
.../Include/Acpi/GlobalNvsAreaDef.h | 128 +
.../Include/Guid/PchRcVariable.h | 414 +
.../Include/Guid/SetupVariable.h | 539 ++
.../Include/IioBifurcationSlotTable.h | 100 +
.../PurleyOpenBoardPkg/Include/Platform.h | 92 +
.../Include/Ppi/SystemBoard.h | 63 +
.../Include/Protocol/PciIovPlatform.h | 70 +
.../PurleyOpenBoardPkg/Include/SetupTable.h | 21 +
.../PurleyOpenBoardPkg/Include/SioRegs.h | 35 +
.../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec | 141 +
.../DxePlatformBootManagerLib/BdsPlatform.c | 1354 +++
.../DxePlatformBootManagerLib/BdsPlatform.h | 184 +
.../DxePlatformBootManagerLib.inf | 96 +
.../DxePlatformBootManagerLib/MemoryTest.c | 85 +
.../PlatformBootOption.c | 559 ++
.../Pci/PciPlatform/IoApic.h | 22 +
.../Pci/PciPlatform/PciIovPlatformPolicy.c | 96 +
.../Pci/PciPlatform/PciIovPlatformPolicy.h | 51 +
.../Pci/PciPlatform/PciPlatform.c | 183 +
.../Pci/PciPlatform/PciPlatform.h | 201 +
.../Pci/PciPlatform/PciPlatform.inf | 70 +
.../Pci/PciPlatform/PciPlatformHooks.c | 527 ++
.../Pci/PciPlatform/PciPlatformHooks.h | 24 +
.../Pci/PciPlatform/PciSupportLib.c | 103 +
.../Pci/PciPlatform/PciSupportLib.h | 44 +
.../Policy/IioUdsDataDxe/IioUdsDataDxe.c | 86 +
.../Policy/IioUdsDataDxe/IioUdsDataDxe.h | 81 +
.../Policy/IioUdsDataDxe/IioUdsDataDxe.inf | 36 +
.../SiliconPolicyInitLib.c | 130 +
.../SiliconPolicyInitLib.inf | 39 +
.../PchPolicyUpdateUsb.c | 99 +
.../SiliconPolicyUpdateLib.c | 659 ++
.../SiliconPolicyUpdateLib.inf | 54 +
.../PlatformCpuPolicy/PlatformCpuPolicy.c | 654 ++
.../PlatformCpuPolicy/PlatformCpuPolicy.inf | 80 +
.../Policy/S3NvramSave/S3NvramSave.c | 256 +
.../Policy/S3NvramSave/S3NvramSave.h | 31 +
.../Policy/S3NvramSave/S3NvramSave.inf | 59 +
.../Policy/SystemBoard/SystemBoardCommon.c | 625 ++
.../Policy/SystemBoard/SystemBoardPei.c | 255 +
.../Policy/SystemBoard/SystemBoardPei.h | 182 +
.../Policy/SystemBoard/SystemBoardPei.inf | 76 +
Platform/Intel/Readme.md | 34 +
Platform/Intel/build.cfg | 1 +
Readme.md | 1 +
.../Iio/Include/Protocol/IioSystem.h | 58 +
.../Include/Guid/MemoryConfigData.h | 19 +
.../Include/Guid/MemoryMapData.h | 74 +
.../Include/Guid/PartialMirrorGuid.h | 59 +
.../Include/Guid/SmramMemoryReserve.h | 43 +
.../Include/Guid/SocketCommonRcVariable.h | 41 +
.../Include/Guid/SocketIioVariable.h | 264 +
.../Include/Guid/SocketMemoryVariable.h | 321 +
.../Include/Guid/SocketMpLinkVariable.h | 173 +
.../Include/Guid/SocketPciResourceData.h | 42 +
.../Guid/SocketPowermanagementVariable.h | 227 +
.../Guid/SocketProcessorCoreVariable.h | 115 +
.../Include/Guid/SocketVariable.h | 35 +
.../Include/Library/CpuPpmLib.h | 707 ++
.../Include/Library/CsrToPcieAddress.h | 42 +
.../Include/Library/MmPciBaseLib.h | 48 +
.../Include/Library/PcieAddress.h | 80 +
.../Include/Library/PciePlatformHookLib.h | 27 +
.../Include/Library/UsraAccessApi.h | 85 +
.../Include/MaxSocket.h | 19 +
.../Include/Ppi/SiliconRegAccess.h | 162 +
.../Include/Protocol/IioUds.h | 44 +
.../Include/Protocol/PciCallback.h | 84 +
.../Include/Protocol/SiliconRegAccess.h | 227 +
.../Include/SocketConfiguration.h | 514 ++
.../Include/UncoreCommonIncludes.h | 354 +
.../Include/UsraAccessType.h | 195 +
.../Chip/Skx/Include/Iio/IioConfig.h | 300 +
.../Chip/Skx/Include/Iio/IioPlatformData.h | 298 +
.../Chip/Skx/Include/Iio/IioRegs.h | 314 +
.../Skx/Include/Iio/IioSetupDefinitions.h | 111 +
.../Chip/Skx/Include/KtiDisc.h | 26 +
.../Chip/Skx/Include/KtiHost.h | 136 +
.../Chip/Skx/Include/KtiSi.h | 39 +
.../Chip/Skx/Include/Protocol/CpuCsrAccess.h | 143 +
.../Chip/Skx/Include/Setup/IioUniversalData.h | 187 +
.../BaseMemoryCoreLib/Core/Include/CpuHost.h | 255 +
.../Core/Include/CsrToPcieAddress.h | 42 +
.../Core/Include/DataTypes.h | 111 +
.../BaseMemoryCoreLib/Core/Include/MemHost.h | 328 +
.../Core/Include/MemHostChipCommon.h | 122 +
.../BaseMemoryCoreLib/Core/Include/MemRegs.h | 13 +
.../Core/Include/MrcCommonTypes.h | 20 +
.../Core/Include/PcieAddress.h | 65 +
.../BaseMemoryCoreLib/Core/Include/Printf.h | 74 +
.../BaseMemoryCoreLib/Core/Include/SysHost.h | 136 +
.../Core/Include/SysHostChipCommon.h | 86 +
.../BaseMemoryCoreLib/Core/Include/SysRegs.h | 68 +
.../Core/Include/UsbDebugPort.h | 318 +
.../Platform/Purley/Include/MemDefaults.h | 17 +
.../Platform/Purley/Include/MemPlatform.h | 81 +
.../Platform/Purley/Include/PlatformHost.h | 176 +
.../Library/CsrToPcieLib/CpuCsrAccessDefine.h | 56 +
.../Library/CsrToPcieLib/CsrToPcieDxeLib.inf | 85 +
.../Library/CsrToPcieLib/CsrToPcieLib.c | 179 +
.../Library/CsrToPcieLib/CsrToPciePeiLib.inf | 81 +
.../CsrToPcieLibNull/BaseCsrToPcieLibNull.inf | 67 +
.../Library/CsrToPcieLibNull/CsrToPcieLib.c | 41 +
.../Library/DxeMmPciBaseLib/DxeMmPciBaseLib.c | 89 +
.../DxeMmPciBaseLib/DxeMmPciBaseLib.inf | 60 +
.../Library/DxeMmPciBaseLib/SmmMmPciBaseLib.c | 86 +
.../DxeMmPciBaseLib/SmmMmPciBaseLib.inf | 60 +
.../Library/MmPciBaseLib/MmPciBaseLib.c | 69 +
.../Library/MmPciBaseLib/MmPciBaseLib.inf | 55 +
.../Library/PcieAddressLib/PcieAddressLib.c | 305 +
.../Library/PcieAddressLib/PcieAddressLib.inf | 70 +
.../Chip/Common/CpuPciAccessCommon.c | 812 ++
.../Chip/Include/CpuCsrAccessDefine.h | 52 +
.../ProcMemInit/Chip/Include/CpuPciAccess.h | 117 +
.../Chip/Include/CpuPciAccessCommon.h | 83 +
.../ProcMemInit/Chip/Include/Rc_Revision.h | 13 +
.../Library/UsraAccessLib/CsrAccess.c | 118 +
.../Library/UsraAccessLib/PcieAccess.c | 354 +
.../Library/UsraAccessLib/UsraAccessLib.c | 235 +
.../Library/UsraAccessLib/UsraAccessLib.h | 257 +
.../Library/UsraAccessLib/UsraAccessLib.inf | 62 +
.../IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec | 609 ++
.../Include/Library/CpuConfigLib.h | 667 ++
.../Include/Protocol/IntelCpuPcdsSetDone.h | 18 +
.../Pch/AcpiTables/Dsdt/GpioDefine.asl | 784 ++
.../Pch/AcpiTables/Dsdt/GpioLib.asl | 1024 +++
.../Pch/AcpiTables/Dsdt/IrqLink.asl | 607 ++
.../Pch/AcpiTables/Dsdt/Pch.asl | 833 ++
.../Pch/AcpiTables/Dsdt/PchAcpiTables.inf | 34 +
.../Pch/AcpiTables/Dsdt/PchHda.asl | 306 +
.../Pch/AcpiTables/Dsdt/PchHeci.asl | 22 +
.../Pch/AcpiTables/Dsdt/PchIsh.asl | 21 +
.../Pch/AcpiTables/Dsdt/PchNvs.asl | 270 +
.../Pch/AcpiTables/Dsdt/PchPcie.asl | 202 +
.../Pch/AcpiTables/Dsdt/PchRstPcieStorage.asl | 216 +
.../Pch/AcpiTables/Dsdt/PchSata.asl | 221 +
.../Pch/AcpiTables/Dsdt/PchScs.asl | 8 +
.../Pch/AcpiTables/Dsdt/PchSerialIo.asl | 7 +
.../Pch/AcpiTables/Dsdt/PchXdci.asl | 8 +
.../Pch/AcpiTables/Dsdt/PchXhci.asl | 557 ++
.../Pch/AcpiTables/Dsdt/RP01_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP02_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP03_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP04_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP05_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP06_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP07_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP08_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP09_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP10_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP11_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP12_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP13_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP14_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP15_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP16_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP17_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP18_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP19_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/RP20_ADR.asl | 14 +
.../Pch/AcpiTables/Dsdt/TraceHubDebug.asl | 142 +
.../Pch/AcpiTables/Dsdt/usbsbd.asl | 63 +
.../Pch/Include/GpioConfig.h | 230 +
.../Pch/Include/GpioPinsSklH.h | 298 +
.../Pch/Include/GpioPinsSklLp.h | 201 +
.../Pch/Include/Library/GpioLib.h | 777 ++
.../Pch/Include/Library/GpioNativeLib.h | 218 +
.../Pch/Include/Library/PchCycleDecodingLib.h | 344 +
.../Pch/Include/Library/PchGbeLib.h | 58 +
.../Pch/Include/Library/PchInfoLib.h | 231 +
.../Pch/Include/Library/PchP2sbLib.h | 154 +
.../Pch/Include/Library/PchPcrLib.h | 190 +
.../Pch/Include/Library/PchPmcLib.h | 56 +
.../Pch/Include/Library/PchPolicyLib.h | 66 +
.../Pch/Include/Library/PchSbiAccessLib.h | 156 +
.../Pch/Include/Library/PchSerialIoLib.h | 212 +
.../Pch/Include/Library/SpiFlashCommonLib.h | 96 +
.../Pch/Include/PchAccess.h | 621 ++
.../Pch/Include/PchLimits.h | 102 +
.../Pch/Include/PchPolicyCommon.h | 2212 +++++
.../Pch/Include/PchReservedResources.h | 81 +
.../Pch/Include/PcieRegs.h | 279 +
.../Pch/Include/Ppi/PchPcieDeviceTable.h | 124 +
.../Pch/Include/Ppi/PchPolicy.h | 19 +
.../Pch/Include/Ppi/PchReset.h | 93 +
.../Pch/Include/Ppi/Spi.h | 25 +
.../Pch/Include/Protocol/PchReset.h | 112 +
.../Pch/Include/Protocol/Spi.h | 306 +
.../Pch/Include/Register/PchRegsDci.h | 24 +
.../Pch/Include/Register/PchRegsDmi.h | 188 +
.../Pch/Include/Register/PchRegsEva.h | 110 +
.../Pch/Include/Register/PchRegsFia.h | 81 +
.../Pch/Include/Register/PchRegsGpio.h | 511 ++
.../Pch/Include/Register/PchRegsHda.h | 226 +
.../Pch/Include/Register/PchRegsHsio.h | 171 +
.../Pch/Include/Register/PchRegsIsh.h | 51 +
.../Pch/Include/Register/PchRegsItss.h | 68 +
.../Pch/Include/Register/PchRegsLan.h | 135 +
.../Pch/Include/Register/PchRegsLpc.h | 430 +
.../Pch/Include/Register/PchRegsP2sb.h | 100 +
.../Pch/Include/Register/PchRegsPcie.h | 513 ++
.../Pch/Include/Register/PchRegsPcr.h | 64 +
.../Pch/Include/Register/PchRegsPmc.h | 627 ++
.../Pch/Include/Register/PchRegsPsf.h | 210 +
.../Pch/Include/Register/PchRegsPsth.h | 46 +
.../Pch/Include/Register/PchRegsSata.h | 634 ++
.../Pch/Include/Register/PchRegsScs.h | 152 +
.../Pch/Include/Register/PchRegsSerialIo.h | 282 +
.../Pch/Include/Register/PchRegsSmbus.h | 134 +
.../Pch/Include/Register/PchRegsSpi.h | 291 +
.../Pch/Include/Register/PchRegsThermal.h | 93 +
.../Pch/Include/Register/PchRegsTraceHub.h | 125 +
.../Pch/Include/Register/PchRegsUsb.h | 463 +
.../Pch/Include/SaRegs.h | 700 ++
.../Library/PchResetCommonLib.h | 59 +
.../Pch/IncludePrivate/PchHHsioAx.h | 16 +
.../Pch/IncludePrivate/PchHHsioBx.h | 16 +
.../Pch/IncludePrivate/PchHHsioDx.h | 16 +
.../Pch/IncludePrivate/PchHsio.h | 147 +
.../Pch/IncludePrivate/PchLbgHsioAx.h | 16 +
.../Pch/IncludePrivate/PchLbgHsioBx.h | 17 +
.../Pch/IncludePrivate/PchLbgHsioBxD.h | 19 +
.../Pch/IncludePrivate/PchLbgHsioBxD_Ext.h | 19 +
.../Pch/IncludePrivate/PchLbgHsioBx_Ext.h | 17 +
.../Pch/IncludePrivate/PchLbgHsioSx.h | 17 +
.../Pch/IncludePrivate/PchLbgHsioSx_Ext.h | 17 +
.../Pch/IncludePrivate/PchLpHsioBx.h | 16 +
.../Pch/IncludePrivate/PchLpHsioCx.h | 16 +
.../Pch/IncludePrivate/PchPolicyHob.h | 18 +
.../DxeRuntimeResetSystemLib.inf | 63 +
.../DxeRuntimeResetSystemLib/PchReset.c | 633 ++
.../DxeRuntimeResetSystemLib/PchReset.h | 105 +
.../Pch/Library/PeiDxeSmmGpioLib/GpioInit.c | 403 +
.../Pch/Library/PeiDxeSmmGpioLib/GpioLib.c | 2738 ++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 216 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 448 +
.../Library/PeiDxeSmmGpioLib/PchSklGpioData.c | 59 +
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 48 +
.../PchCycleDecodingLib.c | 1169 +++
.../PeiDxeSmmPchCycleDecodingLib.inf | 33 +
.../Library/PeiDxeSmmPchGbeLib/PchGbeLib.c | 160 +
.../PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf | 37 +
.../Library/PeiDxeSmmPchInfoLib/PchInfoLib.c | 505 ++
.../PeiDxeSmmPchInfoLib/PchInfoStrLib.c | 291 +
.../PeiDxeSmmPchInfoLib.inf | 32 +
.../Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c | 331 +
.../PeiDxeSmmPchP2sbLib.inf | 30 +
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 453 +
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 31 +
.../Library/PeiDxeSmmPchPmcLib/PchPmcLib.c | 153 +
.../PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 31 +
.../PchSbiAccessLib.c | 370 +
.../PeiDxeSmmPchSbiAccessLib.inf | 31 +
.../Library/PeiPchPolicyLib/PchPrintPolicy.c | 730 ++
.../Library/PeiPchPolicyLib/PeiPchPolicyLib.c | 581 ++
.../PeiPchPolicyLib/PeiPchPolicyLib.inf | 48 +
.../PeiPchPolicyLib/PeiPchPolicyLibrary.h | 25 +
.../Library/PeiPchPolicyLib/Rvp3PolicyLib.c | 205 +
.../SmmSpiFlashCommonLib.inf | 50 +
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 192 +
.../SpiFlashCommonSmmLib.c | 53 +
.../BasePchResetCommonLib.inf | 27 +
.../BasePchResetCommonLib/PchResetCommon.c | 168 +
.../Intel/PurleyRefreshSiliconPkg/SiPkg.dec | 390 +
.../SiPkgCommonLib.dsc | 33 +
.../PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc | 22 +
.../PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc | 12 +
401 files changed, 91922 insertions(+)
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c
create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
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create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/PchReset.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/PchReset.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/PchSklGpioData.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoStrLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/Rvp3PolicyLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/Pch/LibraryPrivate/BasePchResetCommonLib/PchResetCommon.c
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc

--
2.27.0.windows.1


Re: [edk2-non-osi] [PATCH V1 0/9] PurleySiliconBinPkg: Restore Silicon FVs

Nate DeSimone
 

The series has been pushed as ace1d78~..acc452f

Thanks,
Nate

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate DeSimone
Sent: Tuesday, May 11, 2021 2:54 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Abbas, Mohamed <mohamed.abbas@intel.com>; Michael Kubacki <michael.kubacki@microsoft.com>; Bobroff, Zachary <zacharyb@ami.com>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@ami.com>
Subject: [edk2-devel] [edk2-non-osi] [PATCH V1 0/9] PurleySiliconBinPkg: Restore Silicon FVs

This patch series adds silicon firmware volumes back into the PurleySiliconBinPkg. Note that actual binaries provided by this patch series are the original binaries from 2018, which are unlikely to boot with the new PurleyRefreshSiliconPkg. The purpose of this patch series is to reinstate the directory structure so that it is possible to compile Purley MinPlatform. New binaries will be provided as part of an upcoming patch series.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Mike Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Mohamed Abbas <mohamed.abbas@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Zachary Bobroff <zacharyb@ami.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Nate DeSimone (9):
PurleySiliconBinPkg/FV: Add License.txt
PurleySiliconBinPkg/FV: Add RELEASE FvLateSilicon
PurleySiliconBinPkg/FV: Remove DEBUG FvLateSilicon
PurleySiliconBinPkg/FV: Add RELEASE FvPostMemorySilicon
PurleySiliconBinPkg/FV: Add DEBUG FvPostMemorySilicon
PurleySiliconBinPkg/FV: Add RELEASE FvPreMemorySilicon
PurleySiliconBinPkg/FV: Add DEBUG FvPreMemorySilicon
PurleySiliconBinPkg/FV: Add RELEASE FvTempMemorySilicon
PurleySiliconBinPkg/FV: Add DEBUG FvTempMemorySilicon

.../FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv | Bin 0 -> 663512 bytes
.../FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt | 17 +
.../FV/FvLateSilicon/DEBUG/FvLateSilicon.inf | 4009 +++++++++++++++++ .../FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv | Bin 0 -> 429688 bytes
.../RELEASE/FVLATESILICON.Fv.txt | 17 +
.../FvLateSilicon/RELEASE/FvLateSilicon.inf | 3811 ++++++++++++++++
.../DEBUG/FVPOSTMEMORYSILICON.Fv | Bin 0 -> 196608 bytes
.../DEBUG/FVPOSTMEMORYSILICON.Fv.txt | 3 +
.../DEBUG/FvPostMemorySilicon.inf | 279 ++
.../RELEASE/FVPOSTMEMORYSILICON.Fv | Bin 0 -> 196608 bytes
.../RELEASE/FVPOSTMEMORYSILICON.Fv.txt | 3 +
.../RELEASE/FvPostMemorySilicon.inf | 267 ++
.../DEBUG/FVPREMEMORYSILICON.Fv | Bin 0 -> 1245184 bytes
.../DEBUG/FVPREMEMORYSILICON.Fv.txt | 7 +
.../DEBUG/FvPreMemorySilicon.inf | 1096 +++++
.../RELEASE/FVPREMEMORYSILICON.Fv | Bin 0 -> 1245184 bytes
.../RELEASE/FVPREMEMORYSILICON.Fv.txt | 7 +
.../RELEASE/FvPreMemorySilicon.inf | 1051 +++++
.../DEBUG/FVTEMPMEMORYSILICON.Fv | Bin 0 -> 131072 bytes
.../DEBUG/FVTEMPMEMORYSILICON.Fv.txt | 4 +
.../DEBUG/FvTempMemorySilicon.inf | 267 ++
.../RELEASE/FVTEMPMEMORYSILICON.Fv | Bin 0 -> 131072 bytes
.../RELEASE/FVTEMPMEMORYSILICON.Fv.txt | 4 +
.../RELEASE/FvTempMemorySilicon.inf | 263 ++
.../Intel/PurleySiliconBinPkg/FV/License.txt | 37 +
25 files changed, 11142 insertions(+)
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FvLateSilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FvLateSilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FvPostMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FvPostMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FvPreMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FvPreMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FvTempMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FvTempMemorySilicon.inf
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/License.txt

--
2.27.0.windows.1


Re: [PATCH v1 3/3] CryptoPkg/BaseCryptLib: Fix possible uninitialized use

Yao, Jiewen
 

Hi Sergei
Thank you very much for the fix.
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>

I am a little surprised why it is not caught before. It is an obvious logic issue.

Do you think we can do anything on CI, to catch it during pre-check-in in the future?
I just feel it is burden to make it post-check-in fix.


Thank you
Yao Jiewen

-----Original Message-----
From: Sergei Dmitrouk <sergei@posteo.net>
Sent: Friday, May 14, 2021 8:17 PM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>;
Lu, XiaoyuX <xiaoyux.lu@intel.com>; Jiang, Guomin <guomin.jiang@intel.com>
Subject: [PATCH v1 3/3] CryptoPkg/BaseCryptLib: Fix possible uninitialized use

`Result` can be used uninitialized in both functions after following
either first or second `goto` statement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Sergei Dmitrouk <sergei@posteo.net>
---
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c | 1 +
CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c | 1 +
2 files changed, 2 insertions(+)

diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
index 4009d37d5f91..0b2960f06c4c 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPss.c
@@ -82,6 +82,7 @@ RsaPssVerify (
EVP_PKEY_CTX *KeyCtx;
CONST EVP_MD *HashAlg;

+ Result = FALSE;
EvpRsaKey = NULL;
EvpVerifyCtx = NULL;
KeyCtx = NULL;
diff --git a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
index b66b6f7296ad..ece765f9ae0a 100644
--- a/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
+++ b/CryptoPkg/Library/BaseCryptLib/Pk/CryptRsaPssSign.c
@@ -97,6 +97,7 @@ RsaPssSign (
EVP_PKEY_CTX *KeyCtx;
CONST EVP_MD *HashAlg;

+ Result = FALSE;
EvpRsaKey = NULL;
EvpVerifyCtx = NULL;
KeyCtx = NULL;
--
2.17.6


Re: [PATCH] UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation

Ni, Ray
 

Laszlo, Do you think that another API is also needed: GetPhysicalAddressWidth() that returns number 36/52? physical address width is needed by (besides those that rely on the width for mask calculation): UefiCpuPkg\CpuMpPei\CpuPaging.c UefiCpuPkg\PiSmmCpuDxeSmm\X64\PageTbl.c MdeModulePkg\Core\DxeIplPeim\X64\VirtualMemory.c MdeModulePkg\Universal\Acpi\S3SaveStateDxe\AcpiS3ContextSave.c MdeModulePkg\Universal\CapsulePei\UefiCapsule.c MdePkg\Library\SmmIoLib\SmmIoLib.c OvmfPkg\XenPlatformPei\MemDetect.c UefiCpuPkg\Universal\Acpi\S3Resume2Pei\S3Resume.c UefiPayloadPkg\UefiPayloadEntry\X64\VirtualMemory.c

GetPhysicalAddressMask() can call GetPhysicalAddressWidth().

Since it's a large-scale change but the SMM high MMIO access bug is critical/urgent, I prefer to firstly push this bug fix change and then work on the new APIs.

https://bugzilla.tianocore.org/show_bug.cgi?id=3394 was submitted to capture this.


Re: 回复: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer

Lendacky, Thomas
 

On 5/14/21 2:54 PM, Lendacky, Thomas via groups.io wrote:
On 5/10/21 10:04 PM, gaoliming via groups.io wrote:
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Thanks, Liming.

Sorry, for the delay, your email ended up in my Spam folder... urg, IT at
its best. Anyway...

The patch is changing enough that I don't think I should add your
Reviewed-by: just yet. Look for a new version soon.
Ugh, I thought this was for AP reset stack... wrong patch. Disregard.

Thanks,
Tom


Thanks,
Tom


-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Lendacky,
Thomas
发送时间: 2021年5月10日 22:25
收件人: devel@edk2.groups.io
抄送: Brijesh Singh <brijesh.singh@amd.com>; Eric Dong
<eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Laszlo Ersek
<lersek@redhat.com>; Rahul Kumar <rahul1.kumar@intel.com>
主题: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to
SEV-ES jump table pointer

BZ: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3385&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C0587fecbb35842c6d81408d9171212b5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566188656978758%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=sdSuHzrY%2BTfhad8aLKLSHvnPnL91CqHxclfH5E07aAc%3D&amp;reserved=0

A VS2012 build fails with a cast conversion warning when the SEV-ES work
area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.

When casting from a PCD value to a pointer, the cast should first be done
to a UINTN and then to the pointer. Update the code to perform a cast to
a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 3d945972a025..dc2a54aa31e8 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1265,7 +1265,7 @@ SetSevEsJumpTable (
UINT32 Offset, InsnByte;
UINT8 LoNib, HiNib;

- JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32
(PcdSevEsWorkAreaBase);
+ JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32
(PcdSevEsWorkAreaBase);
ASSERT (JmpFar != NULL);

//
--
2.31.0














[PATCH v2] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324

The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed so that
when PcdSevEsIsEnabled is true, they will track the previous reset buffer
allocation in order to ensure that the new buffer allocation is below the
previous allocation. When PcdSevEsIsEnabled is false, the original logic
is followed.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Marvin Häuser <mhaeuser@posteo.de>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>

---

Changes since v1:
- Renamed the wakeup buffer variables to be unique in the PEI and DXE
libraries and to make it obvious they are SEV-ES specific.
- Use PcdGetBool (PcdSevEsIsEnabled) to make the changes regression-free
so that the new support is only use for SEV-ES guests.
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 19 +++++++-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 49 +++++++++++++-------
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 19 +++++++-
3 files changed, 69 insertions(+), 18 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..93fc63bf93e3 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID *mReservedApLoopFunc = NULL;
UINTN mReservedTopOfApStack;
volatile UINT32 mNumberToFinish = 0;

+//
+// Begin wakeup buffer allocation below 0x88000
+//
+STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000;
+
/**
Enable Debug Agent to support source debugging on AP function.

@@ -102,7 +107,14 @@ GetWakeupBuffer (
// LagacyBios driver depends on CPU Arch protocol which guarantees below
// allocation runs earlier than LegacyBios driver.
//
- StartAddress = 0x88000;
+ if (PcdGetBool (PcdSevEsIsEnabled)) {
+ //
+ // SEV-ES Wakeup buffer should be under 0x88000 and under any previous one
+ //
+ StartAddress = mSevEsDxeWakeupBuffer;
+ } else {
+ StartAddress = 0x88000;
+ }
Status = gBS->AllocatePages (
AllocateMaxAddress,
MemoryType,
@@ -112,6 +124,11 @@ GetWakeupBuffer (
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+ } else if (PcdGetBool (PcdSevEsIsEnabled)) {
+ //
+ // Next SEV-ES wakeup buffer allocation must be below this allocation
+ //
+ mSevEsDxeWakeupBuffer = StartAddress;
}

DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..b9a06747edbf 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
AddressMap->SwitchToRealSize +
sizeof (MP_CPU_EXCHANGE_INFO);

- //
- // The AP reset stack is only used by SEV-ES guests. Do not add to the
- // allocation if SEV-ES is not enabled.
- //
- if (PcdGetBool (PcdSevEsIsEnabled)) {
- //
- // Stack location is based on APIC ID, so use the total number of
- // processors for calculating the total stack area.
- //
- Size += AP_RESET_STACK_SIZE * PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
-
- Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
- }
-
return Size;
}

@@ -1192,6 +1178,7 @@ AllocateResetVector (
)
{
UINTN ApResetVectorSize;
+ UINTN ApResetStackSize;

if (CpuMpData->WakeupBuffer == (UINTN) -1) {
ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);
@@ -1207,9 +1194,39 @@ AllocateResetVector (
CpuMpData->AddressMap.ModeTransitionOffset
);
//
- // The reset stack starts at the end of the buffer.
+ // The AP reset stack is only used by SEV-ES guests. Do not allocate it
+ // if SEV-ES is not enabled.
//
- CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + ApResetVectorSize;
+ if (PcdGetBool (PcdSevEsIsEnabled)) {
+ //
+ // Stack location is based on ProcessorNumber, so use the total number
+ // of processors for calculating the total stack area.
+ //
+ ApResetStackSize = (AP_RESET_STACK_SIZE *
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
+
+ //
+ // Invoke GetWakeupBuffer a second time to allocate the stack area
+ // below 1MB. The returned buffer will be page aligned and sized and
+ // below the previously allocated buffer.
+ //
+ CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer (ApResetStackSize);
+
+ //
+ // Check to be sure that the "allocate below" behavior hasn't changed.
+ // This will also catch a failed allocation, as "-1" is returned on
+ // failure.
+ //
+ if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "SEV-ES AP reset stack is not below wakeup buffer\n"
+ ));
+
+ ASSERT (FALSE);
+ CpuDeadLoop ();
+ }
+ }
}
BackupAndPrepareWakeupBuffer (CpuMpData);
}
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..90015c650c68 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
#include <Guid/S3SmmInitDone.h>
#include <Ppi/ShadowMicrocode.h>

+STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
+
/**
S3 SMM Init Done notification function.

@@ -220,7 +222,13 @@ GetWakeupBuffer (
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
- if (WakeupBufferEnd > BASE_1MB) {
+ if (PcdGetBool (PcdSevEsIsEnabled) &&
+ WakeupBufferEnd > mSevEsPeiWakeupBuffer) {
+ //
+ // SEV-ES Wakeup buffer should be under 1MB and under any previous one
+ //
+ WakeupBufferEnd = mSevEsPeiWakeupBuffer;
+ } else if (WakeupBufferEnd > BASE_1MB) {
//
// Wakeup buffer should be under 1MB
//
@@ -244,6 +252,15 @@ GetWakeupBuffer (
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize));
+
+ if (PcdGetBool (PcdSevEsIsEnabled)) {
+ //
+ // Next SEV-ES wakeup buffer allocation must be below this
+ // allocation
+ //
+ mSevEsPeiWakeupBuffer = WakeupBufferStart;
+ }
+
return (UINTN)WakeupBufferStart;
}
}
--
2.31.0


Re: 回复: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer

Lendacky, Thomas
 

On 5/10/21 10:04 PM, gaoliming via groups.io wrote:
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Thanks, Liming.

Sorry, for the delay, your email ended up in my Spam folder... urg, IT at
its best. Anyway...

The patch is changing enough that I don't think I should add your
Reviewed-by: just yet. Look for a new version soon.

Thanks,
Tom


-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Lendacky,
Thomas
发送时间: 2021年5月10日 22:25
收件人: devel@edk2.groups.io
抄送: Brijesh Singh <brijesh.singh@amd.com>; Eric Dong
<eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Laszlo Ersek
<lersek@redhat.com>; Rahul Kumar <rahul1.kumar@intel.com>
主题: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to
SEV-ES jump table pointer

BZ: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3385&;data=04%7C01%7Cthomas.lendacky%40amd.com%7Ce447839eff4f4dfcf2f408d9142974b8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566181281381668%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Hy8B0K8gLfdQyPFtkIQlYGQ82r2f5x%2BRf0PkWilprjc%3D&amp;reserved=0

A VS2012 build fails with a cast conversion warning when the SEV-ES work
area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.

When casting from a PCD value to a pointer, the cast should first be done
to a UINTN and then to the pointer. Update the code to perform a cast to
a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 3d945972a025..dc2a54aa31e8 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1265,7 +1265,7 @@ SetSevEsJumpTable (
UINT32 Offset, InsnByte;
UINT8 LoNib, HiNib;

- JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32
(PcdSevEsWorkAreaBase);
+ JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32
(PcdSevEsWorkAreaBase);
ASSERT (JmpFar != NULL);

//
--
2.31.0











Re: [PATCH] Maintainers.txt: add Sami Mujawar as top-level ArmVirtPkg reviewer

Ard Biesheuvel
 

On Fri, 14 May 2021 at 16:59, Sami Mujawar <Sami.Mujawar@arm.com> wrote:

Hi Laszlo,

I can help with the reviews for ArmVirtPkg.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 14/05/2021, 12:49, "Laszlo Ersek" <lersek@redhat.com> wrote:

For distributing ArmVirtPkg patch review tasks better, move Sami Mujawar
from the "ArmVirtPkg: Kvmtool" section to the top-level "ArmVirtPkg"
section.

Given that "ArmVirtPkg: Kvmtool" remains without a specific "R" role,
remove "ArmVirtPkg: Kvmtool" altogether.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Julien Grall <julien@xen.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
Maintainers.txt | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index cafe6b1ab85d..1ec9185e70b9 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -143,33 +143,24 @@ M: Ard Biesheuvel <ardb+tianocore@kernel.org>
ArmVirtPkg
F: ArmVirtPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/ArmVirtPkg
M: Laszlo Ersek <lersek@redhat.com>
M: Ard Biesheuvel <ardb+tianocore@kernel.org>
R: Leif Lindholm <leif@nuviainc.com>
+R: Sami Mujawar <sami.mujawar@arm.com>

ArmVirtPkg: modules used on Xen
F: ArmVirtPkg/ArmVirtXen.*
F: ArmVirtPkg/Library/XenArmGenericTimerVirtCounterLib/
F: ArmVirtPkg/Library/XenVirtMemInfoLib/
F: ArmVirtPkg/PrePi/
F: ArmVirtPkg/XenAcpiPlatformDxe/
F: ArmVirtPkg/XenPlatformHasAcpiDtDxe/
F: ArmVirtPkg/XenioFdtDxe/
R: Julien Grall <julien@xen.org>

-ArmVirtPkg: Kvmtool emulated platform support
-F: ArmVirtPkg/ArmVirtKvmTool.*
-F: ArmVirtPkg/KvmtoolPlatformDxe/
-F: ArmVirtPkg/Library/Fdt16550SerialPortHookLib/
-F: ArmVirtPkg/Library/KvmtoolPlatformPeiLib/
-F: ArmVirtPkg/Library/KvmtoolRtcFdtClientLib/
-F: ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/
-F: ArmVirtPkg/Library/NorFlashKvmtoolLib/
-R: Sami Mujawar <sami.mujawar@arm.com>
-
BaseTools
F: BaseTools/
W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
M: Bob Feng <bob.c.feng@intel.com>
M: Liming Gao <gaoliming@byosoft.com.cn>
R: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>


Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Marvin Häuser
 

On 14.05.21 17:23, Lendacky, Thomas wrote:
On 5/14/21 10:04 AM, Marvin Häuser wrote:
Good day Thomas,
Hi Marvin,

Thank you very much for the quick patch. Comments inline.

Best regards,
Marvin

On 11.05.21 22:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3324&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C25d0b0bdc5d14a8bc4ff08d916e99c10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566014883375137%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=8%2BywcjFoZ00AymlBdxt%2BMCP0JClc64soY6pwcfz08zo%3D&amp;reserved=0


The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed to track
the previous reset buffer allocation in order to ensure that the new
buffer allocation is below the previous allocation.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
  UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 12 ++++-
  UefiCpuPkg/Library/MpInitLib/MpLib.c    | 48 +++++++++++++-------
  UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 14 ++++--
  3 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..fdfa0755d37a 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID             *mReservedApLoopFunc = NULL;
  UINTN            mReservedTopOfApStack;
  volatile UINT32  mNumberToFinish = 0;
  +//
+// Begin wakeup buffer allocation below 0x88000
+//
This definitely is not an issue of your patch at all, but I find the
comments of the behaviour very lacking. Might this be a good opportunity
to briefly document it? It took me quite a bit of git blame to fully
figure it out, especially due to the non-descriptive commit message. The
constant is explained very well in the description:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2%2Fcommit%2Fe4ff6349bf9ee4f3f392141374901ea4994e043e&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C25d0b0bdc5d14a8bc4ff08d916e99c10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566014883375137%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=NHR7dQjJbXQK5j4zc0ni0Q%2FZtOQp7szwDEzpHY6V9Dc%3D&amp;reserved=0
I think a separate patch would be best... and since you understand it so
well now, maybe something you could submit :)
:)

+STATIC EFI_PHYSICAL_ADDRESS mWakeupBuffer = 0x88000;
Hmm, I wonder whether a global variable is the best solution here. With an
explanation from the commit above, a top-down allocator makes good sense
for this scenario. However, a "GetWakeupBuffer(Size, MaxAddress)" function
might be more self-descriptive. What do you think?
Given the previous comments to not introduce any regressions in the
non-SEV-ES path, it is probably not a good idea to change this as part of
this patch. A separate distinct patch would be best.

But understand that GetWakeupBuffer() has a different implementation in
PEI and DXE. The only common thing is that GetWakeupBuffer() knows to be
under 1MB. PEI doesn't have the 0x88000 limitation that DXE does, so I
don't think the MaxAddress parameter helps here.
For now you are right, yes. There currently is an open ticket which would likely be resolved by aligning the PEI behaviour with DXE, which would resolve this issue as well. But also better to push to a separate thread, sorry.

+
  /**
    Enable Debug Agent to support source debugging on AP function.
  @@ -102,7 +107,7 @@ GetWakeupBuffer (
    // LagacyBios driver depends on CPU Arch protocol which guarantees
below
    // allocation runs earlier than LegacyBios driver.
    //
-  StartAddress = 0x88000;
+  StartAddress = mWakeupBuffer;
    Status = gBS->AllocatePages (
                    AllocateMaxAddress,
                    MemoryType,
@@ -112,6 +117,11 @@ GetWakeupBuffer (
    ASSERT_EFI_ERROR (Status);
    if (EFI_ERROR (Status)) {
      StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+  } else {
+    //
+    // Next wakeup buffer allocation must be below this allocation
+    //
+    mWakeupBuffer = StartAddress;
    }
      DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize =
%x\n",
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..a76dae437606 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
             AddressMap->SwitchToRealSize +
             sizeof (MP_CPU_EXCHANGE_INFO);
  -  //
-  // The AP reset stack is only used by SEV-ES guests. Do not add to the
-  // allocation if SEV-ES is not enabled.
-  //
-  if (PcdGetBool (PcdSevEsIsEnabled)) {
-    //
-    // Stack location is based on APIC ID, so use the total number of
-    // processors for calculating the total stack area.
-    //
-    Size += AP_RESET_STACK_SIZE * PcdGet32
(PcdCpuMaxLogicalProcessorNumber);
-
-    Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
-  }
-
    return Size;
  }
  @@ -1207,9 +1193,39 @@ AllocateResetVector (
CpuMpData->AddressMap.ModeTransitionOffset
                                      );
      //
-    // The reset stack starts at the end of the buffer.
+    // The AP reset stack is only used by SEV-ES guests. Do not
allocate it
+    // if SEV-ES is not enabled.
      //
-    CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer +
ApResetVectorSize;
+    if (PcdGetBool (PcdSevEsIsEnabled)) {
+      UINTN  ApResetStackSize;
Personally, I do not mind this at all, but I think the code style
prohibits declaring variables in inner scopes. Though preferably I would
like to see this, nowadays, arbitrary restriction lifted rather than the
patch be changed. Do the package maintainers have comments on this?
Yup, noted in other comments. So the variable will be moved.
Thx

+
+      //
+      // Stack location is based on ProcessorNumber, so use the total
number
+      // of processors for calculating the total stack area.
+      //
+      ApResetStackSize = AP_RESET_STACK_SIZE *
+                           PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
+
+      //
+      // Invoke GetWakeupBuffer a second time to allocate the stack area
+      // below 1MB. The returned buffer will be page aligned and sized and
+      // below the previously allocated buffer.
+      //
+      CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer
(ApResetStackSize);
+
+      //
+      // Check to be sure that the "allocate below" behavior hasn't
changed.
+      // This will also catch a failed allocation, as "-1" is returned on
+      // failure.
+      //
+      if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+        DEBUG ((DEBUG_ERROR,
+          "SEV-ES AP reset stack is not below wakeup buffer\n"));
+
+        ASSERT (FALSE);
Should the ASSERT not only catch the broken "allocate below" behaviour,
i.e. not trigger on failed allocation?
I think it's best to trigger on a failed allocation as well rather than
continuing and allowing a page fault or some other problem to occur.
Well, it should handle the error in a safe way, i.e. the deadloop below. To not ASSERT on plausible conditions is a common design guideline in most low-level projects including Linux kernel.

Best regards,
Marvin

Thanks,
Tom

+        CpuDeadLoop ();
+      }
+    }
    }
    BackupAndPrepareWakeupBuffer (CpuMpData);
  }
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..4d09e89b4128 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
  #include <Guid/S3SmmInitDone.h>
  #include <Ppi/ShadowMicrocode.h>
  +STATIC UINT64 mWakeupBuffer = BASE_1MB;
+
  /**
    S3 SMM Init Done notification function.
  @@ -220,11 +222,11 @@ GetWakeupBuffer (
          // Need memory under 1MB to be collected here
          //
          WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart +
Hob.ResourceDescriptor->ResourceLength;
-        if (WakeupBufferEnd > BASE_1MB) {
+        if (WakeupBufferEnd > mWakeupBuffer) {
            //
-          // Wakeup buffer should be under 1MB
+          // Wakeup buffer should be under 1MB and under the previous one
            //
-          WakeupBufferEnd = BASE_1MB;
+          WakeupBufferEnd = mWakeupBuffer;
          }
          while (WakeupBufferEnd > WakeupBufferSize) {
            //
@@ -244,6 +246,12 @@ GetWakeupBuffer (
            }
            DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x,
WakeupBufferSize = %x\n",
                                 WakeupBufferStart, WakeupBufferSize));
+
+          //
+          // Next wakeup buffer allocation must be below this allocation
+          //
+          mWakeupBuffer = WakeupBufferStart;
+
            return (UINTN)WakeupBufferStart;
          }
        }


Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Lendacky, Thomas
 

On 5/14/21 10:04 AM, Marvin Häuser wrote:
Good day Thomas,
Hi Marvin,


Thank you very much for the quick patch. Comments inline.

Best regards,
Marvin

On 11.05.21 22:50, Lendacky, Thomas wrote:
BZ:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3324&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C25d0b0bdc5d14a8bc4ff08d916e99c10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566014883375137%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=8%2BywcjFoZ00AymlBdxt%2BMCP0JClc64soY6pwcfz08zo%3D&amp;reserved=0


The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed to track
the previous reset buffer allocation in order to ensure that the new
buffer allocation is below the previous allocation.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
  UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 12 ++++-
  UefiCpuPkg/Library/MpInitLib/MpLib.c    | 48 +++++++++++++-------
  UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 14 ++++--
  3 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..fdfa0755d37a 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID             *mReservedApLoopFunc = NULL;
  UINTN            mReservedTopOfApStack;
  volatile UINT32  mNumberToFinish = 0;
  +//
+// Begin wakeup buffer allocation below 0x88000
+//
This definitely is not an issue of your patch at all, but I find the
comments of the behaviour very lacking. Might this be a good opportunity
to briefly document it? It took me quite a bit of git blame to fully
figure it out, especially due to the non-descriptive commit message. The
constant is explained very well in the description:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2%2Fcommit%2Fe4ff6349bf9ee4f3f392141374901ea4994e043e&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C25d0b0bdc5d14a8bc4ff08d916e99c10%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637566014883375137%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=NHR7dQjJbXQK5j4zc0ni0Q%2FZtOQp7szwDEzpHY6V9Dc%3D&amp;reserved=0
I think a separate patch would be best... and since you understand it so
well now, maybe something you could submit :)


+STATIC EFI_PHYSICAL_ADDRESS mWakeupBuffer = 0x88000;
Hmm, I wonder whether a global variable is the best solution here. With an
explanation from the commit above, a top-down allocator makes good sense
for this scenario. However, a "GetWakeupBuffer(Size, MaxAddress)" function
might be more self-descriptive. What do you think?
Given the previous comments to not introduce any regressions in the
non-SEV-ES path, it is probably not a good idea to change this as part of
this patch. A separate distinct patch would be best.

But understand that GetWakeupBuffer() has a different implementation in
PEI and DXE. The only common thing is that GetWakeupBuffer() knows to be
under 1MB. PEI doesn't have the 0x88000 limitation that DXE does, so I
don't think the MaxAddress parameter helps here.


+
  /**
    Enable Debug Agent to support source debugging on AP function.
  @@ -102,7 +107,7 @@ GetWakeupBuffer (
    // LagacyBios driver depends on CPU Arch protocol which guarantees
below
    // allocation runs earlier than LegacyBios driver.
    //
-  StartAddress = 0x88000;
+  StartAddress = mWakeupBuffer;
    Status = gBS->AllocatePages (
                    AllocateMaxAddress,
                    MemoryType,
@@ -112,6 +117,11 @@ GetWakeupBuffer (
    ASSERT_EFI_ERROR (Status);
    if (EFI_ERROR (Status)) {
      StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+  } else {
+    //
+    // Next wakeup buffer allocation must be below this allocation
+    //
+    mWakeupBuffer = StartAddress;
    }
      DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize =
%x\n",
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..a76dae437606 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
             AddressMap->SwitchToRealSize +
             sizeof (MP_CPU_EXCHANGE_INFO);
  -  //
-  // The AP reset stack is only used by SEV-ES guests. Do not add to the
-  // allocation if SEV-ES is not enabled.
-  //
-  if (PcdGetBool (PcdSevEsIsEnabled)) {
-    //
-    // Stack location is based on APIC ID, so use the total number of
-    // processors for calculating the total stack area.
-    //
-    Size += AP_RESET_STACK_SIZE * PcdGet32
(PcdCpuMaxLogicalProcessorNumber);
-
-    Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
-  }
-
    return Size;
  }
  @@ -1207,9 +1193,39 @@ AllocateResetVector (
                                     
CpuMpData->AddressMap.ModeTransitionOffset
                                      );
      //
-    // The reset stack starts at the end of the buffer.
+    // The AP reset stack is only used by SEV-ES guests. Do not
allocate it
+    // if SEV-ES is not enabled.
      //
-    CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer +
ApResetVectorSize;
+    if (PcdGetBool (PcdSevEsIsEnabled)) {
+      UINTN  ApResetStackSize;
Personally, I do not mind this at all, but I think the code style
prohibits declaring variables in inner scopes. Though preferably I would
like to see this, nowadays, arbitrary restriction lifted rather than the
patch be changed. Do the package maintainers have comments on this?
Yup, noted in other comments. So the variable will be moved.


+
+      //
+      // Stack location is based on ProcessorNumber, so use the total
number
+      // of processors for calculating the total stack area.
+      //
+      ApResetStackSize = AP_RESET_STACK_SIZE *
+                           PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
+
+      //
+      // Invoke GetWakeupBuffer a second time to allocate the stack area
+      // below 1MB. The returned buffer will be page aligned and sized and
+      // below the previously allocated buffer.
+      //
+      CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer
(ApResetStackSize);
+
+      //
+      // Check to be sure that the "allocate below" behavior hasn't
changed.
+      // This will also catch a failed allocation, as "-1" is returned on
+      // failure.
+      //
+      if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+        DEBUG ((DEBUG_ERROR,
+          "SEV-ES AP reset stack is not below wakeup buffer\n"));
+
+        ASSERT (FALSE);
Should the ASSERT not only catch the broken "allocate below" behaviour,
i.e. not trigger on failed allocation?
I think it's best to trigger on a failed allocation as well rather than
continuing and allowing a page fault or some other problem to occur.

Thanks,
Tom


+        CpuDeadLoop ();
+      }
+    }
    }
    BackupAndPrepareWakeupBuffer (CpuMpData);
  }
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..4d09e89b4128 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
  #include <Guid/S3SmmInitDone.h>
  #include <Ppi/ShadowMicrocode.h>
  +STATIC UINT64 mWakeupBuffer = BASE_1MB;
+
  /**
    S3 SMM Init Done notification function.
  @@ -220,11 +222,11 @@ GetWakeupBuffer (
          // Need memory under 1MB to be collected here
          //
          WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart +
Hob.ResourceDescriptor->ResourceLength;
-        if (WakeupBufferEnd > BASE_1MB) {
+        if (WakeupBufferEnd > mWakeupBuffer) {
            //
-          // Wakeup buffer should be under 1MB
+          // Wakeup buffer should be under 1MB and under the previous one
            //
-          WakeupBufferEnd = BASE_1MB;
+          WakeupBufferEnd = mWakeupBuffer;
          }
          while (WakeupBufferEnd > WakeupBufferSize) {
            //
@@ -244,6 +246,12 @@ GetWakeupBuffer (
            }
            DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x,
WakeupBufferSize = %x\n",
                                 WakeupBufferStart, WakeupBufferSize));
+
+          //
+          // Next wakeup buffer allocation must be below this allocation
+          //
+          mWakeupBuffer = WakeupBufferStart;
+
            return (UINTN)WakeupBufferStart;
          }
        }


Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Marvin Häuser
 

Good day Thomas,

Thank you very much for the quick patch. Comments inline.

Best regards,
Marvin

On 11.05.21 22:50, Lendacky, Thomas wrote:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324

The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed to track
the previous reset buffer allocation in order to ensure that the new
buffer allocation is below the previous allocation.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 12 ++++-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 48 +++++++++++++-------
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 14 ++++--
3 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..fdfa0755d37a 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID *mReservedApLoopFunc = NULL;
UINTN mReservedTopOfApStack;
volatile UINT32 mNumberToFinish = 0;
+//
+// Begin wakeup buffer allocation below 0x88000
+//
This definitely is not an issue of your patch at all, but I find the comments of the behaviour very lacking. Might this be a good opportunity to briefly document it? It took me quite a bit of git blame to fully figure it out, especially due to the non-descriptive commit message. The constant is explained very well in the description: https://github.com/tianocore/edk2/commit/e4ff6349bf9ee4f3f392141374901ea4994e043e

+STATIC EFI_PHYSICAL_ADDRESS mWakeupBuffer = 0x88000;
Hmm, I wonder whether a global variable is the best solution here. With an explanation from the commit above, a top-down allocator makes good sense for this scenario. However, a "GetWakeupBuffer(Size, MaxAddress)" function might be more self-descriptive. What do you think?

+
/**
Enable Debug Agent to support source debugging on AP function.
@@ -102,7 +107,7 @@ GetWakeupBuffer (
// LagacyBios driver depends on CPU Arch protocol which guarantees below
// allocation runs earlier than LegacyBios driver.
//
- StartAddress = 0x88000;
+ StartAddress = mWakeupBuffer;
Status = gBS->AllocatePages (
AllocateMaxAddress,
MemoryType,
@@ -112,6 +117,11 @@ GetWakeupBuffer (
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+ } else {
+ //
+ // Next wakeup buffer allocation must be below this allocation
+ //
+ mWakeupBuffer = StartAddress;
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..a76dae437606 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
AddressMap->SwitchToRealSize +
sizeof (MP_CPU_EXCHANGE_INFO);
- //
- // The AP reset stack is only used by SEV-ES guests. Do not add to the
- // allocation if SEV-ES is not enabled.
- //
- if (PcdGetBool (PcdSevEsIsEnabled)) {
- //
- // Stack location is based on APIC ID, so use the total number of
- // processors for calculating the total stack area.
- //
- Size += AP_RESET_STACK_SIZE * PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
-
- Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
- }
-
return Size;
}
@@ -1207,9 +1193,39 @@ AllocateResetVector (
CpuMpData->AddressMap.ModeTransitionOffset
);
//
- // The reset stack starts at the end of the buffer.
+ // The AP reset stack is only used by SEV-ES guests. Do not allocate it
+ // if SEV-ES is not enabled.
//
- CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + ApResetVectorSize;
+ if (PcdGetBool (PcdSevEsIsEnabled)) {
+ UINTN ApResetStackSize;
Personally, I do not mind this at all, but I think the code style prohibits declaring variables in inner scopes. Though preferably I would like to see this, nowadays, arbitrary restriction lifted rather than the patch be changed. Do the package maintainers have comments on this?

+
+ //
+ // Stack location is based on ProcessorNumber, so use the total number
+ // of processors for calculating the total stack area.
+ //
+ ApResetStackSize = AP_RESET_STACK_SIZE *
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
+
+ //
+ // Invoke GetWakeupBuffer a second time to allocate the stack area
+ // below 1MB. The returned buffer will be page aligned and sized and
+ // below the previously allocated buffer.
+ //
+ CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer (ApResetStackSize);
+
+ //
+ // Check to be sure that the "allocate below" behavior hasn't changed.
+ // This will also catch a failed allocation, as "-1" is returned on
+ // failure.
+ //
+ if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+ DEBUG ((DEBUG_ERROR,
+ "SEV-ES AP reset stack is not below wakeup buffer\n"));
+
+ ASSERT (FALSE);
Should the ASSERT not only catch the broken "allocate below" behaviour, i.e. not trigger on failed allocation?

+ CpuDeadLoop ();
+ }
+ }
}
BackupAndPrepareWakeupBuffer (CpuMpData);
}
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..4d09e89b4128 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
#include <Guid/S3SmmInitDone.h>
#include <Ppi/ShadowMicrocode.h>
+STATIC UINT64 mWakeupBuffer = BASE_1MB;
+
/**
S3 SMM Init Done notification function.
@@ -220,11 +222,11 @@ GetWakeupBuffer (
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
- if (WakeupBufferEnd > BASE_1MB) {
+ if (WakeupBufferEnd > mWakeupBuffer) {
//
- // Wakeup buffer should be under 1MB
+ // Wakeup buffer should be under 1MB and under the previous one
//
- WakeupBufferEnd = BASE_1MB;
+ WakeupBufferEnd = mWakeupBuffer;
}
while (WakeupBufferEnd > WakeupBufferSize) {
//
@@ -244,6 +246,12 @@ GetWakeupBuffer (
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize));
+
+ //
+ // Next wakeup buffer allocation must be below this allocation
+ //
+ mWakeupBuffer = WakeupBufferStart;
+
return (UINTN)WakeupBufferStart;
}
}


[PATCH v1 1/1] BaseTools: build: Set ReturnCode on POSTBUILD fail

Kirkendall, Garrett
 

When build.by POSTBUILD handling section returns other than 0, set
ReturnCode to POSTBUILD_ERROR so build.py exits with return code other
than 0.

Fix for https://bugzilla.tianocore.org/show_bug.cgi?id=1977

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
---
BaseTools/Source/Python/build/build.py | 1 +
1 file changed, 1 insertion(+)

diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index 037493f0b02a..3e4d83409f49 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -2757,6 +2757,7 @@ def Main():
Conclusion = "Done"
except:
Conclusion = "Failed"
+ ReturnCode = POSTBUILD_ERROR
elif ReturnCode == ABORT_ERROR:
Conclusion = "Aborted"
else:
--
2.30.1.windows.1


[PATCH v1 0/1] BaseTools: build: Set ReturnCode on POSTBUILD fail

Kirkendall, Garrett
 

When build.by POSTBUILD handling section returns other than 0, set
ReturnCode to POSTBUILD_ERROR so build.py exits with return code other
than 0.

Fix for https://bugzilla.tianocore.org/show_bug.cgi?id=1977

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Garrett Kirkendall (1):
BaseTools: build: Set ReturnCode on POSTBUILD fail

BaseTools/Source/Python/build/build.py | 1 +
1 file changed, 1 insertion(+)

--
2.30.1.windows.1


Re: [PATCH] Maintainers.txt: add Sami Mujawar as top-level ArmVirtPkg reviewer

Sami Mujawar
 

Hi Laszlo,

I can help with the reviews for ArmVirtPkg.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 14/05/2021, 12:49, "Laszlo Ersek" <lersek@redhat.com> wrote:

For distributing ArmVirtPkg patch review tasks better, move Sami Mujawar
from the "ArmVirtPkg: Kvmtool" section to the top-level "ArmVirtPkg"
section.

Given that "ArmVirtPkg: Kvmtool" remains without a specific "R" role,
remove "ArmVirtPkg: Kvmtool" altogether.

Cc: Andrew Fish <afish@apple.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Julien Grall <julien@xen.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
Maintainers.txt | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index cafe6b1ab85d..1ec9185e70b9 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -143,33 +143,24 @@ M: Ard Biesheuvel <ardb+tianocore@kernel.org>
ArmVirtPkg
F: ArmVirtPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/ArmVirtPkg
M: Laszlo Ersek <lersek@redhat.com>
M: Ard Biesheuvel <ardb+tianocore@kernel.org>
R: Leif Lindholm <leif@nuviainc.com>
+R: Sami Mujawar <sami.mujawar@arm.com>

ArmVirtPkg: modules used on Xen
F: ArmVirtPkg/ArmVirtXen.*
F: ArmVirtPkg/Library/XenArmGenericTimerVirtCounterLib/
F: ArmVirtPkg/Library/XenVirtMemInfoLib/
F: ArmVirtPkg/PrePi/
F: ArmVirtPkg/XenAcpiPlatformDxe/
F: ArmVirtPkg/XenPlatformHasAcpiDtDxe/
F: ArmVirtPkg/XenioFdtDxe/
R: Julien Grall <julien@xen.org>

-ArmVirtPkg: Kvmtool emulated platform support
-F: ArmVirtPkg/ArmVirtKvmTool.*
-F: ArmVirtPkg/KvmtoolPlatformDxe/
-F: ArmVirtPkg/Library/Fdt16550SerialPortHookLib/
-F: ArmVirtPkg/Library/KvmtoolPlatformPeiLib/
-F: ArmVirtPkg/Library/KvmtoolRtcFdtClientLib/
-F: ArmVirtPkg/Library/KvmtoolVirtMemInfoLib/
-F: ArmVirtPkg/Library/NorFlashKvmtoolLib/
-R: Sami Mujawar <sami.mujawar@arm.com>
-
BaseTools
F: BaseTools/
W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
M: Bob Feng <bob.c.feng@intel.com>
M: Liming Gao <gaoliming@byosoft.com.cn>
R: Yuwei Chen <yuwei.chen@intel.com>

base-commit: 32928415e36b3e234efb5c24143e06060a68fba3
--
2.19.1.3.g30247aa5d201


IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Lendacky, Thomas
 

On 5/14/21 8:33 AM, Tom Lendacky wrote:
On 5/14/21 4:14 AM, Laszlo Ersek wrote:
On 05/11/21 22:50, Lendacky, Thomas wrote:
BZ: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3324&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C7c28b41e27cc4b9a8b9508d916b8a955%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637565804655837525%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ixw2PdtFLryJs9KHplJ8bvomtaqjBJF8KuDdWO5ERdw%3D&amp;reserved=0
...


@@ -220,11 +222,11 @@ GetWakeupBuffer (
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
- if (WakeupBufferEnd > BASE_1MB) {
+ if (WakeupBufferEnd > mWakeupBuffer) {
//
- // Wakeup buffer should be under 1MB
+ // Wakeup buffer should be under 1MB and under the previous one
//
- WakeupBufferEnd = BASE_1MB;
+ WakeupBufferEnd = mWakeupBuffer;
}
while (WakeupBufferEnd > WakeupBufferSize) {
//
(7) Can we use a WakeupBufferLimit helper variable here, and set it like
"StartAddress" under (2)?
Will do.
Actually, WakeupBufferEnd is like a helper variable here, so probably best
to just do:

if (PcdGetBool (PcdSevEsIsEnabled) &&
WakeupBufferEnd > mSevEsPeiWakeupBuffer) {
//
// SEV-ES Wakeup buffer should be under 1MB and under any previous one
//
WakeupBufferEnd = mSevEsPeiWakeupBuffer;
} else if (WakeupBufferEnd > BASE_1MB) {
//
// Wakeup buffer should be under 1MB
//
WakeupBufferEnd = BASE_1MB;
}

which makes for a nice diff:

@@ -220,7 +222,13 @@ GetWakeupBuffer (
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
- if (WakeupBufferEnd > BASE_1MB) {
+ if (PcdGetBool (PcdSevEsIsEnabled) &&
+ WakeupBufferEnd > mSevEsPeiWakeupBuffer) {
+ //
+ // SEV-ES Wakeup buffer should be under 1MB and under any previous one
+ //
+ WakeupBufferEnd = mSevEsPeiWakeupBuffer;
+ } else if (WakeupBufferEnd > BASE_1MB) {
//
// Wakeup buffer should be under 1MB
//

Thanks,
Tom



Re: [PATCH v1 1/1] BaseTools: Add DTCPP_FLAGS for GCC5 RISCV64 toolchain

Bob Feng
 

Reviewed-by: Bob Feng <bob.c.feng@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Daniel Schaefer
Sent: Friday, May 14, 2021 2:03 PM
To: devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Chen, Christine <yuwei.chen@intel.com>; Abner Chang <abner.chang@hpe.com>
Subject: [edk2-devel] [PATCH v1 1/1] BaseTools: Add DTCPP_FLAGS for GCC5 RISCV64 toolchain

Some/all platforms are going to require EDK2 to build a device tree and use it in the early stages of boot.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Abner Chang <abner.chang@hpe.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
BaseTools/Conf/tools_def.template | 1 +
1 file changed, 1 insertion(+)

diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 5db3f6119188..498696e583fc 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2458,6 +2458,7 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
*_GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV64_DLINK2_FLAGS)
*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
*_GCC5_RISCV64_OBJCOPY_FLAGS =
+*_GCC5_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)

####################################################################################
#
--
2.30.1


Re: [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

Lendacky, Thomas
 

On 5/14/21 4:14 AM, Laszlo Ersek wrote:
On 05/11/21 22:50, Lendacky, Thomas wrote:
BZ: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3324&;data=04%7C01%7Cthomas.lendacky%40amd.com%7C7c28b41e27cc4b9a8b9508d916b8a955%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637565804655837525%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=Ixw2PdtFLryJs9KHplJ8bvomtaqjBJF8KuDdWO5ERdw%3D&amp;reserved=0

The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed to track
the previous reset buffer allocation in order to ensure that the new
buffer allocation is below the previous allocation.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 12 ++++-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 48 +++++++++++++-------
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 14 ++++--
3 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..fdfa0755d37a 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID *mReservedApLoopFunc = NULL;
UINTN mReservedTopOfApStack;
volatile UINT32 mNumberToFinish = 0;

+//
+// Begin wakeup buffer allocation below 0x88000
+//
+STATIC EFI_PHYSICAL_ADDRESS mWakeupBuffer = 0x88000;
(1) Please rename this to mSevEsDxeWakeupBuffer. The code is correct
as-is, but regarding code editors that can jump to tags, it helps if we
eliminate duplicate identifiers.
Ok, will do here and in the PEI file.


+
/**
Enable Debug Agent to support source debugging on AP function.

@@ -102,7 +107,7 @@ GetWakeupBuffer (
// LagacyBios driver depends on CPU Arch protocol which guarantees below
// allocation runs earlier than LegacyBios driver.
//
- StartAddress = 0x88000;
+ StartAddress = mWakeupBuffer;
Status = gBS->AllocatePages (
AllocateMaxAddress,
MemoryType,
@@ -112,6 +117,11 @@ GetWakeupBuffer (
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+ } else {
+ //
+ // Next wakeup buffer allocation must be below this allocation
+ //
+ mWakeupBuffer = StartAddress;
}

DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
(2) Please make these changes conditional on "PcdSevEsIsEnabled". If the
PCD is false, the behavior of the function shouldn't change at all --
not just the caller-observable behavior, but the internal behavior either.

For the SEV-ES disabled case, it's much easier to see that the change is
regression-free if we don't just rely on GetWakeupBuffer() not being
called for a second time, but explicitly make the patch so that it does
nothing here if the PCD is false.

Something like:

if (PcdGetBool (PcdSevEsIsEnabled)) {
StartAddress = mSevEsDxeWakeupBuffer;
} else {
StartAddress = 0x88000;
}

...

if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
} else if PcdGetBool (PcdSevEsIsEnabled) {
mSevEsDxeWakeupBuffer = StartAddress;
}
Will do.


diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..a76dae437606 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
AddressMap->SwitchToRealSize +
sizeof (MP_CPU_EXCHANGE_INFO);

- //
- // The AP reset stack is only used by SEV-ES guests. Do not add to the
- // allocation if SEV-ES is not enabled.
- //
- if (PcdGetBool (PcdSevEsIsEnabled)) {
- //
- // Stack location is based on APIC ID, so use the total number of
- // processors for calculating the total stack area.
- //
- Size += AP_RESET_STACK_SIZE * PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
-
- Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
- }
-
return Size;
}
This change is clearly regression-free in case the PCD is false. OK.

@@ -1207,9 +1193,39 @@ AllocateResetVector (
CpuMpData->AddressMap.ModeTransitionOffset
);
//
- // The reset stack starts at the end of the buffer.
+ // The AP reset stack is only used by SEV-ES guests. Do not allocate it
+ // if SEV-ES is not enabled.
//
- CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + ApResetVectorSize;
+ if (PcdGetBool (PcdSevEsIsEnabled)) {
+ UINTN ApResetStackSize;
(3) While I very much like inner-block-scoped variables, and use them
heavily in ArmVirtPkg and OvmfPkg, unfortunately they are not tolerated
in the rest of edk2. Please move this variable to the top of the
function, and if necessary, put "SevEs" in its name.
Will do.


+
+ //
+ // Stack location is based on ProcessorNumber, so use the total number
+ // of processors for calculating the total stack area.
+ //
+ ApResetStackSize = AP_RESET_STACK_SIZE *
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
(4) A bit more idiomatic way to break this up:

ApResetStackSize = (AP_RESET_STACK_SIZE *
PcdGet32 (PcdCpuMaxLogicalProcessorNumber));

(indented similarly to the controlling expressions of "if", "while" ...)
Ok.


+
+ //
+ // Invoke GetWakeupBuffer a second time to allocate the stack area
+ // below 1MB. The returned buffer will be page aligned and sized and
+ // below the previously allocated buffer.
+ //
+ CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer (ApResetStackSize);
+
+ //
+ // Check to be sure that the "allocate below" behavior hasn't changed.
+ // This will also catch a failed allocation, as "-1" is returned on
+ // failure.
+ //
+ if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+ DEBUG ((DEBUG_ERROR,
+ "SEV-ES AP reset stack is not below wakeup buffer\n"));
(5) Indentation:

DEBUG ((
DEBUG_ERROR,
"SEV-ES AP reset stack is not below wakeup buffer\n"
));

(The condensed style you used is superior IMO, and I encourage it in
ArmVirtPkg and OvmfPkg, but it's not universally accepted in the rest of
edk2.)
Heh, I was trying to figure this one out and seeing multiple forms. I'll
update it.


+
+ ASSERT (FALSE);
+ CpuDeadLoop ();
+ }
+ }
}
BackupAndPrepareWakeupBuffer (CpuMpData);
}
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..4d09e89b4128 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
#include <Guid/S3SmmInitDone.h>
#include <Ppi/ShadowMicrocode.h>

+STATIC UINT64 mWakeupBuffer = BASE_1MB;
+
/**
S3 SMM Init Done notification function.
(6) Please rename this to mSevEsPeiWakeupBuffer. (Same argument as in (1).)
Yup.


@@ -220,11 +222,11 @@ GetWakeupBuffer (
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
- if (WakeupBufferEnd > BASE_1MB) {
+ if (WakeupBufferEnd > mWakeupBuffer) {
//
- // Wakeup buffer should be under 1MB
+ // Wakeup buffer should be under 1MB and under the previous one
//
- WakeupBufferEnd = BASE_1MB;
+ WakeupBufferEnd = mWakeupBuffer;
}
while (WakeupBufferEnd > WakeupBufferSize) {
//
(7) Can we use a WakeupBufferLimit helper variable here, and set it like
"StartAddress" under (2)?
Will do.


@@ -244,6 +246,12 @@ GetWakeupBuffer (
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize));
+
+ //
+ // Next wakeup buffer allocation must be below this allocation
+ //
+ mWakeupBuffer = WakeupBufferStart;
+
return (UINTN)WakeupBufferStart;
}
}
(8) And IMO I think we should adjust mSevEsPeiWakeupBuffer here
conditionally on the PCD as well.
Will do.

Thanks,
Tom


Thanks!
Laszlo

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