Date   

Re: [PATCH] MdeModulePkg: Retrive boot manager menu from any fv

Wu, Hao A
 

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Monday, May 10, 2021 5:00 PM
To: Wu, Hao A <hao.a.wu@intel.com>; devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Gao, Zhichao
<zhichao.gao@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg: Retrive boot manager menu
from any fv

Hi Hao,

I don't have the data about the boot performance.
However, I think it has little impact for the originally working platforms.
In function GetSectionFromAnyFv, It will first search section in current FV.
If it finds the section, it will return succuss.
Only if it can't find the section, it will take extra time to search in other FV. This
case won't happen in originally working platforms

Thanks Zhiguang.
The implementation of GetSectionFromAnyFv() will try searching the caller's FFS first, so there should be no impact to currently working platforms.

Could you help to update the function comments for BmRegisterBootManagerMenu() to reflect this change (first searching the same FV, if fails then all FVs).
With this handled:
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>

Hello Zhichao and Ray, do you have comments for this patch? Thanks in advance.

Best Regards,
Hao Wu



Thanks
Zhiguang

-----Original Message-----
From: Wu, Hao A <hao.a.wu@intel.com>
Sent: Monday, May 10, 2021 4:42 PM
To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Gao, Zhichao
<zhichao.gao@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg: Retrive boot manager
menu from any fv

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Zhiguang Liu
Sent: Monday, May 10, 2021 4:16 PM
To: devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A
<hao.a.wu@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>; Ni, Ray
<ray.ni@intel.com>
Subject: [edk2-devel] [PATCH] MdeModulePkg: Retrive boot manager
menu
from any fv

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384

Currently, UefiBootManagerLib has the below assumption:
Assume the BootManagerMenuFile is in the same FV as the module
links to this library.
It has some limitation now, so remove the assumption.

Hello Zhiguang,

Sorry for a question. Do you know what is the boot performance impact
if 'GetSectionFromAnyFv()' is being used?
Any data on the impact for originally working platforms?

Best Regards,
Hao Wu



Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
index 6cc34d29c0..b8df4d590f 100644
--- a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
+++ b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
@@ -2,7 +2,7 @@
Library functions which relates with booting. Copyright (c)
2019, NVIDIA CORPORATION. All rights reserved.-Copyright (c) 2011 -
2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2011
- 2021, Intel Corporation. All rights reserved.<BR> (C) Copyright
2015-2021 Hewlett Packard Enterprise Development LP<BR> SPDX-License-
Identifier:
BSD-2- Clause-Patent @@ -2385,7 +2385,6 @@
EfiBootManagerRefreshAllBootOption (
This function is called to get or create the boot option for the
Boot
Manager
Menu. The Boot Manager Menu is shown after successfully booting a
boot
option.- Assume the BootManagerMenuFile is in the same FV as the
module
links to this library. @param BootOption Return the boot option of the
Boot Manager Menu @@ -2437,7 +2436,7 @@
BmRegisterBootManagerMenu (
if (DevicePath == NULL) { Data = NULL;- Status = GetSectionFromFv (+
Status = GetSectionFromAnyFv ( PcdGetPtr
(PcdBootManagerMenuFile), EFI_SECTION_PE32, 0,@@ -
2455,7 +2454,7 @@ BmRegisterBootManagerMenu (
// // Get BootManagerMenu application's description from EFI User
Interface Section. //- Status = GetSectionFromFv (+ Status =
GetSectionFromAnyFv ( PcdGetPtr (PcdBootManagerMenuFile),
EFI_SECTION_USER_INTERFACE, 0,--
2.30.0.windows.2



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Re: Build fails with VS2012

Rebecca Cran
 

Thanks. The obvious toolchains that are missing from ReadMe.rst are any versions of XCODE and CLANG.
Also, it might be nice to specify _which_ GCC5 versions are supported, since that covers gcc 5 through 11 and gcc 5.x currently causes a build error. We maybe only care about gcc 7 and newer these days?

I just tried building with VS2015 and VS2013, and there was a build error because it seems the location of rc.exe has changed. After fixing that they successfully built OVMF. But it sounds like we possibly only want to make sure that VS2017 and VS2019 are kept working now.

I've cc'd Bret and Sean because I'm wondering if there are plans to add more toolchain/OS combinations into the GitHub/Azure solution? For example adding macOS with XCODE5? Also, how about post-commit or nightly builds that run more extensive tests, possibly generating binaries for OVMF that people can try without building it themselves? Or would that be something that might be useful for me to implement as a third-party solution?

--
Rebecca Cran

On 5/10/21 5:31 PM, Michael D Kinney wrote:
I think there a few categories of tool chains:
1) Tool chains that are in tools_def.txt and are used by EDK II CI to perform pre-commit and post-commit changes. These are documented in Readme.rst
2) Tool chains that are in tools_def.txt that are fully supported by the EDK II community. Should be documented in Readme.rst.
3) Tool chains that are in tools_def.txt, but are not supported by the EDK II community, but some downstream consumers use the tool chain are willing to fix issues that impact them.
4) Tool chains that are in tools_def.txt, but are not used by anyone.
We need to make sure we document (1), (2), and (3) so we can identify and delete (4) from tools_def.txt.
Thanks,
Mike

-----Original Message-----
From: Rebecca Cran <rebecca@nuviainc.com>
Sent: Monday, May 10, 2021 6:21 AM
To: devel@edk2.groups.io; lersek@redhat.com; rebecca@bsdio.com
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: [edk2-devel] Build fails with VS2012

On 5/10/21 5:56 AM, Laszlo Ersek wrote:
Hi Rebecca

+Tom

On 05/08/21 21:47, Rebecca Cran wrote:
I'm setting up a new Jenkins server to do Bhyve builds and run on
platforms that aren't currently tested with the GitHub/Azure system.

Since VS2012 appears to be a supported toolchain, I tried building
OvmfPkgX64 with it (I'm also planning on testing VS2013, VS2015, VS2017
and VS2019), but it fails with:


Building ...
c:\users\administrator\src\edk2\NetworkPkg\Library\DxeUdpIoLib\DxeUdpIoLib.inf
[X64]
c:\users\administrator\src\edk2\UefiCpuPkg\Library\MpInitLib\MpLib.c(1268)
: error C2220: warning treated as error - no 'object' file generated
c:\users\administrator\src\edk2\UefiCpuPkg\Library\MpInitLib\MpLib.c(1268)
: warning C4306: 'type cast' : conversion from 'int' to
'SEV_ES_AP_JMP_FAR *' of greater size
I think the compiler is justified to complain here:

7b7508ad784d1 (Tom Lendacky 2020-08-12 15:21:42 -0500 1268) JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32
(PcdSevEsWorkAreaBase);

The proper way to spell such casts is with (UINTN) in the middle.

Can you please file a new BZ?
I've created https://bugzilla.tianocore.org/show_bug.cgi?id=3385

I know the GitHub/Azure system only tests with VS2017 and VS2019: are
there plans to drop the older VS versions, or should they still work?
And would it be considered useful to _check_ that they still work, or
should they be considered unsupported?
I'd suggest dropping them.

Earlier, Ard raised a similar question for gcc too -- IIRC, Ard suggested that GCC4* be removed. I agree with the idea.
Thanks. If we're ready to go ahead, should I create a patch to remove them?

Do you know what the new minimum version of gcc should then be? I'd like
to run builds with it so we can catch any issues.

Would we remove all VS versions except VS2017 and VS2019, or would we
keep others like VS2015 for now?

--
Rebecca Cran


Re: Build fails with VS2012

Michael D Kinney
 

I think there a few categories of tool chains:

1) Tool chains that are in tools_def.txt and are used by EDK II CI to perform pre-commit and post-commit changes. These are documented in Readme.rst
2) Tool chains that are in tools_def.txt that are fully supported by the EDK II community. Should be documented in Readme.rst.
3) Tool chains that are in tools_def.txt, but are not supported by the EDK II community, but some downstream consumers use the tool chain are willing to fix issues that impact them.
4) Tool chains that are in tools_def.txt, but are not used by anyone.

We need to make sure we document (1), (2), and (3) so we can identify and delete (4) from tools_def.txt.

Thanks,

Mike

-----Original Message-----
From: Rebecca Cran <rebecca@nuviainc.com>
Sent: Monday, May 10, 2021 6:21 AM
To: devel@edk2.groups.io; lersek@redhat.com; rebecca@bsdio.com
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: [edk2-devel] Build fails with VS2012

On 5/10/21 5:56 AM, Laszlo Ersek wrote:
Hi Rebecca

+Tom

On 05/08/21 21:47, Rebecca Cran wrote:
I'm setting up a new Jenkins server to do Bhyve builds and run on
platforms that aren't currently tested with the GitHub/Azure system.

Since VS2012 appears to be a supported toolchain, I tried building
OvmfPkgX64 with it (I'm also planning on testing VS2013, VS2015, VS2017
and VS2019), but it fails with:


Building ...
c:\users\administrator\src\edk2\NetworkPkg\Library\DxeUdpIoLib\DxeUdpIoLib.inf
[X64]
c:\users\administrator\src\edk2\UefiCpuPkg\Library\MpInitLib\MpLib.c(1268)
: error C2220: warning treated as error - no 'object' file generated
c:\users\administrator\src\edk2\UefiCpuPkg\Library\MpInitLib\MpLib.c(1268)
: warning C4306: 'type cast' : conversion from 'int' to
'SEV_ES_AP_JMP_FAR *' of greater size
I think the compiler is justified to complain here:

7b7508ad784d1 (Tom Lendacky 2020-08-12 15:21:42 -0500 1268) JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32
(PcdSevEsWorkAreaBase);

The proper way to spell such casts is with (UINTN) in the middle.

Can you please file a new BZ?
I've created https://bugzilla.tianocore.org/show_bug.cgi?id=3385

I know the GitHub/Azure system only tests with VS2017 and VS2019: are
there plans to drop the older VS versions, or should they still work?
And would it be considered useful to _check_ that they still work, or
should they be considered unsupported?
I'd suggest dropping them.

Earlier, Ard raised a similar question for gcc too -- IIRC, Ard suggested that GCC4* be removed. I agree with the idea.
Thanks. If we're ready to go ahead, should I create a patch to remove them?

Do you know what the new minimum version of gcc should then be? I'd like
to run builds with it so we can catch any issues.

Would we remove all VS versions except VS2017 and VS2019, or would we
keep others like VS2015 for now?

--
Rebecca Cran


[PATCH v3 2/2] SecurityPkg: Add support for RngDxe on AARCH64

Rebecca Cran
 

AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.

Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
SecurityPkg/SecurityPkg.dec | 2 +
SecurityPkg/SecurityPkg.dsc | 11 +-
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf | 24 ++-
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h | 0
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h | 17 --
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h | 117 ++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c | 127 +++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c | 0
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c | 45 +-----
SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c | 146 +++++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c | 170 ++++++++------------
11 files changed, 483 insertions(+), 176 deletions(-)

diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
index dfbbb0365a2b..4001650fa28e 100644
--- a/SecurityPkg/SecurityPkg.dec
+++ b/SecurityPkg/SecurityPkg.dec
@@ -297,6 +297,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationPass|0x0303100A|UINT32|0x00010030
gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationFail|0x0303100B|UINT32|0x00010031

+ gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00010032
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Image verification policy for OptionRom. Only following values are valid:<BR><BR>
# NOTE: Do NOT use 0x5 and 0x2 since it violates the UEFI specification and has been removed.<BR>
diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
index 12ccd1634941..bd4b810bce61 100644
--- a/SecurityPkg/SecurityPkg.dsc
+++ b/SecurityPkg/SecurityPkg.dsc
@@ -259,6 +259,12 @@ [Components]
[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf

+[Components.IA32, Components.X64, Components.AARCH64]
+ #
+ # Random Number Generator
+ #
+ SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+
[Components.IA32, Components.X64]
SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf

@@ -334,11 +340,6 @@ [Components.IA32, Components.X64]
SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf
SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/StandaloneMmTcg2PhysicalPresenceLib.inf

- #
- # Random Number Generator
- #
- SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
-
#
# Opal Password solution
#
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
index 99d6f6b35fc2..f3300971993f 100644
--- a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
@@ -26,15 +26,22 @@ [Defines]
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
#

[Sources.common]
RngDxe.c
- RdRand.c
- RdRand.h
- AesCore.c
- AesCore.h
+ RngDxeInternals.h
+
+[Sources.IA32, Sources.X64]
+ Rand/RngDxe.c
+ Rand/RdRand.c
+ Rand/RdRand.h
+ Rand/AesCore.c
+ Rand/AesCore.h
+
+[Sources.AARCH64]
+ AArch64/RngDxe.c

[Packages]
MdePkg/MdePkg.dec
@@ -50,12 +57,19 @@ [LibraryClasses]
RngLib

[Guids]
+ gEfiRngAlgorithmSp80090Hash256Guid ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
+ gEfiRngAlgorithmSp80090Hmac256Guid ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
gEfiRngAlgorithmSp80090Ctr256Guid ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
+ gEfiRngAlgorithmX9313DesGuid ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
+ gEfiRngAlgorithmX931AesGuid ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG
gEfiRngAlgorithmRaw ## SOMETIMES_PRODUCES ## GUID # Unique ID of the algorithm for RNG

[Protocols]
gEfiRngProtocolGuid ## PRODUCES

+[Pcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm ## CONSUMES
+
[Depex]
TRUE

diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/AesCore.h b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/AesCore.h
similarity index 100%
rename from SecurityPkg/RandomNumberGenerator/RngDxe/AesCore.h
rename to SecurityPkg/RandomNumberGenerator/RngDxe/Rand/AesCore.h
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.h b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.h
similarity index 72%
rename from SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.h
rename to SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.h
index 12ab1f34ec6d..072378e062e7 100644
--- a/SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.h
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.h
@@ -23,23 +23,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include <Protocol/Rng.h>

-/**
- Calls RDRAND to fill a buffer of arbitrary size with random bytes.
-
- @param[in] Length Size of the buffer, in bytes, to fill with.
- @param[out] RandBuffer Pointer to the buffer to store the random result.
-
- @retval EFI_SUCCESS Random bytes generation succeeded.
- @retval EFI_NOT_READY Failed to request random bytes.
-
-**/
-EFI_STATUS
-EFIAPI
-RdRandGetBytes (
- IN UINTN Length,
- OUT UINT8 *RandBuffer
- );
-
/**
Generate high-quality entropy source through RDRAND.

diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h
new file mode 100644
index 000000000000..2660ed5875e0
--- /dev/null
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h
@@ -0,0 +1,117 @@
+/** @file
+ Function prototypes for UEFI Random Number Generator protocol support.
+
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RNGDXE_INTERNALS_H_
+#define RNGDXE_INTERNALS_H_
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
+ On output with a return code of EFI_SUCCESS, the size
+ in bytes of the data returned in RNGAlgorithmList. On output
+ with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of RNGAlgorithmList required to obtain the list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver
+ with one EFI_RNG_ALGORITHM element for each supported
+ RNG algorithm. The list must not change across multiple
+ calls to the same driver. The first algorithm in the list
+ is the default algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned successfully.
+ @retval EFI_UNSUPPORTED The services is not supported by this driver.
+ @retval EFI_DEVICE_ERROR The list of algorithms could not be retrieved due to a
+ hardware or firmware error.
+ @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetInfo (
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ );
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG
+ algorithm to use. May be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by
+ RNGValue. The driver shall return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the
+ resulting RNG value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by
+ this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or
+ firmware error.
+ @retval EFI_NOT_READY There is not enough random data available to satisfy the length
+ requested by RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ );
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
+ On output with a return code of EFI_SUCCESS, the size
+ in bytes of the data returned in RNGAlgorithmList. On output
+ with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of RNGAlgorithmList required to obtain the list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver
+ with one EFI_RNG_ALGORITHM element for each supported
+ RNG algorithm. The list must not change across multiple
+ calls to the same driver. The first algorithm in the list
+ is the default algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned successfully.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
+
+**/
+UINTN
+EFIAPI
+ArchGetSupportedRngAlgorithms (
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ );
+
+/**
+ Runs CPU RNG instruction to fill a buffer of arbitrary size with random bytes.
+
+ @param[in] Length Size of the buffer, in bytes, to fill with.
+ @param[out] RandBuffer Pointer to the buffer to store the random result.
+
+ @retval EFI_SUCCESS Random bytes generation succeeded.
+ @retval EFI_NOT_READY Failed to request random bytes.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetBytes (
+ IN UINTN Length,
+ OUT UINT8 *RandBuffer
+ );
+
+#endif // RNGDXE_INTERNALS_H_
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c b/SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c
new file mode 100644
index 000000000000..2810a9eb94ad
--- /dev/null
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c
@@ -0,0 +1,127 @@
+/** @file
+ RNG Driver to produce the UEFI Random Number Generator protocol.
+
+ The driver will use the RNDR instruction to produce random numbers.
+
+ RNG Algorithms defined in UEFI 2.4:
+ - EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID
+ - EFI_RNG_ALGORITHM_RAW - Unsupported
+ - EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID
+ - EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID
+ - EFI_RNG_ALGORITHM_X9_31_3DES_GUID - Unsupported
+ - EFI_RNG_ALGORITHM_X9_31_AES_GUID - Unsupported
+
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/TimerLib.h>
+#include <Protocol/Rng.h>
+
+#include "RngDxeInternals.h"
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG
+ algorithm to use. May be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by
+ RNGValue. The driver shall return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the
+ resulting RNG value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by
+ this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or
+ firmware error.
+ @retval EFI_NOT_READY There is not enough random data available to satisfy the length
+ requested by RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ EFI_STATUS Status;
+
+ if ((RNGValueLength == 0) || (RNGValue == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (RNGAlgorithm == NULL) {
+ //
+ // Use the default RNG algorithm if RNGAlgorithm is NULL.
+ //
+ RNGAlgorithm = PcdGetPtr (PcdCpuRngSupportedAlgorithm);
+ }
+
+ if (CompareGuid (RNGAlgorithm, PcdGetPtr (PcdCpuRngSupportedAlgorithm))) {
+ Status = RngGetBytes (RNGValueLength, RNGValue);
+ return Status;
+ }
+
+ //
+ // Other algorithms are unsupported by this driver.
+ //
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
+ On output with a return code of EFI_SUCCESS, the size
+ in bytes of the data returned in RNGAlgorithmList. On output
+ with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of RNGAlgorithmList required to obtain the list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver
+ with one EFI_RNG_ALGORITHM element for each supported
+ RNG algorithm. The list must not change across multiple
+ calls to the same driver. The first algorithm in the list
+ is the default algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned successfully.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
+
+**/
+UINTN
+EFIAPI
+ArchGetSupportedRngAlgorithms (
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ UINTN RequiredSize;
+ EFI_RNG_ALGORITHM *CpuRngSupportedAlgorithm;
+
+ RequiredSize = sizeof (EFI_RNG_ALGORITHM);
+
+ if (*RNGAlgorithmListSize < RequiredSize) {
+ *RNGAlgorithmListSize = RequiredSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ CpuRngSupportedAlgorithm = PcdGetPtr (PcdCpuRngSupportedAlgorithm);
+
+ CopyMem(&RNGAlgorithmList[0], CpuRngSupportedAlgorithm, sizeof (EFI_RNG_ALGORITHM));
+
+ *RNGAlgorithmListSize = RequiredSize;
+ return EFI_SUCCESS;
+}
+
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/AesCore.c b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/AesCore.c
similarity index 100%
rename from SecurityPkg/RandomNumberGenerator/RngDxe/AesCore.c
rename to SecurityPkg/RandomNumberGenerator/RngDxe/Rand/AesCore.c
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.c b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.c
similarity index 71%
rename from SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.c
rename to SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.c
index e7dd5ab18111..83025a47d43d 100644
--- a/SecurityPkg/RandomNumberGenerator/RngDxe/RdRand.c
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RdRand.c
@@ -8,48 +8,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/RngLib.h>

-#include "RdRand.h"
#include "AesCore.h"
-
-/**
- Calls RDRAND to fill a buffer of arbitrary size with random bytes.
-
- @param[in] Length Size of the buffer, in bytes, to fill with.
- @param[out] RandBuffer Pointer to the buffer to store the random result.
-
- @retval EFI_SUCCESS Random bytes generation succeeded.
- @retval EFI_NOT_READY Failed to request random bytes.
-
-**/
-EFI_STATUS
-EFIAPI
-RdRandGetBytes (
- IN UINTN Length,
- OUT UINT8 *RandBuffer
- )
-{
- BOOLEAN IsRandom;
- UINT64 TempRand[2];
-
- while (Length > 0) {
- IsRandom = GetRandomNumber128 (TempRand);
- if (!IsRandom) {
- return EFI_NOT_READY;
- }
- if (Length >= sizeof (TempRand)) {
- WriteUnaligned64 ((UINT64*)RandBuffer, TempRand[0]);
- RandBuffer += sizeof (UINT64);
- WriteUnaligned64 ((UINT64*)RandBuffer, TempRand[1]);
- RandBuffer += sizeof (UINT64);
- Length -= sizeof (TempRand);
- } else {
- CopyMem (RandBuffer, TempRand, Length);
- Length = 0;
- }
- }
-
- return EFI_SUCCESS;
-}
+#include "RdRand.h"
+#include "RngDxeInternals.h"

/**
Creates a 128bit random value that is fully forward and backward prediction resistant,
@@ -92,7 +53,7 @@ RdRandGetSeed128 (
//
for (Index = 0; Index < 32; Index++) {
MicroSecondDelay (10);
- Status = RdRandGetBytes (16, RandByte);
+ Status = RngGetBytes (16, RandByte);
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c
new file mode 100644
index 000000000000..6b628a9f8bc6
--- /dev/null
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c
@@ -0,0 +1,146 @@
+/** @file
+ RNG Driver to produce the UEFI Random Number Generator protocol.
+
+ The driver will use the new RDRAND instruction to produce high-quality, high-performance
+ entropy and random number.
+
+ RNG Algorithms defined in UEFI 2.4:
+ - EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID - Supported
+ (RDRAND implements a hardware NIST SP800-90 AES-CTR-256 based DRBG)
+ - EFI_RNG_ALGORITHM_RAW - Supported
+ (Structuring RDRAND invocation can be guaranteed as high-quality entropy source)
+ - EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID - Unsupported
+ - EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID - Unsupported
+ - EFI_RNG_ALGORITHM_X9_31_3DES_GUID - Unsupported
+ - EFI_RNG_ALGORITHM_X9_31_AES_GUID - Unsupported
+
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RdRand.h"
+#include "RngDxeInternals.h"
+
+/**
+ Produces and returns an RNG value using either the default or specified RNG algorithm.
+
+ @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
+ @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG
+ algorithm to use. May be NULL in which case the function will
+ use its default RNG algorithm.
+ @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by
+ RNGValue. The driver shall return exactly this numbers of bytes.
+ @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the
+ resulting RNG value.
+
+ @retval EFI_SUCCESS The RNG value was returned successfully.
+ @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by
+ this driver.
+ @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or
+ firmware error.
+ @retval EFI_NOT_READY There is not enough random data available to satisfy the length
+ requested by RNGValueLength.
+ @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetRNG (
+ IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
+ IN UINTN RNGValueLength,
+ OUT UINT8 *RNGValue
+ )
+{
+ EFI_STATUS Status;
+
+ if ((RNGValueLength == 0) || (RNGValue == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_UNSUPPORTED;
+ if (RNGAlgorithm == NULL) {
+ //
+ // Use the default RNG algorithm if RNGAlgorithm is NULL.
+ //
+ RNGAlgorithm = &gEfiRngAlgorithmSp80090Ctr256Guid;
+ }
+
+ //
+ // NIST SP800-90-AES-CTR-256 supported by RDRAND
+ //
+ if (CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmSp80090Ctr256Guid)) {
+ Status = RngGetBytes (RNGValueLength, RNGValue);
+ return Status;
+ }
+
+ //
+ // The "raw" algorithm is intended to provide entropy directly
+ //
+ if (CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
+ //
+ // When a DRBG is used on the output of a entropy source,
+ // its security level must be at least 256 bits according to UEFI Spec.
+ //
+ if (RNGValueLength < 32) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = RdRandGenerateEntropy (RNGValueLength, RNGValue);
+ return Status;
+ }
+
+ //
+ // Other algorithms were unsupported by this driver.
+ //
+ return Status;
+}
+
+/**
+ Returns information about the random number generation implementation.
+
+ @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
+ On output with a return code of EFI_SUCCESS, the size
+ in bytes of the data returned in RNGAlgorithmList. On output
+ with a return code of EFI_BUFFER_TOO_SMALL,
+ the size of RNGAlgorithmList required to obtain the list.
+ @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver
+ with one EFI_RNG_ALGORITHM element for each supported
+ RNG algorithm. The list must not change across multiple
+ calls to the same driver. The first algorithm in the list
+ is the default algorithm for the driver.
+
+ @retval EFI_SUCCESS The RNG algorithm list was returned successfully.
+ @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result.
+
+**/
+UINTN
+EFIAPI
+ArchGetSupportedRngAlgorithms (
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ )
+{
+ UINTN RequiredSize;
+ EFI_RNG_ALGORITHM *CpuRngSupportedAlgorithm;
+
+ RequiredSize = 2 * sizeof (EFI_RNG_ALGORITHM);
+
+ if (*RNGAlgorithmListSize < RequiredSize) {
+ *RNGAlgorithmListSize = RequiredSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ CpuRngSupportedAlgorithm = PcdGetPtr (PcdCpuRngSupportedAlgorithm);
+
+ CopyMem(&RNGAlgorithmList[0], CpuRngSupportedAlgorithm, sizeof (EFI_RNG_ALGORITHM));
+
+ // x86 platforms also support EFI_RNG_ALGORITHM_RAW via RDSEED
+ CopyMem(&RNGAlgorithmList[1], &gEfiRngAlgorithmRaw, sizeof (EFI_RNG_ALGORITHM));
+
+ *RNGAlgorithmListSize = RequiredSize;
+ return EFI_SUCCESS;
+}
+
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c
index 13d3dbd0bfbe..b959c70536ea 100644
--- a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c
@@ -1,34 +1,32 @@
/** @file
RNG Driver to produce the UEFI Random Number Generator protocol.

- The driver will use the new RDRAND instruction to produce high-quality, high-performance
- entropy and random number.
+ The driver uses CPU RNG instructions to produce high-quality,
+ high-performance entropy and random number.

RNG Algorithms defined in UEFI 2.4:
- - EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID - Supported
- (RDRAND implements a hardware NIST SP800-90 AES-CTR-256 based DRBG)
- - EFI_RNG_ALGORITHM_RAW - Supported
- (Structuring RDRAND invocation can be guaranteed as high-quality entropy source)
- - EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID - Unsupported
- - EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID - Unsupported
- - EFI_RNG_ALGORITHM_X9_31_3DES_GUID - Unsupported
- - EFI_RNG_ALGORITHM_X9_31_AES_GUID - Unsupported
+ - EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID
+ - EFI_RNG_ALGORITHM_RAW
+ - EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID
+ - EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID
+ - EFI_RNG_ALGORITHM_X9_31_3DES_GUID
+ - EFI_RNG_ALGORITHM_X9_31_AES_GUID

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent

**/

-#include "RdRand.h"
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/RngLib.h>
+#include <Library/TimerLib.h>
+#include <Protocol/Rng.h>

-//
-// Supported RNG Algorithms list by this driver.
-//
-EFI_RNG_ALGORITHM mSupportedRngAlgorithms[] = {
- EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID,
- EFI_RNG_ALGORITHM_RAW
-};
+#include "RngDxeInternals.h"

/**
Returns information about the random number generation implementation.
@@ -62,106 +60,23 @@ RngGetInfo (
)
{
EFI_STATUS Status;
- UINTN RequiredSize;

if ((This == NULL) || (RNGAlgorithmListSize == NULL)) {
return EFI_INVALID_PARAMETER;
}

- RequiredSize = sizeof (mSupportedRngAlgorithms);
- if (*RNGAlgorithmListSize < RequiredSize) {
- Status = EFI_BUFFER_TOO_SMALL;
+ //
+ // Return algorithm list supported by driver.
+ //
+ if (RNGAlgorithmList != NULL) {
+ Status = ArchGetSupportedRngAlgorithms (RNGAlgorithmListSize, RNGAlgorithmList);
} else {
- //
- // Return algorithm list supported by driver.
- //
- if (RNGAlgorithmList != NULL) {
- CopyMem (RNGAlgorithmList, mSupportedRngAlgorithms, RequiredSize);
- Status = EFI_SUCCESS;
- } else {
- Status = EFI_INVALID_PARAMETER;
- }
+ Status = EFI_INVALID_PARAMETER;
}
- *RNGAlgorithmListSize = RequiredSize;

return Status;
}

-/**
- Produces and returns an RNG value using either the default or specified RNG algorithm.
-
- @param[in] This A pointer to the EFI_RNG_PROTOCOL instance.
- @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG
- algorithm to use. May be NULL in which case the function will
- use its default RNG algorithm.
- @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by
- RNGValue. The driver shall return exactly this numbers of bytes.
- @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the
- resulting RNG value.
-
- @retval EFI_SUCCESS The RNG value was returned successfully.
- @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by
- this driver.
- @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or
- firmware error.
- @retval EFI_NOT_READY There is not enough random data available to satisfy the length
- requested by RNGValueLength.
- @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero.
-
-**/
-EFI_STATUS
-EFIAPI
-RngGetRNG (
- IN EFI_RNG_PROTOCOL *This,
- IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
- IN UINTN RNGValueLength,
- OUT UINT8 *RNGValue
- )
-{
- EFI_STATUS Status;
-
- if ((RNGValueLength == 0) || (RNGValue == NULL)) {
- return EFI_INVALID_PARAMETER;
- }
-
- Status = EFI_UNSUPPORTED;
- if (RNGAlgorithm == NULL) {
- //
- // Use the default RNG algorithm if RNGAlgorithm is NULL.
- //
- RNGAlgorithm = &gEfiRngAlgorithmSp80090Ctr256Guid;
- }
-
- //
- // NIST SP800-90-AES-CTR-256 supported by RDRAND
- //
- if (CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmSp80090Ctr256Guid)) {
- Status = RdRandGetBytes (RNGValueLength, RNGValue);
- return Status;
- }
-
- //
- // The "raw" algorithm is intended to provide entropy directly
- //
- if (CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) {
- //
- // When a DRBG is used on the output of a entropy source,
- // its security level must be at least 256 bits according to UEFI Spec.
- //
- if (RNGValueLength < 32) {
- return EFI_INVALID_PARAMETER;
- }
-
- Status = RdRandGenerateEntropy (RNGValueLength, RNGValue);
- return Status;
- }
-
- //
- // Other algorithms were unsupported by this driver.
- //
- return Status;
-}
-
//
// The Random Number Generator (RNG) protocol
//
@@ -204,3 +119,44 @@ RngDriverEntry (

return Status;
}
+
+
+/**
+ Calls RDRAND to fill a buffer of arbitrary size with random bytes.
+
+ @param[in] Length Size of the buffer, in bytes, to fill with.
+ @param[out] RandBuffer Pointer to the buffer to store the random result.
+
+ @retval EFI_SUCCESS Random bytes generation succeeded.
+ @retval EFI_NOT_READY Failed to request random bytes.
+
+**/
+EFI_STATUS
+EFIAPI
+RngGetBytes (
+ IN UINTN Length,
+ OUT UINT8 *RandBuffer
+ )
+{
+ BOOLEAN IsRandom;
+ UINT64 TempRand[2];
+
+ while (Length > 0) {
+ IsRandom = GetRandomNumber128 (TempRand);
+ if (!IsRandom) {
+ return EFI_NOT_READY;
+ }
+ if (Length >= sizeof (TempRand)) {
+ WriteUnaligned64 ((UINT64*)RandBuffer, TempRand[0]);
+ RandBuffer += sizeof (UINT64);
+ WriteUnaligned64 ((UINT64*)RandBuffer, TempRand[1]);
+ RandBuffer += sizeof (UINT64);
+ Length -= sizeof (TempRand);
+ } else {
+ CopyMem (RandBuffer, TempRand, Length);
+ Length = 0;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
--
2.26.2


[PATCH v3 1/2] MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions

Rebecca Cran
 

Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that is a part of FEAT_RNG.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
MdePkg/MdePkg.dec | 9 +-
MdePkg/MdePkg.dsc | 4 +-
MdePkg/Library/BaseRngLib/BaseRngLib.inf | 23 +++-
MdePkg/Library/BaseRngLib/AArch64/ArmRng.h | 43 ++++++
MdePkg/Library/BaseRngLib/BaseRngLibInternals.h | 78 +++++++++++
MdePkg/Library/BaseRngLib/AArch64/Rndr.c | 139 ++++++++++++++++++++
MdePkg/Library/BaseRngLib/BaseRng.c | 87 ++++++------
MdePkg/Library/BaseRngLib/Rand/RdRand.c | 131 ++++++++++++++++++
MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S | 31 +++++
MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm | 30 +++++
MdePkg/Library/BaseRngLib/AArch64/ArmRng.S | 37 ++++++
MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm | 39 ++++++
MdePkg/Library/BaseRngLib/BaseRngLib.uni | 6 +-
13 files changed, 603 insertions(+), 54 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 8965e903e093..b49f88d8e18f 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -267,6 +267,11 @@ [LibraryClasses]
#
RegisterFilterLib|Include/Library/RegisterFilterLib.h

+[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]
+ ## @libraryclass Provides services to generate random number.
+ #
+ RngLib|Include/Library/RngLib.h
+
[LibraryClasses.IA32, LibraryClasses.X64]
## @libraryclass Abstracts both S/W SMI generation and detection.
##
@@ -288,10 +293,6 @@ [LibraryClasses.IA32, LibraryClasses.X64]
#
SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h

- ## @libraryclass Provides services to generate random number.
- #
- RngLib|Include/Library/RngLib.h
-
## @libraryclass Provides services to log the SMI handler registration.
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h

diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index d363419006ea..a94959169b2f 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -145,6 +145,9 @@ [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf

+[Components.IA32, Components.X64, Components.AARCH64]
+ MdePkg/Library/BaseRngLib/BaseRngLib.inf
+
[Components.IA32, Components.X64]
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -168,7 +171,6 @@ [Components.IA32, Components.X64]
MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
MdePkg/Library/SmmMemLib/SmmMemLib.inf
MdePkg/Library/SmmIoLib/SmmIoLib.inf
- MdePkg/Library/BaseRngLib/BaseRngLib.inf
MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLib.inf b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
index 31740751c69c..1fcceb941495 100644
--- a/MdePkg/Library/BaseRngLib/BaseRngLib.inf
+++ b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
@@ -1,9 +1,10 @@
## @file
# Instance of RNG (Random Number Generator) Library.
#
-# BaseRng Library that uses CPU RdRand instruction access to provide
-# high-quality random numbers.
+# BaseRng Library that uses CPU RNG instructions (e.g. RdRand) to
+# provide random numbers.
#
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,11 +23,25 @@ [Defines]
CONSTRUCTOR = BaseRngLibConstructor

#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
#

-[Sources.Ia32, Sources.X64]
+[Sources]
BaseRng.c
+ BaseRngLibInternals.h
+
+[Sources.Ia32, Sources.X64]
+ Rand/RdRand.c
+
+[Sources.AARCH64]
+ AArch64/Rndr.c
+ AArch64/ArmRng.h
+
+ AArch64/ArmReadIdIsar0.S | GCC
+ AArch64/ArmRng.S | GCC
+
+ AArch64/ArmReadIdIsar0.asm | MSFT
+ AArch64/ArmRng.asm | MSFT

[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
new file mode 100644
index 000000000000..a597e98bf0d5
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
@@ -0,0 +1,43 @@
+/** @file
+ Random number generator service that uses the RNDR instruction
+ to provide pseudorandom numbers.
+
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ARM_RNG_H_
+#define ARM_RNG_H_
+
+/**
+ Generates a random number using RNDR.
+ Returns TRUE on success; FALSE on failure.
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArmRndr (
+ OUT UINT64 *Rand
+ );
+
+/**
+ Reads the ID_AA64ISAR0 Register.
+
+ @return The contents of the ID_AA64ISAR0 register.
+
+**/
+UINT64
+EFIAPI
+ArmReadIdIsar0 (
+ VOID
+ );
+
+#endif /* ARM_RNG_H_ */
+
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h b/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
new file mode 100644
index 000000000000..b6b4e9eef227
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
@@ -0,0 +1,78 @@
+/** @file
+
+ Architecture specific interface to RNG functionality.
+
+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RNGLIB_INTERNALS_H_
+
+/**
+ Generates a 16-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 16-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber16 (
+ OUT UINT16 *Rand
+ );
+
+/**
+ Generates a 32-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 32-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber32 (
+ OUT UINT32 *Rand
+ );
+
+/**
+ Generates a 64-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber64 (
+ OUT UINT64 *Rand
+ );
+
+/**
+ Checks whether the RNG instruction is supported.
+
+ @retval TRUE RNG instruction is supported.
+ @retval FALSE RNG instruction is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+ArchIsRngSupported (
+ VOID
+ );
+
+#if defined (MDE_CPU_AARCH64)
+
+// RNDR, Random Number
+#define RNDR S3_3_C2_C4_0
+
+#endif
+
+#endif // BASE_RNGLIB_INTERNALS_H_
diff --git a/MdePkg/Library/BaseRngLib/AArch64/Rndr.c b/MdePkg/Library/BaseRngLib/AArch64/Rndr.c
new file mode 100644
index 000000000000..c9f8c813ed35
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/Rndr.c
@@ -0,0 +1,139 @@
+/** @file
+ Random number generator service that uses the RNDR instruction
+ to provide pseudorandom numbers.
+
+ Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RngLib.h>
+
+#include "ArmRng.h"
+#include "BaseRngLibInternals.h"
+
+STATIC BOOLEAN mRndrSupported;
+
+//
+// Bit mask used to determine if RNDR instruction is supported.
+//
+#define RNDR_MASK ((UINT64)MAX_UINT16 << 60U)
+
+/**
+ The constructor function checks whether or not RNDR instruction is supported
+ by the host hardware.
+
+ The constructor function checks whether or not RNDR instruction is supported.
+ It will ASSERT() if RNDR instruction is not supported.
+ It will always return EFI_SUCCESS.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+BaseRngLibConstructor (
+ VOID
+ )
+{
+ UINT64 Isar0;
+ //
+ // Determine RNDR support by examining bits 63:60 of the ISAR0 register returned by
+ // MSR. A non-zero value indicates that the processor supports the RNDR instruction.
+ //
+ Isar0 = ArmReadIdIsar0 ();
+ ASSERT ((Isar0 & RNDR_MASK) != 0);
+
+ mRndrSupported = ((Isar0 & RNDR_MASK) != 0);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Generates a 16-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 16-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber16 (
+ OUT UINT16 *Rand
+ )
+{
+ UINT64 Rand64;
+
+ if (ArchGetRandomNumber64 (&Rand64)) {
+ *Rand = Rand64 & MAX_UINT16;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Generates a 32-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 32-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber32 (
+ OUT UINT32 *Rand
+ )
+{
+ UINT64 Rand64;
+
+ if (ArchGetRandomNumber64 (&Rand64)) {
+ *Rand = Rand64 & MAX_UINT32;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Generates a 64-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber64 (
+ OUT UINT64 *Rand
+ )
+{
+ return ArmRndr (Rand);
+}
+
+/**
+ Checks whether RNDR is supported.
+
+ @retval TRUE RNDR is supported.
+ @retval FALSE RNDR is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+ArchIsRngSupported (
+ VOID
+ )
+{
+ return mRndrSupported;
+}
diff --git a/MdePkg/Library/BaseRngLib/BaseRng.c b/MdePkg/Library/BaseRngLib/BaseRng.c
index 7ad7aec9d38f..5b63d8f7146b 100644
--- a/MdePkg/Library/BaseRngLib/BaseRng.c
+++ b/MdePkg/Library/BaseRngLib/BaseRng.c
@@ -1,8 +1,10 @@
/** @file
- Random number generator services that uses RdRand instruction access
- to provide high-quality random numbers.
+ Random number generator services that uses CPU RNG instructions to
+ provide random numbers.

+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -10,46 +12,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>

-//
-// Bit mask used to determine if RdRand instruction is supported.
-//
-#define RDRAND_MASK BIT30
+#include "BaseRngLibInternals.h"

//
// Limited retry number when valid random data is returned.
// Uses the recommended value defined in Section 7.3.17 of "Intel 64 and IA-32
-// Architectures Software Developer's Mannual".
+// Architectures Software Developer's Manual".
//
-#define RDRAND_RETRY_LIMIT 10
+#define GETRANDOM_RETRY_LIMIT 10

-/**
- The constructor function checks whether or not RDRAND instruction is supported
- by the host hardware.
-
- The constructor function checks whether or not RDRAND instruction is supported.
- It will ASSERT() if RDRAND instruction is not supported.
- It will always return RETURN_SUCCESS.
-
- @retval RETURN_SUCCESS The constructor always returns EFI_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-BaseRngLibConstructor (
- VOID
- )
-{
- UINT32 RegEcx;
-
- //
- // Determine RDRAND support by examining bit 30 of the ECX register returned by
- // CPUID. A value of 1 indicates that processor support RDRAND instruction.
- //
- AsmCpuid (1, 0, 0, &RegEcx, 0);
- ASSERT ((RegEcx & RDRAND_MASK) == RDRAND_MASK);
-
- return RETURN_SUCCESS;
-}

/**
Generates a 16-bit random number.
@@ -72,11 +43,19 @@ GetRandomNumber16 (

ASSERT (Rand != NULL);

+ if (Rand == NULL) {
+ return FALSE;
+ }
+
+ if (!ArchIsRngSupported ()) {
+ return FALSE;
+ }
+
//
// A loop to fetch a 16 bit random value with a retry count limit.
//
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {
- if (AsmRdRand16 (Rand)) {
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {
+ if (ArchGetRandomNumber16 (Rand)) {
return TRUE;
}
}
@@ -105,11 +84,19 @@ GetRandomNumber32 (

ASSERT (Rand != NULL);

+ if (Rand == NULL) {
+ return FALSE;
+ }
+
+ if (!ArchIsRngSupported ()) {
+ return FALSE;
+ }
+
//
// A loop to fetch a 32 bit random value with a retry count limit.
//
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {
- if (AsmRdRand32 (Rand)) {
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {
+ if (ArchGetRandomNumber32 (Rand)) {
return TRUE;
}
}
@@ -138,11 +125,19 @@ GetRandomNumber64 (

ASSERT (Rand != NULL);

+ if (Rand == NULL) {
+ return FALSE;
+ }
+
+ if (!ArchIsRngSupported ()) {
+ return FALSE;
+ }
+
//
// A loop to fetch a 64 bit random value with a retry count limit.
//
- for (Index = 0; Index < RDRAND_RETRY_LIMIT; Index++) {
- if (AsmRdRand64 (Rand)) {
+ for (Index = 0; Index < GETRANDOM_RETRY_LIMIT; Index++) {
+ if (ArchGetRandomNumber64 (Rand)) {
return TRUE;
}
}
@@ -169,6 +164,14 @@ GetRandomNumber128 (
{
ASSERT (Rand != NULL);

+ if (Rand == NULL) {
+ return FALSE;
+ }
+
+ if (!ArchIsRngSupported ()) {
+ return FALSE;
+ }
+
//
// Read first 64 bits
//
diff --git a/MdePkg/Library/BaseRngLib/Rand/RdRand.c b/MdePkg/Library/BaseRngLib/Rand/RdRand.c
new file mode 100644
index 000000000000..09fb875ac3f9
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/Rand/RdRand.c
@@ -0,0 +1,131 @@
+/** @file
+ Random number generator services that uses RdRand instruction access
+ to provide high-quality random numbers.
+
+Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+#include "BaseRngLibInternals.h"
+
+//
+// Bit mask used to determine if RdRand instruction is supported.
+//
+#define RDRAND_MASK BIT30
+
+
+STATIC BOOLEAN mRdRandSupported;
+
+/**
+ The constructor function checks whether or not RDRAND instruction is supported
+ by the host hardware.
+
+ The constructor function checks whether or not RDRAND instruction is supported.
+ It will ASSERT() if RDRAND instruction is not supported.
+ It will always return EFI_SUCCESS.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+BaseRngLibConstructor (
+ VOID
+ )
+{
+ UINT32 RegEcx;
+
+ //
+ // Determine RDRAND support by examining bit 30 of the ECX register returned by
+ // CPUID. A value of 1 indicates that processor support RDRAND instruction.
+ //
+ AsmCpuid (1, 0, 0, &RegEcx, 0);
+ ASSERT ((RegEcx & RDRAND_MASK) == RDRAND_MASK);
+
+ mRdRandSupported = ((RegEcx & RDRAND_MASK) == RDRAND_MASK);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Generates a 16-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 16-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber16 (
+ OUT UINT16 *Rand
+ )
+{
+ return AsmRdRand16 (Rand);
+}
+
+/**
+ Generates a 32-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 32-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber32 (
+ OUT UINT32 *Rand
+ )
+{
+ return AsmRdRand32 (Rand);
+}
+
+/**
+ Generates a 64-bit random number.
+
+ @param[out] Rand Buffer pointer to store the 64-bit random value.
+
+ @retval TRUE Random number generated successfully.
+ @retval FALSE Failed to generate the random number.
+
+**/
+BOOLEAN
+EFIAPI
+ArchGetRandomNumber64 (
+ OUT UINT64 *Rand
+ )
+{
+ return AsmRdRand64 (Rand);
+}
+
+/**
+ Checks whether RDRAND is supported.
+
+ @retval TRUE RDRAND is supported.
+ @retval FALSE RDRAND is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+ArchIsRngSupported (
+ VOID
+ )
+{
+ /*
+ Existing software depends on this always returning TRUE, so for
+ now hard-code it.
+
+ return mRdRandSupported;
+ */
+ return TRUE;
+}
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S b/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
new file mode 100644
index 000000000000..82a00d362212
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
@@ -0,0 +1,31 @@
+#------------------------------------------------------------------------------
+#
+# ArmReadIdIsar0() for AArch64
+#
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(ArmReadIdIsar0)
+
+#/**
+# Reads the ID_AA64ISAR0 Register.
+#
+# @return The contents of the ID_AA64ISAR0 register.
+#
+#**/
+#UINT64
+#EFIAPI
+#ArmReadIdIsar0 (
+# VOID
+# );
+#
+ASM_PFX(ArmReadIdIsar0):
+ mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
+ ret
+
+
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm b/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
new file mode 100644
index 000000000000..1d9f9a808c0c
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
@@ -0,0 +1,30 @@
+;------------------------------------------------------------------------------
+;
+; ArmReadIdIsar0() for AArch64
+;
+; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT ArmReadIdIsar0
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Reads the ID_AA64ISAR0 Register.
+;
+; @return The contents of the ID_AA64ISAR0 register.
+;
+;**/
+;UINT64
+;EFIAPI
+;ArmReadIdIsar0 (
+; VOID
+; );
+;
+ArmReadIdIsar0
+ mrs x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
+ ret
+
+ END
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.S b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.S
new file mode 100644
index 000000000000..5159f467e3a6
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.S
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# ArmRndr() for AArch64
+#
+# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include "BaseRngLibInternals.h"
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(ArmRndr)
+
+#/**
+# Generates a random number using RNDR.
+# Returns TRUE on success; FALSE on failure.
+#
+# @param[out] Rand Buffer pointer to store the 64-bit random value.
+#
+# @retval TRUE Random number generated successfully.
+# @retval FALSE Failed to generate the random number.
+#
+#**/
+#BOOLEAN
+#EFIAPI
+#ArmRndr (
+# OUT UINT64 *Rand
+# );
+#
+ASM_PFX(ArmRndr):
+ mrs x1, RNDR
+ str x1, [x0]
+ cset x0, ne // RNDR sets NZCV to 0b0100 on failure
+ ret
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm
new file mode 100644
index 000000000000..33144196cb54
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------
+;
+; ArmRndr() for AArch64
+;
+; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+#include "BaseRngLibInternals.h"
+
+ EXPORT ArmRndr
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+
+;/**
+; Generates a random number using RNDR.
+; Returns TRUE on success; FALSE on failure.
+;
+; @param[out] Rand Buffer pointer to store the 64-bit random value.
+;
+; @retval TRUE Random number generated successfully.
+; @retval FALSE Failed to generate the random number.
+;
+;**/
+;BOOLEAN
+;EFIAPI
+;ArmRndr (
+; OUT UINT64 *Rand
+; );
+;
+ArmRndr
+ mrs x1, RNDR
+ str x1, [x0]
+ cset x0, ne // RNDR sets NZCV to 0b0100 on failure
+ ret
+
+ END
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLib.uni b/MdePkg/Library/BaseRngLib/BaseRngLib.uni
index f3ed954c5209..de5d4f9dd869 100644
--- a/MdePkg/Library/BaseRngLib/BaseRngLib.uni
+++ b/MdePkg/Library/BaseRngLib/BaseRngLib.uni
@@ -1,8 +1,8 @@
// /** @file
// Instance of RNG (Random Number Generator) Library.
//
-// BaseRng Library that uses CPU RdRand instruction access to provide
-// high-quality random numbers.
+// BaseRng Library that uses CPU RNG instructions to provide
+// random numbers.
//
// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
//
@@ -13,5 +13,5 @@

#string STR_MODULE_ABSTRACT #language en-US "Instance of RNG Library"

-#string STR_MODULE_DESCRIPTION #language en-US "BaseRng Library that uses CPU RdRand instruction access to provide high-quality random numbers"
+#string STR_MODULE_DESCRIPTION #language en-US "BaseRng Library that uses CPU RNG instructions to provide random numbers"

--
2.26.2


[PATCH v3 0/2] MdePkg,SecurityPkg: Add support to RngDxe and BaseRngLib for AARCH64 RNDR

Rebecca Cran
 

Update MdePkg BaseRngLib and SecurityPkg RngDxe to add support for
the AARCH64 RNDR instruction.

Changes from v2 to v3:

o Fixed the default value of gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm
to be an empty GUID.
o Removed RNDRRS since it wasn't being used.
o Fixed the commit message to remove mention of BaseLib.

Rebecca Cran (2):
MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions
SecurityPkg: Add support for RngDxe on AARCH64

MdePkg/MdePkg.dec | 9 +-
SecurityPkg/SecurityPkg.dec | 2 +
MdePkg/MdePkg.dsc | 4 +-
SecurityPkg/SecurityPkg.dsc | 11 +-
MdePkg/Library/BaseRngLib/BaseRngLib.inf | 23 ++-
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf | 24 ++-
MdePkg/Library/BaseRngLib/AArch64/ArmRng.h | 43 +++++
MdePkg/Library/BaseRngLib/BaseRngLibInternals.h | 78 +++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h | 0
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h | 17 --
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h | 117 ++++++++++++++
MdePkg/Library/BaseRngLib/AArch64/Rndr.c | 139 ++++++++++++++++
MdePkg/Library/BaseRngLib/BaseRng.c | 87 +++++-----
MdePkg/Library/BaseRngLib/Rand/RdRand.c | 131 +++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c | 127 +++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c | 0
SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c | 45 +-----
SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c | 146 +++++++++++++++++
SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c | 170 ++++++++------------
MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S | 31 ++++
MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm | 30 ++++
MdePkg/Library/BaseRngLib/AArch64/ArmRng.S | 37 +++++
MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm | 39 +++++
MdePkg/Library/BaseRngLib/BaseRngLib.uni | 6 +-
24 files changed, 1086 insertions(+), 230 deletions(-)
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
create mode 100644 MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
rename SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h (100%)
rename SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h (72%)
create mode 100644 SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/Rndr.c
create mode 100644 MdePkg/Library/BaseRngLib/Rand/RdRand.c
create mode 100644 SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c
rename SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c (100%)
rename SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c (71%)
create mode 100644 SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.S
create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm

--
2.26.2


[edk2-platforms][PATCH V3 14/14] Platform/Sgi: ACPI PPTT table for RD-N2 platform

Pranav Madhu
 

The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 ++++++++++++++++=
++++
2 files changed, 177 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform=
/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 2ec3e42473a9..c1282a3422ab 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2/Dsdt.asl
RdN2/Madt.aslc
+ RdN2/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM=
/SgiPkg/AcpiTables/RdN2/Pptt.aslc
new file mode 100644
index 000000000000..16daf5b7f266
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -0,0 +1,175 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2 platform
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 pl=
atform
+* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 =
Data
+* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also i=
ncludes
+* system level cache of 32MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_1MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package), /* Parent */ =
\
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
+ 0 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Initialize child core */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) =
\
+ } =
\
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_32MB, /* Size */
+ 32768, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 13/14] Platform/Sgi: Add CPU container for RD-N2 platform

Pranav Madhu
 

The RD-N2 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 176 ++++++++++++++------
1 file changed, 128 insertions(+), 48 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl b/Platform/ARM/=
SgiPkg/AcpiTables/RdN2/Dsdt.asl
index 42cb8655b4fb..c5d6f44b3e44 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -13,100 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
- Device (CP00) { // Neoverse N2 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP01) { // Neoverse N2 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP02) { // Neoverse N2 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP03) { // Neoverse N2 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP04) { // Neoverse N2 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP05) { // Neoverse N2 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP06) { // Neoverse N2 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP07) { // Neoverse N2 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP08) { // Neoverse N2 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse N2 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP09) { // Neoverse N2 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse N2 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP10) { // Neoverse N2 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse N2 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP11) { // Neoverse N2 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse N2 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP12) { // Neoverse N2 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse N2 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP13) { // Neoverse N2 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse N2 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP14) { // Neoverse N2 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse N2 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP15) { // Neoverse N2 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse N2 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--=20
2.17.1


[edk2-platforms][PATCH V3 12/14] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform

Pranav Madhu
 

The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 184 ++++++++++++++=
++++++
2 files changed, 185 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platfo=
rm/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index c49546ec0b27..ffda4f925b19 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -24,6 +24,7 @@
RdV1Mc/Dsdt.asl
RdV1Mc/Hmat.aslc
RdV1Mc/Madt.aslc
+ RdV1Mc/Pptt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
new file mode 100644
index 000000000000..4b91aa9001cf
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -0,0 +1,184 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platfor=
m
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. Th=
e RD-V1
+* quad-chip platform is composed of four identical chips connected over =
cache
+* coherent interconnect. Each of the chip on the platform includes four =
single
+* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Inst=
ruction
+* cache and 1MB L2 cache. The platform also includes a system level cach=
e of
+* 16MB per chip.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_1MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId]), /* Parent */ =
\
+ ((PackageId << 2) | ClusterId), /* ACPI Id */ =
\
+ 0 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Initialize child core */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) =
\
+ } =
\
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ =
\
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ =
\
+ 0, /* Parent */ =
\
+ 0, /* ACPI Id */ =
\
+ 1 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Slc), =
\
+ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_16MB, /* Size */ =
\
+ 16384, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ { =
\
+ PPTT_CLUSTER_INIT (PackageId, 0), =
\
+ PPTT_CLUSTER_INIT (PackageId, 1), =
\
+ PPTT_CLUSTER_INIT (PackageId, 2), =
\
+ PPTT_CLUSTER_INIT (PackageId, 3), =
\
+ } =
\
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package[CHIP_=
COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 11/14] Platform/Sgi: Add CPU container for RD-V1 quad-chip platform

Pranav Madhu
 

The RD-V1 quad-chip platform is composed of four RD-V1 platforms
connected over a coherent link. Each chip has four CPU cores with each
core contained in a minimal cluster logic. Update the processor device
entries accordingly in the DSDT ACPI table by moving each of the
processor device entries into a separate processor container devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 ++++++++++++++-----=
-
1 file changed, 128 insertions(+), 49 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl b/Platform/AR=
M/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index b1e88587080c..16919cc5aaa0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -13,101 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
-
- Device (CP00) { // Neoverse V1 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse V1 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP01) { // Neoverse V1 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse V1 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP02) { // Neoverse V1 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse V1 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP03) { // Neoverse V1 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse V1 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP04) { // Neoverse V1 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse V1 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP05) { // Neoverse V1 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse V1 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP06) { // Neoverse V1 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse V1 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP07) { // Neoverse V1 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse V1 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP08) { // Neoverse V1 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse V1 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP09) { // Neoverse V1 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse V1 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP10) { // Neoverse V1 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse V1 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP11) { // Neoverse V1 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse V1 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP12) { // Neoverse V1 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse V1 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP13) { // Neoverse V1 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse V1 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP14) { // Neoverse V1 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse V1 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP15) { // Neoverse V1 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse V1 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--=20
2.17.1


[edk2-platforms][PATCH V3 10/14] Platform/Sgi: ACPI PPTT Table for RD-V1 platform

Pranav Madhu
 

The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 ++++++++++++++++=
++++
2 files changed, 177 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform=
/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
index a21dcfafef1a..a3e558cf1535 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1/Dsdt.asl
RdV1/Madt.aslc
+ RdV1/Pptt.aslc
Spcr.aslc
Ssdt.asl
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM=
/SgiPkg/AcpiTables/RdV1/Pptt.aslc
new file mode 100644
index 000000000000..e494b101e338
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -0,0 +1,175 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platf=
orm
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. =
The
+* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each o=
f the
+* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 =
cache.
+* The platform also includes a system level cache of 16MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_1MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package), /* Parent */ =
\
+ ((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
+ 0 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Initialize child core */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0) =
\
+ } =
\
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_16MB, /* Size */
+ 16384, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 09/14] Platform/Sgi: Add CPU container for RD-V1 platform

Pranav Madhu
 

The RD-V1 platform is a sixteen core platform with each core contained
in a minimal cluster logic. Update the processor device entries
accordingly in the DSDT ACPI table by moving each of the processor
device entries into a separate processor container device.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 176 ++++++++++++++------
1 file changed, 128 insertions(+), 48 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl b/Platform/ARM/=
SgiPkg/AcpiTables/RdV1/Dsdt.asl
index f3e31e4085a3..05e8601290e2 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -13,100 +13,180 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
- Device (CP00) { // Neoverse V1 core 0
- Name (_HID, "ACPI0007")
+ Device (CL00) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse V1 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP01) { // Neoverse V1 core 1
- Name (_HID, "ACPI0007")
+ Device (CL01) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
+
+ Device (CP01) { // Neoverse V1 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP02) { // Neoverse V1 core 2
- Name (_HID, "ACPI0007")
+ Device (CL02) { // Cluster 2
+ Name (_HID, "ACPI0010")
Name (_UID, 2)
- Name (_STA, 0xF)
+
+ Device (CP02) { // Neoverse V1 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP03) { // Neoverse V1 core 3
- Name (_HID, "ACPI0007")
+ Device (CL03) { // Cluster 3
+ Name (_HID, "ACPI0010")
Name (_UID, 3)
- Name (_STA, 0xF)
+
+ Device (CP03) { // Neoverse V1 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP04) { // Neoverse V1 core 4
- Name (_HID, "ACPI0007")
+ Device (CL04) { // Cluster 4
+ Name (_HID, "ACPI0010")
Name (_UID, 4)
- Name (_STA, 0xF)
+
+ Device (CP04) { // Neoverse V1 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP05) { // Neoverse V1 core 5
- Name (_HID, "ACPI0007")
+ Device (CL05) { // Cluster 5
+ Name (_HID, "ACPI0010")
Name (_UID, 5)
- Name (_STA, 0xF)
+
+ Device (CP05) { // Neoverse V1 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP06) { // Neoverse V1 core 6
- Name (_HID, "ACPI0007")
+ Device (CL06) { // Cluster 6
+ Name (_HID, "ACPI0010")
Name (_UID, 6)
- Name (_STA, 0xF)
+
+ Device (CP06) { // Neoverse V1 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP07) { // Neoverse V1 core 7
- Name (_HID, "ACPI0007")
+ Device (CL07) { // Cluster 7
+ Name (_HID, "ACPI0010")
Name (_UID, 7)
- Name (_STA, 0xF)
+
+ Device (CP07) { // Neoverse V1 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP08) { // Neoverse V1 core 8
- Name (_HID, "ACPI0007")
+ Device (CL08) { // Cluster 8
+ Name (_HID, "ACPI0010")
Name (_UID, 8)
- Name (_STA, 0xF)
+
+ Device (CP08) { // Neoverse V1 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP09) { // Neoverse V1 core 9
- Name (_HID, "ACPI0007")
+ Device (CL09) { // Cluster 9
+ Name (_HID, "ACPI0010")
Name (_UID, 9)
- Name (_STA, 0xF)
+
+ Device (CP09) { // Neoverse V1 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP10) { // Neoverse V1 core 10
- Name (_HID, "ACPI0007")
+ Device (CL10) { // Cluster 10
+ Name (_HID, "ACPI0010")
Name (_UID, 10)
- Name (_STA, 0xF)
+
+ Device (CP10) { // Neoverse V1 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP11) { // Neoverse V1 core 11
- Name (_HID, "ACPI0007")
+ Device (CL11) { // Cluster 11
+ Name (_HID, "ACPI0010")
Name (_UID, 11)
- Name (_STA, 0xF)
+
+ Device (CP11) { // Neoverse V1 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP12) { // Neoverse V1 core 12
- Name (_HID, "ACPI0007")
+ Device (CL12) { // Cluster 12
+ Name (_HID, "ACPI0010")
Name (_UID, 12)
- Name (_STA, 0xF)
+
+ Device (CP12) { // Neoverse V1 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP13) { // Neoverse V1 core 13
- Name (_HID, "ACPI0007")
+ Device (CL13) { // Cluster 13
+ Name (_HID, "ACPI0010")
Name (_UID, 13)
- Name (_STA, 0xF)
+
+ Device (CP13) { // Neoverse V1 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP14) { // Neoverse V1 core 14
- Name (_HID, "ACPI0007")
+ Device (CL14) { // Cluster 14
+ Name (_HID, "ACPI0010")
Name (_UID, 14)
- Name (_STA, 0xF)
+
+ Device (CP14) { // Neoverse V1 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP15) { // Neoverse V1 core 15
- Name (_HID, "ACPI0007")
+ Device (CL15) { // Cluster 15
+ Name (_HID, "ACPI0010")
Name (_UID, 15)
- Name (_STA, 0xF)
+
+ Device (CP15) { // Neoverse V1 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
}
} // Scope(_SB)
}
--=20
2.17.1


[edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform

Pranav Madhu
 

The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 ++++++++++++=
++++++++
2 files changed, 254 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Plat=
form/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+ RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform=
/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index 000000000000..91baab73d108
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,252 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-=
E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of th=
e CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cac=
he.
+* Each cluster includes a 2MB L3 cache. The platform also includes a sys=
tem
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE_E1 2
+
+/*!
+ \brief Define helper macro for populating processor thread informatio=
n.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+ \param ThreadId CPU thread number.
+*/
+#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ =
\
+ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId]), /* Parent */ =
\
+ ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), =
\
+ /* ACPI Id */ =
\
+ 0 /* Num of private resource *=
/ \
+ ) =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId]), /* Parent */ =
\
+ 0, /* ACPI Id */ =
\
+ 2 /* Num of private resour=
ce */ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_32KB, /* Size */ =
\
+ 128, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_32KB, /* Size */ =
\
+ 128, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_256KB, /* Size */ =
\
+ 1024, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* Thread Initialization */ =
\
+ { =
\
+ PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 0), =
\
+ PPTT_THREAD_INIT (PackageId, ClusterId, CpuId, 1) =
\
+ } =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package), /* Parent */ =
\
+ 0, /* ACPI Id */ =
\
+ 1 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].L3Cache), =
\
+ =
\
+ /* L3 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_2MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* Initialize child cores */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 3), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 4), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 5), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 6), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 7) =
\
+ } =
\
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), =
\
+ PPTT_PROCESSOR_PACKAGE_FLAGS, =
\
+ 0, =
\
+ 0, =
\
+ 1 =
\
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Slc), =
\
+ =
\
+ /* SLC parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_8MB, /* Size */ =
\
+ 8192, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ { =
\
+ PPTT_CLUSTER_INIT (PackageId, 0), =
\
+ PPTT_CLUSTER_INIT (PackageId, 1), =
\
+ } =
\
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+} RDE1EDGE_PPTT_THREAD;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
+} RDE1EDGE_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CO=
RE_E1];
+} RDE1EDGE_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDE1EDGE_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDE1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ PPTT_PACKAGE_INIT (0)
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 07/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip

Pranav Madhu
 

The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 207 ++++++++++=
++++++++++
2 files changed, 208 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Pl=
atform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index c7c29b9c5946..617519d9dd38 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -24,6 +24,7 @@
RdN1EdgeX2/Dsdt.asl
RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
+ RdN1EdgeX2/Pptt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platfo=
rm/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
new file mode 100644
index 000000000000..1f92af9496a1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -0,0 +1,207 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip pl=
atform
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT tabl=
e. The
+* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip plat=
forms
+* connected over cache coherent interconnect. Each of the RD-N1-Edge sin=
gle-chip
+* platform includes two clusters with four single-thread CPUS. Each of t=
he CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cac=
he. Each
+* cluster includes a 2MB L3 cache. Each instance of the chip includes a =
system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_512KB, /* Size */ =
\
+ 1024, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId]), /* Parent */ =
\
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ =
\
+ 1 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Cluster[ClusterId].L3Cache), =
\
+ =
\
+ /* L3 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_2MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* Initialize child cores */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) =
\
+ } =
\
+ }
+
+/*!
+ \brief Define helper macro for populating SoC package information.
+ \param PackageId Package instance number.
+*/
+#define PPTT_PACKAGE_INIT(PackageId) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ =
\
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ =
\
+ 0, /* Parent */ =
\
+ 0, /* ACPI Id */ =
\
+ 1 /* Num of private resource */ =
\
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package[PackageId].Slc), =
\
+ =
\
+ /* SLC parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_8MB, /* Size */ =
\
+ 8192, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ { =
\
+ PPTT_CLUSTER_INIT (PackageId, 0), =
\
+ PPTT_CLUSTER_INIT (PackageId, 1), =
\
+ } =
\
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGEX2_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_=
COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 06/14] Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform

Pranav Madhu
 

The RD-N1-Edge dual-chip platform is composed of two RD-N1-Edge
platforms connected over a coherent link. Each chip has two clusters
with four CPUs in each cluster. Add the Differentiated System
Description Table (DSDT) ACPI table for this platform with processor
container devices defined containing the corresponding processor
devices.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 2 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++++++++++=
++++++++++
2 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Pl=
atform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 76886d1c6a17..c7c29b9c5946 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -21,7 +21,7 @@
Gtdt.aslc
Iort.aslc
Mcfg.aslc
- RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Dsdt.asl
RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
RdN1EdgeX2/Srat.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl b/Platfor=
m/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
new file mode 100644
index 000000000000..2379f20a79ef
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -0,0 +1,136 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2021, ARM Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Section 5.2.11.1, Differentiated System Description Table
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ /* Chip 0 CPUs */
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+ }
+
+ /* Chip 1 CPUs */
+ Device (CLU2) { // Cluster 2
+ Name (_HID, "ACPI0010")
+ Name (_UID, 2)
+
+ Device (CP08) { // Neoverse-N1: Cluster 2, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Neoverse-N1: Cluster 2, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Neoverse-N1: Cluster 2, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Neoverse-N1: Cluster 2, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+ }
+
+ Device (CLU3) { // Cluster 3
+ Name (_HID, "ACPI0010")
+ Name (_UID, 3)
+
+ Device (CP12) { // Neoverse-N1: Cluster 3, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Neoverse-N1: Cluster 3, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Neoverse-N1: Cluster 3, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Neoverse-N1: Cluster 3, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+ }
+ } // Scope(_SB)
+}
--=20
2.17.1


[edk2-platforms][PATCH V3 05/14] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform

Pranav Madhu
 

The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 186 ++++++++++++=
++++++++
2 files changed, 188 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Plat=
form/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 22e33239070b..eecb64186473 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1Edge/Madt.aslc
+ RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform=
/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
new file mode 100644
index 000000000000..028efa908c54
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -0,0 +1,186 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip =
platform
+*
+* This file describes the topological structure of the processor block o=
n the
+* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT ta=
ble. The
+* RD-N1-Edge platform includes two clusters with four single-thread CPUS=
. Each
+* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and =
512KB L2
+* cache. Each cluster includes a 2MB L3 cache. The platform also include=
s a
+* system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_512KB, /* Size */ =
\
+ 1024, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package), /* Parent */ =
\
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ =
\
+ 1 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].L3Cache), =
\
+ =
\
+ /* L3 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_2MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* Initialize child cores */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) =
\
+ } =
\
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGE_PPTT_PACKAGE ;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_8MB, /* Size */
+ 8192, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 04/14] Platform/Sgi: Add CPU container for RD-N1-Edge

Pranav Madhu
 

The RD-N1-Edge platform includes two clusters with four single-thread
CPUs. Add processor container devices for the two clusters on the
RD-N1-Edge platform and move the existing processor devices into
respective processor containers.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 88 +++++++++++-------=
--
1 file changed, 48 insertions(+), 40 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl b/Platform/=
ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index d9bac33898b1..b88344c3a7ba 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -13,54 +13,62 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
-
- Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
- Name (_HID, "ACPI0007")
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
Name (_UID, 0)
- Name (_STA, 0xF)
+
+ Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
=20
- Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
- Name (_HID, "ACPI0007")
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
Name (_UID, 1)
- Name (_STA, 0xF)
- }
=20
- Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 2)
- Name (_STA, 0xF)
- }
+ Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
=20
- Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 3)
- Name (_STA, 0xF)
- }
+ Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
=20
- Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
- Name (_HID, "ACPI0007")
- Name (_UID, 4)
- Name (_STA, 0xF)
- }
+ Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
=20
- Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
- Name (_HID, "ACPI0007")
- Name (_UID, 5)
- Name (_STA, 0xF)
+ Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
-
- Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 6)
- Name (_STA, 0xF)
- }
-
- Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 7)
- Name (_STA, 0xF)
- }
-
} // Scope(_SB)
}
--=20
2.17.1


[edk2-platforms][PATCH V3 03/14] Platform/Sgi: ACPI PPTT table for SGI-575 platform

Pranav Madhu
 

The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 172 ++++++++++++++=
++++++
2 files changed, 174 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platfo=
rm/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index 2121fd39f2f0..b1ee16e98ea3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
Sgi575/Dsdt.asl
Sgi575/Madt.aslc
+ Sgi575/Pptt.aslc
Spcr.aslc
Ssdt.asl
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
new file mode 100644
index 000000000000..f3032b7e4cdc
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
@@ -0,0 +1,172 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for SGI-575 platform
+*
+* This file describes the topological structure of the processor block o=
n the
+* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-57=
5
+* platform includes two clusters with four single-thread CPUS. Each of t=
he CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cac=
he.
+* Each cluster includes a 2MB L3 cache.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
+ { =
\
+ /* Parameters for CPU Core */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId]), /* Parent */ =
\
+ ((PackageId << 3) | (ClusterId << 2) | CpuId), /* ACPI Id */ =
\
+ 2 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ { =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
+ }, =
\
+ =
\
+ /* L1 data cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 64, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L1 instruction cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
+ /* Next level of cache */ =
\
+ SIZE_64KB, /* Size */ =
\
+ 256, /* Num of sets */ =
\
+ 4, /* Associativity */ =
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* L2 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_512KB, /* Size */ =
\
+ 1024, /* Num of sets */ =
\
+ 8, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor container informa=
tion.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+*/
+#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
+ { =
\
+ /* Parameters for Cluster */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), =
\
+ /* Length */ =
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package), /* Parent */ =
\
+ ((PackageId << 1) | ClusterId), /* ACPI Id */ =
\
+ 1 /* Num of private resource *=
/ \
+ ), =
\
+ =
\
+ /* Offsets of the private resources */ =
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ Package.Cluster[ClusterId].L3Cache), =
\
+ =
\
+ /* L3 cache parameters */ =
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
+ 0, /* Next level of cache */ =
\
+ SIZE_2MB, /* Size */ =
\
+ 2048, /* Num of sets */ =
\
+ 16, /* Associativity */ =
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
+ 64 /* Line size */ =
\
+ ), =
\
+ =
\
+ /* Initialize child cores */ =
\
+ { =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 0), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 1), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 2), =
\
+ PPTT_CORE_INIT (PackageId, ClusterId, 3) =
\
+ } =
\
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} SGI575_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ SGI575_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from rem=
oving
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable =3D &Pptt;
--=20
2.17.1


[edk2-platforms][PATCH V3 02/14] Platform/Sgi: Add CPU container for SGI-575

Pranav Madhu
 

The SGI-575 platform includes two clusters with four single-thread CPUs.
Add processor container devices for the two clusters on the SGI-575
platform and move the existing processor devices into respective
processor containers.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 99 +++++++++++---------
1 file changed, 54 insertions(+), 45 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl b/Platform/AR=
M/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index fe0b92137bde..7390849e6231 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -12,53 +12,62 @@
=20
DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI=
_ARM_OEM_REVISION) {
Scope(_SB) {
-
- Device(CP00) { // A75-0: Cluster 0, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- Name(_STA, 0xF)
- }
-
- Device(CP01) { // A75-0: Cluster 0, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- Name(_STA, 0xF)
- }
-
- Device(CP02) { // A75-0: Cluster 0, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- Name(_STA, 0xF)
- }
-
- Device(CP03) { // A75-0: Cluster 0, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- Name(_STA, 0xF)
- }
-
- Device(CP04) { // A75-0: Cluster 1, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- Name(_STA, 0xF)
- }
-
- Device(CP05) { // A75-0: Cluster 1, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- Name(_STA, 0xF)
- }
-
- Device(CP06) { // A75-0: Cluster 1, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- Name(_STA, 0xF)
+ Device (CLU0) { // Cluster 0
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+
+ Device (CP00) { // A75-0: Cluster 0, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // A75-0: Cluster 0, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // A75-0: Cluster 0, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // A75-0: Cluster 0, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
}
=20
- Device(CP07) { // A75-0: Cluster 1, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- Name(_STA, 0xF)
+ Device (CLU1) { // Cluster 1
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+
+ Device (CP04) { // A75-0: Cluster 1, Cpu 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // A75-0: Cluster 1, Cpu 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // A75-0: Cluster 1, Cpu 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // A75-0: Cluster 1, Cpu 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
}
=20
// UART PL011
--=20
2.17.1


[edk2-platforms][PATCH V3 01/14] Platform/Sgi: Helper macros for PPTT Table

Pranav Madhu
 

Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 170 ++++++++++++++++++++
1 file changed, 170 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/S=
giPkg/Include/SgiAcpiHeader.h
index dcb4e6c77a74..23e6ee14a761 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -20,6 +20,141 @@
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
=20
+#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
+#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
+
+#pragma pack(1)
+// PPTT processor core structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 ResourceOffset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+} RD_PPTT_CORE;
+
+// PPTT processor cluster structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_CLUSTER;
+
+// PPTT processor cluster structure without cache
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_MINIMAL_CLUSTER;
+
+// PPTT processor package structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
+} RD_PPTT_SLC_PACKAGE;
+#pragma pack ()
+
+//
+// PPTT processor structure flags for different SoC components as define=
d in
+// ACPI 6.3 specification
+//
+
+// Processor structure flags for SoC package
+#define PPTT_PROCESSOR_PACKAGE_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, =
\
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL =
\
+ }
+
+// Processor structure flags for cluster
+#define PPTT_PROCESSOR_CLUSTER_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, =
\
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL =
\
+ }
+
+// Processor structure flags for cluster with multi-thread core
+#define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, =
\
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL =
\
+ }
+
+// Processor structure flags for single-thread core
+#define PPTT_PROCESSOR_CORE_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF =
\
+ }
+
+// Processor structure flags for multi-thread core
+#define PPTT_PROCESSOR_CORE_THREADED_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, =
\
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL =
\
+ }
+
+// Processor structure flags for CPU thread
+#define PPTT_PROCESSOR_THREAD_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, =
\
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, =
\
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF =
\
+ }
+
+// PPTT cache structure flags as defined in ACPI 6.3 Specification
+#define PPTT_CACHE_STRUCTURE_FLAGS =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, =
\
+ EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, =
\
+ EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, =
\
+ EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, =
\
+ EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, =
\
+ EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, =
\
+ EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID =
\
+ }
+
+// PPTT cache attributes for data cache
+#define PPTT_DATA_CACHE_ATTR =
\
+ { =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK =
\
+ }
+
+// PPTT cache attributes for instruction cache
+#define PPTT_INST_CACHE_ATTR =
\
+ { =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK =
\
+ }
+
+// PPTT cache attributes for unified cache
+#define PPTT_UNIFIED_CACHE_ATTR =
\
+ { =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, =
\
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK =
\
+ }
+
// A macro to initialise the common header part of EFI ACPI tables as de=
fined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
@@ -246,4 +381,39 @@
TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLi=
neSize \
}
=20
+// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent,=
\
+ ACPIProcessorID, NumberOfPrivateResource) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ =
\
+ Length, /* Length */ =
\
+ { =
\
+ EFI_ACPI_RESERVED_BYTE, =
\
+ EFI_ACPI_RESERVED_BYTE, =
\
+ }, =
\
+ Flag, /* Processor flags=
*/ \
+ Parent, /* Ref to parent n=
ode */ \
+ ACPIProcessorID, /* UID, as per MAD=
T */ \
+ NumberOfPrivateResource /* Resource count =
*/ \
+ }
+
+// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Siz=
e, \
+ NoOfSets, Associativity, Attributes, LineSize) =
\
+ { =
\
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ =
\
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ =
\
+ { =
\
+ EFI_ACPI_RESERVED_BYTE, =
\
+ EFI_ACPI_RESERVED_BYTE, =
\
+ }, =
\
+ Flag, /* Cache flags */ =
\
+ NextLevelCache, /* Ref to next lev=
el */ \
+ Size, /* Size in bytes *=
/ \
+ NoOfSets, /* Num of sets */ =
\
+ Associativity, /* Num of ways */ =
\
+ Attributes, /* Cache attribute=
s */ \
+ LineSize /* Line size in by=
tes */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--=20
2.17.1

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