Create a PR https://github.com/tianocore/edk2/pull/1500

Thanks,
Bob

The following files have been updated in the Files area of the devel@edk2.groups.io group.

• //Designs/2021/0319/New EFI Protocols for edk2 Redfish Implementation_v2.pdf

By: Nickle Wang <nickle.wang@...>

Reviewed-by: Eric Dong <eric.dong@...>

(Top posting, maybe that way I'll have more luck.)

Min Xu -- it's not really trust-inspiring to not receive any feedback
(not even an out-of-office auto-response) from you, in a week, for a
Maintainers.txt patch that designates you as a reviewer for confidential
computing in OVMF. If we are to extrapolate from this responsiveness,
what should we expect for actual *patch* reviews?

Would you like me to drop your name & entry from patch#2?

Laszlo

Hi Laszlo

Thanks for the remind. I will take care the date and Patch v4 in our next patch.

Thanks,
Ian Kuo

Vincent, Ian:

something is seriously broken in your email setup. I have seen three
messages from you guys on the list, and each one of those is "from the
future". Here are the Date headers from the messages:

- Date: Thu, 8 Apr 2021 05:50:21 +0800
https://edk2.groups.io/g/devel/message/72748

- Date: Sat, 10 Apr 2021 01:34:45 +0800
https://edk2.groups.io/g/devel/message/72862

- Date: Sat, 10 Apr 2021 22:15:09 +0800
https://edk2.groups.io/g/devel/message/72953

Please fix your clock setup, and post a new version.

This is why I am asking: the git-am manual says,

--ignore-date
By default the command records the date from the e-mail
message as the commit author date, and uses the time of
commit creation as the committer date. [...]

When we merge a patch using a github.com Pull Request, the "mergify bot"
preserves the Author Date field. That's a good thing in itself, but it
means that the edk2 commit history would have a patch from the future --
a patch committed in March, but "authored" in April. That's bogus.

Whoever actually applies the patch (probably the ShellPkg maintainer)
can work around the issue, by specifying the "--ignore-date" flag for
"git-am". But that's easy to forget, and not the right thing anyway.

So please just fix your broken clock, and post a new version.

Also: you should have used v1, v2, v3 in the subject prefixes (just pass
-v1, -v2, -v3 to git-format-patch). The next version that you post
should be marked "v4".

Thanks
Laszlo

GenFw will embed a NM10 section which contains the path to the input file,
which means the output files have build paths embedded in them. To reduce
information leakage and ensure reproducible builds, pass --zero in release
builds to remove this information.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3256
Change-Id: Ie607893b979674e237cf04ead5c7690d7b1aedaf
Signed-off-by: Ross Burton <ross.burton@...>
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 1 +
OvmfPkg/Bhyve/BhyveX64.dsc | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 2 ++
OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
OvmfPkg/OvmfPkgX64.dsc | 1 +
OvmfPkg/OvmfXen.dsc | 1 +
6 files changed, 7 insertions(+)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index 65c42284d9..69a05feea9 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -78,6 +78,7 @@
GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
!endif=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
=0D
#=0D
# Disable deprecated APIs.=0D
diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc
index 4a1cdf5aca..132f55cf69 100644
--- a/OvmfPkg/Bhyve/BhyveX64.dsc
+++ b/OvmfPkg/Bhyve/BhyveX64.dsc
@@ -76,6 +76,7 @@
GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
!endif=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
=0D
#=0D
# Disable deprecated APIs.=0D
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 1eaf3e99c6..ce20f09df8 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -90,6 +90,8 @@
=0D
!include NetworkPkg/NetworkBuildOptions.dsc.inc=0D
=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
+=0D
[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]=0D
GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D
XCODE:*_*_*_DLINK_FLAGS =3D -seg1addr 0x1000 -segalign 0x1000=0D
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 4a5a430147..97cc438250 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -84,6 +84,7 @@
GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
!endif=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
=0D
#=0D
# Disable deprecated APIs.=0D
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index d4d601b444..f544fb04bf 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -84,6 +84,7 @@
GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
!endif=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
=0D
#=0D
# Disable deprecated APIs.=0D
diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc
index 507029404f..fcaa35acf1 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -74,6 +74,7 @@
GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D
!endif=0D
+ RELEASE_*_*_GENFW_FLAGS =3D --zero=0D
=0D
#=0D
# Disable deprecated APIs.=0D
--=20
2.25.1

在 2021/3/13 上午4:42, Laszlo Ersek 写道:

On 03/11/21 15:48, Xiaohe Yang wrote:

Hello, I am using EDK2  OvmfPkgX64 at commit 37568365, and have a
problem. The following is the detail.


The Image disk that I use has EFI system partition, and is configured as
a virtio-blk-pci device. Bootorder file-entry is not added in fw_cfg
device. The log of EDK2 shows that

(1)  VirtioBlkDxe.efi is successfully loaded at DXE stage.
BootScriptExecutorDxe drivers "was discovered but not loaded".

(2) PCI enumeration has finished at the start of BDS stage,
virtio-blk-pci device is discovered. And one Option Rom's address is 0/0.

(3) Before entering Shell, log shows "map: No mapping found".

(4) After entering Shell, I choose “Boot From File”, the virtio-blk-pci
device is not displayed.


So I wonder what are the requirements for UEFI to detect the
virtio-blk-pci device as a boot device, except having EFI system partition?

If you have a firmware log with DEBUG_VERBOSE enabled, I could take a look.

Assuming you are *not* on QEMU (e.g., you are developing a new
virtio-blk device, and running OVMF on your non-QEMU emulator), it could
be anything, really. Try to add DEBUG messages to the following drivers
/ functions:

Yes, I am developing a new virtio-blk device on my non-QEMU emulator.

- VirtioPciDeviceDxe
- VirtioPciDeviceBindingSupported
- VirtioPciDeviceBindingStart

- Virtio10Dxe
- Virtio10BindingSupported
- Virtio10BindingStart

- VirtioBlkDxe
- VirtioBlkDriverBindingSupported
- VirtioBlkDriverBindingStart

These drivers all follow the UEFI driver model. So, if you find no
mapping for the virtio-blk-pci device in the UEFI shell, then they fail
to bind your device implementation for some reason.

You mention that there is no "bootorder" fw_cfg file, so
PlatformBdsConnectSequence() will see ConnectDevicesFromQemu() fail, and
then EfiBootManagerConnectAll() will be called. If the virtio-blk-pci
devices are not connected under those circumstances, then they don't do
something that the virtio PCI transport drivers (0.9.5 or 1.0) expect,
or the virtio-blk device driver expects. There's no silver bullet, you
may have to add DEBUGs to various spots in these drivers, to see what fails.

Thanks
Laszlo

I follow your suggestions and add more debug infos, and the problem is fixed.


Thanks for your help.

Xiaohe Yang

The RealTimeClockLib implemented EFI RealTimeClock
runtime services via RTC Lib.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec =
| 1 +
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 2 +
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf =
| 39 ++
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h =
| 24 +
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c =
| 462 ++++++++++++++++++++
6 files changed, 534 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico=
n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 2686ba3cc3..4c6c5c5f11 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -45,6 +45,7 @@
gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005=0D
gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x0000000=
6=0D
gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x0000000=
7=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008=0D
=0D
[Protocols]=0D
gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0=
x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 99034365d3..9579f8e9b7 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -29,6 +29,10 @@
# Phytium Platform library=0D
ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformL=
ib.inf=0D
=0D
+ #FT2000-4Pkg RTC Driver=0D
+ RealTimeClockLib|Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/Re=
alTimeClockLib.inf=0D
+ TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf=0D
+=0D
# PL011 UART Driver and Dependency Libraries=0D
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL=
ib.inf=0D
PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc=
kLib.inf=0D
@@ -168,6 +172,8 @@
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D
}=0D
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf=0D
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf=0D
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
=0D
#=0D
# Common Arm Timer and Gic Components=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 67458458dd..242f647ca1 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -93,6 +93,8 @@ READ_LOCK_STATUS =3D TRUE
#=0D
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf=0D
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
=0D
INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTime=
ClockLib.inf
new file mode 100644
index 0000000000..09a06d53ae
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.inf
@@ -0,0 +1,39 @@
+#/** @file=0D
+# Phytium RealTime Clock Library file.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D RealTimeClockLib=0D
+ FILE_GUID =3D fb320c94-40fe-11eb-b990-171865af292c=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D RealTimeClockLib=0D
+=0D
+[Sources.common]=0D
+ RealTimeClockLib.c=0D
+ RealTimeClockLib.h=0D
+=0D
+[Packages]=0D
+ ArmPlatformPkg/ArmPlatformPkg.dec=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ DxeServicesTableLib=0D
+ IoLib=0D
+ TimeBaseLib=0D
+ UefiRuntimeLib=0D
+=0D
+[Guids]=0D
+ gEfiEventVirtualAddressChangeGuid=0D
+=0D
+[Pcd]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.h b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl=
ockLib.h
new file mode 100644
index 0000000000..41ce002dc3
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.h
@@ -0,0 +1,24 @@
+/** @file=0D
+ Phytium RealTime Clock Header.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef REAL_TIME_CLOCK_H_=0D
+#define REAL_TIME_CLOCK_H_=0D
+=0D
+#define RTC_CMR 0x4=0D
+#define RTC_AES_SEL 0x8=0D
+#define RTC_CCR 0xC=0D
+#define RTC_STAT 0x10=0D
+#define RTC_RSTAT 0x14=0D
+#define RTC_EOI 0x18=0D
+#define RTC_CDR_LOW 0x20=0D
+#define RTC_CCVR 0x24=0D
+#define RTC_CLR_LOW 0x28=0D
+#define RTC_CLR 0x2C=0D
+=0D
+#endif // REAL_TIME_CLOCK_H_=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl=
ockLib.c
new file mode 100644
index 0000000000..bf3047fb67
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.c
@@ -0,0 +1,462 @@
+/** @file=0D
+ Implement EFI RealTimeClock runtime services via RTC Lib.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <PiDxe.h>=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DxeServicesTableLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/TimeBaseLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiRuntimeLib.h>=0D
+#include <Protocol/RealTimeClock.h>=0D
+#include "RealTimeClockLib.h"=0D
+=0D
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;=0D
+STATIC UINTN mRtcBase;=0D
+STATIC CONST CHAR16 mTimeZoneVariableName[] =3D L"RtcTimeZone";=0D
+STATIC CONST CHAR16 mDaylightVariableName[] =3D L"RtcDaylight";=0D
+=0D
+/**=0D
+ Returns the current time and date information, and the time-keeping capa=
bilities=0D
+ of the hardware platform.=0D
+=0D
+ @param Time A pointer to storage to receive a snapsho=
t of the current time.=0D
+ @param Capabilities An optional pointer to a buffer to receiv=
e the real time clock=0D
+ device's capabilities.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER Time is NULL.=0D
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to ha=
rdware error.=0D
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an=
authentication failure.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibGetTime (=0D
+ OUT EFI_TIME *Time,=0D
+ OUT EFI_TIME_CAPABILITIES *Capabilities=0D
+ )=0D
+{=0D
+ UINT32 EpochSeconds;=0D
+ INT16 TimeZone;=0D
+ UINT8 Daylight;=0D
+ UINTN Size;=0D
+ EFI_STATUS Status;=0D
+=0D
+ // Ensure Time is a valid pointer=0D
+ if (Time =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100);=0D
+ //=0D
+ //read cdr high 32bit=0D
+ //=0D
+ EpochSeconds =3D MmioRead32 (mRtcBase + RTC_CCVR);=0D
+ MmioRead32 (mRtcBase + RTC_CDR_LOW);=0D
+ //=0D
+ // Get the current time zone information from non-volatile storage=0D
+ //=0D
+ Size =3D sizeof (TimeZone);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&TimeZone=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The time zone variable does not exist in non-volatile storage, so c=
reate it.=0D
+ //UTC+8:00=0D
+ //=0D
+ Time->TimeZone =3D -480;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_=
VARIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time->TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ } else {=0D
+ //=0D
+ // Got the time zone=0D
+ //=0D
+ Time->TimeZone =3D TimeZone;=0D
+ //=0D
+ // Check TimeZone bounds: -1440 to 1440 or 2047=0D
+ //=0D
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))=0D
+ && (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE)) {=0D
+ Time->TimeZone =3D EFI_UNSPECIFIED_TIMEZONE;=0D
+ }=0D
+ //=0D
+ // Adjust for the correct time zone=0D
+ //=0D
+ if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) {=0D
+ EpochSeconds -=3D Time->TimeZone * SEC_PER_MIN;=0D
+ }=0D
+ }=0D
+ //=0D
+ // Get the current daylight information from non-volatile storage=0D
+ //=0D
+ Size =3D sizeof (Daylight);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&Daylight=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The daylight variable does not exist in non-volatile storage, so cr=
eate it.=0D
+ //=0D
+ Time->Daylight =3D 0;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_=
VARIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time->Daylight)=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ } else {=0D
+ //=0D
+ // Got the daylight information=0D
+ //=0D
+ Time->Daylight =3D Daylight;=0D
+ //=0D
+ // Adjust for the correct period=0D
+ //=0D
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGH=
T) {=0D
+ //=0D
+ // Convert to adjusted time, i.e. spring forwards one hour=0D
+ //=0D
+ EpochSeconds +=3D SEC_PER_HOUR;=0D
+ }=0D
+ }=0D
+=0D
+ //=0D
+ // Convert from internal 32-bit time to UEFI time=0D
+ //=0D
+ EpochToEfiTime (EpochSeconds, Time);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Sets the current local time and date information.=0D
+=0D
+ @param[in] Time A pointer to the current time.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER A time field is out of range.=0D
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardw=
are error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibSetTime (=0D
+ IN EFI_TIME *Time=0D
+ )=0D
+{=0D
+ UINTN EpochSeconds;=0D
+ EFI_STATUS Status;=0D
+ //=0D
+ // the maximum time span is just over 136 years.=0D
+ // Time is stored in Unix Epoch format, so it starts in 1970,=0D
+ // Therefore it can not exceed the year 2106.=0D
+ //=0D
+ if ((Time->Year < 1970) || (Time->Year >=3D 2106)) {=0D
+ return EFI_UNSUPPORTED;=0D
+ }=0D
+ EpochSeconds =3D EfiTimeToEpoch (Time);=0D
+ //=0D
+ // Adjust for the correct time zone, i.e. convert to UTC time zone=0D
+ //=0D
+ if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) {=0D
+ EpochSeconds +=3D Time->TimeZone * SEC_PER_MIN;=0D
+ }=0D
+ //=0D
+ // Adjust for the correct period=0D
+ //=0D
+ if (((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGHT=
)=0D
+ && (EpochSeconds > SEC_PER_HOUR)) {=0D
+ //=0D
+ // Convert to un-adjusted time, i.e. fall back one hour=0D
+ //=0D
+ EpochSeconds -=3D SEC_PER_HOUR;=0D
+ }=0D
+ //=0D
+ // Set the Rtc=0D
+ //=0D
+ MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100);=0D
+ MmioWrite32 (mRtcBase + RTC_CLR_LOW, 0x0);=0D
+ MmioWrite32 (mRtcBase + RTC_CLR, (UINT32)EpochSeconds);=0D
+ //=0D
+ // Save the current time zone information into non-volatile storage=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ sizeof (Time->TimeZone),=0D
+ (VOID *)&(Time->TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ // Save the current daylight information into non-volatile storage=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ sizeof (Time->Daylight),=0D
+ (VOID *)&(Time->Daylight)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Returns the current wakeup alarm clock setting.=0D
+=0D
+ @param[out] Enabled Indicates if the alarm is currently e=
nabled or disabled.=0D
+ @param[out] Pending Indicates if the alarm signal is pend=
ing and requires acknowledgement.=0D
+ @param[out] Time The current alarm setting.=0D
+=0D
+ @retval EFI_SUCCESS The alarm settings were returned.=0D
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.=0D
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieve=
d due to a hardware error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibGetWakeupTime (=0D
+ OUT BOOLEAN *Enabled,=0D
+ OUT BOOLEAN *Pending,=0D
+ OUT EFI_TIME *Time=0D
+ )=0D
+{=0D
+ // Not a required feature=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Sets the system wakeup alarm clock time.=0D
+=0D
+ @param[in] Enabled Enable or disable the wakeup alarm.=0D
+ @param[out] Time If Enable is TRUE, the time to set th=
e wakeup alarm for.=0D
+=0D
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup al=
arm was enabled. If=0D
+ Enable is FALSE, then the wakeup alar=
m was disabled.=0D
+ @retval EFI_INVALID_PARAMETER A time field is out of range.=0D
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due =
to a hardware error.=0D
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on th=
is platform.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibSetWakeupTime (=0D
+ IN BOOLEAN Enabled,=0D
+ OUT EFI_TIME *Time=0D
+ )=0D
+{=0D
+ // Not a required feature=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+/**=0D
+ Fixup internal data so that EFI can be call in virtual mode.=0D
+ Call the passed in Child Notify event and convert any pointers in=0D
+ lib to virtual mode.=0D
+=0D
+ @param[in] Event The Event that is being processed=0D
+ @param[in] Context Event Context=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+LibRtcVirtualNotifyEvent (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ //=0D
+ // Only needed if you are going to support the OS calling RTC functions =
in virtual mode.=0D
+ // You will need to call EfiConvertPointer (). To convert any stored phy=
sical addresses=0D
+ // to virtual address. After the OS transitions to calling in virtual mo=
de, all future=0D
+ // runtime calls will be made in virtual mode.=0D
+ //=0D
+ EfiConvertPointer (0x0, (VOID **)&mRtcBase);=0D
+=0D
+ return;=0D
+}=0D
+=0D
+/**=0D
+ This is the declaration of an EFI image entry point. This can be the ent=
ry point to an application=0D
+ written to this specification, an EFI boot service driver, or an EFI run=
time driver.=0D
+=0D
+ @param[in] ImageHandle Handle that identifies the loaded imag=
e.=0D
+ @param[in] SystemTable System Table for this image.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=
=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibRtcInitialize (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_HANDLE Handle;=0D
+ INT16 TimeZone;=0D
+ UINTN Size;=0D
+ EFI_TIME Time;=0D
+ UINT8 Daylight;=0D
+ //=0D
+ // Initialize RTC Base Address=0D
+ //=0D
+ mRtcBase =3D PcdGet32 (PcdRtcBaseAddress);=0D
+ //=0D
+ // Declare the controller as EFI_MEMORY_RUNTIME=0D
+ //=0D
+ Status =3D gDS->AddMemorySpace (=0D
+ EfiGcdMemoryTypeMemoryMappedIo,=0D
+ mRtcBase,=0D
+ SIZE_4KB,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ //init timezone=0D
+ //=0D
+ Size =3D sizeof (TimeZone);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&TimeZone=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The time zone variable does not exist in non-volatile storage, so c=
reate it.=0D
+ //UTC 8:00=0D
+ //=0D
+ Time.TimeZone =3D -480;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time.TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+ //=0D
+ //daylight init=0D
+ //=0D
+ Size =3D sizeof (Daylight);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&Daylight=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The daylight variable does not exist in non-volatile storage, so cr=
eate it.=0D
+ //=0D
+ Time.Daylight =3D 0;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time.Daylight)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+=0D
+ Status =3D gDS->SetMemorySpaceAttributes (mRtcBase, SIZE_4KB, EFI_MEMORY=
_UC | EFI_MEMORY_RUNTIME);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ // Install the protocol=0D
+ //=0D
+ Handle =3D NULL;=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &Handle,=0D
+ &gEfiRealTimeClockArchProtocolGuid,=0D
+ NULL,=0D
+ NULL=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ //=0D
+ // Register for the virtual address change event=0D
+ //=0D
+ Status =3D gBS->CreateEventEx (=0D
+ EVT_NOTIFY_SIGNAL,=0D
+ TPL_NOTIFY,=0D
+ LibRtcVirtualNotifyEvent,=0D
+ NULL,=0D
+ &gEfiEventVirtualAddressChangeGuid,=0D
+ &mRtcVirtualAddrChangeEvent=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
--=20
2.25.1

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Maintainers.txt | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index afbd2cff0e..b6cfe74e09 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -321,3 +321,11 @@ F: Silicon/SiFive/
M: Abner Chang <abner.chang@...>=0D
M: Gilbert Chen <gilbert.chen@...>=0D
R: Daniel Schaefer <daniel.schaefer@...>=0D
+=0D
+Phytium platforms and silicon=0D
+F: Platform/Phytium/=0D
+F: Silicon/silicon/=0D
+M: Leif Lindholm <leif@...>=0D
+R: Peng Xie <xiepeng@...>=0D
+R: Ling Jia <jialing@...>=0D
+R: Yiqi Shu <shuyiqi@...>=0D
--=20
2.25.1

The FlashFvbDxe provided the fvb protocol,
which requested by the flash operators.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | =
1 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | =
1 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 6=
1 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 10=
4 ++
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 130=
4 ++++++++++++++++++++
5 files changed, 1471 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 1c47051441..99034365d3 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -253,6 +253,7 @@
# NOR Flash driver=0D
#=0D
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf=0D
+ Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf=0D
=0D
#=0D
# Usb Support=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 831f7a6828..67458458dd 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -103,6 +103,7 @@ READ_LOCK_STATUS =3D TRUE
=0D
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D
+ INF Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf=
=0D
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D
=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.i=
nf
new file mode 100644
index 0000000000..ff23721d6e
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
@@ -0,0 +1,61 @@
+#/** @file=0D
+# Phytium NorFlash Fvb Drivers.=0D
+#=0D
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D FlashFvbDxe=0D
+ FILE_GUID =3D b8923820-3e7c-11eb-b12c-17525e90ecc8=
=0D
+ MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D
+ VERSION_STRING =3D 0.1=0D
+ ENTRY_POINT =3D FvbEntryPoint=0D
+=0D
+[Sources]=0D
+ FlashFvbDxe.c=0D
+ FlashFvbDxe.h=0D
+=0D
+[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ DxeServicesTableLib=0D
+ HobLib=0D
+ MemoryAllocationLib=0D
+ UefiBootServicesTableLib=0D
+ UefiRuntimeLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[Guids]=0D
+ gEfiAuthenticatedVariableGuid=0D
+ gEfiEventVirtualAddressChangeGuid=0D
+ gEfiSystemNvDataFvGuid=0D
+ gEfiVariableGuid=0D
+=0D
+[Protocols]=0D
+ gEfiDevicePathProtocolGuid=0D
+ gEfiFirmwareVolumeBlockProtocolGuid=0D
+ gSpiNorFlashProtocolGuid=0D
+=0D
+[Pcd.common]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize=0D
+=0D
+[Depex]=0D
+ gSpiNorFlashProtocolGuid=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.h b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
new file mode 100644
index 0000000000..e63ff9f220
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
@@ -0,0 +1,104 @@
+/** @file=0D
+ Phytium NorFlash Fvb Drivers Header.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+#ifndef FVB_FLASH_DXE_H_=0D
+#define FVB_FLASH_DXE_H_=0D
+=0D
+#include <Protocol/BlockIo.h>=0D
+#include <Protocol/FirmwareVolumeBlock.h>=0D
+#include <Protocol/SpiNorFlashProtocol.h>=0D
+=0D
+#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba=
) * (LbaSize)))=0D
+#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'N', '=
O', 'R')=0D
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, FT_FVB_DEVICE, Fvb=
Protocol, FVB_FLASH_SIGNATURE)=0D
+=0D
+typedef struct _FT_FVB_DEVICE FT_FVB_DEVICE;=0D
+=0D
+#define NOR_FLASH_ERASE_RETRY 10=0D
+=0D
+typedef struct {=0D
+ VENDOR_DEVICE_PATH Vendor;=0D
+ EFI_DEVICE_PATH_PROTOCOL End;=0D
+ } FT_FVB_DEVICE_PATH;=0D
+=0D
+struct _FT_FVB_DEVICE {=0D
+ UINT32 Signature;=0D
+ EFI_HANDLE Handle;=0D
+=0D
+ UINTN DeviceBaseAddress;=0D
+ UINTN RegionBaseAddress;=0D
+ UINTN Size;=0D
+ EFI_LBA StartLba;=0D
+ EFI_BLOCK_IO_MEDIA Media;=0D
+=0D
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;=0D
+=0D
+ FT_FVB_DEVICE_PATH DevicePath;=0D
+ EFI_NORFLASH_DRV_PROTOCOL *SpiFlashProtocol;=0D
+ VOID *ShadowBuffer;=0D
+ UINTN FvbSize;=0D
+ };=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ OUT EFI_FVB_ATTRIBUTES_2 * Attributes=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbSetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN OUT EFI_FVB_ATTRIBUTES_2 * Attributes=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetPhysicalAddress (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ OUT EFI_PHYSICAL_ADDRESS * Address=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetBlockSize (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ OUT UINTN * BlockSize,=0D
+ OUT UINTN * NumberOfBlocks=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbRead (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN * NumBytes,=0D
+ IN OUT UINT8 * Buffer=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbWrite (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN * NumBytes,=0D
+ IN UINT8 * Buffer=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEraseBlocks (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ ...=0D
+ );=0D
+=0D
+#endif // FVB_FLASH_DXE_H_=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
new file mode 100644
index 0000000000..794db68987
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
@@ -0,0 +1,1304 @@
+/** @file=0D
+ Phytium NorFlash Fvb Drivers.=0D
+=0D
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/BaseLib.h>=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DxeServicesTableLib.h>=0D
+#include <Library/HobLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiRuntimeLib.h>=0D
+#include <Guid/VariableFormat.h>=0D
+=0D
+#include "FlashFvbDxe.h"=0D
+=0D
+STATIC EFI_EVENT FvbVirtualAddrChangeEvent;=0D
+STATIC FT_FVB_DEVICE *FvbDevice;=0D
+STATIC UINTN mFlashNvStorageVariableBase;=0D
+STATIC UINTN mFlashNvStorageFtwWorkingBase;=0D
+STATIC UINTN mFlashNvStorageFtwSpareBase;=0D
+STATIC UINT32 mFlashNvStorageVariableSize;=0D
+STATIC UINT32 mFlashNvStorageFtwWorkingSize;=0D
+STATIC UINT32 mFlashNvStorageFtwSpareSize;=0D
+=0D
+STATIC FT_FVB_DEVICE FvbFlashInstanceTemplate =3D {=0D
+ FVB_FLASH_SIGNATURE, // Signature=0D
+ NULL, // Handle ... NEED TO BE FILLED=0D
+ 0, // DeviceBaseAddress ... NEED TO BE FILLED=0D
+ 0, // RegionBaseAddress ... NEED TO BE FILLED=0D
+ 0, // Size ... NEED TO BE FILLED=0D
+ 0, // StartLba=0D
+ {=0D
+ 0, // MediaId ... NEED TO BE FILLED=0D
+ FALSE, // RemovableMedia=0D
+ TRUE, // MediaPresent=0D
+ FALSE, // LogicalPartition=0D
+ FALSE, // ReadOnly=0D
+ FALSE, // WriteCaching;=0D
+ 0, // BlockSize ... NEED TO BE FILLED=0D
+ 4, // IoAlign=0D
+ 0, // LastBlock ... NEED TO BE FILLED=0D
+ 0, // LowestAlignedLba=0D
+ 1, // LogicalBlocksPerPhysicalBlock=0D
+ }, //Media;=0D
+ {=0D
+ FvbGetAttributes, // GetAttributes=0D
+ FvbSetAttributes, // SetAttributes=0D
+ FvbGetPhysicalAddress, // GetPhysicalAddress=0D
+ FvbGetBlockSize, // GetBlockSize=0D
+ FvbRead, // Read=0D
+ FvbWrite, // Write=0D
+ FvbEraseBlocks, // EraseBlocks=0D
+ NULL, // ParentHandle=0D
+ }, // FvbProtoccol;=0D
+=0D
+ {=0D
+ {=0D
+ {=0D
+ HARDWARE_DEVICE_PATH,=0D
+ HW_VENDOR_DP,=0D
+ {=0D
+ (UINT8) sizeof (VENDOR_DEVICE_PATH),=0D
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)=0D
+ }=0D
+ },=0D
+ {=0D
+ 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }=0D
+ }, // GUID ... NEED TO BE FILLED=0D
+ },=0D
+ {=0D
+ END_DEVICE_PATH_TYPE,=0D
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,=0D
+ {=0D
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),=0D
+ 0=0D
+ }=0D
+ }=0D
+ }, // DevicePath=0D
+=0D
+ NULL, // SpiFlashProtocol ... NEED TO BE FILLED=0D
+ NULL, // ShadowBuffer ... NEED TO BE FILLED=0D
+ 0 // Fvb Size=0D
+};=0D
+=0D
+=0D
+/**=0D
+ Erases a single block of flash.=0D
+=0D
+ @param[in] FlashInstance The poiter of the fvb device sturct.=0D
+=0D
+ @param[in] BlockAddress Physical address of Lba to be erased.=0D
+=0D
+ @retval EFI_SUCCESS The erase single block request successfull=
y completed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashEraseSingleBlock (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN UINTN BlockAddress=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN Index;=0D
+ EFI_TPL OriginalTPL;=0D
+=0D
+ if ( ! EfiAtRuntime ()) {=0D
+ OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D
+ } else {=0D
+ OriginalTPL =3D TPL_HIGH_LEVEL;=0D
+ }=0D
+=0D
+ Index =3D 0;=0D
+=0D
+ do {=0D
+ Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAdd=
ress);=0D
+ Index++;=0D
+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status =3D=3D EFI_WRITE_PRO=
TECTED));=0D
+=0D
+ if (Index =3D=3D NOR_FLASH_ERASE_RETRY) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "EraseSingleBlock(BlockAddress=3D0x%08x: BlockLocked Error (try to e=
rase % d times)\n",=0D
+ BlockAddress,=0D
+ Index=0D
+ ));=0D
+ }=0D
+=0D
+ if ( ! EfiAtRuntime ()) {=0D
+ gBS->RestoreTPL (OriginalTPL);=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Readed the specified number of bytes from the form the block to output b=
uffer.=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=
=0D
+=0D
+ @param[in] Lba The starting logical block index to wri=
te to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin=
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[out] Buffer The pointer to a caller-allocated buffe=
r that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbFlashRead() is executed successfully=
.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashRead (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ OUT VOID *Buffer=0D
+ )=0D
+{=0D
+ UINTN Address;=0D
+=0D
+ Address =3D GET_DATA_OFFSET (=0D
+ FlashInstance->RegionBaseAddress,=0D
+ Lba,=0D
+ FlashInstance->Media.BlockSize=0D
+ ) + Offset;=0D
+=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+=0D
+ // The buffer must be valid=0D
+ if (Buffer =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ return FlashInstance->SpiFlashProtocol->Read (Address, Buffer, BufferSiz=
eInBytes);=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Write a full or portion of a block. It must not span block boundaries; t=
hat is,=0D
+ Offset + *NumBytes <=3D FlashInstance->Media.BlockSize.=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=
=0D
+=0D
+ @param[in] Lba The starting logical block index to wri=
te to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin=
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[out] Buffer The pointer to a caller-allocated buffe=
r that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbWriteBlock() is executed successfull=
y.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE The write spaned block boundaries.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbWriteBlock (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ IN UINT8 *Buffer=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN BlockSize;=0D
+ UINTN BlockAddress;=0D
+=0D
+ // Detect WriteDisabled state=0D
+ if (FlashInstance->Media.ReadOnly =3D=3D TRUE) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - Can not write:Device is in WriteDisabled sta=
te.\n"=0D
+ ));=0D
+ // It is in WriteDisabled state, return an error right away=0D
+ return EFI_ACCESS_DENIED;=0D
+ }=0D
+=0D
+ // Cache the block size to avoid de-referencing pointers all the time=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+=0D
+ // The write must not span block boundaries.=0D
+ // We need to check each variable individually because adding two large =
values together overflows.=0D
+ if ((Offset >=3D BlockSize) ||=0D
+ (BufferSizeInBytes > BlockSize) ||=0D
+ ((Offset + BufferSizeInBytes) > BlockSize))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset =3D0x %x + NumB=
ytes =3D0x%x) > BlockSize =3D0x%x\n",=0D
+ Offset,=0D
+ BufferSizeInBytes,=0D
+ BlockSize=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to write=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: NumBytes =3D=3D 0\n"=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // Check we did get some memory. Buffer is BlockSize.=0D
+ if (FlashInstance->ShadowBuffer =3D=3D NULL) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - ShadowBuffer is NULL!\n"=0D
+ ));=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ //=0D
+ // Write the word to NOR.=0D
+ //=0D
+ BlockAddress =3D GET_DATA_OFFSET (=0D
+ FlashInstance->RegionBaseAddress,=0D
+ Lba,=0D
+ FlashInstance->Media.BlockSize=0D
+ );=0D
+=0D
+ // Read NOR Flash data into shadow buffer=0D
+ Status =3D FlashInstance->SpiFlashProtocol->Read (=0D
+ BlockAddress,=0D
+ FlashInstance->ShadowBuffer,=0D
+ BlockSize=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ // Put the data at the appropriate location inside the buffer area=0D
+ CopyMem (=0D
+ (VOID *) ((UINTN)FlashInstance->ShadowBuffer + Offset),=0D
+ Buffer,=0D
+ BufferSizeInBytes=0D
+ );=0D
+=0D
+ Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAddre=
ss);=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ // Write the modified buffer back to the NorFlash=0D
+ Status =3D FlashInstance->SpiFlashProtocol->Write (BlockAddress,=0D
+ FlashInstance->ShadowBuffer,=0D
+ BlockSize=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Writes the specified number of bytes from the input buffer to the block.=
=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=0D
+=0D
+ @param[in] Lba The starting logical block index to writ=
e to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin =
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[in] Buffer The pointer to a caller-allocated buffer=
that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbFlashWrite() is executed successfully=
.=0D
+=0D
+ @retval EFI_WRITE_PROTECTED Flash state is in the WriteDisabled stat=
e.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The pointer of Buffer is NULL.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashWrite (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ IN VOID *Buffer=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT32 BlockSize;=0D
+ UINT32 BlockOffset;=0D
+ UINTN RemainingBytes;=0D
+ UINTN WriteSize;=0D
+=0D
+ if (FlashInstance->Media.ReadOnly =3D=3D TRUE) {=0D
+ return EFI_WRITE_PROTECTED;=0D
+ }=0D
+=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+=0D
+ if (Buffer =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+ BlockOffset =3D Offset;=0D
+ RemainingBytes =3D BufferSizeInBytes;=0D
+=0D
+ // The write must not span block boundaries.=0D
+ // We need to check each variable individually because adding=0D
+ // two large values together overflows.=0D
+ if (Offset >=3D BlockSize) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: Offset =3D0x%x > BlockS=
ize =3D0x%x\n",=0D
+ Offset,=0D
+ BlockSize=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to read=0D
+ // Write either all the remaining bytes, or the number of bytes that bri=
ng=0D
+ // us up to a block boundary, whichever is less.=0D
+ // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next=
=0D
+ // block boundary (even if it is already on one).=0D
+ WriteSize =3D MIN (RemainingBytes, BlockSize - BlockOffset);=0D
+=0D
+ do {=0D
+ Status =3D FvbWriteBlock (=0D
+ FlashInstance,=0D
+ Lba,=0D
+ BlockOffset,=0D
+ WriteSize,=0D
+ Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Now continue writing either all the remaining bytes or single block=
s.=0D
+ RemainingBytes -=3D WriteSize;=0D
+ Buffer =3D (UINT8 *) Buffer + WriteSize;=0D
+ Lba++;=0D
+ BlockOffset =3D 0;=0D
+ WriteSize =3D MIN (RemainingBytes, BlockSize);=0D
+ } while (RemainingBytes);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Initialises the FV Header and Variable Store Header=0D
+ to support variable operations.=0D
+=0D
+ @param[in] Ptr Location to initialise the headers.=0D
+=0D
+ @retval EFI_SUCCESS FvbInitFvAndVariableStoreHeaders()=0D
+ is executed successfully.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbInitFvAndVariableStoreHeaders (=0D
+ IN FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ VOID * Headers;=0D
+ UINTN HeadersLength;=0D
+ UINT32 TempAttributes;=0D
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;=0D
+ VARIABLE_STORE_HEADER *VariableStoreHeader;=0D
+=0D
+ HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) +=0D
+ sizeof (EFI_FV_BLOCK_MAP_ENTRY) +=0D
+ sizeof (VARIABLE_STORE_HEADER);=0D
+=0D
+ Headers =3D AllocateZeroPool (HeadersLength);=0D
+=0D
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area=
=0D
+ // AND the FTW working area AND the FTW Spare contiguous.=0D
+ ASSERT (mFlashNvStorageVariableBase + mFlashNvStorageVariableSize =3D=3D=
mFlashNvStorageFtwWorkingBase);=0D
+ ASSERT (mFlashNvStorageFtwWorkingBase + mFlashNvStorageFtwWorkingSize =
=3D=3D mFlashNvStorageFtwSpareBase);=0D
+=0D
+ // Check if the size of the area is at least one block size=0D
+ ASSERT ((mFlashNvStorageVariableSize > 0) && (mFlashNvStorageVariableSiz=
e / FlashInstance->Media.BlockSize > 0));=0D
+ ASSERT ((mFlashNvStorageFtwWorkingSize > 0) && (mFlashNvStorageFtwWorkin=
gSize / FlashInstance->Media.BlockSize > 0));=0D
+ ASSERT ((mFlashNvStorageFtwSpareSize > 0) && (mFlashNvStorageFtwSpareSiz=
e / FlashInstance->Media.BlockSize > 0));=0D
+=0D
+ // Ensure the Variable area Base Addresses are aligned on a block size b=
oundaries=0D
+ ASSERT (mFlashNvStorageVariableBase % FlashInstance->Media.BlockSize =3D=
=3D 0);=0D
+ ASSERT (mFlashNvStorageFtwWorkingBase % FlashInstance->Media.BlockSize =
=3D=3D 0);=0D
+ ASSERT (mFlashNvStorageFtwSpareBase % FlashInstance->Media.BlockSize =3D=
=3D 0);=0D
+=0D
+ //=0D
+ // EFI_FIRMWARE_VOLUME_HEADER=0D
+ //=0D
+ FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Headers;=0D
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid=
);=0D
+ FirmwareVolumeHeader->FvLength =3D FlashInstance->FvbSize;=0D
+=0D
+ TempAttributes =3D (=0D
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled=
=0D
+ EFI_FVB2_READ_STATUS | // Reads are currently =
enabled=0D
+ EFI_FVB2_STICKY_WRITE | // A block erase is req=
uired to=0D
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped=
=0D
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bi=
ts take this value=0D
+ EFI_FVB2_WRITE_STATUS | // Writes are currently=
enabled=0D
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enable=
d=0D
+ );=0D
+=0D
+ FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE;=0D
+ FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2) TempAttribut=
es;=0D
+=0D
+ FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE=
R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);=0D
+ FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION;=0D
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D FlashInstance->Media.Las=
tBlock + 1;=0D
+ FirmwareVolumeHeader->BlockMap[0].Length =3D FlashInstance->Media.Blo=
ckSize;=0D
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0;=0D
+ FirmwareVolumeHeader->BlockMap[1].Length =3D 0;=0D
+ FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 (=0D
+ (UINT16 *)FirmwareVolumeHeader,=0D
+ FirmwareVolumeHeader->HeaderLength=0D
+ );=0D
+=0D
+ //=0D
+ // VARIABLE_STORE_HEADER=0D
+ //=0D
+ VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)Headers + Firm=
wareVolumeHeader->HeaderLength);=0D
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui=
d);=0D
+ VariableStoreHeader->Size =3D mFlashNvStorageVariableSize - FirmwareVo=
lumeHeader->HeaderLength;=0D
+ VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED;=0D
+ VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY;=0D
+=0D
+ // Install the combined super-header in the NorFlash=0D
+ Status =3D FvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, =
Headers);=0D
+=0D
+ FreePool (Headers);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Check the integrity of firmware volume header.=0D
+=0D
+ @param[in] FwVolHeader A pointer to a firmware volume header=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume is consistent=0D
+=0D
+ @retval EFI_NOT_FOUND The firmware volume has been corrupted.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbValidateFvHeader (=0D
+ IN FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ UINT16 Checksum;=0D
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;=0D
+ VARIABLE_STORE_HEADER *VariableStoreHeader;=0D
+ UINTN VariableStoreLength;=0D
+ UINTN FvLength;=0D
+=0D
+ FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)GET_DATA_OFFSET (FlashInst=
ance->RegionBaseAddress,=0D
+ FlashInstance->StartLba,=0D
+ FlashInstance->Media.Block=
Size=0D
+ );=0D
+ FvLength =3D FlashInstance->FvbSize;=0D
+=0D
+=0D
+ if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) ||=0D
+ (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) ||=0D
+ (FwVolHeader->FvLength !=3D FvLength))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: No Firmware Volume header present\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ // Check the Firmware Volume Guid=0D
+ if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)=
=3D=3D FALSE ) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: Firmware Volume Guid non-compatible\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ // Verify the header checksum=0D
+ Checksum =3D CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderL=
ength);=0D
+ if (Checksum !=3D 0) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n",=0D
+ Checksum));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)FwVolHeader + =
FwVolHeader->HeaderLength);=0D
+=0D
+ // Check the Variable Store Guid=0D
+ if ( ! CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) =
&&=0D
+ ! CompareGuid (&VariableStoreHeader->Signature,=0D
+ &gEfiAuthenticatedVariableGuid))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "%a: Variable Store Guid non-compatible\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ VariableStoreLength =3D mFlashNvStorageVariableSize - FwVolHeader->Heade=
rLength;=0D
+ if (VariableStoreHeader->Size !=3D VariableStoreLength) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: Variable Store Length does not match\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetAttributes() function retrieves the attributes and=0D
+ current settings of the block.=0D
+=0D
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL in=
stance.=0D
+=0D
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribu=
tes and=0D
+ current settings are returned.=0D
+ Type EFI_FVB_ATTRIBUTES_2 is defined in=0D
+ EFI_FIRMWARE_VOLUME_HEADER.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume attributes were returned.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes=0D
+ )=0D
+{=0D
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;=0D
+ CONST FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2) (=0D
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled=0D
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled=0D
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bit=
s into EFI_FVB2_ERASE_POLARITY=0D
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped=0D
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this valu=
e (i.e. '1')=0D
+ );=0D
+=0D
+ // Check if it is write protected=0D
+ if (FlashInstance->Media.ReadOnly !=3D TRUE) {=0D
+ FlashFvbAttributes =3D FlashFvbAttributes |=0D
+ EFI_FVB2_WRITE_STATUS | // Writes are curren=
tly enabled=0D
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be ena=
bled=0D
+ }=0D
+=0D
+ *Attributes =3D FlashFvbAttributes;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbSetAttributes() function sets configurable firmware volume attrib=
utes=0D
+ and returns the new settings of the firmware volume.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst=
ance.=0D
+=0D
+ @param Attributes On input, Attributes is a pointer to=0D
+ EFI_FVB_ATTRIBUTES_2 that contains the d=
esired=0D
+ firmware volume settings.=0D
+ On successful return, it contains the ne=
w=0D
+ settings of the firmware volume.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume attributes were retu=
rned.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict=
with=0D
+ the capabilities as declared in the firm=
ware=0D
+ volume header.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbSetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes=0D
+ )=0D
+{=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetPhysicalAddress() function retrieves the base address of=0D
+ a memory-mapped firmware volume. This function should be called=0D
+ only for memory-mapped firmware volumes.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.=
=0D
+=0D
+ @param Address Pointer to a caller-allocated=0D
+ EFI_PHYSICAL_ADDRESS that, on successful=0D
+ return from GetPhysicalAddress(), contains the=
=0D
+ base address of the firmware volume.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume base address was returned.=
=0D
+=0D
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetPhysicalAddress (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ OUT EFI_PHYSICAL_ADDRESS *Address=0D
+ )=0D
+{=0D
+ ASSERT (Address !=3D NULL);=0D
+=0D
+ *Address =3D mFlashNvStorageVariableBase;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetBlockSize() function retrieves the size of the requested=0D
+ block. It also returns the number of additional blocks with=0D
+ the identical size. The FvbGetBlockSize() function is used to=0D
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).=0D
+=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst=
ance.=0D
+=0D
+ @param Lba Indicates the block whose size to return=
.=0D
+=0D
+ @param BlockSize Pointer to a caller-allocated UINTN in w=
hich=0D
+ the size of the block is returned.=0D
+=0D
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in=0D
+ which the number of consecutive blocks,=
=0D
+ starting with Lba, is returned. All=0D
+ blocks in this range have a size of=0D
+ BlockSize.=0D
+=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume base address was ret=
urned.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetBlockSize (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ OUT UINTN *BlockSize,=0D
+ OUT UINTN *NumberOfBlocks=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ if (Lba > FlashInstance->Media.LastBlock) {=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ } else {=0D
+ // This is easy because in this platform each NorFlash device has equa=
l sized blocks.=0D
+ *BlockSize =3D (UINTN) FlashInstance->Media.BlockSize;=0D
+ *NumberOfBlocks =3D (UINTN) (FlashInstance->Media.LastBlock - Lba + 1)=
;=0D
+ Status =3D EFI_SUCCESS;=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Reads the specified number of bytes into a buffer from the specified blo=
ck.=0D
+=0D
+ The FvbRead() function reads the requested number of bytes from the=0D
+ requested block and stores them in the provided buffer.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance=
.=0D
+=0D
+ @param Lba The starting logical block index from which =
to read.=0D
+=0D
+ @param Offset Offset into the block at which to begin read=
ing.=0D
+=0D
+ @param NumBytes Pointer to a UINTN.=0D
+ At entry, *NumBytes contains the total size =
of the=0D
+ buffer.=0D
+ At exit, *NumBytes contains the total number=
of=0D
+ bytes read.=0D
+=0D
+ @param Buffer Pointer to a caller-allocated buffer that wi=
ll be=0D
+ used to hold the data that is read.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume was read successfully, a=
nd=0D
+ contents are in Buffer.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.=0D
+ On output, NumBytes contains the total numbe=
r of=0D
+ bytes returned in Buffer.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled s=
tate.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctl=
y and=0D
+ could not be read.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbRead (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN *NumBytes,=0D
+ IN OUT UINT8 *Buffer=0D
+ )=0D
+{=0D
+ UINTN BlockSize;=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+ EFI_STATUS Status;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ // Cache the block size to avoid de-referencing pointers all the time=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+=0D
+ // The read must not span block boundaries.=0D
+ // We need to check each variable individually because adding two large =
values together overflows.=0D
+ if ((Offset >=3D BlockSize) ||=0D
+ (*NumBytes > BlockSize) ||=0D
+ ((Offset + *NumBytes) > BlockSize)) {=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to read=0D
+ if (*NumBytes =3D=3D 0) {=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ Status =3D FvbFlashRead (=0D
+ FlashInstance,=0D
+ FlashInstance->StartLba + Lba,=0D
+ Offset,=0D
+ *NumBytes,=0D
+ Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Writes the specified number of bytes from the input buffer to the block.=
=0D
+=0D
+ The FvbWrite() function writes the specified number of bytes from=0D
+ the provided buffer to the specified block and offset.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance=
.=0D
+=0D
+ @param Lba The starting logical block index to write to=
.=0D
+=0D
+ @param Offset Offset into the block at which to begin writ=
ing.=0D
+=0D
+ @param NumBytes The pointer to a UINTN.=0D
+ At entry, *NumBytes contains the total size =
of the=0D
+ buffer.=0D
+ At exit, *NumBytes contains the total number=
of=0D
+ bytes actually written.=0D
+=0D
+ @param Buffer The pointer to a caller-allocated buffer tha=
t=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume was written successfully=
.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA bounda=
ry.=0D
+ On output, NumBytes contains the total numbe=
r of=0D
+ bytes actually written.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled =
state.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could=
not be=0D
+ written.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbWrite (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN *NumBytes,=0D
+ IN UINT8 *Buffer=0D
+ )=0D
+{=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ return FvbFlashWrite (FlashInstance,=0D
+ FlashInstance->StartLba + Lba,=0D
+ Offset,=0D
+ *NumBytes,=0D
+ Buffer=0D
+ );=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Erases and initialises a firmware volume block.=0D
+=0D
+ The FvbEraseBlocks() function erases one or more blocks as denoted=0D
+ by the variable argument list.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL=0D
+ instance.=0D
+=0D
+ @param ... The variable argument list is a list of =
tuples.=0D
+ Each tuple describes a range of LBAs to =
erase=0D
+ and consists of the following:=0D
+ An EFI_LBA that indicates the starting L=
BA=0D
+ A UINTN that indicates the number of blo=
cks=0D
+ to erase.=0D
+=0D
+ The list is terminated with an=0D
+ EFI_LBA_LIST_TERMINATOR.=0D
+=0D
+ @retval EFI_SUCCESS The erase request successfully completed=
.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisab=
led=0D
+ state.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is not functioning corr=
ectly=0D
+ and could not be written.=0D
+ The firmware device may have been partia=
lly=0D
+ erased.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the va=
riable=0D
+ argument list do not exist in the firmwa=
re=0D
+ volume.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEraseBlocks (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ ...=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ VA_LIST Args;=0D
+ UINTN BlockAddress; // Physical address of Lba to erase=0D
+ EFI_LBA StartingLba; // Lba from which we start erasing=0D
+ UINTN NumOfLba; // Number of Lba blocks to erase=0D
+ FT_FVB_DEVICE *Instance;=0D
+=0D
+ Instance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ // Detect WriteDisabled state=0D
+ if (Instance->Media.ReadOnly =3D=3D TRUE) {=0D
+ // Firmware volume is in WriteDisabled state=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"=0D
+ ));=0D
+ return EFI_ACCESS_DENIED;=0D
+ }=0D
+=0D
+ // Before erasing, check the entire list of parameters to ensure all spe=
cified blocks are valid=0D
+=0D
+ VA_START (Args, This);=0D
+ do {=0D
+ // Get the Lba from which we start erasing=0D
+ StartingLba =3D VA_ARG (Args, EFI_LBA);=0D
+=0D
+ // Have we reached the end of the list?=0D
+ if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) {=0D
+ //Exit the while loop=0D
+ break;=0D
+ }=0D
+=0D
+ // How many Lba blocks are we requested to erase?=0D
+ NumOfLba =3D VA_ARG (Args, UINT32);=0D
+=0D
+ // All blocks must be within range=0D
+ if ((NumOfLba =3D=3D 0) || ((Instance->StartLba + StartingLba + NumOfL=
ba - 1) > Instance->Media.LastBlock)) {=0D
+ VA_END (Args);=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"=0D
+ ));=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ goto EXIT;=0D
+ }=0D
+ } while (TRUE);=0D
+=0D
+ VA_END (Args);=0D
+=0D
+ //=0D
+ // To get here, all must be ok, so start erasing=0D
+ //=0D
+ VA_START (Args, This);=0D
+ do {=0D
+ // Get the Lba from which we start erasing=0D
+ StartingLba =3D VA_ARG (Args, EFI_LBA);=0D
+=0D
+ // Have we reached the end of the list?=0D
+ if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) {=0D
+ // Exit the while loop=0D
+ break;=0D
+ }=0D
+=0D
+ // How many Lba blocks are we requested to erase?=0D
+ NumOfLba =3D VA_ARG (Args, UINT32);=0D
+=0D
+ // Go through each one and erase it=0D
+ while (NumOfLba > 0) {=0D
+ // Get the physical address of Lba to erase=0D
+ BlockAddress =3D GET_DATA_OFFSET (=0D
+ Instance->RegionBaseAddress,=0D
+ Instance->StartLba + StartingLba,=0D
+ Instance->Media.BlockSize=0D
+ );=0D
+=0D
+ // Erase it=0D
+ Status =3D FvbFlashEraseSingleBlock (Instance, BlockAddress);=0D
+ if (EFI_ERROR (Status)) {=0D
+ VA_END (Args);=0D
+ Status =3D EFI_DEVICE_ERROR;=0D
+ goto EXIT;=0D
+ }=0D
+=0D
+ // Move to the next Lba=0D
+ StartingLba++;=0D
+ NumOfLba--;=0D
+ }=0D
+ } while (TRUE);=0D
+=0D
+ VA_END (Args);=0D
+=0D
+EXIT:=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function inited the NorFlash instance.=0D
+=0D
+ @param[in][out] FlashInstance The pointer of FT_FVB_DEVICE instance.=0D
+=0D
+ @retval EFI_SUCCESS PhytNorFlashFvbInitialize() is executed =
successfully.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+PhytNorFlashFvbInitialize (=0D
+ IN OUT FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT32 FvbNumLba;=0D
+ EFI_BOOT_MODE BootMode;=0D
+ UINTN TotalFvbSize;=0D
+=0D
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME=0D
+ Status =3D gDS->AddMemorySpace (=0D
+ EfiGcdMemoryTypeMemoryMappedIo,=0D
+ mFlashNvStorageVariableBase,=0D
+ FlashInstance->FvbSize,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ Status =3D gDS->SetMemorySpaceAttributes (=0D
+ mFlashNvStorageVariableBase,=0D
+ FlashInstance->FvbSize,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ TotalFvbSize =3D FlashInstance->FvbSize;=0D
+=0D
+ // Set the index of the first LBA for the FVB=0D
+ FlashInstance->StartLba =3D (mFlashNvStorageVariableBase - FlashInstance=
->RegionBaseAddress) / FlashInstance->Media.BlockSize;=0D
+=0D
+ BootMode =3D GetBootModeHob ();=0D
+ if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) {=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ } else {=0D
+ // Determine if there is a valid header at the beginning of the NorFla=
sh=0D
+ Status =3D FvbValidateFvHeader (FlashInstance);=0D
+ }=0D
+=0D
+ // Install the Default FVB header if required=0D
+ if (EFI_ERROR (Status)) {=0D
+ // There is no valid header, so time to install one.=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "NorFlashFvbInitialize: ERROR - The FVB Header is invalid. Installin=
g a correct one for this volume.\n"=0D
+ ));=0D
+=0D
+ // Erase all the NorFlash that is reserved for variable storage=0D
+ FvbNumLba =3D TotalFvbSize / FlashInstance->Media.BlockSize;=0D
+=0D
+ Status =3D FvbEraseBlocks (=0D
+ &FlashInstance->FvbProtocol,=0D
+ (EFI_LBA)0,=0D
+ FvbNumLba,=0D
+ EFI_LBA_LIST_TERMINATOR=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Install all appropriate headers=0D
+ Status =3D FvbInitFvAndVariableStoreHeaders (FlashInstance);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The CreateInstance() function Create Fvb Instance.=0D
+=0D
+ @retval EFI_SUCCESS Create Instance successfully.=0D
+=0D
+ @retval other Create Instance failed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+CreateInstance (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevice;=0D
+=0D
+ // Locate flash protocols=0D
+ Status =3D gBS->LocateProtocol (&gSpiNorFlashProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&FvbDevice->SpiFlashProtocol);=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "Cannot locate NorFlash protocol.\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ NorFlashDevice =3D AllocateRuntimePool (sizeof (NOR_FLASH_DEVICE_DESCRIP=
TION));=0D
+ if (NorFlashDevice =3D=3D NULL) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "Cannot Allocate NorFlashDevice Pool.\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D FvbDevice->SpiFlashProtocol->GetDevices (NorFlashDevice);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D FvbDevice->SpiFlashProtocol->Initialization ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ FvbDevice->DeviceBaseAddress =3D NorFlashDevice->DeviceBaseAddress;=0D
+ FvbDevice->RegionBaseAddress =3D NorFlashDevice->RegionBaseAddress;=0D
+ FvbDevice->Size =3D NorFlashDevice->Size;=0D
+=0D
+ FvbDevice->Media.MediaId =3D 0;=0D
+ FvbDevice->Media.BlockSize =3D NorFlashDevice->BlockSize;=0D
+ FvbDevice->Media.LastBlock =3D (FvbDevice->Size / FvbDevice->Media.Block=
Size) - 1;=0D
+ FvbDevice->FvbSize =3D mFlashNvStorageVariableSize +=0D
+ mFlashNvStorageFtwWorkingSize +=0D
+ mFlashNvStorageFtwSpareSize;=0D
+=0D
+ CopyGuid (&FvbDevice->DevicePath.Vendor.Guid, &NorFlashDevice->Guid);=0D
+=0D
+ FvbDevice->ShadowBuffer =3D AllocateRuntimePool (FvbDevice->Media.BlockS=
ize);=0D
+ if (FvbDevice->ShadowBuffer =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &FvbDevice->Handle,=0D
+ &gEfiDevicePathProtocolGuid,=0D
+ &FvbDevice->DevicePath,=0D
+ &gEfiFirmwareVolumeBlockProtocolGuid,=0D
+ &FvbDevice->FvbProtocol,=0D
+ NULL=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ FreePool (FvbDevice);=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D PhytNorFlashFvbInitialize (FvbDevice);=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "PhytNorFlashFvbInitialize: Fail to init NorFlash devices\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ FreePool (NorFlashDevice);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Fixup internal data so that EFI can be call in virtual mode.=0D
+ Call the passed in Child Notify event and convert any pointers=0D
+ in lib to virtual mode.=0D
+=0D
+ @param[in] Event The Event that is being processed.=0D
+=0D
+ @param[in] Context Event Context.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+STATIC=0D
+VOID=0D
+EFIAPI=0D
+FvbVirtualNotifyEvent (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ // Convert SpiFlashProtocol=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Erase);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Write);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Read);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->GetDevice=
s);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Initializ=
ation);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->EraseSing=
leBlock);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol);=0D
+=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwWorkingBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwSpareBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice);=0D
+=0D
+ return;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function is the entrypoint of the fvb driver.=0D
+=0D
+ @param[in] ImageHandle The firmware allocated handle for the EFI imag=
e.=0D
+=0D
+ @param[in] SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ FvbDevice =3D AllocateRuntimeCopyPool (=0D
+ sizeof (FvbFlashInstanceTemplate),=0D
+ &FvbFlashInstanceTemplate=0D
+ );=0D
+ if (FvbDevice =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariab=
leBase64);=0D
+ mFlashNvStorageFtwWorkingBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwWor=
kingBase64);=0D
+ mFlashNvStorageFtwSpareBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwSpa=
reBase64);=0D
+ mFlashNvStorageVariableSize =3D FixedPcdGet32 (PcdFlashNvStorageVariab=
leSize);=0D
+ mFlashNvStorageFtwWorkingSize =3D FixedPcdGet32 (PcdFlashNvStorageFtwWor=
kingSize);=0D
+ mFlashNvStorageFtwSpareSize =3D FixedPcdGet32 (PcdFlashNvStorageFtwSpa=
reSize);=0D
+=0D
+ Status =3D CreateInstance ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "CreateInstance: Fail to create instance for NorFlash\n"=0D
+ ));=0D
+ }=0D
+=0D
+//=0D
+// Register for the virtual address change event=0D
+//=0D
+ Status =3D gBS->CreateEventEx (=0D
+ EVT_NOTIFY_SIGNAL,=0D
+ TPL_NOTIFY,=0D
+ FvbVirtualNotifyEvent,=0D
+ NULL,=0D
+ &gEfiEventVirtualAddressChangeGuid,=0D
+ &FvbVirtualAddrChangeEvent=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.25.1

The Pci host bridge library is mainly
to get Pci bridge information.

v3:
Optimize the codes of PciHostBridgeLib.c to conform to specifications.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 9 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 6 +
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf =
| 47 +++++
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c =
| 181 ++++++++++++++++++++
4 files changed, 243 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 093b2cd9db..3a9bc2289c 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -37,6 +37,7 @@
[LibraryClasses.common.DXE_DRIVER]=0D
# Pci dependencies=0D
PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme=
ntLib.inf=0D
+ PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/Pc=
iHostBridgeLib.inf=0D
=0D
##########################################################################=
######=0D
#=0D
@@ -263,6 +264,14 @@
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D
=0D
+ #=0D
+ # PCI Support=0D
+ #=0D
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic=
eDxe.inf=0D
+=0D
#=0D
# The following 2 module perform the same work except one operate variab=
le.=0D
# Only one of both should be put into fdf.=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 3106a43fb7..a443d0f3a4 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -135,6 +135,12 @@ READ_LOCK_STATUS =3D TRUE
INF FatPkg/EnhancedFatDxe/Fat.inf=0D
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i=
nf=0D
=0D
+ #=0D
+ # PCI Support=0D
+ #=0D
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D
+=0D
#=0D
# SATA Controller=0D
#=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr=
idgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostB=
ridgeLib.inf
new file mode 100644
index 0000000000..0e6f0797b0
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib=
.inf
@@ -0,0 +1,47 @@
+#/** @file=0D
+# PCI Host Bridge Library instance for Phytium SOC.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D PciHostBridgeLib=0D
+ FILE_GUID =3D f965de0e-40fe-11eb-8290-3f9d1f895a80=
=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build=0D
+# tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D ARM AARCH64=0D
+#=0D
+=0D
+[Sources]=0D
+ PciHostBridgeLib.c=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+=0D
+[Guids]=0D
+=0D
+[FixedPcd]=0D
+ gArmTokenSpaceGuid.PcdPciBusMin=0D
+ gArmTokenSpaceGuid.PcdPciBusMax=0D
+ gArmTokenSpaceGuid.PcdPciIoBase=0D
+ gArmTokenSpaceGuid.PcdPciIoSize=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Size=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Size=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr=
idgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBri=
dgeLib.c
new file mode 100644
index 0000000000..8ed3516749
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib=
.c
@@ -0,0 +1,181 @@
+/** @file=0D
+ PCI host bridge library instance for Phytium SOC.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DevicePathLib.h>=0D
+#include <Library/PciHostBridgeLib.h>=0D
+#include <Protocol/PciHostBridgeResourceAllocation.h>=0D
+#include <Protocol/PciRootBridgeIo.h>=0D
+=0D
+#pragma pack(1)=0D
+=0D
+typedef struct {=0D
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D
+=0D
+#pragma pack ()=0D
+=0D
+#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \=0D
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \=0D
+ { END_DEVICE_PATH_LENGTH, 0 } \=0D
+ }=0D
+=0D
+#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \=0D
+ { (UINT8) (sizeof (ACPI_HID_DEVICE_PA=
TH)), \=0D
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PA=
TH) >> 8)} \=0D
+ }, \=0D
+ EISA_PNP_ID (0x0A03), UID \=0D
+ }=0D
+=0D
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]=
=3D {=0D
+ {=0D
+ ACPI_DEVICE_PATH_DEF (0),=0D
+ END_DEVICE_PATH_DEF=0D
+ },=0D
+};=0D
+=0D
+GLOBAL_REMOVE_IF_UNREFERENCED=0D
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D {=0D
+ L"Mem", L"I/O", L"Bus"=0D
+};=0D
+=0D
+STATIC PCI_ROOT_BRIDGE mRootBridge =3D {=0D
+ 0, // Segment=0D
+ 0, // Supports=0D
+ 0, // Attributes=0D
+ TRUE, // DmaAbove4G=0D
+ FALSE, // NoExtendedConfigSpace=
=0D
+ FALSE, // ResourceAssigned=0D
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes=
=0D
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,=0D
+ {=0D
+ // Bus=0D
+ FixedPcdGet32 (PcdPciBusMin),=0D
+ FixedPcdGet32 (PcdPciBusMax)=0D
+ }, {=0D
+ // Io=0D
+ FixedPcdGet64 (PcdPciIoBase),=0D
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1=0D
+ }, {=0D
+ // Mem=0D
+ FixedPcdGet32 (PcdPciMmio32Base),=0D
+ FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) -=
1)=0D
+ //0x7FFFFFFF=0D
+ }, {=0D
+ // MemAbove4G=0D
+ FixedPcdGet64 (PcdPciMmio64Base),=0D
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - =
1=0D
+ }, {=0D
+ // PMem=0D
+ MAX_UINT64,=0D
+ 0=0D
+ }, {=0D
+ // PMemAbove4G=0D
+ MAX_UINT64,=0D
+ 0=0D
+ },=0D
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath=0D
+};=0D
+=0D
+/**=0D
+ Return all the root bridge instances in an array.=0D
+=0D
+ @param[out] Count Return the count of root bridge instances.=0D
+=0D
+ @return All the root bridge instances in an array.=0D
+ The array should be passed into PciHostBridgeFreeRootBridges()=0D
+ when it's not used.=0D
+=0D
+**/=0D
+PCI_ROOT_BRIDGE *=0D
+EFIAPI=0D
+PciHostBridgeGetRootBridges (=0D
+ OUT UINTN *Count=0D
+ )=0D
+{=0D
+ *Count =3D 1;=0D
+ return &mRootBridge;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Free the root bridge instances array returned from PciHostBridgeGetRootB=
ridges().=0D
+=0D
+ @param[in] Bridges The root bridge instances array.=0D
+ @param[in] Count The count of the array.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+PciHostBridgeFreeRootBridges (=0D
+ IN PCI_ROOT_BRIDGE *Bridges,=0D
+ IN UINTN Count=0D
+ )=0D
+{=0D
+=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Inform the platform that the resource conflict happens.=0D
+=0D
+ @param[in] HostBridgeHandle Handle of the Host Bridge.=0D
+ @param[in] Configuration Pointer to PCI I/O and PCI memory resource=0D
+ descriptors. The Configuration contains the reso=
urces=0D
+ for all the root bridges. The resource for each =
root=0D
+ bridge is terminated with END descriptor and an=
=0D
+ additional END is appended indicating the end of=
the=0D
+ entire resources. The resource descriptor field=
=0D
+ values follow the description in=0D
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL=
=0D
+ SubmitResources().=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+PciHostBridgeResourceConflict (=0D
+ IN EFI_HANDLE HostBridgeHandle,=0D
+ IN VOID *Configuration=0D
+ )=0D
+{=0D
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;=0D
+ BOOLEAN IsPrefetchable;=0D
+=0D
+ Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;=0D
+ while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) {=0D
+ for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript=
or++) {=0D
+ ASSERT (Descriptor->ResType <=0D
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));=0D
+ DEBUG ((DEBUG_INFO, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n",=0D
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType=
],=0D
+ Descriptor->AddrLen,=0D
+ Descriptor->AddrRangeMax=0D
+ ));=0D
+ if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D
+=0D
+ IsPrefetchable =3D (Descriptor->SpecificFlag &=0D
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) !=
=3D 0;=0D
+=0D
+ DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag =3D %ld / %02x%=
s\n",=0D
+ Descriptor->AddrSpaceGranularity,=0D
+ Descriptor->SpecificFlag,=0D
+ (IsPrefetchable) ? L" (Prefetchable)" : L""=0D
+ ));=0D
+ }=0D
+ }=0D
+ //=0D
+ // Skip the end descriptor for root bridge=0D
+ //=0D
+ ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR);=0D
+ Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (=0D
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1=0D
+ );=0D
+ }=0D
+}=0D
--=20
2.25.1

The PlatformLib supported the system library for FT2000/4 chip.
Platform/Phytium: Added the dsc and fdf files of DurianPkg.

v3:
DurianPkg.dsc:Added OrderedCollectionLib to upstream changes in
edk2, and some parameters omitted in V2 version.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec =
| 41 +++
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc =
| 345 ++++++++++++++++++++
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 298 +++++++++++++++++
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 210 ++++++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf =
| 55 ++++
Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h =
| 112 +++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c =
| 137 ++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c =
| 156 +++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHel=
per.S | 76 +++++
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc =
| 119 +++++++
10 files changed, 1549 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico=
n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
new file mode 100644
index 0000000000..48f430c88d
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -0,0 +1,41 @@
+## @file=0D
+# This package provides common Phytium silicon modules.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.=0D
+#=0D
+# SPDX-License-Identifier:BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ DEC_SPECIFICATION =3D 0x0001001b=0D
+ PACKAGE_NAME =3D PhytiumCommnonPkg=0D
+ PACKAGE_GUID =3D b34af0b4-3e7c-11eb-a9d0-0738806d2dec=
=0D
+ PACKAGE_VERSION =3D 0.1=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Include Section - list of Include Paths that are provided by this packag=
e.=0D
+# Comments are used for Keywords and Module Types.=0D
+#=0D
+# Supported Module Types:=0D
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D=
RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION=0D
+#=0D
+##########################################################################=
######=0D
+[Includes]=0D
+ Include # Root include for the package=0D
+=0D
+[Guids.common]=0D
+ gPhytiumPlatformTokenSpaceGuid =3D { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4,=
0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } }=0D
+=0D
+[PcdsFixedAtBuild.common]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001=0D
+=0D
+ #=0D
+ # PCI configuration address space=0D
+ #=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003=0D
+=0D
+[Protocols]=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc b/Si=
licon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
new file mode 100644
index 0000000000..121fe0e7c5
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
@@ -0,0 +1,345 @@
+## @file=0D
+# This package provides common open source Phytium silicon modules.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D
+#=0D
+# SPDX-License-Identifier:BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+=0D
+[LibraryClasses.common]=0D
+ #=0D
+ # ARM Architectural Libraries=0D
+ #=0D
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.=
inf=0D
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf=0D
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf=0D
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo=
rmStackLib.inf=0D
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf=0D
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar=
mGenericTimerPhyCounterLib.inf=0D
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf=0D
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf=0D
+=0D
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf=0D
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib=
Null.inf=0D
+=0D
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf=0D
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf=0D
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf=0D
+ BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i=
nf=0D
+=0D
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf=
=0D
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.in=
f=0D
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte=
nanceLib.inf=0D
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize=
dDisplayLib.inf=0D
+ !if $(TARGET) =3D=3D RELEASE=0D
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D
+ !else=0D
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.=
inf=0D
+ !endif=0D
+=0D
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL=
ib.inf=0D
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD=
ebugPrintErrorLevelLib.inf=0D
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def=
aultExceptionHandlerLib.inf=0D
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i=
nf=0D
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent=
TimerLibNull.inf=0D
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D
+=0D
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf=0D
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf=
=0D
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf=0D
+=0D
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf=0D
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing=
Lib.inf=0D
+=0D
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf=0D
+=0D
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf=0D
+=0D
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC=
offGetEntryPointLib.inf=0D
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC=
offExtraActionLibNull.inf=0D
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf=0D
+ PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecu=
reLibNull.inf=0D
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo=
tManagerLib.inf=0D
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN=
ull.inf=0D
+=0D
+ RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf=0D
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor=
tStatusCodeLibNull.inf=0D
+=0D
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza=
tionLib.inf=0D
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf=0D
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf=0D
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib=
.inf=0D
+ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf=0D
+=0D
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf=0D
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+=0D
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf=0D
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres=
sLib.inf=0D
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U=
efiRuntimeServicesTableLib.inf=0D
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo=
tServicesTableLib.inf=0D
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry=
Point.inf=0D
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA=
pplicationEntryPoint.inf=0D
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic=
esLib.inf=0D
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag=
erLib.inf=0D
+=0D
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf=0D
+ VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var=
iablePolicyHelperLib.inf=0D
+=0D
+ #=0D
+ # Scsi Requirements=0D
+ #=0D
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf=0D
+=0D
+ #=0D
+ # USB Requirements=0D
+ #=0D
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf=0D
+=0D
+ #=0D
+ # Networking Requirements=0D
+ #=0D
+ DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf=0D
+ IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf=0D
+ NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf=0D
+ UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf=0D
+ HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf=0D
+=0D
+[LibraryClasses.common.SEC]=0D
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf=0D
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsB=
aseLib.inf=0D
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib=
/PrePiExtractGuidedSectionLib.inf=0D
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto=
mDecompressLib.inf=0D
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe=
moryAllocationLib.inf=0D
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf=0D
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf=0D
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre=
PiHobListPointerLib.inf=0D
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.=
inf=0D
+=0D
+[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]=0D
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf=0D
+=0D
+[LibraryClasses.common.DXE_CORE]=0D
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf=
=0D
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt=
ractGuidedSectionLib.inf=0D
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf=0D
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC=
oreMemoryAllocationLib.inf=0D
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform=
anceLib.inf=0D
+=0D
+[LibraryClasses.common.DXE_DRIVER]=0D
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS=
ecurityManagementLib.inf=0D
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.=
inf=0D
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL=
ib.inf=0D
+=0D
+[LibraryClasses.common.UEFI_APPLICATION]=0D
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf=0D
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
+=0D
+ #=0D
+ # UiApp dependencies=0D
+ #=0D
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf=
=0D
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.=
inf=0D
+=0D
+[LibraryClasses.common.UEFI_DRIVER]=0D
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt=
ractGuidedSectionLib.inf=0D
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.=
inf=0D
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
+=0D
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D
+ !if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf=0D
+ !endif=0D
+=0D
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf=
=0D
+=0D
+ !if $(TARGET) !=3D RELEASE=0D
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLi=
bSerialPort.inf=0D
+ !endif=0D
+=0D
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll=
ocationLib.inf=0D
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R=
untimeDxeReportStatusCodeLib.inf=0D
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL=
ibRuntimeDxe.inf=0D
+=0D
+[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER]=0D
+ EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyste=
mLib.inf=0D
+=0D
+[LibraryClasses.ARM, LibraryClasses.AARCH64]=0D
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf=0D
+=0D
+ #=0D
+ # Add support for GCC stack protector=0D
+ #=0D
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf=0D
+=0D
+[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION=
, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE=
R]=0D
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D
+=0D
+[BuildOptions]=0D
+ RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG=0D
+ GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG=0D
+=0D
+[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER]=0D
+ GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+=0D
+[PcdsFeatureFlag.common]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE=0D
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE=0D
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE=0D
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE=0D
+=0D
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE=0D
+=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE=0D
+=0D
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector T=
able at PcdCpuVectorBaseAddress=0D
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE=0D
+=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE=0D
+=0D
+[PcdsFixedAtBuild.common]=0D
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF=0D
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0=0D
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320=0D
+ gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE=0D
+=0D
+!if $(TARGET) =3D=3D RELEASE=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21=0D
+!else=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f=0D
+!endif=0D
+=0D
+ # DEBUG_INIT 0x00000001 // Initialization=0D
+ # DEBUG_WARN 0x00000002 // Warnings=0D
+ # DEBUG_LOAD 0x00000004 // Load events=0D
+ # DEBUG_FS 0x00000008 // EFI File system=0D
+ # DEBUG_POOL 0x00000010 // Alloc & Free's=0D
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's=0D
+ # DEBUG_INFO 0x00000040 // Verbose=0D
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers=0D
+ # DEBUG_VARIABLE 0x00000100 // Variable=0D
+ # DEBUG_BM 0x00000400 // Boot Manager=0D
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver=0D
+ # DEBUG_NET 0x00004000 // SNI Driver=0D
+ # DEBUG_UNDI 0x00010000 // UNDI Driver=0D
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver=0D
+ # DEBUG_EVENT 0x00080000 // Event messages=0D
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes=0D
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes=0D
+ # DEBUG_ERROR 0x80000000 // Error=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046=0D
+=0D
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D
+=0D
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000=0D
+=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20=0D
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0=0D
+=0D
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D
+=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL=
SE=0D
+=0D
+!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04=0D
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04=
=0D
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0=
x04=0D
+!endif=0D
+=0D
+!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000=0D
+!else=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000=0D
+!endif=0D
+=0D
+ # Default platform supported RFC 4646 languages: English & French & Chin=
ese Simplified.=0D
+ # Default Value of PlatformLangCodes Variable.=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;=
zh-Hans"=0D
+=0D
+ # Default current RFC 4646 language: Chinese Simplified.=0D
+ # Default Value of PlatformLang Variable.=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"=0D
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4=0D
+=0D
+ #=0D
+ # ACPI Table Version=0D
+ #=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20=0D
+=0D
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE=0D
+=0D
+[PcdsDynamicDefault.common.DEFAULT]=0D
+ ## This PCD defines the video horizontal resolution.=0D
+ # This PCD could be set to 0 then video resolution could be at highest =
resolution.=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640=0D
+ ## This PCD defines the video vertical resolution.=0D
+ # This PCD could be set to 0 then video resolution could be at highest =
resolution.=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480=0D
+=0D
+ ## This PCD defines the Console output row and the default value is 80 a=
ccording to UEFI spec.=0D
+ # This PCD could be set to 0 then console output could be at max column=
and max row.=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128=0D
+ ## This PCD defines the Console output column and the default value is 2=
5 according to UEFI spec.=0D
+ # This PCD could be set to 0 then console output could be at max column=
and max row.=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40=0D
+=0D
+ ## Specify the video horizontal resolution of text setup.=0D
+ # @Prompt Video Horizontal Resolution of Text Setup=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640=0D
+=0D
+ ## Specify the video vertical resolution of text setup.=0D
+ # @Prompt Video Vertical Resolution of Text Setup=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480=0D
+=0D
+ ## Specify the console output column of text setup.=0D
+ # @Prompt Console Output Column of Text Setup=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128=0D
+ ## Specify the console output row of text setup.=0D
+ # @Prompt Console Output Row of Text Setup=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40=0D
+=0D
+ ## The number of seconds that the firmware will wait before initiating t=
he original default boot selection.=0D
+ # A value of 0 indicates that the default boot selection is to be initi=
ated immediately on boot.=0D
+ # The value of 0xFFFF then firmware will wait for user input before boo=
ting.=0D
+ # @Prompt Boot Timeout (s)=0D
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
new file mode 100644
index 0000000000..b523ecd658
--- /dev/null
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -0,0 +1,298 @@
+## @file=0D
+# This package provides common open source Phytium Platform modules.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D
+#=0D
+# SPDX-License-Identifier:BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Defines Section - statements that will be processed to create a Makefile=
.=0D
+#=0D
+##########################################################################=
######=0D
+[Defines]=0D
+ PLATFORM_NAME =3D DurianPkg=0D
+ PLATFORM_GUID =3D 8f7ac876-3e7c-11eb-86cb-33f68535d613=
=0D
+ PLATFORM_VERSION =3D 0.1=0D
+ DSC_SPECIFICATION =3D 0x0001001c=0D
+ OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)=0D
+ SUPPORTED_ARCHITECTURES =3D AARCH64=0D
+ BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
+ SKUID_IDENTIFIER =3D DEFAULT=0D
+ FLASH_DEFINITION =3D Platform/Phytium/DurianPkg/DurianPkg.=
fdf=0D
+=0D
+!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc=0D
+=0D
+[LibraryClasses.common]=0D
+ # Phytium Platform library=0D
+ ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformL=
ib.inf=0D
+=0D
+ # PL011 UART Driver and Dependency Libraries=0D
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL=
ib.inf=0D
+ PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc=
kLib.inf=0D
+ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf=0D
+=0D
+[LibraryClasses.common.DXE_DRIVER]=0D
+=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+[PcdsFixedAtBuild.common]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform"=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0"=0D
+=0D
+ gArmTokenSpaceGuid.PcdVFPEnabled|1=0D
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x101=0D
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0=0D
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|4=0D
+=0D
+ #=0D
+ # NV Storage PCDs.=0D
+ #=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000=
=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000=
=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe1000=
0=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0001000=
0=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000=
=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000=
=0D
+=0D
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)=0D
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000=0D
+=0D
+ #=0D
+ # PL011 - Serial Terminal=0D
+ #=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0=0D
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000=0D
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200=0D
+=0D
+ #=0D
+ # ARM General Interrupt Controller=0D
+ #=0D
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000=0D
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000=0D
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000=0D
+=0D
+ # System IO space=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000=0D
+=0D
+ #=0D
+ # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for=0D
+ # PBF(the processor basic firmware, Mainly deals the initialization=0D
+ # of the chip).=0D
+ #=0D
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000=0D
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000=0D
+=0D
+ # Stack Size=0D
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000=0D
+=0D
+ #=0D
+ # Designware PCI Root Complex=0D
+ #=0D
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000=0D
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000=0D
+ gArmTokenSpaceGuid.PcdPciBusMin|0=0D
+ gArmTokenSpaceGuid.PcdPciBusMax|255=0D
+ gArmTokenSpaceGuid.PcdPciIoBase|0x00000=0D
+ gArmTokenSpaceGuid.PcdPciIoSize|0xf00000=0D
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Components Section - list of all EDK II Modules needed by this Platform=
=0D
+#=0D
+##########################################################################=
######=0D
+[Components.common]=0D
+ #=0D
+ # PCD database=0D
+ #=0D
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D
+=0D
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf=0D
+ ShellPkg/Application/Shell/Shell.inf {=0D
+ <LibraryClasses>=0D
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman=
dLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm=
andsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm=
andsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm=
andsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co=
mmandsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewC=
ommandLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm=
andsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1=
CommandsLib.inf=0D
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1=
CommandsLib.inf=0D
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar=
singLib.inf=0D
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf=
gCommandLib.inf=0D
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTre=
eLib/BaseOrderedCollectionRedBlackTreeLib.inf=0D
+ }=0D
+=0D
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {=0D
+ <LibraryClasses>=0D
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf=0D
+ }=0D
+=0D
+ #=0D
+ # Dxe core entry=0D
+ #=0D
+ MdeModulePkg/Core/Dxe/DxeMain.inf {=0D
+ <LibraryClasses>=0D
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu=
idedSectionExtractLib.inf=0D
+ }=0D
+=0D
+ #=0D
+ # DXE driver=0D
+ #=0D
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {=0D
+ <LibraryClasses>=0D
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D
+ }=0D
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf=0D
+=0D
+ #=0D
+ # Common Arm Timer and Gic Components=0D
+ #=0D
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D
+=0D
+ #=0D
+ # security system=0D
+ #=0D
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {=0D
+ <LibraryClasses>=0D
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio=
nLib.inf=0D
+ }=0D
+=0D
+ #=0D
+ # network, mod for https boot.=0D
+ #=0D
+ NetworkPkg/SnpDxe/SnpDxe.inf=0D
+ NetworkPkg/DpcDxe/DpcDxe.inf=0D
+ NetworkPkg/MnpDxe/MnpDxe.inf=0D
+ NetworkPkg/ArpDxe/ArpDxe.inf=0D
+ NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf=0D
+ NetworkPkg/Ip4Dxe/Ip4Dxe.inf=0D
+ NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf=0D
+ NetworkPkg/Udp4Dxe/Udp4Dxe.inf=0D
+ NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf=0D
+=0D
+ NetworkPkg/Ip6Dxe/Ip6Dxe.inf=0D
+ NetworkPkg/Udp6Dxe/Udp6Dxe.inf=0D
+ NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf=0D
+ NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf=0D
+ NetworkPkg/TcpDxe/TcpDxe.inf=0D
+=0D
+ NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf=0D
+=0D
+ NetworkPkg/DnsDxe/DnsDxe.inf=0D
+ NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf=0D
+ NetworkPkg/HttpDxe/HttpDxe.inf=0D
+=0D
+ #=0D
+ # FV Filesystem=0D
+ #=0D
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf=0D
+=0D
+ #=0D
+ # Common Console Components=0D
+ # ConIn,ConOut,StdErr=0D
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf=0D
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf=0D
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf=
=0D
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf=0D
+=0D
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx=
e.inf=0D
+=0D
+ #=0D
+ # Hii database init=0D
+ #=0D
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D
+=0D
+ #=0D
+ # FAT filesystem + GPT/MBR partitioning=0D
+ #=0D
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf=0D
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf=0D
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf=0D
+ FatPkg/EnhancedFatDxe/Fat.inf=0D
+=0D
+ #=0D
+ # Generic Watchdog Timer=0D
+ #=0D
+ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D
+=0D
+ #=0D
+ # Usb Support=0D
+ #=0D
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf=0D
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf=0D
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf=0D
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf=0D
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf=0D
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf=0D
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf=0D
+=0D
+ #=0D
+ # IDE/AHCI Support=0D
+ #=0D
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf=0D
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D
+=0D
+ #=0D
+ # PCI Support=0D
+ #=0D
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic=
eDxe.inf=0D
+=0D
+ #=0D
+ # The following 2 module perform the same work except one operate variab=
le.=0D
+ # Only one of both should be put into fdf.=0D
+ #=0D
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim=
eDxe.inf=0D
+=0D
+ #=0D
+ # NVME Support=0D
+ #=0D
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D
+=0D
+=0D
+ #=0D
+ # Bds=0D
+ #=0D
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf=0D
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf=0D
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf=0D
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf=0D
+ MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf=0D
+ MdeModulePkg/Application/UiApp/UiApp.inf {=0D
+ <LibraryClasses>=0D
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf=
=0D
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf=0D
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc=
eManagerUiLib.inf=0D
+ }=0D
+ MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf=0D
+=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
new file mode 100644
index 0000000000..9d75b072c6
--- /dev/null
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -0,0 +1,210 @@
+## @file=0D
+# This package provides common open source Phytium Platform modules.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D
+#=0D
+# SPDX-License-Identifier:BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# FD Section=0D
+# The [FD] Section is made up of the definition statements and a=0D
+# description of what goes into the Flash Device Image. Each FD section=
=0D
+# defines one flash "device" image. A flash device image may be one of=0D
+# the following: Removable media bootable image (like a boot floppy=0D
+# image,) an Option ROM image (that would be "flashed" into an add-in=0D
+# card,) a System "Flash" image (that would be burned into a system's=0D
+# flash) or an Update ("Capsule") image that will be used to update and=0D
+# existing system flash.=0D
+#=0D
+##########################################################################=
######=0D
+=0D
+[FD.PHYTIUM]=0D
+BaseAddress =3D 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress=0D
+Size =3D 0x01000000|gArmTokenSpaceGuid.PcdFdSize=0D
+ErasePolarity =3D 1=0D
+=0D
+# This one is tricky, it must be: BlockSize * NumBlocks =3D Size=0D
+BlockSize =3D 0x10000=0D
+NumBlocks =3D 0x100=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Following are lists of FD Region layout which correspond to the location=
s of different=0D
+# images within the flash device.=0D
+#=0D
+# Regions must be defined in ascending order and may not overlap.=0D
+#=0D
+# A Layout Region start with a eight digit hex offset (leading "0x" requir=
ed) followed by=0D
+# the pipe "|" character, followed by the size of the region, also in hex =
with the leading=0D
+# "0x" characters. Like:=0D
+# Offset|Size=0D
+# PcdOffsetCName|PcdSizeCName=0D
+# RegionType <FV, DATA, or FILE>=0D
+#=0D
+##########################################################################=
######=0D
+=0D
+0x00000000|0x200000=0D
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize=0D
+FV =3D FVMAIN_COMPACT=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# FV Section=0D
+#=0D
+# [FV] section is used to define what components or modules are placed wit=
hin a flash=0D
+# device file. This section also defines order the components and modules=
are positioned=0D
+# within the image. The [FV] section consists of define statements, set s=
tatements and=0D
+# module statements.=0D
+#=0D
+##########################################################################=
######=0D
+=0D
+[FV.FvMain]=0D
+BlockSize =3D 0x40=0D
+NumBlocks =3D 0 # This FV gets compressed so make it just=
big enough=0D
+FvAlignment =3D 16 # FV alignment and FV attributes setting=
.=0D
+ERASE_POLARITY =3D 1=0D
+MEMORY_MAPPED =3D TRUE=0D
+STICKY_WRITE =3D TRUE=0D
+LOCK_CAP =3D TRUE=0D
+LOCK_STATUS =3D TRUE=0D
+WRITE_DISABLED_CAP =3D TRUE=0D
+WRITE_ENABLED_CAP =3D TRUE=0D
+WRITE_STATUS =3D TRUE=0D
+WRITE_LOCK_CAP =3D TRUE=0D
+WRITE_LOCK_STATUS =3D TRUE=0D
+READ_DISABLED_CAP =3D TRUE=0D
+READ_ENABLED_CAP =3D TRUE=0D
+READ_STATUS =3D TRUE=0D
+READ_LOCK_CAP =3D TRUE=0D
+READ_LOCK_STATUS =3D TRUE=0D
+=0D
+ APRIORI DXE {=0D
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D
+ }=0D
+=0D
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf=0D
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D
+=0D
+ #=0D
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)=0D
+ #=0D
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
+=0D
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu=
ntimeDxe.inf=0D
+=0D
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D
+=0D
+ #=0D
+ # Variable services=0D
+ #=0D
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i=
nf=0D
+=0D
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D
+=0D
+ #=0D
+ # Multiple Console IO support=0D
+ #=0D
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf=0D
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf=0D
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe=
.inf=0D
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf=0D
+=0D
+ #=0D
+ # FAT filesystem + GPT/MBR partitioning=0D
+ #=0D
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf=0D
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf=0D
+ INF FatPkg/EnhancedFatDxe/Fat.inf=0D
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i=
nf=0D
+=0D
+ #=0D
+ # SATA Controller=0D
+ #=0D
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf=0D
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D
+=0D
+ #=0D
+ # NVMe boot devices=0D
+ #=0D
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D
+=0D
+ #=0D
+ # Usb Support=0D
+ #=0D
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf=0D
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf=0D
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf=0D
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf=0D
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf=0D
+ INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf=0D
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf=0D
+=0D
+ #=0D
+ # NetWork=0D
+ #=0D
+ INF NetworkPkg/SnpDxe/SnpDxe.inf=0D
+ INF NetworkPkg/DpcDxe/DpcDxe.inf=0D
+ INF NetworkPkg/MnpDxe/MnpDxe.inf=0D
+ INF NetworkPkg/ArpDxe/ArpDxe.inf=0D
+ INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf=0D
+ INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf=0D
+ INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf=0D
+ INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf=0D
+ INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf=0D
+=0D
+ #=0D
+ # UEFI applications=0D
+ #=0D
+ INF ShellPkg/Application/Shell/Shell.inf=0D
+=0D
+ #=0D
+ # Bds=0D
+ #=0D
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf=0D
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf=0D
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf=0D
+ INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf=0D
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf=0D
+ INF MdeModulePkg/Application/UiApp/UiApp.inf=0D
+=0D
+[FV.FVMAIN_COMPACT]=0D
+FvAlignment =3D 16=0D
+ERASE_POLARITY =3D 1=0D
+MEMORY_MAPPED =3D TRUE=0D
+STICKY_WRITE =3D TRUE=0D
+LOCK_CAP =3D TRUE=0D
+LOCK_STATUS =3D TRUE=0D
+WRITE_DISABLED_CAP =3D TRUE=0D
+WRITE_ENABLED_CAP =3D TRUE=0D
+WRITE_STATUS =3D TRUE=0D
+WRITE_LOCK_CAP =3D TRUE=0D
+WRITE_LOCK_STATUS =3D TRUE=0D
+READ_DISABLED_CAP =3D TRUE=0D
+READ_ENABLED_CAP =3D TRUE=0D
+READ_STATUS =3D TRUE=0D
+READ_LOCK_CAP =3D TRUE=0D
+READ_LOCK_STATUS =3D TRUE=0D
+=0D
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf=0D
+=0D
+ FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {=0D
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE=
D =3D TRUE {=0D
+ SECTION FV_IMAGE =3D FVMAIN=0D
+ }=0D
+ }=0D
+=0D
+!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.in=
f b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
new file mode 100644
index 0000000000..40c070767a
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
@@ -0,0 +1,55 @@
+#/** @file=0D
+# Library for Phytium Platform.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D PlatformLib=0D
+ FILE_GUID =3D fac08f56-40fe-11eb-a2a3-27b46864b1f3=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D ArmPlatformLib=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ ArmPlatformPkg/ArmPlatformPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ ArmSmcLib=0D
+ HobLib=0D
+=0D
+[Sources.common]=0D
+ PlatformLib.c=0D
+ PlatformLibMem.c=0D
+=0D
+[Sources.AARCH64]=0D
+ AArch64/PhytiumPlatformHelper.S=0D
+=0D
+[Guids]=0D
+=0D
+[FixedPcd]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize=0D
+ gArmTokenSpaceGuid.PcdPciBusMin=0D
+ gArmTokenSpaceGuid.PcdPciBusMax=0D
+ gArmTokenSpaceGuid.PcdPciIoBase=0D
+ gArmTokenSpaceGuid.PcdPciIoSize=0D
+ gArmTokenSpaceGuid.PcdPciIoTranslation=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Size=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Translation=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Size=0D
+=0D
+[Pcd]=0D
+ gArmPlatformTokenSpaceGuid.PcdCoreCount=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterfac=
e.h b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
new file mode 100644
index 0000000000..c4395153a3
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
@@ -0,0 +1,112 @@
+/** @file=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef SYSTEM_SERVICE_INTERFACE_H_=0D
+#define SYSTEM_SERVICE_INTERFACE_H_=0D
+=0D
+/* SMC function IDs for OEM Service queries */=0D
+#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03=0D
+#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001=0D
+#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002=0D
+#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003=0D
+#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004=0D
+#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005=0D
+#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006=0D
+#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007=0D
+#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008=0D
+#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C=0D
+=0D
+#define PHYTIUM_IOBASE_MASK 0xfffffff=0D
+#define PHYTIUM_MEMIO32_MASK 0xffffffff=0D
+#define PHYTIUM_MEMIO64_MASK 0xffffffffff=0D
+=0D
+#pragma pack(1)=0D
+=0D
+typedef struct {=0D
+ UINT64 CpuMapCount;=0D
+ UINT64 CpuMap[1];=0D
+} PHYTIUM_CPU_MAP_INFO;=0D
+=0D
+=0D
+typedef struct {=0D
+ UINT64 CpuFreq; // Hz=0D
+ UINT64 CpuL3CacheSize; // Byte=0D
+ UINT64 CpuL3CacheLineSize; // Byte=0D
+} PHYTIUM_CPU_COURE_INFO;=0D
+=0D
+typedef struct {=0D
+ UINT64 CupVersion; //cpu version=0D
+ PHYTIUM_CPU_COURE_INFO CpuCoreInfo; //cpu core info=0D
+ PHYTIUM_CPU_MAP_INFO CpuMapInfo; //cpu map info=0D
+}PHYTIUM_CPU_INFO;=0D
+=0D
+typedef struct {=0D
+ UINT64 MemSize; // MB=0D
+ UINT64 MemDramId;=0D
+ UINT64 MemModuleId;=0D
+ UINT64 MemSerial;=0D
+ UINT64 MemSlotNumber;=0D
+ UINT64 MemFeatures;=0D
+} MCU_DIMM;=0D
+=0D
+#define MCU_DIMM_MAXCOUNT 2=0D
+=0D
+typedef struct {=0D
+ UINT64 MemFreq; // MHz=0D
+ UINT64 MemDimmCount;=0D
+ MCU_DIMM McuDimm[1];=0D
+} MCU_DIMMS;=0D
+=0D
+typedef struct {=0D
+ UINT64 MemStart;=0D
+ UINT64 MemSize;=0D
+ UINT64 MemNodeId;=0D
+} MEMORY_BLOCK;=0D
+=0D
+typedef struct {=0D
+ UINT64 MemBlockCount;=0D
+ MEMORY_BLOCK MemBlock[1];=0D
+} MEMORY_INFO;=0D
+=0D
+typedef struct {=0D
+ UINT8 PciLane;=0D
+ UINT8 PciSpeed;=0D
+ UINT8 Reserved[6];=0D
+} PCI_BLOCK;=0D
+=0D
+typedef struct {=0D
+ UINT64 PciCount;=0D
+ PCI_BLOCK PciBlock[1];=0D
+} PHYTIUM_PCI_CONTROLLER;=0D
+=0D
+typedef struct {=0D
+ UINT8 BusStart;=0D
+ UINT8 BusEnd;=0D
+ UINT8 Reserved[6];=0D
+ UINT64 PciConfigBase;=0D
+ UINT64 IoBase;=0D
+ UINT64 IoSize;=0D
+ UINT64 Mem32Base;=0D
+ UINT64 Mem32Size;=0D
+ UINT64 Mem64Base;=0D
+ UINT64 Mem64Size;=0D
+ UINT16 IntA;=0D
+ UINT16 IntB;=0D
+ UINT16 IntC;=0D
+ UINT16 IntD;=0D
+} PCI_HOST_BLOCK;=0D
+=0D
+typedef struct {=0D
+ UINT64 PciHostCount;=0D
+ PCI_HOST_BLOCK PciHostBlock[1];=0D
+} PHYTIUM_PCI_HOST_BRIDGE;=0D
+=0D
+#pragma pack ()=0D
+=0D
+=0D
+#endif // SYSTEM_SERVICE_INTERFACE_H_=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c =
b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
new file mode 100644
index 0000000000..6a8d226574
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
@@ -0,0 +1,137 @@
+/** @file=0D
+ Library for Phytium platform.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/ArmPlatformLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <Ppi/ArmMpCoreInfo.h>=0D
+=0D
+ARM_CORE_INFO mPhytiumMpCoreInfoTable[] =3D {=0D
+ {=0D
+ 0x0, 0x0, // Cluster 0, Core 0=0D
+=0D
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value=0D
+ (EFI_PHYSICAL_ADDRESS)0,=0D
+ (EFI_PHYSICAL_ADDRESS)0,=0D
+ (EFI_PHYSICAL_ADDRESS)0,=0D
+ (UINT64)0xFFFFFFFF=0D
+ }=0D
+};=0D
+=0D
+/*=0D
+ This function geted the current Boot Mode.=0D
+=0D
+ This function returns the boot reason on the platform.=0D
+=0D
+ @return Return the current Boot Mode of the platform.=0D
+=0D
+*/=0D
+EFI_BOOT_MODE=0D
+ArmPlatformGetBootMode (=0D
+ VOID=0D
+ )=0D
+{=0D
+ return BOOT_WITH_FULL_CONFIGURATION;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Initialize controllers that must setup in the normal world.=0D
+=0D
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/=
PlatformPeim=0D
+ in the PEI phase.=0D
+=0D
+ @retval EFI_SUCCESS ArmPlatformInitialize() is executed successf=
ully.=0D
+=0D
+**/=0D
+RETURN_STATUS=0D
+ArmPlatformInitialize (=0D
+ IN UINTN MpId=0D
+ )=0D
+{=0D
+ return RETURN_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function Inited the system (or sometimes called permanent) memory.=
=0D
+=0D
+ This memory is generally represented by the DRAM.=0D
+=0D
+ @param[in] None.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+VOID=0D
+ArmPlatformInitializeSystemMemory (=0D
+ VOID=0D
+ )=0D
+{=0D
+ // Nothing to do here=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function geted the information of core.=0D
+=0D
+ @param[out] CoreCount The count of CoreInfoTable.=0D
+ @param[out] ArmCoreTable The pointer of CoreInfoTable.=0D
+=0D
+ @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed succes=
sfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+PrePeiCoreGetMpCoreInfo (=0D
+ OUT UINTN *CoreCount,=0D
+ OUT ARM_CORE_INFO **ArmCoreTable=0D
+ )=0D
+{=0D
+ *CoreCount =3D PcdGet32 (PcdCoreCount);=0D
+ *ArmCoreTable =3D mPhytiumMpCoreInfoTable;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+//=0D
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is=0D
+// undefined in the contect of PrePeiCore=0D
+//=0D
+EFI_GUID mArmMpCoreInfoPpiGuid =3D ARM_MP_CORE_INFO_PPI_GUID;=0D
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo };=0D
+=0D
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D=0D
+{=0D
+ {=0D
+ EFI_PEI_PPI_DESCRIPTOR_PPI,=0D
+ &mArmMpCoreInfoPpiGuid,=0D
+ &mMpCoreInfoPpi=0D
+ }=0D
+};=0D
+=0D
+=0D
+/**=0D
+ This function geted the information of Ppitable.=0D
+=0D
+ @param[out] PpiListSize The size of Ppitable.=0D
+ @param[out] PpiList The pointer of Ppitable.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+VOID=0D
+ArmPlatformGetPlatformPpiList (=0D
+ OUT UINTN *PpiListSize,=0D
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList=0D
+ )=0D
+{=0D
+ *PpiListSize =3D sizeof (gPlatformPpiTable);=0D
+ *PpiList =3D gPlatformPpiTable;=0D
+}=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem=
.c b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
new file mode 100644
index 0000000000..7e54cb6e74
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
@@ -0,0 +1,156 @@
+/** @file=0D
+ Library of memory map for Phytium platform.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/ArmPlatformLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/HobLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/ArmSmcLib.h>=0D
+#include <SystemServiceInterface.h>=0D
+=0D
+// Number of Virtual Memory Map Descriptors=0D
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32=0D
+=0D
+// DDR attributes=0D
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK=
=0D
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UN=
BUFFERED=0D
+=0D
+/**=0D
+ Return the Virtual Memory Map of your platform=0D
+=0D
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize th=
e MMU on your platform.=0D
+=0D
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des=
cribing a Physical-to-=0D
+ Virtual Memory mapping. This array must b=
e ended by a zero-filled=0D
+ entry=0D
+**/=0D
+VOID=0D
+ArmPlatformGetVirtualMemoryMap (=0D
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap=0D
+ )=0D
+{=0D
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;=0D
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;=0D
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D
+ MEMORY_BLOCK *MemBlock;=0D
+ MEMORY_INFO *MemInfo;=0D
+ ARM_SMC_ARGS ArmSmcArgs;=0D
+ UINT32 MemBlockCnt;=0D
+ UINT32 Index1;=0D
+ UINT32 Index2;=0D
+=0D
+ MemBlock =3D NULL;=0D
+ MemInfo =3D NULL;=0D
+ MemBlockCnt =3D 0;=0D
+ Index1 =3D 0;=0D
+ Index2 =3D 0;=0D
+ CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;=0D
+=0D
+ ASSERT (VirtualMemoryMap !=3D NULL);=0D
+ VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages \=0D
+ (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DES=
CRIPTOR) * \=0D
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));=0D
+ if (VirtualMemoryTable =3D=3D NULL) {=0D
+ return;=0D
+ }=0D
+=0D
+ ResourceAttributes =3D=0D
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |=0D
+ EFI_RESOURCE_ATTRIBUTE_TESTED;=0D
+=0D
+ MemInfo =3D AllocatePages (1);=0D
+ ASSERT (MemInfo !=3D NULL);=0D
+=0D
+ ArmSmcArgs.Arg0 =3D PHYTIUM_OEM_SVC_MEM_REGIONS;=0D
+ ArmSmcArgs.Arg1 =3D (UINTN) MemInfo;=0D
+ ArmSmcArgs.Arg2 =3D EFI_PAGE_SIZE;=0D
+ ArmCallSmc (&ArmSmcArgs);=0D
+ if (ArmSmcArgs.Arg0 =3D=3D 0) {=0D
+ MemBlockCnt =3D MemInfo->MemBlockCount;=0D
+ MemBlock =3D MemInfo->MemBlock;=0D
+ } else {=0D
+ ASSERT (FALSE);=0D
+ }=0D
+=0D
+ //Soc Io Space=0D
+ VirtualMemoryTable[Index1].PhysicalBase =3D PcdGet64 (PcdSystemIoBase)=
;=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdSystemIoBase)=
;=0D
+ VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdSystemIoSize)=
;=0D
+ VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT=
E_DEVICE;=0D
+=0D
+ //=0D
+ // PCI Configuration Space=0D
+ //=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciConfigBas=
e);=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciConfigBas=
e);=0D
+ VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciConfigSiz=
e);=0D
+ VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU=
TE_DEVICE;=0D
+=0D
+ //=0D
+ // PCI Memory Space=0D
+ //=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciIoBase) +=
PcdGet64 (PcdPciIoTranslation);=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciIoBase) +=
PcdGet64 (PcdPciIoTranslation);=0D
+ VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciIoSize);=
=0D
+ VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU=
TE_DEVICE;=0D
+=0D
+ //=0D
+ // PCI Memory Space=0D
+ //=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet32 (PcdPciMmio32Bas=
e);=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D PcdGet32 (PcdPciMmio32Bas=
e);=0D
+ VirtualMemoryTable[Index1].Length =3D PcdGet32 (PcdPciMmio32Siz=
e);=0D
+ VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU=
TE_DEVICE;=0D
+=0D
+ //=0D
+ // 64-bit PCI Memory Space=0D
+ //=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D PcdGet64 (PcdPciMmio64Bas=
e);=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D PcdGet64 (PcdPciMmio64Bas=
e);=0D
+ VirtualMemoryTable[Index1].Length =3D PcdGet64 (PcdPciMmio64Siz=
e);=0D
+ VirtualMemoryTable[Index1].Attributes =3D ARM_MEMORY_REGION_ATTRIBU=
TE_DEVICE;=0D
+=0D
+ //DDR=0D
+ for (Index2 =3D 0; Index2 < MemBlockCnt; Index2++) {=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D MemBlock->MemStart;=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D MemBlock->MemStart;=0D
+ VirtualMemoryTable[Index1].Length =3D MemBlock->MemSize;=0D
+ VirtualMemoryTable[Index1].Attributes =3D CacheAttributes;=0D
+=0D
+ BuildResourceDescriptorHob (=0D
+ EFI_RESOURCE_SYSTEM_MEMORY,=0D
+ ResourceAttributes,=0D
+ MemBlock->MemStart,=0D
+ MemBlock->MemSize=0D
+ );=0D
+=0D
+ MemBlock++;=0D
+ }=0D
+=0D
+ // End of Table=0D
+ VirtualMemoryTable[++Index1].PhysicalBase =3D 0;=0D
+ VirtualMemoryTable[Index1].VirtualBase =3D 0;=0D
+ VirtualMemoryTable[Index1].Length =3D 0;=0D
+ VirtualMemoryTable[Index1].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU=
TES)0;=0D
+=0D
+=0D
+ for (Index2 =3D 0; Index2 < Index1; Index2++) {=0D
+ DEBUG ((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12l=
x Attributes %12lx\n",\=0D
+ VirtualMemoryTable[Index2].PhysicalBase, VirtualMemoryTable[Index2].=
VirtualBase, \=0D
+ VirtualMemoryTable[Index2].Length, VirtualMemoryTable[Index2].Attrib=
utes));=0D
+ }=0D
+=0D
+ *VirtualMemoryMap =3D VirtualMemoryTable;=0D
+}=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/Phytiu=
mPlatformHelper.S b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64=
/PhytiumPlatformHelper.S
new file mode 100644
index 0000000000..cce23b7861
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatfo=
rmHelper.S
@@ -0,0 +1,76 @@
+#=0D
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.=0D
+#=0D
+# This program and the accompanying materials=0D
+# are licensed and made available under the terms and conditions of the B=
SD License=0D
+# which accompanies this distribution. The full text of the license may =
be found at=0D
+# http://opensource.org/licenses/bsd-license.php=0D
+#=0D
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=0D
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM=
PLIED.=0D
+#=0D
+#=0D
+=0D
+#include <AsmMacroIoLibV8.h>=0D
+#include <Base.h>=0D
+#include <Library/ArmLib.h>=0D
+#include <Library/PcdLib.h>=0D
+#include <AutoGen.h>=0D
+=0D
+.text=0D
+.align 2=0D
+=0D
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)=0D
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)=0D
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)=0D
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)=0D
+=0D
+PrimaryCoreMpid: .word 0x0=0D
+=0D
+=0D
+ASM_PFX(ArmPlatformPeiBootAction):=0D
+ // Save MPIDR_EL1[23:0] in a variable.=0D
+ mov x20, x30=0D
+ bl ASM_PFX(ArmReadMpidr)=0D
+ lsl w0, w0, #8=0D
+ lsr w0, w0, #8=0D
+ ldr x1, =3DPrimaryCoreMpid=0D
+ str w0, [x1]=0D
+ ret x20=0D
+=0D
+//UINTN=0D
+//ArmPlatformGetPrimaryCoreMpId (=0D
+// VOID=0D
+// );=0D
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):=0D
+ ldr x0, =3DPrimaryCoreMpid=0D
+ ldr w0, [x0]=0D
+ ret=0D
+=0D
+//UINTN=0D
+//ArmPlatformIsPrimaryCore (=0D
+// IN UINTN MpId=0D
+// );=0D
+ASM_PFX(ArmPlatformIsPrimaryCore):=0D
+ mov x20, x30=0D
+ bl ASM_PFX(ArmReadMpidr)=0D
+ lsl w0, w0, #8=0D
+ lsr w0, w0, #8=0D
+ ldr x1, =3DPrimaryCoreMpid=0D
+ ldr w1, [x1]=0D
+ cmp w0, w1=0D
+ cset x0, eq=0D
+ ret x20=0D
+=0D
+//UINTN=0D
+//ArmPlatformGetCorePosition (=0D
+// IN UINTN MpId=0D
+// );=0D
+// With this function: CorePos =3D (ClusterId * 4) + CoreId=0D
+ASM_PFX(ArmPlatformGetCorePosition):=0D
+ and x1, x0, #ARM_CORE_MASK=0D
+ and x0, x0, #ARM_CLUSTER_MASK=0D
+ add x0, x1, x0, LSR #6=0D
+ ret=0D
+=0D
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc b/Si=
licon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
new file mode 100644
index 0000000000..641266c601
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
@@ -0,0 +1,119 @@
+## @file=0D
+# This package provides common open source Phytium silicon modules.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D
+#=0D
+# SPDX-License-Identifier:BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
##=0D
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section =
#=0D
+##########################################################################=
##=0D
+#=0D
+#[Rule.Common.DXE_DRIVER]=0D
+# FILE DRIVER =3D $(NAMED_GUID) {=0D
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_=
NAME).depex=0D
+# COMPRESS PI_STD {=0D
+# GUIDED {=0D
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=
=0D
+# UI STRING=3D"$(MODULE_NAME)" Optional=0D
+# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N=
UMBER)=0D
+# }=0D
+# }=0D
+# }=0D
+#=0D
+##########################################################################=
##=0D
+=0D
+[Rule.Common.SEC]=0D
+ FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED {=0D
+ TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi=
=0D
+ }=0D
+=0D
+[Rule.Common.PEI_CORE]=0D
+ FILE PEI_CORE =3D $(NAMED_GUID) FIXED {=0D
+ TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi=
=0D
+ UI STRING =3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.PEIM]=0D
+ FILE PEIM =3D $(NAMED_GUID) FIXED {=0D
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex=
=0D
+ TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi=
=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.PEIM.TIANOCOMPRESSED]=0D
+ FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {=0D
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex=
=0D
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR=
UE {=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+ }=0D
+=0D
+[Rule.Common.DXE_CORE]=0D
+ FILE DXE_CORE =3D $(NAMED_GUID) {=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.UEFI_DRIVER]=0D
+ FILE DRIVER =3D $(NAMED_GUID) {=0D
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA=
ME).depex=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.DXE_DRIVER]=0D
+ FILE DRIVER =3D $(NAMED_GUID) {=0D
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA=
ME).depex=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.DXE_RUNTIME_DRIVER]=0D
+ FILE DRIVER =3D $(NAMED_GUID) {=0D
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA=
ME).depex=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ }=0D
+=0D
+[Rule.Common.UEFI_APPLICATION]=0D
+ FILE APPLICATION =3D $(NAMED_GUID) {=0D
+ UI STRING =3D"$(MODULE_NAME)" Optional=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ }=0D
+=0D
+[Rule.Common.UEFI_DRIVER.BINARY]=0D
+ FILE DRIVER =3D $(NAMED_GUID) {=0D
+ DXE_DEPEX DXE_DEPEX Optional |.depex=0D
+ PE32 PE32 |.efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE=
R)=0D
+ }=0D
+=0D
+[Rule.Common.UEFI_APPLICATION.BINARY]=0D
+ FILE APPLICATION =3D $(NAMED_GUID) {=0D
+ PE32 PE32 |.efi=0D
+ UI STRING=3D"$(MODULE_NAME)" Optional=0D
+ VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE=
R)=0D
+ }=0D
+=0D
+[Rule.Common.USER_DEFINED.BIOSINFO]=0D
+ FILE FREEFORM =3D $(NAMED_GUID) {=0D
+ RAW BIN Align =3D 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi=0D
+ }=0D
+=0D
+[Rule.Common.UEFI_APPLICATION.UI]=0D
+ FILE APPLICATION =3D $(NAMED_GUID) {=0D
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D
+ UI STRING=3D"Enter Setup"=0D
+ VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE=
R)=0D
+ }=0D
+=0D
+[Rule.Common.USER_DEFINED.ACPITABLE]=0D
+ FILE FREEFORM =3D $(NAMED_GUID) {=0D
+ RAW ACPI |.acpi=0D
+ RAW ASL |.aml=0D
+ }=0D
--=20
2.25.1

The PCI Segment Library for Phytium platform.
with multiple RCs.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 9=
+-
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28=
+
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434=
++++++++++++++++++++
3 files changed, 1464 insertions(+), 7 deletions(-)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 28e52e15e3..093b2cd9db 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -35,7 +35,8 @@
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf=0D
=0D
[LibraryClasses.common.DXE_DRIVER]=0D
-=0D
+ # Pci dependencies=0D
+ PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme=
ntLib.inf=0D
=0D
##########################################################################=
######=0D
#=0D
@@ -262,12 +263,6 @@
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D
=0D
- #=0D
- # PCI Support=0D
- #=0D
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D
- MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic=
eDxe.inf=0D
-=0D
#=0D
# The following 2 module perform the same work except one operate variab=
le.=0D
# Only one of both should be put into fdf.=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLi=
b.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000000..67360016ef
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,28 @@
+#/** @file=0D
+# PCI Segment Library for Phytium platform with multiple RCs.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D PciSegmentLib=0D
+ FILE_GUID =3D fa5173d2-40fe-11eb-9b2f-cb20dc669fd3=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D PciSegmentLib=0D
+=0D
+[Sources]=0D
+ PciSegmentLib.c=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ IoLib=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLi=
b.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000000..c10b152e0d
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1434 @@
+/** @file=0D
+ PCI Segment Library for SoC with multiple RCs.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Base.h>=0D
+#include <Library/PciSegmentLib.h>=0D
+#include <Library/BaseLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/IoLib.h>=0D
+=0D
+#define PCI_SEG_CONFIG_BASE 0x40000000=0D
+#define PCIE_BIF_MODE 0x29100800=0D
+=0D
+typedef enum {=0D
+ PciCfgWidthUint8 =3D 0,=0D
+ PciCfgWidthUint16,=0D
+ PciCfgWidthUint32,=0D
+ PciCfgWidthMax=0D
+} PCI_CFG_WIDTH;=0D
+=0D
+/**=0D
+ Assert the validity of a PCI Segment address.=0D
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48=
..63=0D
+=0D
+ @param[in] A The address to validate.=0D
+ @param[in] M Additional bits to assert to be zero.=0D
+=0D
+**/=0D
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \=0D
+ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0)=0D
+=0D
+=0D
+#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \=0D
+{ \=0D
+ (Bus) =3D (((Address) >> 20) & 0xff); \=0D
+ (Device) =3D (((Address) >> 15) & 0x1f); \=0D
+ (Function) =3D (((Address) >> 12) & 0x07); \=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function geted the config base of PCI device.=0D
+ @param[in] Address The address that encodes the PCI Bus, Device, Funct=
ion and=0D
+ Register.=0D
+=0D
+ @return The value of the config base of PCI device.=0D
+=0D
+**/=0D
+STATIC=0D
+UINT64=0D
+PciSegmentLibGetConfigBase (=0D
+ IN UINT64 Address=0D
+ )=0D
+{=0D
+ UINT8 Bus;=0D
+ UINT8 Device;=0D
+ UINT8 Function;=0D
+ UINT8 RootPortCount;=0D
+ UINT8 Peu0RootPortCount;=0D
+ UINT8 Peu1RootPortCount;=0D
+ UINT32 BifMode;=0D
+ UINT32 Peu0BifMode;=0D
+ UINT32 Peu1BifMode;=0D
+=0D
+ EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function);=0D
+ BifMode =3D MmioRead32 (PCIE_BIF_MODE);=0D
+ Peu0BifMode =3D BifMode & 0x3;=0D
+ Peu1BifMode =3D (BifMode >> 2) & 0x3;=0D
+=0D
+ if ((Peu0BifMode =3D=3D 1)) {=0D
+ Peu0RootPortCount =3D 3;=0D
+ } else {=0D
+ Peu0RootPortCount =3D 2;=0D
+ }=0D
+=0D
+ if ((Peu1BifMode =3D=3D 1)) {=0D
+ Peu1RootPortCount =3D 3;=0D
+ } else {=0D
+ Peu1RootPortCount =3D 2;=0D
+ }=0D
+ RootPortCount =3D Peu0RootPortCount + Peu1RootPortCount;=0D
+ //ignore device > 0 or function > 0 on root port=0D
+ if (RootPortCount =3D=3D 4) {=0D
+ if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D =
4)) {=0D
+ if (Device !=3D 0 || Function !=3D 0) {=0D
+ return 0xFFFFFFFF;=0D
+ }=0D
+ return PCI_SEG_CONFIG_BASE;=0D
+ }=0D
+ } else if (RootPortCount =3D=3D 5) {=0D
+ if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D =
4) || (Bus =3D=3D 5)) {=0D
+ if (Device !=3D 0 || Function !=3D 0) {=0D
+ return 0xFFFFFFFF;=0D
+ }=0D
+ return PCI_SEG_CONFIG_BASE;=0D
+ }=0D
+ } else if (RootPortCount =3D=3D 6) {=0D
+ if ((Bus =3D=3D 1) || (Bus =3D=3D 2) || (Bus =3D=3D 3) || (Bus =3D=3D =
4) || (Bus =3D=3D 5) || (Bus =3D=3D 6)) {=0D
+ if (Device !=3D 0 || Function !=3D 0) {=0D
+ return 0xFFFFFFFF;=0D
+ }=0D
+ return PCI_SEG_CONFIG_BASE;=0D
+ }=0D
+ }=0D
+=0D
+ return PCI_SEG_CONFIG_BASE;=0D
+}=0D
+=0D
+/**=0D
+ Internal worker function to read a PCI configuration register.=0D
+=0D
+ @param[in] Address The address that encodes the PCI Bus, Device, Functi=
on and=0D
+ Register.=0D
+ @param[in] Width The width of data to read=0D
+=0D
+ @return The value read from the PCI configuration register.=0D
+=0D
+**/=0D
+STATIC=0D
+UINT32=0D
+PciSegmentLibReadWorker (=0D
+ IN UINT64 Address,=0D
+ IN PCI_CFG_WIDTH Width=0D
+ )=0D
+{=0D
+ UINT64 Base;=0D
+=0D
+ Base =3D PciSegmentLibGetConfigBase (Address);=0D
+ if (Base =3D=3D 0xFFFFFFFF) {=0D
+ return 0xFFFFFFFF;=0D
+ }=0D
+=0D
+ switch (Width) {=0D
+ case PciCfgWidthUint8:=0D
+ return MmioRead8 (Base + (UINT32)Address);=0D
+ case PciCfgWidthUint16:=0D
+ return MmioRead16 (Base + (UINT32)Address);=0D
+ case PciCfgWidthUint32:=0D
+ return MmioRead32 (Base + (UINT32)Address);=0D
+ default:=0D
+ ASSERT (FALSE);=0D
+ }=0D
+=0D
+ return 0;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Internal worker function to writes a PCI configuration register.=0D
+=0D
+ @param[in] Address The address that encodes the PCI Bus, Device, Functi=
on and=0D
+ Register.=0D
+ @param[in] Width The width of data to write=0D
+ @param[in] Data The value to write.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+STATIC=0D
+UINT32=0D
+PciSegmentLibWriteWorker (=0D
+ IN UINT64 Address,=0D
+ IN PCI_CFG_WIDTH Width,=0D
+ IN UINT32 Data=0D
+ )=0D
+{=0D
+ UINT64 Base;=0D
+=0D
+ Base =3D PciSegmentLibGetConfigBase (Address);=0D
+ if (Base =3D=3D 0xFFFFFFFF) {=0D
+ return 0xFFFFFFFF;=0D
+ }=0D
+=0D
+ switch (Width) {=0D
+ case PciCfgWidthUint8:=0D
+ MmioWrite8 (Base + (UINT32)Address, Data);=0D
+ break;=0D
+ case PciCfgWidthUint16:=0D
+ MmioWrite16 (Base + (UINT32)Address, Data);=0D
+ break;=0D
+ case PciCfgWidthUint32:=0D
+ MmioWrite32 (Base + (UINT32)Address, Data);=0D
+ break;=0D
+ default:=0D
+ ASSERT (FALSE);=0D
+ }=0D
+=0D
+ return Data;=0D
+}=0D
+=0D
+/**=0D
+ Register a PCI device so PCI configuration registers may be accessed aft=
er=0D
+ SetVirtualAddressMap().=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Bus, D=
evice, Function and=0D
+ Register.=0D
+=0D
+ @retval RETURN_SUCCESS The PCI device was registered for runti=
me access.=0D
+ @retval RETURN_UNSUPPORTED An attempt was made to call this functi=
on=0D
+ after ExitBootServices().=0D
+ @retval RETURN_UNSUPPORTED The resources required to access the PC=
I device=0D
+ at runtime could not be mapped.=0D
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl=
e to=0D
+ complete the registration.=0D
+=0D
+**/=0D
+RETURN_STATUS=0D
+EFIAPI=0D
+PciSegmentRegisterForRuntimeAccess (=0D
+ IN UINTN Address=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D
+=0D
+ return RETURN_UNSUPPORTED;=0D
+}=0D
+=0D
+/**=0D
+ Reads an 8-bit PCI configuration register.=0D
+=0D
+ Reads and returns the 8-bit PCI configuration register specified by Addr=
ess.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function,=0D
+ and Register.=0D
+=0D
+ @return The 8-bit PCI configuration register specified by Address.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentRead8 (=0D
+ IN UINT64 Address=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D
+=0D
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);=0D
+}=0D
+=0D
+/**=0D
+ Writes an 8-bit PCI configuration register.=0D
+=0D
+ Writes the 8-bit PCI configuration register specified by Address with th=
e value specified by Value.=0D
+ Value is returned. This function must guarantee that all PCI read and w=
rite operations are serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, D=
evice, Function, and Register.=0D
+ @param[in] Value The value to write.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentWrite8 (=0D
+ IN UINT64 Address,=0D
+ IN UINT8 Value=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D
+=0D
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Valu=
e);=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-b=
it value.=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address,=0D
+ performs a bitwise OR between the read result and the value specified by=
OrData,=0D
+ and writes the result to the 8-bit PCI configuration register specified =
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentOr8 (=0D
+ IN UINT64 Address,=0D
+ IN UINT8 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | O=
rData));=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-=
bit value.=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ and writes the result to the 8-bit PCI configuration register specified =
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentAnd8 (=0D
+ IN UINT64 Address,=0D
+ IN UINT8 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & A=
ndData));=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-=
bit value,=0D
+ followed a bitwise OR with another 8-bit value.=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ performs a bitwise OR between the result of the AND operation and the va=
lue specified by OrData,=0D
+ and writes the result to the 8-bit PCI configuration register specified =
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regis=
ter.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentAndThenOr8 (=0D
+ IN UINT64 Address,=0D
+ IN UINT8 AndData,=0D
+ IN UINT8 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & =
AndData) | OrData));=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field of a PCI configuration register.=0D
+=0D
+ Reads the bit field in an 8-bit PCI configuration register. The bit fiel=
d is=0D
+ specified by the StartBit and the EndBit. The value of the bit field is=
=0D
+ returned.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 7, then ASSERT().=0D
+ If EndBit is greater than 7, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to read.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..7.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..7.=0D
+=0D
+ @return The value of the bit field read from the PCI configuration regis=
ter.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentBitFieldRead8 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit=0D
+ )=0D
+{=0D
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);=0D
+}=0D
+=0D
+/**=0D
+ Writes a bit field to a PCI configuration register.=0D
+=0D
+ Writes Value to the bit field of the PCI configuration register. The bit=
=0D
+ field is specified by the StartBit and the EndBit. All other bits in the=
=0D
+ destination PCI configuration register are preserved. The new value of t=
he=0D
+ 8-bit register is returned.=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..7.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..7.=0D
+ @param[in] Value The new value of the bit field.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentBitFieldWrite8 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT8 Value=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (=0D
+ Address,=0D
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Va=
lue)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, =
and=0D
+ writes the result back to the bit field in the 8-bit port.=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address, perform=
s a=0D
+ bitwise OR between the read result and the value specified by=0D
+ OrData, and writes the result to the 8-bit PCI configuration register=0D
+ specified by Address. The value written to the PCI configuration registe=
r is=0D
+ returned. This function must guarantee that all PCI read and write opera=
tions=0D
+ are serialized. Extra left bits in OrData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 7, then ASSERT().=0D
+ If EndBit is greater than 7, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If OrData is larger than the bitmask value range specified by StartBit a=
nd EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..7.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..7.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentBitFieldOr8 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT8 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (=0D
+ Address,=0D
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrDat=
a)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in an 8-bit PCI configuration register, performs a bit=
wise=0D
+ AND, and writes the result back to the bit field in the 8-bit register.=
=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address, perform=
s a=0D
+ bitwise AND between the read result and the value specified by AndData, =
and=0D
+ writes the result to the 8-bit PCI configuration register specified by=0D
+ Address. The value written to the PCI configuration register is returned=
.=0D
+ This function must guarantee that all PCI read and write operations are=
=0D
+ serialized. Extra left bits in AndData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 7, then ASSERT().=0D
+ If EndBit is greater than 7, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If AndData is larger than the bitmask value range specified by StartBit =
and EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..7.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..7.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentBitFieldAnd8 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT8 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (=0D
+ Address,=0D
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndD=
ata)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a=
=0D
+ bitwise OR, and writes the result back to the bit field in the=0D
+ 8-bit port.=0D
+=0D
+ Reads the 8-bit PCI configuration register specified by Address, perform=
s a=0D
+ bitwise AND followed by a bitwise OR between the read result and=0D
+ the value specified by AndData, and writes the result to the 8-bit PCI=0D
+ configuration register specified by Address. The value written to the PC=
I=0D
+ configuration register is returned. This function must guarantee that al=
l PCI=0D
+ read and write operations are serialized. Extra left bits in both AndDat=
a and=0D
+ OrData are stripped.=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..7.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..7.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+ @param[in] OrData The value to OR with the result of the AND operati=
on.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT8=0D
+EFIAPI=0D
+PciSegmentBitFieldAndThenOr8 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT8 AndData,=0D
+ IN UINT8 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite8 (=0D
+ Address,=0D
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit=
, AndData, OrData)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a 16-bit PCI configuration register.=0D
+=0D
+ Reads and returns the 16-bit PCI configuration register specified by Add=
ress.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+=0D
+ @return The 16-bit PCI configuration register specified by Address.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentRead16 (=0D
+ IN UINT64 Address=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);=0D
+=0D
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);=0D
+}=0D
+=0D
+/**=0D
+ Writes a 16-bit PCI configuration register.=0D
+=0D
+ Writes the 16-bit PCI configuration register specified by Address with t=
he value specified by Value.=0D
+ Value is returned. This function must guarantee that all PCI read and w=
rite operations are serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, D=
evice, Function, and Register.=0D
+ @param[in] Value The value to write.=0D
+=0D
+ @return The parameter of Value.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentWrite16 (=0D
+ IN UINT64 Address,=0D
+ IN UINT16 Value=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);=0D
+=0D
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Va=
lue);=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise OR of a 16-bit PCI configuration register with=0D
+ a 16-bit value.=0D
+=0D
+ Reads the 16-bit PCI configuration register specified by Address, perfor=
ms a=0D
+ bitwise OR between the read result and the value specified by=0D
+ OrData, and writes the result to the 16-bit PCI configuration register=0D
+ specified by Address. The value written to the PCI configuration registe=
r is=0D
+ returned. This function must guarantee that all PCI read and write opera=
tions=0D
+ are serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Devic=
e, Function and=0D
+ Register.=0D
+ @param[in] OrData The value to OR with the PCI configuration register.=
=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentOr16 (=0D
+ IN UINT64 Address,=0D
+ IN UINT16 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) =
| OrData));=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-=
bit value.=0D
+=0D
+ Reads the 16-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ and writes the result to the 16-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentAnd16 (=0D
+ IN UINT64 Address,=0D
+ IN UINT16 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) =
& AndData));=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-=
bit value,=0D
+ followed a bitwise OR with another 16-bit value.=0D
+=0D
+ Reads the 16-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ performs a bitwise OR between the result of the AND operation and the va=
lue specified by OrData,=0D
+ and writes the result to the 16-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentAndThenOr16 (=0D
+ IN UINT64 Address,=0D
+ IN UINT16 AndData,=0D
+ IN UINT16 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address)=
& AndData) | OrData));=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field of a PCI configuration register.=0D
+=0D
+ Reads the bit field in a 16-bit PCI configuration register. The bit fiel=
d is=0D
+ specified by the StartBit and the EndBit. The value of the bit field is=
=0D
+ returned.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 15, then ASSERT().=0D
+ If EndBit is greater than 15, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to read.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..15.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..15.=0D
+=0D
+ @return The value of the bit field read from the PCI configuration regis=
ter.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentBitFieldRead16 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit=0D
+ )=0D
+{=0D
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);=0D
+}=0D
+=0D
+/**=0D
+ Writes a bit field to a PCI configuration register.=0D
+=0D
+ Writes Value to the bit field of the PCI configuration register. The bit=
=0D
+ field is specified by the StartBit and the EndBit. All other bits in the=
=0D
+ destination PCI configuration register are preserved. The new value of t=
he=0D
+ 16-bit register is returned.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 15, then ASSERT().=0D
+ If EndBit is greater than 15, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If Value is larger than the bitmask value range specified by StartBit an=
d EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..15.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..15.=0D
+ @param[in] Value The new value of the bit field.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentBitFieldWrite16 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT16 Value=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (=0D
+ Address,=0D
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, =
Value)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads the 16-bit PCI configuration register specified by Address,=0D
+ performs a bitwise OR between the read result and the value specified by=
OrData,=0D
+ and writes the result to the 16-bit PCI configuration register specified=
by Address.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 15, then ASSERT().=0D
+ If EndBit is greater than 15, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If OrData is larger than the bitmask value range specified by StartBit a=
nd EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..15.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..15.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentBitFieldOr16 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT16 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (=0D
+ Address,=0D
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrD=
ata)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,=
=0D
+ and writes the result back to the bit field in the 16-bit port.=0D
+=0D
+ Reads the 16-bit PCI configuration register specified by Address,=0D
+ performs a bitwise OR between the read result and the value specified by=
OrData,=0D
+ and writes the result to the 16-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+ Extra left bits in OrData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 16-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 7, then ASSERT().=0D
+ If EndBit is greater than 7, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If AndData is larger than the bitmask value range specified by StartBit =
and EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ The ordinal of the least significant bit in a byte is =
bit 0.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ The ordinal of the most significant bit in a byte is b=
it 7.=0D
+ @param[in] AndData The value to AND with the read value from the PCI =
configuration register.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentBitFieldAnd16 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT16 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (=0D
+ Address,=0D
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, An=
dData)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a=
=0D
+ bitwise OR, and writes the result back to the bit field in the=0D
+ 16-bit port.=0D
+=0D
+ Reads the 16-bit PCI configuration register specified by Address, perfor=
ms a=0D
+ bitwise AND followed by a bitwise OR between the read result and=0D
+ the value specified by AndData, and writes the result to the 16-bit PCI=
=0D
+ configuration register specified by Address. The value written to the PC=
I=0D
+ configuration register is returned. This function must guarantee that al=
l PCI=0D
+ read and write operations are serialized. Extra left bits in both AndDat=
a and=0D
+ OrData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 15, then ASSERT().=0D
+ If EndBit is greater than 15, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If AndData is larger than the bitmask value range specified by StartBit =
and EndBit, then ASSERT().=0D
+ If OrData is larger than the bitmask value range specified by StartBit a=
nd EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..15.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..15.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+ @param[in] OrData The value to OR with the result of the AND operati=
on.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT16=0D
+EFIAPI=0D
+PciSegmentBitFieldAndThenOr16 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT16 AndData,=0D
+ IN UINT16 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite16 (=0D
+ Address,=0D
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndB=
it, AndData, OrData)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a 32-bit PCI configuration register.=0D
+=0D
+ Reads and returns the 32-bit PCI configuration register specified by Add=
ress.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function,=0D
+ and Register.=0D
+=0D
+ @return The 32-bit PCI configuration register specified by Address.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentRead32 (=0D
+ IN UINT64 Address=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);=0D
+=0D
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);=0D
+}=0D
+=0D
+/**=0D
+ Writes a 32-bit PCI configuration register.=0D
+=0D
+ Writes the 32-bit PCI configuration register specified by Address with t=
he value specified by Value.=0D
+ Value is returned. This function must guarantee that all PCI read and w=
rite operations are serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, D=
evice,=0D
+ Function, and Register.=0D
+ @param[in] Value The value to write.=0D
+=0D
+ @return The parameter of Value.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentWrite32 (=0D
+ IN UINT64 Address,=0D
+ IN UINT32 Value=0D
+ )=0D
+{=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);=0D
+=0D
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b=
it value.=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address,=0D
+ performs a bitwise OR between the read result and the value specified by=
OrData,=0D
+ and writes the result to the 32-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function, and Register.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentOr32 (=0D
+ IN UINT64 Address,=0D
+ IN UINT32 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);=
=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-=
bit value.=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ and writes the result to the 32-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function,=0D
+ and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentAnd32 (=0D
+ IN UINT64 Address,=0D
+ IN UINT32 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData)=
;=0D
+}=0D
+=0D
+/**=0D
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-=
bit value,=0D
+ followed a bitwise OR with another 32-bit value.=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address,=0D
+ performs a bitwise AND between the read result and the value specified b=
y AndData,=0D
+ performs a bitwise OR between the result of the AND operation and the va=
lue specified by OrData,=0D
+ and writes the result to the 32-bit PCI configuration register specified=
by Address.=0D
+ The value written to the PCI configuration register is returned.=0D
+ This function must guarantee that all PCI read and write operations are =
serialized.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+=0D
+ @param[in] Address The address that encodes the PCI Segment, Bus, Dev=
ice, Function,=0D
+ and Register.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentAndThenOr32 (=0D
+ IN UINT64 Address,=0D
+ IN UINT32 AndData,=0D
+ IN UINT32 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData=
) | OrData);=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field of a PCI configuration register.=0D
+=0D
+ Reads the bit field in a 32-bit PCI configuration register. The bit fiel=
d is=0D
+ specified by the StartBit and the EndBit. The value of the bit field is =
returned.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 31, then ASSERT().=0D
+ If EndBit is greater than 31, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to read.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..31.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..31.=0D
+=0D
+ @return The value of the bit field read from the PCI configuration regis=
ter.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentBitFieldRead32 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit=0D
+ )=0D
+{=0D
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);=0D
+}=0D
+=0D
+/**=0D
+ Writes a bit field to a PCI configuration register.=0D
+=0D
+ Writes Value to the bit field of the PCI configuration register. The bit=
=0D
+ field is specified by the StartBit and the EndBit. All other bits in the=
=0D
+ destination PCI configuration register are preserved. The new value of t=
he=0D
+ 32-bit register is returned.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 31, then ASSERT().=0D
+ If EndBit is greater than 31, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If Value is larger than the bitmask value range specified by StartBit an=
d EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..31.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..31.=0D
+ @param[in] Value The new value of the bit field.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentBitFieldWrite32 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT32 Value=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (=0D
+ Address,=0D
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, =
Value)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, =
and=0D
+ writes the result back to the bit field in the 32-bit port.=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address, perfor=
ms a=0D
+ bitwise OR between the read result and the value specified by=0D
+ OrData, and writes the result to the 32-bit PCI configuration register=0D
+ specified by Address. The value written to the PCI configuration registe=
r is=0D
+ returned. This function must guarantee that all PCI read and write opera=
tions=0D
+ are serialized. Extra left bits in OrData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 31, then ASSERT().=0D
+ If EndBit is greater than 31, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If OrData is larger than the bitmask value range specified by StartBit a=
nd EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..31.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..31.=0D
+ @param[in] OrData The value to OR with the PCI configuration registe=
r.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentBitFieldOr32 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT32 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (=0D
+ Address,=0D
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrD=
ata)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in a 32-bit PCI configuration register, performs a bit=
wise=0D
+ AND, and writes the result back to the bit field in the 32-bit register.=
=0D
+=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address, perfor=
ms a bitwise=0D
+ AND between the read result and the value specified by AndData, and writ=
es the result=0D
+ to the 32-bit PCI configuration register specified by Address. The value=
written to=0D
+ the PCI configuration register is returned. This function must guarante=
e that all PCI=0D
+ read and write operations are serialized. Extra left bits in AndData ar=
e stripped.=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If Address is not aligned on a 32-bit boundary, then ASSERT().=0D
+ If StartBit is greater than 31, then ASSERT().=0D
+ If EndBit is greater than 31, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If AndData is larger than the bitmask value range specified by StartBit =
and EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..31.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..31.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentBitFieldAnd32 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT32 AndData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (=0D
+ Address,=0D
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, An=
dData)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a=
=0D
+ bitwise OR, and writes the result back to the bit field in the=0D
+ 32-bit port.=0D
+=0D
+ Reads the 32-bit PCI configuration register specified by Address, perfor=
ms a=0D
+ bitwise AND followed by a bitwise OR between the read result and=0D
+ the value specified by AndData, and writes the result to the 32-bit PCI=
=0D
+ configuration register specified by Address. The value written to the PC=
I=0D
+ configuration register is returned. This function must guarantee that al=
l PCI=0D
+ read and write operations are serialized. Extra left bits in both AndDat=
a and=0D
+ OrData are stripped.=0D
+=0D
+ If any reserved bits in Address are set, then ASSERT().=0D
+ If StartBit is greater than 31, then ASSERT().=0D
+ If EndBit is greater than 31, then ASSERT().=0D
+ If EndBit is less than StartBit, then ASSERT().=0D
+ If AndData is larger than the bitmask value range specified by StartBit =
and EndBit, then ASSERT().=0D
+ If OrData is larger than the bitmask value range specified by StartBit a=
nd EndBit, then ASSERT().=0D
+=0D
+ @param[in] Address The PCI configuration register to write.=0D
+ @param[in] StartBit The ordinal of the least significant bit in the bi=
t field.=0D
+ Range 0..31.=0D
+ @param[in] EndBit The ordinal of the most significant bit in the bit=
field.=0D
+ Range 0..31.=0D
+ @param[in] AndData The value to AND with the PCI configuration regist=
er.=0D
+ @param[in] OrData The value to OR with the result of the AND operati=
on.=0D
+=0D
+ @return The value written back to the PCI configuration register.=0D
+=0D
+**/=0D
+UINT32=0D
+EFIAPI=0D
+PciSegmentBitFieldAndThenOr32 (=0D
+ IN UINT64 Address,=0D
+ IN UINTN StartBit,=0D
+ IN UINTN EndBit,=0D
+ IN UINT32 AndData,=0D
+ IN UINT32 OrData=0D
+ )=0D
+{=0D
+ return PciSegmentWrite32 (=0D
+ Address,=0D
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndB=
it, AndData, OrData)=0D
+ );=0D
+}=0D
+=0D
+/**=0D
+ Reads a range of PCI configuration registers into a caller supplied buff=
er.=0D
+=0D
+ Reads the range of PCI configuration registers specified by StartAddress=
and=0D
+ Size into the buffer specified by Buffer. This function only allows the =
PCI=0D
+ configuration registers from a single PCI function to be read. Size is=0D
+ returned. When possible 32-bit PCI configuration read cycles are used to=
read=0D
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, =
8-bit=0D
+ and 16-bit PCI configuration read cycles may be used at the beginning an=
d the=0D
+ end of the range.=0D
+=0D
+ If any reserved bits in StartAddress are set, then ASSERT().=0D
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D
+ If Size > 0 and Buffer is NULL, then ASSERT().=0D
+=0D
+ @param[in] StartAddress The starting address that encodes the PCI Segm=
ent, Bus,=0D
+ Device, Function and Register.=0D
+ @param[in] Size The size in bytes of the transfer.=0D
+ @param[in] Buffer The pointer to a buffer receiving the data rea=
d.=0D
+=0D
+ @return Size=0D
+=0D
+**/=0D
+UINTN=0D
+EFIAPI=0D
+PciSegmentReadBuffer (=0D
+ IN UINT64 StartAddress,=0D
+ IN UINTN Size,=0D
+ OUT VOID *Buffer=0D
+ )=0D
+{=0D
+ UINTN ReturnValue;=0D
+=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);=0D
+ ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D
+=0D
+ if (Size =3D=3D 0) {=0D
+ return Size;=0D
+ }=0D
+=0D
+ ASSERT (Buffer !=3D NULL);=0D
+=0D
+ //=0D
+ // Save Size for return=0D
+ //=0D
+ ReturnValue =3D Size;=0D
+=0D
+ if ((StartAddress & BIT0) !=3D 0) {=0D
+ //=0D
+ // Read a byte if StartAddress is byte aligned,=0D
+ // Volatile ensure that the latest values are read every time.=0D
+ //=0D
+ *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress);=0D
+ StartAddress +=3D sizeof (UINT8);=0D
+ Size -=3D sizeof (UINT8);=0D
+ Buffer =3D (UINT8 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) {=0D
+ //=0D
+ // Read a word if StartAddress is word aligned=0D
+ //=0D
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));=0D
+ StartAddress +=3D sizeof (UINT16);=0D
+ Size -=3D sizeof (UINT16);=0D
+ Buffer =3D (UINT16 *)Buffer + 1;=0D
+ }=0D
+=0D
+ while (Size >=3D sizeof (UINT32)) {=0D
+ //=0D
+ // Read as many double words as possible=0D
+ //=0D
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));=0D
+ StartAddress +=3D sizeof (UINT32);=0D
+ Size -=3D sizeof (UINT32);=0D
+ Buffer =3D (UINT32 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT16)) {=0D
+ //=0D
+ // Read the last remaining word if exist=0D
+ //=0D
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));=0D
+ StartAddress +=3D sizeof (UINT16);=0D
+ Size -=3D sizeof (UINT16);=0D
+ Buffer =3D (UINT16 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT8)) {=0D
+ //=0D
+ // Read the last remaining byte if exist=0D
+ //=0D
+ *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress);=0D
+ }=0D
+=0D
+ return ReturnValue;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Copies the data in a caller supplied buffer to a specified range of PCI=
=0D
+ configuration space.=0D
+=0D
+ Writes the range of PCI configuration registers specified by StartAddres=
s and=0D
+ Size from the buffer specified by Buffer. This function only allows the =
PCI=0D
+ configuration registers from a single PCI function to be written. Size i=
s=0D
+ returned. When possible 32-bit PCI configuration write cycles are used t=
o=0D
+ write from StartAdress to StartAddress + Size. Due to alignment restrict=
ions,=0D
+ 8-bit and 16-bit PCI configuration write cycles may be used at the begin=
ning=0D
+ and the end of the range.=0D
+=0D
+ If any reserved bits in StartAddress are set, then ASSERT().=0D
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D
+ If Size > 0 and Buffer is NULL, then ASSERT().=0D
+=0D
+ @param[in] StartAddress The starting address that encodes the PCI Segm=
ent, Bus,=0D
+ Device, Function and Register.=0D
+ @param[in] Size The size in bytes of the transfer.=0D
+ @param[in] Buffer The pointer to a buffer containing the data to=
write.=0D
+=0D
+ @return The parameter of Size.=0D
+=0D
+**/=0D
+UINTN=0D
+EFIAPI=0D
+PciSegmentWriteBuffer (=0D
+ IN UINT64 StartAddress,=0D
+ IN UINTN Size,=0D
+ IN VOID *Buffer=0D
+ )=0D
+{=0D
+ UINTN ReturnValue;=0D
+=0D
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);=0D
+ ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D
+=0D
+ if (Size =3D=3D 0) {=0D
+ return 0;=0D
+ }=0D
+=0D
+ ASSERT (Buffer !=3D NULL);=0D
+=0D
+ //=0D
+ // Save Size for return=0D
+ //=0D
+ ReturnValue =3D Size;=0D
+=0D
+ if ((StartAddress & BIT0) !=3D 0) {=0D
+ //=0D
+ // Write a byte if StartAddress is byte aligned=0D
+ //=0D
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);=0D
+ StartAddress +=3D sizeof (UINT8);=0D
+ Size -=3D sizeof (UINT8);=0D
+ Buffer =3D (UINT8 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) {=0D
+ //=0D
+ // Write a word if StartAddress is word aligned=0D
+ //=0D
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));=0D
+ StartAddress +=3D sizeof (UINT16);=0D
+ Size -=3D sizeof (UINT16);=0D
+ Buffer =3D (UINT16 *)Buffer + 1;=0D
+ }=0D
+=0D
+ while (Size >=3D sizeof (UINT32)) {=0D
+ //=0D
+ // Write as many double words as possible=0D
+ //=0D
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));=0D
+ StartAddress +=3D sizeof (UINT32);=0D
+ Size -=3D sizeof (UINT32);=0D
+ Buffer =3D (UINT32 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT16)) {=0D
+ //=0D
+ // Write the last remaining word if exist=0D
+ //=0D
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));=0D
+ StartAddress +=3D sizeof (UINT16);=0D
+ Size -=3D sizeof (UINT16);=0D
+ Buffer =3D (UINT16 *)Buffer + 1;=0D
+ }=0D
+=0D
+ if (Size >=3D sizeof (UINT8)) {=0D
+ //=0D
+ // Write the last remaining byte if exist=0D
+ //=0D
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);=0D
+ }=0D
+=0D
+ return ReturnValue;=0D
+}=0D
--=20
2.25.1

This driver installs SMBIOS information for FT2000/4.

Signed-off-by: Ling Jia <jialing@...>
Reviewed-by: Leif Lindholm <leif@...>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 6 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in=
f | 47 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c =
| 943 ++++++++++++++++++++
4 files changed, 1002 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 6f38acb636..28e52e15e3 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -286,6 +286,12 @@
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf=0D
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe=
.inf=0D
=0D
+ #=0D
+ # SMBIOS=0D
+ #=0D
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D
+ Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.=
inf=0D
+=0D
#=0D
# Bds=0D
#=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index f435f7cb51..3106a43fb7 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -178,6 +178,12 @@ READ_LOCK_STATUS =3D TRUE
#=0D
INF ShellPkg/Application/Shell/Shell.inf=0D
=0D
+ #=0D
+ # SMBIOS=0D
+ #=0D
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D
+ INF Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform=
Dxe.inf=0D
+=0D
#=0D
# Bds=0D
#=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl=
atformDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/Smbio=
sPlatformDxe.inf
new file mode 100644
index 0000000000..69a021e048
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD=
xe.inf
@@ -0,0 +1,47 @@
+#/** @file=0D
+# This driver installs SMBIOS information for Phytium.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=

=0D

+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D SmbiosPlatformDxe=0D
+ FILE_GUID =3D d64f09f8-40dc-11eb-9be6-f7a038f956ba=
=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D SmbiosTablePublishEntry=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D AARCH64=0D
+#=0D
+[Sources]=0D
+ SmbiosPlatformDxe.c=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ IoLib=0D
+ UefiBootServicesTableLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[Guids]=0D
+ gEfiGlobalVariableGuid=0D
+=0D
+[Protocols]=0D
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED=0D
+=0D
+[Guids]=0D
+=0D
+[Depex]=0D
+ gEfiSmbiosProtocolGuid=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl=
atformDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosP=
latformDxe.c
new file mode 100644
index 0000000000..4a1f77dfb2
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD=
xe.c
@@ -0,0 +1,943 @@
+/** @file=0D
+ This driver installs SMBIOS information for Phytium Durian platforms.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+=0D
+#include <IndustryStandard/SmBios.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Platform.h>=0D
+#include <Protocol/Smbios.h>=0D
+=0D
+// SMBIOS tables often reference each other using=0D
+// fixed constants, define a list of these constants=0D
+// for our hardcoded tables=0D
+=0D
+#define TYPE0_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Vendor */ \=0D
+ "V1.0\0" /* BiosVersion */ \=0D
+ __DATE__"\0" /* BiosReleaseDate */=0D
+=0D
+#define TYPE1_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "Phytium Durian Development Platform\0" /* Product Name */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* SerialNumber */ \=0D
+ "Not set\0" /* SKUNumber */ \=0D
+ "FT-2000/4\0" /* Family */ \=0D
+=0D
+#define TYPE2_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "Phytium Durian Development Platform\0" /* Product Name */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* Serial */ \=0D
+ "Not Set\0" /* BaseBoardAssetTag */ \=0D
+ "Not Set\0" /* BaseBoardChassisLocation */=0D
+=0D
+#define TYPE3_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* Serial */ \=0D
+ "Not Set\0" /* AssetTag */=0D
+=0D
+#define TYPE4_STRINGS \=
=0D
+ "FT-2000/4\0" /* socket type */ \=
=0D
+ "PHYTIUM LTD\0" /* manufactuer */ \=
=0D
+ "FT-2000/4\0" /* processor version */ \=
=0D
+ "Not Set\0" /* SerialNumber */ \=
=0D
+ "Not Set\0" /* processor 2 description */ \=
=0D
+ "Not Set\0" /* AssetTag */=0D
+=0D
+=0D
+#define TYPE7_STRINGS \=0D
+ "L1 Instruction\0" /* L1I */ \=0D
+ "L1 Data\0" /* L1D */ \=0D
+ "L2\0" /* L2 */=0D
+=0D
+#define TYPE7_L1DATA_STRINGS \=0D
+ "L1 Data Cache\0" /* L1 data */=0D
+=0D
+=0D
+#define TYPE7_L1INS_STRINGS \=0D
+ "L1 Instruction Cache\0" /* L1 ins */=0D
+=0D
+#define TYPE7_L2_STRINGS \=0D
+ "L2 Cache\0" /* L2 */=0D
+=0D
+#define TYPE7_L3_STRINGS \=0D
+ "L3 Cache\0" /* L3 */=0D
+=0D
+=0D
+#define TYPE9_STRINGS \=0D
+ "PCIE_SLOT0\0" /* Slot0 */ \=0D
+ "PCIE_SLOT1\0" /* Slot1 */ \=0D
+ "PCIE_SLOT2\0" /* Slot2 */ \=0D
+ "PCIE_SLOT3\0" /* Slot3 */=0D
+=0D
+#define TYPE9_STRINGS_PCIE0X16 \=0D
+ "PCIE0_X16\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE0X1 \=0D
+ "PCIE0_X1\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE1X16 \=0D
+ "PCIE1_X16\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE1X1 \=0D
+ "PCIE1_X1\0"=0D
+=0D
+#define TYPE13_STRINGS \=0D
+ "en|US|iso8859-1\0" \=0D
+ "zh|CN|unicode\0"=0D
+=0D
+=0D
+#define TYPE16_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE17_STRINGS_CHANNEL0 \=0D
+ "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \=0D
+ "Bank0\0" /* bank description */ \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0"=0D
+=0D
+#define TYPE17_STRINGS_CHANNEL1 \=0D
+ "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \=0D
+ "Bank0\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0"=0D
+=0D
+=0D
+#define TYPE19_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE32_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE39_STRINGS \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/=0D
+=0D
+#define TYPE38_STRINGS \=0D
+ "\0"=0D
+=0D
+//=0D
+// Type definition and contents of the default SMBIOS table.=0D
+// This table covers only the minimum structures required by=0D
+// the SMBIOS specification (section 6.2, version 3.0)=0D
+//=0D
+#pragma pack(1)=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE0 Base;=0D
+ INT8 Strings[sizeof (TYPE0_STRINGS)];=0D
+} ARM_TYPE0;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE1 Base;=0D
+ UINT8 Strings[sizeof (TYPE1_STRINGS)];=0D
+} ARM_TYPE1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE2 Base;=0D
+ UINT8 Strings[sizeof (TYPE2_STRINGS)];=0D
+} ARM_TYPE2;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE3 Base;=0D
+ UINT8 Strings[sizeof (TYPE3_STRINGS)];=0D
+} ARM_TYPE3;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE4 Base;=0D
+ UINT8 Strings[sizeof (TYPE4_STRINGS)];=0D
+} ARM_TYPE4;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L1DATA_STRINGS)];=0D
+} ARM_TYPE7_L1DATA;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L1INS_STRINGS)];=0D
+} ARM_TYPE7_L1INS;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L2_STRINGS)];=0D
+} ARM_TYPE7_L2;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L3_STRINGS)];=0D
+} ARM_TYPE7_L3;=0D
+=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS)];=0D
+} ARM_TYPE9;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X16)];=0D
+} ARM_TYPE9_PCIE0X16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X1)];=0D
+} ARM_TYPE9_PCIE0X1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X16)];=0D
+} ARM_TYPE9_PCIE1X16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X1)];=0D
+} ARM_TYPE9_PCIE1X1;=0D
+=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE13 Base;=0D
+ UINT8 Strings[sizeof (TYPE13_STRINGS)];=0D
+} ARM_TYPE13;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE16 Base;=0D
+ UINT8 Strings[sizeof (TYPE16_STRINGS)];=0D
+} ARM_TYPE16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE17 Base;=0D
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL0)];=0D
+} ARM_TYPE17_CHANNEL0;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE17 Base;=0D
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL1)];=0D
+} ARM_TYPE17_CHANNEL1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE19 Base;=0D
+ UINT8 Strings[sizeof (TYPE19_STRINGS)];=0D
+} ARM_TYPE19;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE32 Base;=0D
+ UINT8 Strings[sizeof (TYPE32_STRINGS)];=0D
+} ARM_TYPE32;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE38 Base;=0D
+ UINT8 Strings[sizeof (TYPE38_STRINGS)];=0D
+} ARM_TYPE38;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE39 Base;=0D
+ UINT8 Strings[sizeof (TYPE39_STRINGS)];=0D
+} ARM_TYPE39;=0D
+=0D
+enum SMBIOS_REFRENCE_HANDLES {=0D
+ SMBIOS_HANDLE_L1I =3D 0x1000,=0D
+ SMBIOS_HANDLE_L1D,=0D
+ SMBIOS_HANDLE_L2,=0D
+ SMBIOS_HANDLE_L3,=0D
+ SMBIOS_HANDLE_MOTHERBOARD,=0D
+ SMBIOS_HANDLE_CHASSIS,=0D
+ SMBIOS_HANDLE_CLUSTER,=0D
+ SMBIOS_HANDLE_MEMORY,=0D
+ SMBIOS_HANDLE_DIMM_0,=0D
+ SMBIOS_HANDLE_DIMM_1=0D
+};=0D
+=0D
+#define SERIAL_LEN 10 //this must be less than the buffer len allocated i=
n the type1 structure=0D
+=0D
+#pragma pack()=0D
+=0D
+//BIOS Information (Type 0)=0D
+ARM_TYPE0 BiosInfo_Type0 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1, //Vendor=0D
+ 2, //BiosVersion=0D
+ 0x8800, //BiosSegment=0D
+ 3, //BiosReleaseDate=0D
+ 0xFF, //BiosSize=0D
+ { //BiosCharacteristics=0D
+ 0, // Reserved =
:2=0D
+ 0, // Unknown =
:1=0D
+ 0, // BiosCharacteristicsN=
otSupported :1=0D
+ 0, // IsaIsSupported =
:1=0D
+ 0, // McaIsSupported =
:1=0D
+ 0, // EisaIsSupported =
:1=0D
+ 1, // PciIsSupported =
:1=0D
+ 0, // PcmciaIsSupported =
:1=0D
+ 0, // PlugAndPlayIsSupport=
ed :1=0D
+ 0, // ApmIsSupported =
:1=0D
+ 1, // BiosIsUpgradable =
:1=0D
+ 0, // BiosShadowingAllowed=
:1=0D
+ 0, // VlVesaIsSupported =
:1=0D
+ 0, // EscdSupportIsAvailab=
le :1=0D
+ 1, // BootFromCdIsSupporte=
d :1=0D
+ 1, // SelectableBootIsSupp=
orted :1=0D
+ 0, // RomBiosIsSocketed =
:1=0D
+ 0, // BootFromPcmciaIsSupp=
orted :1=0D
+ 0, // EDDSpecificationIsSu=
pported :1=0D
+ 0, // JapaneseNecFloppyIsS=
upported :1=0D
+ 0, // JapaneseToshibaFlopp=
yIsSupported :1=0D
+ 0, // Floppy525_360IsSuppo=
rted :1=0D
+ 0, // Floppy525_12IsSuppor=
ted :1=0D
+ 0, // Floppy35_720IsSuppor=
ted :1=0D
+ 0, // Floppy35_288IsSuppor=
ted :1=0D
+ 0, // PrintScreenIsSupport=
ed :1=0D
+ 0, // Keyboard8042IsSuppor=
ted :1=0D
+ 0, // SerialIsSupported =
:1=0D
+ 0, // PrinterIsSupported =
:1=0D
+ 0, // CgaMonoIsSupported =
:1=0D
+ 0, // NecPc98 =
:1=0D
+ 0 // ReservedForVendor =
:3=0D
+ },=0D
+ {=0D
+ 0x03, //BIOSCharacteristicsEx=
tensionBytes[0]=0D
+ 0x0D //BIOSCharacteristicsEx=
tensionBytes[1]=0D
+ },=0D
+ 0xFF, //SystemBiosMajorReleas=
e;=0D
+ 0xFF, //SystemBiosMinorReleas=
e;=0D
+ 0xFF, //EmbeddedControllerFir=
mwareMajorRelease;=0D
+ 0xFF, //EmbeddedControllerFir=
mwareMinorRelease;=0D
+ },=0D
+ TYPE0_STRINGS=0D
+};=0D
+=0D
+//System Information (Type 1).=0D
+ARM_TYPE1 SystemInfo_Type1 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED // Handle=0D
+ },=0D
+ 1, // Manufacturer=0D
+ 2, // ProductName=0D
+ 3, // Version=0D
+ 4, // SerialNumber=0D
+ { // Uuid=0D
+ 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa,=
0xbb, 0xcc}=0D
+ },=0D
+ SystemWakeupTypePowerSwitch, // SystemWakeupType=
=0D
+ 5, // SKUNumber,=0D
+ 6 // Family=0D
+ },=0D
+ TYPE1_STRINGS=0D
+};=0D
+=0D
+//Base Board (or Module) Information (Type 2)=0D
+ARM_TYPE2 BaseboardInfo_Type2 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Len=
gth=0D
+ SMBIOS_HANDLE_MOTHERBOARD // Handle=0D
+ },=0D
+ 1, // BaseBoard=
Manufacturer=0D
+ 2, // BaseBoard=
ProductName=0D
+ 3, // BaseBoard=
Version=0D
+ 4, // BaseBoard=
SerialNumber=0D
+ 5, // BaseBoard=
AssetTag=0D
+ { // FeatureFl=
ag=0D
+ 1, // Motherboa=
rd :1=0D
+ 0, // RequiresD=
aughterCard :1=0D
+ 0, // Removable=
:1=0D
+ 1, // Replaceab=
le :1=0D
+ 0, // HotSwappa=
ble :1=0D
+ 0 // Reserved =
:3=0D
+ },=0D
+ 6, // BaseBoard=
ChassisLocation=0D
+ 0, // ChassisHa=
ndle;=0D
+ BaseBoardTypeMotherBoard, // BoardType=
;=0D
+ 0, // NumberOfC=
ontainedObjectHandles;=0D
+ {=0D
+ 0=0D
+ } // Contained=
ObjectHandles[1];=0D
+ },=0D
+ TYPE2_STRINGS=0D
+};=0D
+=0D
+//System Enclosure or Chassis (Type 3)=0D
+ARM_TYPE3 SystemEnclosure_Type3 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Len=
gth=0D
+ SMBIOS_HANDLE_CHASSIS // Handle=0D
+ },=0D
+ 1, // Manufactr=
urer=0D
+ MiscChassisTypeMainServerChassis, // Type=0D
+ 2, // Version=0D
+ 3, // SerialNum=
ber=0D
+ 4, // AssetTag=
=0D
+ ChassisStateSafe, // BootupSta=
te=0D
+ ChassisStateSafe, // PowerSupp=
lyState=0D
+ ChassisStateSafe, // ThermalSt=
ate=0D
+ ChassisSecurityStatusNone, // SecurityS=
tate=0D
+ {=0D
+ 0, // OemDefine=
d[0]=0D
+ 0, // OemDefine=
d[1]=0D
+ 0, // OemDefine=
d[2]=0D
+ 0 // OemDefine=
d[3]=0D
+ },=0D
+ 2, // Height=0D
+ 1, // NumberofP=
owerCords=0D
+ 0, // Contained=
ElementCount=0D
+ 0, // Contained=
ElementRecordLength=0D
+ { // Contained=
Elements[0]=0D
+ {=0D
+ 0, // Contained=
ElementType=0D
+ 0, // Contained=
ElementMinimum=0D
+ 0 // Contained=
ElementMaximum=0D
+ }=0D
+ }=0D
+ },=0D
+ TYPE3_STRINGS=0D
+};=0D
+=0D
+//Processor Infomation (Type 4)=0D
+ARM_TYPE4 ProcessorInfo_Type4 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE4), //Length=0D
+ SMBIOS_HANDLE_CLUSTER //Handle=0D
+ },=0D
+ 1, //Socket=0D
+ CentralProcessor, //ProcessorType=0D
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily=0D
+ 2, //ProcessorManufacture=0D
+ { //ProcessorId=0D
+ { //Signature=0D
+ 0=0D
+ },=0D
+ { //FeatureFlags=0D
+ 0=0D
+ }=0D
+ },=0D
+ 3, //ProcessorVersion=0D
+ { //Voltage=0D
+ 0, 0, 0, 1, 0, 1=0D
+ },=0D
+ 1, //ExternalClock=0D
+ 1, //MaxSpeed=0D
+ 0, //CurrentSpeed=0D
+ 0x41, //Status=0D
+ ProcessorUpgradeUnknown, //ProcessorUpgrade=0D
+ SMBIOS_HANDLE_L1D, //L1Ins=0D
+ SMBIOS_HANDLE_L2, //L1Data=0D
+ SMBIOS_HANDLE_L3, //L2=0D
+ 4, //SerialNumber=0D
+ 5, //AssetTag=0D
+ 6, //PartNumber=0D
+=0D
+ 4, //CoreCount=0D
+ 0, //EnabledCoreCount=0D
+ 0, //ThreadCount=0D
+ 0x00EC, //ProcessorCharacteristics=
=0D
+=0D
+ ProcessorFamilyARMv8, //ProcessorFamily2=0D
+=0D
+ 0, //CoreCount2=0D
+ 0, //EnabledCoreCount2=0D
+ 0 //ThreadCount2=0D
+ },=0D
+ TYPE4_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L1 DATA=0D
+ARM_TYPE7_L1DATA L1Data_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L1D //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0180, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeData, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 128,=0D
+ 128=0D
+ },=0D
+ TYPE7_L1DATA_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L1 INS=0D
+ARM_TYPE7_L1INS L1Ins_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L1I //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0180, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorParity, //ErrorCorrectionType=
=0D
+ CacheTypeInstruction, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 128,=0D
+ 128=0D
+ },=0D
+ TYPE7_L1INS_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L2=0D
+ARM_TYPE7_L2 L2_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L2 //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0281, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeUnified, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 4096,=0D
+ 4096=0D
+ },=0D
+ TYPE7_L2_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L3=0D
+ARM_TYPE7_L3 L3_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L3 //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0281, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeUnified, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 4096,=0D
+ 4096=0D
+ },=0D
+ TYPE7_L3_STRINGS=0D
+};=0D
+=0D
+//PCIE0_X16 (Type 9)=0D
+ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth16X,=0D
+ SlotUsageInUse,=0D
+ SlotLengthLong,=0D
+ 0,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE0X16=0D
+};=0D
+=0D
+//PCIE0_X1 (Type 9)=0D
+ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth1X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthShort,=0D
+ 1,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE0X1=0D
+};=0D
+=0D
+//PCIE1_X16 (Type 9)=0D
+ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth16X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthLong,=0D
+ 2,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE1X16=0D
+};=0D
+=0D
+//PCIE1_X1 (Type 9)=0D
+ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth1X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthShort,=0D
+ 3,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE1X1=0D
+};=0D
+=0D
+//Bios Language Information (Type13)=0D
+ARM_TYPE13 BiosLangInfo_Type13 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 2,=0D
+ 0,=0D
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},=0D
+ 2=0D
+ },=0D
+ TYPE13_STRINGS=0D
+};=0D
+=0D
+//Physical Memory Array (Type 16)=0D
+ARM_TYPE16 MemArray_Type16 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length=0D
+ SMBIOS_HANDLE_MEMORY=0D
+ },=0D
+ MemoryArrayLocationSystemBoard,=0D
+ MemoryArrayUseSystemMemory,=0D
+ MemoryErrorCorrectionNone,=0D
+ 0x1000000, //16G=0D
+ 0xFFFE,=0D
+ 2=0D
+ },=0D
+ TYPE16_STRINGS=0D
+};=0D
+=0D
+//Memory Device (Type17)=0D
+ARM_TYPE17_CHANNEL0 MemDev_Type17_0 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length=0D
+ SMBIOS_HANDLE_DIMM_0=0D
+ },=0D
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs=0D
+ 0xFFFE, //no errors=0D
+ 64, //single DIMM, no ECC is 64bits (for ecc this wo=
uld be 72)=0D
+ 64, //data width of this device (64-bits)=0D
+ 0x4000, //16GB=0D
+ 0x09, //FormFactor=0D
+ 0, //not part of a set=0D
+ 1, //right side of board=0D
+ 2, //bank 0=0D
+ MemoryTypeDdr4, //LP DDR4=0D
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered=0D
+ 2400, //2400Mhz DDR=0D
+ 3, //Manufacturer=0D
+ 4, //serial=0D
+ 5, //asset tag=0D
+ 6, //part number=0D
+ 0, //attrbute=0D
+ 0x2000, // 8G=0D
+ 2400, //2400MHz=0D
+ 1500, //Max V=0D
+ 1500, //Max V=0D
+ 1500, //Configure V=0D
+ },=0D
+ TYPE17_STRINGS_CHANNEL0=0D
+};=0D
+=0D
+//Memory Device (Type17)=0D
+ARM_TYPE17_CHANNEL1 MemDev_Type17_1 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length=0D
+ SMBIOS_HANDLE_DIMM_1=0D
+ },=0D
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs=0D
+ 0xFFFE, //no errors=0D
+ 64, //single DIMM, no ECC is 64bits (for ecc this wo=
uld be 72)=0D
+ 64, //data width of this device (64-bits)=0D
+ 0x2000, //8GB=0D
+ 0x09, //FormFactor=0D
+ 0, //not part of a set=0D
+ 1, //right side of board=0D
+ 2, //bank 0=0D
+ MemoryTypeDdr4, //LP DDR4=0D
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered=0D
+ 2400, //2400Mhz DDR=0D
+ 3, //varies between diffrent production runs=0D
+ 4, //serial=0D
+ 5, //asset tag=0D
+ 6, //part number=0D
+ 0, //attrbute=0D
+ 0x4000, // 16G=0D
+ 2400, //2400MHz=0D
+ 1500, //Max V=0D
+ 1500, //Max V=0D
+ 1500, //Configure V=0D
+ },=0D
+ TYPE17_STRINGS_CHANNEL1=0D
+};=0D
+=0D
+//Memory Array Mapped Address (Type 19)=0D
+ARM_TYPE19 MemArrayMapAddr_Type19 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 0,=0D
+ 0x1000000, //16G=0D
+ SMBIOS_HANDLE_MEMORY, //handle=0D
+ 2,=0D
+ 0, //starting addr of first 2GB=0D
+ 0, //ending addr of first 2GB=0D
+ },=0D
+ TYPE19_STRINGS=0D
+};=0D
+=0D
+//System Boot Information (Type 32)=0D
+ARM_TYPE32 SystemBoot_Type32 =3D {=0D
+ {=0D
+ {=0D
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ { // Reserved[6]=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0=0D
+ },=0D
+ BootInformationStatusNoError // BootInformationSta=
tus=0D
+ },=0D
+ TYPE32_STRINGS=0D
+};=0D
+=0D
+VOID *DefaultCommonTables[]=3D=0D
+{=0D
+ &BiosInfo_Type0,=0D
+ &SystemInfo_Type1,=0D
+ &BaseboardInfo_Type2,=0D
+ &SystemEnclosure_Type3,=0D
+ &ProcessorInfo_Type4,=0D
+ &L1Data_Type7,=0D
+ &L1Ins_Type7,=0D
+ &L2_Type7,=0D
+ &L3_Type7,=0D
+ &Pcie0X16_Type9,=0D
+ &Pcie0X1_Type9,=0D
+ &Pcie1X16_Type9,=0D
+ &Pcie1X1_Type9,=0D
+ &MemArray_Type16,=0D
+ &MemDev_Type17_0,=0D
+ &MemDev_Type17_1,=0D
+ &MemArrayMapAddr_Type19,=0D
+ &BiosLangInfo_Type13,=0D
+ &SystemBoot_Type32,=0D
+ NULL=0D
+};=0D
+=0D
+=0D
+/**=0D
+ Installed a whole table worth of structructures.=0D
+=0D
+ @param[in] Smbios The Pointer of Smbios Protocol.=0D
+=0D
+ @retval EFI_SUCCESS Table data successfully installed.=0D
+ @retval Other Table data was not installed.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+InstallStructures (=0D
+ IN EFI_SMBIOS_PROTOCOL *Smbios,=0D
+ IN VOID *DefaultTables[]=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_SMBIOS_HANDLE SmbiosHandle;=0D
+ UINT32 TableEntry;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ for ( TableEntry =3D0; DefaultTables[TableEntry] !=3D NULL; TableEntry++=
)=0D
+ {=0D
+ SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry]=
)->Handle;=0D
+ Status =3D Smbios->Add (=0D
+ Smbios,=0D
+ NULL,=0D
+ &SmbiosHandle,=0D
+ (EFI_SMBIOS_TABLE_HEADER *) DefaultTables[TableEntry]=0D
+ );=0D
+ if (EFI_ERROR (Status))=0D
+ break;=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Installed All SMBIOS information.=0D
+=0D
+ @param[in] Smbios The Pointer of Smbios Protocol.=0D
+=0D
+ @retval EFI_SUCCESS SMBIOS information successfully installed.=0D
+ @retval Other SMBIOS information was not installed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+InstallAllStructures (=0D
+ IN EFI_SMBIOS_PROTOCOL *Smbios=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ Status =3D InstallStructures (Smbios, DefaultCommonTables);=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Find the smbios protocol and installed SMBIOS information=0D
+ for ARM platforms.=0D
+=0D
+ @param[in] ImageHandle Module's image handle.=0D
+ @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE.=0D
+=0D
+ @retval EFI_SUCCESS Smbios data successfully installed.=0D
+ @retval Other Smbios data was not installed.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SmbiosTablePublishEntry (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_SMBIOS_PROTOCOL *Smbios;=0D
+=0D
+ //=0D
+ // Find the SMBIOS protocol=0D
+ //=0D
+ Status =3D gBS->LocateProtocol (=0D
+ &gEfiSmbiosProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&Smbios=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D InstallAllStructures (Smbios);=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.25.1