Date   

Re: GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

Nate DeSimone
 

Hi Pedro,

 

Great to meet you and welcome to the TianoCore project! Glad you hear you are interested! A MinPlatform board port can go in two wildly different directions, depending on the answer to one question: Does MinPlatform currently have support for the Processor/Chipset/SoC used by the motherboard?

 

If yes, then building the new board port only needs to focus on the things that change between each motherboard. For a good example of that of what to expect to be different between motherboards, take a look at the differences between https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp and https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme.

 

A few things stick out:

 

  1. The WhiskeyLakeURvp has DIMM slots for its DRAM, whereas the UpXtreme board has soldered down DRAM. This changes the methodology for getting the SPD Data (https://en.wikipedia.org/wiki/Serial_presence_detect). For DRAM in DIMM slots, one must read the SPD data by sending read commands over the SMBus (https://en.wikipedia.org/wiki/System_Management_Bus). Each physical DIMM slot will have a different SMBus address where the SPD chip is located, and different motherboards use different addresses. Building the new board port requires the implementer to know what SMBus addresses to use. For an example of this, see the following snippet from https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c:

    PcdSet32S (PcdMrcSpdData, 0);
    PcdSet16S (PcdMrcSpdDataSize, 0);
    PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
    PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
    PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
    PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);

    For soldered down DRAM, typically there is no SPD chip. So the MinPlatform board code needs to carry a copy of the SPD data for the DRAM. That creates the problem that different DRAM vendors need different SPD data, and the motherboard manufacturer will often need to purchase DRAM from more than one memory vendor. To address this, the board code needs some way to detect which memory vendor was used on the current board and choose the correct SPD data. The UpXtreme board port gives a good example of this. Here is the same snippet of code from https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaInitPreMemLib.c:

    BomId = PcdGet8(PcdBoardBomId);
    DEBUG ((DEBUG_INFO"Up Xtreme Bom ID 0x%x\n",BomId));
    if ((BomId & BIT1) == BIT1) {
      
    PcdSet32S (PcdMrcSpdData, (UINTNmUpXtremeSamsungDdr4Spd);
      
    PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSamsungDdr4SpdSize);
      
    DEBUG ((DEBUG_INFO"Using Xtreme SPD Samsung Ddr4\n"));
    else {
      
    PcdSet32S (PcdMrcSpdData, (UINTNmUpXtremeSkhynixDdr4Spd);
      
    PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSkhynixDdr4SpdSize);
      
    DEBUG ((DEBUG_INFO"Using Xtreme SPD Skhynix Ddr4\n"));
    }
    PcdSet8S (PcdMrcSpdAddressTable0, 0);
    PcdSet8S (PcdMrcSpdAddressTable1, 0);
    PcdSet8S (PcdMrcSpdAddressTable2, 0);
    PcdSet8S (PcdMrcSpdAddressTable3, 0);

    In this case, the SMBus addresses are set to zero and the SPD data is provided directly. The board code chooses between the different SPD data payloads based on a BOM (Bill of Materials) identifier. For the UpXtreme, the BomId is initialized by reading the value of 6 GPIO pins and constructing an integer, see https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeDetect.c:

    // Sample the GPIO pin level
    for (Index = 0Index < NumberOfGpiosIndex++) {
      
    Status = GpioGetInputValue (mUpxGpioBomPad[Index], &GpioData);
      
    if (EFI_ERROR(Status)) {
        
    break;
      }
      
    BomId = (BomId << 1) + (GpioData & 1);
    }
    if (Index == NumberOfGpios) {
      
    PcdSet8S(PcdBoardBomId, BomId);
    }

  2. The usage of the GPIO pins provided by the chipset will often vary between motherboard designs. This requires board code to initialize the pins differently. Usually this is done by writing a table describing the GPIO usage for the board. For an example of different GPIO tables for each board, see https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c and https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableUpXtreme.c.

  3. One of the uses of GPIO pins is to provide interrupt signaling, the different GPIO tables will also result in the need for different interrupt routing. This requires the GPIO pins that are used for interrupts to be programmed correctly. And the interrupt routing needs to be reflected in the FADT and MADT ACPI tables. MinPlatformPkg contains the code to generate these ACPI tables based on PCD values: https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c. But the PCD values may need to be adjusted.

  4. The policy data provided to the FSP needs to be adjusted according to the board design. Motherboards will have different configurations for the number of PCIe/USB/SATA ports provided. Intel chipsets have a design called “Flex I/O Architecture” (FIA). FIA allows a single HSIO (High Speed I/O) lane to behave as either a USB, PCIe, or SATA lane. Note that a lane in a combination of two pins; two pins are needed for differential voltage signaling. The FIA configuration varies between motherboards, so the configuration needs to be reflected in the FSP input values.

 

The following Processor/Chipset/SoC are currently supported by MinPlatform, so this type of project would need to choose a motherboard designed for one of these:

 

  • Kaby Lake
  • Whiskey Lake
  • Comet Lake
  • Tiger Lake

 

If MinPlatform currently does NOT support for the Processor/Chipset/SoC used by the motherboard, then a new *OpenBoardPkg will need to be constructed. For the purposes of a GSoC project, I would not recommend attempting this unless the code for the Processor/Chipset/SoC and motherboard already exists somewhere else in TianoCore. Raspberry Pi and Qemu are good examples where this scenario exists, as we already have code to support both of those targets. In that case, Creating the OpenBoardPkg would be an exercise in adapting that existing code to the MinPlatform architecture: https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/2_architecture/#2-architecture.

 

MinPlatform is designed to limit the amount of EFI firmware internals you need in order to implement a MinPlatform board port. In general, we try to create generic code that provides those details whenever possible and limit the implementation work to purely the changes needed to get a new motherboard working.

 

The ACPICA tools are currently only used during the build process to compile the firmware image. They are not executable as UEFI pre-OS applications, which could be useful in some cases. For example, dumping a disassembly of the ACPI code to the UEFI shell might be a useful debugging tool in some cases.

 

To my knowledge, I don’t believe anyone has worked on the ext2 driver since GSoC 2011. While some progress was made during GSoC 2011, it was not completed. The code from that project is available here: https://github.com/GunioRobot/Ext2Pkg At this point, the filesystem driver would probably need to support ext4 to be really useful. I haven’t done a detailed investigation on how much work that would be. Honestly it should like you might have a better idea of it than I do 😊.

 

Sorry for the long email, but I hope it helps. Finally I'd like to reiterate... Welcome to the project!

 

With Best Regards,

Nate

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Pedro Falcato
Sent: Friday, March 12, 2021 5:08 AM
To: devel@edk2.groups.io
Subject: [edk2-devel] GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

 

Hi everyone!

 

I'm Pedro Falcato, a student from FCT Nova in Lisbon, Portugal. I've gotten a bunch of experience over the years with C/C++, x86 in general and UEFI/ACPI with my hobby OS/kernel development, and I've got to say, I'm quite interested in some of the projects you've got here.

 

So, a few questions:

 

1) What entails building a MinPlatform board port for any board whatsoever? I've seen Kaaira wants to do the Qemu port, I would love to do something like that but for the RPi or some real motherboard, but I fear it might be too difficult?

 

2) How much knowledge of EFI firmware internals do you need? With my EFI bootloader development over the years I already have a firm hand on how the external-facing API looks like, but I have to say I haven't really read the parts of the spec that describe the driver and internal APIs, so to speak.

 

3) Isn't there already an ACPICA port for UEFI environments? What stops us from going one step further and also build the rest of the "user-space" utilities?

 

4) How's the status of the ext2 driver? How different do Tianocore filesystem implementations look from the standard-ish kernel interfaces you can see in Linux, *BSD, etc? I'm also quite interested in this one because I've written a read/write ext2 driver before, so the concepts are kind-of fresh in my head.

 

I hope you folks can answer my questions so I can figure out what project I want to work on! :)

 

Looking forward to working in Tianocore!

 

Thanks,

Pedro Falcato


[PATCH v2 1/1] CryptoPkg: Added CC flags for ARM on IntrinsicLib

Matthew Carlson
 

From: Matthew Carlson <macarl@microsoft.com>

Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>

This added the compiler flags that were already defined for X64 and IA32.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821
Ref: https://github.com/tianocore/edk2/pull/1493

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io
---
CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)

diff --git a/CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf b/CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
index fcbb93316cf7..21a0dede77fe 100644
--- a/CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+++ b/CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
@@ -64,4 +64,6 @@
MSFT:RELEASE_*_IA32_CC_FLAGS == /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /FIAutoGen.h /EHs-c- /GR- /GF
MSFT:DEBUG_*_X64_CC_FLAGS == /nologo /c /WX /GS- /X /W4 /Gs32768 /D UNICODE /O1b2s /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm
MSFT:RELEASE_*_X64_CC_FLAGS == /nologo /c /WX /GS- /X /W4 /Gs32768 /D UNICODE /O1b2s /Gy /FIAutoGen.h /EHs-c- /GR- /GF
+ MSFT:DEBUG_*_AARCH64_CC_FLAGS == /nologo /c /WX /GS- /X /W4 /Gs32768 /D UNICODE /O1b2s /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm
+ MSFT:RELEASE_*_AARCH64_CC_FLAGS == /nologo /c /WX /GS- /X /W4 /Gs32768 /D UNICODE /O1b2s /Gy /FIAutoGen.h /EHs-c- /GR- /GF
INTEL:*_*_*_CC_FLAGS = /Oi-
--
2.30.1.windows.1


[PATCH v2 0/1] CryptoPkg: Add flags for IntrinsicLib

Matthew Carlson
 

Small patch series that fixes a bugzilla.

V2: Actually added the patch information.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io

Matthew Carlson (1):
CryptoPkg: Added CC flags for ARM on IntrinsicLib

CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)

--
2.30.1.windows.1


Re: [PATCH v1 1/1] CryptoPkg: Added CC flags for ARM on IntrinsicLib

Yao, Jiewen
 

May I know where the patch is?

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Matthew
Carlson
Sent: Tuesday, March 16, 2021 5:09 AM
To: devel@edk2.groups.io
Cc: Matthew Carlson <macarl@microsoft.com>; Matthew Carlson
<matthewfcarlson@gmail.com>; Yao, Jiewen <jiewen.yao@intel.com>; Wang,
Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX <xiaoyux.lu@intel.com>; Jiang,
Guomin <guomin.jiang@intel.com>
Subject: [edk2-devel] [PATCH v1 1/1] CryptoPkg: Added CC flags for ARM on
IntrinsicLib

From: Matthew Carlson <macarl@microsoft.com>

Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>

This added the compiler flags that were already defined for X64 and IA32.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821
Ref: https://github.com/tianocore/edk2/pull/1493

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io
---
CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)





[PATCH v1 1/1] CryptoPkg: Added CC flags for ARM on IntrinsicLib

Matthew Carlson
 

From: Matthew Carlson <macarl@microsoft.com>

Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>

This added the compiler flags that were already defined for X64 and IA32.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821
Ref: https://github.com/tianocore/edk2/pull/1493

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io
---
CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)


[PATCH v1 0/1] CryptoPkg: Add flags for IntrinsicLib

Matthew Carlson
 

Small patch series that fixes a bugzilla.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io

Matthew Carlson (1):
CryptoPkg: Added CC flags for ARM on IntrinsicLib

CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)

--
2.30.1.windows.1


[PATCH v1 1/1] CryptoPkg: Added CC flags for ARM on IntrinsicLib

Matthew Carlson
 

From: Matthew Carlson <macarl@microsoft.com>

Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>

This added the compiler flags that were already defined for X64 and IA32.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821
Ref: https://github.com/tianocore/edk2/pull/1493

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io
---
CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)


[PATCH v1 0/1] CryptoPkg: Add flags for IntrinsicLib

Matthew Carlson
 

Small patch series that fixes a bugzilla.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2821

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: devel@edk2.groups.io

Matthew Carlson (1):
CryptoPkg: Added CC flags for ARM on IntrinsicLib

CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf | 2 ++
1 file changed, 2 insertions(+)

--
2.30.1.windows.1


[PATCH 5/5] StandaloneMmPkg: build for 32bit arm machines

Etienne Carriere
 

This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side directory
for several components: StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
StandaloneMmPkg/Core/StandaloneMmCore.inf | 2 +-
.../StandaloneMmCpu/{AArch64 => }/EventHandle.c | 12 ++++++++++--
.../{AArch64 => }/StandaloneMmCpu.c | 2 +-
.../{AArch64 => }/StandaloneMmCpu.h | 0
.../{AArch64 => }/StandaloneMmCpu.inf | 0
.../StandaloneMmCoreEntryPoint.h | 0
.../{AArch64 => Arm}/CreateHobList.c | 2 +-
.../{AArch64 => Arm}/SetPermissions.c | 2 +-
.../StandaloneMmCoreEntryPoint.c | 16 ++++++++--------
.../StandaloneMmCoreEntryPoint.inf | 14 +++++++-------
.../{AArch64 => Arm}/StandaloneMmCoreHobLib.c | 0
.../StandaloneMmCoreHobLibInternal.c | 0
.../StandaloneMmCoreHobLib.inf | 8 ++++----
...nternal.c => ArmStandaloneMmMemLibInternal.c} | 9 ++++++++-
.../StandaloneMmMemLib/StandaloneMmMemLib.inf | 6 +++---
.../VariableMmDependency.inf | 2 +-
StandaloneMmPkg/StandaloneMmPkg.dsc | 8 ++++----
17 files changed, 49 insertions(+), 34 deletions(-)
rename StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c (92%)
rename StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c (96%)
rename StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h (100%)
rename StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf (100%)
rename StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h (100%)
rename StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/CreateHobList.c (97%)
rename StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/SetPermissions.c (96%)
rename StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.c (94%)
rename StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLib.c (100%)
rename StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => Arm}/StandaloneMmCoreHobLibInternal.c (100%)
rename StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c => ArmStandaloneMmMemLibInternal.c} (86%)

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
PI_SPECIFICATION_VERSION = 0x00010032
ENTRY_POINT = StandaloneMmMain

-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM

[Sources]
StandaloneMmCore.c
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 92%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..2d7fd81133 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@

Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2021, Linaro Limited

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -27,6 +28,13 @@

#include "StandaloneMmCpu.h"

+#ifdef MDE_CPU_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#endif
+
EFI_STATUS
EFIAPI
MmFoundationEntryRegister (
@@ -92,8 +100,8 @@ PiMmStandaloneArmTfCpuDriverEntry (
// receipt of a synchronous MM request. Use the Event ID to distinguish
// between synchronous and asynchronous events.
//
- if ((ARM_SMC_ID_MM_COMMUNICATE_AARCH64 != EventId) &&
- (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 != EventId)) {
+ if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
+ (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId)) {
DEBUG ((DEBUG_INFO, "UnRecognized Event - 0x%x\n", EventId));
return EFI_INVALID_PARAMETER;
}
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
similarity index 96%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index d4590bcd19..10097f792f 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -10,7 +10,7 @@

#include <Base.h>
#include <Pi/PiMmCis.h>
-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/DebugLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/ArmLib.h>
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
similarity index 100%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.h
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.h
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
similarity index 100%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf
diff --git a/StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
similarity index 100%
rename from StandaloneMmPkg/Include/Library/AArch64/StandaloneMmCoreEntryPoint.h
rename to StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
similarity index 97%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
index 4d4cf3d5ff..85f8194687 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
similarity index 96%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
index 4a380df4a6..cd4b90823e 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/SetPermissions.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/SetPermissions.c
@@ -14,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/MmramMemoryReserve.h>
#include <Guid/MpInformation.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmSvcLib.h>
#include <Library/DebugLib.h>
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
similarity index 94%
rename from StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
index b445d6942e..e199e81bbd 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/StandaloneMmCoreEntryPoint.c
@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

#include <PiMm.h>

-#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>
+#include <Library/Arm/StandaloneMmCoreEntryPoint.h>

#include <PiPei.h>
#include <Guid/MmramMemoryReserve.h>
@@ -182,13 +182,13 @@ DelegatedEventLoop (
}

if (FfaEnabled) {
- EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
EventCompleteSvcArgs->Arg1 = 0;
EventCompleteSvcArgs->Arg2 = 0;
- EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg4 = SvcStatus;
} else {
- EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ EventCompleteSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
EventCompleteSvcArgs->Arg1 = SvcStatus;
}
}
@@ -273,13 +273,13 @@ InitArmSvcArgs (
)
{
if (FeaturePcdGet (PcdFfaEnable)) {
- InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP;
InitMmFoundationSvcArgs->Arg1 = 0;
InitMmFoundationSvcArgs->Arg2 = 0;
- InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg3 = ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg4 = *Ret;
} else {
- InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64;
+ InitMmFoundationSvcArgs->Arg0 = ARM_SVC_ID_SP_EVENT_COMPLETE;
InitMmFoundationSvcArgs->Arg1 = *Ret;
}
}
@@ -395,7 +395,7 @@ _ModuleEntryPoint (
//
ProcessModuleEntryPointList (HobStart);

- DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP 0x%lx\n", (UINT64) CpuDriverEntryPoint));
+ DEBUG ((DEBUG_INFO, "Shared Cpu Driver EP %p\n", (void *) CpuDriverEntryPoint));

finish:
if (Status == RETURN_UNSUPPORTED) {
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
index 4fa426f58e..1762586cfa 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
@@ -21,10 +21,10 @@
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
#

-[Sources.AARCH64]
- AArch64/StandaloneMmCoreEntryPoint.c
- AArch64/SetPermissions.c
- AArch64/CreateHobList.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreEntryPoint.c
+ Arm/SetPermissions.c
+ Arm/CreateHobList.c

[Sources.X64]
X64/StandaloneMmCoreEntryPoint.c
@@ -34,14 +34,14 @@
MdeModulePkg/MdeModulePkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec

-[Packages.AARCH64]
+[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec

[LibraryClasses]
BaseLib
DebugLib

-[LibraryClasses.AARCH64]
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
StandaloneMmMmuLib
ArmSvcLib

@@ -51,7 +51,7 @@
gEfiStandaloneMmNonSecureBufferGuid
gEfiArmTfCpuDriverEpDescriptorGuid

-[FeaturePcd.AARCH64]
+[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable

[BuildOptions]
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
similarity index 100%
rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLib.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLib.c
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
similarity index 100%
rename from StandaloneMmPkg/Library/StandaloneMmCoreHobLib/AArch64/StandaloneMmCoreHobLibInternal.c
rename to StandaloneMmPkg/Library/StandaloneMmCoreHobLib/Arm/StandaloneMmCoreHobLibInternal.c
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
index a2559920e8..34ed536480 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf
@@ -22,7 +22,7 @@
LIBRARY_CLASS = HobLib|MM_CORE_STANDALONE

#
-# VALID_ARCHITECTURES = X64 AARCH64
+# VALID_ARCHITECTURES = X64 AARCH64 ARM
#
[Sources.common]
Common.c
@@ -30,9 +30,9 @@
[Sources.X64]
X64/StandaloneMmCoreHobLib.c

-[Sources.AARCH64]
- AArch64/StandaloneMmCoreHobLib.c
- AArch64/StandaloneMmCoreHobLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ Arm/StandaloneMmCoreHobLib.c
+ Arm/StandaloneMmCoreHobLibInternal.c

[Packages]
MdePkg/MdePkg.dec
diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
similarity index 86%
rename from StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
rename to StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
index 4124959e04..c430f4baa0 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/AArch64/StandaloneMmMemLibInternal.c
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/ArmStandaloneMmMemLibInternal.c
@@ -20,6 +20,13 @@
//
extern EFI_PHYSICAL_ADDRESS mMmMemLibInternalMaximumSupportAddress;

+#ifdef MDE_CPU_AARCH64
+#define ARM_PHYSICAL_ADDRESS_BITS 36
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_PHYSICAL_ADDRESS_BITS 32
+#endif
+
/**
Calculate and save the maximum support address.

@@ -31,7 +38,7 @@ MmMemLibInternalCalculateMaximumSupportAddress (
{
UINT8 PhysicalAddressBits;

- PhysicalAddressBits = 36;
+ PhysicalAddressBits = ARM_PHYSICAL_ADDRESS_BITS;

//
// Save the maximum support address in one global variable
diff --git a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
index 062b0d7a11..b29d97a746 100644
--- a/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
+++ b/StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf
@@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 AARCH64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64 ARM
#

[Sources.Common]
@@ -37,8 +37,8 @@
[Sources.IA32, Sources.X64]
X86StandaloneMmMemLibInternal.c

-[Sources.AARCH64]
- AArch64/StandaloneMmMemLibInternal.c
+[Sources.AARCH64, Sources.ARM]
+ ArmStandaloneMmMemLibInternal.c

[Packages]
MdePkg/MdePkg.dec
diff --git a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
index a2a059c5d6..ffb2a6d083 100644
--- a/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
+++ b/StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf
@@ -20,7 +20,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = AARCH64
+# VALID_ARCHITECTURES = AARCH64|ARM
#
#

diff --git a/StandaloneMmPkg/StandaloneMmPkg.dsc b/StandaloneMmPkg/StandaloneMmPkg.dsc
index 73f3f0f6b1..ebc14bd5a7 100644
--- a/StandaloneMmPkg/StandaloneMmPkg.dsc
+++ b/StandaloneMmPkg/StandaloneMmPkg.dsc
@@ -20,7 +20,7 @@
PLATFORM_VERSION = 1.0
DSC_SPECIFICATION = 0x00010011
OUTPUT_DIRECTORY = Build/StandaloneMm
- SUPPORTED_ARCHITECTURES = AARCH64|X64
+ SUPPORTED_ARCHITECTURES = AARCH64|X64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT

@@ -57,7 +57,7 @@
StandaloneMmDriverEntryPoint|MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf
VariableMmDependency|StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf

-[LibraryClasses.AARCH64]
+[LibraryClasses.AARCH64, LibraryClasses.ARM]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
StandaloneMmMmuLib|ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
@@ -115,7 +115,7 @@
StandaloneMmPkg/Library/StandaloneMmMemoryAllocationLib/StandaloneMmMemoryAllocationLib.inf
StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf

-[Components.AARCH64]
+[Components.AARCH64, Components.ARM]
StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf
StandaloneMmPkg/Library/StandaloneMmPeCoffExtraActionLib/StandaloneMmPeCoffExtraActionLib.inf

@@ -128,7 +128,7 @@
# module style (EDK or EDKII) specified in [Components] section.
#
###################################################################################################
-[BuildOptions.AARCH64]
+[BuildOptions.AARCH64, BuildOptions.ARM]
GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp -mstrict-align
GCC:*_*_*_CC_FLAGS = -mstrict-align

--
2.17.1


[PATCH 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures

Etienne Carriere
 

Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
.../StandaloneMmCpu/AArch64/StandaloneMmCpu.c | 8 ++++----
.../AArch64/CreateHobList.c | 14 +++++++-------
.../AArch64/StandaloneMmCoreEntryPoint.c | 2 +-
3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
index 6884095c49..d4590bcd19 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
@@ -164,8 +164,8 @@ StandaloneMmCpuInitialize (

// Share the entry point of the CPU driver
DEBUG ((DEBUG_INFO, "Sharing Cpu Driver EP *0x%lx = 0x%lx\n",
- (UINT64) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
- (UINT64) PiMmStandaloneArmTfCpuDriverEntry));
+ (UINTN) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
+ (UINTN) PiMmStandaloneArmTfCpuDriverEntry));
*(CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr) = PiMmStandaloneArmTfCpuDriverEntry;

// Find the descriptor that contains the whereabouts of the buffer for
@@ -180,8 +180,8 @@ StandaloneMmCpuInitialize (
return Status;
}

- DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINT64) NsCommBufMmramRange->PhysicalStart));
- DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINT64) NsCommBufMmramRange->PhysicalSize));
+ DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINTN) NsCommBufMmramRange->PhysicalStart));
+ DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINTN) NsCommBufMmramRange->PhysicalSize));

CopyMem (&mNsCommBuffer, NsCommBufMmramRange, sizeof(EFI_MMRAM_DESCRIPTOR));
DEBUG ((DEBUG_INFO, "mNsCommBuffer: 0x%016lx - 0x%lx\n", mNsCommBuffer.CpuStart, mNsCommBuffer.PhysicalSize));
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
index e8fb96bd6e..4d4cf3d5ff 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
@@ -72,14 +72,14 @@ CreateHobListFromBootInfo (

// Create a hoblist with a PHIT and EOH
HobStart = HobConstructor (
- (VOID *) PayloadBootInfo->SpMemBase,
+ (VOID *) (UINTN) PayloadBootInfo->SpMemBase,
(UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,
- (VOID *) PayloadBootInfo->SpHeapBase,
- (VOID *) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)
+ (VOID *) (UINTN) PayloadBootInfo->SpHeapBase,
+ (VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)
);

// Check that the Hoblist starts at the bottom of the Heap
- ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);
+ ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);

// Build a Boot Firmware Volume HOB
BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);
@@ -190,9 +190,9 @@ CreateHobListFromBootInfo (
MmramRanges[3].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;

// Base and size of heap memory shared by all cpus
- MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;
- MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) HobStart;
- MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) HobStart;
+ MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+ MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+ MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
MmramRanges[4].RegionState = EFI_CACHEABLE | EFI_ALLOCATED;

// Base and size of heap memory shared by all cpus
diff --git a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
index 6c50f470aa..b445d6942e 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
@@ -328,7 +328,7 @@ _ModuleEntryPoint (

// Locate PE/COFF File information for the Standalone MM core module
Status = LocateStandaloneMmCorePeCoffData (
- (EFI_FIRMWARE_VOLUME_HEADER *) PayloadBootInfo->SpImageBase,
+ (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PayloadBootInfo->SpImageBase,
&TeData,
&TeDataSize
);
--
2.17.1


[PATCH 3/5] GenGv: Arm: support images entered in Thumb mode

Etienne Carriere
 

Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 as its LSBit set when
the entry instruction executes in Thumb mode.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 39 ++++++++++++++++-----
1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6..1b12cb9165 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -34,9 +34,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "FvLib.h"
#include "PeCoffLib.h"

-#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000
#define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000

+//
+// Arm instruction to jump to Fv enry instruction in Arm or Thumb mode.
+// From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate)
+// BLX (encoding A2) branches to offset in Thumb instruction set mode.
+// BL (encoding A1) branches to offset in Arm instruction set mode.
+//
+#define ARM_JUMP_OFFSET_MAX 0xffffff
+#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2))
+
+#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \
+ (((Imm32) & (1 << 1)) << (24 - 1)) | \
+ (((Imm32) >> 2) & 0x7fffff))
+#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8)
+
+//
+// Arm instruction to retrun from exception (MOVS PC, LR)
+//
+#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E
+
+
BOOLEAN mArm = FALSE;
BOOLEAN mRiscV = FALSE;
STATIC UINT32 MaxFfsAlignment = 0;
@@ -2203,23 +2222,25 @@ Returns:
// if we found an SEC core entry point then generate a branch instruction
// to it and populate a debugger SWI entry as well
if (UpdateVectorSec) {
+ UINT32 EntryOffset;

VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector");

- // B SecEntryPoint - signed_immed_24 part +/-32MB offset
- // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8
- ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2;
+ EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);

- if (ResetVector[0] > 0x00FFFFFF) {
- Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV");
+ if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
+ Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV");
return EFI_ABORTED;
}

- // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint"
- ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
+ if (SecCoreEntryAddress & 1) {
+ ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
+ } else {
+ ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
+ }

// SWI handler movs pc,lr. Just in case a debugger uses SWI
- ResetVector[2] = 0xE1B0F07E;
+ ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;

// Place holder to support a common interrupt handler from ROM.
// Currently not supported. For this to be used the reset vector would not be in this FV
--
2.17.1


[PATCH 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg

Etienne Carriere
 

This changes modify ArmPkg to prepare building StandaloneMm
firmware for 32bit Arm architectures, factorizing the AArch64
implementation.

This change adds MmCommunicationDxe driver and ArmMmuPeiLib
and ArmmmuStandaloneMmLib libraries to the list of the
standard components build for ArmPkg on when building for an
ARM architecture.

AArch64/ArmMmuStandaloneMmLib.c is moved to its parent
directory and built for both 32bit and 64bit architectures.

This change modifies MmCommunication to use macro
ARM_SMC_ID_MM_COMMUNICATE that is defined to the 32bit or
64bit SMC identifier defined in FF-A specification upon the
target architecture.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
ArmPkg/ArmPkg.dec | 2 +-
ArmPkg/ArmPkg.dsc | 2 +-
.../MmCommunicationDxe/MmCommunication.c | 2 +-
.../{AArch64 => }/ArmMmuStandaloneMmLib.c | 23 ++++++++++---------
.../ArmMmuStandaloneMmLib.inf | 6 ++---
5 files changed, 18 insertions(+), 17 deletions(-)
rename ArmPkg/Library/StandaloneMmMmuLib/{AArch64 => }/ArmMmuStandaloneMmLib.c (90%)

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index a8a22c649f..07e9930fb0 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -84,7 +84,7 @@
# hardware coherency (i.e., no virtualization or cache coherent DMA)
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043

-[PcdsFeatureFlag.AARCH64]
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
## Used to select method for requesting services from S-EL1.<BR><BR>
# TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
# FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 7194eb2d3c..208d609b1b 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -151,7 +151,7 @@
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf

-[Components.AARCH64]
+[Components.AARCH64, Components.ARM]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
index b1e3095809..4ae38a9f22 100644
--- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
+++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
@@ -125,7 +125,7 @@ MmCommunication2Communicate (
}

// SMC Function ID
- CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64;
+ CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE;

// Cookie
CommunicateSmcArgs.Arg1 = 0;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
similarity index 90%
rename from ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
rename to ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
index 5f453d18e4..77bf3dcedf 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
@@ -2,6 +2,7 @@
File managing the MMU for ARMv8 architecture in S-EL0

Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2021, Linaro Limited
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
@@ -62,7 +63,7 @@ SendMemoryPermissionRequest (
// for other Direct Request calls which are not atomic
// We therefore check only for Direct Response by the
// callee.
- if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
+ if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP) {
// A Direct Response means FF-A success
// Now check the payload for errors
// The callee sends back the return value
@@ -103,8 +104,8 @@ SendMemoryPermissionRequest (
// Check error response from Callee.
if (*RetVal & BIT31) {
// Bit 31 set means there is an error retured
- // See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64 and
- // Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
+ // See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET and
+ // Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET.
switch (*RetVal) {
case ARM_SVC_SPM_RET_NOT_SUPPORTED:
return EFI_UNSUPPORTED;
@@ -160,17 +161,17 @@ GetMemoryPermissions (
}

// Prepare the message parameters.
- // See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET_AARCH64.
+ // See [1], Section 13.5.5.1 MM_SP_MEMORY_ATTRIBUTES_GET.
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
- SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
- SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
} else {
- SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = 0;
SvcArgs.Arg3 = 0;
@@ -215,19 +216,19 @@ RequestMemoryPermissionChange (
ARM_SVC_ARGS SvcArgs;

// Prepare the message parameters.
- // See [1], Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET_AARCH64.
+ // See [1], Section 13.5.5.2 MM_SP_MEMORY_ATTRIBUTES_SET.
ZeroMem (&SvcArgs, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
// See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
- SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
SvcArgs.Arg2 = 0;
- SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg3 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg4 = BaseAddress;
SvcArgs.Arg5 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg6 = Permissions;
} else {
- SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64;
+ SvcArgs.Arg0 = ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES;
SvcArgs.Arg1 = BaseAddress;
SvcArgs.Arg2 = EFI_SIZE_TO_PAGES (Length);
SvcArgs.Arg3 = Permissions;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
index 89dda509c5..ebb1568279 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
@@ -16,14 +16,14 @@
LIBRARY_CLASS = StandaloneMmMmuLib
PI_SPECIFICATION_VERSION = 0x00010032

-[Sources.AARCH64]
- AArch64/ArmMmuStandaloneMmLib.c
+[Sources]
+ ArmMmuStandaloneMmLib.c

[Packages]
ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec

-[FeaturePcd.AARCH64]
+[FeaturePcd.ARM, FeaturePcd.AARCH64]
gArmTokenSpaceGuid.PcdFfaEnable

[LibraryClasses]
--
2.17.1


[PATCH 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A and Mm SVC IDs

Etienne Carriere
 

Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per FF-A specification [1]. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture. This will allow to factorize 64bit and 32bit in
packages implementation.

[1] https://developer.arm.com/documentation/den0077/latest

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 12 ++++++++++++
ArmPkg/Include/IndustryStandard/ArmMmSvc.h | 15 +++++++++++++++
2 files changed, 27 insertions(+)

diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
index 65b8343ade..ebcb54b28b 100644
--- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
@@ -17,9 +17,21 @@
#define ARM_FFA_SVC_H_

#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070

+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#endif
+
#define SPM_MAJOR_VERSION_FFA 1
#define SPM_MINOR_VERSION_FFA 0

diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
index 71a5398558..14f81d2a8b 100644
--- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
@@ -15,10 +15,25 @@
* privileged operations on its behalf.
*/
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065

+/* Generic IDs when using AArch32 or AArch64 execution state */
+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#endif
+
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
--
2.17.1


[PATCH v3 45/46] Silicon/Phytium: Added Rtc driver to FT2000/4

Ling Jia <jialing@...>
 

The RealTimeClockLib implemented EFI RealTimeClock
runtime services via RTC Lib.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec =
| 1 +
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 2 +
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf =
| 39 ++
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h =
| 24 +
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c =
| 462 ++++++++++++++++++++
6 files changed, 534 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico=
n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 2686ba3cc3a2..4c6c5c5f1118 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -45,6 +45,7 @@ [PcdsFixedAtBuild.common]
gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005=0D
gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x0000000=
6=0D
gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x0000000=
7=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008=0D
=0D
[Protocols]=0D
gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0=
x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 99034365d38f..9579f8e9b7d0 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -29,6 +29,10 @@ [LibraryClasses.common]
# Phytium Platform library=0D
ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformL=
ib.inf=0D
=0D
+ #FT2000-4Pkg RTC Driver=0D
+ RealTimeClockLib|Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/Re=
alTimeClockLib.inf=0D
+ TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf=0D
+=0D
# PL011 UART Driver and Dependency Libraries=0D
SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL=
ib.inf=0D
PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc=
kLib.inf=0D
@@ -168,6 +172,8 @@ [Components.common]
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D
}=0D
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf=0D
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf=0D
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
=0D
#=0D
# Common Arm Timer and Gic Components=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 67458458ddd5..242f647ca1b1 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -93,6 +93,8 @@ [FV.FvMain]
#=0D
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf=0D
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf=0D
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
=0D
INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTime=
ClockLib.inf
new file mode 100644
index 000000000000..09a06d53aef7
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.inf
@@ -0,0 +1,39 @@
+#/** @file=0D
+# Phytium RealTime Clock Library file.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D RealTimeClockLib=0D
+ FILE_GUID =3D fb320c94-40fe-11eb-b990-171865af292c=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D RealTimeClockLib=0D
+=0D
+[Sources.common]=0D
+ RealTimeClockLib.c=0D
+ RealTimeClockLib.h=0D
+=0D
+[Packages]=0D
+ ArmPlatformPkg/ArmPlatformPkg.dec=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ DxeServicesTableLib=0D
+ IoLib=0D
+ TimeBaseLib=0D
+ UefiRuntimeLib=0D
+=0D
+[Guids]=0D
+ gEfiEventVirtualAddressChangeGuid=0D
+=0D
+[Pcd]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.h b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl=
ockLib.h
new file mode 100644
index 000000000000..41ce002dc3be
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.h
@@ -0,0 +1,24 @@
+/** @file=0D
+ Phytium RealTime Clock Header.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef REAL_TIME_CLOCK_H_=0D
+#define REAL_TIME_CLOCK_H_=0D
+=0D
+#define RTC_CMR 0x4=0D
+#define RTC_AES_SEL 0x8=0D
+#define RTC_CCR 0xC=0D
+#define RTC_STAT 0x10=0D
+#define RTC_RSTAT 0x14=0D
+#define RTC_EOI 0x18=0D
+#define RTC_CDR_LOW 0x20=0D
+#define RTC_CCVR 0x24=0D
+#define RTC_CLR_LOW 0x28=0D
+#define RTC_CLR 0x2C=0D
+=0D
+#endif // REAL_TIME_CLOCK_H_=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeC=
lockLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeCl=
ockLib.c
new file mode 100644
index 000000000000..bf3047fb6795
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib=
.c
@@ -0,0 +1,462 @@
+/** @file=0D
+ Implement EFI RealTimeClock runtime services via RTC Lib.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <PiDxe.h>=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DxeServicesTableLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/TimeBaseLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiRuntimeLib.h>=0D
+#include <Protocol/RealTimeClock.h>=0D
+#include "RealTimeClockLib.h"=0D
+=0D
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;=0D
+STATIC UINTN mRtcBase;=0D
+STATIC CONST CHAR16 mTimeZoneVariableName[] =3D L"RtcTimeZone";=0D
+STATIC CONST CHAR16 mDaylightVariableName[] =3D L"RtcDaylight";=0D
+=0D
+/**=0D
+ Returns the current time and date information, and the time-keeping capa=
bilities=0D
+ of the hardware platform.=0D
+=0D
+ @param Time A pointer to storage to receive a snapsho=
t of the current time.=0D
+ @param Capabilities An optional pointer to a buffer to receiv=
e the real time clock=0D
+ device's capabilities.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER Time is NULL.=0D
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to ha=
rdware error.=0D
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an=
authentication failure.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibGetTime (=0D
+ OUT EFI_TIME *Time,=0D
+ OUT EFI_TIME_CAPABILITIES *Capabilities=0D
+ )=0D
+{=0D
+ UINT32 EpochSeconds;=0D
+ INT16 TimeZone;=0D
+ UINT8 Daylight;=0D
+ UINTN Size;=0D
+ EFI_STATUS Status;=0D
+=0D
+ // Ensure Time is a valid pointer=0D
+ if (Time =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100);=0D
+ //=0D
+ //read cdr high 32bit=0D
+ //=0D
+ EpochSeconds =3D MmioRead32 (mRtcBase + RTC_CCVR);=0D
+ MmioRead32 (mRtcBase + RTC_CDR_LOW);=0D
+ //=0D
+ // Get the current time zone information from non-volatile storage=0D
+ //=0D
+ Size =3D sizeof (TimeZone);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&TimeZone=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The time zone variable does not exist in non-volatile storage, so c=
reate it.=0D
+ //UTC+8:00=0D
+ //=0D
+ Time->TimeZone =3D -480;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_=
VARIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time->TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ } else {=0D
+ //=0D
+ // Got the time zone=0D
+ //=0D
+ Time->TimeZone =3D TimeZone;=0D
+ //=0D
+ // Check TimeZone bounds: -1440 to 1440 or 2047=0D
+ //=0D
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))=0D
+ && (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE)) {=0D
+ Time->TimeZone =3D EFI_UNSPECIFIED_TIMEZONE;=0D
+ }=0D
+ //=0D
+ // Adjust for the correct time zone=0D
+ //=0D
+ if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) {=0D
+ EpochSeconds -=3D Time->TimeZone * SEC_PER_MIN;=0D
+ }=0D
+ }=0D
+ //=0D
+ // Get the current daylight information from non-volatile storage=0D
+ //=0D
+ Size =3D sizeof (Daylight);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&Daylight=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The daylight variable does not exist in non-volatile storage, so cr=
eate it.=0D
+ //=0D
+ Time->Daylight =3D 0;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_=
VARIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time->Daylight)=0D
+ );=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ } else {=0D
+ //=0D
+ // Got the daylight information=0D
+ //=0D
+ Time->Daylight =3D Daylight;=0D
+ //=0D
+ // Adjust for the correct period=0D
+ //=0D
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGH=
T) {=0D
+ //=0D
+ // Convert to adjusted time, i.e. spring forwards one hour=0D
+ //=0D
+ EpochSeconds +=3D SEC_PER_HOUR;=0D
+ }=0D
+ }=0D
+=0D
+ //=0D
+ // Convert from internal 32-bit time to UEFI time=0D
+ //=0D
+ EpochToEfiTime (EpochSeconds, Time);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Sets the current local time and date information.=0D
+=0D
+ @param[in] Time A pointer to the current time.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER A time field is out of range.=0D
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardw=
are error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibSetTime (=0D
+ IN EFI_TIME *Time=0D
+ )=0D
+{=0D
+ UINTN EpochSeconds;=0D
+ EFI_STATUS Status;=0D
+ //=0D
+ // the maximum time span is just over 136 years.=0D
+ // Time is stored in Unix Epoch format, so it starts in 1970,=0D
+ // Therefore it can not exceed the year 2106.=0D
+ //=0D
+ if ((Time->Year < 1970) || (Time->Year >=3D 2106)) {=0D
+ return EFI_UNSUPPORTED;=0D
+ }=0D
+ EpochSeconds =3D EfiTimeToEpoch (Time);=0D
+ //=0D
+ // Adjust for the correct time zone, i.e. convert to UTC time zone=0D
+ //=0D
+ if (Time->TimeZone !=3D EFI_UNSPECIFIED_TIMEZONE) {=0D
+ EpochSeconds +=3D Time->TimeZone * SEC_PER_MIN;=0D
+ }=0D
+ //=0D
+ // Adjust for the correct period=0D
+ //=0D
+ if (((Time->Daylight & EFI_TIME_IN_DAYLIGHT) =3D=3D EFI_TIME_IN_DAYLIGHT=
)=0D
+ && (EpochSeconds > SEC_PER_HOUR)) {=0D
+ //=0D
+ // Convert to un-adjusted time, i.e. fall back one hour=0D
+ //=0D
+ EpochSeconds -=3D SEC_PER_HOUR;=0D
+ }=0D
+ //=0D
+ // Set the Rtc=0D
+ //=0D
+ MmioWrite32 (mRtcBase + RTC_AES_SEL, 0x100);=0D
+ MmioWrite32 (mRtcBase + RTC_CLR_LOW, 0x0);=0D
+ MmioWrite32 (mRtcBase + RTC_CLR, (UINT32)EpochSeconds);=0D
+ //=0D
+ // Save the current time zone information into non-volatile storage=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ sizeof (Time->TimeZone),=0D
+ (VOID *)&(Time->TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ // Save the current daylight information into non-volatile storage=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ sizeof (Time->Daylight),=0D
+ (VOID *)&(Time->Daylight)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Returns the current wakeup alarm clock setting.=0D
+=0D
+ @param[out] Enabled Indicates if the alarm is currently e=
nabled or disabled.=0D
+ @param[out] Pending Indicates if the alarm signal is pend=
ing and requires acknowledgement.=0D
+ @param[out] Time The current alarm setting.=0D
+=0D
+ @retval EFI_SUCCESS The alarm settings were returned.=0D
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.=0D
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieve=
d due to a hardware error.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibGetWakeupTime (=0D
+ OUT BOOLEAN *Enabled,=0D
+ OUT BOOLEAN *Pending,=0D
+ OUT EFI_TIME *Time=0D
+ )=0D
+{=0D
+ // Not a required feature=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Sets the system wakeup alarm clock time.=0D
+=0D
+ @param[in] Enabled Enable or disable the wakeup alarm.=0D
+ @param[out] Time If Enable is TRUE, the time to set th=
e wakeup alarm for.=0D
+=0D
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup al=
arm was enabled. If=0D
+ Enable is FALSE, then the wakeup alar=
m was disabled.=0D
+ @retval EFI_INVALID_PARAMETER A time field is out of range.=0D
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due =
to a hardware error.=0D
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on th=
is platform.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibSetWakeupTime (=0D
+ IN BOOLEAN Enabled,=0D
+ OUT EFI_TIME *Time=0D
+ )=0D
+{=0D
+ // Not a required feature=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+/**=0D
+ Fixup internal data so that EFI can be call in virtual mode.=0D
+ Call the passed in Child Notify event and convert any pointers in=0D
+ lib to virtual mode.=0D
+=0D
+ @param[in] Event The Event that is being processed=0D
+ @param[in] Context Event Context=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+LibRtcVirtualNotifyEvent (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ //=0D
+ // Only needed if you are going to support the OS calling RTC functions =
in virtual mode.=0D
+ // You will need to call EfiConvertPointer (). To convert any stored phy=
sical addresses=0D
+ // to virtual address. After the OS transitions to calling in virtual mo=
de, all future=0D
+ // runtime calls will be made in virtual mode.=0D
+ //=0D
+ EfiConvertPointer (0x0, (VOID **)&mRtcBase);=0D
+=0D
+ return;=0D
+}=0D
+=0D
+/**=0D
+ This is the declaration of an EFI image entry point. This can be the ent=
ry point to an application=0D
+ written to this specification, an EFI boot service driver, or an EFI run=
time driver.=0D
+=0D
+ @param[in] ImageHandle Handle that identifies the loaded imag=
e.=0D
+ @param[in] SystemTable System Table for this image.=0D
+=0D
+ @retval EFI_SUCCESS The operation completed successfully.=
=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+LibRtcInitialize (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_HANDLE Handle;=0D
+ INT16 TimeZone;=0D
+ UINTN Size;=0D
+ EFI_TIME Time;=0D
+ UINT8 Daylight;=0D
+ //=0D
+ // Initialize RTC Base Address=0D
+ //=0D
+ mRtcBase =3D PcdGet32 (PcdRtcBaseAddress);=0D
+ //=0D
+ // Declare the controller as EFI_MEMORY_RUNTIME=0D
+ //=0D
+ Status =3D gDS->AddMemorySpace (=0D
+ EfiGcdMemoryTypeMemoryMappedIo,=0D
+ mRtcBase,=0D
+ SIZE_4KB,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ //init timezone=0D
+ //=0D
+ Size =3D sizeof (TimeZone);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&TimeZone=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The time zone variable does not exist in non-volatile storage, so c=
reate it.=0D
+ //UTC 8:00=0D
+ //=0D
+ Time.TimeZone =3D -480;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mTimeZoneVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time.TimeZone)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+ //=0D
+ //daylight init=0D
+ //=0D
+ Size =3D sizeof (Daylight);=0D
+ Status =3D EfiGetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ NULL,=0D
+ &Size,=0D
+ (VOID *)&Daylight=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT (Status !=3D EFI_INVALID_PARAMETER);=0D
+ ASSERT (Status !=3D EFI_BUFFER_TOO_SMALL);=0D
+ //=0D
+ // The daylight variable does not exist in non-volatile storage, so cr=
eate it.=0D
+ //=0D
+ Time.Daylight =3D 0;=0D
+ //=0D
+ // Store it=0D
+ //=0D
+ Status =3D EfiSetVariable (=0D
+ (CHAR16 *)mDaylightVariableName,=0D
+ &gEfiCallerIdGuid,=0D
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VA=
RIABLE_RUNTIME_ACCESS,=0D
+ Size,=0D
+ (VOID *)&(Time.Daylight)=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+=0D
+ Status =3D gDS->SetMemorySpaceAttributes (mRtcBase, SIZE_4KB, EFI_MEMORY=
_UC | EFI_MEMORY_RUNTIME);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ //=0D
+ // Install the protocol=0D
+ //=0D
+ Handle =3D NULL;=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &Handle,=0D
+ &gEfiRealTimeClockArchProtocolGuid,=0D
+ NULL,=0D
+ NULL=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ //=0D
+ // Register for the virtual address change event=0D
+ //=0D
+ Status =3D gBS->CreateEventEx (=0D
+ EVT_NOTIFY_SIGNAL,=0D
+ TPL_NOTIFY,=0D
+ LibRtcVirtualNotifyEvent,=0D
+ NULL,=0D
+ &gEfiEventVirtualAddressChangeGuid,=0D
+ &mRtcVirtualAddrChangeEvent=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
--=20
2.25.1


[PATCH v3 46/46] Maintainers.txt: Added maintainers and reviewers for the DurianPkg

Ling Jia <jialing@...>
 

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Maintainers.txt | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index afbd2cff0e9c..b6cfe74e09da 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -321,3 +321,11 @@ F: Silicon/SiFive/
M: Abner Chang <abner.chang@hpe.com>=0D
M: Gilbert Chen <gilbert.chen@hpe.com>=0D
R: Daniel Schaefer <daniel.schaefer@hpe.com>=0D
+=0D
+Phytium platforms and silicon=0D
+F: Platform/Phytium/=0D
+F: Silicon/silicon/=0D
+M: Leif Lindholm <leif@nuviainc.com>=0D
+R: Peng Xie <xiepeng@phytium.com.cn>=0D
+R: Ling Jia <jialing@phytium.com.cn>=0D
+R: Yiqi Shu <shuyiqi@phytium.com.cn>=0D
--=20
2.25.1


[PATCH v3 39/46] Silicon/Phytium: Added SMBIOS support to FT2000/4

Ling Jia <jialing@...>
 

This driver installs SMBIOS information for FT2000/4.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 6 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.in=
f | 47 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c =
| 943 ++++++++++++++++++++
4 files changed, 1002 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 6f38acb6361c..28e52e15e393 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -286,6 +286,12 @@ [Components.common]
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf=0D
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe=
.inf=0D
=0D
+ #=0D
+ # SMBIOS=0D
+ #=0D
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D
+ Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.=
inf=0D
+=0D
#=0D
# Bds=0D
#=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index f435f7cb51c2..3106a43fb744 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -178,6 +178,12 @@ [FV.FvMain]
#=0D
INF ShellPkg/Application/Shell/Shell.inf=0D
=0D
+ #=0D
+ # SMBIOS=0D
+ #=0D
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D
+ INF Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatform=
Dxe.inf=0D
+=0D
#=0D
# Bds=0D
#=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl=
atformDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/Smbio=
sPlatformDxe.inf
new file mode 100644
index 000000000000..69a021e04823
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD=
xe.inf
@@ -0,0 +1,47 @@
+#/** @file=0D
+# This driver installs SMBIOS information for Phytium.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D SmbiosPlatformDxe=0D
+ FILE_GUID =3D d64f09f8-40dc-11eb-9be6-f7a038f956ba=
=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D SmbiosTablePublishEntry=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D AARCH64=0D
+#=0D
+[Sources]=0D
+ SmbiosPlatformDxe.c=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ IoLib=0D
+ UefiBootServicesTableLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[Guids]=0D
+ gEfiGlobalVariableGuid=0D
+=0D
+[Protocols]=0D
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED=0D
+=0D
+[Guids]=0D
+=0D
+[Depex]=0D
+ gEfiSmbiosProtocolGuid=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPl=
atformDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosP=
latformDxe.c
new file mode 100644
index 000000000000..4a1f77dfb2a6
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformD=
xe.c
@@ -0,0 +1,943 @@
+/** @file=0D
+ This driver installs SMBIOS information for Phytium Durian platforms.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+=0D
+#include <IndustryStandard/SmBios.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Platform.h>=0D
+#include <Protocol/Smbios.h>=0D
+=0D
+// SMBIOS tables often reference each other using=0D
+// fixed constants, define a list of these constants=0D
+// for our hardcoded tables=0D
+=0D
+#define TYPE0_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Vendor */ \=0D
+ "V1.0\0" /* BiosVersion */ \=0D
+ __DATE__"\0" /* BiosReleaseDate */=0D
+=0D
+#define TYPE1_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "Phytium Durian Development Platform\0" /* Product Name */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* SerialNumber */ \=0D
+ "Not set\0" /* SKUNumber */ \=0D
+ "FT-2000/4\0" /* Family */ \=0D
+=0D
+#define TYPE2_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "Phytium Durian Development Platform\0" /* Product Name */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* Serial */ \=0D
+ "Not Set\0" /* BaseBoardAssetTag */ \=0D
+ "Not Set\0" /* BaseBoardChassisLocation */=0D
+=0D
+#define TYPE3_STRINGS \=0D
+ "PHYTIUM LTD\0" /* Manufacturer */ \=0D
+ "None\0" /* Version */ \=0D
+ "Not Set\0" /* Serial */ \=0D
+ "Not Set\0" /* AssetTag */=0D
+=0D
+#define TYPE4_STRINGS \=
=0D
+ "FT-2000/4\0" /* socket type */ \=
=0D
+ "PHYTIUM LTD\0" /* manufactuer */ \=
=0D
+ "FT-2000/4\0" /* processor version */ \=
=0D
+ "Not Set\0" /* SerialNumber */ \=
=0D
+ "Not Set\0" /* processor 2 description */ \=
=0D
+ "Not Set\0" /* AssetTag */=0D
+=0D
+=0D
+#define TYPE7_STRINGS \=0D
+ "L1 Instruction\0" /* L1I */ \=0D
+ "L1 Data\0" /* L1D */ \=0D
+ "L2\0" /* L2 */=0D
+=0D
+#define TYPE7_L1DATA_STRINGS \=0D
+ "L1 Data Cache\0" /* L1 data */=0D
+=0D
+=0D
+#define TYPE7_L1INS_STRINGS \=0D
+ "L1 Instruction Cache\0" /* L1 ins */=0D
+=0D
+#define TYPE7_L2_STRINGS \=0D
+ "L2 Cache\0" /* L2 */=0D
+=0D
+#define TYPE7_L3_STRINGS \=0D
+ "L3 Cache\0" /* L3 */=0D
+=0D
+=0D
+#define TYPE9_STRINGS \=0D
+ "PCIE_SLOT0\0" /* Slot0 */ \=0D
+ "PCIE_SLOT1\0" /* Slot1 */ \=0D
+ "PCIE_SLOT2\0" /* Slot2 */ \=0D
+ "PCIE_SLOT3\0" /* Slot3 */=0D
+=0D
+#define TYPE9_STRINGS_PCIE0X16 \=0D
+ "PCIE0_X16\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE0X1 \=0D
+ "PCIE0_X1\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE1X16 \=0D
+ "PCIE1_X16\0"=0D
+=0D
+#define TYPE9_STRINGS_PCIE1X1 \=0D
+ "PCIE1_X1\0"=0D
+=0D
+#define TYPE13_STRINGS \=0D
+ "en|US|iso8859-1\0" \=0D
+ "zh|CN|unicode\0"=0D
+=0D
+=0D
+#define TYPE16_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE17_STRINGS_CHANNEL0 \=0D
+ "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \=0D
+ "Bank0\0" /* bank description */ \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0"=0D
+=0D
+#define TYPE17_STRINGS_CHANNEL1 \=0D
+ "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \=0D
+ "Bank0\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0" \=0D
+ "Not Set\0"=0D
+=0D
+=0D
+#define TYPE19_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE32_STRINGS \=0D
+ "\0" /* nothing */=0D
+=0D
+#define TYPE39_STRINGS \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/ \=0D
+ "Not specified\0" /* not specified*/=0D
+=0D
+#define TYPE38_STRINGS \=0D
+ "\0"=0D
+=0D
+//=0D
+// Type definition and contents of the default SMBIOS table.=0D
+// This table covers only the minimum structures required by=0D
+// the SMBIOS specification (section 6.2, version 3.0)=0D
+//=0D
+#pragma pack(1)=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE0 Base;=0D
+ INT8 Strings[sizeof (TYPE0_STRINGS)];=0D
+} ARM_TYPE0;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE1 Base;=0D
+ UINT8 Strings[sizeof (TYPE1_STRINGS)];=0D
+} ARM_TYPE1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE2 Base;=0D
+ UINT8 Strings[sizeof (TYPE2_STRINGS)];=0D
+} ARM_TYPE2;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE3 Base;=0D
+ UINT8 Strings[sizeof (TYPE3_STRINGS)];=0D
+} ARM_TYPE3;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE4 Base;=0D
+ UINT8 Strings[sizeof (TYPE4_STRINGS)];=0D
+} ARM_TYPE4;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L1DATA_STRINGS)];=0D
+} ARM_TYPE7_L1DATA;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L1INS_STRINGS)];=0D
+} ARM_TYPE7_L1INS;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L2_STRINGS)];=0D
+} ARM_TYPE7_L2;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE7 Base;=0D
+ UINT8 Strings[sizeof (TYPE7_L3_STRINGS)];=0D
+} ARM_TYPE7_L3;=0D
+=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS)];=0D
+} ARM_TYPE9;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X16)];=0D
+} ARM_TYPE9_PCIE0X16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X1)];=0D
+} ARM_TYPE9_PCIE0X1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X16)];=0D
+} ARM_TYPE9_PCIE1X16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE9 Base;=0D
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X1)];=0D
+} ARM_TYPE9_PCIE1X1;=0D
+=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE13 Base;=0D
+ UINT8 Strings[sizeof (TYPE13_STRINGS)];=0D
+} ARM_TYPE13;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE16 Base;=0D
+ UINT8 Strings[sizeof (TYPE16_STRINGS)];=0D
+} ARM_TYPE16;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE17 Base;=0D
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL0)];=0D
+} ARM_TYPE17_CHANNEL0;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE17 Base;=0D
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL1)];=0D
+} ARM_TYPE17_CHANNEL1;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE19 Base;=0D
+ UINT8 Strings[sizeof (TYPE19_STRINGS)];=0D
+} ARM_TYPE19;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE32 Base;=0D
+ UINT8 Strings[sizeof (TYPE32_STRINGS)];=0D
+} ARM_TYPE32;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE38 Base;=0D
+ UINT8 Strings[sizeof (TYPE38_STRINGS)];=0D
+} ARM_TYPE38;=0D
+=0D
+typedef struct {=0D
+ SMBIOS_TABLE_TYPE39 Base;=0D
+ UINT8 Strings[sizeof (TYPE39_STRINGS)];=0D
+} ARM_TYPE39;=0D
+=0D
+enum SMBIOS_REFRENCE_HANDLES {=0D
+ SMBIOS_HANDLE_L1I =3D 0x1000,=0D
+ SMBIOS_HANDLE_L1D,=0D
+ SMBIOS_HANDLE_L2,=0D
+ SMBIOS_HANDLE_L3,=0D
+ SMBIOS_HANDLE_MOTHERBOARD,=0D
+ SMBIOS_HANDLE_CHASSIS,=0D
+ SMBIOS_HANDLE_CLUSTER,=0D
+ SMBIOS_HANDLE_MEMORY,=0D
+ SMBIOS_HANDLE_DIMM_0,=0D
+ SMBIOS_HANDLE_DIMM_1=0D
+};=0D
+=0D
+#define SERIAL_LEN 10 //this must be less than the buffer len allocated i=
n the type1 structure=0D
+=0D
+#pragma pack()=0D
+=0D
+//BIOS Information (Type 0)=0D
+ARM_TYPE0 BiosInfo_Type0 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1, //Vendor=0D
+ 2, //BiosVersion=0D
+ 0x8800, //BiosSegment=0D
+ 3, //BiosReleaseDate=0D
+ 0xFF, //BiosSize=0D
+ { //BiosCharacteristics=0D
+ 0, // Reserved =
:2=0D
+ 0, // Unknown =
:1=0D
+ 0, // BiosCharacteristicsN=
otSupported :1=0D
+ 0, // IsaIsSupported =
:1=0D
+ 0, // McaIsSupported =
:1=0D
+ 0, // EisaIsSupported =
:1=0D
+ 1, // PciIsSupported =
:1=0D
+ 0, // PcmciaIsSupported =
:1=0D
+ 0, // PlugAndPlayIsSupport=
ed :1=0D
+ 0, // ApmIsSupported =
:1=0D
+ 1, // BiosIsUpgradable =
:1=0D
+ 0, // BiosShadowingAllowed=
:1=0D
+ 0, // VlVesaIsSupported =
:1=0D
+ 0, // EscdSupportIsAvailab=
le :1=0D
+ 1, // BootFromCdIsSupporte=
d :1=0D
+ 1, // SelectableBootIsSupp=
orted :1=0D
+ 0, // RomBiosIsSocketed =
:1=0D
+ 0, // BootFromPcmciaIsSupp=
orted :1=0D
+ 0, // EDDSpecificationIsSu=
pported :1=0D
+ 0, // JapaneseNecFloppyIsS=
upported :1=0D
+ 0, // JapaneseToshibaFlopp=
yIsSupported :1=0D
+ 0, // Floppy525_360IsSuppo=
rted :1=0D
+ 0, // Floppy525_12IsSuppor=
ted :1=0D
+ 0, // Floppy35_720IsSuppor=
ted :1=0D
+ 0, // Floppy35_288IsSuppor=
ted :1=0D
+ 0, // PrintScreenIsSupport=
ed :1=0D
+ 0, // Keyboard8042IsSuppor=
ted :1=0D
+ 0, // SerialIsSupported =
:1=0D
+ 0, // PrinterIsSupported =
:1=0D
+ 0, // CgaMonoIsSupported =
:1=0D
+ 0, // NecPc98 =
:1=0D
+ 0 // ReservedForVendor =
:3=0D
+ },=0D
+ {=0D
+ 0x03, //BIOSCharacteristicsEx=
tensionBytes[0]=0D
+ 0x0D //BIOSCharacteristicsEx=
tensionBytes[1]=0D
+ },=0D
+ 0xFF, //SystemBiosMajorReleas=
e;=0D
+ 0xFF, //SystemBiosMinorReleas=
e;=0D
+ 0xFF, //EmbeddedControllerFir=
mwareMajorRelease;=0D
+ 0xFF, //EmbeddedControllerFir=
mwareMinorRelease;=0D
+ },=0D
+ TYPE0_STRINGS=0D
+};=0D
+=0D
+//System Information (Type 1).=0D
+ARM_TYPE1 SystemInfo_Type1 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED // Handle=0D
+ },=0D
+ 1, // Manufacturer=0D
+ 2, // ProductName=0D
+ 3, // Version=0D
+ 4, // SerialNumber=0D
+ { // Uuid=0D
+ 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa,=
0xbb, 0xcc}=0D
+ },=0D
+ SystemWakeupTypePowerSwitch, // SystemWakeupType=
=0D
+ 5, // SKUNumber,=0D
+ 6 // Family=0D
+ },=0D
+ TYPE1_STRINGS=0D
+};=0D
+=0D
+//Base Board (or Module) Information (Type 2)=0D
+ARM_TYPE2 BaseboardInfo_Type2 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Len=
gth=0D
+ SMBIOS_HANDLE_MOTHERBOARD // Handle=0D
+ },=0D
+ 1, // BaseBoard=
Manufacturer=0D
+ 2, // BaseBoard=
ProductName=0D
+ 3, // BaseBoard=
Version=0D
+ 4, // BaseBoard=
SerialNumber=0D
+ 5, // BaseBoard=
AssetTag=0D
+ { // FeatureFl=
ag=0D
+ 1, // Motherboa=
rd :1=0D
+ 0, // RequiresD=
aughterCard :1=0D
+ 0, // Removable=
:1=0D
+ 1, // Replaceab=
le :1=0D
+ 0, // HotSwappa=
ble :1=0D
+ 0 // Reserved =
:3=0D
+ },=0D
+ 6, // BaseBoard=
ChassisLocation=0D
+ 0, // ChassisHa=
ndle;=0D
+ BaseBoardTypeMotherBoard, // BoardType=
;=0D
+ 0, // NumberOfC=
ontainedObjectHandles;=0D
+ {=0D
+ 0=0D
+ } // Contained=
ObjectHandles[1];=0D
+ },=0D
+ TYPE2_STRINGS=0D
+};=0D
+=0D
+//System Enclosure or Chassis (Type 3)=0D
+ARM_TYPE3 SystemEnclosure_Type3 =3D {=0D
+ {=0D
+ { // Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Len=
gth=0D
+ SMBIOS_HANDLE_CHASSIS // Handle=0D
+ },=0D
+ 1, // Manufactr=
urer=0D
+ MiscChassisTypeMainServerChassis, // Type=0D
+ 2, // Version=0D
+ 3, // SerialNum=
ber=0D
+ 4, // AssetTag=
=0D
+ ChassisStateSafe, // BootupSta=
te=0D
+ ChassisStateSafe, // PowerSupp=
lyState=0D
+ ChassisStateSafe, // ThermalSt=
ate=0D
+ ChassisSecurityStatusNone, // SecurityS=
tate=0D
+ {=0D
+ 0, // OemDefine=
d[0]=0D
+ 0, // OemDefine=
d[1]=0D
+ 0, // OemDefine=
d[2]=0D
+ 0 // OemDefine=
d[3]=0D
+ },=0D
+ 2, // Height=0D
+ 1, // NumberofP=
owerCords=0D
+ 0, // Contained=
ElementCount=0D
+ 0, // Contained=
ElementRecordLength=0D
+ { // Contained=
Elements[0]=0D
+ {=0D
+ 0, // Contained=
ElementType=0D
+ 0, // Contained=
ElementMinimum=0D
+ 0 // Contained=
ElementMaximum=0D
+ }=0D
+ }=0D
+ },=0D
+ TYPE3_STRINGS=0D
+};=0D
+=0D
+//Processor Infomation (Type 4)=0D
+ARM_TYPE4 ProcessorInfo_Type4 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE4), //Length=0D
+ SMBIOS_HANDLE_CLUSTER //Handle=0D
+ },=0D
+ 1, //Socket=0D
+ CentralProcessor, //ProcessorType=0D
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily=0D
+ 2, //ProcessorManufacture=0D
+ { //ProcessorId=0D
+ { //Signature=0D
+ 0=0D
+ },=0D
+ { //FeatureFlags=0D
+ 0=0D
+ }=0D
+ },=0D
+ 3, //ProcessorVersion=0D
+ { //Voltage=0D
+ 0, 0, 0, 1, 0, 1=0D
+ },=0D
+ 1, //ExternalClock=0D
+ 1, //MaxSpeed=0D
+ 0, //CurrentSpeed=0D
+ 0x41, //Status=0D
+ ProcessorUpgradeUnknown, //ProcessorUpgrade=0D
+ SMBIOS_HANDLE_L1D, //L1Ins=0D
+ SMBIOS_HANDLE_L2, //L1Data=0D
+ SMBIOS_HANDLE_L3, //L2=0D
+ 4, //SerialNumber=0D
+ 5, //AssetTag=0D
+ 6, //PartNumber=0D
+=0D
+ 4, //CoreCount=0D
+ 0, //EnabledCoreCount=0D
+ 0, //ThreadCount=0D
+ 0x00EC, //ProcessorCharacteristics=
=0D
+=0D
+ ProcessorFamilyARMv8, //ProcessorFamily2=0D
+=0D
+ 0, //CoreCount2=0D
+ 0, //EnabledCoreCount2=0D
+ 0 //ThreadCount2=0D
+ },=0D
+ TYPE4_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L1 DATA=0D
+ARM_TYPE7_L1DATA L1Data_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L1D //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0180, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeData, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 128,=0D
+ 128=0D
+ },=0D
+ TYPE7_L1DATA_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L1 INS=0D
+ARM_TYPE7_L1INS L1Ins_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L1I //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0180, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorParity, //ErrorCorrectionType=
=0D
+ CacheTypeInstruction, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 128,=0D
+ 128=0D
+ },=0D
+ TYPE7_L1INS_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L2=0D
+ARM_TYPE7_L2 L2_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L2 //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0281, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeUnified, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 4096,=0D
+ 4096=0D
+ },=0D
+ TYPE7_L2_STRINGS=0D
+};=0D
+=0D
+//Cache Information (Type7) L3=0D
+ARM_TYPE7_L3 L3_Type7 =3D {=0D
+ {=0D
+ { //Header=0D
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type=0D
+ sizeof (SMBIOS_TABLE_TYPE7), //Length=0D
+ SMBIOS_HANDLE_L3 //Handle=0D
+ },=0D
+ 1, //SocketDesignation=0D
+ 0x0281, //CacheConfiguration=0D
+ 0, //MaximumCacheSize=0D
+ 0, //InstalledSize=0D
+ { //SupportedSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ { //CurrentSRAMType=0D
+ 0, 0, 0, 0, 0, 1, 0, 0=0D
+ },=0D
+ 0, //CacheSpeed=0D
+ CacheErrorSingleBit, //ErrorCorrectionType=
=0D
+ CacheTypeUnified, //SystemCacheType=0D
+ CacheAssociativity8Way, //Associativity=0D
+ 4096,=0D
+ 4096=0D
+ },=0D
+ TYPE7_L3_STRINGS=0D
+};=0D
+=0D
+//PCIE0_X16 (Type 9)=0D
+ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth16X,=0D
+ SlotUsageInUse,=0D
+ SlotLengthLong,=0D
+ 0,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE0X16=0D
+};=0D
+=0D
+//PCIE0_X1 (Type 9)=0D
+ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth1X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthShort,=0D
+ 1,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE0X1=0D
+};=0D
+=0D
+//PCIE1_X16 (Type 9)=0D
+ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth16X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthLong,=0D
+ 2,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE1X16=0D
+};=0D
+=0D
+//PCIE1_X1 (Type 9)=0D
+ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 1,=0D
+ SlotTypePciX,=0D
+ SlotDataBusWidth1X,=0D
+ SlotUsageAvailable,=0D
+ SlotLengthShort,=0D
+ 3,=0D
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown=0D
+ {1, 0, 0, 0, 0}, //PME and SMBUS=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ 0xFF,=0D
+ },=0D
+ TYPE9_STRINGS_PCIE1X1=0D
+};=0D
+=0D
+//Bios Language Information (Type13)=0D
+ARM_TYPE13 BiosLangInfo_Type13 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 2,=0D
+ 0,=0D
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},=0D
+ 2=0D
+ },=0D
+ TYPE13_STRINGS=0D
+};=0D
+=0D
+//Physical Memory Array (Type 16)=0D
+ARM_TYPE16 MemArray_Type16 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length=0D
+ SMBIOS_HANDLE_MEMORY=0D
+ },=0D
+ MemoryArrayLocationSystemBoard,=0D
+ MemoryArrayUseSystemMemory,=0D
+ MemoryErrorCorrectionNone,=0D
+ 0x1000000, //16G=0D
+ 0xFFFE,=0D
+ 2=0D
+ },=0D
+ TYPE16_STRINGS=0D
+};=0D
+=0D
+//Memory Device (Type17)=0D
+ARM_TYPE17_CHANNEL0 MemDev_Type17_0 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length=0D
+ SMBIOS_HANDLE_DIMM_0=0D
+ },=0D
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs=0D
+ 0xFFFE, //no errors=0D
+ 64, //single DIMM, no ECC is 64bits (for ecc this wo=
uld be 72)=0D
+ 64, //data width of this device (64-bits)=0D
+ 0x4000, //16GB=0D
+ 0x09, //FormFactor=0D
+ 0, //not part of a set=0D
+ 1, //right side of board=0D
+ 2, //bank 0=0D
+ MemoryTypeDdr4, //LP DDR4=0D
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered=0D
+ 2400, //2400Mhz DDR=0D
+ 3, //Manufacturer=0D
+ 4, //serial=0D
+ 5, //asset tag=0D
+ 6, //part number=0D
+ 0, //attrbute=0D
+ 0x2000, // 8G=0D
+ 2400, //2400MHz=0D
+ 1500, //Max V=0D
+ 1500, //Max V=0D
+ 1500, //Configure V=0D
+ },=0D
+ TYPE17_STRINGS_CHANNEL0=0D
+};=0D
+=0D
+//Memory Device (Type17)=0D
+ARM_TYPE17_CHANNEL1 MemDev_Type17_1 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length=0D
+ SMBIOS_HANDLE_DIMM_1=0D
+ },=0D
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs=0D
+ 0xFFFE, //no errors=0D
+ 64, //single DIMM, no ECC is 64bits (for ecc this wo=
uld be 72)=0D
+ 64, //data width of this device (64-bits)=0D
+ 0x2000, //8GB=0D
+ 0x09, //FormFactor=0D
+ 0, //not part of a set=0D
+ 1, //right side of board=0D
+ 2, //bank 0=0D
+ MemoryTypeDdr4, //LP DDR4=0D
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered=0D
+ 2400, //2400Mhz DDR=0D
+ 3, //varies between diffrent production runs=0D
+ 4, //serial=0D
+ 5, //asset tag=0D
+ 6, //part number=0D
+ 0, //attrbute=0D
+ 0x4000, // 16G=0D
+ 2400, //2400MHz=0D
+ 1500, //Max V=0D
+ 1500, //Max V=0D
+ 1500, //Configure V=0D
+ },=0D
+ TYPE17_STRINGS_CHANNEL1=0D
+};=0D
+=0D
+//Memory Array Mapped Address (Type 19)=0D
+ARM_TYPE19 MemArrayMapAddr_Type19 =3D {=0D
+ {=0D
+ { // SMBIOS_STRUCTURE Hdr=0D
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type=0D
+ sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ 0,=0D
+ 0x1000000, //16G=0D
+ SMBIOS_HANDLE_MEMORY, //handle=0D
+ 2,=0D
+ 0, //starting addr of first 2GB=0D
+ 0, //ending addr of first 2GB=0D
+ },=0D
+ TYPE19_STRINGS=0D
+};=0D
+=0D
+//System Boot Information (Type 32)=0D
+ARM_TYPE32 SystemBoot_Type32 =3D {=0D
+ {=0D
+ {=0D
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,=0D
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length=0D
+ SMBIOS_HANDLE_PI_RESERVED=0D
+ },=0D
+ { // Reserved[6]=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0,=0D
+ 0=0D
+ },=0D
+ BootInformationStatusNoError // BootInformationSta=
tus=0D
+ },=0D
+ TYPE32_STRINGS=0D
+};=0D
+=0D
+VOID *DefaultCommonTables[]=3D=0D
+{=0D
+ &BiosInfo_Type0,=0D
+ &SystemInfo_Type1,=0D
+ &BaseboardInfo_Type2,=0D
+ &SystemEnclosure_Type3,=0D
+ &ProcessorInfo_Type4,=0D
+ &L1Data_Type7,=0D
+ &L1Ins_Type7,=0D
+ &L2_Type7,=0D
+ &L3_Type7,=0D
+ &Pcie0X16_Type9,=0D
+ &Pcie0X1_Type9,=0D
+ &Pcie1X16_Type9,=0D
+ &Pcie1X1_Type9,=0D
+ &MemArray_Type16,=0D
+ &MemDev_Type17_0,=0D
+ &MemDev_Type17_1,=0D
+ &MemArrayMapAddr_Type19,=0D
+ &BiosLangInfo_Type13,=0D
+ &SystemBoot_Type32,=0D
+ NULL=0D
+};=0D
+=0D
+=0D
+/**=0D
+ Installed a whole table worth of structructures.=0D
+=0D
+ @param[in] Smbios The Pointer of Smbios Protocol.=0D
+=0D
+ @retval EFI_SUCCESS Table data successfully installed.=0D
+ @retval Other Table data was not installed.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+InstallStructures (=0D
+ IN EFI_SMBIOS_PROTOCOL *Smbios,=0D
+ IN VOID *DefaultTables[]=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_SMBIOS_HANDLE SmbiosHandle;=0D
+ UINT32 TableEntry;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ for ( TableEntry =3D0; DefaultTables[TableEntry] !=3D NULL; TableEntry++=
)=0D
+ {=0D
+ SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry]=
)->Handle;=0D
+ Status =3D Smbios->Add (=0D
+ Smbios,=0D
+ NULL,=0D
+ &SmbiosHandle,=0D
+ (EFI_SMBIOS_TABLE_HEADER *) DefaultTables[TableEntry]=0D
+ );=0D
+ if (EFI_ERROR (Status))=0D
+ break;=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Installed All SMBIOS information.=0D
+=0D
+ @param[in] Smbios The Pointer of Smbios Protocol.=0D
+=0D
+ @retval EFI_SUCCESS SMBIOS information successfully installed.=0D
+ @retval Other SMBIOS information was not installed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+InstallAllStructures (=0D
+ IN EFI_SMBIOS_PROTOCOL *Smbios=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ Status =3D InstallStructures (Smbios, DefaultCommonTables);=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Find the smbios protocol and installed SMBIOS information=0D
+ for ARM platforms.=0D
+=0D
+ @param[in] ImageHandle Module's image handle.=0D
+ @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE.=0D
+=0D
+ @retval EFI_SUCCESS Smbios data successfully installed.=0D
+ @retval Other Smbios data was not installed.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SmbiosTablePublishEntry (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_SMBIOS_PROTOCOL *Smbios;=0D
+=0D
+ //=0D
+ // Find the SMBIOS protocol=0D
+ //=0D
+ Status =3D gBS->LocateProtocol (=0D
+ &gEfiSmbiosProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&Smbios=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D InstallAllStructures (Smbios);=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.25.1


[PATCH v3 41/46] Silicon/Phytium: Added PciHostBridgeLib to FT2000/4

Ling Jia <jialing@...>
 

The Pci host bridge library is mainly
to get Pci bridge information.

v3:
Optimize the codes of PciHostBridgeLib.c to conform to specifications.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc =
| 9 +
Platform/Phytium/DurianPkg/DurianPkg.fdf =
| 6 +
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf =
| 47 +++++
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c =
| 181 ++++++++++++++++++++
4 files changed, 243 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 093b2cd9dbd4..3a9bc2289cf3 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -37,6 +37,7 @@ [LibraryClasses.common]
[LibraryClasses.common.DXE_DRIVER]=0D
# Pci dependencies=0D
PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegme=
ntLib.inf=0D
+ PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/Pc=
iHostBridgeLib.inf=0D
=0D
##########################################################################=
######=0D
#=0D
@@ -263,6 +264,14 @@ [Components.common]
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D
=0D
+ #=0D
+ # PCI Support=0D
+ #=0D
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic=
eDxe.inf=0D
+=0D
#=0D
# The following 2 module perform the same work except one operate variab=
le.=0D
# Only one of both should be put into fdf.=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 3106a43fb744..a443d0f3a4ac 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -135,6 +135,12 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf=0D
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i=
nf=0D
=0D
+ #=0D
+ # PCI Support=0D
+ #=0D
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D
+=0D
#=0D
# SATA Controller=0D
#=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr=
idgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostB=
ridgeLib.inf
new file mode 100644
index 000000000000..0e6f0797b0fe
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib=
.inf
@@ -0,0 +1,47 @@
+#/** @file=0D
+# PCI Host Bridge Library instance for Phytium SOC.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D PciHostBridgeLib=0D
+ FILE_GUID =3D f965de0e-40fe-11eb-8290-3f9d1f895a80=
=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build=0D
+# tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D ARM AARCH64=0D
+#=0D
+=0D
+[Sources]=0D
+ PciHostBridgeLib.c=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+=0D
+[Guids]=0D
+=0D
+[FixedPcd]=0D
+ gArmTokenSpaceGuid.PcdPciBusMin=0D
+ gArmTokenSpaceGuid.PcdPciBusMax=0D
+ gArmTokenSpaceGuid.PcdPciIoBase=0D
+ gArmTokenSpaceGuid.PcdPciIoSize=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio32Size=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Base=0D
+ gArmTokenSpaceGuid.PcdPciMmio64Size=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBr=
idgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBri=
dgeLib.c
new file mode 100644
index 000000000000..8ed3516749a1
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib=
.c
@@ -0,0 +1,181 @@
+/** @file=0D
+ PCI host bridge library instance for Phytium SOC.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DevicePathLib.h>=0D
+#include <Library/PciHostBridgeLib.h>=0D
+#include <Protocol/PciHostBridgeResourceAllocation.h>=0D
+#include <Protocol/PciRootBridgeIo.h>=0D
+=0D
+#pragma pack(1)=0D
+=0D
+typedef struct {=0D
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D
+=0D
+#pragma pack ()=0D
+=0D
+#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \=0D
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \=0D
+ { END_DEVICE_PATH_LENGTH, 0 } \=0D
+ }=0D
+=0D
+#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \=0D
+ { (UINT8) (sizeof (ACPI_HID_DEVICE_PA=
TH)), \=0D
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PA=
TH) >> 8)} \=0D
+ }, \=0D
+ EISA_PNP_ID (0x0A03), UID \=0D
+ }=0D
+=0D
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]=
=3D {=0D
+ {=0D
+ ACPI_DEVICE_PATH_DEF (0),=0D
+ END_DEVICE_PATH_DEF=0D
+ },=0D
+};=0D
+=0D
+GLOBAL_REMOVE_IF_UNREFERENCED=0D
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D {=0D
+ L"Mem", L"I/O", L"Bus"=0D
+};=0D
+=0D
+STATIC PCI_ROOT_BRIDGE mRootBridge =3D {=0D
+ 0, // Segment=0D
+ 0, // Supports=0D
+ 0, // Attributes=0D
+ TRUE, // DmaAbove4G=0D
+ FALSE, // NoExtendedConfigSpace=
=0D
+ FALSE, // ResourceAssigned=0D
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes=
=0D
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,=0D
+ {=0D
+ // Bus=0D
+ FixedPcdGet32 (PcdPciBusMin),=0D
+ FixedPcdGet32 (PcdPciBusMax)=0D
+ }, {=0D
+ // Io=0D
+ FixedPcdGet64 (PcdPciIoBase),=0D
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1=0D
+ }, {=0D
+ // Mem=0D
+ FixedPcdGet32 (PcdPciMmio32Base),=0D
+ FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) -=
1)=0D
+ //0x7FFFFFFF=0D
+ }, {=0D
+ // MemAbove4G=0D
+ FixedPcdGet64 (PcdPciMmio64Base),=0D
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - =
1=0D
+ }, {=0D
+ // PMem=0D
+ MAX_UINT64,=0D
+ 0=0D
+ }, {=0D
+ // PMemAbove4G=0D
+ MAX_UINT64,=0D
+ 0=0D
+ },=0D
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath=0D
+};=0D
+=0D
+/**=0D
+ Return all the root bridge instances in an array.=0D
+=0D
+ @param[out] Count Return the count of root bridge instances.=0D
+=0D
+ @return All the root bridge instances in an array.=0D
+ The array should be passed into PciHostBridgeFreeRootBridges()=0D
+ when it's not used.=0D
+=0D
+**/=0D
+PCI_ROOT_BRIDGE *=0D
+EFIAPI=0D
+PciHostBridgeGetRootBridges (=0D
+ OUT UINTN *Count=0D
+ )=0D
+{=0D
+ *Count =3D 1;=0D
+ return &mRootBridge;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Free the root bridge instances array returned from PciHostBridgeGetRootB=
ridges().=0D
+=0D
+ @param[in] Bridges The root bridge instances array.=0D
+ @param[in] Count The count of the array.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+PciHostBridgeFreeRootBridges (=0D
+ IN PCI_ROOT_BRIDGE *Bridges,=0D
+ IN UINTN Count=0D
+ )=0D
+{=0D
+=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Inform the platform that the resource conflict happens.=0D
+=0D
+ @param[in] HostBridgeHandle Handle of the Host Bridge.=0D
+ @param[in] Configuration Pointer to PCI I/O and PCI memory resource=0D
+ descriptors. The Configuration contains the reso=
urces=0D
+ for all the root bridges. The resource for each =
root=0D
+ bridge is terminated with END descriptor and an=
=0D
+ additional END is appended indicating the end of=
the=0D
+ entire resources. The resource descriptor field=
=0D
+ values follow the description in=0D
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL=
=0D
+ SubmitResources().=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+PciHostBridgeResourceConflict (=0D
+ IN EFI_HANDLE HostBridgeHandle,=0D
+ IN VOID *Configuration=0D
+ )=0D
+{=0D
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;=0D
+ BOOLEAN IsPrefetchable;=0D
+=0D
+ Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;=0D
+ while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) {=0D
+ for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript=
or++) {=0D
+ ASSERT (Descriptor->ResType <=0D
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));=0D
+ DEBUG ((DEBUG_INFO, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n",=0D
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType=
],=0D
+ Descriptor->AddrLen,=0D
+ Descriptor->AddrRangeMax=0D
+ ));=0D
+ if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D
+=0D
+ IsPrefetchable =3D (Descriptor->SpecificFlag &=0D
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) !=
=3D 0;=0D
+=0D
+ DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag =3D %ld / %02x%=
s\n",=0D
+ Descriptor->AddrSpaceGranularity,=0D
+ Descriptor->SpecificFlag,=0D
+ (IsPrefetchable) ? L" (Prefetchable)" : L""=0D
+ ));=0D
+ }=0D
+ }=0D
+ //=0D
+ // Skip the end descriptor for root bridge=0D
+ //=0D
+ ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR);=0D
+ Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (=0D
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1=0D
+ );=0D
+ }=0D
+}=0D
--=20
2.25.1


[PATCH v3 44/46] Silicon/Phytium: Added fvb driver for norflash

Ling Jia <jialing@...>
 

The FlashFvbDxe provided the fvb protocol,
which requested by the flash operators.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | =
1 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | =
1 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 6=
1 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 10=
4 ++
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 130=
4 ++++++++++++++++++++
5 files changed, 1471 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 1c4705144151..99034365d38f 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -253,6 +253,7 @@ [Components.common]
# NOR Flash driver=0D
#=0D
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf=0D
+ Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf=0D
=0D
#=0D
# Usb Support=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 831f7a682837..67458458ddd5 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -103,6 +103,7 @@ [FV.FvMain]
=0D
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf=0D
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf=0D
+ INF Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf=
=0D
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf=0D
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D
=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.i=
nf
new file mode 100644
index 000000000000..ff23721d6e41
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
@@ -0,0 +1,61 @@
+#/** @file=0D
+# Phytium NorFlash Fvb Drivers.=0D
+#=0D
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D FlashFvbDxe=0D
+ FILE_GUID =3D b8923820-3e7c-11eb-b12c-17525e90ecc8=
=0D
+ MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D
+ VERSION_STRING =3D 0.1=0D
+ ENTRY_POINT =3D FvbEntryPoint=0D
+=0D
+[Sources]=0D
+ FlashFvbDxe.c=0D
+ FlashFvbDxe.h=0D
+=0D
+[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ DxeServicesTableLib=0D
+ HobLib=0D
+ MemoryAllocationLib=0D
+ UefiBootServicesTableLib=0D
+ UefiRuntimeLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[Guids]=0D
+ gEfiAuthenticatedVariableGuid=0D
+ gEfiEventVirtualAddressChangeGuid=0D
+ gEfiSystemNvDataFvGuid=0D
+ gEfiVariableGuid=0D
+=0D
+[Protocols]=0D
+ gEfiDevicePathProtocolGuid=0D
+ gEfiFirmwareVolumeBlockProtocolGuid=0D
+ gSpiNorFlashProtocolGuid=0D
+=0D
+[Pcd.common]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize=0D
+=0D
+[Depex]=0D
+ gSpiNorFlashProtocolGuid=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.h b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
new file mode 100644
index 000000000000..e63ff9f220f6
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
@@ -0,0 +1,104 @@
+/** @file=0D
+ Phytium NorFlash Fvb Drivers Header.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+#ifndef FVB_FLASH_DXE_H_=0D
+#define FVB_FLASH_DXE_H_=0D
+=0D
+#include <Protocol/BlockIo.h>=0D
+#include <Protocol/FirmwareVolumeBlock.h>=0D
+#include <Protocol/SpiNorFlashProtocol.h>=0D
+=0D
+#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba=
) * (LbaSize)))=0D
+#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'N', '=
O', 'R')=0D
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, FT_FVB_DEVICE, Fvb=
Protocol, FVB_FLASH_SIGNATURE)=0D
+=0D
+typedef struct _FT_FVB_DEVICE FT_FVB_DEVICE;=0D
+=0D
+#define NOR_FLASH_ERASE_RETRY 10=0D
+=0D
+typedef struct {=0D
+ VENDOR_DEVICE_PATH Vendor;=0D
+ EFI_DEVICE_PATH_PROTOCOL End;=0D
+ } FT_FVB_DEVICE_PATH;=0D
+=0D
+struct _FT_FVB_DEVICE {=0D
+ UINT32 Signature;=0D
+ EFI_HANDLE Handle;=0D
+=0D
+ UINTN DeviceBaseAddress;=0D
+ UINTN RegionBaseAddress;=0D
+ UINTN Size;=0D
+ EFI_LBA StartLba;=0D
+ EFI_BLOCK_IO_MEDIA Media;=0D
+=0D
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;=0D
+=0D
+ FT_FVB_DEVICE_PATH DevicePath;=0D
+ EFI_NORFLASH_DRV_PROTOCOL *SpiFlashProtocol;=0D
+ VOID *ShadowBuffer;=0D
+ UINTN FvbSize;=0D
+ };=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ OUT EFI_FVB_ATTRIBUTES_2 * Attributes=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbSetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN OUT EFI_FVB_ATTRIBUTES_2 * Attributes=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetPhysicalAddress (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ OUT EFI_PHYSICAL_ADDRESS * Address=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetBlockSize (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ OUT UINTN * BlockSize,=0D
+ OUT UINTN * NumberOfBlocks=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbRead (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN * NumBytes,=0D
+ IN OUT UINT8 * Buffer=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbWrite (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN * NumBytes,=0D
+ IN UINT8 * Buffer=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEraseBlocks (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL * This,=0D
+ ...=0D
+ );=0D
+=0D
+#endif // FVB_FLASH_DXE_H_=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbD=
xe.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
new file mode 100644
index 000000000000..e9f7e566b1a0
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
@@ -0,0 +1,1304 @@
+/** @file=0D
+ Phytium NorFlash Fvb Drivers.=0D
+=0D
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/BaseLib.h>=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DxeServicesTableLib.h>=0D
+#include <Library/HobLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiRuntimeLib.h>=0D
+#include <Guid/VariableFormat.h>=0D
+=0D
+#include "FlashFvbDxe.h"=0D
+=0D
+STATIC EFI_EVENT FvbVirtualAddrChangeEvent;=0D
+STATIC FT_FVB_DEVICE *FvbDevice;=0D
+STATIC UINTN mFlashNvStorageVariableBase;=0D
+STATIC UINTN mFlashNvStorageFtwWorkingBase;=0D
+STATIC UINTN mFlashNvStorageFtwSpareBase;=0D
+STATIC UINT32 mFlashNvStorageVariableSize;=0D
+STATIC UINT32 mFlashNvStorageFtwWorkingSize;=0D
+STATIC UINT32 mFlashNvStorageFtwSpareSize;=0D
+=0D
+STATIC FT_FVB_DEVICE FvbFlashInstanceTemplate =3D {=0D
+ FVB_FLASH_SIGNATURE, // Signature=0D
+ NULL, // Handle ... NEED TO BE FILLED=0D
+ 0, // DeviceBaseAddress ... NEED TO BE FILLED=0D
+ 0, // RegionBaseAddress ... NEED TO BE FILLED=0D
+ 0, // Size ... NEED TO BE FILLED=0D
+ 0, // StartLba=0D
+ {=0D
+ 0, // MediaId ... NEED TO BE FILLED=0D
+ FALSE, // RemovableMedia=0D
+ TRUE, // MediaPresent=0D
+ FALSE, // LogicalPartition=0D
+ FALSE, // ReadOnly=0D
+ FALSE, // WriteCaching;=0D
+ 0, // BlockSize ... NEED TO BE FILLED=0D
+ 4, // IoAlign=0D
+ 0, // LastBlock ... NEED TO BE FILLED=0D
+ 0, // LowestAlignedLba=0D
+ 1, // LogicalBlocksPerPhysicalBlock=0D
+ }, //Media;=0D
+ {=0D
+ FvbGetAttributes, // GetAttributes=0D
+ FvbSetAttributes, // SetAttributes=0D
+ FvbGetPhysicalAddress, // GetPhysicalAddress=0D
+ FvbGetBlockSize, // GetBlockSize=0D
+ FvbRead, // Read=0D
+ FvbWrite, // Write=0D
+ FvbEraseBlocks, // EraseBlocks=0D
+ NULL, // ParentHandle=0D
+ }, // FvbProtoccol;=0D
+=0D
+ {=0D
+ {=0D
+ {=0D
+ HARDWARE_DEVICE_PATH,=0D
+ HW_VENDOR_DP,=0D
+ {=0D
+ (UINT8) sizeof (VENDOR_DEVICE_PATH),=0D
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)=0D
+ }=0D
+ },=0D
+ {=0D
+ 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }=0D
+ }, // GUID ... NEED TO BE FILLED=0D
+ },=0D
+ {=0D
+ END_DEVICE_PATH_TYPE,=0D
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,=0D
+ {=0D
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),=0D
+ 0=0D
+ }=0D
+ }=0D
+ }, // DevicePath=0D
+=0D
+ NULL, // SpiFlashProtocol ... NEED TO BE FILLED=0D
+ NULL, // ShadowBuffer ... NEED TO BE FILLED=0D
+ 0 // Fvb Size=0D
+};=0D
+=0D
+=0D
+/**=0D
+ Erases a single block of flash.=0D
+=0D
+ @param[in] FlashInstance The poiter of the fvb device sturct.=0D
+=0D
+ @param[in] BlockAddress Physical address of Lba to be erased.=0D
+=0D
+ @retval EFI_SUCCESS The erase single block request successfull=
y completed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashEraseSingleBlock (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN UINTN BlockAddress=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN Index;=0D
+ EFI_TPL OriginalTPL;=0D
+=0D
+ if ( ! EfiAtRuntime ()) {=0D
+ OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL);=0D
+ } else {=0D
+ OriginalTPL =3D TPL_HIGH_LEVEL;=0D
+ }=0D
+=0D
+ Index =3D 0;=0D
+=0D
+ do {=0D
+ Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAdd=
ress);=0D
+ Index++;=0D
+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status =3D=3D EFI_WRITE_PRO=
TECTED));=0D
+=0D
+ if (Index =3D=3D NOR_FLASH_ERASE_RETRY) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "EraseSingleBlock(BlockAddress=3D0x%08x: BlockLocked Error (try to e=
rase % d times)\n",=0D
+ BlockAddress,=0D
+ Index=0D
+ ));=0D
+ }=0D
+=0D
+ if ( ! EfiAtRuntime ()) {=0D
+ gBS->RestoreTPL (OriginalTPL);=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Readed the specified number of bytes from the form the block to output b=
uffer.=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=
=0D
+=0D
+ @param[in] Lba The starting logical block index to wri=
te to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin=
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[out] Buffer The pointer to a caller-allocated buffe=
r that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbFlashRead() is executed successfully=
.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashRead (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ OUT VOID *Buffer=0D
+ )=0D
+{=0D
+ UINTN Address;=0D
+=0D
+ Address =3D GET_DATA_OFFSET (=0D
+ FlashInstance->RegionBaseAddress,=0D
+ Lba,=0D
+ FlashInstance->Media.BlockSize=0D
+ ) + Offset;=0D
+=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+=0D
+ // The buffer must be valid=0D
+ if (Buffer =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ return FlashInstance->SpiFlashProtocol->Read (Address, Buffer, BufferSiz=
eInBytes);=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Write a full or portion of a block. It must not span block boundaries; t=
hat is,=0D
+ Offset + *NumBytes <=3D FlashInstance->Media.BlockSize.=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=
=0D
+=0D
+ @param[in] Lba The starting logical block index to wri=
te to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin=
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[out] Buffer The pointer to a caller-allocated buffe=
r that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbWriteBlock() is executed successfull=
y.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE The write spaned block boundaries.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbWriteBlock (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ IN UINT8 *Buffer=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINTN BlockSize;=0D
+ UINTN BlockAddress;=0D
+=0D
+ // Detect WriteDisabled state=0D
+ if (FlashInstance->Media.ReadOnly =3D=3D TRUE) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - Can not write:Device is in WriteDisabled sta=
te.\n"=0D
+ ));=0D
+ // It is in WriteDisabled state, return an error right away=0D
+ return EFI_ACCESS_DENIED;=0D
+ }=0D
+=0D
+ // Cache the block size to avoid de-referencing pointers all the time=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+=0D
+ // The write must not span block boundaries.=0D
+ // We need to check each variable individually because adding two large =
values together overflows.=0D
+ if ((Offset >=3D BlockSize) ||=0D
+ (BufferSizeInBytes > BlockSize) ||=0D
+ ((Offset + BufferSizeInBytes) > BlockSize))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset =3D0x %x + NumB=
ytes =3D0x%x) > BlockSize =3D0x%x\n",=0D
+ Offset,=0D
+ BufferSizeInBytes,=0D
+ BlockSize=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to write=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: NumBytes =3D=3D 0\n"=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // Check we did get some memory. Buffer is BlockSize.=0D
+ if (FlashInstance->ShadowBuffer =3D=3D NULL) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbWriteBlock: ERROR - ShadowBuffer is NULL!\n"=0D
+ ));=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ //=0D
+ // Write the word to NOR.=0D
+ //=0D
+ BlockAddress =3D GET_DATA_OFFSET (=0D
+ FlashInstance->RegionBaseAddress,=0D
+ Lba,=0D
+ FlashInstance->Media.BlockSize=0D
+ );=0D
+=0D
+ // Read NOR Flash data into shadow buffer=0D
+ Status =3D FlashInstance->SpiFlashProtocol->Read (=0D
+ BlockAddress,=0D
+ FlashInstance->ShadowBuffer,=0D
+ BlockSize=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ // Put the data at the appropriate location inside the buffer area=0D
+ CopyMem (=0D
+ (VOID *) ((UINTN)FlashInstance->ShadowBuffer + Offset),=0D
+ Buffer,=0D
+ BufferSizeInBytes=0D
+ );=0D
+=0D
+ Status =3D FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAddre=
ss);=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ // Write the modified buffer back to the NorFlash=0D
+ Status =3D FlashInstance->SpiFlashProtocol->Write (BlockAddress,=0D
+ FlashInstance->ShadowBuffer,=0D
+ BlockSize=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ // Return one of the pre-approved error statuses=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Writes the specified number of bytes from the input buffer to the block.=
=0D
+=0D
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.=0D
+=0D
+ @param[in] Lba The starting logical block index to writ=
e to.=0D
+=0D
+ @param[in] Offset Offset into the block at which to begin =
writing.=0D
+=0D
+ @param[in] BufferSizeInBytes The number of bytes to be writed.=0D
+=0D
+ @param[in] Buffer The pointer to a caller-allocated buffer=
that=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS FvbFlashWrite() is executed successfully=
.=0D
+=0D
+ @retval EFI_WRITE_PROTECTED Flash state is in the WriteDisabled stat=
e.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The pointer of Buffer is NULL.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbFlashWrite (=0D
+ IN FT_FVB_DEVICE *FlashInstance,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN UINTN BufferSizeInBytes,=0D
+ IN VOID *Buffer=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT32 BlockSize;=0D
+ UINT32 BlockOffset;=0D
+ UINTN RemainingBytes;=0D
+ UINTN WriteSize;=0D
+=0D
+ if (FlashInstance->Media.ReadOnly =3D=3D TRUE) {=0D
+ return EFI_WRITE_PROTECTED;=0D
+ }=0D
+=0D
+ if (BufferSizeInBytes =3D=3D 0) {=0D
+ return EFI_SUCCESS;=0D
+ }=0D
+=0D
+ if (Buffer =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+ BlockOffset =3D Offset;=0D
+ RemainingBytes =3D BufferSizeInBytes;=0D
+=0D
+ // The write must not span block boundaries.=0D
+ // We need to check each variable individually because adding=0D
+ // two large values together overflows.=0D
+ if (Offset >=3D BlockSize) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: Offset =3D0x%x > BlockS=
ize =3D0x%x\n",=0D
+ Offset,=0D
+ BlockSize=0D
+ ));=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to read=0D
+ // Write either all the remaining bytes, or the number of bytes that bri=
ng=0D
+ // us up to a block boundary, whichever is less.=0D
+ // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next=
=0D
+ // block boundary (even if it is already on one).=0D
+ WriteSize =3D MIN (RemainingBytes, BlockSize - BlockOffset);=0D
+=0D
+ do {=0D
+ Status =3D FvbWriteBlock (=0D
+ FlashInstance,=0D
+ Lba,=0D
+ BlockOffset,=0D
+ WriteSize,=0D
+ Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Now continue writing either all the remaining bytes or single block=
s.=0D
+ RemainingBytes -=3D WriteSize;=0D
+ Buffer =3D (UINT8 *) Buffer + WriteSize;=0D
+ Lba++;=0D
+ BlockOffset =3D 0;=0D
+ WriteSize =3D MIN (RemainingBytes, BlockSize);=0D
+ } while (RemainingBytes);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Initialises the FV Header and Variable Store Header=0D
+ to support variable operations.=0D
+=0D
+ @param[in] Ptr Location to initialise the headers.=0D
+=0D
+ @retval EFI_SUCCESS FvbInitFvAndVariableStoreHeaders()=0D
+ is executed successfully.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbInitFvAndVariableStoreHeaders (=0D
+ IN FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ VOID * Headers;=0D
+ UINTN HeadersLength;=0D
+ UINT32 TempAttributes;=0D
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;=0D
+ VARIABLE_STORE_HEADER *VariableStoreHeader;=0D
+=0D
+ HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) +=0D
+ sizeof (EFI_FV_BLOCK_MAP_ENTRY) +=0D
+ sizeof (VARIABLE_STORE_HEADER);=0D
+=0D
+ Headers =3D AllocateZeroPool (HeadersLength);=0D
+=0D
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area=
=0D
+ // AND the FTW working area AND the FTW Spare contiguous.=0D
+ ASSERT (mFlashNvStorageVariableBase + mFlashNvStorageVariableSize =3D=3D=
mFlashNvStorageFtwWorkingBase);=0D
+ ASSERT (mFlashNvStorageFtwWorkingBase + mFlashNvStorageFtwWorkingSize =
=3D=3D mFlashNvStorageFtwSpareBase);=0D
+=0D
+ // Check if the size of the area is at least one block size=0D
+ ASSERT ((mFlashNvStorageVariableSize > 0) && (mFlashNvStorageVariableSiz=
e / FlashInstance->Media.BlockSize > 0));=0D
+ ASSERT ((mFlashNvStorageFtwWorkingSize > 0) && (mFlashNvStorageFtwWorkin=
gSize / FlashInstance->Media.BlockSize > 0));=0D
+ ASSERT ((mFlashNvStorageFtwSpareSize > 0) && (mFlashNvStorageFtwSpareSiz=
e / FlashInstance->Media.BlockSize > 0));=0D
+=0D
+ // Ensure the Variable area Base Addresses are aligned on a block size b=
oundaries=0D
+ ASSERT (mFlashNvStorageVariableBase % FlashInstance->Media.BlockSize =3D=
=3D 0);=0D
+ ASSERT (mFlashNvStorageFtwWorkingBase % FlashInstance->Media.BlockSize =
=3D=3D 0);=0D
+ ASSERT (mFlashNvStorageFtwSpareBase % FlashInstance->Media.BlockSize =3D=
=3D 0);=0D
+=0D
+ //=0D
+ // EFI_FIRMWARE_VOLUME_HEADER=0D
+ //=0D
+ FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)Headers;=0D
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid=
);=0D
+ FirmwareVolumeHeader->FvLength =3D FlashInstance->FvbSize;=0D
+=0D
+ TempAttributes =3D (=0D
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled=
=0D
+ EFI_FVB2_READ_STATUS | // Reads are currently =
enabled=0D
+ EFI_FVB2_STICKY_WRITE | // A block erase is req=
uired to=0D
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped=
=0D
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bi=
ts take this value=0D
+ EFI_FVB2_WRITE_STATUS | // Writes are currently=
enabled=0D
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enable=
d=0D
+ );=0D
+=0D
+ FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE;=0D
+ FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2) TempAttribut=
es;=0D
+=0D
+ FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE=
R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);=0D
+ FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION;=0D
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D FlashInstance->Media.Las=
tBlock + 1;=0D
+ FirmwareVolumeHeader->BlockMap[0].Length =3D FlashInstance->Media.Blo=
ckSize;=0D
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0;=0D
+ FirmwareVolumeHeader->BlockMap[1].Length =3D 0;=0D
+ FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 (=0D
+ (UINT16 *)FirmwareVolumeHeader,=0D
+ FirmwareVolumeHeader->HeaderLength=0D
+ );=0D
+=0D
+ //=0D
+ // VARIABLE_STORE_HEADER=0D
+ //=0D
+ VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)Headers + Firm=
wareVolumeHeader->HeaderLength);=0D
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui=
d);=0D
+ VariableStoreHeader->Size =3D mFlashNvStorageVariableSize - FirmwareVo=
lumeHeader->HeaderLength;=0D
+ VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED;=0D
+ VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY;=0D
+=0D
+ // Install the combined super-header in the NorFlash=0D
+ Status =3D FvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, =
Headers);=0D
+=0D
+ FreePool (Headers);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Check the integrity of firmware volume header.=0D
+=0D
+ @param[in] FwVolHeader A pointer to a firmware volume header=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume is consistent=0D
+=0D
+ @retval EFI_NOT_FOUND The firmware volume has been corrupted.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+FvbValidateFvHeader (=0D
+ IN FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ UINT16 Checksum;=0D
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;=0D
+ VARIABLE_STORE_HEADER *VariableStoreHeader;=0D
+ UINTN VariableStoreLength;=0D
+ UINTN FvLength;=0D
+=0D
+ FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)GET_DATA_OFFSET (FlashInst=
ance->RegionBaseAddress,=0D
+ FlashInstance->StartLba,=0D
+ FlashInstance->Media.Block=
Size=0D
+ );=0D
+ FvLength =3D FlashInstance->FvbSize;=0D
+=0D
+=0D
+ if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) ||=0D
+ (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) ||=0D
+ (FwVolHeader->FvLength !=3D FvLength))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: No Firmware Volume header present\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ // Check the Firmware Volume Guid=0D
+ if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)=
=3D=3D FALSE ) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: Firmware Volume Guid non-compatible\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ // Verify the header checksum=0D
+ Checksum =3D CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderL=
ength);=0D
+ if (Checksum !=3D 0) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n",=0D
+ Checksum));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ VariableStoreHeader =3D (VARIABLE_STORE_HEADER *) ((UINTN)FwVolHeader + =
FwVolHeader->HeaderLength);=0D
+=0D
+ // Check the Variable Store Guid=0D
+ if ( ! CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) =
&&=0D
+ ! CompareGuid (&VariableStoreHeader->Signature,=0D
+ &gEfiAuthenticatedVariableGuid))=0D
+ {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "%a: Variable Store Guid non-compatible\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ VariableStoreLength =3D mFlashNvStorageVariableSize - FwVolHeader->Heade=
rLength;=0D
+ if (VariableStoreHeader->Size !=3D VariableStoreLength) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "ValidateFvHeader: Variable Store Length does not match\n"=0D
+ ));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetAttributes() function retrieves the attributes and=0D
+ current settings of the block.=0D
+=0D
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL in=
stance.=0D
+=0D
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribu=
tes and=0D
+ current settings are returned.=0D
+ Type EFI_FVB_ATTRIBUTES_2 is defined in=0D
+ EFI_FIRMWARE_VOLUME_HEADER.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume attributes were returned.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes=0D
+ )=0D
+{=0D
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;=0D
+ CONST FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2) (=0D
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled=0D
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled=0D
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bit=
s into EFI_FVB2_ERASE_POLARITY=0D
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped=0D
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this valu=
e (i.e. '1')=0D
+ );=0D
+=0D
+ // Check if it is write protected=0D
+ if (FlashInstance->Media.ReadOnly !=3D TRUE) {=0D
+ FlashFvbAttributes =3D FlashFvbAttributes |=0D
+ EFI_FVB2_WRITE_STATUS | // Writes are curren=
tly enabled=0D
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be ena=
bled=0D
+ }=0D
+=0D
+ *Attributes =3D FlashFvbAttributes;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbSetAttributes() function sets configurable firmware volume attrib=
utes=0D
+ and returns the new settings of the firmware volume.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst=
ance.=0D
+=0D
+ @param Attributes On input, Attributes is a pointer to=0D
+ EFI_FVB_ATTRIBUTES_2 that contains the d=
esired=0D
+ firmware volume settings.=0D
+ On successful return, it contains the ne=
w=0D
+ settings of the firmware volume.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume attributes were retu=
rned.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict=
with=0D
+ the capabilities as declared in the firm=
ware=0D
+ volume header.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbSetAttributes (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes=0D
+ )=0D
+{=0D
+ return EFI_UNSUPPORTED;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetPhysicalAddress() function retrieves the base address of=0D
+ a memory-mapped firmware volume. This function should be called=0D
+ only for memory-mapped firmware volumes.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.=
=0D
+=0D
+ @param Address Pointer to a caller-allocated=0D
+ EFI_PHYSICAL_ADDRESS that, on successful=0D
+ return from GetPhysicalAddress(), contains the=
=0D
+ base address of the firmware volume.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume base address was returned.=
=0D
+=0D
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetPhysicalAddress (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ OUT EFI_PHYSICAL_ADDRESS *Address=0D
+ )=0D
+{=0D
+ ASSERT (Address !=3D NULL);=0D
+=0D
+ *Address =3D mFlashNvStorageVariableBase;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The FvbGetBlockSize() function retrieves the size of the requested=0D
+ block. It also returns the number of additional blocks with=0D
+ the identical size. The FvbGetBlockSize() function is used to=0D
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).=0D
+=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL inst=
ance.=0D
+=0D
+ @param Lba Indicates the block whose size to return=
.=0D
+=0D
+ @param BlockSize Pointer to a caller-allocated UINTN in w=
hich=0D
+ the size of the block is returned.=0D
+=0D
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in=0D
+ which the number of consecutive blocks,=
=0D
+ starting with Lba, is returned. All=0D
+ blocks in this range have a size of=0D
+ BlockSize.=0D
+=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume base address was ret=
urned.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbGetBlockSize (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ OUT UINTN *BlockSize,=0D
+ OUT UINTN *NumberOfBlocks=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ if (Lba > FlashInstance->Media.LastBlock) {=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ } else {=0D
+ // This is easy because in this platform each NorFlash device has equa=
l sized blocks.=0D
+ *BlockSize =3D (UINTN) FlashInstance->Media.BlockSize;=0D
+ *NumberOfBlocks =3D (UINTN) (FlashInstance->Media.LastBlock - Lba + 1)=
;=0D
+ Status =3D EFI_SUCCESS;=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Reads the specified number of bytes into a buffer from the specified blo=
ck.=0D
+=0D
+ The FvbRead() function reads the requested number of bytes from the=0D
+ requested block and stores them in the provided buffer.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance=
.=0D
+=0D
+ @param Lba The starting logical block index from which =
to read.=0D
+=0D
+ @param Offset Offset into the block at which to begin read=
ing.=0D
+=0D
+ @param NumBytes Pointer to a UINTN.=0D
+ At entry, *NumBytes contains the total size =
of the=0D
+ buffer.=0D
+ At exit, *NumBytes contains the total number=
of=0D
+ bytes read.=0D
+=0D
+ @param Buffer Pointer to a caller-allocated buffer that wi=
ll be=0D
+ used to hold the data that is read.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume was read successfully, a=
nd=0D
+ contents are in Buffer.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.=0D
+ On output, NumBytes contains the total numbe=
r of=0D
+ bytes returned in Buffer.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled s=
tate.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctl=
y and=0D
+ could not be read.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbRead (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN *NumBytes,=0D
+ IN OUT UINT8 *Buffer=0D
+ )=0D
+{=0D
+ UINTN BlockSize;=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+ EFI_STATUS Status;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ // Cache the block size to avoid de-referencing pointers all the time=0D
+ BlockSize =3D FlashInstance->Media.BlockSize;=0D
+=0D
+ // The read must not span block boundaries.=0D
+ // We need to check each variable individually because adding two large =
values together overflows.=0D
+ if ((Offset >=3D BlockSize) ||=0D
+ (*NumBytes > BlockSize) ||=0D
+ ((Offset + *NumBytes) > BlockSize)) {=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ // We must have some bytes to read=0D
+ if (*NumBytes =3D=3D 0) {=0D
+ return EFI_BAD_BUFFER_SIZE;=0D
+ }=0D
+=0D
+ Status =3D FvbFlashRead (=0D
+ FlashInstance,=0D
+ FlashInstance->StartLba + Lba,=0D
+ Offset,=0D
+ *NumBytes,=0D
+ Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Writes the specified number of bytes from the input buffer to the block.=
=0D
+=0D
+ The FvbWrite() function writes the specified number of bytes from=0D
+ the provided buffer to the specified block and offset.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance=
.=0D
+=0D
+ @param Lba The starting logical block index to write to=
.=0D
+=0D
+ @param Offset Offset into the block at which to begin writ=
ing.=0D
+=0D
+ @param NumBytes The pointer to a UINTN.=0D
+ At entry, *NumBytes contains the total size =
of the=0D
+ buffer.=0D
+ At exit, *NumBytes contains the total number=
of=0D
+ bytes actually written.=0D
+=0D
+ @param Buffer The pointer to a caller-allocated buffer tha=
t=0D
+ contains the source for the write.=0D
+=0D
+ @retval EFI_SUCCESS The firmware volume was written successfully=
.=0D
+=0D
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA bounda=
ry.=0D
+ On output, NumBytes contains the total numbe=
r of=0D
+ bytes actually written.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled =
state.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could=
not be=0D
+ written.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbWrite (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ IN EFI_LBA Lba,=0D
+ IN UINTN Offset,=0D
+ IN OUT UINTN *NumBytes,=0D
+ IN UINT8 *Buffer=0D
+ )=0D
+{=0D
+ FT_FVB_DEVICE *FlashInstance;=0D
+=0D
+ FlashInstance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ return FvbFlashWrite (FlashInstance,=0D
+ FlashInstance->StartLba + Lba,=0D
+ Offset,=0D
+ *NumBytes,=0D
+ Buffer=0D
+ );=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Erases and initialises a firmware volume block.=0D
+=0D
+ The FvbEraseBlocks() function erases one or more blocks as denoted=0D
+ by the variable argument list.=0D
+=0D
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL=0D
+ instance.=0D
+=0D
+ @param ... The variable argument list is a list of =
tuples.=0D
+ Each tuple describes a range of LBAs to =
erase=0D
+ and consists of the following:=0D
+ An EFI_LBA that indicates the starting L=
BA=0D
+ A UINTN that indicates the number of blo=
cks=0D
+ to erase.=0D
+=0D
+ The list is terminated with an=0D
+ EFI_LBA_LIST_TERMINATOR.=0D
+=0D
+ @retval EFI_SUCCESS The erase request successfully completed=
.=0D
+=0D
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisab=
led=0D
+ state.=0D
+=0D
+ @retval EFI_DEVICE_ERROR The block device is not functioning corr=
ectly=0D
+ and could not be written.=0D
+ The firmware device may have been partia=
lly=0D
+ erased.=0D
+=0D
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the va=
riable=0D
+ argument list do not exist in the firmwa=
re=0D
+ volume.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEraseBlocks (=0D
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,=0D
+ ...=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ VA_LIST Args;=0D
+ UINTN BlockAddress; // Physical address of Lba to erase=0D
+ EFI_LBA StartingLba; // Lba from which we start erasing=0D
+ UINTN NumOfLba; // Number of Lba blocks to erase=0D
+ FT_FVB_DEVICE *Instance;=0D
+=0D
+ Instance =3D INSTANCE_FROM_FVB_THIS (This);=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+=0D
+ // Detect WriteDisabled state=0D
+ if (Instance->Media.ReadOnly =3D=3D TRUE) {=0D
+ // Firmware volume is in WriteDisabled state=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"=0D
+ ));=0D
+ return EFI_ACCESS_DENIED;=0D
+ }=0D
+=0D
+ // Before erasing, check the entire list of parameters to ensure all spe=
cified blocks are valid=0D
+=0D
+ VA_START (Args, This);=0D
+ do {=0D
+ // Get the Lba from which we start erasing=0D
+ StartingLba =3D VA_ARG (Args, EFI_LBA);=0D
+=0D
+ // Have we reached the end of the list?=0D
+ if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) {=0D
+ //Exit the while loop=0D
+ break;=0D
+ }=0D
+=0D
+ // How many Lba blocks are we requested to erase?=0D
+ NumOfLba =3D VA_ARG (Args, UINT32);=0D
+=0D
+ // All blocks must be within range=0D
+ if ((NumOfLba =3D=3D 0) || ((Instance->StartLba + StartingLba + NumOfL=
ba - 1) > Instance->Media.LastBlock)) {=0D
+ VA_END (Args);=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"=0D
+ ));=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ goto EXIT;=0D
+ }=0D
+ } while (TRUE);=0D
+=0D
+ VA_END (Args);=0D
+=0D
+ //=0D
+ // To get here, all must be ok, so start erasing=0D
+ //=0D
+ VA_START (Args, This);=0D
+ do {=0D
+ // Get the Lba from which we start erasing=0D
+ StartingLba =3D VA_ARG (Args, EFI_LBA);=0D
+=0D
+ // Have we reached the end of the list?=0D
+ if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) {=0D
+ // Exit the while loop=0D
+ break;=0D
+ }=0D
+=0D
+ // How many Lba blocks are we requested to erase?=0D
+ NumOfLba =3D VA_ARG (Args, UINT32);=0D
+=0D
+ // Go through each one and erase it=0D
+ while (NumOfLba > 0) {=0D
+ // Get the physical address of Lba to erase=0D
+ BlockAddress =3D GET_DATA_OFFSET (=0D
+ Instance->RegionBaseAddress,=0D
+ Instance->StartLba + StartingLba,=0D
+ Instance->Media.BlockSize=0D
+ );=0D
+=0D
+ // Erase it=0D
+ Status =3D FvbFlashEraseSingleBlock (Instance, BlockAddress);=0D
+ if (EFI_ERROR (Status)) {=0D
+ VA_END (Args);=0D
+ Status =3D EFI_DEVICE_ERROR;=0D
+ goto EXIT;=0D
+ }=0D
+=0D
+ // Move to the next Lba=0D
+ StartingLba++;=0D
+ NumOfLba--;=0D
+ }=0D
+ } while (TRUE);=0D
+=0D
+ VA_END (Args);=0D
+=0D
+EXIT:=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function inited the NorFlash instance.=0D
+=0D
+ @param[in][out] FlashInstance The pointer of FT_FVB_DEVICE instance.=0D
+=0D
+ @retval EFI_SUCCESS PhytNorFlashFvbInitialize() is executed =
successfully.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+PhytNorFlashFvbInitialize (=0D
+ IN OUT FT_FVB_DEVICE *FlashInstance=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT32 FvbNumLba;=0D
+ EFI_BOOT_MODE BootMode;=0D
+ UINTN TotalFvbSize;=0D
+=0D
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME=0D
+ Status =3D gDS->AddMemorySpace (=0D
+ EfiGcdMemoryTypeMemoryMappedIo,=0D
+ mFlashNvStorageVariableBase,=0D
+ FlashInstance->FvbSize,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ Status =3D gDS->SetMemorySpaceAttributes (=0D
+ mFlashNvStorageVariableBase,=0D
+ FlashInstance->FvbSize,=0D
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ TotalFvbSize =3D FlashInstance->FvbSize;=0D
+=0D
+ // Set the index of the first LBA for the FVB=0D
+ FlashInstance->StartLba =3D (mFlashNvStorageVariableBase - FlashInstance=
->RegionBaseAddress) / FlashInstance->Media.BlockSize;=0D
+=0D
+ BootMode =3D GetBootModeHob ();=0D
+ if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) {=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ } else {=0D
+ // Determine if there is a valid header at the beginning of the NorFla=
sh=0D
+ Status =3D FvbValidateFvHeader (FlashInstance);=0D
+ }=0D
+=0D
+ // Install the Default FVB header if required=0D
+ if (EFI_ERROR (Status)) {=0D
+ // There is no valid header, so time to install one.=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "NorFlashFvbInitialize: ERROR - The FVB Header is invalid. Installin=
g a correct one for this volume.\n"=0D
+ ));=0D
+=0D
+ // Erase all the NorFlash that is reserved for variable storage=0D
+ FvbNumLba =3D TotalFvbSize / FlashInstance->Media.BlockSize;=0D
+=0D
+ Status =3D FvbEraseBlocks (=0D
+ &FlashInstance->FvbProtocol,=0D
+ (EFI_LBA)0,=0D
+ FvbNumLba,=0D
+ EFI_LBA_LIST_TERMINATOR=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ // Install all appropriate headers=0D
+ Status =3D FvbInitFvAndVariableStoreHeaders (FlashInstance);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The CreateInstance() function Create Fvb Instance.=0D
+=0D
+ @retval EFI_SUCCESS Create Instance successfully.=0D
+=0D
+ @retval other Create Instance failed.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+CreateInstance (=0D
+ VOID=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevice;=0D
+=0D
+ // Locate flash protocols=0D
+ Status =3D gBS->LocateProtocol (&gSpiNorFlashProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&FvbDevice->SpiFlashProtocol);=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "Cannot locate NorFlash protocol.\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ NorFlashDevice =3D AllocateRuntimePool (sizeof (NOR_FLASH_DEVICE_DESCRIP=
TION));=0D
+ if (NorFlashDevice =3D=3D NULL) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "Cannot Allocate NorFlashDevice Pool.\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D FvbDevice->SpiFlashProtocol->GetDevices (NorFlashDevice);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D FvbDevice->SpiFlashProtocol->Initialization ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ FvbDevice->DeviceBaseAddress =3D NorFlashDevice->DeviceBaseAddress;=0D
+ FvbDevice->RegionBaseAddress =3D NorFlashDevice->RegionBaseAddress;=0D
+ FvbDevice->Size =3D NorFlashDevice->Size;=0D
+=0D
+ FvbDevice->Media.MediaId =3D 0;=0D
+ FvbDevice->Media.BlockSize =3D NorFlashDevice->BlockSize;=0D
+ FvbDevice->Media.LastBlock =3D (FvbDevice->Size / FvbDevice->Media.Block=
Size) - 1;=0D
+ FvbDevice->FvbSize =3D mFlashNvStorageVariableBase +=0D
+ mFlashNvStorageFtwWorkingBase +=0D
+ mFlashNvStorageFtwSpareBase;=0D
+=0D
+ CopyGuid (&FvbDevice->DevicePath.Vendor.Guid, &NorFlashDevice->Guid);=0D
+=0D
+ FvbDevice->ShadowBuffer =3D AllocateRuntimePool (FvbDevice->Media.BlockS=
ize);=0D
+ if (FvbDevice->ShadowBuffer =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &FvbDevice->Handle,=0D
+ &gEfiDevicePathProtocolGuid,=0D
+ &FvbDevice->DevicePath,=0D
+ &gEfiFirmwareVolumeBlockProtocolGuid,=0D
+ &FvbDevice->FvbProtocol,=0D
+ NULL=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ FreePool (FvbDevice);=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D PhytNorFlashFvbInitialize (FvbDevice);=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "PhytNorFlashFvbInitialize: Fail to init NorFlash devices\n"=0D
+ ));=0D
+ return Status;=0D
+ }=0D
+=0D
+ FreePool (NorFlashDevice);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Fixup internal data so that EFI can be call in virtual mode.=0D
+ Call the passed in Child Notify event and convert any pointers=0D
+ in lib to virtual mode.=0D
+=0D
+ @param[in] Event The Event that is being processed.=0D
+=0D
+ @param[in] Context Event Context.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+STATIC=0D
+VOID=0D
+EFIAPI=0D
+FvbVirtualNotifyEvent (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ // Convert SpiFlashProtocol=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Erase);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Write);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Read);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->GetDevice=
s);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->Initializ=
ation);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol->EraseSing=
leBlock);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice->SpiFlashProtocol);=0D
+=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwWorkingBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageFtwSpareBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&FvbDevice);=0D
+=0D
+ return;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function is the entrypoint of the fvb driver.=0D
+=0D
+ @param[in] ImageHandle The firmware allocated handle for the EFI imag=
e.=0D
+=0D
+ @param[in] SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+FvbEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ FvbDevice =3D AllocateRuntimeCopyPool (=0D
+ sizeof (FvbFlashInstanceTemplate),=0D
+ &FvbFlashInstanceTemplate=0D
+ );=0D
+ if (FvbDevice =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariab=
leBase64);=0D
+ mFlashNvStorageFtwWorkingBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwWor=
kingBase64);=0D
+ mFlashNvStorageFtwSpareBase =3D FixedPcdGet64 (PcdFlashNvStorageFtwSpa=
reBase64);=0D
+ mFlashNvStorageVariableSize =3D FixedPcdGet64 (PcdFlashNvStorageVariab=
leSize);=0D
+ mFlashNvStorageFtwWorkingSize =3D FixedPcdGet64 (PcdFlashNvStorageFtwWor=
kingSize);=0D
+ mFlashNvStorageFtwSpareSize =3D FixedPcdGet64 (PcdFlashNvStorageFtwSpa=
reSize);=0D
+=0D
+ Status =3D CreateInstance ();=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((=0D
+ DEBUG_ERROR,=0D
+ "CreateInstance: Fail to create instance for NorFlash\n"=0D
+ ));=0D
+ }=0D
+=0D
+//=0D
+// Register for the virtual address change event=0D
+//=0D
+ Status =3D gBS->CreateEventEx (=0D
+ EVT_NOTIFY_SIGNAL,=0D
+ TPL_NOTIFY,=0D
+ FvbVirtualNotifyEvent,=0D
+ NULL,=0D
+ &gEfiEventVirtualAddressChangeGuid,=0D
+ &FvbVirtualAddrChangeEvent=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.25.1


[PATCH v3 43/46] Silicon/Phytium: Added flash driver support to Phytium Silicon

Ling Jia <jialing@...>
 

The SpiNorFlashDxe provided norflash initialization,
read-write, erase and other interfaces.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | =
1 +
Platform/Phytium/DurianPkg/DurianPkg.dsc | =
5 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | =
1 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | =
48 +++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | =
99 +++++
Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | =
74 ++++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | =
424 ++++++++++++++++++++
7 files changed, 652 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico=
n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 69842b89e021..2686ba3cc3a2 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -48,3 +48,4 @@ [PcdsFixedAtBuild.common]
=0D
[Protocols]=0D
gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0=
x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}=0D
+ gSpiNorFlashProtocolGuid =3D { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a,=
0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 68698d613f96..1c4705144151 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -249,6 +249,11 @@ [Components.common]
#=0D
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
=0D
+ #=0D
+ # NOR Flash driver=0D
+ #=0D
+ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf=0D
+=0D
#=0D
# Usb Support=0D
#=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index 1cf1927484db..831f7a682837 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -96,6 +96,7 @@ [FV.FvMain]
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
=0D
INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
+ INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.in=
f=0D
=0D
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu=
ntimeDxe.inf=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash=
Dxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe=
.inf
new file mode 100644
index 000000000000..2933dc502eed
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
@@ -0,0 +1,48 @@
+#/** @file=0D
+# Phytium NorFlash Drivers.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D SpiNorFlashDxe=0D
+ FILE_GUID =3D f37ef706-187c-48fd-9102-ddbf86f551be=
=0D
+ MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D NorFlashPlatformEntryPoint=0D
+=0D
+[Sources.common]=0D
+ SpiNorFlashDxe.c=0D
+ SpiNorFlashDxe.h=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ IoLib=0D
+ UefiLib=0D
+ UefiBootServicesTableLib=0D
+ UefiRuntimeLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[FixedPcd]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase=0D
+[Guids]=0D
+ gEfiEventVirtualAddressChangeGuid=0D
+=0D
+[Protocols]=0D
+ gSpiMasterProtocolGuid=0D
+ gSpiNorFlashProtocolGuid=0D
+=0D
+ [Depex]=0D
+ TRUE=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash=
Dxe.h b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
new file mode 100644
index 000000000000..55f5e8273f7f
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
@@ -0,0 +1,99 @@
+/** @file=0D
+ Phytium NorFlash Drivers Header.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef SPI_NORFLASH_DXE_H_=0D
+#define SPI_NORFLASH_DXE_H_=0D
+=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Library/UefiRuntimeLib.h>=0D
+#include <Protocol/SpiProtocol.h>=0D
+#include <Protocol/SpiNorFlashProtocol.h>=0D
+=0D
+//=0D
+// Norflash registers=0D
+//=0D
+#define REG_FLASH_CAP 0x000=0D
+#define REG_RD_CFG 0x004=0D
+#define REG_WR_CFG 0x008=0D
+#define REG_FLUSH_REG 0x00C=0D
+#define REG_CMD_PORT 0x010=0D
+#define REG_ADDR_PORT 0x014=0D
+#define REG_HD_PORT 0x018=0D
+#define REG_LD_PORT 0x01C=0D
+#define REG_CS_CFG 0x020=0D
+#define REG_WIP_CFG 0x024=0D
+#define REG_WP_REG 0x028=0D
+=0D
+#define NORFLASH_SIGNATURE SIGNATURE_32 ('F', 'T', 'S', 'F')=0D
+=0D
+extern EFI_GUID gSpiMasterProtocolGuid;=0D
+extern EFI_GUID gSpiNorFlashProtocolGuid;=0D
+=0D
+//=0D
+// Platform Nor Flash Functions=0D
+//=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformEraseSingleBlock (=0D
+ IN UINTN BlockAddress=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformErase (=0D
+ IN UINT64 Offset,=0D
+ IN UINT64 Length=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformRead (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ OUT UINT32 Len=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformWrite (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ IN UINT32 Len=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformGetDevices (=0D
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformInitialization (=0D
+ VOID=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ );=0D
+=0D
+typedef struct {=0D
+ EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;=0D
+ UINTN Signature;=0D
+ EFI_HANDLE Handle;=0D
+} NorFlash_Device;=0D
+=0D
+#endif // SPI_NORFLASH_DXE_H_=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashP=
rotocol.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashPr=
otocol.h
new file mode 100644
index 000000000000..b3ae26c5d44f
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol=
.h
@@ -0,0 +1,74 @@
+/** @file=0D
+ The Header of Protocol For NorFlash.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef SPI_NORFALSH_H_=0D
+#define SPI_NORFALSH_H_=0D
+=0D
+typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;=0D
+extern EFI_GUID gSpiNorFlashProtocolGuid;=0D
+=0D
+typedef struct {=0D
+ UINTN DeviceBaseAddress; // Start address of the Device Base Ad=
dress (DBA)=0D
+ UINTN RegionBaseAddress; // Start address of one single region=
=0D
+ UINTN Size;=0D
+ UINTN BlockSize;=0D
+ EFI_GUID Guid;=0D
+} NOR_FLASH_DEVICE_DESCRIPTION;=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (=0D
+ IN UINT64 Offset,=0D
+ IN UINT64 Length=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (=0D
+ IN UINTN BlockAddress=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ OUT UINT32 Len=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ IN UINT32 Len=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (=0D
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (=0D
+ VOID=0D
+ );=0D
+=0D
+struct _EFI_NORFLASH_DRV_PROTOCOL{=0D
+ NORFLASH_PLATFORM_INIT_INTERFACE Initialization;=0D
+ NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices;=0D
+ NORFLASH_PLATFORM_ERASE_INTERFACE Erase;=0D
+ NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock;=0D
+ NORFLASH_PLATFORM_READ_INTERFACE Read;=0D
+ NORFLASH_PLATFORM_WRITE_INTERFACE Write;=0D
+};=0D
+=0D
+#endif // SPI_NORFALSH_H_=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlash=
Dxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
new file mode 100644
index 000000000000..1c339c447858
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
@@ -0,0 +1,424 @@
+/** @file=0D
+ Phytium NorFlash Drivers.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "SpiNorFlashDxe.h"=0D
+=0D
+typedef struct {=0D
+ UINT32 Flash_Index;=0D
+ UINT32 Flash_Write;=0D
+ UINT32 Flash_Erase;=0D
+ UINT32 Flash_Pp;=0D
+} FLASH_CMD_INFO;=0D
+=0D
+STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent;=0D
+STATIC UINTN mNorFlashControlBase;=0D
+STATIC UINT8 mCmdWrite;=0D
+STATIC UINT8 mCmdEares;=0D
+STATIC UINT8 mCmdPp;=0D
+=0D
+#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase)=0D
+#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize)=0D
+=0D
+EFI_SPI_DRV_PROTOCOL *mSpiMasterProtocol;=0D
+NorFlash_Device *mFlashInstance;=0D
+=0D
+NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices =3D {=0D
+ SPI_FLASH_BASE, /* Device Base Address */=0D
+ SPI_FLASH_BASE, /* Region Base Address */=0D
+ SIZE_1MB * 16, /* Size */=0D
+ SIZE_64KB, /* Block Size */=0D
+ {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5=
E, 0x59 } }=0D
+};=0D
+=0D
+=0D
+/**=0D
+ This function writed up to 256 bytes to flash through spi driver.=0D
+=0D
+ @param[in] Address The address of the flash.=0D
+ @param[in] Buffer The pointer of buffer to be writed.=0D
+ @param[in] BufferSizeInBytes The bytes to be writed.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashWrite256() is executed successfull=
y.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+NorFlashWrite256 (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ IN UINT32 BufferSizeInBytes=0D
+ )=0D
+{=0D
+ UINT32 Index;=0D
+ UINT8 CmdId;=0D
+ UINT32 *TempBuffer;=0D
+ UINT8 WriteSize;=0D
+=0D
+ TempBuffer =3D Buffer;=0D
+ WriteSize =3D sizeof (UINT32);=0D
+=0D
+ if (BufferSizeInBytes > 256) {=0D
+ DEBUG ((DEBUG_ERROR, "The max length is 256 bytes.\n"));=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ if ((BufferSizeInBytes % WriteSize) !=3D 0) {=0D
+ DEBUG ((DEBUG_ERROR, "The length must four bytes aligned.\n"));=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ if ((Address % WriteSize) !=3D 0) {=0D
+ DEBUG ((DEBUG_ERROR, "The address must four bytes aligned.\n"));=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ CmdId =3D mCmdPp;=0D
+ mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT);=0D
+ mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D
+=0D
+ CmdId =3D mCmdWrite;=0D
+ mSpiMasterProtocol->SpiSetConfig (CmdId, 0x000208, REG_WR_CFG);=0D
+=0D
+ for (Index =3D 0; Index < (BufferSizeInBytes / WriteSize); Index++) {=0D
+ MmioWrite32 ((Address + (Index * WriteSize)), TempBuffer[Index]);=0D
+ }=0D
+=0D
+ mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);=0D
+=0D
+ mSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+/**=0D
+ This function erased a sector of flash through spi driver.=0D
+=0D
+ @param[in] BlockAddress The sector address to be erased.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+STATIC=0D
+inline void=0D
+NorFlashPlatformEraseSector (=0D
+ IN UINTN BlockAddress=0D
+ )=0D
+{=0D
+ UINT8 CmdId;=0D
+=0D
+ CmdId =3D mCmdPp;=0D
+ mSpiMasterProtocol->SpiSetConfig (CmdId, 0x400000, REG_CMD_PORT);=0D
+ mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D
+=0D
+ CmdId =3D mCmdEares;=0D
+ mSpiMasterProtocol->SpiSetConfig (CmdId, 0x408000, REG_CMD_PORT);=0D
+ mSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);=0D
+ mSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D
+=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Fixup internal data so that EFI can be call in virtual mode.=0D
+ Call the passed in Child Notify event and convert any pointers in=0D
+ lib to virtual mode.=0D
+=0D
+ @param[in] Event The Event that is being processed.=0D
+=0D
+ @param[in] Context Event Context.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+PlatformNorFlashVirtualNotifyEvent (=0D
+ IN EFI_EVENT Event,=0D
+ IN VOID *Context=0D
+ )=0D
+{=0D
+ EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase);=0D
+ EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiGetConfig);=0D
+ EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol->SpiSetConfig);=0D
+ EfiConvertPointer (0x0, (VOID **)&mSpiMasterProtocol);=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function inited the flash platform.=0D
+=0D
+ @param None.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformInitialization() is execut=
ed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformInitialization (=0D
+ VOID=0D
+ )=0D
+{=0D
+=0D
+ mCmdWrite =3D 0x2;=0D
+ mCmdEares =3D 0xD8;=0D
+ mCmdPp =3D 0x6;=0D
+=0D
+ mNorFlashControlBase =3D FixedPcdGet64 (PcdSpiControllerBase);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function geted the flash device information.=0D
+=0D
+ @param[out] NorFlashDevices the pointer to store flash device informa=
tion.=0D
+ @param[out] Count the number of the flash device.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed s=
uccessfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformGetDevices (=0D
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D
+ )=0D
+{=0D
+=0D
+ *NorFlashDevices =3D mNorFlashDevices;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function readed flash content form the specified area of flash.=0D
+=0D
+ @param[in] Address The address of the flash.=0D
+ @param[in] Buffer The pointer of the Buffer to be stored.=0D
+ @param[out] Len The bytes readed form flash.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformRead() is executed succes=
sfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformRead (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ OUT UINT32 Len=0D
+ )=0D
+{=0D
+=0D
+ DEBUG ((DEBUG_BLKIO,=0D
+ "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Len:0x%x\n",=0D
+ Address, Buffer, Len=0D
+ ));=0D
+=0D
+ CopyMem ((VOID *)Buffer, (VOID *)Address, Len);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function erased one block flash content.=0D
+=0D
+ @param[in] BlockAddress the BlockAddress to be erased.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is exe=
cuted successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformEraseSingleBlock (=0D
+ IN UINTN BlockAddress=0D
+ )=0D
+{=0D
+=0D
+ NorFlashPlatformEraseSector (BlockAddress);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function erased the flash content of the specified area.=0D
+=0D
+ @param[in] Offset the offset of the flash.=0D
+ @param[in] Length length to be erased.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformErase() is executed succe=
ssfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformErase (=0D
+ IN UINT64 Offset,=0D
+ IN UINT64 Length=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ UINT64 Index;=0D
+ UINT64 Count;=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+ if ((Length % SIZE_64KB) =3D=3D 0) {=0D
+ Count =3D Length / SIZE_64KB;=0D
+ for (Index =3D 0; Index < Count; Index++) {=0D
+ NorFlashPlatformEraseSingleBlock (Offset);=0D
+ Offset +=3D SIZE_64KB;=0D
+ }=0D
+ } else {=0D
+ Status =3D EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function writed data to flash.=0D
+=0D
+ @param[in] Address the address of the flash.=0D
+=0D
+ @param[in] Buffer the pointer of the Buffer to be writed.=0D
+=0D
+ @param[in] BufferSizeInBytes the bytes of the Buffer.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformWrite() is executed succe=
ssfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformWrite (=0D
+ IN UINTN Address,=0D
+ IN VOID *Buffer,=0D
+ IN UINT32 BufferSizeInBytes=0D
+ )=0D
+{=0D
+ UINT32 Index;=0D
+ UINT32 Remainder;=0D
+ UINT32 Quotient;=0D
+ EFI_STATUS Status;=0D
+ UINTN TmpAddress;=0D
+=0D
+ TmpAddress =3D Address;=0D
+ Remainder =3D BufferSizeInBytes % 256;=0D
+ Quotient =3D BufferSizeInBytes / 256;=0D
+=0D
+ if (BufferSizeInBytes <=3D 256) {=0D
+ Status =3D NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);=0D
+ } else {=0D
+ for (Index =3D 0; Index < Quotient; Index++) {=0D
+ Status =3D NorFlashWrite256 (TmpAddress, Buffer, 256);=0D
+ TmpAddress +=3D 256;=0D
+ Buffer +=3D 256;=0D
+ }=0D
+=0D
+ if (Remainder !=3D 0) {=0D
+ Status =3D NorFlashWrite256 (TmpAddress, Buffer, Remainder);=0D
+ }=0D
+ }=0D
+=0D
+ if (EFI_ERROR (Status)) {=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function inited the flash driver protocol.=0D
+=0D
+ @param[in] NorFlashProtocol A pointer to the norflash protocol struct=
.=0D
+=0D
+ @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed suc=
cessfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformInitProtocol (=0D
+ IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol=0D
+ )=0D
+{=0D
+ NorFlashProtocol->Initialization =3D NorFlashPlatformInitialization;=
=0D
+ NorFlashProtocol->GetDevices =3D NorFlashPlatformGetDevices;=0D
+ NorFlashProtocol->Erase =3D NorFlashPlatformErase;=0D
+ NorFlashProtocol->EraseSingleBlock =3D NorFlashPlatformEraseSingleBlock=
;=0D
+ NorFlashProtocol->Read =3D NorFlashPlatformRead;=0D
+ NorFlashProtocol->Write =3D NorFlashPlatformWrite;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function is the entrypoint of the norflash driver.=0D
+=0D
+ @param[in] ImageHandle The firmware allocated handle for the EFI imag=
e.=0D
+=0D
+ @param[in] SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+NorFlashPlatformEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ Status =3D gBS->LocateProtocol (=0D
+ &gSpiMasterProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&mSpiMasterProtocol=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return EFI_DEVICE_ERROR;=0D
+ }=0D
+=0D
+ mFlashInstance =3D AllocateRuntimeZeroPool (sizeof (NorFlash_Device));=0D
+ if (mFlashInstance =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ NorFlashPlatformInitProtocol (&mFlashInstance->FlashProtocol);=0D
+=0D
+ mFlashInstance->Signature =3D NORFLASH_SIGNATURE;=0D
+=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &(mFlashInstance->Handle),=0D
+ &gSpiNorFlashProtocolGuid,=0D
+ &(mFlashInstance->FlashProtocol),=0D
+ NULL=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ //Register for the virtual address change event=0D
+ Status =3D gBS->CreateEventEx (=0D
+ EVT_NOTIFY_SIGNAL,=0D
+ TPL_NOTIFY,=0D
+ PlatformNorFlashVirtualNotifyEvent,=0D
+ NULL,=0D
+ &gEfiEventVirtualAddressChangeGuid,=0D
+ &mSpiNorFlashVirtualAddrChangeEvent=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
--=20
2.25.1


[PATCH v3 42/46] Silicon/Phytium: Added Spi driver support to FT2000/4

Ling Jia <jialing@...>
 

The SpiDxe is to provide Spi bus read-write interfaces.

v3:
Optimized the codes to conform to specifications.

Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 9 +
Platform/Phytium/DurianPkg/DurianPkg.dsc | 5 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | 2 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 +++++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 64 ++++=
+++
Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 +++++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 198 ++++=
++++++++++++++++
7 files changed, 373 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silico=
n/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 48f430c88de6..69842b89e021 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -38,4 +38,13 @@ [PcdsFixedAtBuild.common]
gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002=0D
gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003=0D
=0D
+ #=0D
+ # SPI Flash Controller Register Base Address and Size=0D
+ #=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0|UINT64|0x00000004=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x0000000=
6=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x0000000=
7=0D
+=0D
[Protocols]=0D
+ gSpiMasterProtocolGuid =3D { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0=
x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/Du=
rianPkg/DurianPkg.dsc
index 3a9bc2289cf3..68698d613f96 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -244,6 +244,11 @@ [Components.common]
#=0D
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf=0D
=0D
+ #=0D
+ # Spi driver=0D
+ #=0D
+ Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
+=0D
#=0D
# Usb Support=0D
#=0D
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/Du=
rianPkg/DurianPkg.fdf
index a443d0f3a4ac..1cf1927484db 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -95,6 +95,8 @@ [FV.FvMain]
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf=0D
=0D
+ INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf=0D
+=0D
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu=
ntimeDxe.inf=0D
=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf b/Silico=
n/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
new file mode 100644
index 000000000000..21d75f268da4
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
@@ -0,0 +1,44 @@
+#/** @file=0D
+# Phytium Spi Master Drivers.=0D
+#=0D
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR=
=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#**/=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001b=0D
+ BASE_NAME =3D SpiDxe=0D
+ FILE_GUID =3D 2ba95e5c-f7f5-11ea-bf18-67fdc5787495=
=0D
+ MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D SpiMasterDrvEntryPoint=0D
+=0D
+[Sources.common]=0D
+ SpiDxe.c=0D
+ SpiDxe.h=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ IoLib=0D
+ UefiLib=0D
+ UefiBootServicesTableLib=0D
+ UefiDriverEntryPoint=0D
+=0D
+[Guids]=0D
+=0D
+[Protocols]=0D
+ gSpiMasterProtocolGuid=0D
+=0D
+[FixedPcd]=0D
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase=0D
+=0D
+[Depex]=0D
+ TRUE=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h b/Silicon/=
Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
new file mode 100644
index 000000000000..fbadd01921ff
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
@@ -0,0 +1,64 @@
+/** @file=0D
+ Phytium Spi Drivers Header=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef SPI_DXE_H_=0D
+#define SPI_DXE_H_=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+#include <Protocol/SpiProtocol.h>=0D
+#include <Uefi/UefiBaseType.h>=0D
+=0D
+#define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I')=0D
+#define REG_MODE_REG 0x02C=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterGetConfig (=0D
+ IN UINT8 CmdId,=0D
+ OUT UINT32 *Config,=0D
+ IN UINTN RegAddr=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterSetConfig (=0D
+ IN UINT8 CmdId,=0D
+ IN UINT32 Config,=0D
+ IN UINTN RegAddr=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterSetMode (=0D
+ IN UINT32 Config=0D
+ );=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterInit (=0D
+ VOID=0D
+ );=0D
+=0D
+typedef struct {=0D
+ EFI_SPI_DRV_PROTOCOL SpiMasterProtocol;=0D
+ UINTN Signature;=0D
+ EFI_HANDLE Handle;=0D
+} PHYT_SPI_MASTER;=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterDrvEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ );=0D
+=0D
+#endif // SPI_DXE_H_=0D
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.=
h b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h
new file mode 100644
index 000000000000..3ed64d1a5dd7
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h
@@ -0,0 +1,51 @@
+/** @file=0D
+ The Header of Protocol For SPI.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef SPI_H_=0D
+#define SPI_H_=0D
+=0D
+extern EFI_GUID gSpiMasterProtocolGuid;=0D
+typedef struct _EFI_SPI_DRV_PROTOCOL EFI_SPI_DRV_PROTOCOL;=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *SPI_DRV_INIT_INTERFACE) (=0D
+ VOID=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *SPI_DRV_SET_CONFIG_INTERFACE)(=0D
+ IN UINT8 CmdId,=0D
+ IN UINT32 Config,=0D
+ IN UINTN RegAddr=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *SPI_DRV_GET_CONFIG_INTERFACE)(=0D
+ IN UINT8 CmdId,=0D
+ OUT UINT32 *Config,=0D
+ IN UINTN RegAddr=0D
+ );=0D
+=0D
+typedef=0D
+EFI_STATUS=0D
+(EFIAPI *SPI_DRV_CONFIG_MODE_INTERFACE)(=0D
+ IN UINT32 Config=0D
+ );=0D
+=0D
+struct _EFI_SPI_DRV_PROTOCOL{=0D
+ SPI_DRV_INIT_INTERFACE SpiInit;=0D
+ SPI_DRV_SET_CONFIG_INTERFACE SpiSetConfig;=0D
+ SPI_DRV_GET_CONFIG_INTERFACE SpiGetConfig;=0D
+ SPI_DRV_CONFIG_MODE_INTERFACE SpiSetMode;=0D
+};=0D
+=0D
+#endif // SPI_H_=0D
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c b/Silicon/=
Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
new file mode 100644
index 000000000000..885bbd63619c
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
@@ -0,0 +1,198 @@
+/** @file=0D
+ Phytium Spi Master Drivers.=0D
+=0D
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>=
=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "SpiDxe.h"=0D
+=0D
+PHYT_SPI_MASTER *pSpiMasterInstance;=0D
+static UINTN mSpiControlBase;=0D
+=0D
+/**=0D
+ This function inited a spi driver.=0D
+=0D
+ @param None.=0D
+=0D
+ @retval None.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterInit (=0D
+ VOID=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function seted config to spi registers.=0D
+=0D
+ @param[in] CmdId The id of command.=0D
+=0D
+ @param[in] Config The value to be seted.=0D
+=0D
+ @param[in] RegAddr The address of spi registers.=0D
+=0D
+ @retval EFI_SUCCESS SpiMasterSetConfig() is executed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterSetConfig (=0D
+ IN UINT8 CmdId,=0D
+ IN UINT32 Config,=0D
+ IN UINTN RegAddr=0D
+ )=0D
+{=0D
+ UINTN SpiAddr;=0D
+ UINT32 Value;=0D
+=0D
+ SpiAddr =3D 0;=0D
+ Value =3D 0;=0D
+=0D
+ if (CmdId !=3D 0) {=0D
+ Value =3D (CmdId << 24) | (Config & 0xffffff);=0D
+ } else {=0D
+ Value =3D Config;=0D
+ }=0D
+=0D
+ SpiAddr =3D mSpiControlBase + RegAddr;=0D
+ MmioWrite32 (SpiAddr, Value);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function geted config from spi registers.=0D
+=0D
+ @param[in] CmdId The id of command.=0D
+=0D
+ @param[out] Config The pointer of the config.=0D
+=0D
+ @param[in] RegAddr The address of spi registers.=0D
+=0D
+ @retval EFI_SUCCESS SpiMasterGetConfig() is executed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterGetConfig (=0D
+ IN UINT8 CmdId,=0D
+ OUT UINT32 *Config,=0D
+ IN UINTN RegAddr=0D
+ )=0D
+{=0D
+ UINTN SpiAddr;=0D
+ UINT32 Value;=0D
+=0D
+ SpiAddr =3D 0;=0D
+ Value =3D 0;=0D
+=0D
+ SpiAddr =3D mSpiControlBase + RegAddr;=0D
+ Value =3D MmioRead32 (SpiAddr);=0D
+=0D
+ if (CmdId !=3D 0) {=0D
+ *Config =3D Value & 0xffffff;=0D
+ } else {=0D
+ *Config =3D Value;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function seted spi mode.=0D
+=0D
+ @param[in] Config The value to seted.=0D
+=0D
+ @retval EFI_SUCCESS SpiMasterSetMode() is executed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterSetMode (=0D
+ IN UINT32 Config=0D
+ )=0D
+{=0D
+=0D
+ SpiMasterSetConfig (0, Config, REG_MODE_REG);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function inited the spi driver protocol.=0D
+=0D
+ @param[in] SpiMasterProtocol A pointer to the master protocol struct.=
=0D
+=0D
+ @retval EFI_SUCCESS SpiMasterInitProtocol() is executed succ=
essfully.=0D
+=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterInitProtocol (=0D
+ IN EFI_SPI_DRV_PROTOCOL *SpiMasterProtocol=0D
+ )=0D
+{=0D
+=0D
+ SpiMasterProtocol->SpiInit =3D SpiMasterInit;=0D
+ SpiMasterProtocol->SpiSetConfig =3D SpiMasterSetConfig;=0D
+ SpiMasterProtocol->SpiGetConfig =3D SpiMasterGetConfig;=0D
+ SpiMasterProtocol->SpiSetMode =3D SpiMasterSetMode;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ This function is the entrypoint of the spi driver.=0D
+=0D
+ @param[in] ImageHandle The firmware allocated handle for the EFI imag=
e.=0D
+=0D
+ @param[in] SystemTable A pointer to the EFI System Table.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+SpiMasterDrvEntryPoint (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ pSpiMasterInstance =3D AllocateRuntimeZeroPool (sizeof (PHYT_SPI_MASTER)=
);=0D
+ if (pSpiMasterInstance =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ mSpiControlBase =3D FixedPcdGet64 (PcdSpiControllerBase);=0D
+=0D
+ SpiMasterInitProtocol (&pSpiMasterInstance->SpiMasterProtocol);=0D
+=0D
+ pSpiMasterInstance->Signature =3D SPI_MASTER_SIGNATURE;=0D
+=0D
+ Status =3D gBS->InstallMultipleProtocolInterfaces (=0D
+ &(pSpiMasterInstance->Handle),=0D
+ &gSpiMasterProtocolGuid,=0D
+ &(pSpiMasterInstance->SpiMasterProtocol),=0D
+ NULL=0D
+ );=0D
+ ASSERT_EFI_ERROR (Status);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
--=20
2.25.1

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