Date   

Re: [PATCH] BaseTools: Add EDKII_DSC_PLATFORM_GUID MACRO

Michael Kubacki
 

Tested-by: Michael Kubacki <michael.kubacki@...>

It looks like you're only putting one space of indentation before the GUID is printed on the new line after EDKII_DSC_PLATFORM_GUID and there should be two.

#define EDKII_DSC_PLATFORM_GUID \\\n %s

Should be:

#define EDKII_DSC_PLATFORM_GUID \\\n %s

Two spaces before GUID:
#define EFI_CALLER_ID_GUID \
{0x1652B3C2, 0xA7A1, 0x46AC, {0xAF, 0x93, 0xDD, 0x6D, 0xEE, 0x44, 0x66, 0x69}}

One space before GUID:
#define EDKII_DSC_PLATFORM_GUID \
{0xC29BB610, 0x84F9, 0x448D, {0xA7, 0xDD, 0x5A, 0x04, 0xC5, 0xA5, 0x4F, 0x52}}

On 10/9/2020 8:07 PM, fengyunhua wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2969
Add EDKII_DSC_PLATFORM_GUID MACRO
Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Signed-off-by: Yunhua Feng <fengyunhua@...>
---
BaseTools/Source/Python/AutoGen/GenC.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/BaseTools/Source/Python/AutoGen/GenC.py b/BaseTools/Source/Python/AutoGen/GenC.py
index 5e0d11e165..5b63d278be 100755
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -1980,12 +1980,14 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
AutoGenH.Append("#include <Library/PcdLib.h>\n")
AutoGenH.Append('\nextern GUID gEfiCallerIdGuid;')
+ AutoGenH.Append('\nextern GUID gEdkiiDscPlatformGuid;')
AutoGenH.Append('\nextern CHAR8 *gEfiCallerBaseName;\n\n')
if Info.IsLibrary:
return
AutoGenH.Append("#define EFI_CALLER_ID_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenH.Append("#define EDKII_DSC_PLATFORM_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))
if Info.IsLibrary:
return
@@ -2002,6 +2004,7 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
# Publish the CallerId Guid
#
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEfiCallerIdGuid = %s;\n' % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEdkiiDscPlatformGuid = %s;\n' % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *gEfiCallerBaseName = "%s";\n' % Info.Name)
## Create common code for header file


[PATCH 9/9] UefiCpuPkg/MpInitLib: For SEV-ES guest set stack based on processor number

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

Set the SEV-ES reset stack address for an AP based on the processor number
instead of the APIC ID in case the APIC IDs are not zero-based and densely
packed/enumerated. This will ensure an AP reset stack address does not get
set outside of the AP reset stack memory allocation.

Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Rahul Kumar <rahul1.kumar@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 07426274f639..71922141b70b 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -680,11 +680,16 @@ MpInitLibSevEsAPReset (
IN CPU_MP_DATA *CpuMpData
)
{
+ EFI_STATUS Status;
+ UINTN ProcessorNumber;
UINT16 Code16, Code32;
AP_RESET *APResetFn;
UINTN BufferStart;
UINTN StackStart;

+ Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);
+ ASSERT_EFI_ERROR (Status);
+
Code16 = GetProtectedMode16CS ();
Code32 = GetProtectedMode32CS ();

@@ -696,7 +701,7 @@ MpInitLibSevEsAPReset (

BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;
StackStart = CpuMpData->SevEsAPResetStackStart -
- (AP_RESET_STACK_SIZE * GetApicId ());
+ (AP_RESET_STACK_SIZE * ProcessorNumber);

//
// This call never returns.
--
2.28.0


[PATCH 8/9] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Disable interrupts when using GHCB

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

The QemuFlashPtrWrite() flash services runtime uses the GHCB and VmgExit()
directly to perform the flash write when running as an SEV-ES guest. If an
interrupt arrives between VmgInit() and VmgDone(), the Dr7 read in the
interrupt handler will generate a #VC, which can overwrite information in
the GHCB that QemuFlashPtrWrite() has set. Prevent this from occurring by
disabling interrupts around the usage of the GHCB.

Fixes: 437eb3f7a8db ("OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash detection with SEV-ES")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
index 5d5a117c48e0..872e58db7cc0 100644
--- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
+++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
@@ -9,6 +9,7 @@

**/

+#include <Library/BaseLib.h>
#include <Library/UefiRuntimeLib.h>
#include <Library/MemEncryptSevLib.h>
#include <Library/VmgExitLib.h>
@@ -54,6 +55,7 @@ QemuFlashPtrWrite (
GHCB *Ghcb;
UINT32 ScratchIndex;
UINT32 ScratchBit;
+ BOOLEAN InterruptsEnabled;

Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
Ghcb = Msr.Ghcb;
@@ -61,6 +63,15 @@ QemuFlashPtrWrite (
ScratchIndex = GhcbSwScratch / 8;
ScratchBit = GhcbSwScratch & 0x07;

+ //
+ // Be sure that an interrupt can't cause a #VC while the GHCB is
+ // being used.
+ //
+ InterruptsEnabled = GetInterruptState ();
+ if (InterruptsEnabled) {
+ DisableInterrupts ();
+ }
+
//
// Writing to flash is emulated by the hypervisor through the use of write
// protection. This won't work for an SEV-ES guest because the write won't
@@ -74,6 +85,10 @@ QemuFlashPtrWrite (
Ghcb->SaveArea.ValidBitmap[ScratchIndex] |= (1 << ScratchBit);
VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, (UINT64) (UINTN) Ptr, 1);
VmgDone (Ghcb);
+
+ if (InterruptsEnabled) {
+ EnableInterrupts ();
+ }
} else {
*Ptr = Value;
}
--
2.28.0


[PATCH 7/9] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Fix erase blocks for SEV-ES

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

The original SEV-ES support missed updating the QemuFlashEraseBlock()
function to successfully erase blocks. Update QemuFlashEraseBlock() to
call the QemuFlashPtrWrite() to be able to successfully perform the
commands under SEV-ES.

Fixes: 437eb3f7a8db ("OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash detection with SEV-ES")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c
index 0d29bf701aca..d19997032ec9 100644
--- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c
+++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c
@@ -232,8 +232,8 @@ QemuFlashEraseBlock (
}

Ptr = QemuFlashPtr (Lba, 0);
- *Ptr = BLOCK_ERASE_CMD;
- *Ptr = BLOCK_ERASE_CONFIRM_CMD;
+ QemuFlashPtrWrite (Ptr, BLOCK_ERASE_CMD);
+ QemuFlashPtrWrite (Ptr, BLOCK_ERASE_CONFIRM_CMD);
return EFI_SUCCESS;
}

--
2.28.0


[PATCH 6/9] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Set the SwScratch valid bit

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

All fields that are set in the GHCB should have their associated bit in
the GHCB ValidBitmap field set. Add support to set the bit for the scratch
area field (SwScratch).

Fixes: 437eb3f7a8db ("OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash detection with SEV-ES")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
index 565383ee26d2..5d5a117c48e0 100644
--- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
+++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c
@@ -52,10 +52,15 @@ QemuFlashPtrWrite (
if (MemEncryptSevEsIsEnabled ()) {
MSR_SEV_ES_GHCB_REGISTER Msr;
GHCB *Ghcb;
+ UINT32 ScratchIndex;
+ UINT32 ScratchBit;

Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
Ghcb = Msr.Ghcb;

+ ScratchIndex = GhcbSwScratch / 8;
+ ScratchBit = GhcbSwScratch & 0x07;
+
//
// Writing to flash is emulated by the hypervisor through the use of write
// protection. This won't work for an SEV-ES guest because the write won't
@@ -66,6 +71,7 @@ QemuFlashPtrWrite (
VmgInit (Ghcb);
Ghcb->SharedBuffer[0] = Value;
Ghcb->SaveArea.SwScratch = (UINT64) (UINTN) Ghcb->SharedBuffer;
+ Ghcb->SaveArea.ValidBitmap[ScratchIndex] |= (1 << ScratchBit);
VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, (UINT64) (UINTN) Ptr, 1);
VmgDone (Ghcb);
} else {
--
2.28.0


[PATCH 5/9] UefiCpuPkg/MpInitLib: Set the SW exit fields when performing VMGEXIT

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

All fields that are set in the GHCB should have their associated bit in
the GHCB ValidBitmap field set. Add support to set the bits for the
software exit information fields when performing a VMGEXIT (SwExitCode,
SwExitInfo1, SwExitInfo2).

Fixes: 20da7ca42a33 ("UefiCpuPkg/MpInitLib: Prepare SEV-ES guest APs for OS use")
Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Rahul Kumar <rahul1.kumar@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index 5d30f35b201c..5532a1d391bc 100644
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -533,6 +533,12 @@ BITS 64

mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD
mov [rdx + 0x390], rax
+ mov rax, 114 ; Set SwExitCode valid bit
+ bts [rdx + 0x3f0], rax
+ inc rax ; Set SwExitInfo1 valid bit
+ bts [rdx + 0x3f0], rax
+ inc rax ; Set SwExitInfo2 valid bit
+ bts [rdx + 0x3f0], rax

pop rdx
pop rcx
--
2.28.0


[PATCH 4/9] OvmfPkg/VmgExitLib: Set the SwScratch valid bit for MMIO events

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

All fields that are set in the GHCB should have their associated bit in
the GHCB ValidBitmap field set. Add support to set the bit for the scratch
area field (SwScratch).

Fixes: c45f678a1ea2 ("OvmfPkg/VmgExitLib: Add support for NPF NAE events (MMIO)")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Brijesh Singh <brijesh.singh@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
index 40120e29af18..6d6fe6800031 100644
--- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
+++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
@@ -720,6 +720,7 @@ MmioExit (
CopyMem (Ghcb->SharedBuffer, &InstructionData->Ext.RegData, Bytes);

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
@@ -749,6 +750,7 @@ MmioExit (
CopyMem (Ghcb->SharedBuffer, InstructionData->Immediate, Bytes);

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
@@ -781,6 +783,7 @@ MmioExit (
ExitInfo2 = Bytes;

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
@@ -811,6 +814,7 @@ MmioExit (
ExitInfo2 = Bytes;

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
@@ -836,6 +840,7 @@ MmioExit (
ExitInfo2 = Bytes;

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
--
2.28.0


[PATCH 3/9] OvmfPkg/VmgExitLib: Set the SwScratch valid bit for IOIO events

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

All fields that are set in the GHCB should have their associated bit in
the GHCB ValidBitmap field set. Add support to set the bit for the scratch
area field (SwScratch).

Fixes: 0020157a9825 ("OvmfPkg/VmgExitLib: Support string IO for IOIO_PROT NAE events")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Brijesh Singh <brijesh.singh@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
index c5484a3f478c..40120e29af18 100644
--- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
+++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
@@ -1289,6 +1289,7 @@ IoioExit (
}

Ghcb->SaveArea.SwScratch = (UINT64) Ghcb->SharedBuffer;
+ GhcbSetRegValid (Ghcb, GhcbSwScratch);
Status = VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, ExitInfo2);
if (Status != 0) {
return Status;
--
2.28.0


[PATCH 2/9] OvmfPkg/VmgExitLib: Set the SW exit fields when performing VMGEXIT

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

All fields that are set in the GHCB should have their associated bit in
the GHCB ValidBitmap field set. Add support to set the bits for the
software exit information fields when performing a VMGEXIT (SwExitCode,
SwExitInfo1, SwExitInfo2).

Fixes: 61bacc0fa16f ("OvmfPkg/VmgExitLib: Implement library support for VmgExitLib in OVMF")
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Brijesh Singh <brijesh.singh@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
OvmfPkg/Library/VmgExitLib/VmgExitLib.c | 30 ++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitLib.c b/OvmfPkg/Library/VmgExitLib/VmgExitLib.c
index 53040cc6f649..6cf649c6101b 100644
--- a/OvmfPkg/Library/VmgExitLib/VmgExitLib.c
+++ b/OvmfPkg/Library/VmgExitLib/VmgExitLib.c
@@ -78,6 +78,32 @@ VmgExitErrorCheck (
return Status;
}

+/**
+ Marks a field at the specified offset as valid in the GHCB.
+
+ The ValidBitmap area represents the areas of the GHCB that have been marked
+ valid. Set the area of the GHCB at the specified offset as valid.
+
+ @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication Block
+ @param[in] Offset Offset in the GHCB to mark valid
+
+**/
+STATIC
+VOID
+GhcbSetOffsetValid (
+ IN OUT GHCB *Ghcb,
+ IN GHCB_QWORD_OFFSET Offset
+ )
+{
+ UINT32 OffsetIndex;
+ UINT32 OffsetBit;
+
+ OffsetIndex = Offset / 8;
+ OffsetBit = Offset & 0x07;
+
+ Ghcb->SaveArea.ValidBitmap[OffsetIndex] |= (1 << OffsetBit);
+}
+
/**
Perform VMGEXIT.

@@ -110,6 +136,10 @@ VmgExit (
Ghcb->SaveArea.SwExitInfo1 = ExitInfo1;
Ghcb->SaveArea.SwExitInfo2 = ExitInfo2;

+ GhcbSetOffsetValid (Ghcb, GhcbSwExitCode);
+ GhcbSetOffsetValid (Ghcb, GhcbSwExitInfo1);
+ GhcbSetOffsetValid (Ghcb, GhcbSwExitInfo2);
+
//
// Guest memory is used for the guest-hypervisor communication, so fence
// the invocation of the VMGEXIT instruction to ensure GHCB accesses are
--
2.28.0


[PATCH 1/9] OvmfPkg/VmgExitLib: Update ValidBitmap settings

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

Use OFFSET_OF () and sizeof () to calculate the GHCB register field
offsets instead of hardcoding the values in the GHCB_REGISTER enum.
Rename GHCB_REGISTER to GHCB_QWORD_OFFSET to more appropriately describe
the enum. While redefing the values, only include (and add) fields that
are used per the GHCB specification.

Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is
not used/defined in the GHCB specification and then rename the reserved
fields as appropriate.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Brijesh Singh <brijesh.singh@...>
Signed-off-by: Tom Lendacky <thomas.lendacky@...>
---
MdePkg/Include/Register/Amd/Ghcb.h | 48 ++++++++------------
OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 4 +-
2 files changed, 20 insertions(+), 32 deletions(-)

diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h
index 54a80da0f6d7..33c7e8939a28 100644
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -82,50 +82,25 @@
#define IOIO_SEG_DS (BIT11 | BIT10)


-typedef enum {
- GhcbCpl = 25,
- GhcbRflags = 46,
- GhcbRip,
- GhcbRsp = 59,
- GhcbRax = 63,
- GhcbRcx = 97,
- GhcbRdx,
- GhcbRbx,
- GhcbRbp = 101,
- GhcbRsi,
- GhcbRdi,
- GhcbR8,
- GhcbR9,
- GhcbR10,
- GhcbR11,
- GhcbR12,
- GhcbR13,
- GhcbR14,
- GhcbR15,
- GhcbXCr0 = 125,
-} GHCB_REGISTER;
-
typedef PACKED struct {
UINT8 Reserved1[203];
UINT8 Cpl;
- UINT8 Reserved2[148];
- UINT64 Dr7;
- UINT8 Reserved3[144];
+ UINT8 Reserved2[300];
UINT64 Rax;
- UINT8 Reserved4[264];
+ UINT8 Reserved3[264];
UINT64 Rcx;
UINT64 Rdx;
UINT64 Rbx;
- UINT8 Reserved5[112];
+ UINT8 Reserved4[112];
UINT64 SwExitCode;
UINT64 SwExitInfo1;
UINT64 SwExitInfo2;
UINT64 SwScratch;
- UINT8 Reserved6[56];
+ UINT8 Reserved5[56];
UINT64 XCr0;
UINT8 ValidBitmap[16];
UINT64 X87StateGpa;
- UINT8 Reserved7[1016];
+ UINT8 Reserved6[1016];
} GHCB_SAVE_AREA;

typedef PACKED struct {
@@ -136,6 +111,19 @@ typedef PACKED struct {
UINT32 GhcbUsage;
} GHCB;

+typedef enum {
+ GhcbCpl = OFFSET_OF (GHCB, SaveArea.Cpl) / sizeof (UINT64),
+ GhcbRax = OFFSET_OF (GHCB, SaveArea.Rax) / sizeof (UINT64),
+ GhcbRbx = OFFSET_OF (GHCB, SaveArea.Rbx) / sizeof (UINT64),
+ GhcbRcx = OFFSET_OF (GHCB, SaveArea.Rcx) / sizeof (UINT64),
+ GhcbRdx = OFFSET_OF (GHCB, SaveArea.Rdx) / sizeof (UINT64),
+ GhcbXCr0 = OFFSET_OF (GHCB, SaveArea.XCr0) / sizeof (UINT64),
+ GhcbSwExitCode = OFFSET_OF (GHCB, SaveArea.SwExitCode) / sizeof (UINT64),
+ GhcbSwExitInfo1 = OFFSET_OF (GHCB, SaveArea.SwExitInfo1) / sizeof (UINT64),
+ GhcbSwExitInfo2 = OFFSET_OF (GHCB, SaveArea.SwExitInfo2) / sizeof (UINT64),
+ GhcbSwScratch = OFFSET_OF (GHCB, SaveArea.SwScratch) / sizeof (UINT64),
+} GHCB_QWORD_OFFSET;
+
typedef union {
struct {
UINT32 Lower32Bits;
diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
index 8e42b305e83c..c5484a3f478c 100644
--- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
+++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c
@@ -153,7 +153,7 @@ STATIC
BOOLEAN
GhcbIsRegValid (
IN GHCB *Ghcb,
- IN GHCB_REGISTER Reg
+ IN GHCB_QWORD_OFFSET Reg
)
{
UINT32 RegIndex;
@@ -179,7 +179,7 @@ STATIC
VOID
GhcbSetRegValid (
IN OUT GHCB *Ghcb,
- IN GHCB_REGISTER Reg
+ IN GHCB_QWORD_OFFSET Reg
)
{
UINT32 RegIndex;
--
2.28.0


[PATCH 0/9] SEV-ES guest support fixes and cleanup

Lendacky, Thomas
 

From: Tom Lendacky <thomas.lendacky@...>

This patch series provides some fixes, updates and cleanup to the SEV-ES
guest support:

The first patch updates the calculation of the qword offset of fields
within the GHCB. Specifically, it removes the hardcoding of the offsets
and uses the OFFSET_OF () and sizeof () functions to calculate the
values, removes unused values and add values that will be used in later
patches.

The next five patches set the SwExitCode/SwExitInfo1/SwExitInfo2/SwScratch
valid bits in the GHCB ValidBitmap area when these fields are set at
VMGEXIT.

The next two patches update the Qemu flash drive services support to
add SEV-ES support to erasing blocks and to disable interrupts when using
the GHCB.

Finally, the last patch uses the processor number for setting the AP stack
pointer instead of the APIC ID (using GetProcessorNumber()).

---

These patches are based on commit:
ae511331e0fb ("BaseTools Build_Rule: Add the missing ASM16_FLAGS for ASM16 source file")

Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Eric Dong <eric.dong@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Liming Gao <gaoliming@...>
Cc: Jordan Justen <jordan.l.justen@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Rahul Kumar <rahul1.kumar@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Ray Ni <ray.ni@...>
Cc: Tom Lendacky <thomas.lendacky@...>
Cc: Brijesh Singh <brijesh.singh@...>

Tom Lendacky (9):
OvmfPkg/VmgExitLib: Update ValidBitmap settings
OvmfPkg/VmgExitLib: Set the SW exit fields when performing VMGEXIT
OvmfPkg/VmgExitLib: Set the SwScratch valid bit for IOIO events
OvmfPkg/VmgExitLib: Set the SwScratch valid bit for MMIO events
UefiCpuPkg/MpInitLib: Set the SW exit fields when performing VMGEXIT
OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Set the SwScratch valid bit
OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Fix erase blocks for SEV-ES
OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Disable interrupts when using
GHCB
UefiCpuPkg/MpInitLib: For SEV-ES guest set stack based on processor
number

MdePkg/Include/Register/Amd/Ghcb.h | 48 ++++++++------------
OvmfPkg/Library/VmgExitLib/VmgExitLib.c | 30 ++++++++++++
OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 10 +++-
OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c | 4 +-
OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c | 21 +++++++++
UefiCpuPkg/Library/MpInitLib/MpLib.c | 7 ++-
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 +++
7 files changed, 91 insertions(+), 35 deletions(-)

--
2.28.0


Re: [PATCH] BaseTools: Add EDKII_DSC_PLATFORM_GUID MACRO

Bob Feng
 

Yunhua, Please complete the description sentence, for example "Add EDKII_DSC_PLATFORM_GUID MACRO to AutoGen.h and AutoGen.c".

After changing the description, Reviewed-by: Bob Feng <bob.c.feng@...>

-----Original Message-----
From: fengyunhua <fengyunhua@...>
Sent: Saturday, October 10, 2020 11:07 AM
To: devel@edk2.groups.io
Cc: gaoliming@...; Feng, Bob C <bob.c.feng@...>
Subject: [PATCH] BaseTools: Add EDKII_DSC_PLATFORM_GUID MACRO

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2969

Add EDKII_DSC_PLATFORM_GUID MACRO

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Signed-off-by: Yunhua Feng <fengyunhua@...>
---
BaseTools/Source/Python/AutoGen/GenC.py | 3 +++
1 file changed, 3 insertions(+)

diff --git a/BaseTools/Source/Python/AutoGen/GenC.py b/BaseTools/Source/Python/AutoGen/GenC.py
index 5e0d11e165..5b63d278be 100755
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -1980,12 +1980,14 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
AutoGenH.Append("#include <Library/PcdLib.h>\n")

AutoGenH.Append('\nextern GUID gEfiCallerIdGuid;')
+ AutoGenH.Append('\nextern GUID gEdkiiDscPlatformGuid;')
AutoGenH.Append('\nextern CHAR8 *gEfiCallerBaseName;\n\n')

if Info.IsLibrary:
return

AutoGenH.Append("#define EFI_CALLER_ID_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenH.Append("#define EDKII_DSC_PLATFORM_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))

if Info.IsLibrary:
return
@@ -2002,6 +2004,7 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
# Publish the CallerId Guid
#
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEfiCallerIdGuid = %s;\n' % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEdkiiDscPlatformGuid = %s;\n' % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *gEfiCallerBaseName = "%s";\n' % Info.Name)

## Create common code for header file
--
2.27.0.windows.1


回复: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for hiding page-access caps from OSes hides SP and CRYPTO caps too

gaoliming
 

Meg:
Pull Request is created https://github.com/tianocore/edk2/pull/999

Thanks
Liming

-----邮件原件-----
发件人: bounce+27952+66058+4905953+8761045@groups.io
<bounce+27952+66058+4905953+8761045@groups.io> 代表 gaoliming
发送时间: 2020年10月9日 17:30
收件人: devel@edk2.groups.io; jacek.kukiello@...; 'Rothman, Michael
A' <michael.a.rothman@...>
抄送: 'Kinney, Michael D' <michael.d.kinney@...>; 'Wang, Jian J'
<jian.j.wang@...>; 'Wu, Hao A' <hao.a.wu@...>; 'Bi, Dandan'
<dandan.bi@...>; 'Liu, Zhiguang' <zhiguang.liu@...>; 'Oleksiy
Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel' <ard.biesheuvel@...>
主题: 回复: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding page-access caps from OSes hides SP and CRYPTO caps too

Meg:
Thanks for your detail information. I understand this problem now.
I agree your patch to revert the change introduced by previous
3bd5c994c879f78e8e3d5346dc3b627f199291aa.

Reviewed-by: Liming Gao <gaoliming@...>

If no other comments, I will merge this patch set tomorrow.

Thanks
Liming
-----邮件原件-----
发件人: bounce+27952+66053+4905953+8761045@groups.io
<bounce+27952+66053+4905953+8761045@groups.io> 代表 Malgorzata
Kukiello
发送时间: 2020年10月9日 14:01
收件人: devel@edk2.groups.io; Kukiello, Malgorzata
<jacek.kukiello@...>; gaoliming@...; Rothman, Michael
A
<michael.a.rothman@...>
抄送: Kinney, Michael D <michael.d.kinney@...>; Wang, Jian J
<jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Bi, Dandan
<dandan.bi@...>; Liu, Zhiguang <zhiguang.liu@...>; 'Oleksiy
Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel'
<ard.biesheuvel@...>
主题: Re: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding
page-access caps from OSes hides SP and CRYPTO caps too

Liming,
Any update/comment? It's pretty urgent from my perspective.
Thanks
Meg

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Malgorzata Kukiello
Sent: Friday, October 2, 2020 2:52 PM
To: devel@edk2.groups.io; gaoliming@...; Rothman, Michael A
<michael.a.rothman@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Wang, Jian J
<jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Bi, Dandan
<dandan.bi@...>; Liu, Zhiguang <zhiguang.liu@...>; 'Oleksiy
Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel'
<ard.biesheuvel@...>
Subject: Re: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding page-access caps from OSes hides SP and CRYPTO caps too

Liming,
I am trying to enable a crypto technology, that requires handling on the OS
side (implemented in the kernel.org patch), generally speaking I mark in
memory map all regions that can be encrypted using the before mentioned
tech. Then OS checks that attribute and decides whether or not to enable
that.
So the real problem is that currently all my attributes are overwritten and
cleared.
Thanks
Meg

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Tuesday, September 29, 2020 3:13 AM
To: devel@edk2.groups.io; Kukiello, Malgorzata <jacek.kukiello@...>;
Rothman, Michael A <michael.a.rothman@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Wang, Jian J
<jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Bi, Dandan
<dandan.bi@...>; Liu, Zhiguang <zhiguang.liu@...>; 'Oleksiy
Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel'
<ard.biesheuvel@...>
Subject: 回复: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding page-access caps from OSes hides SP and CRYPTO caps too

Meg:
What real problem do you meet with? What purpose is for this change?
And,
I also include UEFI Arch Rothman.

Rothman:
Can you help clarify what OS (Windows or Linux) behavior is expected for
UEFI SP and CRYPTO memory attribute?

Thanks
Liming
-----邮件原件-----
发件人: bounce+27952+65683+4905953+8761045@groups.io
<bounce+27952+65683+4905953+8761045@groups.io> 代表
Malgorzata
Kukiello
发送时间: 2020年9月28日 23:39
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Kinney, Michael D <michael.d.kinney@...>; Wang, Jian J
<jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Bi, Dandan
<dandan.bi@...>; Liu, Zhiguang <zhiguang.liu@...>;
'Oleksiy Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel'
<ard.biesheuvel@...>
主题: Re: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding
page-access caps from OSes hides SP and CRYPTO caps too

Liming,
As for mktme there is a change commited:
https://patchwork.kernel.org/patch/10935909/
As for SP I can't find anything specific.
Thanks
Meg

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Friday, September 25, 2020 10:55 AM
To: devel@edk2.groups.io; Kukiello, Malgorzata
<jacek.kukiello@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Wang, Jian J
<jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Bi, Dandan
<dandan.bi@...>; Liu, Zhiguang <zhiguang.liu@...>;
'Oleksiy Yakovlev' <oleksiyy@...>; 'Ard Biesheuvel'
<ard.biesheuvel@...>
Subject: 回复: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround
for
hiding page-access caps from OSes hides SP and CRYPTO caps too

Malgorzata:
How do know OS (Windows or Linux) behavior for SP and CRYPTO
attribute?
Is there the public document to describe this behavior?

Thanks
Liming
-----邮件原件-----
发件人: bounce+27952+65566+4905953+8761045@groups.io
<bounce+27952+65566+4905953+8761045@groups.io> 代表
Malgorzata
Kukiello
发送时间: 2020年9月24日 18:22
收件人: devel@edk2.groups.io
抄送: Malgorzata Kukiello <jacek.kukiello@...>; Michael D
Kinney
<michael.d.kinney@...>; Jian J Wang <jian.j.wang@...>;
Hao A Wu <hao.a.wu@...>; Dandan Bi <dandan.bi@...>;
Liming Gao <gaoliming@...>; Zhiguang Liu
<zhiguang.liu@...>; Oleksiy Yakovlev <oleksiyy@...>; Ard
Biesheuvel <ard.biesheuvel@...>
主题: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for
hiding
page-access caps from OSes hides SP and CRYPTO caps too

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2982

The workaround in the UEFI memmap construction, near the end of the
function CoreGetMemoryMap()
[MdeModulePkg/Core/Dxe/Mem/Page.c]
should
not clear the SP and CRYPTO bits, because OSes do (apparently)
correctly interpret SP and CRYPTO as capabilities, and not as
currently set attributes (upon which the OSes should set their page
tables). For this reason, the SP and CRYPTO bits should be separated
from the bitmask that we use for hiding the page-access attributes,
in the workaround

Signed-off-by: Malgorzata Kukiello <jacek.kukiello@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Jian J Wang <jian.j.wang@...>
Cc: Hao A Wu <hao.a.wu@...>
Cc: Dandan Bi <dandan.bi@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Oleksiy Yakovlev <oleksiyy@...>
Cc: Ard Biesheuvel (ARM address) <ard.biesheuvel@...>

MdeModulePkg/Core/Dxe/Mem/Page.c | 12 ++++++------
MdePkg/Include/Uefi/UefiSpec.h | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
--------------------------------------------------------------------
-
Intel Technology Poland sp. z o.o.
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Wydzia Gospodarczy Krajowego Rejestru Sdowego - KRS 101882 | NIP
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ul. Sowackiego 173 | 80-298 Gdask | Sd Rejonowy Gdask Pnoc | VII
Wydzia Gospodarczy Krajowego Rejestru Sdowego - KRS 101882 | NIP
957-07-52-316 | Kapita zakadowy 200.000 PLN.
Ta wiadomo wraz z zacznikami jest przeznaczona dla okrelonego adresata
i moe zawiera informacje poufne. W razie przypadkowego otrzymania tej
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jakiekolwiek przegldanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). If you are not the intended
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or distribution by others is strictly prohibited.











---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Sowackiego 173 | 80-298 Gdask | Sd Rejonowy Gdask Pnoc | VII Wydzia
Gospodarczy Krajowego Rejestru Sdowego - KRS 101882 | NIP
957-07-52-316
| Kapita zakadowy 200.000 PLN.
Ta wiadomo wraz z zacznikami jest przeznaczona dla okrelonego adresata i
moe zawiera informacje poufne. W razie przypadkowego otrzymania tej
wiadomoci, prosimy o powiadomienie nadawcy oraz trwae jej usunicie;
jakiekolwiek przegldanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the
sole use of the intended recipient(s). If you are not the intended recipient,
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by
others is strictly prohibited.






---------------------------------------------------------------------
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ul. Sowackiego 173 | 80-298 Gdask | Sd Rejonowy Gdask Pnoc | VII Wydzia
Gospodarczy Krajowego Rejestru Sdowego - KRS 101882 | NIP
957-07-52-316
| Kapita zakadowy 200.000 PLN.
Ta wiadomo wraz z zacznikami jest przeznaczona dla okrelonego adresata i
moe zawiera informacje poufne. W razie przypadkowego otrzymania tej
wiadomoci, prosimy o powiadomienie nadawcy oraz trwae jej usunicie;
jakiekolwiek przegldanie lub rozpowszechnianie jest zabronione.
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please contact the sender and delete all copies; any review or distribution
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others is strictly prohibited.










回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".

gaoliming
 

-----邮件原件-----
发件人: bounce+27952+66090+4905953+8761045@groups.io
<bounce+27952+66090+4905953+8761045@groups.io> 代表 gaoliming
发送时间: 2020年10月10日 10:33
收件人: 'Liu, Zhiguang' <zhiguang.liu@...>; devel@edk2.groups.io
抄送: 'Wang, Sanyo' <sanyo.wang@...>; 'Kinney, Michael D'
<michael.d.kinney@...>; 'Gao, Zhichao' <zhichao.gao@...>;
'Sean Brogan' <spbrogan@...>
主题: 回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding
DDR5 definitions".

The pull request needs rebase. I will submit new pull request today.

Thanks
Liming
-----邮件原件-----
发件人: Liu, Zhiguang <zhiguang.liu@...>
发送时间: 2020年10月10日 8:49
收件人: gaoliming <gaoliming@...>; devel@edk2.groups.io
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
'Sean Brogan' <spbrogan@...>
主题: RE: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding
DDR5
definitions".

Hi Liming

In pull request https://github.com/tianocore/edk2/pull/996
Merge failed because
tanocore.PatchCheck Failing after 34s — Build #20201009.4 failed

Detail:
The commit message format is not valid:
* Missing Signed-off-by! (Note: this must be added by the code
contributor!)
https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-For
mat

However, I abstract the patch from Outlook and run PatchCheck to check it
in
my local machine, the result is ok.

Detail:
E:\edk2\BaseTools\Scripts>py PatchCheck.py
0001-MdePkg-SMBIOS-3.4.0-Update-adding-DDR5-definitions-.patch
Checking patch file:
0001-MdePkg-SMBIOS-3.4.0-Update-adding-DDR5-definitions-.patch
[PATCH] MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".
The commit message format passed all checks.
The code passed all checks.

Do you know why?

Thanks
Zhiguang
-----Original Message-----
From: gaoliming <gaoliming@...>
Sent: Friday, October 9, 2020 5:21 PM
To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@...>
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
'Sean
Brogan' <spbrogan@...>
Subject: 回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

https://github.com/tianocore/edk2/pull/996 is created.

-----邮件原件-----
发件人: bounce+27952+66054+4905953+8761045@groups.io
<bounce+27952+66054+4905953+8761045@groups.io> 代表
Zhiguang
Liu
发送时间: 2020年10月9日 15:24
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
Sean Brogan <spbrogan@...>
主题: Re: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding
DDR5
definitions".

Hi Liming,
This patch also gets R-B from Sean Brogan.
Please help merge this patch.

Thanks
Zhiguang

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, September 30, 2020 8:45 AM
To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@...>
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>
Subject: 回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

Reviewed-by: Liming Gao <gaoliming@...>

-----邮件原件-----
发件人: bounce+27952+65712+4905953+8761045@groups.io
<bounce+27952+65712+4905953+8761045@groups.io> 代表
Zhiguang
Liu
发送时间: 2020年9月29日 16:12
收件人: devel@edk2.groups.io; Liu, Zhiguang
<zhiguang.liu@...>
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Liming Gao
<gaoliming@...>
主题: Re: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5
definitions".


Reviewed-by: Zhiguang Liu <zhiguang.liu@...>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf
Of
Zhiguang
Liu
Sent: Tuesday, September 29, 2020 4:09 PM
To: devel@edk2.groups.io
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Liming Gao
<gaoliming@...>
Subject: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

From: "Wang, Sanyo" <sanyo.wang@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352

SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5)

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Sanyo Wang <sanyo.wang@...>
---
MdePkg/Include/IndustryStandard/SmBios.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/IndustryStandard/SmBios.h
b/MdePkg/Include/IndustryStandard/SmBios.h
index ea23685851..f2db11f947 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1718,7 +1718,9 @@ typedef enum {
MemoryTypeLpddr4 = 0x1E,

MemoryTypeLogicalNonVolatileDevice = 0x1F,

MemoryTypeHBM = 0x20,

- MemoryTypeHBM2 = 0x21

+ MemoryTypeHBM2 = 0x21,

+ MemoryTypeDdr5 = 0x22,

+ MemoryTypeLpddr5 = 0x23

} MEMORY_DEVICE_TYPE;



///

--
2.25.1.windows.1



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[PATCH] BaseTools: Add EDKII_DSC_PLATFORM_GUID MACRO

fengyunhua <fengyunhua@...>
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2969

Add EDKII_DSC_PLATFORM_GUID MACRO

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Signed-off-by: Yunhua Feng <fengyunhua@...>
---
BaseTools/Source/Python/AutoGen/GenC.py | 3 +++
1 file changed, 3 insertions(+)

diff --git a/BaseTools/Source/Python/AutoGen/GenC.py b/BaseTools/Source/Python/AutoGen/GenC.py
index 5e0d11e165..5b63d278be 100755
--- a/BaseTools/Source/Python/AutoGen/GenC.py
+++ b/BaseTools/Source/Python/AutoGen/GenC.py
@@ -1980,12 +1980,14 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
AutoGenH.Append("#include <Library/PcdLib.h>\n")

AutoGenH.Append('\nextern GUID gEfiCallerIdGuid;')
+ AutoGenH.Append('\nextern GUID gEdkiiDscPlatformGuid;')
AutoGenH.Append('\nextern CHAR8 *gEfiCallerBaseName;\n\n')

if Info.IsLibrary:
return

AutoGenH.Append("#define EFI_CALLER_ID_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenH.Append("#define EDKII_DSC_PLATFORM_GUID \\\n %s\n" % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))

if Info.IsLibrary:
return
@@ -2002,6 +2004,7 @@ def CreateHeaderCode(Info, AutoGenC, AutoGenH):
# Publish the CallerId Guid
#
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEfiCallerIdGuid = %s;\n' % GuidStringToGuidStructureString(Info.Guid))
+ AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED GUID gEdkiiDscPlatformGuid = %s;\n' % GuidStringToGuidStructureString(Info.PlatformInfo.Guid))
AutoGenC.Append('\nGLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *gEfiCallerBaseName = "%s";\n' % Info.Name)

## Create common code for header file
--
2.27.0.windows.1


[PATCH] BaseMemoryLibSse2: Take advantage of write combining buffers

Compostella, Jeremy
 

The current SSE2 implementation of the ZeroMem(), SetMem(),
SetMem16(), SetMem32() and SetMem64() functions is writing 16 bytes
per 16 bytes. It hurts the performances so bad that this is even
slower than a simple 'rep stos' (4% slower) in regular RAM.

To take full advantages of the 'movntdq' instruction it is better to
"queue" a total of 64 bytes in the write combining buffers. This
patch implements such a change. Below is a table where I measured
(with 'rdtsc') the time to write an entire 100MB RAM buffer. These
functions operate almost twice faster.

| Function | Arch | Untouched | 64 bytes | Result |
|----------+------+-----------+----------+--------|
| ZeroMem | Ia32 | 17765947 | 9136062 | 1.945x |
| ZeroMem | X64 | 17525170 | 9233391 | 1.898x |
| SetMem | Ia32 | 17522291 | 9137272 | 1.918x |
| SetMem | X64 | 17949261 | 9176978 | 1.956x |
| SetMem16 | Ia32 | 18219673 | 9372062 | 1.944x |
| SetMem16 | X64 | 17523331 | 9275184 | 1.889x |
| SetMem32 | Ia32 | 18495036 | 9273053 | 1.994x |
| SetMem32 | X64 | 17368864 | 9285885 | 1.870x |
| SetMem64 | Ia32 | 18564473 | 9241362 | 2.009x |
| SetMem64 | X64 | 17506951 | 9280148 | 1.886x |

Signed-off-by: Jeremy Compostella <jeremy.compostella@...>
---
.../BaseMemoryLibSse2/Ia32/SetMem.nasm | 11 ++++++----
.../BaseMemoryLibSse2/Ia32/SetMem16.nasm | 11 ++++++----
.../BaseMemoryLibSse2/Ia32/SetMem32.nasm | 9 ++++++---
.../BaseMemoryLibSse2/Ia32/SetMem64.nasm | 20 +++++++++++++++----
.../BaseMemoryLibSse2/Ia32/ZeroMem.nasm | 11 ++++++----
.../Library/BaseMemoryLibSse2/X64/SetMem.nasm | 9 ++++++---
.../BaseMemoryLibSse2/X64/SetMem16.nasm | 11 ++++++----
.../BaseMemoryLibSse2/X64/SetMem32.nasm | 9 ++++++---
.../BaseMemoryLibSse2/X64/SetMem64.nasm | 19 ++++++++++++++----
.../BaseMemoryLibSse2/X64/ZeroMem.nasm | 13 +++++++-----
10 files changed, 85 insertions(+), 38 deletions(-)

diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
index 24313cb4b3..a8744300c6 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
@@ -34,7 +34,7 @@ ASM_PFX(InternalMemSetMem):
mov al, [esp + 16] ; al <- Value
xor ecx, ecx
sub ecx, edi
- and ecx, 15 ; ecx + edi aligns on 16-byte boundary
+ and ecx, 63 ; ecx + edi aligns on 16-byte boundary
jz .0
cmp ecx, edx
cmova ecx, edx
@@ -42,8 +42,8 @@ ASM_PFX(InternalMemSetMem):
rep stosb
.0:
mov ecx, edx
- and edx, 15
- shr ecx, 4 ; ecx <- # of DQwords to set
+ and edx, 63
+ shr ecx, 6 ; ecx <- # of DQwords to set
jz @SetBytes
mov ah, al ; ax <- Value | (Value << 8)
add esp, -16
@@ -53,7 +53,10 @@ ASM_PFX(InternalMemSetMem):
movlhps xmm0, xmm0 ; xmm0 <- Value repeats 16 times
.1:
movntdq [edi], xmm0 ; edi should be 16-byte aligned
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
movdqu xmm0, [esp] ; restore xmm0
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
index 6e308b5594..d461ee086c 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemSetMem16):
mov edi, [esp + 8]
xor ecx, ecx
sub ecx, edi
- and ecx, 15 ; ecx + edi aligns on 16-byte boundary
+ and ecx, 63 ; ecx + edi aligns on 16-byte boundary
mov eax, [esp + 16]
jz .0
shr ecx, 1
@@ -43,15 +43,18 @@ ASM_PFX(InternalMemSetMem16):
rep stosw
.0:
mov ecx, edx
- and edx, 7
- shr ecx, 3
+ and edx, 31
+ shr ecx, 5
jz @SetWords
movd xmm0, eax
pshuflw xmm0, xmm0, 0
movlhps xmm0, xmm0
.1:
movntdq [edi], xmm0 ; edi should be 16-byte aligned
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@SetWords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
index 2cfc8cb0dd..3ffdcd07d7 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
@@ -43,14 +43,17 @@ ASM_PFX(InternalMemSetMem32):
rep stosd
.0:
mov ecx, edx
- and edx, 3
- shr ecx, 2
+ and edx, 15
+ shr ecx, 4
jz @SetDwords
movd xmm0, eax
pshufd xmm0, xmm0, 0
.1:
movntdq [edi], xmm0
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@SetDwords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
index e153495a68..cd000648ae 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
@@ -38,17 +38,29 @@ ASM_PFX(InternalMemSetMem64):
add edx, 8
dec ecx
.0:
- shr ecx, 1
+ push ebx
+ mov ebx, ecx
+ and ebx, 7
+ shr ecx, 3
jz @SetQwords
movlhps xmm0, xmm0
.1:
movntdq [edx], xmm0
- lea edx, [edx + 16]
+ movntdq [edx + 16], xmm0
+ movntdq [edx + 32], xmm0
+ movntdq [edx + 48], xmm0
+ lea edx, [edx + 64]
loop .1
mfence
@SetQwords:
- jnc .2
+ test ebx, ebx
+ jz .3
+ mov ecx, ebx
+.2
movq qword [edx], xmm0
-.2:
+ lea edx, [edx + 8]
+ loop .2
+.3:
+ pop ebx
ret

diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
index cd34006f59..0e0828551b 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemZeroMem):
xor ecx, ecx
sub ecx, edi
xor eax, eax
- and ecx, 15
+ and ecx, 63
jz .0
cmp ecx, edx
cmova ecx, edx
@@ -41,13 +41,16 @@ ASM_PFX(InternalMemZeroMem):
rep stosb
.0:
mov ecx, edx
- and edx, 15
- shr ecx, 4
+ and edx, 63
+ shr ecx, 6
jz @ZeroBytes
pxor xmm0, xmm0
.1:
movntdq [edi], xmm0
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@ZeroBytes:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
index 5bd1c2262d..28b11ee586 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
@@ -42,8 +42,8 @@ ASM_PFX(InternalMemSetMem):
rep stosb
.0:
mov rcx, rdx
- and rdx, 15
- shr rcx, 4
+ and rdx, 63
+ shr rcx, 6
jz @SetBytes
mov ah, al ; ax <- Value repeats twice
movdqa [rsp + 0x10], xmm0 ; save xmm0
@@ -52,7 +52,10 @@ ASM_PFX(InternalMemSetMem):
movlhps xmm0, xmm0 ; xmm0 <- Value repeats 16 times
.1:
movntdq [rdi], xmm0 ; rdi should be 16-byte aligned
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
movdqa xmm0, [rsp + 0x10] ; restore xmm0
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
index 90d159820a..375be19313 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemSetMem16):
mov r9, rdi
xor rcx, rcx
sub rcx, rdi
- and rcx, 15
+ and rcx, 63
mov rax, r8
jz .0
shr rcx, 1
@@ -43,15 +43,18 @@ ASM_PFX(InternalMemSetMem16):
rep stosw
.0:
mov rcx, rdx
- and edx, 7
- shr rcx, 3
+ and edx, 31
+ shr rcx, 5
jz @SetWords
movd xmm0, eax
pshuflw xmm0, xmm0, 0
movlhps xmm0, xmm0
.1:
movntdq [rdi], xmm0
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@SetWords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
index 928e086889..5d12beaa9a 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
@@ -43,14 +43,17 @@ ASM_PFX(InternalMemSetMem32):
rep stosd
.0:
mov rcx, rdx
- and edx, 3
- shr rcx, 2
+ and edx, 15
+ shr rcx, 4
jz @SetDwords
movd xmm0, eax
pshufd xmm0, xmm0, 0
.1:
movntdq [rdi], xmm0
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@SetDwords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
index d771810542..265983d5ad 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
@@ -37,17 +37,28 @@ ASM_PFX(InternalMemSetMem64):
add rdx, 8
dec rcx
.0:
- shr rcx, 1
+ push rbx
+ mov rbx, rcx
+ and rbx, 7
+ shr rcx, 3
jz @SetQwords
movlhps xmm0, xmm0
.1:
movntdq [rdx], xmm0
- lea rdx, [rdx + 16]
+ movntdq [rdx + 16], xmm0
+ movntdq [rdx + 32], xmm0
+ movntdq [rdx + 48], xmm0
+ lea rdx, [rdx + 64]
loop .1
mfence
@SetQwords:
- jnc .2
- mov [rdx], r8
+ push rdi
+ mov rcx, rbx
+ mov rax, r8
+ mov rdi, rdx
+ rep stosq
+ pop rdi
.2:
+ pop rbx
ret

diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
index 5ddcae9ca5..21f504e3b7 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
@@ -32,7 +32,7 @@ ASM_PFX(InternalMemZeroMem):
xor rcx, rcx
xor eax, eax
sub rcx, rdi
- and rcx, 15
+ and rcx, 63
mov r8, rdi
jz .0
cmp rcx, rdx
@@ -41,13 +41,16 @@ ASM_PFX(InternalMemZeroMem):
rep stosb
.0:
mov rcx, rdx
- and edx, 15
- shr rcx, 4
+ and edx, 63
+ shr rcx, 6
jz @ZeroBytes
pxor xmm0, xmm0
.1:
- movntdq [rdi], xmm0 ; rdi should be 16-byte aligned
- add rdi, 16
+ movntdq [rdi], xmm0
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@ZeroBytes:
--
2.25.3


[PATCH] BaseMemoryLibSse2: Take advantage of write combining buffers

Compostella, Jeremy <jeremy.compostella@...>
 

The current SSE2 implementation of the ZeroMem(), SetMem(),
SetMem16(), SetMem32 and SetMem64 functions is writing 16 bytes per 16
bytes. It hurts the performances so bad that this is even slower than
a simple 'rep stos' (4% slower) in regular DRAM.

To take full advantages of the 'movntdq' instruction it is better to
"queue" a total of 64 bytes in the write combining buffers. This
patch implement such a change. Below is a table where I measured
(with 'rdtsc') the time to write an entire 100MB RAM buffer. These
functions operate almost two times faster.

| Function | Arch | Untouched | 64 bytes | Result |
|----------+------+-----------+----------+--------|
| ZeroMem | Ia32 | 17765947 | 9136062 | 1.945x |
| ZeroMem | X64 | 17525170 | 9233391 | 1.898x |
| SetMem | Ia32 | 17522291 | 9137272 | 1.918x |
| SetMem | X64 | 17949261 | 9176978 | 1.956x |
| SetMem16 | Ia32 | 18219673 | 9372062 | 1.944x |
| SetMem16 | X64 | 17523331 | 9275184 | 1.889x |
| SetMem32 | Ia32 | 18495036 | 9273053 | 1.994x |
| SetMem32 | X64 | 17368864 | 9285885 | 1.870x |
| SetMem64 | Ia32 | 18564473 | 9241362 | 2.009x |
| SetMem64 | X64 | 17506951 | 9280148 | 1.886x |

Signed-off-by: Jeremy Compostella <jeremy.compostella@...>
---
.../BaseMemoryLibSse2/Ia32/SetMem.nasm | 11 ++++++----
.../BaseMemoryLibSse2/Ia32/SetMem16.nasm | 11 ++++++----
.../BaseMemoryLibSse2/Ia32/SetMem32.nasm | 9 ++++++---
.../BaseMemoryLibSse2/Ia32/SetMem64.nasm | 20 +++++++++++++++----
.../BaseMemoryLibSse2/Ia32/ZeroMem.nasm | 11 ++++++----
.../Library/BaseMemoryLibSse2/X64/SetMem.nasm | 9 ++++++---
.../BaseMemoryLibSse2/X64/SetMem16.nasm | 11 ++++++----
.../BaseMemoryLibSse2/X64/SetMem32.nasm | 9 ++++++---
.../BaseMemoryLibSse2/X64/SetMem64.nasm | 19 ++++++++++++++----
.../BaseMemoryLibSse2/X64/ZeroMem.nasm | 13 +++++++-----
10 files changed, 85 insertions(+), 38 deletions(-)

diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
index 24313cb4b3..a8744300c6 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem.nasm
@@ -34,7 +34,7 @@ ASM_PFX(InternalMemSetMem):
mov al, [esp + 16] ; al <- Value
xor ecx, ecx
sub ecx, edi
- and ecx, 15 ; ecx + edi aligns on 16-byte boundary
+ and ecx, 63 ; ecx + edi aligns on 16-byte boundary
jz .0
cmp ecx, edx
cmova ecx, edx
@@ -42,8 +42,8 @@ ASM_PFX(InternalMemSetMem):
rep stosb
.0:
mov ecx, edx
- and edx, 15
- shr ecx, 4 ; ecx <- # of DQwords to set
+ and edx, 63
+ shr ecx, 6 ; ecx <- # of DQwords to set
jz @SetBytes
mov ah, al ; ax <- Value | (Value << 8)
add esp, -16
@@ -53,7 +53,10 @@ ASM_PFX(InternalMemSetMem):
movlhps xmm0, xmm0 ; xmm0 <- Value repeats 16 times
.1:
movntdq [edi], xmm0 ; edi should be 16-byte aligned
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
movdqu xmm0, [esp] ; restore xmm0
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
index 6e308b5594..d461ee086c 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem16.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemSetMem16):
mov edi, [esp + 8]
xor ecx, ecx
sub ecx, edi
- and ecx, 15 ; ecx + edi aligns on 16-byte boundary
+ and ecx, 63 ; ecx + edi aligns on 16-byte boundary
mov eax, [esp + 16]
jz .0
shr ecx, 1
@@ -43,15 +43,18 @@ ASM_PFX(InternalMemSetMem16):
rep stosw
.0:
mov ecx, edx
- and edx, 7
- shr ecx, 3
+ and edx, 31
+ shr ecx, 5
jz @SetWords
movd xmm0, eax
pshuflw xmm0, xmm0, 0
movlhps xmm0, xmm0
.1:
movntdq [edi], xmm0 ; edi should be 16-byte aligned
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@SetWords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
index 2cfc8cb0dd..3ffdcd07d7 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem32.nasm
@@ -43,14 +43,17 @@ ASM_PFX(InternalMemSetMem32):
rep stosd
.0:
mov ecx, edx
- and edx, 3
- shr ecx, 2
+ and edx, 15
+ shr ecx, 4
jz @SetDwords
movd xmm0, eax
pshufd xmm0, xmm0, 0
.1:
movntdq [edi], xmm0
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@SetDwords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
index e153495a68..cd000648ae 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/SetMem64.nasm
@@ -38,17 +38,29 @@ ASM_PFX(InternalMemSetMem64):
add edx, 8
dec ecx
.0:
- shr ecx, 1
+ push ebx
+ mov ebx, ecx
+ and ebx, 7
+ shr ecx, 3
jz @SetQwords
movlhps xmm0, xmm0
.1:
movntdq [edx], xmm0
- lea edx, [edx + 16]
+ movntdq [edx + 16], xmm0
+ movntdq [edx + 32], xmm0
+ movntdq [edx + 48], xmm0
+ lea edx, [edx + 64]
loop .1
mfence
@SetQwords:
- jnc .2
+ test ebx, ebx
+ jz .3
+ mov ecx, ebx
+.2
movq qword [edx], xmm0
-.2:
+ lea edx, [edx + 8]
+ loop .2
+.3:
+ pop ebx
ret

diff --git a/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
index cd34006f59..0e0828551b 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/Ia32/ZeroMem.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemZeroMem):
xor ecx, ecx
sub ecx, edi
xor eax, eax
- and ecx, 15
+ and ecx, 63
jz .0
cmp ecx, edx
cmova ecx, edx
@@ -41,13 +41,16 @@ ASM_PFX(InternalMemZeroMem):
rep stosb
.0:
mov ecx, edx
- and edx, 15
- shr ecx, 4
+ and edx, 63
+ shr ecx, 6
jz @ZeroBytes
pxor xmm0, xmm0
.1:
movntdq [edi], xmm0
- add edi, 16
+ movntdq [edi + 16], xmm0
+ movntdq [edi + 32], xmm0
+ movntdq [edi + 48], xmm0
+ add edi, 64
loop .1
mfence
@ZeroBytes:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
index 5bd1c2262d..28b11ee586 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem.nasm
@@ -42,8 +42,8 @@ ASM_PFX(InternalMemSetMem):
rep stosb
.0:
mov rcx, rdx
- and rdx, 15
- shr rcx, 4
+ and rdx, 63
+ shr rcx, 6
jz @SetBytes
mov ah, al ; ax <- Value repeats twice
movdqa [rsp + 0x10], xmm0 ; save xmm0
@@ -52,7 +52,10 @@ ASM_PFX(InternalMemSetMem):
movlhps xmm0, xmm0 ; xmm0 <- Value repeats 16 times
.1:
movntdq [rdi], xmm0 ; rdi should be 16-byte aligned
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
movdqa xmm0, [rsp + 0x10] ; restore xmm0
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
index 90d159820a..375be19313 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem16.nasm
@@ -33,7 +33,7 @@ ASM_PFX(InternalMemSetMem16):
mov r9, rdi
xor rcx, rcx
sub rcx, rdi
- and rcx, 15
+ and rcx, 63
mov rax, r8
jz .0
shr rcx, 1
@@ -43,15 +43,18 @@ ASM_PFX(InternalMemSetMem16):
rep stosw
.0:
mov rcx, rdx
- and edx, 7
- shr rcx, 3
+ and edx, 31
+ shr rcx, 5
jz @SetWords
movd xmm0, eax
pshuflw xmm0, xmm0, 0
movlhps xmm0, xmm0
.1:
movntdq [rdi], xmm0
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@SetWords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
index 928e086889..5d12beaa9a 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem32.nasm
@@ -43,14 +43,17 @@ ASM_PFX(InternalMemSetMem32):
rep stosd
.0:
mov rcx, rdx
- and edx, 3
- shr rcx, 2
+ and edx, 15
+ shr rcx, 4
jz @SetDwords
movd xmm0, eax
pshufd xmm0, xmm0, 0
.1:
movntdq [rdi], xmm0
- add rdi, 16
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@SetDwords:
diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
index d771810542..265983d5ad 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/SetMem64.nasm
@@ -37,17 +37,28 @@ ASM_PFX(InternalMemSetMem64):
add rdx, 8
dec rcx
.0:
- shr rcx, 1
+ push rbx
+ mov rbx, rcx
+ and rbx, 7
+ shr rcx, 3
jz @SetQwords
movlhps xmm0, xmm0
.1:
movntdq [rdx], xmm0
- lea rdx, [rdx + 16]
+ movntdq [rdx + 16], xmm0
+ movntdq [rdx + 32], xmm0
+ movntdq [rdx + 48], xmm0
+ lea rdx, [rdx + 64]
loop .1
mfence
@SetQwords:
- jnc .2
- mov [rdx], r8
+ push rdi
+ mov rcx, rbx
+ mov rax, r8
+ mov rdi, rdx
+ rep stosq
+ pop rdi
.2:
+ pop rbx
ret

diff --git a/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm b/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
index 5ddcae9ca5..21f504e3b7 100644
--- a/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
+++ b/MdePkg/Library/BaseMemoryLibSse2/X64/ZeroMem.nasm
@@ -32,7 +32,7 @@ ASM_PFX(InternalMemZeroMem):
xor rcx, rcx
xor eax, eax
sub rcx, rdi
- and rcx, 15
+ and rcx, 63
mov r8, rdi
jz .0
cmp rcx, rdx
@@ -41,13 +41,16 @@ ASM_PFX(InternalMemZeroMem):
rep stosb
.0:
mov rcx, rdx
- and edx, 15
- shr rcx, 4
+ and edx, 63
+ shr rcx, 6
jz @ZeroBytes
pxor xmm0, xmm0
.1:
- movntdq [rdi], xmm0 ; rdi should be 16-byte aligned
- add rdi, 16
+ movntdq [rdi], xmm0
+ movntdq [rdi + 16], xmm0
+ movntdq [rdi + 32], xmm0
+ movntdq [rdi + 48], xmm0
+ add rdi, 64
loop .1
mfence
@ZeroBytes:
--
2.25.3


Re: [PATCH v1 1/1] ShellPkg/UefiShellAcpiViewCommandLib: acpi version update for GTDT

Shashi Mallela
 

Hi Lief,

The macro has only been updated to reflect the latest ACPI version 6.3 and stay in sync with the edk2-platform gtdt updates made for sbsa platform
based on the same ACPI version 6.3.

Thanks
Shashi


Re: [PATCH v1 1/1] ShellPkg/UefiShellAcpiViewCommandLib: acpi version update for GTDT

Shashi Mallela
 

Hi Lief,

The macro is only updated to reflect the latest ACPI version being considered for GTDT.Since i had updated the edk2-platform code to use the latest structure definitions from EFI_ACPI_6_3,did the same
here for version number consistency.

Thanks
Shashi


回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".

gaoliming
 

The pull request needs rebase. I will submit new pull request today.

Thanks
Liming

-----邮件原件-----
发件人: Liu, Zhiguang <zhiguang.liu@...>
发送时间: 2020年10月10日 8:49
收件人: gaoliming <gaoliming@...>; devel@edk2.groups.io
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
'Sean Brogan' <spbrogan@...>
主题: RE: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding DDR5
definitions".

Hi Liming

In pull request https://github.com/tianocore/edk2/pull/996
Merge failed because
tanocore.PatchCheck Failing after 34s — Build #20201009.4 failed

Detail:
The commit message format is not valid:
* Missing Signed-off-by! (Note: this must be added by the code contributor!)
https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-For
mat

However, I abstract the patch from Outlook and run PatchCheck to check it in
my local machine, the result is ok.

Detail:
E:\edk2\BaseTools\Scripts>py PatchCheck.py
0001-MdePkg-SMBIOS-3.4.0-Update-adding-DDR5-definitions-.patch
Checking patch file:
0001-MdePkg-SMBIOS-3.4.0-Update-adding-DDR5-definitions-.patch
[PATCH] MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".
The commit message format passed all checks.
The code passed all checks.

Do you know why?

Thanks
Zhiguang
-----Original Message-----
From: gaoliming <gaoliming@...>
Sent: Friday, October 9, 2020 5:21 PM
To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@...>
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
'Sean
Brogan' <spbrogan@...>
Subject: 回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

https://github.com/tianocore/edk2/pull/996 is created.

-----邮件原件-----
发件人: bounce+27952+66054+4905953+8761045@groups.io
<bounce+27952+66054+4905953+8761045@groups.io> 代表 Zhiguang
Liu
发送时间: 2020年10月9日 15:24
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Gao, Zhichao <zhichao.gao@...>;
Sean Brogan <spbrogan@...>
主题: Re: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update "adding
DDR5
definitions".

Hi Liming,
This patch also gets R-B from Sean Brogan.
Please help merge this patch.

Thanks
Zhiguang

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, September 30, 2020 8:45 AM
To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@...>
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>
Subject: 回复: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

Reviewed-by: Liming Gao <gaoliming@...>

-----邮件原件-----
发件人: bounce+27952+65712+4905953+8761045@groups.io
<bounce+27952+65712+4905953+8761045@groups.io> 代表
Zhiguang
Liu
发送时间: 2020年9月29日 16:12
收件人: devel@edk2.groups.io; Liu, Zhiguang
<zhiguang.liu@...>
抄送: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Liming Gao
<gaoliming@...>
主题: Re: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5
definitions".


Reviewed-by: Zhiguang Liu <zhiguang.liu@...>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Zhiguang
Liu
Sent: Tuesday, September 29, 2020 4:09 PM
To: devel@edk2.groups.io
Cc: Wang, Sanyo <sanyo.wang@...>; Kinney, Michael D
<michael.d.kinney@...>; Liming Gao
<gaoliming@...>
Subject: [edk2-devel] [PATCH] MdePkg: SMBIOS 3.4.0 Update
"adding
DDR5 definitions".

From: "Wang, Sanyo" <sanyo.wang@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352

SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5)

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Sanyo Wang <sanyo.wang@...>
---
MdePkg/Include/IndustryStandard/SmBios.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/IndustryStandard/SmBios.h
b/MdePkg/Include/IndustryStandard/SmBios.h
index ea23685851..f2db11f947 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1718,7 +1718,9 @@ typedef enum {
MemoryTypeLpddr4 = 0x1E,

MemoryTypeLogicalNonVolatileDevice = 0x1F,

MemoryTypeHBM = 0x20,

- MemoryTypeHBM2 = 0x21

+ MemoryTypeHBM2 = 0x21,

+ MemoryTypeDdr5 = 0x22,

+ MemoryTypeLpddr5 = 0x23

} MEMORY_DEVICE_TYPE;



///

--
2.25.1.windows.1



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