Date   

who can help restore the iBFT spec link to working state?

Laszlo Ersek
 

Hi,

the iBFT spec link

http://www.microsoft.com/whdc/system/platform/firmware/ibft.mspx

as shown at

https://uefi.org/acpi

does not work (it has not worked since at least August 13th, which is
when I first reported this issue on the ASWG mailing list).

Who from Microsoft can please help the community with a working, stable
link to the iBFT spec?

Thanks,
Laszlo


Re: [PATCH v1 1/1] UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.

Zeng, Star
 

A little surprised by "Average time taken to find CpuCrystalFrequencyHob: about 2000 ns".
It depends on the hob is built early or late?
Seemingly, NanoSecondDelay() will always have some deviation.

Thanks,
Star

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Laszlo Ersek
Sent: Friday, September 25, 2020 2:46 PM
To: Ni, Ray <ray.ni@intel.com>; Lou, Yun <yun.lou@intel.com>; devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>
Subject: Re: [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.

On 09/25/20 07:25, Ni, Ray wrote:
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

Thanks
Laszlo


-----Original Message-----
From: Lou, Yun <yun.lou@intel.com>
Sent: Friday, September 25, 2020 11:58 AM
To: devel@edk2.groups.io
Cc: Lou, Yun <yun.lou@intel.com>; Ni, Ray <ray.ni@intel.com>; Dong,
Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar,
Rahul1 <rahul1.kumar@intel.com>
Subject: [PATCH v1 1/1] UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2832

1. Remove PEI instance(PeiCpuTimerLib).
PeiCpuTimerLib is currently designed to save time by getting CPU TSC frequncy from Hob.
BaseCpuTimerLib is designed to calculate TSC frequency by using CPUID[15h] each time.
The time it takes to find CpuCrystalFrequencyHob (about 2000ns) is
much longer than it takes to calculate TSC frequency with CPUID[15h]
(about 450ns), which means using BaseCpuTimerLib to trigger a delay
is more accurate than using PeiCpuTimerLib, recommend to use BaseCpuTimerLib instead of PeiCpuTimerLib.

2. Remove DXE instance(DxeCpuTimerLib).
DxeCpuTimerLib is designed to calculate TSC frequency with CPUID[15h]
in its constructor function, then save it in a global variable. For
this design, once the driver containing this instance is running, the constructor function is called, it will take extra time to calculate TSC frequency.
The time it takes to get TSC frequncy from global variable is shorter
than it takes to calculate TSC frequency with CPUID[15h], but 450ns is a short time, the impact on the platform is very limited.
In addition, in order to simplify the code, recommend to use BaseCpuTimerLib instead of DxeCpuTimerLib.

I did some experiments on one Intel server platform and collected the following data:
1. Average time taken to find CpuCrystalFrequencyHob: about 2000 ns.
2. Average time taken to calculate TSC frequency: about 450 ns.

Reference code:
//
// Calculate average time taken to find Hob.
//
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - GetFirstGuidHob (1000 cycles)\n"));
Ticks1 = AsmReadTsc();
for (i = 0; i < 1000; i++) {
GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);
}
Ticks2 = AsmReadTsc();

if (GuidHob == NULL) {
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - CpuCrystalFrequencyHob can not be found!\n"));
} else {
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - Average time taken to find Hob = %d ns\n", \
DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1),
1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));
}

//
// Calculate average time taken to calculate CPU frequency.
//
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib]
GetPerformanceCounterFrequency - CpuidCoreClockCalculateTscFrequency
(1000 cycles)\n"));
Ticks1 = AsmReadTsc();
for (i = 0; i < 1000; i++) {
Freq = CpuidCoreClockCalculateTscFrequency ();
}
Ticks2 = AsmReadTsc();
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - Average time taken to calculate TSC frequency = %d ns\n", \
DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1),
1000000000), *CpuCrystalCounterFrequency, NULL), 1000)));

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c | 85 --------------------
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c | 58 -------------
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf | 37 ---------
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni | 17 ----
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf | 36 ---------
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni | 17 ----
UefiCpuPkg/UefiCpuPkg.dsc | 4 +-
7 files changed, 1 insertion(+), 253 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
deleted file mode 100644
index 269e5a3e83d7..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/** @file

- CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer Library.

-

- Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>

- SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#include <PiDxe.h>

-#include <Library/TimerLib.h>

-#include <Library/BaseLib.h>

-#include <Library/HobLib.h>

-

-extern GUID mCpuCrystalFrequencyHobGuid;

-

-/**

- CPUID Leaf 0x15 for Core Crystal Clock Frequency.

-

- The TSC counting frequency is determined by using CPUID leaf 0x15. Frequency in MHz = Core XTAL frequency * EBX/EAX.

- In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not supported.

- @return The number of TSC counts per second.

-

-**/

-UINT64

-CpuidCoreClockCalculateTscFrequency (

- VOID

- );

-

-//

-// Cached CPU Crystal counter frequency

-//

-UINT64 mCpuCrystalCounterFrequency = 0;

-

-

-/**

- Internal function to retrieves the 64-bit frequency in Hz.

-

- Internal function to retrieves the 64-bit frequency in Hz.

-

- @return The frequency in Hz.

-

-**/

-UINT64

-InternalGetPerformanceCounterFrequency (

- VOID

- )

-{

- return mCpuCrystalCounterFrequency;

-}

-

-/**

- The constructor function is to initialize CpuCrystalCounterFrequency.

-

- @param ImageHandle The firmware allocated handle for the EFI image.

- @param SystemTable A pointer to the EFI System Table.

-

- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.

-

-**/

-EFI_STATUS

-EFIAPI

-DxeCpuTimerLibConstructor (

- IN EFI_HANDLE ImageHandle,

- IN EFI_SYSTEM_TABLE *SystemTable

- )

-{

- EFI_HOB_GUID_TYPE *GuidHob;

-

- //

- // Initialize CpuCrystalCounterFrequency

- //

- GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);

- if (GuidHob != NULL) {

- mCpuCrystalCounterFrequency = *(UINT64*)GET_GUID_HOB_DATA (GuidHob);

- } else {

- mCpuCrystalCounterFrequency = CpuidCoreClockCalculateTscFrequency ();

- }

-

- if (mCpuCrystalCounterFrequency == 0) {

- return EFI_UNSUPPORTED;

- }

-

- return EFI_SUCCESS;

-}

-

diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
deleted file mode 100644
index 91a721205653..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/** @file

- CPUID Leaf 0x15 for Core Crystal Clock frequency instance as PEI Timer Library.

-

- Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>

- SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#include <PiPei.h>

-#include <Library/TimerLib.h>

-#include <Library/BaseLib.h>

-#include <Library/HobLib.h>

-#include <Library/DebugLib.h>

-

-extern GUID mCpuCrystalFrequencyHobGuid;

-

-/**

- CPUID Leaf 0x15 for Core Crystal Clock Frequency.

-

- The TSC counting frequency is determined by using CPUID leaf 0x15. Frequency in MHz = Core XTAL frequency * EBX/EAX.

- In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not supported.

- @return The number of TSC counts per second.

-

-**/

-UINT64

-CpuidCoreClockCalculateTscFrequency (

- VOID

- );

-

-/**

- Internal function to retrieves the 64-bit frequency in Hz.

-

- Internal function to retrieves the 64-bit frequency in Hz.

-

- @return The frequency in Hz.

-

-**/

-UINT64

-InternalGetPerformanceCounterFrequency (

- VOID

- )

-{

- UINT64 *CpuCrystalCounterFrequency;

- EFI_HOB_GUID_TYPE *GuidHob;

-

- CpuCrystalCounterFrequency = NULL;

- GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);

- if (GuidHob == NULL) {

- CpuCrystalCounterFrequency = (UINT64*)BuildGuidHob(&mCpuCrystalFrequencyHobGuid, sizeof
(*CpuCrystalCounterFrequency));

- ASSERT (CpuCrystalCounterFrequency != NULL);

- *CpuCrystalCounterFrequency = CpuidCoreClockCalculateTscFrequency ();

- } else {

- CpuCrystalCounterFrequency = (UINT64*)GET_GUID_HOB_DATA (GuidHob);

- }

-

- return *CpuCrystalCounterFrequency;

-}

-

diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
deleted file mode 100644
index 6c83549c87da..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
+++ /dev/null
@@ -1,37 +0,0 @@
-## @file

-# DXE CPU Timer Library

-#

-# Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency. The performance

-# counter features are provided by the processors time stamp counter.

-#

-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-#

-##

-

-[Defines]

- INF_VERSION = 0x00010005

- BASE_NAME = DxeCpuTimerLib

- FILE_GUID = F22CC0DA-E7DB-4E4D-ABE2-A608188233A2

- MODULE_TYPE = DXE_DRIVER

- VERSION_STRING = 1.0

- LIBRARY_CLASS = TimerLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
UEFI_APPLICATION UEFI_DRIVER SMM_CORE

- CONSTRUCTOR = DxeCpuTimerLibConstructor

- MODULE_UNI_FILE = DxeCpuTimerLib.uni

-

-[Sources]

- CpuTimerLib.c

- DxeCpuTimerLib.c

-

-[Packages]

- MdePkg/MdePkg.dec

- UefiCpuPkg/UefiCpuPkg.dec

-

-[LibraryClasses]

- BaseLib

- PcdLib

- DebugLib

- HobLib

-

-[Pcd]

- gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
CONSUMES

diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
deleted file mode 100644
index f55b92abace7..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
+++ /dev/null
@@ -1,17 +0,0 @@
-// /** @file

-// DXE CPU Timer Library

-//

-// Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency. The performance

-// counter features are provided by the processors time stamp counter.

-//

-// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>

-//

-// SPDX-License-Identifier: BSD-2-Clause-Patent

-//

-// **/

-

-

-#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library"

-

-#string STR_MODULE_DESCRIPTION #language en-US "Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency."

-

diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
deleted file mode 100644
index 7af0fc44a65d..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
+++ /dev/null
@@ -1,36 +0,0 @@
-## @file

-# PEI CPU Timer Library

-#

-# Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency. The performance

-# counter features are provided by the processors time stamp counter.

-#

-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>

-# SPDX-License-Identifier: BSD-2-Clause-Patent

-#

-##

-

-[Defines]

- INF_VERSION = 0x00010005

- BASE_NAME = PeiCpuTimerLib

- FILE_GUID = 2B13DE00-1A5F-4DD7-A298-01B08AF1015A

- MODULE_TYPE = BASE

- VERSION_STRING = 1.0

- LIBRARY_CLASS = TimerLib|PEI_CORE PEIM

- MODULE_UNI_FILE = PeiCpuTimerLib.uni

-

-[Sources]

- CpuTimerLib.c

- PeiCpuTimerLib.c

-

-[Packages]

- MdePkg/MdePkg.dec

- UefiCpuPkg/UefiCpuPkg.dec

-

-[LibraryClasses]

- BaseLib

- PcdLib

- DebugLib

- HobLib

-

-[Pcd]

- gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
CONSUMES

diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
deleted file mode 100644
index 49beb44908d6..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
+++ /dev/null
@@ -1,17 +0,0 @@
-// /** @file

-// PEI CPU Timer Library

-//

-// Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency. The performance

-// counter features are provided by the processors time stamp counter.

-//

-// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>

-//

-// SPDX-License-Identifier: BSD-2-Clause-Patent

-//

-// **/

-

-

-#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library"

-

-#string STR_MODULE_DESCRIPTION #language en-US "Provides basic timer support using CPUID Leaf 0x15 XTAL
frequency."

-

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index b2b6d78a71b0..e915b5c81b66 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -1,7 +1,7 @@
## @file

# UefiCpuPkg Package

#

-# Copyright (c) 2007 - 2019, Intel Corporation. All rights
reserved.<BR>

+# Copyright (c) 2007 - 2020, Intel Corporation. All rights
+reserved.<BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

@@ -107,8 +107,6 @@ [Components]

UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.
inf

UefiCpuPkg/Application/Cpuid/Cpuid.inf

UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf

- UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf

- UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf



[Components.IA32, Components.X64]

UefiCpuPkg/CpuDxe/CpuDxe.inf

--
2.28.0.windows.1


[PATCH v2 1/2] MdePkg: Definitions for Extended Interrupt Flags

Sami Mujawar
 

Add Interrupt Vector Flag definitions for Extended Interrupt
Descriptor, and macros to test the flags.
Ref: ACPI specification 6.4.3.6

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2
- Updated based on review comments to just define the bit [SAMI]
locations. Also dropped the IS_xxx macros.

MdePkg/Include/IndustryStandard/Acpi10.h | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index adeb5ae8c219f31d2403fc7aa217bfb4e1e44694..7ac9b967b54dcc92f2c20366bf1ff08d67c4c971 100644
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -2,6 +2,7 @@
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

@@ -377,6 +378,16 @@ typedef struct {
#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00

//
+// Interrupt Vector Flags definitions for Extended Interrupt Descriptor
+// Ref ACPI specification 6.4.3.6
+//
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
+
+//
// Ensure proper structure formats
//
#pragma pack(1)
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 2/2] DynamicTablesPkg: Add SSDT CMN-600 Table generator

Sami Mujawar
 

From: Pierre Gondois <pierre.gondois@arm.com>

The Generic ACPI for Arm Components 1.0 Platform Design
Document, s2.6.4 "ASL code examples" provides information
to describe an Arm CoreLink CMN-600 Coherent Mesh Network
using an ASL definition block table.

The SSDT CMN-600 Table Generator uses the Configuration
Manager protocol to obtain the following information about
the CMN-600 device on the platform:
- the PERIPHBASE address location and address range;
- the ROOTNODEBASE address location;
- the number of Debug and Trace Controller (DTC)
and their respective interrupt number;

The CMN-600 mesh is described using the CM_ARM_CMN_600_INFO
and CM_ARM_EXTENDED_INTERRUPT structures in the Configuration
Manager.

The SSDT CMN-600 Table generator:
- gets the CMN-600 hardware information
from the configuration manager.
- uses the AmlLib interfaces to parse the AML
template BLOB and construct an AML tree.
- uses the AmlLib to update:
- the "_UID" value;
- the address location and range of the PERIPHBASE;
- the address location of the ROOTNODEBASE;
- the number of Debug and Trace Controller (DTC)
and their respective interrupt number;
- serializes the AML tree to an output buffer.
This output buffer contains the fixed-up AML code,
which is then installed as an ACPI SSDT table.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Co-authored-by: Sami Mujawar <sami.mujawar@arm.com>
---

Notes:
v2:
- Updates corresponding to changes done in Acpi10.h based on [SAMI]
review comments for [PATCH v1 1/1].

DynamicTablesPkg/DynamicTables.dsc.inc | 2 +
DynamicTablesPkg/DynamicTablesPkg.ci.yaml | 4 +
DynamicTablesPkg/Include/AcpiTableGenerator.h | 5 +
DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 64 +-
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c | 708 ++++++++++++++++++++
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h | 51 ++
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf | 34 +
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl | 81 +++
8 files changed, 943 insertions(+), 6 deletions(-)

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc b/DynamicTablesPkg/DynamicTables.dsc.inc
index 7fb14d8d1463f7d4502fd3a7708bc94bc336357d..fa33b7ee67e615e236cb13224c859594566df19f 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -34,6 +34,7 @@ [Components.common]

# AML Fixup
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortLibArm.inf
+ DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf

#
# Dynamic Table Factory Dxe
@@ -53,6 +54,7 @@ [Components.common]

# AML Fixup
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortLibArm.inf
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
}

#
diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
index c0d09e79fdf7f6003b5bbda45abc82a0caf4e53f..52c8c2ab4aefb21bea0289a4fd02209ae937a221 100644
--- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
+++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
@@ -70,6 +70,7 @@
# in matching files
"ExtendWords": [
"ARMHB", # ARMHB000
+ "ARMHC", # ARMHC600
"ARMLTD",
"EISAID",
"CCIDX",
@@ -81,8 +82,11 @@
"lgreater",
"lless",
"MPIDR",
+ "PERIPHBASE",
"pytool",
"Roadmap",
+ "ROOTNODEBASE",
+ "ssdtcmn",
"ssdtserialporttemplate",
"SMMUV",
"standardised",
diff --git a/DynamicTablesPkg/Include/AcpiTableGenerator.h b/DynamicTablesPkg/Include/AcpiTableGenerator.h
index ef5018c312c1abbc205a06b037ffd6063cf02f0a..352331d6dc957b664d31d55b50efcce5b90d8ada 100644
--- a/DynamicTablesPkg/Include/AcpiTableGenerator.h
+++ b/DynamicTablesPkg/Include/AcpiTableGenerator.h
@@ -59,6 +59,10 @@ The Dynamic Tables Framework implements the following ACPI table generators:
The SSDT Serial generator collates the Serial port information
from the Configuration Manager and patches the SSDT Serial Port
template to build the SSDT Serial port table.
+ - SSDT CMN-600:
+ The SSDT CMN-600 generator collates the CMN-600 information
+ from the Configuration Manager and patches the SSDT CMN-600
+ template to build the SSDT CMN-600 table.
*/

/** The ACPI_TABLE_GENERATOR_ID type describes ACPI table generator ID.
@@ -83,6 +87,7 @@ typedef enum StdAcpiTableId {
EStdAcpiTableIdPptt, ///< PPTT Generator
EStdAcpiTableIdSrat, ///< SRAT Generator
EStdAcpiTableIdSsdtSerialPort, ///< SSDT Serial-Port Generator
+ EStdAcpiTableIdSsdtCmn600, ///< SSDT Cmn-600 Generator
EStdAcpiTableIdMax
} ESTD_ACPI_TABLE_ID;

diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index b2534a6505d6fb695f0751bbb09d365bd93d092e..f0654866444e5497a010f7e7177199604f5d32b6 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -57,6 +57,7 @@ typedef enum ArmObjectID {
EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci
EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info
+ EArmObjCmn600Info, ///< 36 - CMN-600 Info
EArmObjMax
} EARM_OBJECT_ID;

@@ -653,18 +654,37 @@ typedef struct CmArmIdMapping {
UINT32 Flags;
} CM_ARM_ID_MAPPING;

-/** A structure that describes the
- SMMU interrupts for the Platform.
-
- ID: EArmObjSmmuInterruptArray
+/** A structure that describes the Arm
+ Generic Interrupts.
*/
-typedef struct CmArmSmmuInterrupt {
+typedef struct CmArmGenericInterrupt {
/// Interrupt number
UINT32 Interrupt;

/// Flags
UINT32 Flags;
-} CM_ARM_SMMU_INTERRUPT;
+} CM_ARM_GENERIC_INTERRUPT;
+
+/** A structure that describes the SMMU interrupts for the Platform.
+
+ Interrupt Interrupt number.
+ Flags Interrupt flags as defined for SMMU node.
+
+ ID: EArmObjSmmuInterruptArray
+*/
+typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;
+
+/** A structure that describes the AML Extended Interrupts.
+
+ Interrupt Interrupt number.
+ Flags Interrupt flags as defined by the Interrupt
+ Vector Flags (Byte 3) of the Extended Interrupt
+ resource descriptor.
+ See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h
+
+ ID: EArmObjExtendedInterruptInfo
+*/
+typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;

/** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT

@@ -825,6 +845,38 @@ typedef struct CmArmGenericInitiatorAffinityInfo {
CM_OBJECT_TOKEN DeviceHandleToken;
} CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;

+/** A structure that describes the CMN-600 hardware.
+
+ ID: EArmObjCmn600Info
+*/
+typedef struct CmArmCmn600Info {
+ /// The PERIPHBASE address.
+ /// Corresponds to the Configuration Node Region (CFGR) base address.
+ UINT64 PeriphBaseAddress;
+
+ /// The PERIPHBASE address length.
+ /// Corresponds to the CFGR base address length.
+ UINT64 PeriphBaseAddressLength;
+
+ /// The ROOTNODEBASE address.
+ /// Corresponds to the Root node (ROOT) base address.
+ UINT64 RootNodeBaseAddress;
+
+ /// The Debug and Trace Logic Controller (DTC) count.
+ /// CMN-600 can have maximum 4 DTCs.
+ UINT8 DtcCount;
+
+ /// DTC Interrupt list.
+ /// The first interrupt resource descriptor pertains to
+ /// DTC[0], the second to DTC[1] and so on.
+ /// DtcCount determines the number of DTC Interrupts that
+ /// are populated. If DTC count is 2 then DtcInterrupt[2]
+ /// and DtcInterrupt[3] are ignored.
+ /// Note: The size of CM_ARM_CMN_600_INFO structure remains
+ /// constant and does not vary with the DTC count.
+ CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];
+} CM_ARM_CMN_600_INFO;
+
#pragma pack()

#endif // ARM_NAMESPACE_OBJECTS_H_
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
new file mode 100644
index 0000000000000000000000000000000000000000..97a5c55fa3f60b6885862a76223994ab5c3daa26
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
@@ -0,0 +1,708 @@
+/** @file
+ SSDT CMN-600 AML Table Generator.
+
+ Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - Arm CoreLink CMN-600 Coherent Mesh Network Technical Reference Manual r3p0
+ - Generic ACPI for Arm Components 1.0 Platform Design Document
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiTable.h>
+
+// Module specific include files.
+#include <AcpiTableGenerator.h>
+#include <ConfigurationManagerObject.h>
+#include <ConfigurationManagerHelper.h>
+#include <Library/AmlLib/AmlLib.h>
+#include <Library/TableHelperLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+#include "SsdtCmn600Generator.h"
+
+/** C array containing the compiled AML template.
+ This symbol is defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 ssdtcmn600template_aml_code[];
+
+/** SSDT CMN-600 Table Generator.
+
+ Requirements:
+ The following Configuration Manager Object(s) are required by
+ this Generator:
+ - EArmObjCmn600Info
+*/
+
+/** This macro expands to a function that retrieves the CMN-600
+ Information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjCmn600Info,
+ CM_ARM_CMN_600_INFO
+ );
+
+/** Check the CMN-600 Information.
+
+ @param [in] Cmn600InfoList Array of CMN-600 information structure.
+ @param [in] Cmn600Count Count of CMN-600 information structure.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+ValidateCmn600Info (
+ IN CONST CM_ARM_CMN_600_INFO * Cmn600InfoList,
+ IN CONST UINT32 Cmn600Count
+ )
+{
+ UINT32 Index;
+ UINT32 DtcIndex;
+ CONST CM_ARM_CMN_600_INFO * Cmn600Info;
+ CONST CM_ARM_GENERIC_INTERRUPT * DtcInterrupt;
+
+ if ((Cmn600InfoList == NULL) ||
+ (Cmn600Count == 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Validate each Cmn600Info structure.
+ for (Index = 0; Index < Cmn600Count; Index++) {
+ Cmn600Info = &Cmn600InfoList[Index];
+
+ // At least one DTC is required.
+ if ((Cmn600Info->DtcCount == 0) ||
+ (Cmn600Info->DtcCount > MAX_DTC_COUNT)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Invalid DTC configuration:\n"
+ ));
+ goto error_handler;
+ }
+
+ // Check PERIPHBASE and ROOTNODEBASE address spaces are initialized.
+ if ((Cmn600Info->PeriphBaseAddress == 0) ||
+ (Cmn600Info->RootNodeBaseAddress == 0)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Invalid PERIPHBASE or ROOTNODEBASE.\n"
+ ));
+ goto error_handler;
+ }
+
+ // The PERIPHBASE address must be 64MB aligned for a (X < 4) && (Y < 4)
+ // dimension mesh, and 256MB aligned otherwise.
+ // Check it is a least 64MB aligned.
+ if ((Cmn600Info->PeriphBaseAddress &
+ (PERIPHBASE_MIN_ADDRESS_LENGTH - 1)) != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: PERIPHBASE address must be 64MB aligned.\n"
+ ));
+ goto error_handler;
+ }
+
+ // The PERIPHBASE address is at most 64MB for a (X < 4) && (Y < 4)
+ // dimension mesh, and 256MB otherwise. Check it is not more than 256MB.
+ if (Cmn600Info->PeriphBaseAddressLength > PERIPHBASE_MAX_ADDRESS_LENGTH) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: PERIPHBASE address range must be < 256MB.\n"
+ ));
+ goto error_handler;
+ }
+
+ // Check the 16 KB alignment of the ROOTNODEBASE address.
+ if ((Cmn600Info->PeriphBaseAddress &
+ (ROOTNODEBASE_ADDRESS_LENGTH - 1)) != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Root base address must be 16KB aligned.\n"
+ ));
+ goto error_handler;
+ }
+
+ // The ROOTNODEBASE address space should be included in the PERIPHBASE
+ // address space.
+ if ((Cmn600Info->PeriphBaseAddress > Cmn600Info->RootNodeBaseAddress) ||
+ ((Cmn600Info->PeriphBaseAddress + Cmn600Info->PeriphBaseAddressLength) <
+ (Cmn600Info->RootNodeBaseAddress + ROOTNODEBASE_ADDRESS_LENGTH))) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600:"
+ " ROOTNODEBASE address space not in PERIPHBASE address space.\n"
+ ));
+ goto error_handler;
+ }
+
+ for (DtcIndex = 0; DtcIndex < Cmn600Info->DtcCount; DtcIndex++) {
+ DtcInterrupt = &Cmn600Info->DtcInterrupt[DtcIndex];
+ if (((DtcInterrupt->Flags &
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK) == 0)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: DTC Interrupt must be consumer.\n"
+ ));
+ goto error_handler;
+ }
+ } // for DTC Interrupt
+
+ } //for Cmn600InfoList
+
+ return EFI_SUCCESS;
+
+error_handler:
+
+ DEBUG ((
+ DEBUG_ERROR,
+ "PeriphBaseAddress = 0x%llx\n"
+ "PeriphBaseAddressLength = 0x%llx\n"
+ "RootNodeBaseAddress = 0x%llx\n"
+ "DtcCount = %u\n",
+ Cmn600Info->PeriphBaseAddress,
+ Cmn600Info->PeriphBaseAddressLength,
+ Cmn600Info->RootNodeBaseAddress,
+ Cmn600Info->DtcCount
+ ));
+
+ DEBUG_CODE (
+ for (DtcIndex = 0; DtcIndex < Cmn600Info->DtcCount; DtcIndex++) {
+ DtcInterrupt = &Cmn600Info->DtcInterrupt[DtcIndex];
+ DEBUG ((
+ DEBUG_ERROR,
+ " DTC[%d]:\n",
+ DtcIndex
+ ));
+ DEBUG ((
+ DEBUG_ERROR,
+ " Interrupt = 0x%lx\n",
+ DtcInterrupt->Interrupt
+ ));
+ DEBUG ((
+ DEBUG_ERROR,
+ " Flags = 0x%lx\n",
+ DtcInterrupt->Flags
+ ));
+ } // for
+ );
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/** Build a SSDT table describing the CMN-600 device.
+
+ The table created by this function must be freed by FreeSsdtCmn600Table.
+
+ @param [in] Cmn600Info Pointer to a Cmn600 structure.
+ @param [in] Name The Name to give to the Device.
+ Must be a NULL-terminated ASL NameString
+ e.g.: "DEV0", "DV15.DEV0", etc.
+ @param [in] Uid UID for the CMN600 device.
+ @param [out] Table If success, pointer to the created SSDT table.
+
+ @retval EFI_SUCCESS Table generated successfully.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND Could not find information.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+FixupCmn600Info (
+ IN CONST CM_ARM_CMN_600_INFO * Cmn600Info,
+ IN CONST CHAR8 * Name,
+ IN CONST UINT64 Uid,
+ OUT EFI_ACPI_DESCRIPTION_HEADER ** Table
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS Status1;
+ UINT8 Index;
+ CONST CM_ARM_GENERIC_INTERRUPT * DtcInt;
+
+ EFI_ACPI_DESCRIPTION_HEADER * SsdtCmn600Template;
+ AML_ROOT_NODE_HANDLE RootNodeHandle;
+ AML_OBJECT_NODE_HANDLE NameOpIdNode;
+ AML_OBJECT_NODE_HANDLE NameOpCrsNode;
+ AML_DATA_NODE_HANDLE CmnPeriphBaseRdNode;
+ AML_DATA_NODE_HANDLE CmnRootNodeBaseRdNode;
+ AML_OBJECT_NODE_HANDLE DeviceNode;
+
+ // Parse the Ssdt CMN-600 Template.
+ SsdtCmn600Template = (EFI_ACPI_DESCRIPTION_HEADER*)
+ ssdtcmn600template_aml_code;
+
+ RootNodeHandle = NULL;
+ Status = AmlParseDefinitionBlock (
+ SsdtCmn600Template,
+ &RootNodeHandle
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to parse SSDT CMN-600 Template."
+ " Status = %r\n",
+ Status
+ ));
+ return Status;
+ }
+
+ // Get the _UID NameOp object defined by the "Name ()" statement,
+ // and update its value.
+ Status = AmlFindNode (
+ RootNodeHandle,
+ "\\_SB_.CMN0._UID",
+ &NameOpIdNode
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ Status = AmlNameOpUpdateInteger (NameOpIdNode, (UINT64)Uid);
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Get the _CRS object defined by the "Name ()" statement.
+ Status = AmlFindNode (
+ RootNodeHandle,
+ "\\_SB.CMN0._CRS",
+ &NameOpCrsNode
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Get the first Rd node in the "_CRS" object.
+ // This is the PERIPHBASE node.
+ Status = AmlNameOpCrsGetFirstRdNode (NameOpCrsNode, &CmnPeriphBaseRdNode);
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ if (CmnPeriphBaseRdNode == NULL) {
+ Status = EFI_INVALID_PARAMETER;
+ goto error_handler;
+ }
+
+ // Update the PERIPHBASE base address and length.
+ Status = AmlUpdateRdQWord (
+ CmnPeriphBaseRdNode,
+ Cmn600Info->PeriphBaseAddress,
+ Cmn600Info->PeriphBaseAddressLength
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Get the QWord node corresponding to the ROOTNODEBASE.
+ // It is the second Resource Data element in the BufferNode's
+ // variable list of arguments.
+ Status = AmlNameOpCrsGetNextRdNode (
+ CmnPeriphBaseRdNode,
+ &CmnRootNodeBaseRdNode
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ if (CmnRootNodeBaseRdNode == NULL) {
+ Status = EFI_INVALID_PARAMETER;
+ goto error_handler;
+ }
+
+ // Update the ROOTNODEBASE base address and length.
+ Status = AmlUpdateRdQWord (
+ CmnRootNodeBaseRdNode,
+ Cmn600Info->RootNodeBaseAddress,
+ ROOTNODEBASE_ADDRESS_LENGTH
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Add the Interrupt node(s).
+ // Generate Resource Data node(s) corresponding to the "Interrupt ()"
+ // ASL function and add it at the last position in the list of
+ // Resource Data nodes.
+ for (Index = 0; Index < Cmn600Info->DtcCount; Index++) {
+ DtcInt = &Cmn600Info->DtcInterrupt[Index];
+ Status = AmlCodeGenCrsAddRdInterrupt (
+ NameOpCrsNode,
+ ((DtcInt->Flags &
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK) != 0),
+ ((DtcInt->Flags &
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK) != 0),
+ ((DtcInt->Flags &
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK) != 0),
+ ((DtcInt->Flags &
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK) != 0),
+ (UINT32*)&DtcInt->Interrupt,
+ 1
+ );
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+ } // for
+
+ // Fixup the CMN600 device name.
+ // This MUST be done at the end, otherwise AML paths won't be valid anymore.
+ // Get the CMN0 variable defined by the "Device ()" statement.
+ Status = AmlFindNode (RootNodeHandle, "\\_SB_.CMN0", &DeviceNode);
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Update the CMN600 Device's name.
+ Status = AmlDeviceOpUpdateName (DeviceNode, (CHAR8*)Name);
+ if (EFI_ERROR (Status)) {
+ goto error_handler;
+ }
+
+ // Serialise the definition block
+ Status = AmlSerializeDefinitionBlock (
+ RootNodeHandle,
+ Table
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to Serialize SSDT Table Data."
+ " Status = %r\n",
+ Status
+ ));
+ }
+
+error_handler:
+ // Cleanup
+ if (RootNodeHandle != NULL) {
+ Status1 = AmlDeleteTree (RootNodeHandle);
+ if (EFI_ERROR (Status1)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to cleanup AML tree."
+ " Status = %r\n",
+ Status1
+ ));
+ // If Status was success but we failed to delete the AML Tree
+ // return Status1 else return the original error code, i.e. Status.
+ if (!EFI_ERROR (Status)) {
+ return Status1;
+ }
+ }
+ }
+
+ return Status;
+}
+
+/** Free any resources allocated for constructing the SSDT tables for CMN-600.
+
+ @param [in] This Pointer to the ACPI table generator.
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol Interface.
+ @param [in, out] Table Pointer to an array of pointers
+ to ACPI Table(s).
+ @param [in] TableCount Number of ACPI table(s).
+
+ @retval EFI_SUCCESS The resources were freed successfully.
+ @retval EFI_INVALID_PARAMETER The table pointer is NULL or invalid.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+FreeSsdtCmn600TableResourcesEx (
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *** CONST Table,
+ IN CONST UINTN TableCount
+ )
+{
+ EFI_ACPI_DESCRIPTION_HEADER ** TableList;
+ UINTN Index;
+
+ ASSERT (This != NULL);
+ ASSERT (AcpiTableInfo != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+ ASSERT (AcpiTableInfo->AcpiTableSignature == This->AcpiTableSignature);
+
+ if ((Table == NULL) ||
+ (*Table == NULL) ||
+ (TableCount == 0)) {
+ DEBUG ((DEBUG_ERROR, "ERROR: SSDT-CMN-600: Invalid Table Pointer\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ TableList = *Table;
+
+ for (Index = 0; Index < TableCount; Index++) {
+ if ((TableList[Index] != NULL) &&
+ (TableList[Index]->Signature ==
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE)) {
+ FreePool (TableList[Index]);
+ } else {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Could not free SSDT table at index %d."
+ " Status = %r\n",
+ Index,
+ EFI_INVALID_PARAMETER
+ ));
+ return EFI_INVALID_PARAMETER;
+ }
+ } //for
+
+ // Free the table list.
+ FreePool (*Table);
+ *Table = NULL;
+ return EFI_SUCCESS;
+}
+
+/** Construct SSDT tables for describing CMN-600 meshes.
+
+ This function invokes the Configuration Manager protocol interface
+ to get the required hardware information for generating the ACPI
+ table.
+
+ If this function allocates any resources then they must be freed
+ in the FreeXXXXTableResourcesEx function.
+
+ @param [in] This Pointer to the ACPI table generator.
+ @param [in] AcpiTableInfo Pointer to the ACPI table information.
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager
+ Protocol interface.
+ @param [out] Table Pointer to a list of generated ACPI table(s).
+ @param [out] TableCount Number of generated ACPI table(s).
+
+ @retval EFI_SUCCESS Table generated successfully.
+ @retval EFI_BAD_BUFFER_SIZE The size returned by the Configuration
+ Manager is less than the Object size for
+ the requested object.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND Could not find information.
+ @retval EFI_OUT_OF_RESOURCES Could not allocate memory.
+ @retval EFI_UNSUPPORTED Unsupported configuration.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+BuildSsdtCmn600TableEx (
+ IN CONST ACPI_TABLE_GENERATOR * This,
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,
+ OUT EFI_ACPI_DESCRIPTION_HEADER *** Table,
+ OUT UINTN * CONST TableCount
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Index;
+ CM_ARM_CMN_600_INFO * Cmn600Info;
+ UINT32 Cmn600Count;
+ CHAR8 NewName[5];
+ EFI_ACPI_DESCRIPTION_HEADER ** TableList;
+
+ ASSERT (This != NULL);
+ ASSERT (AcpiTableInfo != NULL);
+ ASSERT (CfgMgrProtocol != NULL);
+ ASSERT (Table != NULL);
+ ASSERT (TableCount != NULL);
+ ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+ ASSERT (AcpiTableInfo->AcpiTableSignature == This->AcpiTableSignature);
+
+ *Table = NULL;
+
+ // Get CMN-600 information.
+ Status = GetEArmObjCmn600Info (
+ CfgMgrProtocol,
+ CM_NULL_TOKEN,
+ &Cmn600Info,
+ &Cmn600Count
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to get the CMN-600 information."
+ " Status = %r\n",
+ Status
+ ));
+ return Status;
+ }
+
+ if ((Cmn600Count == 0) || (Cmn600Count > MAX_CMN600_DEVICES_SUPPORTED)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: CMN600 peripheral count = %d."
+ " This must be between 1 to 16.\n",
+ Cmn600Count
+ ));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Validate the CMN-600 Info.
+ Status = ValidateCmn600Info (Cmn600Info, Cmn600Count);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Invalid CMN600 information. Status = %r\n",
+ Status
+ ));
+ return Status;
+ }
+
+ // Allocate a table to store pointers to the SSDT tables.
+ TableList = (EFI_ACPI_DESCRIPTION_HEADER**)
+ AllocateZeroPool (
+ (sizeof (EFI_ACPI_DESCRIPTION_HEADER*) * Cmn600Count)
+ );
+ if (TableList == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to allocate memory for Table List."
+ " Status = %r\n",
+ Status
+ ));
+ return Status;
+ }
+
+ // Setup the table list early so that that appropriate cleanup
+ // can be done in case of failure.
+ *Table = TableList;
+
+ NewName[0] = 'C';
+ NewName[1] = 'M';
+ NewName[2] = 'N';
+ NewName[4] = '\0';
+ for (Index = 0; Index < Cmn600Count; Index++) {
+ NewName[3] = AsciiFromHex ((UINT8)(Index));
+
+ // Build a SSDT table describing the CMN600 device.
+ Status = FixupCmn600Info (
+ &Cmn600Info[Index],
+ NewName,
+ Index,
+ &TableList[Index]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: SSDT-CMN-600: Failed to build associated SSDT table."
+ " Status = %r\n",
+ Status
+ ));
+ break;
+ }
+
+ // Increment the table count here so that appropriate clean-up
+ // can be done in case of failure.
+ *TableCount += 1;
+ } // for
+
+ // Note: Table list and CMN600 device count has been setup. The
+ // framework will invoke FreeSsdtCmn600TableResourcesEx() even
+ // on failure, so appropriate clean-up will be done.
+ return Status;
+}
+
+/** This macro defines the Raw Generator revision.
+*/
+#define SSDT_CMN_600_GENERATOR_REVISION CREATE_REVISION (1, 0)
+
+/** The interface for the Raw Table Generator.
+*/
+STATIC
+CONST
+ACPI_TABLE_GENERATOR SsdtCmn600Generator = {
+ // Generator ID
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtCmn600),
+ // Generator Description
+ L"ACPI.STD.SSDT.CMN600.GENERATOR",
+ // ACPI Table Signature
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ // ACPI Table Revision - Unused
+ 0,
+ // Minimum ACPI Table Revision - Unused
+ 0,
+ // Creator ID
+ TABLE_GENERATOR_CREATOR_ID_ARM,
+ // Creator Revision
+ SSDT_CMN_600_GENERATOR_REVISION,
+ // Build table function. Use the extended version instead.
+ NULL,
+ // Free table function. Use the extended version instead.
+ NULL,
+ // Build Table function
+ BuildSsdtCmn600TableEx,
+ // Free Resource function
+ FreeSsdtCmn600TableResourcesEx
+};
+
+/** Register the Generator with the ACPI Table Factory.
+
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS The Generator is registered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_ALREADY_STARTED The Generator for the Table ID
+ is already registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiSsdtCmn600LibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = RegisterAcpiTableGenerator (&SsdtCmn600Generator);
+ DEBUG ((
+ DEBUG_INFO,
+ "SSDT-CMN-600: Register Generator. Status = %r\n",
+ Status
+ ));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+/** Deregister the Generator from the ACPI Table Factory.
+
+ @param [in] ImageHandle The handle to the image.
+ @param [in] SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS The Generator is deregistered.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The Generator is not registered.
+**/
+EFI_STATUS
+EFIAPI
+AcpiSsdtCmn600LibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE * SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = DeregisterAcpiTableGenerator (&SsdtCmn600Generator);
+ DEBUG ((
+ DEBUG_INFO,
+ "SSDT-CMN-600: Deregister Generator. Status = %r\n",
+ Status
+ ));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab03b72236e78c28a5e36452bb5d7e93e957332d
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+ - Std or STD - Standard
+
+ @par Reference(s):
+ - Arm CoreLink CMN-600 Coherent Mesh Network Technical Reference Manual r3p0
+ - Generic ACPI for Arm Components 1.0 Platform Design Document
+**/
+
+#ifndef SSDT_CMN600_GENERATOR_H_
+#define SSDT_CMN600_GENERATOR_H_
+
+/** PeriphBase maximum address length is 256MB (0x10000000)
+ for a (X >= 4) || (Y >= 4) dimensions mesh.
+*/
+#define PERIPHBASE_MAX_ADDRESS_LENGTH SIZE_256MB
+
+/** PeriphBase minimum address length is 64MB (0x04000000)
+ for a (X < 4) && (Y < 4) dimensions mesh.
+*/
+#define PERIPHBASE_MIN_ADDRESS_LENGTH SIZE_64MB
+
+/** RootNodeBase address length is 16KB (0x00004000).
+*/
+#define ROOTNODEBASE_ADDRESS_LENGTH SIZE_16KB
+
+/** Maximum number of CMN-600 Debug and Trace Logic Controllers (DTC).
+*/
+#define MAX_DTC_COUNT 4
+
+/** Starting value for the UID to represent the CMN600 devices.
+*/
+#define CMN600_DEVICE_START_UID 0
+
+/** Maximum CMN-600 devices supported by this generator.
+ This generator supports a maximum of 16 CMN-600 devices.
+ Note: This is not a hard limitation and can be extended if needed.
+ Corresponding changes would be needed to support the Name and
+ UID fields describing the serial port.
+
+*/
+#define MAX_CMN600_DEVICES_SUPPORTED 16
+
+#endif // SSDT_CMN600_GENERATOR_H_
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
new file mode 100644
index 0000000000000000000000000000000000000000..821c0d531b983e19278062a11317bba83fdc141a
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
@@ -0,0 +1,34 @@
+## @file
+# Ssdt CMN-600 Table Generator
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = SsdtCmn600LibArm
+ FILE_GUID = CEDB450D-8F0E-4ACC-8FB7-F72EC7D216A4
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = NULL|DXE_DRIVER
+ CONSTRUCTOR = AcpiSsdtCmn600LibConstructor
+ DESTRUCTOR = AcpiSsdtCmn600LibDestructor
+
+[Sources]
+ SsdtCmn600Generator.c
+ SsdtCmn600Generator.h
+ SsdtCmn600Template.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+
+[LibraryClasses]
+ AmlLib
+ BaseLib
+
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl
new file mode 100644
index 0000000000000000000000000000000000000000..023a89e2ab3d753cb1cdb8c423766294b0ea3fab
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl
@@ -0,0 +1,81 @@
+/** @file
+ SSDT CMN-600 Template
+
+ Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - Arm CoreLink CMN-600 Coherent Mesh Network Technical Reference Manual r3p0
+ - Generic ACPI for Arm Components 1.0 Platform Design Document
+
+ @par Glossary:
+ - {template} - Data fixed up using AML Fixup APIs.
+ - {codegen} - Data generated using AML Codegen APIs.
+**/
+
+DefinitionBlock ("SsdtCmn600.aml", "SSDT", 2, "ARMLTD", "CMN-600", 1) {
+ Scope (_SB) {
+ // CMN-600 device object for a X * Y mesh, where (X >= 4) || (Y >= 4).
+ Device (CMN0) { // {template}
+ Name (_HID, "ARMHC600")
+ Name (_UID, 0x0) // {template}
+
+ Name (_CRS, ResourceTemplate () {
+ // Descriptor for 256 MB of the CFG region at offset PERIPHBASE.
+ QWordMemory (
+ ResourceConsumer, // bit 0 of general flags is 0.
+ PosDecode,
+ MinFixed, // Range is fixed.
+ MaxFixed, // Range is Fixed.
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xA0000000, // MinAddress // {template}
+ 0xAFFFFFFF, // MaxAddress // {template}
+ 0x00000000, // Translation
+ 0x10000000, // RangeLength // {template}
+ , // ResourceSourceIndex
+ , // ResourceSource
+ CFGR // DescriptorName
+ ) // QWordMemory
+
+ // Descriptor for the root node. This is a 16 KB region at offset
+ // ROOTNODEBASE. In this example, ROOTNODEBASE starts at the 16 KB
+ // aligned offset of PERIPHBASE.
+ QWordMemory (
+ ResourceConsumer, // bit 0 of general flags is 0.
+ PosDecode,
+ MinFixed, // Range is fixed.
+ MaxFixed, // Range is Fixed.
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xA0000000, // MinAddress // {template}
+ 0xAFFFFFFF, // MaxAddress // {template}
+ 0x00000000, // Translation
+ 0x10000000, // RangeLength // {template}
+ , // ResourceSourceIndex
+ , // ResourceSource
+ ROOT // DescriptorName
+ ) // QWordMemory
+
+ // The Interrupt information is generated using AmlCodegen.
+ // Interrupt on PMU0 overflow, attached to DTC [0], with GSIV = <gsiv0>.
+ //
+ // Interrupt ( // {codegen}
+ // ResourceConsumer, // ResourceUsage
+ // Level, // EdgeLevel
+ // ActiveHigh, // ActiveLevel
+ // Exclusive, // Shared
+ // , // ResourceSourceIndex
+ // , // ResourceSource
+ // // DescriptorName
+ // ) {
+ // 0xA5 // <gsiv0 >
+ // } // Interrupt
+
+ }) // Name
+ } // Device
+ } // _SB
+} // DefinitionBlock
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 0/2] Support for dynamic CMN-600 AML generation

Sami Mujawar
 

The 'Generic ACPI for Arm Components 1.0 Platform Design Document' provides
a standard description for an 'Arm CoreLink CMN-600 Coherent Mesh Network'.

This patch series adds:
- definition for extended interrupt flags.
- support for generating SSDT table(s) describing the CMN-600 mesh(es) using
Dynamic AML. This also demonstrates the use of AML Fixup and AML Codegen
techniques.
- addresses the review feedback for "[PATCH v1 1/2] MdePkg: Definitions for
Extended Interrupt Flags" and makes corresponding changes to the subsequent
patch.

The changes can be seen at:
https://github.com/samimujawar/edk2/tree/1411_cmn600_generator_v2

Pierre Gondois (1):
DynamicTablesPkg: Add SSDT CMN-600 Table generator

Sami Mujawar (1):
MdePkg: Definitions for Extended Interrupt Flags

DynamicTablesPkg/DynamicTables.dsc.inc | 2 +
DynamicTablesPkg/DynamicTablesPkg.ci.yaml | 4 +
DynamicTablesPkg/Include/AcpiTableGenerator.h | 5 +
DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 64 +-
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c | 708 ++++++++++++++++++++
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h | 51 ++
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf | 34 +
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl | 81 +++
MdePkg/Include/IndustryStandard/Acpi10.h | 11 +
9 files changed, 954 insertions(+), 6 deletions(-)
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.h
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600LibArm.inf
create mode 100644 DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Template.asl

--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


Re: [edk2-platforms 4/4] LS1046aFrwy: Enable USB support for LS1046AFRWY board.

Leif Lindholm
 

On Tue, Sep 15, 2020 at 21:59:03 +0530, Meenakshi Aggarwal wrote:
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 ++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 +++++++++++++
3 files changed, 18 insertions(+)
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf

diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 4e1d6a7ae7a2..7004533ed5f1 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -31,6 +31,9 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000

+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x2F00000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x100000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|3

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
old mode 100644
new mode 100755
index 3f29dadd5d1d..266fdbd2b4d3
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -43,4 +43,6 @@ [Components.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
}

+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
old mode 100644
new mode 100755
index 24af547729c7..34c4e5a02516
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -120,6 +120,19 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
1.9.1


Re: [edk2-platforms 3/4] Silicon/NXP: Implement USB Errata

Leif Lindholm
 

On Tue, Sep 15, 2020 at 21:59:02 +0530, Meenakshi Aggarwal wrote:
Implement USB errata A009008, A009798, A008997, A009007
Make USB,SEC and SATA snoopable
Somewhat nitpicking, but for both subject and message - can you say
"errata workarounds" rather than "errata"?

Ideally, I would like to see the addition of the SCFG as a separate
patch from the one that implements the workarounds.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++++
Silicon/NXP/LS1046A/Include/Soc.h | 2 +
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 +++++++++++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++
11 files changed, 493 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3a568c0437e7..90dce69fd472 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -30,6 +30,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320

[PcdsFixedAtBuild.common]
# Pcds for PCI Express
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index db110553605f..4e1d6a7ae7a2 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE

################################################################################
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..d64286b199c6 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -28,6 +28,8 @@ [LibraryClasses]

[Sources.common]
ChassisLib.c
+ Erratum.c

[FeaturePcd]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
index 01ed0f6592d2..e2336bb18f29 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -14,6 +14,7 @@ [Defines]
LIBRARY_CLASS = SocLib

[Packages]
+ ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1046A/LS1046A.dec
@@ -25,3 +26,4 @@ [LibraryClasses]

[Sources.common]
SocLib.c
+
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 7e8bf224884b..f8fa7ed67596 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -11,6 +11,7 @@
#include <Uefi.h>

#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000

#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
@@ -26,6 +27,10 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SACR_PAGESIZE_MASK 0x00010000

+#define USB_PHY1_BASE_ADDRESS 0x084F0000
+#define USB_PHY2_BASE_ADDRESS 0x08500000
+#define USB_PHY3_BASE_ADDRESS 0x08510000
+
/**
The Device Configuration Unit provides general purpose configuration and
status for the device. These registers only support 32-bit accesses.
@@ -45,4 +50,111 @@ typedef struct {
} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
#pragma pack()

+/* Supplemental Configuration Unit (SCFG) */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfgCr;
+#define SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
+ **/
+#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
+ **/
+#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define SCFG_USBPWRFAULT_SHARED 0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
+
#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
new file mode 100644
index 000000000000..0231ef0a283d
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
@@ -0,0 +1,23 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for Erratas
+*
+* Copyright 2020 NXP
+*
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef ERRATUM_H__
+#define ERRATUM_H__
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+
+#endif
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index 89992a4b6fd5..c99368b4733d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -13,6 +13,48 @@
#include <Chassis.h>

/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
Read Dcfg register

@param Address The MMIO register to read.
@@ -48,4 +90,24 @@ ChassisInit (
VOID
);

+VOID
+ErratumA009008 (
+ VOID
+ );
+
+VOID
+ErratumA009798 (
+ VOID
+ );
+
+VOID
+ErratumA008997 (
+ VOID
+ );
+
+VOID
+ErratumA009007 (
+ VOID
+ );
+
#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
index 84f433d5cb94..e1d97e531263 100644
--- a/Silicon/NXP/LS1046A/Include/Soc.h
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -25,6 +25,7 @@
#define LS1046A_QSPI0_SIZE (SIZE_512MB)

#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS

/**
Reset Control Word (RCW) Bits
@@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6

typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;

#endif // SOC_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index 91b19f832f00..e6410a53f480 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -15,6 +15,69 @@
#include <Library/SerialPortLib.h>

/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Or32 (Address, Value);
+}
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Read32 (Address);
+}
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Write32 (Address, Value);
+}
+
+/**
Read Dcfg register

@param Address The MMIO register to read.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
new file mode 100644
index 000000000000..1806975ec8f5
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
@@ -0,0 +1,159 @@
+/** @file
+ This file containa all erratas need to be applied on different SoCs.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "Erratum.h"
+
+/*
+* A-009008: USB High Speed (HS) eye height adjustment
+* Affects: USB
+* Description: USB HS eye diagram fails with the default value at many corners, particularly at a high
+* temperature (105°C).
Please rewrap above two lines below 80 columns.
Apply to comment blocks below also.

/
Leif

+* Impact: USB HS eye diagram may fail using the default value.
+*/
+VOID
+ErratumA009008 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+
+ return;
+}
+
+/*
+* A-009798: USB high speed squelch threshold adjustment
+* Affects: USB
+* Description: The default setting for USB high speed squelch threshold results in a threshold close to or
+* lower than 100mV. This leads to a receiver compliance test failure for a 100mV threshold.
+* Impact: If the errata is not applied, only the USB high speed receiver sensitivity compliance test fails,
+* however USB data continues to transfer.
+*/
+VOID
+ErratumA009798 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
+
+ return;
+}
+
+/*
+* A-008997: USB3 LFPS peak-to-peak differential output voltage adjustment settings
+* Affects: USB
+* Description: Low Frequency Periodic Signaling (LFPS) peak-to-peak differential output voltage test
+* compliance fails using default transmitter settings. Software is required to change the
+* transmitter signal swings to pass compliance tests.
+* Impact: LFPS peak-to-peak differential output voltage compliance test fails.
+*/
+VOID
+ErratumA008997 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+
+ return;
+}
+
+/*
+* A-009007: USB3PHY observing intermittent failure in receive compliance tests
+* at higher jitter frequency using default register values
+*
+* Affects: USB
+*
+* Description: Receive compliance tests may fail intermittently at high jitter
+* frequencies using default register values.
+*
+* Impact: Receive compliance test fails at default register setting.
+*/
+
+VOID
+ConfigUsbLane0 (
+ IN UINTN UsbPhy
+ )
+{
+ UINTN RegAddress;
+
+ RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
+
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
+
+ return;
+}
+
+VOID
+ErratumA009007 (
+ VOID
+ )
+{
+ UINTN UsbPhy;
+
+ UsbPhy = USB_PHY1_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY2_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY3_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ return;
+}
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 3b15aee6ecae..80342d7230e4 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -11,6 +11,8 @@
#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
#include <Library/SocLib.h>
+
+#include <Library/SocLib.h>
#include <Soc.h>

/**
@@ -65,6 +67,47 @@ SocGetClock (
}

/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+STATIC
+VOID
+ConfigScfgMux (VOID)
+{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+
+ ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+STATIC
+VOID
+ApplyErrata (
+ VOID
+ )
+{
+ ErratumA009008 ();
+ ErratumA009798 ();
+ ErratumA008997 ();
+ ErratumA009007 ();
+}
+
+
+
+/**
Function to initialize SoC specific constructs
**/
VOID
@@ -72,7 +115,30 @@ SocInit (
VOID
)
{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+
+ /* Make SEC, SATA and USB reads and writes snoopable */
+ ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+ SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
+
+ ApplyErrata ();
ChassisInit ();

+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
--
1.9.1


Re: [edk2-platforms 2/4] Platform/NXP/LS1046aFrwyPkg: GPIO mux changes for USB

Leif Lindholm
 

Same comment as for previous patch:

Commit messages are not optional.

On Tue, Sep 15, 2020 at 21:59:01 +0530, Meenakshi Aggarwal wrote:
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
And only the poster can sign off.

Please address for all patches in series.

---
Silicon/NXP/NxpQoriqLs.dec | 8 ++++++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 5 +++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 2 ++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
.../Library/ArmPlatformLib/ArmPlatformLib.c | 17 +++++++++++++++++
5 files changed, 33 insertions(+)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 0c3608696569..3a568c0437e7 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -29,6 +29,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319

[PcdsFixedAtBuild.common]
# Pcds for PCI Express
@@ -48,6 +49,13 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351
gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352

+ #
+ # Pcds for Gpio
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0|UINT32|0x00000355
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0|UINT64|0x00000356
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0|UINT64|0x00000357
+
[PcdsDynamic.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index dbe7f408fce9..db110553605f 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -27,9 +27,14 @@ [PcdsDynamicDefault.common]

[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0x04
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
+

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE

################################################################################
#
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index fc600de01d74..21c87df73220 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -103,6 +103,8 @@ [LibraryClasses.common]
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf

+ GpioLib|Silicon/NXP/Library/GpioLib/GpioLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7802696bf39b..2e755842a714 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -25,6 +25,7 @@ [Packages]
[LibraryClasses]
ArmLib
DebugLib
+ GpioLib
SocLib

[Sources.common]
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index e1f20da09337..d467992a3e47 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,11 +8,14 @@

#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/GpioLib.h>
#include <Library/SocLib.h>

#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>

+#define USB2_MUX_SEL_GPIO 23
+
ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
@@ -89,6 +92,19 @@ NxpPlatformGetClock(
}

/**
+ FRWY-LS1046A GPIO 23 use for USB2
+ mux seclection
+**/
+STATIC VOID MuxSelectUsb2 (VOID)
+{
+
+ SetDir (GPIO3, USB2_MUX_SEL_GPIO, OUTPUT);
+ SetData (GPIO3, USB2_MUX_SEL_GPIO, HIGH);
Oh, I didn't spot in previous patch that these functions were exported
(my bad). They need more global names then - at least
GpioSetDirection/GpioSetData.

/
Leif

+
+ return;
+}
+
+/**
Initialize controllers that must setup in the normal world

This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
@@ -101,6 +117,7 @@ ArmPlatformInitialize (
)
{
SocInit ();
+ MuxSelectUsb2 ();

return EFI_SUCCESS;
}
--
1.9.1


*yet more* development process failure

Laszlo Ersek
 

Hi,

so check out this pull request:

https://github.com/tianocore/edk2/pull/960

- empty PR description
- useless PR title ("pr925")
- merges patches for *five* different BZs
(2882, 2965, 2880, 2978, 2881) in one go
- all of those BZs are still in CONFIRMED state
- none of those BZs reference the corresponding patches
in the mailing list archive.

So, all of this, *right after* the last two discussions on edk2-devel:

* development process failure
https://edk2.groups.io/g/devel/message/65313

* more development process failure
https://edk2.groups.io/g/devel/message/65315

Why is it that people that utterly disregard the process are allowed to
modify the master branch?

And don't give me the "lacking documentation" excuse. I'm not buying
that. The on-list discussions linked above are NINE DAYS old.

Instead, some maintainers just don't give a shit about the community,
and/or the exchanges on the list, they just do whatever they damn pleae.

Laszlo


Re: [edk2-platforms 1/4] Silicon/NXP: Add GPIO driver support.

Leif Lindholm
 

Needs an actual commit message.
What GPIO controller? If it does not have an explicit name, what
family of devices is it in?

On Tue, Sep 15, 2020 at 21:59:00 +0530, Meenakshi Aggarwal wrote:
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Only the poster can sign off that the post is being submitted in
accordance with the Developer's Certificate of Origin:
https://developercertificate.org/

If the author is different from the poster, that should be described
in the patch metadata (i.e. Author: ).

I have permitted (although I'm not a fan) Co-authored-by: tags, if
that is what this is intended to describe.

---
Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 +++++
Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++++++
Silicon/NXP/Library/GpioLib/GpioLib.c | 242 ++++++++++++++++++++++++++++++++
3 files changed, 391 insertions(+)
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c

diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/GpioLib/GpioLib.inf
new file mode 100644
index 000000000000..7878d1d03db2
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = GpioLib
+ FILE_GUID = addec2b8-d2e0-43c0-a277-41a8d42f3f4f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioLib
+
+[Sources.common]
+ GpioLib.c
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ BaseLib
Flip order of above two lines.

+ IoAccessLib
+ IoLib
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian
diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Library/GpioLib.h
new file mode 100644
index 000000000000..5821806226ee
--- /dev/null
+++ b/Silicon/NXP/Include/Library/GpioLib.h
@@ -0,0 +1,110 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef GPIO_H__
+#define GPIO_H__
+
+#include <Uefi.h>
+
+/* enum for GPIO number */
+typedef enum _GPIO_BLOCK {
+ GPIO1,
+ GPIO2,
+ GPIO3,
+ GPIO4,
+ GPIO_MAX
+} GPIO_BLOCK;
+
+/* enum for GPIO direction */
+typedef enum _GPIO_DIRECTION {
+ INPUT,
+ OUTPUT
+} GPIO_DIRECTION;
+
+/* enum for GPIO state */
+typedef enum _GPIO_STATE {
+ LOW,
+ HIGH
+} GPIO_VAL;
+
+/**
+ SetDir Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ );
+
+/**
+ GetDir Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+ /**
+ GetData Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+/**
+ SetData Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+SetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ );
+
+/**
+ SetOpenDrain Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ );
+
+#endif
diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/GpioLib/GpioLib.c
new file mode 100644
index 000000000000..33cc45c2152b
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.c
@@ -0,0 +1,242 @@
+/** @file
+
Which controller is this for. There should be a comment here
sufficient for me to figure out where I should start looking for
documentation.

+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+STATIC MMIO_OPERATIONS *mGpioOps;
+
+/* Structure for GPIO Regsters */
+typedef struct GpioRegs {
+ UINT32 GpDir;
+ UINT32 GpOdr;
+ UINT32 GpData;
+ UINT32 GpIer;
+ UINT32 GpImr;
+ UINT32 GpIcr;
Are the above registers the official names as per the documentation?
If so, this is fine even though it violates the CamelCase naming
style, but please add a glossary entry to the top-of-file comment
block.

+} GPIO_REGS;
+
+/**
+ GetBaseAddr GPIO controller Base Address
+
+ @param[in] Id GPIO controller number
+
+ @retval GPIO controller Base Address, if found
+ @retval NULL, if not a valid controller number
+
+ **/
+STATIC
+VOID *
+GetBaseAddr (
+ IN UINT8 Id
+ )
+{
+
+ UINTN GpioBaseAddr;
+ UINTN MaxGpioController;
+
+ mGpioOps = GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndian));
+
+ MaxGpioController = PcdGet32 (PcdNumGpioController);
+
+ if (Id < MaxGpioController) {
+ GpioBaseAddr = PcdGet64 (PcdGpioModuleBaseAddress) +
+ (Id * PcdGet64 (PcdGpioControllerOffset));
+ return (VOID *) GpioBaseAddr;
No space after ).

+ }
+ else {
Move to line above.

+ DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d-%d",
+ Id, GPIO1, MaxGpioController));
+ return NULL;
+ }
+}
+
+/**
+ GetBitMask: Return Bit Mask
+
+ @param[in] Bit Bit to create bitmask
+ @retval Bitmask
+
+ **/
+
+STATIC
+UINT32
+GetBitMask (
+ IN UINT32 Bit
+ )
+{
+
+ if (!FeaturePcdGet (PcdGpioControllerBigEndian)) {
+ return (1 << Bit);
+ } else {
+ return (1 << (31 - Bit));
+ }
The above confuses me greatly - endianness affects byte order, not
bit order. Is this some compensation for PowerPC numbering bits
backwards, and these reused blocks being affected by this when in
big-endian mode?

Needs a very descriptive comment. The current function comment block
contains no information, it just keeps repeating the function name in
different word order.

+}
+
+
+/**
+ SetDir Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetDir (
SetDirection

+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
The variable should be called something descriptive. You are using it
to read a specific value out of a specific register. In this instance,
DirectionMask would be a better alternative.

Please address accordingly in functions below, with appropriate
descriptive names for each location.

+ UINT32 Value;
+
+ Regs = GetBaseAddr(Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
+
+ if (Dir) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value | BitMask));
+ }
+ else {
+ mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GetDir Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GetDir (
GetDirection

+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 BitMask;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
+
+ return (Value & BitMask);
+}
+
+/**
+ GetData Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 BitMask;
+
+ Regs = (VOID *)GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+
Spurious extra blank line.

+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
+
+ if (Value & BitMask) {
+ return 1;
+ } else {
+ return 0;
+ }
return (Value & BitMask) == BitMask; ?

+}
+
+/**
+ SetData Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+SetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
+ UINT32 Value;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
+
+ if (Data) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value | BitMask));
+ } else {
+ mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ SetOpenDrain Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
+ UINT32 Value;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
Missing space before (.

+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpOdr);
+ if (OpenDrain) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value | BitMask));
+ }
+ else {
Move to line above.

/
Leif

+ mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
--
1.9.1


[PATCH v1 1/1] UefiCpuPkg: Remove PEI/DXE instances of CpuTimerLib.

Jason Lou
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2832

1. Remove PEI instance(PeiCpuTimerLib).
PeiCpuTimerLib is currently designed to save time by getting CPU TSC frequn=
cy from Hob.
BaseCpuTimerLib is designed to calculate TSC frequency by using CPUID[15h] =
each time.
The time it takes to find CpuCrystalFrequencyHob (about 2000ns) is much lon=
ger than it takes to
calculate TSC frequency with CPUID[15h] (about 450ns), which means using Ba=
seCpuTimerLib to
trigger a delay is more accurate than using PeiCpuTimerLib, recommend to us=
e BaseCpuTimerLib
instead of PeiCpuTimerLib.

2. Remove DXE instance(DxeCpuTimerLib).
DxeCpuTimerLib is designed to calculate TSC frequency with CPUID[15h] in it=
s constructor function,
then save it in a global variable. For this design, once the driver contain=
ing this instance is
running, the constructor function is called, it will take extra time to cal=
culate TSC frequency.
The time it takes to get TSC frequncy from global variable is shorter than =
it takes to calculate
TSC frequency with CPUID[15h], but 450ns is a short time, the impact on the=
platform is very limited.
In addition, in order to simplify the code, recommend to use BaseCpuTimerLi=
b instead of DxeCpuTimerLib.

I did some experiments on one Intel server platform and collected the follo=
wing data:
1. Average time taken to find CpuCrystalFrequencyHob: about 2000 ns.
2. Average time taken to calculate TSC frequency: about 450 ns.

Reference code:
//
// Calculate average time taken to find Hob.
//
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - =
GetFirstGuidHob (1000 cycles)\n"));
Ticks1 =3D AsmReadTsc();
for (i =3D 0; i < 1000; i++) {
GuidHob =3D GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);
}
Ticks2 =3D AsmReadTsc();

if (GuidHob =3D=3D NULL) {
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - CpuCrystalFrequencyHob can n=
ot be found!\n"));
} else {
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - Average time taken to find H=
ob =3D %d ns\n", \
DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 100000=
0000), *CpuCrystalCounterFrequency, NULL), 1000)));
}

//
// Calculate average time taken to calculate CPU frequency.
//
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] GetPerformanceCounterFrequency - =
CpuidCoreClockCalculateTscFrequency (1000 cycles)\n"));
Ticks1 =3D AsmReadTsc();
for (i =3D 0; i < 1000; i++) {
Freq =3D CpuidCoreClockCalculateTscFrequency ();
}
Ticks2 =3D AsmReadTsc();
DEBUG((DEBUG_ERROR, "[PeiCpuTimerLib] - Average time taken to calculat=
e TSC frequency =3D %d ns\n", \
DivU64x32(DivU64x64Remainder(MultU64x32((Ticks2 - Ticks1), 10000000=
00), *CpuCrystalCounterFrequency, NULL), 1000)));

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c | 85 --------------------
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c | 58 -------------
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf | 37 ---------
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni | 17 ----
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf | 36 ---------
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni | 17 ----
UefiCpuPkg/UefiCpuPkg.dsc | 4 +-
7 files changed, 1 insertion(+), 253 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c b/UefiCpuPkg/L=
ibrary/CpuTimerLib/DxeCpuTimerLib.c
deleted file mode 100644
index 269e5a3e83d7..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/** @file=0D
- CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer Libra=
ry.=0D
-=0D
- Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>=0D
- SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-=0D
-**/=0D
-=0D
-#include <PiDxe.h>=0D
-#include <Library/TimerLib.h>=0D
-#include <Library/BaseLib.h>=0D
-#include <Library/HobLib.h>=0D
-=0D
-extern GUID mCpuCrystalFrequencyHobGuid;=0D
-=0D
-/**=0D
- CPUID Leaf 0x15 for Core Crystal Clock Frequency.=0D
-=0D
- The TSC counting frequency is determined by using CPUID leaf 0x15. Frequ=
ency in MHz =3D Core XTAL frequency * EBX/EAX.=0D
- In newer flavors of the CPU, core xtal frequency is returned in ECX or 0=
if not supported.=0D
- @return The number of TSC counts per second.=0D
-=0D
-**/=0D
-UINT64=0D
-CpuidCoreClockCalculateTscFrequency (=0D
- VOID=0D
- );=0D
-=0D
-//=0D
-// Cached CPU Crystal counter frequency=0D
-//=0D
-UINT64 mCpuCrystalCounterFrequency =3D 0;=0D
-=0D
-=0D
-/**=0D
- Internal function to retrieves the 64-bit frequency in Hz.=0D
-=0D
- Internal function to retrieves the 64-bit frequency in Hz.=0D
-=0D
- @return The frequency in Hz.=0D
-=0D
-**/=0D
-UINT64=0D
-InternalGetPerformanceCounterFrequency (=0D
- VOID=0D
- )=0D
-{=0D
- return mCpuCrystalCounterFrequency;=0D
-}=0D
-=0D
-/**=0D
- The constructor function is to initialize CpuCrystalCounterFrequency.=0D
-=0D
- @param ImageHandle The firmware allocated handle for the EFI image.=0D
- @param SystemTable A pointer to the EFI System Table.=0D
-=0D
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.=0D
-=0D
-**/=0D
-EFI_STATUS=0D
-EFIAPI=0D
-DxeCpuTimerLibConstructor (=0D
- IN EFI_HANDLE ImageHandle,=0D
- IN EFI_SYSTEM_TABLE *SystemTable=0D
- )=0D
-{=0D
- EFI_HOB_GUID_TYPE *GuidHob;=0D
-=0D
- //=0D
- // Initialize CpuCrystalCounterFrequency=0D
- //=0D
- GuidHob =3D GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);=0D
- if (GuidHob !=3D NULL) {=0D
- mCpuCrystalCounterFrequency =3D *(UINT64*)GET_GUID_HOB_DATA (GuidHob);=
=0D
- } else {=0D
- mCpuCrystalCounterFrequency =3D CpuidCoreClockCalculateTscFrequency ()=
;=0D
- }=0D
-=0D
- if (mCpuCrystalCounterFrequency =3D=3D 0) {=0D
- return EFI_UNSUPPORTED;=0D
- }=0D
-=0D
- return EFI_SUCCESS;=0D
-}=0D
-=0D
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c b/UefiCpuPkg/L=
ibrary/CpuTimerLib/PeiCpuTimerLib.c
deleted file mode 100644
index 91a721205653..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/** @file=0D
- CPUID Leaf 0x15 for Core Crystal Clock frequency instance as PEI Timer L=
ibrary.=0D
-=0D
- Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>=0D
- SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-=0D
-**/=0D
-=0D
-#include <PiPei.h>=0D
-#include <Library/TimerLib.h>=0D
-#include <Library/BaseLib.h>=0D
-#include <Library/HobLib.h>=0D
-#include <Library/DebugLib.h>=0D
-=0D
-extern GUID mCpuCrystalFrequencyHobGuid;=0D
-=0D
-/**=0D
- CPUID Leaf 0x15 for Core Crystal Clock Frequency.=0D
-=0D
- The TSC counting frequency is determined by using CPUID leaf 0x15. Frequ=
ency in MHz =3D Core XTAL frequency * EBX/EAX.=0D
- In newer flavors of the CPU, core xtal frequency is returned in ECX or 0=
if not supported.=0D
- @return The number of TSC counts per second.=0D
-=0D
-**/=0D
-UINT64=0D
-CpuidCoreClockCalculateTscFrequency (=0D
- VOID=0D
- );=0D
-=0D
-/**=0D
- Internal function to retrieves the 64-bit frequency in Hz.=0D
-=0D
- Internal function to retrieves the 64-bit frequency in Hz.=0D
-=0D
- @return The frequency in Hz.=0D
-=0D
-**/=0D
-UINT64=0D
-InternalGetPerformanceCounterFrequency (=0D
- VOID=0D
- )=0D
-{=0D
- UINT64 *CpuCrystalCounterFrequency;=0D
- EFI_HOB_GUID_TYPE *GuidHob;=0D
-=0D
- CpuCrystalCounterFrequency =3D NULL;=0D
- GuidHob =3D GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid);=0D
- if (GuidHob =3D=3D NULL) {=0D
- CpuCrystalCounterFrequency =3D (UINT64*)BuildGuidHob(&mCpuCrystalFreq=
uencyHobGuid, sizeof (*CpuCrystalCounterFrequency));=0D
- ASSERT (CpuCrystalCounterFrequency !=3D NULL);=0D
- *CpuCrystalCounterFrequency =3D CpuidCoreClockCalculateTscFrequency ()=
;=0D
- } else {=0D
- CpuCrystalCounterFrequency =3D (UINT64*)GET_GUID_HOB_DATA (GuidHob);=0D
- }=0D
-=0D
- return *CpuCrystalCounterFrequency;=0D
-}=0D
-=0D
diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf b/UefiCpuPkg=
/Library/CpuTimerLib/DxeCpuTimerLib.inf
deleted file mode 100644
index 6c83549c87da..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
+++ /dev/null
@@ -1,37 +0,0 @@
-## @file=0D
-# DXE CPU Timer Library=0D
-#=0D
-# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. The =
performance=0D
-# counter features are provided by the processors time stamp counter.=0D
-#=0D
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
-# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-#=0D
-##=0D
-=0D
-[Defines]=0D
- INF_VERSION =3D 0x00010005=0D
- BASE_NAME =3D DxeCpuTimerLib=0D
- FILE_GUID =3D F22CC0DA-E7DB-4E4D-ABE2-A608188233A2=
=0D
- MODULE_TYPE =3D DXE_DRIVER=0D
- VERSION_STRING =3D 1.0=0D
- LIBRARY_CLASS =3D TimerLib|DXE_CORE DXE_DRIVER DXE_RUNT=
IME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE=0D
- CONSTRUCTOR =3D DxeCpuTimerLibConstructor=0D
- MODULE_UNI_FILE =3D DxeCpuTimerLib.uni=0D
-=0D
-[Sources]=0D
- CpuTimerLib.c=0D
- DxeCpuTimerLib.c=0D
-=0D
-[Packages]=0D
- MdePkg/MdePkg.dec=0D
- UefiCpuPkg/UefiCpuPkg.dec=0D
-=0D
-[LibraryClasses]=0D
- BaseLib=0D
- PcdLib=0D
- DebugLib=0D
- HobLib=0D
-=0D
-[Pcd]=0D
- gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES=0D
diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni b/UefiCpuPkg=
/Library/CpuTimerLib/DxeCpuTimerLib.uni
deleted file mode 100644
index f55b92abace7..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
+++ /dev/null
@@ -1,17 +0,0 @@
-// /** @file=0D
-// DXE CPU Timer Library=0D
-//=0D
-// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. The=
performance=0D
-// counter features are provided by the processors time stamp counter.=0D
-//=0D
-// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
-//=0D
-// SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-//=0D
-// **/=0D
-=0D
-=0D
-#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library=
"=0D
-=0D
-#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti=
mer support using CPUID Leaf 0x15 XTAL frequency."=0D
-=0D
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf b/UefiCpuPkg=
/Library/CpuTimerLib/PeiCpuTimerLib.inf
deleted file mode 100644
index 7af0fc44a65d..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
+++ /dev/null
@@ -1,36 +0,0 @@
-## @file=0D
-# PEI CPU Timer Library=0D
-#=0D
-# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. The =
performance=0D
-# counter features are provided by the processors time stamp counter.=0D
-#=0D
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
-# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-#=0D
-##=0D
-=0D
-[Defines]=0D
- INF_VERSION =3D 0x00010005=0D
- BASE_NAME =3D PeiCpuTimerLib=0D
- FILE_GUID =3D 2B13DE00-1A5F-4DD7-A298-01B08AF1015A=
=0D
- MODULE_TYPE =3D BASE=0D
- VERSION_STRING =3D 1.0=0D
- LIBRARY_CLASS =3D TimerLib|PEI_CORE PEIM=0D
- MODULE_UNI_FILE =3D PeiCpuTimerLib.uni=0D
-=0D
-[Sources]=0D
- CpuTimerLib.c=0D
- PeiCpuTimerLib.c=0D
-=0D
-[Packages]=0D
- MdePkg/MdePkg.dec=0D
- UefiCpuPkg/UefiCpuPkg.dec=0D
-=0D
-[LibraryClasses]=0D
- BaseLib=0D
- PcdLib=0D
- DebugLib=0D
- HobLib=0D
-=0D
-[Pcd]=0D
- gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES=0D
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni b/UefiCpuPkg=
/Library/CpuTimerLib/PeiCpuTimerLib.uni
deleted file mode 100644
index 49beb44908d6..000000000000
--- a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
+++ /dev/null
@@ -1,17 +0,0 @@
-// /** @file=0D
-// PEI CPU Timer Library=0D
-//=0D
-// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. The=
performance=0D
-// counter features are provided by the processors time stamp counter.=0D
-//=0D
-// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
-//=0D
-// SPDX-License-Identifier: BSD-2-Clause-Patent=0D
-//=0D
-// **/=0D
-=0D
-=0D
-#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library=
"=0D
-=0D
-#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti=
mer support using CPUID Leaf 0x15 XTAL frequency."=0D
-=0D
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index b2b6d78a71b0..e915b5c81b66 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -1,7 +1,7 @@
## @file=0D
# UefiCpuPkg Package=0D
#=0D
-# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>=
=0D
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -107,8 +107,6 @@ [Components]
UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf=
=0D
UefiCpuPkg/Application/Cpuid/Cpuid.inf=0D
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf=0D
- UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf=0D
- UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf=0D
=0D
[Components.IA32, Components.X64]=0D
UefiCpuPkg/CpuDxe/CpuDxe.inf=0D
--=20
2.28.0.windows.1


Re: [PATCH] EmulatorPkg/Unix Prevents the compiler form optimizing unused variable

Ni, Ray
 

Jordan, Andrew,
I will defer to you to review the patch.

Thanks,
Ray

-----Original Message-----
From: LiuYu <liuyu@greatwall.com.cn>
Sent: Friday, September 25, 2020 1:49 PM
To: Justen, Jordan L <jordan.l.justen@intel.com>; afish@apple.com; Ni, Ray <ray.ni@intel.com>
Cc: devel@edk2.groups.io; LiuYu <liuyu@greatwall.com.cn>
Subject: [edk2-devel][PATCH] EmulatorPkg/Unix Prevents the compiler form optimizing unused variable

gInXcode is only used by GDB script and if optimization is turned on then compiler
treats this variable as unused so it can't been linked in the final object.

Signed-off-by: LiuYu <liuyu@greatwall.com.cn>
---
EmulatorPkg/Unix/Host/Host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/EmulatorPkg/Unix/Host/Host.c b/EmulatorPkg/Unix/Host/Host.c
index b4e5510613..b851264c8e 100644
--- a/EmulatorPkg/Unix/Host/Host.c
+++ b/EmulatorPkg/Unix/Host/Host.c
@@ -54,7 +54,7 @@ IMAGE_CONTEXT_TO_MOD_HANDLE *mImageContextModHandleArray = NULL;
EFI_PEI_PPI_DESCRIPTOR *gPpiList;


-int gInXcode = 0;
+int gInXcode __attribute__((used)) = 0;


/*++
--
2.20.1


回复: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for hiding page-access caps from OSes hides SP and CRYPTO caps too

gaoliming
 

Malgorzata:
How do know OS (Windows or Linux) behavior for SP and CRYPTO attribute? Is
there the public document to describe this behavior?

Thanks
Liming
-----邮件原件-----
发件人: bounce+27952+65566+4905953+8761045@groups.io
<bounce+27952+65566+4905953+8761045@groups.io> 代表 Malgorzata
Kukiello
发送时间: 2020年9月24日 18:22
收件人: devel@edk2.groups.io
抄送: Malgorzata Kukiello <jacek.kukiello@intel.com>; Michael D Kinney
<michael.d.kinney@intel.com>; Jian J Wang <jian.j.wang@intel.com>; Hao A
Wu <hao.a.wu@intel.com>; Dandan Bi <dandan.bi@intel.com>; Liming Gao
<gaoliming@byosoft.com.cn>; Zhiguang Liu <zhiguang.liu@intel.com>;
Oleksiy Yakovlev <oleksiyy@ami.com>; Ard Biesheuvel
<ard.biesheuvel@arm.com>
主题: [edk2-devel] [PATCH v2 0/2] UEFI memmap workaround for hiding
page-access caps from OSes hides SP and CRYPTO caps too

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2982

The workaround in the UEFI memmap construction, near the end of the
function CoreGetMemoryMap() [MdeModulePkg/Core/Dxe/Mem/Page.c]
should
not clear the SP and CRYPTO bits, because OSes do (apparently) correctly
interpret SP and CRYPTO as capabilities, and not as currently set
attributes (upon which the OSes should set their page tables). For this
reason, the SP and CRYPTO bits should be separated from the bitmask that
we use for hiding the page-access attributes, in the workaround

Signed-off-by: Malgorzata Kukiello <jacek.kukiello@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Oleksiy Yakovlev <oleksiyy@ami.com>
Cc: Ard Biesheuvel (ARM address) <ard.biesheuvel@arm.com>

MdeModulePkg/Core/Dxe/Mem/Page.c | 12 ++++++------
MdePkg/Include/Uefi/UefiSpec.h | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
---------------------------------------------------------------------
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please contact the sender and delete all copies; any review or
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others is strictly prohibited.






Re: [edk2-test] Contributions.txt still mentions the TianoCore Contribution Agreement

Laszlo Ersek
 

On 09/24/20 23:42, Rebecca Cran wrote:
While working on the SctPkg, I noticed the Contributions.txt file in the
top of the repo still mentions the TianoCore Contribution Agreement.
Does it need updated?

(CC'ing the other stewards)

Most likely so.

It's probably best to "replay" (or "port") edk2 commit 3806e1fd1397 to
edk2-test.

The "TianoCore Contribution Agreement" should be mentioned indirectly,
if at all, namely via a reference to edk2's "License-History.txt".


Note that "BaseTools/Scripts/PatchCheck.py" in edk2 already rejects
commit messages that contain "Contributed-under" lines; see the
"check_contributed_under" method.

Thanks
Laszlo


Re: [PATCH v2 1/2] CryptoPkg/OpensslLib: Add native instruction support for X64

Zurcher, Christopher J
 

I found how to undefine WIN32 and now CLANGPDB is building just fine. But it is very strange that it is only setting WIN32 by default on the assembly build, and I can only guess it's somehow triggered by adding the additional OPENSSL_FLAGS_CONFIG defines.

Thanks,
Christopher Zurcher

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Zurcher,
Christopher J
Sent: Thursday, September 24, 2020 19:29
To: devel@edk2.groups.io; Zurcher, Christopher J
<christopher.j.zurcher@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
gaoliming@byosoft.com.cn; Jiang, Guomin <guomin.jiang@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX <xiaoyux.lu@intel.com>;
'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Subject: Re: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add native
instruction support for X64

My final hurdle for CLANG is that the compiler is defining the macro "WIN32"
which triggers OpenSSL to include some Windows API calls and breaks the
build. VS2015 is not defining this by default.
Is there any clang option to prevent this macro definition?

Thanks,
Christopher Zurcher

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Zurcher,
Christopher J
Sent: Thursday, September 24, 2020 18:15
To: Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io;
gaoliming@byosoft.com.cn; Jiang, Guomin <guomin.jiang@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Subject: Re: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add native
instruction support for X64

I have no objection to CHAR16; it looks like OpenSSL doesn't actually use
wchar_t anywhere.

--
Christopher Zurcher

-----Original Message-----
From: Yao, Jiewen <jiewen.yao@intel.com>
Sent: Thursday, September 24, 2020 18:11
To: Zurcher, Christopher J <christopher.j.zurcher@intel.com>;
devel@edk2.groups.io; gaoliming@byosoft.com.cn; Jiang, Guomin
<guomin.jiang@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add native
instruction support for X64

I think we configure wchar_t to be 16bits by using -fshort-wchar.

Should we use
typedef CHAR16 wchar_t;
instead of
typedef UINT32 wchar_t;

Thank you
Yao Jiewen

-----Original Message-----
From: Zurcher, Christopher J <christopher.j.zurcher@intel.com>
Sent: Friday, September 25, 2020 9:07 AM
To: devel@edk2.groups.io; gaoliming@byosoft.com.cn; Yao, Jiewen
<jiewen.yao@intel.com>; Jiang, Guomin <guomin.jiang@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add
native
instruction support for X64

I've discovered the failure was because CryptoPkg includes its own
stddef.h
which is a wrapper for CrtLibSupport.h
I have added the required definitions to this file and have resolved
the
error:
typedef INTN ptrdiff_t;
typedef UINT32 wchar_t;

Thanks,
Christopher Zurcher

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Thursday, September 24, 2020 17:49
To: devel@edk2.groups.io; Zurcher, Christopher J
<christopher.j.zurcher@intel.com>; Yao, Jiewen
<jiewen.yao@intel.com>;
Jiang,
Guomin <guomin.jiang@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
'Ard Biesheuvel' <ard.biesheuvel@linaro.org>
Subject: 回复: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add
native
instruction support for X64

Zurcher:
Can you specify the detail build step to reproduce the build error
with
CLANGPDB tool chain?

Thanks
Liming
-----邮件原件-----
发件人: bounce+27952+65588+4905953+8761045@groups.io
<bounce+27952+65588+4905953+8761045@groups.io> 代表 Zurcher,
Christopher J
发送时间: 2020年9月25日 8:28
收件人: Yao, Jiewen <jiewen.yao@intel.com>; Jiang, Guomin
<guomin.jiang@intel.com>; devel@edk2.groups.io
抄送: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>; Ard Biesheuvel <ard.biesheuvel@linaro.org>
主题: Re: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib: Add
native
instruction support for X64

I was able to successfully build and run the non-optimized code
with
LLVM,
but the optimized version returns this error during build:

C:\Program Files\LLVM\lib\clang\9.0.0\include\stdatomic.h:91:17:
error:
unknown type name 'wchar_t'
typedef _Atomic(wchar_t) atomic_wchar_t;

Is there a known build issue with CLANGPDB and the stdatomic.h
file?

Thanks,
Christopher Zurcher

-----Original Message-----
From: Yao, Jiewen <jiewen.yao@intel.com>
Sent: Tuesday, September 22, 2020 19:35
To: Zurcher, Christopher J <christopher.j.zurcher@intel.com>;
Jiang,
Guomin
<guomin.jiang@intel.com>; devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib:
Add
native
instruction support for X64

For GCC, please refer to
https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-
II-
with-
Native-GCC

For LLVM, please refer to
https://github.com/tianocore/tianocore.github.io/wiki/CLANG9-
Tools-
Chain

Thank you
Yao Jiewen

-----Original Message-----
From: Zurcher, Christopher J <christopher.j.zurcher@intel.com>
Sent: Tuesday, September 22, 2020 11:22 PM
To: Jiang, Guomin <guomin.jiang@intel.com>;
devel@edk2.groups.io;
Yao,
Jiewen <jiewen.yao@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2] CryptoPkg/OpensslLib:
Add
native
instruction support for X64

I have unit tested SHA1, SHA512, and AES as well.
I do not have the build environment available to test GCC and
LLVM.

--
Christopher Zurcher

-----Original Message-----
From: Jiang, Guomin <guomin.jiang@intel.com>
Sent: Wednesday, September 16, 2020 02:17
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>;
Zurcher,
Christopher J <christopher.j.zurcher@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2]
CryptoPkg/OpensslLib:
Add
native
instruction support for X64

Hi Zurcher,

[Jiewen] Since you also add other sha (sha1, sha512) and
aesni,
I
think
those
need unit test for them too.
Can you update the status about it?

[Jiewen] I think we need support build with GCC and LLVM,
and
with
X64.

It is better to support the GCC and LLVM.

Thanks
Guomin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf
Of
Yao,
Jiewen
Sent: Tuesday, August 25, 2020 7:36 AM
To: Zurcher, Christopher J
<christopher.j.zurcher@intel.com>;
devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>; Ard Biesheuvel
<ard.biesheuvel@linaro.org>
Subject: Re: [edk2-devel] [PATCH v2 1/2]
CryptoPkg/OpensslLib:
Add
native
instruction support for X64

Below:

-----Original Message-----
From: Zurcher, Christopher J
<christopher.j.zurcher@intel.com>
Sent: Tuesday, August 25, 2020 5:26 AM
To: devel@edk2.groups.io; Zurcher, Christopher J
<christopher.j.zurcher@intel.com>; Yao, Jiewen
<jiewen.yao@intel.com>
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: RE: [edk2-devel] [PATCH v2 1/2]
CryptoPkg/OpensslLib:
Add
native
instruction support for X64

1) I have confirmed that the ApiHooks.c file is still
required
even
without
the AVX
instructions included. The x86_64 assembly files in
OpenSSL
set
a
flag
called
$win64 and automatically include calls to the
RtlVirtualUnwind
function
if
NASM
is selected as the assembler scheme.

https://docs.microsoft.com/en-us/windows/win32/api/winnt/nf-winnt-
rtlvirtualunwind

I have submitted an issue against OpenSSL since I don't
think
using
the
NASM
assembler should force the inclusion of Windows-specific
API
hooks,
but
that
change cannot be made in OpenSSL 1.1.1 and we will have
to
wait
for
OpenSSL 3
or later to remove the stub function.

https://github.com/openssl/openssl/issues/12712
[Jiewen] Thanks.

2) So far I have only built with VS.
[Jiewen] I think we need support build with GCC and LLVM,
and
with
X64.


3) The X64 SHA256 implementation was successfully
exercised
across a
large
number of devices in a production environment as a
verification
step
in a
multi-
GB data transfer scenario.
[Jiewen] Since you also add other sha (sha1, sha512) and
aesni,
I
think
those
need unit test for them too.


Thanks,
Christopher Zurcher

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On
Behalf
Of
Zurcher,
Christopher J
Sent: Tuesday, August 18, 2020 15:50
To: Yao, Jiewen <jiewen.yao@intel.com>;
devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: Re: [edk2-devel] [PATCH v2 1/2]
CryptoPkg/OpensslLib:
Add
native
instruction support for X64

After further review, the ApiHooks.c file may no longer
be
needed
since
we
are no longer including the AVX instructions. I will
look
over
the
dependencies and send a new patch set if I can
eliminate
the
API
hooks
file.

Thanks,
Christopher Zurcher

-----Original Message-----
From: Yao, Jiewen <jiewen.yao@intel.com>
Sent: Thursday, August 13, 2020 08:04
To: Zurcher, Christopher J
<christopher.j.zurcher@intel.com>;
devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Lu, XiaoyuX
<xiaoyux.lu@intel.com>;
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: RE: [PATCH v2 1/2] CryptoPkg/OpensslLib: Add
native
instruction
support for X64

Hi Christopher
Thanks.

1) Would you please help me understand more on
"ApiHooks.c
contains
a
stub
function for a Windows API call" ?
Why we need this?
If it is compiler specific in openssl, should we
submit
patch to
openssl to
exclude this with OPENSSL_SYS_UEFI? That should be a
cleaner
solution
for
UEFI.

2) Would you please describe what compiler you have
tried?
VS?
GCC?
LLVM?

3) Would you please describe what unit test you have
done?

Thank you
Yao Jiewen


-----Original Message-----
From: Zurcher, Christopher J
<christopher.j.zurcher@intel.
com>
Sent: Tuesday, August 4, 2020 8:24 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Wang, Jian
J
<jian.j.wang@intel.com>;
Lu, XiaoyuX <xiaoyux.lu@intel.com>; Ard Biesheuvel
<ard.biesheuvel@linaro.org>
Subject: [PATCH v2 1/2] CryptoPkg/OpensslLib: Add
native
instruction
support
for X64

BZ:
https://bugzilla.tianocore.org/show_bug.cgi?id=2507

Adding OpensslLibX64.inf and modifying
process_files.pl
to
process
this
file and generate the necessary assembly files.
ApiHooks.c contains a stub function for a Windows
API
call.
uefi-asm.conf contains the limited assembly
configurations
for
OpenSSL.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Christopher J Zurcher
<christopher.j.zurcher@intel.com>
---
CryptoPkg/Library/OpensslLib/OpensslLib.inf
|
2 +-
CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
|
2 +-
CryptoPkg/Library/OpensslLib/OpensslLibX64.inf
|
656
++++++++++++++++++++
CryptoPkg/Library/Include/openssl/opensslconf.h
|
3 -
CryptoPkg/Library/OpensslLib/ApiHooks.c
|
18 +
CryptoPkg/Library/OpensslLib/OpensslLibConstructor.c
|
34 +
CryptoPkg/Library/OpensslLib/process_files.pl
|
223
+++++--
CryptoPkg/Library/OpensslLib/uefi-asm.conf
|
15 +
8 files changed, 903 insertions(+), 50 deletions(-
)

diff --git
a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index dbbe5386a1..bd62d86936 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -16,7 +16,7 @@
VERSION_STRING = 1.0

LIBRARY_CLASS = OpensslLib

DEFINE OPENSSL_PATH = openssl

- DEFINE OPENSSL_FLAGS = -DL_ENDIAN -
DOPENSSL_SMALL_FOOTPRINT
-D_CRT_SECURE_NO_DEPRECATE -
D_CRT_NONSTDC_NO_DEPRECATE

+ DEFINE OPENSSL_FLAGS = -DL_ENDIAN -
DOPENSSL_SMALL_FOOTPRINT
-D_CRT_SECURE_NO_DEPRECATE -
D_CRT_NONSTDC_NO_DEPRECATE -
DOPENSSL_NO_ASM



#

# VALID_ARCHITECTURES = IA32 X64 ARM
AARCH64

diff --git
a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
index 616ccd9f62..2b7324a990 100644
---
a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+++
b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
@@ -16,7 +16,7 @@
VERSION_STRING = 1.0

LIBRARY_CLASS = OpensslLib

DEFINE OPENSSL_PATH = openssl

- DEFINE OPENSSL_FLAGS = -DL_ENDIAN -
DOPENSSL_SMALL_FOOTPRINT
-D_CRT_SECURE_NO_DEPRECATE -
D_CRT_NONSTDC_NO_DEPRECATE

+ DEFINE OPENSSL_FLAGS = -DL_ENDIAN -
DOPENSSL_SMALL_FOOTPRINT
-D_CRT_SECURE_NO_DEPRECATE -
D_CRT_NONSTDC_NO_DEPRECATE -
DOPENSSL_NO_ASM



#

# VALID_ARCHITECTURES = IA32 X64 ARM
AARCH64

diff --git
a/CryptoPkg/Library/OpensslLib/OpensslLibX64.inf
b/CryptoPkg/Library/OpensslLib/OpensslLibX64.inf
new file mode 100644
index 0000000000..825eea0254
--- /dev/null
+++
b/CryptoPkg/Library/OpensslLib/OpensslLibX64.inf
@@ -0,0 +1,656 @@
+## @file

+# This module provides OpenSSL Library
implementation.

+#

+# Copyright (c) 2010 - 2020, Intel Corporation.
All
rights
reserved.<BR>

+# (C) Copyright 2020 Hewlett Packard Enterprise
Development
LP<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+ INF_VERSION = 0x00010005

+ BASE_NAME = OpensslLibX64

+ MODULE_UNI_FILE = OpensslLib.uni

+ FILE_GUID =
18125E50-0117-4DD0-BE54-
4784AD995FEF

+ MODULE_TYPE = BASE

+ VERSION_STRING = 1.0

+ LIBRARY_CLASS = OpensslLib

+ DEFINE OPENSSL_PATH = openssl

+ DEFINE OPENSSL_FLAGS = -DL_ENDIAN -
DOPENSSL_SMALL_FOOTPRINT
-D_CRT_SECURE_NO_DEPRECATE -
D_CRT_NONSTDC_NO_DEPRECATE

+ DEFINE OPENSSL_FLAGS_CONFIG =
-DOPENSSL_CPUID_OBJ -
DSHA1_ASM -
DSHA256_ASM -DSHA512_ASM -DAESNI_ASM -DVPAES_ASM -
DGHASH_ASM

+ CONSTRUCTOR =
OpensslLibConstructor

+

+#

+# VALID_ARCHITECTURES = X64

+#

+

+[Sources]

+ OpensslLibConstructor.c

+ $(OPENSSL_PATH)/e_os.h

+ $(OPENSSL_PATH)/ms/uplink.h

+# Autogenerated files list starts here

+ X64/crypto/aes/aesni-mb-x86_64.nasm

+ X64/crypto/aes/aesni-sha1-x86_64.nasm

+ X64/crypto/aes/aesni-sha256-x86_64.nasm

+ X64/crypto/aes/aesni-x86_64.nasm

+ X64/crypto/aes/vpaes-x86_64.nasm

+ X64/crypto/modes/ghash-x86_64.nasm

+ X64/crypto/sha/sha1-mb-x86_64.nasm

+ X64/crypto/sha/sha1-x86_64.nasm

+ X64/crypto/sha/sha256-mb-x86_64.nasm

+ X64/crypto/sha/sha256-x86_64.nasm

+ X64/crypto/sha/sha512-x86_64.nasm

+ X64/crypto/x86_64cpuid.nasm

+ $(OPENSSL_PATH)/crypto/aes/aes_cbc.c

+ $(OPENSSL_PATH)/crypto/aes/aes_cfb.c

+ $(OPENSSL_PATH)/crypto/aes/aes_core.c

+ $(OPENSSL_PATH)/crypto/aes/aes_ige.c

+ $(OPENSSL_PATH)/crypto/aes/aes_misc.c

+ $(OPENSSL_PATH)/crypto/aes/aes_ofb.c

+ $(OPENSSL_PATH)/crypto/aes/aes_wrap.c

+ $(OPENSSL_PATH)/crypto/aria/aria.c

+ $(OPENSSL_PATH)/crypto/asn1/a_bitstr.c

+ $(OPENSSL_PATH)/crypto/asn1/a_d2i_fp.c

+ $(OPENSSL_PATH)/crypto/asn1/a_digest.c

+ $(OPENSSL_PATH)/crypto/asn1/a_dup.c

+ $(OPENSSL_PATH)/crypto/asn1/a_gentm.c

+ $(OPENSSL_PATH)/crypto/asn1/a_i2d_fp.c

+ $(OPENSSL_PATH)/crypto/asn1/a_int.c

+ $(OPENSSL_PATH)/crypto/asn1/a_mbstr.c

+ $(OPENSSL_PATH)/crypto/asn1/a_object.c

+ $(OPENSSL_PATH)/crypto/asn1/a_octet.c

+ $(OPENSSL_PATH)/crypto/asn1/a_print.c

+ $(OPENSSL_PATH)/crypto/asn1/a_sign.c

+ $(OPENSSL_PATH)/crypto/asn1/a_strex.c

+ $(OPENSSL_PATH)/crypto/asn1/a_strnid.c

+ $(OPENSSL_PATH)/crypto/asn1/a_time.c

+ $(OPENSSL_PATH)/crypto/asn1/a_type.c

+ $(OPENSSL_PATH)/crypto/asn1/a_utctm.c

+ $(OPENSSL_PATH)/crypto/asn1/a_utf8.c

+ $(OPENSSL_PATH)/crypto/asn1/a_verify.c

+ $(OPENSSL_PATH)/crypto/asn1/ameth_lib.c

+ $(OPENSSL_PATH)/crypto/asn1/asn1_err.c

+ $(OPENSSL_PATH)/crypto/asn1/asn1_gen.c

+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.c

+ $(OPENSSL_PATH)/crypto/asn1/asn1_lib.c

+ $(OPENSSL_PATH)/crypto/asn1/asn1_par.c

+ $(OPENSSL_PATH)/crypto/asn1/asn_mime.c

+ $(OPENSSL_PATH)/crypto/asn1/asn_moid.c

+ $(OPENSSL_PATH)/crypto/asn1/asn_mstbl.c

+ $(OPENSSL_PATH)/crypto/asn1/asn_pack.c

+ $(OPENSSL_PATH)/crypto/asn1/bio_asn1.c

+ $(OPENSSL_PATH)/crypto/asn1/bio_ndef.c

+ $(OPENSSL_PATH)/crypto/asn1/d2i_pr.c

+ $(OPENSSL_PATH)/crypto/asn1/d2i_pu.c

+ $(OPENSSL_PATH)/crypto/asn1/evp_asn1.c

+ $(OPENSSL_PATH)/crypto/asn1/f_int.c

+ $(OPENSSL_PATH)/crypto/asn1/f_string.c

+ $(OPENSSL_PATH)/crypto/asn1/i2d_pr.c

+ $(OPENSSL_PATH)/crypto/asn1/i2d_pu.c

+ $(OPENSSL_PATH)/crypto/asn1/n_pkey.c

+ $(OPENSSL_PATH)/crypto/asn1/nsseq.c

+ $(OPENSSL_PATH)/crypto/asn1/p5_pbe.c

+ $(OPENSSL_PATH)/crypto/asn1/p5_pbev2.c

+ $(OPENSSL_PATH)/crypto/asn1/p5_scrypt.c

+ $(OPENSSL_PATH)/crypto/asn1/p8_pkey.c

+ $(OPENSSL_PATH)/crypto/asn1/t_bitst.c

+ $(OPENSSL_PATH)/crypto/asn1/t_pkey.c

+ $(OPENSSL_PATH)/crypto/asn1/t_spki.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_dec.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_enc.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_fre.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_new.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_prn.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_scn.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_typ.c

+ $(OPENSSL_PATH)/crypto/asn1/tasn_utl.c

+ $(OPENSSL_PATH)/crypto/asn1/x_algor.c

+ $(OPENSSL_PATH)/crypto/asn1/x_bignum.c

+ $(OPENSSL_PATH)/crypto/asn1/x_info.c

+ $(OPENSSL_PATH)/crypto/asn1/x_int64.c

+ $(OPENSSL_PATH)/crypto/asn1/x_long.c

+ $(OPENSSL_PATH)/crypto/asn1/x_pkey.c

+ $(OPENSSL_PATH)/crypto/asn1/x_sig.c

+ $(OPENSSL_PATH)/crypto/asn1/x_spki.c

+ $(OPENSSL_PATH)/crypto/asn1/x_val.c

+ $(OPENSSL_PATH)/crypto/async/arch/async_null.c

+ $(OPENSSL_PATH)/crypto/async/arch/async_posix.c

+ $(OPENSSL_PATH)/crypto/async/arch/async_win.c

+ $(OPENSSL_PATH)/crypto/async/async.c

+ $(OPENSSL_PATH)/crypto/async/async_err.c

+ $(OPENSSL_PATH)/crypto/async/async_wait.c

+ $(OPENSSL_PATH)/crypto/bio/b_addr.c

+ $(OPENSSL_PATH)/crypto/bio/b_dump.c

+ $(OPENSSL_PATH)/crypto/bio/b_sock.c

+ $(OPENSSL_PATH)/crypto/bio/b_sock2.c

+ $(OPENSSL_PATH)/crypto/bio/bf_buff.c

+ $(OPENSSL_PATH)/crypto/bio/bf_lbuf.c

+ $(OPENSSL_PATH)/crypto/bio/bf_nbio.c

+ $(OPENSSL_PATH)/crypto/bio/bf_null.c

+ $(OPENSSL_PATH)/crypto/bio/bio_cb.c

+ $(OPENSSL_PATH)/crypto/bio/bio_err.c

+ $(OPENSSL_PATH)/crypto/bio/bio_lib.c

+ $(OPENSSL_PATH)/crypto/bio/bio_meth.c

+ $(OPENSSL_PATH)/crypto/bio/bss_acpt.c

+ $(OPENSSL_PATH)/crypto/bio/bss_bio.c

+ $(OPENSSL_PATH)/crypto/bio/bss_conn.c

+ $(OPENSSL_PATH)/crypto/bio/bss_dgram.c

+ $(OPENSSL_PATH)/crypto/bio/bss_fd.c

+ $(OPENSSL_PATH)/crypto/bio/bss_file.c

+ $(OPENSSL_PATH)/crypto/bio/bss_log.c

+ $(OPENSSL_PATH)/crypto/bio/bss_mem.c

+ $(OPENSSL_PATH)/crypto/bio/bss_null.c

+ $(OPENSSL_PATH)/crypto/bio/bss_sock.c

+ $(OPENSSL_PATH)/crypto/bn/bn_add.c

+ $(OPENSSL_PATH)/crypto/bn/bn_asm.c

+ $(OPENSSL_PATH)/crypto/bn/bn_blind.c

+ $(OPENSSL_PATH)/crypto/bn/bn_const.c

+ $(OPENSSL_PATH)/crypto/bn/bn_ctx.c

+ $(OPENSSL_PATH)/crypto/bn/bn_depr.c

+ $(OPENSSL_PATH)/crypto/bn/bn_dh.c

+ $(OPENSSL_PATH)/crypto/bn/bn_div.c

+ $(OPENSSL_PATH)/crypto/bn/bn_err.c

+ $(OPENSSL_PATH)/crypto/bn/bn_exp.c

+ $(OPENSSL_PATH)/crypto/bn/bn_exp2.c

+ $(OPENSSL_PATH)/crypto/bn/bn_gcd.c

+ $(OPENSSL_PATH)/crypto/bn/bn_gf2m.c

+ $(OPENSSL_PATH)/crypto/bn/bn_intern.c

+ $(OPENSSL_PATH)/crypto/bn/bn_kron.c

+ $(OPENSSL_PATH)/crypto/bn/bn_lib.c

+ $(OPENSSL_PATH)/crypto/bn/bn_mod.c

+ $(OPENSSL_PATH)/crypto/bn/bn_mont.c

+ $(OPENSSL_PATH)/crypto/bn/bn_mpi.c

+ $(OPENSSL_PATH)/crypto/bn/bn_mul.c

+ $(OPENSSL_PATH)/crypto/bn/bn_nist.c

+ $(OPENSSL_PATH)/crypto/bn/bn_prime.c

+ $(OPENSSL_PATH)/crypto/bn/bn_print.c

+ $(OPENSSL_PATH)/crypto/bn/bn_rand.c

+ $(OPENSSL_PATH)/crypto/bn/bn_recp.c

+ $(OPENSSL_PATH)/crypto/bn/bn_shift.c

+ $(OPENSSL_PATH)/crypto/bn/bn_sqr.c

+ $(OPENSSL_PATH)/crypto/bn/bn_sqrt.c

+ $(OPENSSL_PATH)/crypto/bn/bn_srp.c

+ $(OPENSSL_PATH)/crypto/bn/bn_word.c

+ $(OPENSSL_PATH)/crypto/bn/bn_x931p.c

+ $(OPENSSL_PATH)/crypto/buffer/buf_err.c

+ $(OPENSSL_PATH)/crypto/buffer/buffer.c

+ $(OPENSSL_PATH)/crypto/cmac/cm_ameth.c

+ $(OPENSSL_PATH)/crypto/cmac/cm_pmeth.c

+ $(OPENSSL_PATH)/crypto/cmac/cmac.c

+ $(OPENSSL_PATH)/crypto/comp/c_zlib.c

+ $(OPENSSL_PATH)/crypto/comp/comp_err.c

+ $(OPENSSL_PATH)/crypto/comp/comp_lib.c

+ $(OPENSSL_PATH)/crypto/conf/conf_api.c

+ $(OPENSSL_PATH)/crypto/conf/conf_def.c

+ $(OPENSSL_PATH)/crypto/conf/conf_err.c

+ $(OPENSSL_PATH)/crypto/conf/conf_lib.c

+ $(OPENSSL_PATH)/crypto/conf/conf_mall.c

+ $(OPENSSL_PATH)/crypto/conf/conf_mod.c

+ $(OPENSSL_PATH)/crypto/conf/conf_sap.c

+ $(OPENSSL_PATH)/crypto/conf/conf_ssl.c

+ $(OPENSSL_PATH)/crypto/cpt_err.c

+ $(OPENSSL_PATH)/crypto/cryptlib.c

+ $(OPENSSL_PATH)/crypto/ctype.c

+ $(OPENSSL_PATH)/crypto/cversion.c

+ $(OPENSSL_PATH)/crypto/dh/dh_ameth.c

+ $(OPENSSL_PATH)/crypto/dh/dh_asn1.c

+ $(OPENSSL_PATH)/crypto/dh/dh_check.c

+ $(OPENSSL_PATH)/crypto/dh/dh_depr.c

+ $(OPENSSL_PATH)/crypto/dh/dh_err.c

+ $(OPENSSL_PATH)/crypto/dh/dh_gen.c

+ $(OPENSSL_PATH)/crypto/dh/dh_kdf.c

+ $(OPENSSL_PATH)/crypto/dh/dh_key.c

+ $(OPENSSL_PATH)/crypto/dh/dh_lib.c

+ $(OPENSSL_PATH)/crypto/dh/dh_meth.c

+ $(OPENSSL_PATH)/crypto/dh/dh_pmeth.c

+ $(OPENSSL_PATH)/crypto/dh/dh_prn.c

+ $(OPENSSL_PATH)/crypto/dh/dh_rfc5114.c

+ $(OPENSSL_PATH)/crypto/dh/dh_rfc7919.c

+ $(OPENSSL_PATH)/crypto/dso/dso_dl.c

+ $(OPENSSL_PATH)/crypto/dso/dso_dlfcn.c

+ $(OPENSSL_PATH)/crypto/dso/dso_err.c

+ $(OPENSSL_PATH)/crypto/dso/dso_lib.c

+ $(OPENSSL_PATH)/crypto/dso/dso_openssl.c

+ $(OPENSSL_PATH)/crypto/dso/dso_vms.c

+ $(OPENSSL_PATH)/crypto/dso/dso_win32.c

+ $(OPENSSL_PATH)/crypto/ebcdic.c

+ $(OPENSSL_PATH)/crypto/err/err.c

+ $(OPENSSL_PATH)/crypto/err/err_prn.c

+ $(OPENSSL_PATH)/crypto/evp/bio_b64.c

+ $(OPENSSL_PATH)/crypto/evp/bio_enc.c

+ $(OPENSSL_PATH)/crypto/evp/bio_md.c

+ $(OPENSSL_PATH)/crypto/evp/bio_ok.c

+ $(OPENSSL_PATH)/crypto/evp/c_allc.c

+ $(OPENSSL_PATH)/crypto/evp/c_alld.c

+ $(OPENSSL_PATH)/crypto/evp/cmeth_lib.c

+ $(OPENSSL_PATH)/crypto/evp/digest.c

+ $(OPENSSL_PATH)/crypto/evp/e_aes.c

+ $(OPENSSL_PATH)/crypto/evp/e_aes_cbc_hmac_sha1.c

+
$(OPENSSL_PATH)/crypto/evp/e_aes_cbc_hmac_sha256.c

+ $(OPENSSL_PATH)/crypto/evp/e_aria.c

+ $(OPENSSL_PATH)/crypto/evp/e_bf.c

+ $(OPENSSL_PATH)/crypto/evp/e_camellia.c

+ $(OPENSSL_PATH)/crypto/evp/e_cast.c

+ $(OPENSSL_PATH)/crypto/evp/e_chacha20_poly1305.c

+ $(OPENSSL_PATH)/crypto/evp/e_des.c

+ $(OPENSSL_PATH)/crypto/evp/e_des3.c

+ $(OPENSSL_PATH)/crypto/evp/e_idea.c

+ $(OPENSSL_PATH)/crypto/evp/e_null.c

+ $(OPENSSL_PATH)/crypto/evp/e_old.c

+ $(OPENSSL_PATH)/crypto/evp/e_rc2.c

+ $(OPENSSL_PATH)/crypto/evp/e_rc4.c

+ $(OPENSSL_PATH)/crypto/evp/e_rc4_hmac_md5.c

+ $(OPENSSL_PATH)/crypto/evp/e_rc5.c

+ $(OPENSSL_PATH)/crypto/evp/e_seed.c

+ $(OPENSSL_PATH)/crypto/evp/e_sm4.c

+ $(OPENSSL_PATH)/crypto/evp/e_xcbc_d.c

+ $(OPENSSL_PATH)/crypto/evp/encode.c

+ $(OPENSSL_PATH)/crypto/evp/evp_cnf.c

+ $(OPENSSL_PATH)/crypto/evp/evp_enc.c

+ $(OPENSSL_PATH)/crypto/evp/evp_err.c

+ $(OPENSSL_PATH)/crypto/evp/evp_key.c

+ $(OPENSSL_PATH)/crypto/evp/evp_lib.c

+ $(OPENSSL_PATH)/crypto/evp/evp_pbe.c

+ $(OPENSSL_PATH)/crypto/evp/evp_pkey.c

+ $(OPENSSL_PATH)/crypto/evp/m_md2.c

+ $(OPENSSL_PATH)/crypto/evp/m_md4.c

+ $(OPENSSL_PATH)/crypto/evp/m_md5.c

+ $(OPENSSL_PATH)/crypto/evp/m_md5_sha1.c

+ $(OPENSSL_PATH)/crypto/evp/m_mdc2.c

+ $(OPENSSL_PATH)/crypto/evp/m_null.c

+ $(OPENSSL_PATH)/crypto/evp/m_ripemd.c

+ $(OPENSSL_PATH)/crypto/evp/m_sha1.c

+ $(OPENSSL_PATH)/crypto/evp/m_sha3.c

+ $(OPENSSL_PATH)/crypto/evp/m_sigver.c

+ $(OPENSSL_PATH)/crypto/evp/m_wp.c

+ $(OPENSSL_PATH)/crypto/evp/names.c

+ $(OPENSSL_PATH)/crypto/evp/p5_crpt.c

+ $(OPENSSL_PATH)/crypto/evp/p5_crpt2.c

+ $(OPENSSL_PATH)/crypto/evp/p_dec.c

+ $(OPENSSL_PATH)/crypto/evp/p_enc.c

+ $(OPENSSL_PATH)/crypto/evp/p_lib.c

+ $(OPENSSL_PATH)/crypto/evp/p_open.c

+ $(OPENSSL_PATH)/crypto/evp/p_seal.c

+ $(OPENSSL_PATH)/crypto/evp/p_sign.c

+ $(OPENSSL_PATH)/crypto/evp/p_verify.c

+ $(OPENSSL_PATH)/crypto/evp/pbe_scrypt.c

+ $(OPENSSL_PATH)/crypto/evp/pmeth_fn.c

+ $(OPENSSL_PATH)/crypto/evp/pmeth_gn.c

+ $(OPENSSL_PATH)/crypto/evp/pmeth_lib.c

+ $(OPENSSL_PATH)/crypto/ex_data.c

+ $(OPENSSL_PATH)/crypto/getenv.c

+ $(OPENSSL_PATH)/crypto/hmac/hm_ameth.c

+ $(OPENSSL_PATH)/crypto/hmac/hm_pmeth.c

+ $(OPENSSL_PATH)/crypto/hmac/hmac.c

+ $(OPENSSL_PATH)/crypto/init.c

+ $(OPENSSL_PATH)/crypto/kdf/hkdf.c

+ $(OPENSSL_PATH)/crypto/kdf/kdf_err.c

+ $(OPENSSL_PATH)/crypto/kdf/scrypt.c

+ $(OPENSSL_PATH)/crypto/kdf/tls1_prf.c

+ $(OPENSSL_PATH)/crypto/lhash/lh_stats.c

+ $(OPENSSL_PATH)/crypto/lhash/lhash.c

+ $(OPENSSL_PATH)/crypto/md5/md5_dgst.c

+ $(OPENSSL_PATH)/crypto/md5/md5_one.c

+ $(OPENSSL_PATH)/crypto/mem.c

+ $(OPENSSL_PATH)/crypto/mem_dbg.c

+ $(OPENSSL_PATH)/crypto/mem_sec.c

+ $(OPENSSL_PATH)/crypto/modes/cbc128.c

+ $(OPENSSL_PATH)/crypto/modes/ccm128.c

+ $(OPENSSL_PATH)/crypto/modes/cfb128.c

+ $(OPENSSL_PATH)/crypto/modes/ctr128.c

+ $(OPENSSL_PATH)/crypto/modes/cts128.c

+ $(OPENSSL_PATH)/crypto/modes/gcm128.c

+ $(OPENSSL_PATH)/crypto/modes/ocb128.c

+ $(OPENSSL_PATH)/crypto/modes/ofb128.c

+ $(OPENSSL_PATH)/crypto/modes/wrap128.c

+ $(OPENSSL_PATH)/crypto/modes/xts128.c

+ $(OPENSSL_PATH)/crypto/o_dir.c

+ $(OPENSSL_PATH)/crypto/o_fips.c

+ $(OPENSSL_PATH)/crypto/o_fopen.c

+ $(OPENSSL_PATH)/crypto/o_init.c

+ $(OPENSSL_PATH)/crypto/o_str.c

+ $(OPENSSL_PATH)/crypto/o_time.c

+ $(OPENSSL_PATH)/crypto/objects/o_names.c

+ $(OPENSSL_PATH)/crypto/objects/obj_dat.c

+ $(OPENSSL_PATH)/crypto/objects/obj_err.c

+ $(OPENSSL_PATH)/crypto/objects/obj_lib.c

+ $(OPENSSL_PATH)/crypto/objects/obj_xref.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_asn.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_cl.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_err.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_ext.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_ht.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_lib.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_prn.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_srv.c

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_vfy.c

+ $(OPENSSL_PATH)/crypto/ocsp/v3_ocsp.c

+ $(OPENSSL_PATH)/crypto/pem/pem_all.c

+ $(OPENSSL_PATH)/crypto/pem/pem_err.c

+ $(OPENSSL_PATH)/crypto/pem/pem_info.c

+ $(OPENSSL_PATH)/crypto/pem/pem_lib.c

+ $(OPENSSL_PATH)/crypto/pem/pem_oth.c

+ $(OPENSSL_PATH)/crypto/pem/pem_pk8.c

+ $(OPENSSL_PATH)/crypto/pem/pem_pkey.c

+ $(OPENSSL_PATH)/crypto/pem/pem_sign.c

+ $(OPENSSL_PATH)/crypto/pem/pem_x509.c

+ $(OPENSSL_PATH)/crypto/pem/pem_xaux.c

+ $(OPENSSL_PATH)/crypto/pem/pvkfmt.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_add.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_asn.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_attr.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_crpt.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_crt.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_decr.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_init.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_key.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_kiss.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_mutl.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_npas.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_p8d.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_p8e.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_sbag.c

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_utl.c

+ $(OPENSSL_PATH)/crypto/pkcs12/pk12err.c

+ $(OPENSSL_PATH)/crypto/pkcs7/bio_pk7.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_asn1.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_attr.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_doit.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_lib.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_mime.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_smime.c

+ $(OPENSSL_PATH)/crypto/pkcs7/pkcs7err.c

+ $(OPENSSL_PATH)/crypto/rand/drbg_ctr.c

+ $(OPENSSL_PATH)/crypto/rand/drbg_lib.c

+ $(OPENSSL_PATH)/crypto/rand/rand_egd.c

+ $(OPENSSL_PATH)/crypto/rand/rand_err.c

+ $(OPENSSL_PATH)/crypto/rand/rand_lib.c

+ $(OPENSSL_PATH)/crypto/rand/rand_unix.c

+ $(OPENSSL_PATH)/crypto/rand/rand_vms.c

+ $(OPENSSL_PATH)/crypto/rand/rand_win.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_ameth.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_asn1.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_chk.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_crpt.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_depr.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_err.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_gen.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_lib.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_meth.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_mp.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_none.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_oaep.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_ossl.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_pk1.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_pmeth.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_prn.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_pss.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_saos.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_sign.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_ssl.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_x931.c

+ $(OPENSSL_PATH)/crypto/rsa/rsa_x931g.c

+ $(OPENSSL_PATH)/crypto/sha/keccak1600.c

+ $(OPENSSL_PATH)/crypto/sha/sha1_one.c

+ $(OPENSSL_PATH)/crypto/sha/sha1dgst.c

+ $(OPENSSL_PATH)/crypto/sha/sha256.c

+ $(OPENSSL_PATH)/crypto/sha/sha512.c

+ $(OPENSSL_PATH)/crypto/siphash/siphash.c

+ $(OPENSSL_PATH)/crypto/siphash/siphash_ameth.c

+ $(OPENSSL_PATH)/crypto/siphash/siphash_pmeth.c

+ $(OPENSSL_PATH)/crypto/sm3/m_sm3.c

+ $(OPENSSL_PATH)/crypto/sm3/sm3.c

+ $(OPENSSL_PATH)/crypto/sm4/sm4.c

+ $(OPENSSL_PATH)/crypto/stack/stack.c

+ $(OPENSSL_PATH)/crypto/threads_none.c

+ $(OPENSSL_PATH)/crypto/threads_pthread.c

+ $(OPENSSL_PATH)/crypto/threads_win.c

+ $(OPENSSL_PATH)/crypto/txt_db/txt_db.c

+ $(OPENSSL_PATH)/crypto/ui/ui_err.c

+ $(OPENSSL_PATH)/crypto/ui/ui_lib.c

+ $(OPENSSL_PATH)/crypto/ui/ui_null.c

+ $(OPENSSL_PATH)/crypto/ui/ui_openssl.c

+ $(OPENSSL_PATH)/crypto/ui/ui_util.c

+ $(OPENSSL_PATH)/crypto/uid.c

+ $(OPENSSL_PATH)/crypto/x509/by_dir.c

+ $(OPENSSL_PATH)/crypto/x509/by_file.c

+ $(OPENSSL_PATH)/crypto/x509/t_crl.c

+ $(OPENSSL_PATH)/crypto/x509/t_req.c

+ $(OPENSSL_PATH)/crypto/x509/t_x509.c

+ $(OPENSSL_PATH)/crypto/x509/x509_att.c

+ $(OPENSSL_PATH)/crypto/x509/x509_cmp.c

+ $(OPENSSL_PATH)/crypto/x509/x509_d2.c

+ $(OPENSSL_PATH)/crypto/x509/x509_def.c

+ $(OPENSSL_PATH)/crypto/x509/x509_err.c

+ $(OPENSSL_PATH)/crypto/x509/x509_ext.c

+ $(OPENSSL_PATH)/crypto/x509/x509_lu.c

+ $(OPENSSL_PATH)/crypto/x509/x509_meth.c

+ $(OPENSSL_PATH)/crypto/x509/x509_obj.c

+ $(OPENSSL_PATH)/crypto/x509/x509_r2x.c

+ $(OPENSSL_PATH)/crypto/x509/x509_req.c

+ $(OPENSSL_PATH)/crypto/x509/x509_set.c

+ $(OPENSSL_PATH)/crypto/x509/x509_trs.c

+ $(OPENSSL_PATH)/crypto/x509/x509_txt.c

+ $(OPENSSL_PATH)/crypto/x509/x509_v3.c

+ $(OPENSSL_PATH)/crypto/x509/x509_vfy.c

+ $(OPENSSL_PATH)/crypto/x509/x509_vpm.c

+ $(OPENSSL_PATH)/crypto/x509/x509cset.c

+ $(OPENSSL_PATH)/crypto/x509/x509name.c

+ $(OPENSSL_PATH)/crypto/x509/x509rset.c

+ $(OPENSSL_PATH)/crypto/x509/x509spki.c

+ $(OPENSSL_PATH)/crypto/x509/x509type.c

+ $(OPENSSL_PATH)/crypto/x509/x_all.c

+ $(OPENSSL_PATH)/crypto/x509/x_attrib.c

+ $(OPENSSL_PATH)/crypto/x509/x_crl.c

+ $(OPENSSL_PATH)/crypto/x509/x_exten.c

+ $(OPENSSL_PATH)/crypto/x509/x_name.c

+ $(OPENSSL_PATH)/crypto/x509/x_pubkey.c

+ $(OPENSSL_PATH)/crypto/x509/x_req.c

+ $(OPENSSL_PATH)/crypto/x509/x_x509.c

+ $(OPENSSL_PATH)/crypto/x509/x_x509a.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_cache.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_data.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_lib.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_map.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_node.c

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_tree.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_addr.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_admis.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_akey.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_akeya.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_alt.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_asid.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_bcons.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_bitst.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_conf.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_cpols.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_crld.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_enum.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_extku.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_genn.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_ia5.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_info.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_int.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_lib.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_ncons.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_pci.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_pcia.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_pcons.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_pku.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_pmaps.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_prn.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_purp.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_skey.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_sxnet.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_tlsf.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3_utl.c

+ $(OPENSSL_PATH)/crypto/x509v3/v3err.c

+ $(OPENSSL_PATH)/crypto/arm_arch.h

+ $(OPENSSL_PATH)/crypto/mips_arch.h

+ $(OPENSSL_PATH)/crypto/ppc_arch.h

+ $(OPENSSL_PATH)/crypto/s390x_arch.h

+ $(OPENSSL_PATH)/crypto/sparc_arch.h

+ $(OPENSSL_PATH)/crypto/vms_rms.h

+ $(OPENSSL_PATH)/crypto/aes/aes_local.h

+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.h

+ $(OPENSSL_PATH)/crypto/asn1/asn1_local.h

+ $(OPENSSL_PATH)/crypto/asn1/charmap.h

+ $(OPENSSL_PATH)/crypto/asn1/standard_methods.h

+ $(OPENSSL_PATH)/crypto/asn1/tbl_standard.h

+ $(OPENSSL_PATH)/crypto/async/async_local.h

+ $(OPENSSL_PATH)/crypto/async/arch/async_null.h

+ $(OPENSSL_PATH)/crypto/async/arch/async_posix.h

+ $(OPENSSL_PATH)/crypto/async/arch/async_win.h

+ $(OPENSSL_PATH)/crypto/bio/bio_local.h

+ $(OPENSSL_PATH)/crypto/bn/bn_local.h

+ $(OPENSSL_PATH)/crypto/bn/bn_prime.h

+ $(OPENSSL_PATH)/crypto/bn/rsaz_exp.h

+ $(OPENSSL_PATH)/crypto/comp/comp_local.h

+ $(OPENSSL_PATH)/crypto/conf/conf_def.h

+ $(OPENSSL_PATH)/crypto/conf/conf_local.h

+ $(OPENSSL_PATH)/crypto/dh/dh_local.h

+ $(OPENSSL_PATH)/crypto/dso/dso_local.h

+ $(OPENSSL_PATH)/crypto/evp/evp_local.h

+ $(OPENSSL_PATH)/crypto/hmac/hmac_local.h

+ $(OPENSSL_PATH)/crypto/lhash/lhash_local.h

+ $(OPENSSL_PATH)/crypto/md5/md5_local.h

+ $(OPENSSL_PATH)/crypto/modes/modes_local.h

+ $(OPENSSL_PATH)/crypto/objects/obj_dat.h

+ $(OPENSSL_PATH)/crypto/objects/obj_local.h

+ $(OPENSSL_PATH)/crypto/objects/obj_xref.h

+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_local.h

+ $(OPENSSL_PATH)/crypto/pkcs12/p12_local.h

+ $(OPENSSL_PATH)/crypto/rand/rand_local.h

+ $(OPENSSL_PATH)/crypto/rsa/rsa_local.h

+ $(OPENSSL_PATH)/crypto/sha/sha_local.h

+ $(OPENSSL_PATH)/crypto/siphash/siphash_local.h

+ $(OPENSSL_PATH)/crypto/sm3/sm3_local.h

+ $(OPENSSL_PATH)/crypto/store/store_local.h

+ $(OPENSSL_PATH)/crypto/ui/ui_local.h

+ $(OPENSSL_PATH)/crypto/x509/x509_local.h

+ $(OPENSSL_PATH)/crypto/x509v3/ext_dat.h

+ $(OPENSSL_PATH)/crypto/x509v3/pcy_local.h

+ $(OPENSSL_PATH)/crypto/x509v3/standard_exts.h

+ $(OPENSSL_PATH)/crypto/x509v3/v3_admis.h

+ $(OPENSSL_PATH)/ssl/bio_ssl.c

+ $(OPENSSL_PATH)/ssl/d1_lib.c

+ $(OPENSSL_PATH)/ssl/d1_msg.c

+ $(OPENSSL_PATH)/ssl/d1_srtp.c

+ $(OPENSSL_PATH)/ssl/methods.c

+ $(OPENSSL_PATH)/ssl/packet.c

+ $(OPENSSL_PATH)/ssl/pqueue.c

+ $(OPENSSL_PATH)/ssl/record/dtls1_bitmap.c

+ $(OPENSSL_PATH)/ssl/record/rec_layer_d1.c

+ $(OPENSSL_PATH)/ssl/record/rec_layer_s3.c

+ $(OPENSSL_PATH)/ssl/record/ssl3_buffer.c

+ $(OPENSSL_PATH)/ssl/record/ssl3_record.c

+ $(OPENSSL_PATH)/ssl/record/ssl3_record_tls13.c

+ $(OPENSSL_PATH)/ssl/s3_cbc.c

+ $(OPENSSL_PATH)/ssl/s3_enc.c

+ $(OPENSSL_PATH)/ssl/s3_lib.c

+ $(OPENSSL_PATH)/ssl/s3_msg.c

+ $(OPENSSL_PATH)/ssl/ssl_asn1.c

+ $(OPENSSL_PATH)/ssl/ssl_cert.c

+ $(OPENSSL_PATH)/ssl/ssl_ciph.c

+ $(OPENSSL_PATH)/ssl/ssl_conf.c

+ $(OPENSSL_PATH)/ssl/ssl_err.c

+ $(OPENSSL_PATH)/ssl/ssl_init.c

+ $(OPENSSL_PATH)/ssl/ssl_lib.c

+ $(OPENSSL_PATH)/ssl/ssl_mcnf.c

+ $(OPENSSL_PATH)/ssl/ssl_rsa.c

+ $(OPENSSL_PATH)/ssl/ssl_sess.c

+ $(OPENSSL_PATH)/ssl/ssl_stat.c

+ $(OPENSSL_PATH)/ssl/ssl_txt.c

+ $(OPENSSL_PATH)/ssl/ssl_utst.c

+ $(OPENSSL_PATH)/ssl/statem/extensions.c

+ $(OPENSSL_PATH)/ssl/statem/extensions_clnt.c

+ $(OPENSSL_PATH)/ssl/statem/extensions_cust.c

+ $(OPENSSL_PATH)/ssl/statem/extensions_srvr.c

+ $(OPENSSL_PATH)/ssl/statem/statem.c

+ $(OPENSSL_PATH)/ssl/statem/statem_clnt.c

+ $(OPENSSL_PATH)/ssl/statem/statem_dtls.c

+ $(OPENSSL_PATH)/ssl/statem/statem_lib.c

+ $(OPENSSL_PATH)/ssl/statem/statem_srvr.c

+ $(OPENSSL_PATH)/ssl/t1_enc.c

+ $(OPENSSL_PATH)/ssl/t1_lib.c

+ $(OPENSSL_PATH)/ssl/t1_trce.c

+ $(OPENSSL_PATH)/ssl/tls13_enc.c

+ $(OPENSSL_PATH)/ssl/tls_srp.c

+ $(OPENSSL_PATH)/ssl/packet_local.h

+ $(OPENSSL_PATH)/ssl/ssl_cert_table.h

+ $(OPENSSL_PATH)/ssl/ssl_local.h

+ $(OPENSSL_PATH)/ssl/record/record.h

+ $(OPENSSL_PATH)/ssl/record/record_local.h

+ $(OPENSSL_PATH)/ssl/statem/statem.h

+ $(OPENSSL_PATH)/ssl/statem/statem_local.h

+# Autogenerated files list ends here

+ buildinf.h

+ rand_pool_noise.h

+ ossl_store.c

+ rand_pool.c

+

+[Sources.X64]

+ rand_pool_noise_tsc.c

+ ApiHooks.c

+

+[Packages]

+ MdePkg/MdePkg.dec

+ CryptoPkg/CryptoPkg.dec

+

+[LibraryClasses]

+ BaseLib

+ DebugLib

+ TimerLib

+ PrintLib

+

+[BuildOptions]

+ #

+ # Disables the following Visual Studio compiler
warnings
brought
by
openssl
source,

+ # so we do not break the build with /WX option:

+ # C4090: 'function' : different 'const'
qualifiers

+ # C4132: 'object' : const object should be
initialized
(tls13_enc.c)

+ # C4210: nonstandard extension used: function
given
file
scope

+ # C4244: conversion from type1 to type2,
possible
loss of
data

+ # C4245: conversion from type1 to type2,
signed/unsigned
mismatch

+ # C4267: conversion from size_t to type,
possible
loss of
data

+ # C4306: 'identifier' : conversion from
'type1'
to
'type2'
of
greater
size

+ # C4310: cast truncates constant value

+ # C4389: 'operator' : signed/unsigned mismatch
(xxxx)

+ # C4700: uninitialized local variable 'name'
used.
(conf_sap.c(71))

+ # C4702: unreachable code

+ # C4706: assignment within conditional
expression

+ # C4819: The file contains a character that
cannot
be
represented
in
the
current code page

+ #

+ MSFT:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64
-U_MSC_VER
$(OPENSSL_FLAGS) $(OPENSSL_FLAGS_CONFIG) /wd4090
/wd4132
/wd4210
/wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700
/wd4389
/wd4702
/wd4706 /wd4819

+

+ INTEL:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64
-U_MSC_VER -
U__ICC
$(OPENSSL_FLAGS) $(OPENSSL_FLAGS_CONFIG) /w

+

+ #

+ # Suppress the following build warnings in
openssl
so
we
don't
break
the
build
with -Werror

+ # -Werror=maybe-uninitialized: there exist
some
other
paths
for
which
the
variable is not initialized.

+ # -Werror=format: Check calls to printf and
scanf,
etc.,
to
make
sure
that the
arguments supplied have

+ # types appropriate to the
format
string
specified.

+ # -Werror=unused-but-set-variable: Warn
whenever
a
local
variable is
assigned to, but otherwise unused (aside from its
declaration).

+ #

+ GCC:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64
$(OPENSSL_FLAGS)
$(OPENSSL_FLAGS_CONFIG) -Wno-error=maybe-
uninitialized
-Wno-
error=format -Wno-format
-Wno-error=unused-but-set-variable -
DNO_MSABI_VA_FUNCS

+

+ # suppress the following warnings in openssl so
we
don't
break
the
build
with
warnings-as-errors:

+ # 1295: Deprecated declaration <entity> - give
arg
types

+ # 550: <entity> was set but never used

+ # 1293: assignment in condition

+ # 111: statement is unreachable (invariably
"break;"
after
"return
X;"
in case
statement)

+ # 68: integer conversion resulted in a change
of
sign
("if
(Status
==
-1)")

+ # 177: <entity> was declared but never
referenced

+ # 223: function <entity> declared implicitly

+ # 144: a value of type <type> cannot be used to
initialize
an
entity
of
type
<type>

+ # 513: a value of type <type> cannot be
assigned
to
an
entity
of
type
<type>

+ # 188: enumerated type mixed with another type
(i.e.
passing an
integer
as an
enum without a cast)

+ # 1296: Extended constant initialiser used

+ # 128: loop is not reachable - may be emitted
inappropriately
if
code
follows
a conditional return

+ # from the function that evaluates to true
at
compile
time

+ # 546: transfer of control bypasses
initialization
-
may be
emitted
inappropriately if the uninitialized

+ # variable is never referenced after the
jump

+ # 1: ignore "#1-D: last line of file ends
without
a
newline"

+ # 3017: <entity> may be used before being set
(NOTE:
This
was
fixed in
OpenSSL 1.1 HEAD with

+ # commit
d9b8b89bec4480de3a10bdaf9425db371c19145b, and
can
be
dropped then.)

+ XCODE:*_*_X64_CC_FLAGS = -mmmx -msse
-U_WIN32 -
U_WIN64
$(OPENSSL_FLAGS) $(OPENSSL_FLAGS_CONFIG) -w -
std=c99
-Wno-
error=uninitialized

diff --git
a/CryptoPkg/Library/Include/openssl/opensslconf.h
b/CryptoPkg/Library/Include/openssl/opensslconf.h
index 3a2544ea5c..e8f73c4d10 100644
---
a/CryptoPkg/Library/Include/openssl/opensslconf.h
+++
b/CryptoPkg/Library/Include/openssl/opensslconf.h
@@ -112,9 +112,6 @@ extern "C" {
#ifndef OPENSSL_NO_ASAN

# define OPENSSL_NO_ASAN

#endif

-#ifndef OPENSSL_NO_ASM

-# define OPENSSL_NO_ASM

-#endif

#ifndef OPENSSL_NO_ASYNC

# define OPENSSL_NO_ASYNC

#endif

diff --git
a/CryptoPkg/Library/OpensslLib/ApiHooks.c
b/CryptoPkg/Library/OpensslLib/ApiHooks.c
new file mode 100644
index 0000000000..58cff16838
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/ApiHooks.c
@@ -0,0 +1,18 @@
+/** @file

+ OpenSSL Library API hooks.

+

+Copyright (c) 2020, Intel Corporation. All rights
reserved.<BR>

+SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#include <Uefi.h>

+

+VOID *

+__imp_RtlVirtualUnwind (

+ VOID * Args

+ )

+{

+ return NULL;

+}

+

diff --git
a/CryptoPkg/Library/OpensslLib/OpensslLibConstructor.c
b/CryptoPkg/Library/OpensslLib/OpensslLibConstructor.c
new file mode 100644
index 0000000000..ef20d2b84e
--- /dev/null
+++
b/CryptoPkg/Library/OpensslLib/OpensslLibConstructor.c
@@ -0,0 +1,34 @@
+/** @file

+ Constructor to initialize CPUID data for OpenSSL
assembly
operations.

+

+Copyright (c) 2020, Intel Corporation. All rights
reserved.<BR>

+SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#include <Uefi.h>

+

+extern void OPENSSL_cpuid_setup (void);

+

+/**

+ Constructor routine for OpensslLib.

+

+ The constructor calls an internal OpenSSL
function
which
fetches
a
local
copy

+ of the hardware capability flags, used to enable
native
crypto
instructions.

+

+ @param None

+

+ @retval EFI_SUCCESS The construction
succeeded.

+

+**/

+EFI_STATUS

+EFIAPI

+OpensslLibConstructor (

+ VOID

+ )

+{

+ OPENSSL_cpuid_setup ();

+

+ return EFI_SUCCESS;

+}

+

diff --git
a/CryptoPkg/Library/OpensslLib/process_files.pl
b/CryptoPkg/Library/OpensslLib/process_files.pl
index 57ce195394..472f59bc8e 100755
--- a/CryptoPkg/Library/OpensslLib/process_files.pl
+++ b/CryptoPkg/Library/OpensslLib/process_files.pl
@@ -9,9 +9,63 @@
# do not need to do this, since the results are
stored
in
the
EDK2

# git repository for them.

#

+# Due to the script wrapping required to process
the
OpenSSL

+# configuration data, each native architecture
must
be
processed

+# individually by the maintainer (in addition to
the
standard
version):

+# ./process_files.pl

+# ./process_files.pl X64

+# ./process_files.pl [Arch]

+

use strict;

use Cwd;

use File::Copy;

+use File::Basename;

+use File::Path qw(make_path remove_tree);

+use Text::Tabs;

+

+#

+# OpenSSL perlasm generator script does not
transfer
the
copyright
header

+#

+sub copy_license_header

+{

+ my @args = split / /, shift; #Separate args
by
spaces

+ my $source = $args[1]; #Source file
is
second
(after
"perl")

+ my $target = pop @args; #Target file
is
always
last

+ chop ($target); #Remove
newline
char

+

+ my $temp_file_name = "license.tmp";

+ open (my $source_file, "<" . $source) || die
$source;

+ open (my $target_file, "<" . $target) || die
$target;

+ open (my $temp_file, ">" . $temp_file_name) ||
die
$temp_file_name;

+

+ #Add "generated file" warning

+ $source =~ s/^..//; #Remove
leading
"./"

+ print ($temp_file "; WARNING: do not
edit!\r\n");

+ print ($temp_file "; Generated from
$source\r\n");

+ print ($temp_file ";\r\n");

+

+ #Copy source file header to temp file

+ while (my $line = <$source_file>) {

+ next if ($line =~ /#!/); #Ignore
shebang
line

+ $line =~ s/#/;/; #Fix comment
character for
assembly

+ $line =~ s/\s+$/\r\n/; #Trim trailing
whitepsace,
fixup
line
endings

+ print ($temp_file $line);

+ last if ($line =~ /http/); #Last line of
copyright
header
contains a web link

+ }

+ print ($temp_file "\r\n");

+ #Retrieve generated assembly contents

+ while (my $line = <$target_file>) {

+ $line =~ s/\s+$/\r\n/; #Trim trailing
whitepsace,
fixup
line
endings

+ print ($temp_file expand ($line));
#expand()
replaces
tabs with
spaces

+ }

+

+ close ($source_file);

+ close ($target_file);

+ close ($temp_file);

+

+ move ($temp_file_name, $target) ||

+ die "Cannot replace \"" . $target . "\"!";

+}



#

# Find the openssl directory name for use lib. We
have
to
do
this

@@ -21,10 +75,41 @@ use File::Copy;
#

my $inf_file;

my $OPENSSL_PATH;

+my $uefi_config;

+my $extension;

+my $arch;

my @inf;



BEGIN {

$inf_file = "OpensslLib.inf";

+ $uefi_config = "UEFI";

+ $arch = shift;

+

+ if (defined $arch) {

+ if (uc ($arch) eq "X64") {

+ $arch = "X64";

+ $inf_file = "OpensslLibX64.inf";

+ $uefi_config = "UEFI-x86_64";

+ $extension = "nasm";

+ } else {

+ die "Unsupported architecture \"" .
$arch
.
"\"!";

+ }

+ if ($extension eq "nasm") {

+ if (`nasm -v 2>&1`) {

+ #Presence of nasm executable will
trigger
inclusion of
AVX
instructions

+ die "\nCannot run assembly
generators
with
NASM in
path!\n\n";

+ }

+ }

+

+ # Prepare assembly folder

+ if (-d $arch) {

+ remove_tree ($arch, {safe => 1}) ||

+ die "Cannot clean assembly folder
\""
.
$arch
.
"\"!";

+ } else {

+ mkdir $arch ||

+ die "Cannot create assembly folder
\""
.
$arch
.
"\"!";

+ }

+ }



# Read the contents of the inf file

open( FD, "<" . $inf_file ) ||

@@ -47,9 +132,9 @@ BEGIN {
# Configure UEFI

system(

"./Configure",

- "UEFI",

+ "--config=../uefi-asm.conf",

+ "$uefi_config",

"no-afalgeng",

- "no-asm",

"no-async",

"no-autoerrinit",

"no-autoload-config",

@@ -129,23 +214,53 @@ BEGIN {
# Retrieve file lists from OpenSSL configdata

#

use configdata qw/%unified_info/;

+use configdata qw/%config/;

+use configdata qw/%target/;

+

+#

+# Collect build flags from configdata

+#

+my $flags = "";

+foreach my $f (@{$config{lib_defines}}) {

+ $flags .= " -D$f";

+}



my @cryptofilelist = ();

my @sslfilelist = ();

+my @asmfilelist = ();

+my @asmbuild = ();

foreach my $product ((@{$unified_info{libraries}},

@{$unified_info{engines}}))
{

foreach my $o (@{$unified_info{sources}-
{$product}})
{

foreach my $s (@{$unified_info{sources}-
{$o}}) {

- next if ($unified_info{generate}-
{$s});

- next if $s =~ "crypto/bio/b_print.c";

-

# No need to add unused files in UEFI.

# So it can reduce porting time,
compile
time,
library
size.

+ next if $s =~ "crypto/bio/b_print.c";

next if $s =~
"crypto/rand/randfile.c";

next if $s =~ "crypto/store/";

next if $s =~ "crypto/err/err_all.c";

next if $s =~ "crypto/aes/aes_ecb.c";



+ if ($unified_info{generate}->{$s}) {

+ if (defined $arch) {

+ my $buildstring = "perl";

+ foreach my $arg
(@{$unified_info{generate}-
{$s}}) {

+ if ($arg =~ ".pl") {

+ $buildstring .=
" ./openssl/$arg";

+ } elsif ($arg =~
"PERLASM_SCHEME") {

+ $buildstring .= "
$target{perlasm_scheme}";

+ } elsif ($arg =~
"LIB_CFLAGS")
{

+ $buildstring .=
"$flags";

+ }

+ }

+ ($s, my $path, undef) =
fileparse($s,
qr/\.[^.]*/);

+ $buildstring .= "
./$arch/$path$s.$extension";

+ make_path ("./$arch/$path");

+ push @asmbuild,
"$buildstring\n";

+ push @asmfilelist, "
$arch/$path$s.$extension\r\n";

+ }

+ next;

+ }

if ($product =~ "libssl") {

push @sslfilelist, '
$(OPENSSL_PATH)/' .
$s .
"\r\n";

next;

@@ -183,15 +298,31 @@ foreach (@headers){
}





+#

+# Generate assembly files

+#

+if (@asmbuild) {

+ print "\n--> Generating assembly files ... ";

+ foreach my $buildstring (@asmbuild) {

+ system ("$buildstring");

+ copy_license_header ($buildstring);

+ }

+ print "Done!";

+}

+

#

# Update OpensslLib.inf with autogenerated file
list

#

my @new_inf = ();

my $subbing = 0;

-print "\n--> Updating OpensslLib.inf ... ";

+print "\n--> Updating $inf_file ... ";

foreach (@inf) {

+ if ($_ =~ "DEFINE OPENSSL_FLAGS_CONFIG") {

+ push @new_inf, " DEFINE
OPENSSL_FLAGS_CONFIG =" .
$flags
.
"\r\n";

+ next;

+ }

if ( $_ =~ "# Autogenerated files list starts
here" )
{

- push @new_inf, $_, @cryptofilelist,
@sslfilelist;

+ push @new_inf, $_, @asmfilelist,
@cryptofilelist,
@sslfilelist;

$subbing = 1;

next;

}

@@ -216,49 +347,51 @@ rename( $new_inf_file,
$inf_file
)
||
die "rename $inf_file";

print "Done!";



-#

-# Update OpensslLibCrypto.inf with auto-generated
file
list
(no
libssl)

-#

-$inf_file = "OpensslLibCrypto.inf";

-

-# Read the contents of the inf file

-@inf = ();

-@new_inf = ();

-open( FD, "<" . $inf_file ) ||

- die "Cannot open \"" . $inf_file . "\"!";

-@inf = (<FD>);

-close(FD) ||

- die "Cannot close \"" . $inf_file . "\"!";

+if (!defined $arch) {

+ #

+ # Update OpensslLibCrypto.inf with auto-
generated
file
list
(no
libssl)

+ #

+ $inf_file = "OpensslLibCrypto.inf";



-$subbing = 0;

-print "\n--> Updating OpensslLibCrypto.inf ... ";

-foreach (@inf) {

- if ( $_ =~ "# Autogenerated files list starts
here" )
{

- push @new_inf, $_, @cryptofilelist;

- $subbing = 1;

- next;

- }

- if ( $_ =~ "# Autogenerated files list ends
here"
) {

- push @new_inf, $_;

- $subbing = 0;

- next;

+ # Read the contents of the inf file

+ @inf = ();

+ @new_inf = ();

+ open( FD, "<" . $inf_file ) ||

+ die "Cannot open \"" . $inf_file . "\"!";

+ @inf = (<FD>);

+ close(FD) ||

+ die "Cannot close \"" . $inf_file . "\"!";

+

+ $subbing = 0;

+ print "\n--> Updating OpensslLibCrypto.inf ...
";

+ foreach (@inf) {

+ if ( $_ =~ "# Autogenerated files list
starts
here" )
{

+ push @new_inf, $_, @cryptofilelist;

+ $subbing = 1;

+ next;

+ }

+ if ( $_ =~ "# Autogenerated files list
ends
here"
) {

+ push @new_inf, $_;

+ $subbing = 0;

+ next;

+ }

+

+ push @new_inf, $_

+ unless ($subbing);

}



- push @new_inf, $_

- unless ($subbing);

+ $new_inf_file = $inf_file . ".new";

+ open( FD, ">" . $new_inf_file ) ||

+ die $new_inf_file;

+ print( FD @new_inf ) ||

+ die $new_inf_file;

+ close(FD) ||

+ die $new_inf_file;

+ rename( $new_inf_file, $inf_file ) ||

+ die "rename $inf_file";

+ print "Done!";

}



-$new_inf_file = $inf_file . ".new";

-open( FD, ">" . $new_inf_file ) ||

- die $new_inf_file;

-print( FD @new_inf ) ||

- die $new_inf_file;

-close(FD) ||

- die $new_inf_file;

-rename( $new_inf_file, $inf_file ) ||

- die "rename $inf_file";

-print "Done!";

-

#

# Copy opensslconf.h and dso_conf.h generated from
OpenSSL
Configuration

#

diff --git a/CryptoPkg/Library/OpensslLib/uefi-
asm.conf
b/CryptoPkg/Library/OpensslLib/uefi-asm.conf
new file mode 100644
index 0000000000..55eedbf3ba
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/uefi-asm.conf
@@ -0,0 +1,15 @@
+## -*- mode: perl; -*-

+## UEFI assembly openssl configuration targets.

+

+my %targets = (

+#### UEFI

+ "UEFI-x86_64" => {

+ perlasm_scheme => "nasm",

+ # inherit_from => [ "UEFI",
asm("x86_64_asm") ],

+ inherit_from => [ "UEFI" ],

+ cpuid_asm_src => "x86_64cpuid.s",

+ aes_asm_src => "aes_core.c aes_cbc.c
vpaes-
x86_64.s
aesni-
x86_64.s
aesni-sha1-x86_64.s aesni-sha256-x86_64.s
aesni-mb-x86_64.s",

+ sha1_asm_src => "sha1-x86_64.s
sha256-x86_64.s
sha512-
x86_64.s
sha1-mb-x86_64.s sha256-mb-x86_64.s",

+ modes_asm_src => "ghash-x86_64.s",

+ },

+);

--
2.28.0.windows.1

















Re: What is a special documentation block?

Laszlo Ersek
 

On 09/25/20 03:16, Bret Barkelew via groups.io wrote:
Expect a few of these questions as I update 2000+ lines of test code that was written prior to EccCheck.

“The function headers should follow Doxygen special documentation blocks in section 2.3.5�
Doxygen doesn’t have a section 2.3.5.
Nor does the EDKII coding standard.
It probably refers to the syntax that we use for the leading comment
blocks on functions.

"/**" and "**/" for start and finish, @param[in], @param[out], @retval
VALUE, @return, and so on.

https://www.doxygen.nl/manual/commands.html

Thanks
Laszlo


Re: ECC: main function entry point in host-based unit tests

Laszlo Ersek
 

On 09/25/20 04:38, Bret Barkelew via groups.io wrote:
ERROR - EFI coding style error
ERROR - *Error code: 7001
ERROR - *There should be no use of int, unsigned, char, void, long in any .c, .h or .asl files
ERROR - *file: //home/corthon/_uefi/edk2_qemu_ci/edk2/MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/VariablePolicyUnitTest.c
ERROR - *Line number: 763
ERROR - *[main] Return type int
ERROR -
ERROR - EFI coding style error
ERROR - *Error code: 8006
ERROR - *Function name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters
ERROR - *file: //home/corthon/_uefi/edk2_qemu_ci/edk2/MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/VariablePolicyUnitTest.c
ERROR - *Line number: 2253
ERROR - *The function name [main] does not follow the rules

Currently, the host-based unit tests are using a standard C entry point:
int
main ()
"int main()" is not the standard C entry point. Two prototypes for main() are standard:

int main(void);
int main(int argc, char *argv[]);

where
- "int" may be replaced with a typedef name that's defined as "int",
- and *argv[] may be spelled as **argv too.


... Of course, this doesn't address your main point.

ECC#7001 can be suppressed perhaps if you use INT32 rather than "int".

ECC#8006 can be suppressed perhaps with a macro that expands to "main".


Another -- likely better -- idea:

(1) replace the current main() function prototype with

INT32
UnitTestMain (
IN INT32 ArgC,
IN UINT8 **ArgV
);

(2) Introduce

MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/UnitTestMain.h

such that it only declare the above prototype.

(3) Introduce

MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/UnitTestEntry.c

with the following contents:

#include "UnitTestMain.h"

int main(int argc, char **argv)
{
return UnitTestMain(argc, (UINT8 **)argv);
}

(4) List both new source files in

MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/VariablePolicyUnitTest.inf

in the [Sources] section.

(5) Add

MdeModulePkg/Library/VariablePolicyLib/VariablePolicyUnitTest/UnitTestEntry.c

to "EccCheck.IgnoreFiles" in "MdeModulePkg/MdeModulePkg.ci.yaml".

Thanks
Laszlo





That’s going to break both of these.

Another thing to override/figure out for host-based tests

- Bret







Re: [PATCH v1 1/2] MdePkg: Definitions for Extended Interrupt Flags

Sami Mujawar
 

Hi Mike,

I will send an updated patch with the suggested changes. I will also drop the IS_xxx macros.

Regards,

Sami Mujawar

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@intel.com>
Sent: 24 September 2020 11:07 PM
To: Sami Mujawar <Sami.Mujawar@arm.com>; devel@edk2.groups.io; Kinney, Michael D <michael.d.kinney@intel.com>
Cc: gaoliming@byosoft.com.cn; Liu, Zhiguang <zhiguang.liu@intel.com>; Alexei Fedorov <Alexei.Fedorov@arm.com>; Pierre Gondois <Pierre.Gondois@arm.com>; Matteo Carlini <Matteo.Carlini@arm.com>; Ben Adderson <Ben.Adderson@arm.com>; nd <nd@arm.com>
Subject: RE: [PATCH v1 1/2] MdePkg: Definitions for Extended Interrupt Flags

Hi Sami,

The set of define values looks more complex than needed for single bit field checks.

Perhaps we can simplify to just defining the bit locations and the IS_ macros check
for 0 or non-zer0 results?

#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4

#define IS_EXTENDED_INTERRUPT_CONSUMER(Flag) \
(((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK) != 0)

#define IS_EXTENDED_INTERRUPT_EDGE_TRIGGERED(Flag) \
(((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK) != 0)

Are the IS_ macros really required? I do not see those for other bit
fields in ACPI structs.

Thanks,

Mike

-----Original Message-----
From: Sami Mujawar <sami.mujawar@arm.com>
Sent: Tuesday, September 22, 2020 7:08 AM
To: devel@edk2.groups.io
Cc: Sami Mujawar <sami.mujawar@arm.com>; Kinney, Michael D <michael.d.kinney@intel.com>; gaoliming@byosoft.com.cn; Liu, Zhiguang
<zhiguang.liu@intel.com>; Alexei.Fedorov@arm.com; pierre.gondois@arm.com; Matteo.Carlini@arm.com; Ben.Adderson@arm.com; nd@arm.com
Subject: [PATCH v1 1/2] MdePkg: Definitions for Extended Interrupt Flags

Add Interrupt Vector Flag definitions for Extended Interrupt
Descriptor, and macros to test the flags.
Ref: ACPI specification 6.4.3.6

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
MdePkg/Include/IndustryStandard/Acpi10.h | 85 ++++++++++++++++++++
1 file changed, 85 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index adeb5ae8c219f31d2403fc7aa217bfb4e1e44694..fa3f0694b9cf80bf9c1a325099a970b9cf8c1426 100644
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -2,6 +2,7 @@
ACPI 1.0b definitions from the ACPI Specification, revision 1.0b

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/

@@ -377,6 +378,90 @@ typedef struct {
#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00

//
+// Interrupt Vector Flags definitions for Extended Interrupt Descriptor
+// Ref ACPI specification 6.4.3.6
+//
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER 0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_CONSUMER BIT0
+
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_LEVEL_TRIGGERED 0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_EDGE_TRIGGERED BIT1
+
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_ACTIVE_HIGH 0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_ACTIVE_LOW BIT2
+
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_EXCLUSIVE 0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARED BIT3
+
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_NOT_WAKE_CAPABLE 0
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLE BIT4> +
+/* Helper macros to test Extended Interrupt Resource descriptor flags.
+*/
+
+/** Test the Extended Interrupt flags to determine if the Device
+ is an Interrupt Consumer or Producer.
+
+ @param [in] Flag Extended Interrupt Resource descriptor flag.
+
+ @retval TRUE Device is Interrupt Consumer.
+ @retval FALSE Device is Interrupt Producer.
+*/
+#define IS_EXTENDED_INTERRUPT_CONSUMER(Flag) \
+ (((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_CONSUMER) == \
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_CONSUMER)
+
+/** Test if the Extended Interrupt is Edge or Level triggered.
+
+ @param [in] Flag Extended Interrupt Resource descriptor flag.
+
+ @retval TRUE Interrupt is Edge triggered.
+ @retval FALSE Interrupt is Level triggered.
+*/
+#define IS_EXTENDED_INTERRUPT_EDGE_TRIGGERED(Flag) \
+ (((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_EDGE_TRIGGERED) == \
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_EDGE_TRIGGERED)> +
+/** Test if the Extended Interrupt is Active Low or Active High.
+
+ @param [in] Flag Extended Interrupt Resource descriptor flag.
+
+ @retval TRUE Interrupt is Active Low.
+ @retval FALSE Interrupt is Active High.
+*/
+#define IS_EXTENDED_INTERRUPT_ACTIVE_LOW(Flag) \
+ (((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_ACTIVE_LOW) == \
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_ACTIVE_LOW)
+
+/** Test if the Extended Interrupt is Shared or Exclusive.
+
+ @param [in] Flag Extended Interrupt Resource descriptor flag.
+
+ @retval TRUE Interrupt is Shared.
+ @retval FALSE Interrupt is Exclusive.
+*/
+#define IS_EXTENDED_INTERRUPT_SHARED(Flag) \
+ (((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARED) == \
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARED)
+
+/** Test the Extended Interrupt flags to determine if the Device
+ is Wake capable or not.
+
+ @param [in] Flag Extended Interrupt Resource descriptor flag.
+
+ @retval TRUE Interrupt is Wake Capable.
+ @retval FALSE Interrupt is not Wake Capable.
+*/
+#define IS_EXTENDED_INTERRUPT_WAKE_CAPABLE(Flag) \
+ (((Flag) & EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLE) == \
+ EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLE)
+
+//
// Ensure proper structure formats
//
#pragma pack(1)
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'


[PATCH v2 1/1] BaseTools: Copy PACKED definition from MdePkg Base.h

gaoliming
 

From: gaoliming <gaoliming@byosoft.com.cn>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2938

MdePkg Acpi10.h definition depends on PACKED.
When structure PCD refers to Acpi10.h, build will fail,
because PACKED definition is missing in BaseTools BaseTypes.h.

C source tools include BaseTools BaseTypes.h. They don't include MdePkg Base.h.
When C source tools include MdePkg Acpi10.h, they also need PACKED definition.
So, add PACKED definition into BaseTools BaseTypes.h.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
---
V2: update the commit message.
BaseTools/Source/C/Include/Common/BaseTypes.h | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/BaseTools/Source/C/Include/Common/BaseTypes.h b/BaseTools/Source/C/Include/Common/BaseTypes.h
index 31d0662085a8..150980b4c0bf 100644
--- a/BaseTools/Source/C/Include/Common/BaseTypes.h
+++ b/BaseTools/Source/C/Include/Common/BaseTypes.h
@@ -57,6 +57,16 @@
#define NULL ((VOID *) 0)
#endif

+#ifdef __CC_ARM
+ //
+ // Older RVCT ARM compilers don't fully support #pragma pack and require __packed
+ // as a prefix for the structure.
+ //
+ #define PACKED __packed
+#else
+ #define PACKED
+#endif
+
//
// Support for variable length argument lists using the ANSI standard.
//
--
2.27.0.windows.1




GitPatchExtractor 1.1


[PATCH] BaseTools Build_Rule: Add the missing ASM16_FLAGS for ASM16 source file

gaoliming
 

Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
---
BaseTools/Conf/build_rule.template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
index c034869915..1395792cd6 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -515,7 +515,7 @@
"$(PP)" $(DEPS_FLAGS) $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.ii
Trim --source-code --convert-hex --trim-long -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.ii
cd $(OUTPUT_DIR)(+)${s_dir}
- "$(ASM16)" /nologo /c /omf $(INC) /Fo$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj ${d_path}(+)${s_base}.iii
+ "$(ASM16)" /nologo /c /omf $(ASM16_FLAGS) $(INC) /Fo$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj ${d_path}(+)${s_base}.iii
"$(ASMLINK)" $(ASMLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj,${dst},,,,

<Command.GCC>
--
2.27.0.windows.1