Date   

[PATCH v2 2/2] UefiPayloadPkg: Scan for Option ROMs

Marcello Sylvester Bauer <marcello.bauer@...>
 

From: Patrick Rudolph <patrick.rudolph@9elements.com>

Install the gPciPlatformProtocol to scan for Option ROMs.

For every device we probe the Option ROM and provide a pointer
to the activated BAR if found.

It's safe to assume that all ROM bars have been enumerated,
reserved in the bridge resources and are disabled by default.

Enabling them and leaving them enabled will do no harm.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
---
UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkg.fdf | 1 +
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf | 46 +++
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h | 19 +
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c | 426 ++++++++++++++++++++
6 files changed, 494 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay=
loadPkgIa32.dsc
index 12d7ffe81416..9f42d2cd6b74 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
@@ -513,6 +513,7 @@ [Components.IA32]
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+ UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#------------------------------=0D
# Build the shell=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi=
PayloadPkgIa32X64.dsc
index 9bae1daa09bb..59fc1b79457b 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
@@ -514,6 +514,7 @@ [Components.X64]
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+ UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#------------------------------=0D
# Build the shell=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayload=
Pkg.fdf
index 570a8ee7fdc1..9b188724221d 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -151,6 +151,7 @@ [FV.DXEFV]
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
INF UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+INF UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#=0D
# SCSI/ATA/IDE/DISK Support=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf b/UefiPayload=
Pkg/PciPlatformDxe/PciPlatformDxe.inf
new file mode 100644
index 000000000000..96cedad5afc3
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf
@@ -0,0 +1,46 @@
+## @file=0D
+# This driver produces gEfiPciPlatform protocol to load PCI Option ROMs=0D
+#=0D
+# Copyright (c) 2020, 9elements Agency GmbH=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PciPlatformDxe=0D
+ FILE_GUID =3D 86D58F7B-6E7C-401F-BDD4-E32E6D582AAD=
=0D
+ MODULE_TYPE =3D UEFI_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D InstallPciPlatformProtocol=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64=0D
+#=0D
+=0D
+[Sources.common]=0D
+ PciPlatformDxe.h=0D
+ PciPlatformDxe.c=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ UefiDriverEntryPoint=0D
+ UefiBootServicesTableLib=0D
+ DxeServicesTableLib=0D
+ DebugLib=0D
+ MemoryAllocationLib=0D
+ BaseMemoryLib=0D
+ DevicePathLib=0D
+ UefiLib=0D
+ HobLib=0D
+=0D
+[Protocols]=0D
+ gEfiPciPlatformProtocolGuid ## PRODUCES=0D
+ gEfiPciIoProtocolGuid ## COMSUMES=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h b/UefiPayloadPk=
g/PciPlatformDxe/PciPlatformDxe.h
new file mode 100644
index 000000000000..c40518c703f8
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h
@@ -0,0 +1,19 @@
+/** @file=0D
+ Header file for a PCI platform driver.=0D
+=0D
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+=0D
+**/=0D
+#ifndef _PCI_PLATFORM_DXE_H_=0D
+#define _PCI_PLATFORM_DXE_H_=0D
+#include <PiDxe.h>=0D
+=0D
+#include <IndustryStandard/Pci.h>=0D
+#include <IndustryStandard/Acpi.h>=0D
+#include <IndustryStandard/Pci22.h>=0D
+#include <Protocol/PciIo.h>=0D
+#include <Protocol/PciPlatform.h>=0D
+=0D
+#endif=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c b/UefiPayloadPk=
g/PciPlatformDxe/PciPlatformDxe.c
new file mode 100644
index 000000000000..65a1ba967314
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c
@@ -0,0 +1,426 @@
+/** @file=0D
+ This driver will probe for the Option Rom and provide a pointer to=0D
+ the activated BAR if found.=0D
+=0D
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+=0D
+**/=0D
+=0D
+#include "PciPlatformDxe.h"=0D
+#include <Bus/Pci/PciBusDxe/PciBus.h>=0D
+#include <Bus/Pci/PciBusDxe/PciOptionRomSupport.h>=0D
+=0D
+//=0D
+// The driver should only start on one graphics controller.=0D
+// So a global flag is used to remember that the driver is already started=
.=0D
+//=0D
+EFI_HANDLE mDriverHandle =3D NULL;=0D
+=0D
+/**=0D
+ The notification from the PCI bus enumerator to the platform that it is=
=0D
+ about to enter a certain phase during the enumeration process.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL i=
nstance.=0D
+ @param[in] HostBridge The handle of the host bridge controller.=0D
+ @param[in] Phase The phase of the PCI bus enumeration.=0D
+ @param[in] ExecPhase Defines the execution phase of the PCI chipset=
driver.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciPlatformNotify(=0D
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE HostBridge,=0D
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,=0D
+ IN EFI_PCI_EXECUTION_PHASE ExecPhase=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The notification from the PCI bus enumerator to the platform for each PC=
I=0D
+ controller at several predefined points during PCI controller initializa=
tion.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL i=
nstance.=0D
+ @param[in] HostBridge The associated PCI host bridge handle.=0D
+ @param[in] RootBridge The associated PCI root bridge handle.=0D
+ @param[in] PciAddress The address of the PCI device on the PCI bus.=
=0D
+ @param[in] Phase The phase of the PCI controller enumeration.=0D
+ @param[in] ExecPhase Defines the execution phase of the PCI chipset=
driver.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciPlatformPrepController(=0D
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE HostBridge,=0D
+ IN EFI_HANDLE RootBridge,=0D
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,=0D
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,=0D
+ IN EFI_PCI_EXECUTION_PHASE ExecPhase=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+/**=0D
+ Gets the PCI device's option ROM.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL ins=
tance.=0D
+ @param[in] PciHandle The handle of the PCI device.=0D
+ @param[out] RomImage If the call succeeds, the pointer to the pointer=
to the option ROM image.=0D
+ Otherwise, this field is undefined. The memory f=
or RomImage is allocated=0D
+ by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using t=
he EFI Boot Service AllocatePool().=0D
+ It is the caller's responsibility to free the me=
mory using the EFI Boot Service=0D
+ FreePool(), when the caller is done with the opt=
ion ROM.=0D
+ @param[out] RomSize If the call succeeds, a pointer to the size of t=
he option ROM size. Otherwise,=0D
+ this field is undefined.=0D
+=0D
+ @retval EFI_SUCCESS The option ROM was available for this dev=
ice and loaded into memory.=0D
+ @retval EFI_NOT_FOUND No option ROM was available for this devi=
ce.=0D
+ @retval EFI_OUT_OF_RESOURCES No memory was available to load the optio=
n ROM.=0D
+ @retval EFI_DEVICE_ERROR An error occurred in obtaining the option=
ROM.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciGetPciRom (=0D
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE PciHandle,=0D
+ OUT VOID **RomImage,=0D
+ OUT UINTN *RomSize=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ IN EFI_PCI_IO_PROTOCOL *PciIo;=0D
+ UINTN PciSegment;=0D
+ UINTN PciBus;=0D
+ UINTN PciDevice;=0D
+ UINTN PciFunction;=0D
+ UINTN RomBarIndex;=0D
+ UINT32 Buffer;=0D
+ UINT32 AllOnes;=0D
+ PCI_IO_DEVICE *PciIoDevice;=0D
+ UINT8 Indicator;=0D
+ UINT16 OffsetPcir;=0D
+ UINT32 RomBarOffset;=0D
+ UINT32 RomBar;=0D
+ BOOLEAN FirstCheck;=0D
+ PCI_EXPANSION_ROM_HEADER *RomHeader;=0D
+ PCI_DATA_STRUCTURE *RomPcir;=0D
+ UINT64 RomImageSize;=0D
+ UINT32 LegacyImageLength;=0D
+ UINT8 *RomInMemory;=0D
+ UINT8 CodeType;=0D
+=0D
+ if (!RomImage || !RomSize) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ *RomImage =3D NULL;=0D
+ *RomSize =3D 0;=0D
+=0D
+ Status =3D gBS->HandleProtocol (=0D
+ PciHandle,=0D
+ &gEfiPciIoProtocolGuid,=0D
+ (VOID **) &PciIo=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_INFO, "%a: Failed to open gEfiPciIoProtocolGuid\n", __=
FUNCTION__));=0D
+=0D
+ return EFI_UNSUPPORTED;=0D
+ }=0D
+ PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);=0D
+=0D
+ //=0D
+ // Get the location of the PCI device=0D
+ //=0D
+ PciIo->GetLocation (=0D
+ PciIo,=0D
+ &PciSegment,=0D
+ &PciBus,=0D
+ &PciDevice,=0D
+ &PciFunction=0D
+ );=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: Searching Option ROM on device:\n", __FUNCTION_=
_));=0D
+ DEBUG ((DEBUG_INFO, " PciSegment - %02x\n", PciSegment));=0D
+ DEBUG ((DEBUG_INFO, " PciBus - %02x\n", PciBus));=0D
+ DEBUG ((DEBUG_INFO, " PciDevice - %02x\n", PciDevice));=0D
+ DEBUG ((DEBUG_INFO, " PciFunction - %02x\n", PciFunction));=0D
+=0D
+ //=0D
+ // Offset is 0x30 if is not ppb=0D
+ //=0D
+ RomBarIndex =3D PCI_EXPANSION_ROM_BASE;=0D
+=0D
+ if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {=0D
+ //=0D
+ // If is ppb, 0x38=0D
+ //=0D
+ RomBarIndex =3D PCI_BRIDGE_ROMBAR;=0D
+ }=0D
+=0D
+ //=0D
+ // Backup BAR=0D
+ //=0D
+ Status =3D PciIo->Pci.Read (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ return Status;=0D
+ }=0D
+=0D
+ //=0D
+ // The bit0 is 0 to prevent the enabling of the Rom address decoder=0D
+ //=0D
+ AllOnes =3D 0xfffffffe;=0D
+=0D
+ Status =3D PciIo->Pci.Write (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &AllOnes=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Read back=0D
+ //=0D
+ Status =3D PciIo->Pci.Read(=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &AllOnes=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Bits [1, 10] are reserved=0D
+ //=0D
+ AllOnes &=3D 0xFFFFF800;=0D
+ if ((AllOnes =3D=3D 0) || (AllOnes =3D=3D 0xFFFFF800)) {=0D
+ DEBUG ((DEBUG_INFO, "%a: No Option ROM found\n", __FUNCTION__));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ *RomSize =3D (~AllOnes) + 1;=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: Option ROM with size %d\n", __FUNCTION__, *RomS=
ize));=0D
+=0D
+ //=0D
+ // Restore BAR and enable it=0D
+ //=0D
+ Buffer |=3D 1;=0D
+ Status =3D PciIo->Pci.Write (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Allocate memory for Rom header and PCIR=0D
+ //=0D
+ RomHeader =3D AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER));=0D
+ if (RomHeader =3D=3D NULL) {=0D
+ Status =3D EFI_OUT_OF_RESOURCES;=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ RomPcir =3D AllocatePool (sizeof (PCI_DATA_STRUCTURE));=0D
+ if (RomPcir =3D=3D NULL) {=0D
+ FreePool (RomHeader);=0D
+ Status =3D EFI_OUT_OF_RESOURCES;=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ RomBar =3D (UINT32) Buffer &~1;=0D
+=0D
+ RomBarOffset =3D RomBar;=0D
+ FirstCheck =3D TRUE;=0D
+ LegacyImageLength =3D 0;=0D
+ RomImageSize =3D 0;=0D
+=0D
+ do {=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ CopyMem(RomHeader, (VOID *)(UINTN)RomBarOffset, sizeof (PCI_EXPANSION_=
ROM_HEADER));=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: RomHeader->Signature %x\n", __FUNCTION__, Rom=
Header->Signature));=0D
+=0D
+ if (RomHeader->Signature !=3D PCI_EXPANSION_ROM_HEADER_SIGNATURE) {=0D
+=0D
+ RomBarOffset =3D RomBarOffset + 512;=0D
+ if (FirstCheck) {=0D
+ break;=0D
+ } else {=0D
+ RomImageSize =3D RomImageSize + 512;=0D
+ continue;=0D
+ }=0D
+ }=0D
+=0D
+ FirstCheck =3D FALSE;=0D
+ OffsetPcir =3D RomHeader->PcirOffset;=0D
+ //=0D
+ // If the pointer to the PCI Data Structure is invalid, no further ima=
ges can be located.=0D
+ // The PCI Data Structure must be DWORD aligned.=0D
+ //=0D
+ if (OffsetPcir =3D=3D 0 ||=0D
+ (OffsetPcir & 3) !=3D 0 ||=0D
+ RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > *RomSize=
) {=0D
+ break;=0D
+ }=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ CopyMem(RomPcir, (VOID *)(UINTN)RomBarOffset + OffsetPcir, sizeof (PCI=
_DATA_STRUCTURE));=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: RomPcir->Signature %x\n", __FUNCTION__, RomPc=
ir->Signature));=0D
+=0D
+ //=0D
+ // If a valid signature is not present in the PCI Data Structure, no f=
urther images can be located.=0D
+ //=0D
+ if (RomPcir->Signature !=3D PCI_DATA_STRUCTURE_SIGNATURE) {=0D
+ break;=0D
+ }=0D
+ if (RomImageSize + RomPcir->ImageLength * 512 > *RomSize) {=0D
+ break;=0D
+ }=0D
+ if (RomPcir->CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) {=0D
+ CodeType =3D PCI_CODE_TYPE_PCAT_IMAGE;=0D
+ LegacyImageLength =3D ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)R=
omHeader)->Size512) * 512;=0D
+ }=0D
+ Indicator =3D RomPcir->Indicator;=0D
+ RomImageSize =3D RomImageSize + RomPcir->ImageLength * 512;=0D
+ RomBarOffset =3D RomBarOffset + RomPcir->ImageLength * 512;=0D
+ } while (((Indicator & 0x80) =3D=3D 0x00) && ((RomBarOffset - RomBar) < =
*RomSize));=0D
+=0D
+ //=0D
+ // Some Legacy Cards do not report the correct ImageLength so used the m=
aximum=0D
+ // of the legacy length and the PCIR Image Length=0D
+ //=0D
+ if (CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) {=0D
+ RomImageSize =3D MAX (RomImageSize, LegacyImageLength);=0D
+ }=0D
+=0D
+ if (RomImageSize > 0) {=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ RomInMemory =3D (VOID *)(UINTN)RomBar;=0D
+ }=0D
+=0D
+ //=0D
+ // Free allocated memory=0D
+ //=0D
+ FreePool (RomHeader);=0D
+ FreePool (RomPcir);=0D
+=0D
+ if (RomImageSize > 0) {=0D
+ *RomImage =3D RomInMemory;=0D
+ *RomSize =3D RomImageSize;=0D
+ DEBUG ((DEBUG_INFO, "%a: Found Option ROM at %p, length 0x%x\n", __FUN=
CTION__,=0D
+ RomInMemory, RomImageSize));=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+ } else {=0D
+ Status =3D EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+CloseAndReturn:=0D
+ //=0D
+ // Close the I/O Abstraction(s) used to perform the supported test=0D
+ //=0D
+ gBS->CloseProtocol (=0D
+ PciHandle,=0D
+ &gEfiPciIoProtocolGuid,=0D
+ PciIo,=0D
+ PciHandle=0D
+ );=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ Retrieves the platform policy regarding enumeration.=0D
+=0D
+ The GetPlatformPolicy() function retrieves the platform policy regarding=
PCI=0D
+ enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocat=
ion Protocol=0D
+ driver can call this member function to retrieve the policy.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL ins=
tance.=0D
+ @param[out] PciPolicy The platform policy with respect to VGA and ISA =
aliasing.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER PciPolicy is NULL.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciGetPlatformPolicy (=0D
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy=0D
+ )=0D
+{=0D
+ if (PciPolicy =3D=3D NULL)=0D
+ return EFI_INVALID_PARAMETER;=0D
+=0D
+ *PciPolicy =3D 0;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol =3D {=0D
+ PciPlatformNotify,=0D
+ PciPlatformPrepController,=0D
+ PciGetPlatformPolicy,=0D
+ PciGetPciRom,=0D
+};=0D
+=0D
+/**=0D
+ The Entry Point for Option ROM driver.=0D
+=0D
+ It installs DriverBinding.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+InstallPciPlatformProtocol (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ Status =3D gBS->InstallProtocolInterface (=0D
+ &mDriverHandle,=0D
+ &gEfiPciPlatformProtocolGuid,=0D
+ EFI_NATIVE_INTERFACE,=0D
+ &mPciPlatformProtocol=0D
+ );=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.28.0


[PATCH v2 1/2] MdeModulePkg: Fix OptionROM scanning

Marcello Sylvester Bauer <marcello.bauer@...>
 

From: Patrick Rudolph <patrick.rudolph@9elements.com>

The Option ROM scanner can't work as enumeration was done by the
first stage bootloader. Running it will disable the ability of the
PCIPlatform code to scan for ROMs.

Required for the following patch that enables custom Option ROM
scanning using gPciPlatformProtocol.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod=
ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 6c68a97d4e46..7420f0079f7d 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -2530,10 +2530,12 @@ PciEnumeratorLight (
//=0D
RemoveRejectedPciDevices (RootBridgeDev->Handle, RootBridgeDev);=0D
=0D
- //=0D
- // Process option rom light=0D
- //=0D
- ProcessOptionRomLight (RootBridgeDev);=0D
+ if (!PcdGetBool (PcdPciDisableBusEnumeration)) {=0D
+ //=0D
+ // Process option rom light=0D
+ //=0D
+ ProcessOptionRomLight (RootBridgeDev);=0D
+ }=0D
=0D
//=0D
// Determine attributes for all devices under this root bridge=0D
--=20
2.28.0


[PATCH v2 0/2] Add support for scanning Option ROMs

Marcello Sylvester Bauer <marcello.bauer@...>
 

Fix Option ROM enumeration and support scanning.

v2:
* add correct Maintainer and Reviewer to Cc
* PciPlatformDxe:
- Update description
- add function description

Branch: https://github.com/9elements/edk2-1/tree/UefiPayloadPkg-Option_ROMs
PR: https://github.com/tianocore/edk2/pull/926

Patrick Rudolph (2):
MdeModulePkg: Fix OptionROM scanning
UefiPayloadPkg: Scan for Option ROMs

UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkg.fdf | 1 +
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf | 46 +++
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h | 19 +
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 10 +-
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c | 426 ++++++++++++++++++++
7 files changed, 500 insertions(+), 4 deletions(-)
create mode 100644 UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf
create mode 100644 UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h
create mode 100644 UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c

--
2.28.0


Re: [PATCH v1 1/1] Platform/RaspberryPi/ConfigDxe: Fix JTAG Pinout for Pi3/4

Pete Batard
 

Copying Andrei on this, as the existing JTAG pinout is not technically incorrect, since GPIO pin 4 can be used for TDI in ALT5 mode, and we are using the relevant ALT mode in the existing code. See https://sysprogs.com/VisualKernel/tutorials/raspberry/jtagsetup/

As far as I'm concerned, I think it makes sense to use the same ALT mode and have all the JTAG pins grouped, but I'd like to confirm whether we deliberately chose not to use GPIO 26 in order to leave it available for some other purpose, before I approve this patch.

If Andrei says he's okay with it, then I see no objection to this change.

Regards,

/Pete

On 2020.09.14 22:32, Jeff Booher-Kaeding wrote:
Updated the pinout to match the Pi4 datasheet, tested with the RPi4, Pi3 Datasheet has same pinout.
Signed-off-by: Jeff Booher-Kaeding <Jeff.booher-kaeding@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Pete Batard <pete@akeo.ie>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index ac1004fe1836..6e793efb8227 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -502,7 +502,7 @@ ApplyVariables (
* 1 VREF N/A 1
* 3 nTRST GPIO22 ALT4 15
* 4 GND N/A 9
- * 5 TDI GPIO4 ALT5 7
+ * 5 TDI GPIO26 ALT4 37
* 7 TMS GPIO27 ALT4 13
* 9 TCK GPIO25 ALT4 22
* 11 RTCK GPIO23 ALT4 16
@@ -510,14 +510,14 @@ ApplyVariables (
*/
if (PcdGet32 (PcdDebugEnableJTAG)) {
GpioPinFuncSet (22, GPIO_FSEL_ALT4);
- GpioPinFuncSet (4, GPIO_FSEL_ALT5);
+ GpioPinFuncSet (26, GPIO_FSEL_ALT4);
GpioPinFuncSet (27, GPIO_FSEL_ALT4);
GpioPinFuncSet (25, GPIO_FSEL_ALT4);
GpioPinFuncSet (23, GPIO_FSEL_ALT4);
GpioPinFuncSet (24, GPIO_FSEL_ALT4);
} else {
GpioPinFuncSet (22, GPIO_FSEL_INPUT);
- GpioPinFuncSet (4, GPIO_FSEL_INPUT);
+ GpioPinFuncSet (26, GPIO_FSEL_INPUT);
GpioPinFuncSet (27, GPIO_FSEL_INPUT);
GpioPinFuncSet (25, GPIO_FSEL_INPUT);
GpioPinFuncSet (23, GPIO_FSEL_INPUT);


[edk2-platforms 3/4] Silicon/NXP: Implement USB Errata

Meenakshi Aggarwal <meenakshi.aggarwal@...>
 

Implement USB errata A009008, A009798, A008997, A009007
Make USB,SEC and SATA snoopable

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 1 +
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
Silicon/NXP/Chassis2/Include/Chassis.h | 112 +++++++++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++++
Silicon/NXP/LS1046A/Include/Soc.h | 2 +
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 +++++++++++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 +++++++++
11 files changed, 493 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3a568c0437e7..90dce69fd472 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -30,6 +30,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320

[PcdsFixedAtBuild.common]
# Pcds for PCI Express
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index db110553605f..4e1d6a7ae7a2 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -34,6 +34,7 @@ [PcdsFixedAtBuild.common]

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE

################################################################################
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..d64286b199c6 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -28,6 +28,8 @@ [LibraryClasses]

[Sources.common]
ChassisLib.c
+ Erratum.c

[FeaturePcd]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
index 01ed0f6592d2..e2336bb18f29 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -14,6 +14,7 @@ [Defines]
LIBRARY_CLASS = SocLib

[Packages]
+ ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1046A/LS1046A.dec
@@ -25,3 +26,4 @@ [LibraryClasses]

[Sources.common]
SocLib.c
+
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 7e8bf224884b..f8fa7ed67596 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -11,6 +11,7 @@
#include <Uefi.h>

#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000

#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
@@ -26,6 +27,10 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SACR_PAGESIZE_MASK 0x00010000

+#define USB_PHY1_BASE_ADDRESS 0x084F0000
+#define USB_PHY2_BASE_ADDRESS 0x08500000
+#define USB_PHY3_BASE_ADDRESS 0x08510000
+
/**
The Device Configuration Unit provides general purpose configuration and
status for the device. These registers only support 32-bit accesses.
@@ -45,4 +50,111 @@ typedef struct {
} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
#pragma pack()

+/* Supplemental Configuration Unit (SCFG) */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfgCr;
+#define SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
+ **/
+#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
+ **/
+#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define SCFG_USBPWRFAULT_SHARED 0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
+
#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
new file mode 100644
index 000000000000..0231ef0a283d
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
@@ -0,0 +1,23 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for Erratas
+*
+* Copyright 2020 NXP
+*
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef ERRATUM_H__
+#define ERRATUM_H__
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+
+#endif
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index 89992a4b6fd5..c99368b4733d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -13,6 +13,48 @@
#include <Chassis.h>

/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
Read Dcfg register

@param Address The MMIO register to read.
@@ -48,4 +90,24 @@ ChassisInit (
VOID
);

+VOID
+ErratumA009008 (
+ VOID
+ );
+
+VOID
+ErratumA009798 (
+ VOID
+ );
+
+VOID
+ErratumA008997 (
+ VOID
+ );
+
+VOID
+ErratumA009007 (
+ VOID
+ );
+
#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
index 84f433d5cb94..e1d97e531263 100644
--- a/Silicon/NXP/LS1046A/Include/Soc.h
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -25,6 +25,7 @@
#define LS1046A_QSPI0_SIZE (SIZE_512MB)

#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS

/**
Reset Control Word (RCW) Bits
@@ -59,5 +60,6 @@ Bit(s) | Field Name | Description | Notes/comments
#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6

typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;

#endif // SOC_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index 91b19f832f00..e6410a53f480 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -15,6 +15,69 @@
#include <Library/SerialPortLib.h>

/**
+ Or Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgOr32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Or32 (Address, Value);
+}
+
+/**
+ Read Scfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+ScfgRead32 (
+ IN UINTN Address
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Read32 (Address);
+}
+
+/**
+ Write Scfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+ScfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS *ScfgOps;
+
+ ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian));
+
+ return ScfgOps->Write32 (Address, Value);
+}
+
+/**
Read Dcfg register

@param Address The MMIO register to read.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
new file mode 100644
index 000000000000..1806975ec8f5
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
@@ -0,0 +1,159 @@
+/** @file
+ This file containa all erratas need to be applied on different SoCs.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "Erratum.h"
+
+/*
+* A-009008: USB High Speed (HS) eye height adjustment
+* Affects: USB
+* Description: USB HS eye diagram fails with the default value at many corners, particularly at a high
+* temperature (105°C).
+* Impact: USB HS eye diagram may fail using the default value.
+*/
+VOID
+ErratumA009008 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ Value &= ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+
+ return;
+}
+
+/*
+* A-009798: USB high speed squelch threshold adjustment
+* Affects: USB
+* Description: The default setting for USB high speed squelch threshold results in a threshold close to or
+* lower than 100mV. This leads to a receiver compliance test failure for a 100mV threshold.
+* Impact: If the errata is not applied, only the USB high speed receiver sensitivity compliance test fails,
+* however USB data continues to transfer.
+*/
+VOID
+ErratumA009798 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
+
+ return;
+}
+
+/*
+* A-008997: USB3 LFPS peak-to-peak differential output voltage adjustment settings
+* Affects: USB
+* Description: Low Frequency Periodic Signaling (LFPS) peak-to-peak differential output voltage test
+* compliance fails using default transmitter settings. Software is required to change the
+* transmitter signal swings to pass compliance tests.
+* Impact: LFPS peak-to-peak differential output voltage compliance test fails.
+*/
+VOID
+ErratumA008997 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg = (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS;
+
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+ Value = ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
+ Value &= ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << 9));
+
+ return;
+}
+
+/*
+* A-009007: USB3PHY observing intermittent failure in receive compliance tests
+* at higher jitter frequency using default register values
+*
+* Affects: USB
+*
+* Description: Receive compliance tests may fail intermittently at high jitter
+* frequencies using default register values.
+*
+* Impact: Receive compliance test fails at default register setting.
+*/
+
+VOID
+ConfigUsbLane0 (
+ IN UINTN UsbPhy
+ )
+{
+ UINTN RegAddress;
+
+ RegAddress = UsbPhy + USB_PHY_RX_OVRD_IN_HI;
+
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
+
+ return;
+}
+
+VOID
+ErratumA009007 (
+ VOID
+ )
+{
+ UINTN UsbPhy;
+
+ UsbPhy = USB_PHY1_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY2_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy = USB_PHY3_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ return;
+}
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
index 3b15aee6ecae..80342d7230e4 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -11,6 +11,8 @@
#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
#include <Library/SocLib.h>
+
+#include <Library/SocLib.h>
#include <Soc.h>

/**
@@ -65,6 +67,47 @@ SocGetClock (
}

/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+STATIC
+VOID
+ConfigScfgMux (VOID)
+{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+
+ ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+STATIC
+VOID
+ApplyErrata (
+ VOID
+ )
+{
+ ErratumA009008 ();
+ ErratumA009798 ();
+ ErratumA008997 ();
+ ErratumA009007 ();
+}
+
+
+
+/**
Function to initialize SoC specific constructs
**/
VOID
@@ -72,7 +115,30 @@ SocInit (
VOID
)
{
+ LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
+
+ Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
+
+ /* Make SEC, SATA and USB reads and writes snoopable */
+ ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
+ SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
+ SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
+ SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
+ SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
+ SCFG_SNPCNFGCR_SATAWRSNP);
+
+ ApplyErrata ();
ChassisInit ();

+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
--
1.9.1


[edk2-platforms 4/4] LS1046aFrwy: Enable USB support for LS1046AFRWY board.

Meenakshi Aggarwal <meenakshi.aggarwal@...>
 

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 ++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 +++++++++++++
3 files changed, 18 insertions(+)
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf

diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 4e1d6a7ae7a2..7004533ed5f1 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -31,6 +31,9 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000

+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x2F00000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x100000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|3

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
old mode 100644
new mode 100755
index 3f29dadd5d1d..266fdbd2b4d3
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -43,4 +43,6 @@ [Components.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
}

+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
old mode 100644
new mode 100755
index 24af547729c7..34c4e5a02516
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -120,6 +120,19 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# UEFI application (Shell Embedded Boot Loader)
#
--
1.9.1


[edk2-platforms 2/4] Platform/NXP/LS1046aFrwyPkg: GPIO mux changes for USB

Meenakshi Aggarwal <meenakshi.aggarwal@...>
 

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/NxpQoriqLs.dec | 8 ++++++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 5 +++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 2 ++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
.../Library/ArmPlatformLib/ArmPlatformLib.c | 17 +++++++++++++++++
5 files changed, 33 insertions(+)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 0c3608696569..3a568c0437e7 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -29,6 +29,7 @@ [PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317
gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319

[PcdsFixedAtBuild.common]
# Pcds for PCI Express
@@ -48,6 +49,13 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000351
gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000352

+ #
+ # Pcds for Gpio
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0|UINT32|0x00000355
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0|UINT64|0x00000356
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0|UINT64|0x00000357
+
[PcdsDynamic.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600
gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index dbe7f408fce9..db110553605f 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -27,9 +27,14 @@ [PcdsDynamicDefault.common]

[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController|0x04
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress|0x02300000
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset|0x10000
+

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|TRUE

################################################################################
#
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index fc600de01d74..21c87df73220 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -103,6 +103,8 @@ [LibraryClasses.common]
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf

+ GpioLib|Silicon/NXP/Library/GpioLib/GpioLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7802696bf39b..2e755842a714 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -25,6 +25,7 @@ [Packages]
[LibraryClasses]
ArmLib
DebugLib
+ GpioLib
SocLib

[Sources.common]
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index e1f20da09337..d467992a3e47 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,11 +8,14 @@

#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/GpioLib.h>
#include <Library/SocLib.h>

#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>

+#define USB2_MUX_SEL_GPIO 23
+
ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
@@ -89,6 +92,19 @@ NxpPlatformGetClock(
}

/**
+ FRWY-LS1046A GPIO 23 use for USB2
+ mux seclection
+**/
+STATIC VOID MuxSelectUsb2 (VOID)
+{
+
+ SetDir (GPIO3, USB2_MUX_SEL_GPIO, OUTPUT);
+ SetData (GPIO3, USB2_MUX_SEL_GPIO, HIGH);
+
+ return;
+}
+
+/**
Initialize controllers that must setup in the normal world

This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
@@ -101,6 +117,7 @@ ArmPlatformInitialize (
)
{
SocInit ();
+ MuxSelectUsb2 ();

return EFI_SUCCESS;
}
--
1.9.1


[edk2-platforms 1/4] Silicon/NXP: Add GPIO driver support.

Meenakshi Aggarwal <meenakshi.aggarwal@...>
 

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 +++++
Silicon/NXP/Include/Library/GpioLib.h | 110 +++++++++++++++
Silicon/NXP/Library/GpioLib/GpioLib.c | 242 ++++++++++++++++++++++++++++++++
3 files changed, 391 insertions(+)
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c

diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/GpioLib/GpioLib.inf
new file mode 100644
index 000000000000..7878d1d03db2
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = GpioLib
+ FILE_GUID = addec2b8-d2e0-43c0-a277-41a8d42f3f4f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioLib
+
+[Sources.common]
+ GpioLib.c
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ BaseLib
+ IoAccessLib
+ IoLib
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian
diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Library/GpioLib.h
new file mode 100644
index 000000000000..5821806226ee
--- /dev/null
+++ b/Silicon/NXP/Include/Library/GpioLib.h
@@ -0,0 +1,110 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef GPIO_H__
+#define GPIO_H__
+
+#include <Uefi.h>
+
+/* enum for GPIO number */
+typedef enum _GPIO_BLOCK {
+ GPIO1,
+ GPIO2,
+ GPIO3,
+ GPIO4,
+ GPIO_MAX
+} GPIO_BLOCK;
+
+/* enum for GPIO direction */
+typedef enum _GPIO_DIRECTION {
+ INPUT,
+ OUTPUT
+} GPIO_DIRECTION;
+
+/* enum for GPIO state */
+typedef enum _GPIO_STATE {
+ LOW,
+ HIGH
+} GPIO_VAL;
+
+/**
+ SetDir Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ );
+
+/**
+ GetDir Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+ /**
+ GetData Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ );
+
+/**
+ SetData Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+SetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ );
+
+/**
+ SetOpenDrain Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ );
+
+#endif
diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/GpioLib/GpioLib.c
new file mode 100644
index 000000000000..33cc45c2152b
--- /dev/null
+++ b/Silicon/NXP/Library/GpioLib/GpioLib.c
@@ -0,0 +1,242 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+STATIC MMIO_OPERATIONS *mGpioOps;
+
+/* Structure for GPIO Regsters */
+typedef struct GpioRegs {
+ UINT32 GpDir;
+ UINT32 GpOdr;
+ UINT32 GpData;
+ UINT32 GpIer;
+ UINT32 GpImr;
+ UINT32 GpIcr;
+} GPIO_REGS;
+
+/**
+ GetBaseAddr GPIO controller Base Address
+
+ @param[in] Id GPIO controller number
+
+ @retval GPIO controller Base Address, if found
+ @retval NULL, if not a valid controller number
+
+ **/
+STATIC
+VOID *
+GetBaseAddr (
+ IN UINT8 Id
+ )
+{
+
+ UINTN GpioBaseAddr;
+ UINTN MaxGpioController;
+
+ mGpioOps = GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndian));
+
+ MaxGpioController = PcdGet32 (PcdNumGpioController);
+
+ if (Id < MaxGpioController) {
+ GpioBaseAddr = PcdGet64 (PcdGpioModuleBaseAddress) +
+ (Id * PcdGet64 (PcdGpioControllerOffset));
+ return (VOID *) GpioBaseAddr;
+ }
+ else {
+ DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d-%d",
+ Id, GPIO1, MaxGpioController));
+ return NULL;
+ }
+}
+
+/**
+ GetBitMask: Return Bit Mask
+
+ @param[in] Bit Bit to create bitmask
+ @retval Bitmask
+
+ **/
+
+STATIC
+UINT32
+GetBitMask (
+ IN UINT32 Bit
+ )
+{
+
+ if (!FeaturePcdGet (PcdGpioControllerBigEndian)) {
+ return (1 << Bit);
+ } else {
+ return (1 << (31 - Bit));
+ }
+}
+
+
+/**
+ SetDir Set GPIO direction as INPUT or OUTPUT
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Dir GPIO Direction as INPUT or OUTPUT
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Dir
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
+ UINT32 Value;
+
+ Regs = GetBaseAddr(Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
+
+ if (Dir) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value | BitMask));
+ }
+ else {
+ mGpioOps->Write32 ((UINTN)&Regs->GpDir, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GetDir Retrieve GPIO direction
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO Direction as INPUT or OUTPUT
+ **/
+UINT32
+GetDir (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 BitMask;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
+
+ return (Value & BitMask);
+}
+
+/**
+ GetData Retrieve GPIO Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+
+ @retval GPIO value as HIGH or LOW
+ **/
+UINT32
+GetData (
+ IN UINT8 Id,
+ IN UINT32 Bit
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 Value;
+ UINT32 BitMask;
+
+ Regs = (VOID *)GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
+
+ if (Value & BitMask) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/**
+ SetData Set GPIO data Value
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] Data GPIO data value to set
+
+ @retval GPIO value as HIGH or LOW
+ **/
+EFI_STATUS
+SetData (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN Data
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
+ UINT32 Value;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
+
+ if (Data) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value | BitMask));
+ } else {
+ mGpioOps->Write32 ((UINTN)&Regs->GpData, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ SetOpenDrain Set GPIO as Open drain
+
+ @param[in] Id GPIO controller number
+ @param[in] Bit GPIO number
+ @param[in] OpenDrain Set as open drain
+
+ @retval EFI_SUCCESS
+ **/
+EFI_STATUS
+SetOpenDrain (
+ IN UINT8 Id,
+ IN UINT32 Bit,
+ IN BOOLEAN OpenDrain
+ )
+{
+ GPIO_REGS *Regs;
+ UINT32 BitMask;
+ UINT32 Value;
+
+ Regs = GetBaseAddr (Id);
+ BitMask = GetBitMask(Bit);
+
+ Value = mGpioOps->Read32 ((UINTN)&Regs->GpOdr);
+ if (OpenDrain) {
+ mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value | BitMask));
+ }
+ else {
+ mGpioOps->Write32 ((UINTN)&Regs->GpOdr, (Value & (~BitMask)));
+ }
+
+ return EFI_SUCCESS;
+}
--
1.9.1


[edk2-platforms 0/4] Enable USB support on LS1046aFrwy board

Meenakshi Aggarwal <meenakshi.aggarwal@...>
 

This patch set adds GPIO Library.
Gpio Library is required to set muxing to enable USB controller.

Meenakshi Aggarwal (4):
Silicon/NXP: Add GPIO driver support.
Platform/NXP/LS1046aFrwyPkg: GPIO mux changes for USB
Silicon/NXP: Implement USB Errata
LS1046aFrwy: Enable USB support for LS1046AFRWY board.

Silicon/NXP/NxpQoriqLs.dec | 9 +
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 9 +
Silicon/NXP/NxpQoriqLs.dsc.inc | 2 +
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 2 +
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 2 +
Silicon/NXP/Library/GpioLib/GpioLib.inf | 39 ++++
Silicon/NXP/Chassis2/Include/Chassis.h | 112 ++++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 ++
Silicon/NXP/Include/Library/ChassisLib.h | 62 ++++++
Silicon/NXP/Include/Library/GpioLib.h | 110 ++++++++++
Silicon/NXP/LS1046A/Include/Soc.h | 2 +
.../Library/ArmPlatformLib/ArmPlatformLib.c | 17 ++
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 159 ++++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 66 ++++++
Silicon/NXP/Library/GpioLib/GpioLib.c | 242 +++++++++++++++++++++
19 files changed, 935 insertions(+)
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
mode change 100644 => 100755 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c

--
1.9.1


Re: [PATCH] ArmPkg/ArmPciCpuIo2Dxe: Correct pci io memmap address

Ard Biesheuvel
 

On 9/15/20 11:35 AM, LiuYu wrote:
Since the device addresss has been translated in PciRootBridgeIo.c
so shuldn't translate it twice in ArmPciCpuIo2Dxe.c
Signed-off-by: LiuYu <liuyu@greatwall.com.cn>
Nack. The I/O translation in the I/O domain and the mapping of the I/O window in the physical memory space are two different translations, and they both need to be applied.

PciRootBridgeIo.c deals with the former, whereas this driver deals with the latter.


---
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
index d8625e1593..8c46a2778b 100644
--- a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
+++ b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
@@ -399,7 +399,6 @@ CpuIoServiceRead (
return Status;
}
- Address += PcdGet64 (PcdPciIoTranslation);
//
// Select loop based on the width of the transfer
@@ -485,7 +484,6 @@ CpuIoServiceWrite (
return Status;
}
- Address += PcdGet64 (PcdPciIoTranslation);
//
// Select loop based on the width of the transfer


[PATCH] ArmPkg/ArmPciCpuIo2Dxe: Correct pci io memmap address

Yu Liu
 

Since the device addresss has been translated in PciRootBridgeIo.c
so shuldn't translate it twice in ArmPciCpuIo2Dxe.c

Signed-off-by: LiuYu <liuyu@greatwall.com.cn>
---
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c | 2 --
1 file changed, 2 deletions(-)

diff --git a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/ArmPkg/Dr=
ivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
index d8625e1593..8c46a2778b 100644
--- a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
+++ b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
@@ -399,7 +399,6 @@ CpuIoServiceRead (
return Status;
}
=20
- Address +=3D PcdGet64 (PcdPciIoTranslation);
=20
//
// Select loop based on the width of the transfer
@@ -485,7 +484,6 @@ CpuIoServiceWrite (
return Status;
}
=20
- Address +=3D PcdGet64 (PcdPciIoTranslation);
=20
//
// Select loop based on the width of the transfer
--=20
2.20.1


Re: [PATCH 05/22] .mailmap: add entry for Zhichao Gao

Gao, Zhichao
 

Acked-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: Laszlo Ersek <lersek@redhat.com>
Sent: Tuesday, September 8, 2020 3:31 AM
To: edk2-devel-groups-io <devel@edk2.groups.io>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>; Gao, Zhichao
<zhichao.gao@intel.com>
Subject: [PATCH 05/22] .mailmap: add entry for Zhichao Gao

... for git-shortlog purposes.

Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
.mailmap | 1 +
1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index 8ed1d77c9220..a7e2fea7419b 100644
--- a/.mailmap
+++ b/.mailmap
@@ -77,3 +77,4 @@ Vladimir Olovyannikov
<vladimir.olovyannikov@broadcom.com> Vladimir Olovyannikov Yonghong Zhu
<yonghong.zhu@intel.com> Yonghong Zhu <yonghong.zhu@intel.com>
<yzhu52@Edk2> Yu-Chen Lin <yuchenlin@synology.com>
+Zhichao Gao <zhichao.gao@intel.com>
--
2.19.1.3.g30247aa5d201


Re: [PATCH v2 0/3] CryptoPkg/BaseCryptLib: Add EVP (Envelope) Digest interface

Laszlo Ersek
 

Hello Christopher,

On 09/15/20 04:54, Zurcher, Christopher J wrote:

I have to send another patch anyway to add a file in my commit (missed the second copy of CryptEvpMdNull.c in the NullLib folder).
Thank you for the updates. I'll only be capable of a quick skim of the
first patch in the series. It seems you're planning a v3, so I prefer to
check that version.

Thanks
Laszlo


Re: [PATCH 00/22] .mailmap: add mappings after edk2-stable202008

Laszlo Ersek
 

Hi Andrew, Leif,

On 09/07/20 21:30, Laszlo Ersek wrote:
Repo: https://pagure.io/lersek/edk2.git
Branch: update_mailmap_edk2stable202008

If you (singular) are on the CC list of this email (and you are not
Phil), then the output of the following command:

$ git shortlog edk2-stable201905..edk2-stable202008

prints something dubious in relation to you. For example, you could be
listed under two different names, or your name might not appear to be
your real name (per "Developer Certificate of Origin" in "ReadMe.rst").

The patch that you receive in addition to this blurb seeks to solve that
particular issue. Please (a) run the above git-shortlog command and save
the output, (b) apply (or fetch) this series, (c) re-run the
git-shortlog command, (d) if you are OK with the differences related to
your name, please respond with an Acked-by or Reviewed-by to the
specific patch.

Importantly, cross-domain mappings are NOT introduced, so if there's no
feedback from you in a week or so, we can merge the patch anyway (with
steward approval).
I posted this series more than a week ago -- I've only received sporadic
feedback since then. I think I should go ahead with merging this series.
Or do you suggest we wait until Mike can check?

Thanks
Laszlo


Thanks,
Laszlo

Cc: Ching JenX Cheng <ching.jenx.cheng@intel.com>
Cc: Derek Lin <derek.lin2@hpe.com>
Cc: Eric Jin <eric.jin@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Kun Qin <kuqin@microsoft.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Maggie Chu <maggie.chu@intel.com>
Cc: Marc W Chen <marc.w.chen@intel.com>
Cc: Matt DeVillier <matt.devillier@gmail.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Cc: Steven Shi <steven.shi@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Cc: XiaoyuX Lu <xiaoyux.lu@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Laszlo Ersek (22):
.mailmap: add entry for Marc W Chen
.mailmap: add entry for Ching JenX Cheng
.mailmap: add entries for Maggie Chu
.mailmap: add entries for Guo Dong
.mailmap: add entry for Zhichao Gao
.mailmap: add entries for Guomin Jiang
.mailmap: add entry for Eric Jin
.mailmap: add entry for Michael D Kinney
.mailmap: add entry for Tom Lendacky
.mailmap: add entry for Derek Lin
.mailmap: add entry for Zhiguang Liu
.mailmap: add entry for XiaoyuX Lu
.mailmap: add entry for Steven Shi
.mailmap: add entry for Jiaxin Wu
.mailmap: add entry for Wei6 Xu
.mailmap: add entry for Qi Zhang
.mailmap: add entry for Matt DeVillier
.mailmap: add entry for Paul Grimes
.mailmap: add (another) entry for Vladimir Olovyannikov
.mailmap: add (another) entry for Liming Gao
.mailmap: add entry for Kun Qin
.mailmap: add entries for Rebecca Cran

.mailmap | 26 ++++++++++++++++++++
1 file changed, 26 insertions(+)


TianoCore Bug Triage - APAC / NAMO - Tue, 09/15/2020 6:30pm-7:30pm #cal-reminder

devel@edk2.groups.io Calendar <devel@...>
 

Reminder: TianoCore Bug Triage - APAC / NAMO

When: Tuesday, 15 September 2020, 6:30pm to 7:30pm, (GMT-07:00) America/Los Angeles

Where:https://bluejeans.com/889357567?src=join_info

View Event

Organizer: Brian Richardson brian.richardson@...

Description:

https://www.tianocore.org/bug-triage

 

Meeting URL

https://bluejeans.com/889357567?src=join_info

 

Meeting ID

889 357 567

 

Want to dial in from a phone?

Dial one of the following numbers:

+1.408.740.7256 (US (San Jose))

+1.408.317.9253 (US (Primary, San Jose))

 

(see all numbers - https://www.bluejeans.com/numbers)

Enter the meeting ID and passcode followed by #


[PATCH 2/2] SecurityPkg/PeiTpmMeasurementLib: remove gEfiTpmDeviceSelectedGuid

Qi Zhang
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2963

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
---
.../Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.inf | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/SecurityPkg/Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.=
inf b/SecurityPkg/Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.inf
index 6625d0fd01..be5e344d7f 100644
--- a/SecurityPkg/Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.inf
+++ b/SecurityPkg/Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.inf
@@ -46,5 +46,4 @@
gEdkiiTcgPpiGuid ## =
CONSUMES=0D
=0D
[Depex]=0D
- gEfiPeiMasterBootModePpiGuid AND=0D
- gEfiTpmDeviceSelectedGuid=0D
+ gEfiPeiMasterBootModePpiGuid=0D
--=20
2.26.2.windows.1


[PATCH 1/2] IntelFsp2WrapperPkg: remove gPeiTpmInitializationDonePpiGuid from Depex

Qi Zhang
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2963

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
---
IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 3 +--
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index c3578397b6..00166e56a0 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -73,5 +73,4 @@
gEfiPeiFirmwareVolumeInfoMeasurementExcludedPpiGuid ## PRODUCES

[Depex]
- gEfiPeiMasterBootModePpiGuid AND
- gPeiTpmInitializationDonePpiGuid
+ gEfiPeiMasterBootModePpiGuid
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index 884514747f..aeeca58d6d 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
@@ -77,5 +77,4 @@
FspsWrapperPeim.c

[Depex]
- gEfiPeiMemoryDiscoveredPpiGuid AND
- gPeiTpmInitializationDonePpiGuid
+ gEfiPeiMemoryDiscoveredPpiGuid
--
2.26.2.windows.1


[PATCH 0/2] remove TPM related ppi from Depex for Fsp wrapper PEIM driver

Qi Zhang
 

Some open board are TPM disabled. So the boot may hang because
these PPIs can't arrive. And gEdkiiTcgPpiGuid will be notified where
it is used. So we need to remove these PPIs from Depex for Fsp wrapper
PEI and PeiTpmMeasurementLib.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>

Qi Zhang (2):
IntelFsp2WrapperPkg: remove gPeiTpmInitializationDonePpiGuid from
Depex
SecurityPkg/PeiTpmMeasurementLib: remove gEfiTpmDeviceSelectedGuid

IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 3 +--
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 +--
.../Library/PeiTpmMeasurementLib/PeiTpmMeasurementLib.inf | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)

--
2.26.2.windows.1


Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Yao, Jiewen
 

Thanks Abner.

Understood now. Yes, we need follow the regulation as always.

 

I look forward to seeing the DMTF public repo. :-)

 

Thank you

Yao Jiewen

 

From: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>
Sent: Tuesday, September 15, 2020 1:39 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@...>; rfc@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; Fu, Siyuan <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: RE: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

Sure Jiewen, we plan to talk about this on Tianocore design meeting recently. But I may not provide the reference here because it may against to the Redfish working group regulations.

I had requested to public this repo two years ago, however both WG chair and I had no follow up on this. I already restarted the conversation with him… just now.

 

For now, only the implementation of UEFI spec 29.7.2 (Redfish instance),  29.7.3 and 31.1 will be sent to community for review.

 

Thanks

Abner

 

 

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Yao, Jiewen
Sent: Tuesday, September 15, 2020 12:42 PM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; rfc@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; Fu, Siyuan <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

HI Abner

If it is DMTF private repo, should we discuss it in EDKII ?

 

Do we have a public reference somewhere else?

 

Thank you

Yao Jiewen

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner Chang
Sent: Tuesday, September 15, 2020 12:23 PM
To: rfc@edk2.groups.io; devel@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; Fu, Siyuan <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

Hmm. You probably have to join dmtf as a member. That repo is private for members now, not public yet.

 


From: rfc@edk2.groups.io <rfc@edk2.groups.io> on behalf of Bret Barkelew via groups.io <bret.barkelew@...>
Sent: Tuesday, September 15, 2020 12:19:29 PM
To: Chang, Abner (HPS SW/FW Technologist) <
abner.chang@...>; devel@edk2.groups.io <devel@edk2.groups.io>; rfc@edk2.groups.io <rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <
nickle.wang@...>; Chen, Aaron <aaron.chen@...>; siyuan.fu@... <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

That link didn’t work for me.

- Bret

From: Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:59 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Bret Barkelew<mailto:Bret.Barkelew@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] RE: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

No, EFI REST JSON Structure DXE Driver (UEF spec section 29.7.3) is a centralized manager to manage “EFI Redfish JSON resource to C structure Converter libraries/drivers”  for converting Redfish resource in the specific schema from JSON format to the C structure or vice versa.
EFI REST JSON Structure DXE Driver itself doesn’t use JSON library, however “EFI Redfish JSON resource to C structure Converter libraries/drivers” do use open source jansson library to parse JSON payload. Furthermore, “EFI Redfish JSON resource to C structure Converter libraries/drivers” are generated by tool based on the published Redfish schemas. https://github.com/DMTF/Redfish-Schema-C-Struct-Generator<https://urldefense.proofpoint.com/v2/url?u=https-3A__nam06.safelinks.protection.outlook.com_-3Furl-3Dhttps-253A-252F-252Fgithub.com-252FDMTF-252FRedfish-2DSchema-2DC-2DStruct-2DGenerator-26data-3D02-257C01-257Cbret.barkelew-2540microsoft.com-257C1b8115973f364cea229008d8592bc486-257C72f988bf86f141af91ab2d7cd011db47-257C1-257C0-257C637357391811797643-26sdata-3DLdHAPly4oeVhyC6Xk7p0G0r1y8qVxrLfGZrN9EW5WpE-253D-26reserved-3D0&d=DwIF-g&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=goBsQ2eLlP7qVkOJAy8TPlQ0B6NFvNm4rP58u6ASQxc&s=j2rR7JmY2HjCtfOOe9ChSWCNKYseOJX2T-91Z3miShA&e= >

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Bret Barkelew via groups.io
Sent: Tuesday, September 15, 2020 11:41 AM
To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; devel@edk2.groups.io; rfc@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; siyuan.fu@...; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

JSON Structure would probably be worth discussing. I know that there are other places I’ve seen JSON used and it may end up that we want common business logic (similar to using Oniguruma for regex). Do you parse/format JSON in that one?

- Bret

From: Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:33 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Bret Barkelew<mailto:Bret.Barkelew@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] RE: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Not many drivers fall in edk2 repo so far, those are drivers with the corresponding definitions in UEFI spec.

  *   EFI REST EX UEFI Driver for Redfish service
  *   EFI Redfish Discover UEFI Driver
  *   EFI REST JSON Structure DXE Driver

All others have to go through code first policy, will be in edk2-staging repo.

-Abner

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Bret Barkelew via groups.io
Sent: Tuesday, September 15, 2020 11:19 AM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...<mailto:abner.chang@...>>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; Ni, Ray <ray.ni@...<mailto:ray.ni@...>>; Kinney, Michael D <michael.d.kinney@...<mailto:michael.d.kinney@...>>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

I think code review works. I’m primarily interested in seeing how much code falls under the “edk2” vs “edk2-staging” repos.

- Bret

From: Abner Chang via groups.io<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:12 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Seems no one has comment on this topic. Let’s just go through the code review process.
Thanks

Abner

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Abner Chang
Sent: Wednesday, September 9, 2020 11:02 AM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; Ni, Ray <ray.ni@...<mailto:ray.ni@...>>; Michael D Kinney <michael.d.kinney@...<mailto:michael.d.kinney@...>>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Add [RFC] to the subject, add Ray and Mike to the loop.

From: Chang, Abner (HPS SW/FW Technologist)
Sent: Tuesday, September 8, 2020 12:06 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...<mailto:abner.chang@...>>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>
Subject: RE: Request for the new package "RedfishPkg" under edk2 repo

This is the RFC for the new package "RedfishPkg" introduced to edk2 repo, I thought mailing system will add [RFC] prefix to the subject. Sorry for the inconvenience.

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Abner Chang
Sent: Tuesday, September 8, 2020 11:48 AM
To: rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Subject: [edk2-devel] Request for the new package "RedfishPkg" under edk2 repo

Hi everyone,
Given that we are going to contribute code of UEFI Redfish edk2 solution, a new package “RedfishPkg” under edk2 repo is necessary for accommodating the UEFI Redfish driver stacks, that includes

  *   EFI Redfish Host Interface DXE Driver
  *   EFI Refish Credential DXE Driver
  *   EFI REST EX UEFI Driver for Redfish service
  *   EFI Redfish Discover UEFI Driver
  *   EFI Redfish Discover Protocol
  *   EFI Redfish Config UEFI Driver
  *   EFI BIOS Config To Redfish Dxe Driver
  *   EFI REST JSON Structure DXE Driver
  *   EFI Source Coding DXE Driver
  *   EFI BIOS Resource Provision Generation Protocol
  *   EFI BIOS Resource Provision Transport Layer Protocol

The architecture have been discussing in TianoCore Design meeting and the corresponding BZ were created as well.
The code we will start to contribute includes

  *   Contribute to edk2 repo for those drivers already have the corresponding definitions in UEFI spec.
  *   Contribute code to edk2-staging/UEFI _Redfish for those drivers do not have the corresponding definitions in UEFI spec. This is for the evaluation and require ECR to USWG if community agree with having this driver for Redfish edk2 solution.

Please refer to below link for the details, https://github.com/tianocore/edk2-staging/blob/UEFI_Redfish/Readme.md<https://urldefense.proofpoint.com/v2/url?u=https-3A__nam06.safelinks.protection.outlook.com_-3Furl-3Dhttps-253A-252F-252Furldefense.proofpoint.com-252Fv2-252Furl-253Fu-253Dhttps-2D3A-5F-5Fnam06.safelinks.protection.outlook.com-5F-2D3Furl-2D3Dhttps-2D253A-2D252F-2D252Furldefense.proofpoint.com-2D252Fv2-2D252Furl-2D253Fu-2D253Dhttps-2D2D3A-2D5F-2D5Fnam06.safelinks.protection.outlook.com-2D5F-2D2D3Furl-2D2D3Dhttps-2D2D253A-2D2D252F-2D2D252Fgithub.com-2D2D252Ftianocore-2D2D252Fedk2-2D2D2Dstaging-2D2D252Fblob-2D2D252FUEFI-2D2D5FRedfish-2D2D252FReadme.md-2D2D26data-2D2D3D02-2D2D257C01-2D2D257Cbret.barkelew-2D2D2540microsoft.com-2D2D257Cec6961ac4b3143f196be08d859251f68-2D2D257C72f988bf86f141af91ab2d7cd011db47-2D2D257C1-2D2D257C0-2D2D257C637357363278947284-2D2D26sdata-2D2D3Dkt66JYtpN1X1hCrt5cQY3btyQEdoqZYkVPW5J7w8dws-2D2D253D-2D2D26reserved-2D2D3D0-2D2526d-2D253DDwMF-2D2Dg-2D2526c-2D253DC5b8zRQO1miGmBeVZ2LFWg-2D2526r-2D253D-2D5FSN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E-2D2526m-2D253DvNotrFyeoRyYey-2D2D0DOEVOLlZ7unqNGts5l1lH-2D2D4MzqM-2D2526s-2D253DBO3e8WR8joHCC9lD6Guk5Q2XN8DJ0JCOTy2AfB279q8-2D2526e-2D253D-2D26data-2D3D02-2D257C01-2D257Cbret.barkelew-2D2540microsoft.com-2D257C6bd38bf379f64b06f6b808d859282266-2D257C72f988bf86f141af91ab2d7cd011db47-2D257C1-2D257C0-2D257C637357376203679617-2D26sdata-2D3D-2D252Fc1YADqJZbAxtJEfc7R4LRToIVVG-2D252F8P5K9XRzp2RTio-2D253D-2D26reserved-2D3D0-2526d-253DDwMF-2Dg-2526c-253DC5b8zRQO1miGmBeVZ2LFWg-2526r-253D-5FSN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E-2526m-253DDkSlNNriVFNl3jnCeMG8vtCRlB3CgfREapKoapz-2Dcx0-2526s-253DvXm2LZsMsTXRCNZ9IZvid63RGiDHFF5aL-5F2JBwiL7kg-2526e-253D-26data-3D02-257C01-257Cbret.barkelew-2540microsoft.com-257C1b8115973f364cea229008d8592bc486-257C72f988bf86f141af91ab2d7cd011db47-257C1-257C0-257C637357391811802634-26sdata-3Dr9JTbIGJH3tmabZ-252BOtYAjVm5PRXWvuK0Wm2v2NByE1M-253D-26reserved-3D0&d=DwIF-g&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=goBsQ2eLlP7qVkOJAy8TPlQ0B6NFvNm4rP58u6ASQxc&s=2U_MKBpgLtoTglsPa4GJpgQpw6Ga3mBFBfABf7k0TwU&e= >

Thanks
Abner





Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Abner Chang
 

Sure Jiewen, we plan to talk about this on Tianocore design meeting recently. But I may not provide the reference here because it may against to the Redfish working group regulations.

I had requested to public this repo two years ago, however both WG chair and I had no follow up on this. I already restarted the conversation with him… just now.

 

For now, only the implementation of UEFI spec 29.7.2 (Redfish instance),  29.7.3 and 31.1 will be sent to community for review.

 

Thanks

Abner

 

 

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Yao, Jiewen
Sent: Tuesday, September 15, 2020 12:42 PM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; rfc@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; Fu, Siyuan <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

HI Abner

If it is DMTF private repo, should we discuss it in EDKII ?

 

Do we have a public reference somewhere else?

 

Thank you

Yao Jiewen

 

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abner Chang
Sent: Tuesday, September 15, 2020 12:23 PM
To: rfc@edk2.groups.io; devel@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; Fu, Siyuan <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

Hmm. You probably have to join dmtf as a member. That repo is private for members now, not public yet.

 


From: rfc@edk2.groups.io <rfc@edk2.groups.io> on behalf of Bret Barkelew via groups.io <bret.barkelew@...>
Sent: Tuesday, September 15, 2020 12:19:29 PM
To: Chang, Abner (HPS SW/FW Technologist) <
abner.chang@...>; devel@edk2.groups.io <devel@edk2.groups.io>; rfc@edk2.groups.io <rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <
nickle.wang@...>; Chen, Aaron <aaron.chen@...>; siyuan.fu@... <siyuan.fu@...>; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-rfc] [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

 

That link didn’t work for me.

- Bret

From: Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:59 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Bret Barkelew<mailto:Bret.Barkelew@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] RE: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

No, EFI REST JSON Structure DXE Driver (UEF spec section 29.7.3) is a centralized manager to manage “EFI Redfish JSON resource to C structure Converter libraries/drivers”  for converting Redfish resource in the specific schema from JSON format to the C structure or vice versa.
EFI REST JSON Structure DXE Driver itself doesn’t use JSON library, however “EFI Redfish JSON resource to C structure Converter libraries/drivers” do use open source jansson library to parse JSON payload. Furthermore, “EFI Redfish JSON resource to C structure Converter libraries/drivers” are generated by tool based on the published Redfish schemas. https://github.com/DMTF/Redfish-Schema-C-Struct-Generator<https://urldefense.proofpoint.com/v2/url?u=https-3A__nam06.safelinks.protection.outlook.com_-3Furl-3Dhttps-253A-252F-252Fgithub.com-252FDMTF-252FRedfish-2DSchema-2DC-2DStruct-2DGenerator-26data-3D02-257C01-257Cbret.barkelew-2540microsoft.com-257C1b8115973f364cea229008d8592bc486-257C72f988bf86f141af91ab2d7cd011db47-257C1-257C0-257C637357391811797643-26sdata-3DLdHAPly4oeVhyC6Xk7p0G0r1y8qVxrLfGZrN9EW5WpE-253D-26reserved-3D0&d=DwIF-g&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=goBsQ2eLlP7qVkOJAy8TPlQ0B6NFvNm4rP58u6ASQxc&s=j2rR7JmY2HjCtfOOe9ChSWCNKYseOJX2T-91Z3miShA&e= >

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Bret Barkelew via groups.io
Sent: Tuesday, September 15, 2020 11:41 AM
To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; devel@edk2.groups.io; rfc@edk2.groups.io
Cc: Wang, Nickle (HPS SW) <nickle.wang@...>; Chen, Aaron <aaron.chen@...>; siyuan.fu@...; Wang, Fan <fan.wang@...>; Wu, Jiaxin <jiaxin.wu@...>; Ni, Ray <ray.ni@...>; Kinney, Michael D <michael.d.kinney@...>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

JSON Structure would probably be worth discussing. I know that there are other places I’ve seen JSON used and it may end up that we want common business logic (similar to using Oniguruma for regex). Do you parse/format JSON in that one?

- Bret

From: Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:33 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Bret Barkelew<mailto:Bret.Barkelew@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] RE: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Not many drivers fall in edk2 repo so far, those are drivers with the corresponding definitions in UEFI spec.

  *   EFI REST EX UEFI Driver for Redfish service
  *   EFI Redfish Discover UEFI Driver
  *   EFI REST JSON Structure DXE Driver

All others have to go through code first policy, will be in edk2-staging repo.

-Abner

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Bret Barkelew via groups.io
Sent: Tuesday, September 15, 2020 11:19 AM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...<mailto:abner.chang@...>>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; Ni, Ray <ray.ni@...<mailto:ray.ni@...>>; Kinney, Michael D <michael.d.kinney@...<mailto:michael.d.kinney@...>>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

I think code review works. I’m primarily interested in seeing how much code falls under the “edk2” vs “edk2-staging” repos.

- Bret

From: Abner Chang via groups.io<mailto:abner.chang@...>
Sent: Monday, September 14, 2020 8:12 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist)<mailto:abner.chang@...>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW)<mailto:nickle.wang@...>; Chen, Aaron<mailto:aaron.chen@...>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan<mailto:fan.wang@...>; Wu, Jiaxin<mailto:jiaxin.wu@...>; Ni, Ray<mailto:ray.ni@...>; Kinney, Michael D<mailto:michael.d.kinney@...>
Subject: [EXTERNAL] Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Seems no one has comment on this topic. Let’s just go through the code review process.
Thanks

Abner

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Abner Chang
Sent: Wednesday, September 9, 2020 11:02 AM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; Ni, Ray <ray.ni@...<mailto:ray.ni@...>>; Michael D Kinney <michael.d.kinney@...<mailto:michael.d.kinney@...>>
Subject: Re: [edk2-devel] [RFC] Request for the new package "RedfishPkg" under edk2 repo

Add [RFC] to the subject, add Ray and Mike to the loop.

From: Chang, Abner (HPS SW/FW Technologist)
Sent: Tuesday, September 8, 2020 12:06 PM
To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...<mailto:abner.chang@...>>; rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>
Subject: RE: Request for the new package "RedfishPkg" under edk2 repo

This is the RFC for the new package "RedfishPkg" introduced to edk2 repo, I thought mailing system will add [RFC] prefix to the subject. Sorry for the inconvenience.

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] On Behalf Of Abner Chang
Sent: Tuesday, September 8, 2020 11:48 AM
To: rfc@edk2.groups.io<mailto:rfc@edk2.groups.io>
Cc: Wang, Nickle (HPS SW) <nickle.wang@...<mailto:nickle.wang@...>>; Chen, Aaron <aaron.chen@...<mailto:aaron.chen@...>>; siyuan.fu@...<mailto:siyuan.fu@...>; Wang, Fan <fan.wang@...<mailto:fan.wang@...>>; Wu, Jiaxin <jiaxin.wu@...<mailto:jiaxin.wu@...>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io>
Subject: [edk2-devel] Request for the new package "RedfishPkg" under edk2 repo

Hi everyone,
Given that we are going to contribute code of UEFI Redfish edk2 solution, a new package “RedfishPkg” under edk2 repo is necessary for accommodating the UEFI Redfish driver stacks, that includes

  *   EFI Redfish Host Interface DXE Driver
  *   EFI Refish Credential DXE Driver
  *   EFI REST EX UEFI Driver for Redfish service
  *   EFI Redfish Discover UEFI Driver
  *   EFI Redfish Discover Protocol
  *   EFI Redfish Config UEFI Driver
  *   EFI BIOS Config To Redfish Dxe Driver
  *   EFI REST JSON Structure DXE Driver
  *   EFI Source Coding DXE Driver
  *   EFI BIOS Resource Provision Generation Protocol
  *   EFI BIOS Resource Provision Transport Layer Protocol

The architecture have been discussing in TianoCore Design meeting and the corresponding BZ were created as well.
The code we will start to contribute includes

  *   Contribute to edk2 repo for those drivers already have the corresponding definitions in UEFI spec.
  *   Contribute code to edk2-staging/UEFI _Redfish for those drivers do not have the corresponding definitions in UEFI spec. This is for the evaluation and require ECR to USWG if community agree with having this driver for Redfish edk2 solution.

Please refer to below link for the details, https://github.com/tianocore/edk2-staging/blob/UEFI_Redfish/Readme.md<https://urldefense.proofpoint.com/v2/url?u=https-3A__nam06.safelinks.protection.outlook.com_-3Furl-3Dhttps-253A-252F-252Furldefense.proofpoint.com-252Fv2-252Furl-253Fu-253Dhttps-2D3A-5F-5Fnam06.safelinks.protection.outlook.com-5F-2D3Furl-2D3Dhttps-2D253A-2D252F-2D252Furldefense.proofpoint.com-2D252Fv2-2D252Furl-2D253Fu-2D253Dhttps-2D2D3A-2D5F-2D5Fnam06.safelinks.protection.outlook.com-2D5F-2D2D3Furl-2D2D3Dhttps-2D2D253A-2D2D252F-2D2D252Fgithub.com-2D2D252Ftianocore-2D2D252Fedk2-2D2D2Dstaging-2D2D252Fblob-2D2D252FUEFI-2D2D5FRedfish-2D2D252FReadme.md-2D2D26data-2D2D3D02-2D2D257C01-2D2D257Cbret.barkelew-2D2D2540microsoft.com-2D2D257Cec6961ac4b3143f196be08d859251f68-2D2D257C72f988bf86f141af91ab2d7cd011db47-2D2D257C1-2D2D257C0-2D2D257C637357363278947284-2D2D26sdata-2D2D3Dkt66JYtpN1X1hCrt5cQY3btyQEdoqZYkVPW5J7w8dws-2D2D253D-2D2D26reserved-2D2D3D0-2D2526d-2D253DDwMF-2D2Dg-2D2526c-2D253DC5b8zRQO1miGmBeVZ2LFWg-2D2526r-2D253D-2D5FSN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E-2D2526m-2D253DvNotrFyeoRyYey-2D2D0DOEVOLlZ7unqNGts5l1lH-2D2D4MzqM-2D2526s-2D253DBO3e8WR8joHCC9lD6Guk5Q2XN8DJ0JCOTy2AfB279q8-2D2526e-2D253D-2D26data-2D3D02-2D257C01-2D257Cbret.barkelew-2D2540microsoft.com-2D257C6bd38bf379f64b06f6b808d859282266-2D257C72f988bf86f141af91ab2d7cd011db47-2D257C1-2D257C0-2D257C637357376203679617-2D26sdata-2D3D-2D252Fc1YADqJZbAxtJEfc7R4LRToIVVG-2D252F8P5K9XRzp2RTio-2D253D-2D26reserved-2D3D0-2526d-253DDwMF-2Dg-2526c-253DC5b8zRQO1miGmBeVZ2LFWg-2526r-253D-5FSN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E-2526m-253DDkSlNNriVFNl3jnCeMG8vtCRlB3CgfREapKoapz-2Dcx0-2526s-253DvXm2LZsMsTXRCNZ9IZvid63RGiDHFF5aL-5F2JBwiL7kg-2526e-253D-26data-3D02-257C01-257Cbret.barkelew-2540microsoft.com-257C1b8115973f364cea229008d8592bc486-257C72f988bf86f141af91ab2d7cd011db47-257C1-257C0-257C637357391811802634-26sdata-3Dr9JTbIGJH3tmabZ-252BOtYAjVm5PRXWvuK0Wm2v2NByE1M-253D-26reserved-3D0&d=DwIF-g&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6qU3NYRO03nHp9P7Z5q59A3E&m=goBsQ2eLlP7qVkOJAy8TPlQ0B6NFvNm4rP58u6ASQxc&s=2U_MKBpgLtoTglsPa4GJpgQpw6Ga3mBFBfABf7k0TwU&e= >

Thanks
Abner





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