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Re: [PATCH v2 0/3] Add EDKII CI support for DynamicTablesPkg
Alexei Fedorov
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>
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Re: [PATCH v2 3/3] .pytool: CI Settings to support DynamicTablesPkg
Alexei Fedorov
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>
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Re: [PATCH v2 4/4] .azurepipelines: Add DynamicTablesPkg to CI matrix
Alexei Fedorov
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>
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Re: [PATCH v2 2/3] DynamicTablesPkg: Add EDK2 Core CI support
Alexei Fedorov
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>
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Re: [PATCH v2 1/3] DynamicTablesPkg: Fix issues reported by EDKII CI
Alexei Fedorov
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>
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Re: [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations
ping!!
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-----Original Message-----
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Re: [PATCH v3 1/1] ShellPkg/DynamicCommand: add HttpDynamicCommand
Laszlo Ersek
On 07/13/20 20:31, Vladimir Olovyannikov via groups.io wrote:
Introduce an http client utilizing EDK2 HTTP protocol, to diff --git a/ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uni b/ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uniThe line ending with "google.com index.html" lacks the "\r\n" terminator. Because of that, the help text is printed as follows: To get an index file from http://google.com and place it into the current directory: fs0:\> http google.com index.html.SH RETURNVALUES Thanks Laszlo
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Re: [PATCH v2 2/2] OvmfPkg: enable HttpDynamicCommand
Laszlo Ersek
On 07/22/20 22:54, Vladimir Olovyannikov via groups.io wrote:
Enable HttpDynamicCommand (Shell command "http") for OvmfPkg platforms.Reviewed-by: Laszlo Ersek <lersek@...>
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Re: [PATCH v2 1/2] ArmVirtPkg: enable HttpDynamiCommand
Laszlo Ersek
On 07/22/20 22:54, Vladimir Olovyannikov via groups.io wrote:
Enable HttpDynamicCommand (http Shell command)Reviewed-by: Laszlo Ersek <lersek@...>
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Re: [PATCH 1/1] EmbeddedPkg: fix gcc build errors in AndroidBootImgLib
Leif Lindholm
Series pushed as d0da48f112de..e43d0884ed93, with parentheses dropped
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as per Laszlo's comment, and Pierre added as reported-by for this flavour of this patch. Regards, Leif
On Wed, Jul 22, 2020 at 22:34:52 +0200, Laszlo Ersek wrote:
On 07/21/20 14:50, Leif Lindholm wrote:Commit dbd546a32d5aor we could perhaps introduce
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Re: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header
Javeed, Ashraf
Liming.
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Thanks for completing the review. This is just a comment change ask and I can mend the comment to send again. Ashraf
-----Original Message-----
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Re: [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers
Javeed, Ashraf
Liming;
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My response inline. Thanks for the review. Ashraf
-----Original Message-----I did run the ECC Python script and it did not report any issues. I shall check again and make the fixed if required. + UINT16 Uint16;
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Re: [edk2-platforms][PATCH 1/1] Platforms/RaspberryPi: Fix BIOS Release Date and System Manufacturer
Leif Lindholm
On Mon, Jul 20, 2020 at 17:15:07 +0100, Pete Batard wrote:
Per SMBIOS specs, The Type 0 BIOS Release Date is not a free form field butSo, this hunk is very neat, but nigh-on unreviewable. I.e. we should defintely have it - but only once. Could you break this up into some macros to go into some generic helper lib? (I don't have a better idea than EmbeddedPkg TimeBaseLib, but then that is already included in this module.) Would you be OK to break that snippet out separate? / Leif // Populate the Firmware major and minor.
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Re: [PATCH 1/1] EmbeddedPkg: fix gcc build errors in AndroidBootImgLib
Leif Lindholm
On Wed, Jul 22, 2020 at 22:34:52 +0200, Laszlo Ersek wrote:
On 07/21/20 14:50, Leif Lindholm wrote:Ah, do those get picked up automagically?Commit dbd546a32d5aor we could perhaps introduce If so we should definitely do that, as well as for ArmPkg. Yes, I'll do that.Header->PageSize has type UINT32, so this is OK (the addition is I just found the moving a single character aesthetically pleasing :) Reviewed-by: Laszlo Ersek <lersek@...>Thanks! / Leif
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Re: [PATCH v1 2/2] EmbeddedPkg: Add cast from (void*) for VS2017 build
Leif Lindholm
On Wed, Jul 22, 2020 at 23:11:40 +0200, Laszlo Ersek wrote:
Because there was a time when C didn't have void pointers.Personally I'd be OK with either fix (yours or Pierre's); to me bothdiff --git a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.cThe reason I prefer my version, although this one would also solve the Which is only made funnier by the fact that you cannot implement a6.2.6 Representations of typesFurther references: compliant malloc that returns a pointer with less than your largest data type alignment requirement. Sure. But (unsigned char *) still reads as "pointer to region7 An object shall have its stored value accessed only by an lvalueWhereas converting a (VOID*) to UINTN (and maybe back) is only covered containing stuff with 1-byte alignment requirements", whereas (void *) reads as pointer to region containing ...well-let's-not-worry-about-that-for now... See also https://martinfowler.com/bliki/CodeSmell.html (The dependency exploited in edk2 is that UINTNYes. I wouldn't like to to try to port EDK2 to CHERI. I actually find most of these things easier to reason about in the context of fat pointers. But that case also emphasises the danger presented by the special treatment of unsigned char * (for legacy purposes) in the standard is. In a system where pointers contained information about the size/alignment of the element pointed to, that would now in hardware encode "1-byte alignment" instead of "unknown alignment". And would be dereferenced without raising an exception. But, given both patches are for edk2, where UINTN <-> (VOID*)Thanks! / Leif
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Re: [PATCH 2/2] OvmfPkg: enable HttpDynamicCommand
Laszlo Ersek
On 07/22/20 22:02, Vladimir Olovyannikov wrote:
Hi Laszlo,Thank *you* for submitting the set, at my request! :) Referencing the BZ in the cover letter only is indeed not ideal; the-----Original Message-----OK, will do. For future contributions related to a BZ ticket - does it mean cover letter does not get captured in the git history. When submitting a series for a BZ, it's best to mention the BZ in every patch in the series. One frequently used format is """ Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2857 """ placed near the end of the commit message (just above the Signed-off-by and similar tags). But other formats are fine too. Thanks!OK, will do, thanks. Laszlo
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Re: [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers
Liming Gao
Ashraf:
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-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed, Ashraf Sent: 2020年7月22日 23:22 To: devel@edk2.groups.io Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...> Subject: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Register definitions from chapter 7 of Compute Express Link Specification Revision 1.1 are ported into the new Cxl11.h. The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure header, led to the inclusion of upgraded Pci.h. Signed-off-by: Ashraf Javeed <ashraf.javeed@...> Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <liming.gao@...> -- V2: Indentation and double declaration fix, copyright date update V3: Copyright date fix --- MdePkg/Include/IndustryStandard/Cxl11.h | 569 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdePkg/Include/IndustryStandard/Pci.h | 6 ++---- 2 files changed, 571 insertions(+), 4 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/IndustryStandard/Cxl11.h new file mode 100644 index 0000000000..a261bb3fae --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl11.h @@ -0,0 +1,569 @@ +/** @file + CXL 1.1 Register definitions + + This file contains the register definitions based on the Compute + Express Link + (CXL) Specification Revision 1.1. + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL11_H_ +#define _CXL11_H_ + +#include <IndustryStandard/Pci.h> +// +// DVSEC Vendor ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - +Table 58 // (subject to change as per CXL assigned Vendor ID) // +#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086 + +// +// CXL Flex Bus Device default device and function number // Compute +Express Link Specification Revision: 1.1 - Chapter 7.1.1 // +#define CXL_DEV_DEV 0 +#define CXL_DEV_FUNC 0 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +/// +/// The PCIe DVSEC for Flex Bus Device +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // bit 0 + UINT16 IoCapable : 1; // bit 1 + UINT16 MemCapable : 1; // bit 2 + UINT16 MemHwInitMode : 1; // bit 3 + UINT16 HdmCount : 2; // bit 4..5 + UINT16 Reserved1 : 8; // bit 6..13 + UINT16 ViralCapable : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + }Bits; This line should have one space between } and Bits. Otherwise, ECC will report the issue. Please fix it in this header file. }Bits ==> } Bits Thanks Liming + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CacheSfCoverage : 5; // bit 3..7 + UINT16 CacheSfGranularity : 3; // bit 8..10 + UINT16 CacheCleanEviction : 1; // bit 11 + UINT16 Reserved1 : 2; // bit 12..13 + UINT16 ViralEnable : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; + +typedef union { + struct { + UINT16 Reserved1 : 14; // bit 0..13 + UINT16 ViralStatus : 1; // bit 14 + UINT16 Reserved2 : 1; // bit 15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; + +typedef union { + struct { + UINT16 Reserved1 : 1; // bit 0 + UINT16 Reserved2 : 1; // bit 1 + UINT16 Reserved3 : 1; // bit 2 + UINT16 Reserved4 : 13; // bit 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; + +typedef union { + struct { + UINT16 Reserved1 : 1; // bit 0 + UINT16 Reserved2 : 1; // bit 1 + UINT16 Reserved3 : 14; // bit 2..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; + +typedef union { + struct { + UINT16 ConfigLock : 1; // bit 0 + UINT16 Reserved1 : 15; // bit 1..15 + }Bits; + UINT16 Uint16; +} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // bit 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // bit 0 + UINT32 MemoryActive : 1; // bit 1 + UINT32 MediaType : 3; // bit 2..4 + UINT32 MemoryClass : 3; // bit 5..7 + UINT32 DesiredInterleave : 3; // bit 8..10 + UINT32 Reserved : 17; // bit 11..27 + UINT32 MemorySizeLow : 4; // bit 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // bit 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // bit 0..27 + UINT32 MemoryBaseLow : 4; // bit 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; + + +typedef union { + struct { + UINT32 MemorySizeHigh : 32; // bit 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; + +typedef union { + struct { + UINT32 MemoryInfoValid : 1; // bit 0 + UINT32 MemoryActive : 1; // bit 1 + UINT32 MediaType : 3; // bit 2..4 + UINT32 MemoryClass : 3; // bit 5..7 + UINT32 DesiredInterleave : 3; // bit 8..10 + UINT32 Reserved : 17; // bit 11..27 + UINT32 MemorySizeLow : 4; // bit 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; + +typedef union { + struct { + UINT32 MemoryBaseHigh : 32; // bit 0..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; + +typedef union { + struct { + UINT32 Reserved : 28; // bit 0..27 + UINT32 MemoryBaseLow : 4; // bit 28..31 + }Bits; + UINT32 Uint32; +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; + +// +// Flex Bus Device DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, +Table 58 // +#define FLEX_BUS_DEVICE_DVSEC_ID 0 + +// +// PCIe DVSEC for Flex Bus Device +// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, +Figure 95 // typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 + CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10 + CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12 + CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16 + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18 + CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20 + UINT16 Reserved; // offset 22 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48 + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52 +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE; +///@} + +/// +/// PCIe DVSEC for FLex Bus Port +///@{ +typedef union { + struct { + UINT16 CacheCapable : 1; // bit 0 + UINT16 IoCapable : 1; // bit 1 + UINT16 MemCapable : 1; // bit 2 + UINT16 Reserved : 13; // bit 3..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CxlSyncBypassEnable : 1; // bit 3 + UINT16 DriftBufferEnable : 1; // bit 4 + UINT16 Reserved : 3; // bit 5..7 + UINT16 Retimer1Present : 1; // bit 8 + UINT16 Retimer2Present : 1; // bit 9 + UINT16 Reserved2 : 6; // bit 10..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; + +typedef union { + struct { + UINT16 CacheEnable : 1; // bit 0 + UINT16 IoEnable : 1; // bit 1 + UINT16 MemEnable : 1; // bit 2 + UINT16 CxlSyncBypassEnable : 1; // bit 3 + UINT16 DriftBufferEnable : 1; // bit 4 + UINT16 Reserved : 3; // bit 5..7 + UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8 + UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9 + UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10 + UINT16 Reserved2 : 5; // bit 11..15 + }Bits; + UINT16 Uint16; +} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; + +// +// Flex Bus Port DVSEC ID +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, +Table 62 // +#define FLEX_BUS_PORT_DVSEC_ID 7 + +// +// PCIe DVSEC for Flex Bus Port +// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, +Figure 99 // typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4 + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10 + CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12 + CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14 +} CXL_1_1_DVSEC_FLEX_BUS_PORT; +///@} + +/// +/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers +/// + +/// The CXL.Cache and CXL.Memory Architectural register definitions /// +Based on chapter 7.2.2 of Compute Express Link Specification Revision: +1.1 ///@{ + +#define CXL_CAPABILITY_HEADER_OFFSET 0 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlCacheMemVersion : 4; // bit 20..23 + UINT32 ArraySize : 8; // bit 24..31 + } Bits; + UINT32 Uint32; +} CXL_CAPABILITY_HEADER; + +#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlRasCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_RAS_CAPABILITY_HEADER; + +#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_SECURITY_CAPABILITY_HEADER; + +#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC +typedef union { + struct { + UINT32 CxlCapabilityId : 16; // bit 0..15 + UINT32 CxlCapabilityVersion : 4; // bit 16..19 + UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_CAPABILITY_HEADER; + +typedef union { + struct { + UINT32 CacheDataParity : 1; // bit 0..0 + UINT32 CacheAddressParity : 1; // bit 1..1 + UINT32 CacheByteEnableParity : 1; // bit 2..2 + UINT32 CacheDataEcc : 1; // bit 3..3 + UINT32 MemDataParity : 1; // bit 4..4 + UINT32 MemAddressParity : 1; // bit 5..5 + UINT32 MemByteEnableParity : 1; // bit 6..6 + UINT32 MemDataEcc : 1; // bit 7..7 + UINT32 ReInitThreshold : 1; // bit 8..8 + UINT32 RsvdEncodingViolation : 1; // bit 9..9 + UINT32 PoisonReceived : 1; // bit 10..10 + UINT32 ReceiverOverflow : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataParityMask : 1; // bit 0..0 + UINT32 CacheAddressParityMask : 1; // bit 1..1 + UINT32 CacheByteEnableParityMask : 1; // bit 2..2 + UINT32 CacheDataEccMask : 1; // bit 3..3 + UINT32 MemDataParityMask : 1; // bit 4..4 + UINT32 MemAddressParityMask : 1; // bit 5..5 + UINT32 MemByteEnableParityMask : 1; // bit 6..6 + UINT32 MemDataEccMask : 1; // bit 7..7 + UINT32 ReInitThresholdMask : 1; // bit 8..8 + UINT32 RsvdEncodingViolationMask : 1; // bit 9..9 + UINT32 PoisonReceivedMask : 1; // bit 10..10 + UINT32 ReceiverOverflowMask : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 CacheDataParitySeverity : 1; // bit 0..0 + UINT32 CacheAddressParitySeverity : 1; // bit 1..1 + UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2 + UINT32 CacheDataEccSeverity : 1; // bit 3..3 + UINT32 MemDataParitySeverity : 1; // bit 4..4 + UINT32 MemAddressParitySeverity : 1; // bit 5..5 + UINT32 MemByteEnableParitySeverity : 1; // bit 6..6 + UINT32 MemDataEccSeverity : 1; // bit 7..7 + UINT32 ReInitThresholdSeverity : 1; // bit 8..8 + UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9 + UINT32 PoisonReceivedSeverity : 1; // bit 10..10 + UINT32 ReceiverOverflowSeverity : 1; // bit 11..11 + UINT32 Reserved : 20; // bit 12..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; + +typedef union { + struct { + UINT32 CacheDataEcc : 1; // bit 0..0 + UINT32 MemoryDataEcc : 1; // bit 1..1 + UINT32 CrcThreshold : 1; // bit 2..2 + UINT32 RetryThreshold : 1; // bit 3..3 + UINT32 CachePoisonReceived : 1; // bit 4..4 + UINT32 MemoryPoisonReceived : 1; // bit 5..5 + UINT32 PhysicalLayerError : 1; // bit 6..6 + UINT32 Reserved : 25; // bit 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_STATUS; + +typedef union { + struct { + UINT32 CacheDataEccMask : 1; // bit 0..0 + UINT32 MemoryDataEccMask : 1; // bit 1..1 + UINT32 CrcThresholdMask : 1; // bit 2..2 + UINT32 RetryThresholdMask : 1; // bit 3..3 + UINT32 CachePoisonReceivedMask : 1; // bit 4..4 + UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5 + UINT32 PhysicalLayerErrorMask : 1; // bit 6..6 + UINT32 Reserved : 25; // bit 7..31 + } Bits; + UINT32 Uint32; +} CXL_CORRECTABLE_ERROR_MASK; + +typedef union { + struct { + UINT32 FirstErrorPointer : 4; // bit 0..3 + UINT32 Reserved1 : 5; // bit 4..8 + UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9 + UINT32 Reserved2 : 3; // bit 10..12 + UINT32 PoisonEnabled : 1; // bit 13..13 + UINT32 Reserved3 : 18; // bit 14..31 + } Bits; + UINT32 Uint32; +} CXL_ERROR_CAPABILITIES_AND_CONTROL; + +typedef struct { + CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus; + CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask; + CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity; + CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus; + CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask; + CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl; + UINT32 HeaderLog[16]; +} CXL_1_1_RAS_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT32 DeviceTrustLevel : 2; // bit 0..1 + UINT32 Reserved : 30; // bit 2..31 + } Bits; + UINT32 Uint32; +} CXL_1_1_SECURITY_POLICY; + +typedef struct { + CXL_1_1_SECURITY_POLICY SecurityPolicy; +} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; + +typedef union { + struct { + UINT64 CxlLinkVersionSupported : 4; // bit 0..3 + UINT64 CxlLinkVersionReceived : 4; // bit 4..7 + UINT64 LlrWrapValueSupported : 8; // bit 8..15 + UINT64 LlrWrapValueReceived : 8; // bit 16..23 + UINT64 NumRetryReceived : 5; // bit 24..28 + UINT64 NumPhyReinitReceived : 5; // bit 29..33 + UINT64 WrPtrReceived : 8; // bit 34..41 + UINT64 EchoEseqReceived : 8; // bit 42..49 + UINT64 NumFreeBufReceived : 8; // bit 50..57 + UINT64 Reserved : 6; // bit 58..63 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_CAPABILITY; + +typedef union { + struct { + UINT16 LlReset : 1; // bit 0..0 + UINT16 LlInitStall : 1; // bit 1..1 + UINT16 LlCrdStall : 1; // bit 2..2 + UINT16 InitState : 2; // bit 3..4 + UINT16 LlRetryBufferConsumed : 8; // bit 5..12 + UINT16 Reserved : 3; // bit 13..15 + } Bits; + UINT16 Uint16; +} CXL_LINK_LAYER_CONTROL_AND_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_CONTROL; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; + +typedef union { + struct { + UINT64 CacheReqCredits : 10; // bit 0..9 + UINT64 CacheRspCredits : 10; // bit 10..19 + UINT64 CacheDataCredits : 10; // bit 20..29 + UINT64 MemReqRspCredits : 10; // bit 30..39 + UINT64 MemDataCredits : 10; // bit 40..49 + } Bits; + UINT64 Uint64; +} CXL_LINK_LAYER_TX_CREDIT_STATUS; + +typedef union { + struct { + UINT32 AckForceThreshold : 8; // bit 0..7 + UINT32 AckFLushRetimer : 10; // bit 8..17 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_ACK_TIMER_CONTROL; + +typedef union { + struct { + UINT32 MdhDisable : 1; // bit 0..0 + UINT32 Reserved : 31; // bit 1..31 + } Bits; + UINT32 Uint32; +} CXL_LINK_LAYER_DEFEATURE; + +typedef struct { + CXL_LINK_LAYER_CAPABILITY LinkLayerCapability; + CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus; + CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl; + CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus; + CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus; + CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl; + CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature; +} CXL_1_1_LINK_CAPABILITY_STRUCTURE; + +#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 +typedef union { + struct { + UINT32 Reserved1 : 4; // bit 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 + UINT32 Reserved2 : 24; // bit 8..31 + } Bits; + UINT32 Uint32; +} CXL_IO_ARBITRATION_CONTROL; + +#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 +typedef union { + struct { + UINT32 Reserved1 : 4; // bit 0..3 + UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7 + UINT32 Reserved2 : 24; // bit 8..31 + } Bits; + UINT32 Uint32; +} CXL_CACHE_MEMORY_ARBITRATION_CONTROL; +///@} + +/// The CXL.RCRB base register definition /// Based on chapter 7.3 of +Compute Express Link Specification Revision: 1.1 ///@{ typedef union { + struct { + UINT64 RcrbEnable : 1; // bit 0..0 + UINT64 Reserved : 12; // bit 1..12 + UINT64 RcrbBaseAddress : 51; // bit 13..63 + } Bits; + UINT64 Uint64; +} CXL_RCRB_BASE; +///@} + +#pragma pack() + +// +// CXL Downstream / Upstream Port RCRB space register offsets // +Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - +Figure 97 // +#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010 +#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014 +#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100 + +#endif diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h index 8ed96b992a..42c00ac762 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -1,7 +1,7 @@ /** @file Support for the latest PCI standard. -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_ #define _PCI_H_ -#include <IndustryStandard/Pci30.h> -#include <IndustryStandard/PciExpress21.h> -#include <IndustryStandard/PciExpress30.h> +#include <IndustryStandard/PciExpress50.h> #include <IndustryStandard/PciCodeId.h> #endif -- 2.21.0.windows.1
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Re: [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF
Liming Gao
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-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Marcello Sylvester Bauer Sent: 2020年7月22日 21:16 To: devel@edk2.groups.io Cc: Patrick Rudolph <patrick.rudolph@...>; Christian Walter <christian.walter@...>; Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...> Subject: [edk2-devel] [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF Add support for arbitrary sized MMCONF by introducing a new PCD. Signed-off-by: Patrick Rudolph <patrick.rudolph@...> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@...> Cc: Patrick Rudolph <patrick.rudolph@...> Cc: Christian Walter <christian.walter@...> Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <liming.gao@...> --- MdePkg/MdePkg.dec | 4 + MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- MdePkg/Include/Library/PciExpressLib.h | 5 +- MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 216 +++++++++++++++++--- 4 files changed, 193 insertions(+), 38 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..02e736a01126 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] # @Prompt PCI Express Base Address. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a + ## This value is used to set the size of PCI express hierarchy. The default is 256 MB.+ # @Prompt PCI Express Base Size.+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x0000000f+ ## Default current ISO 639-2 language: English & French. # @Prompt Default Value of LangCodes Variable. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001cdiff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf [Liming] 256M is 0x10000000. PCD value is 0x0FFFFFFF. Does it mean that the default value is 256M - 1? Thanks Liming index a7edb74cde71..12734b022ac7 100644 --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf @@ -1,7 +1,7 @@ ## @file-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.+# Instance of PCI Express Library using the variable size PCI Express MMIO window. #-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform+# PCI Express Library that uses the variable size PCI Express MMIO window to perform # PCI Configuration cycles. Layers on top of an I/O Library instance. # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>@@ -38,4 +38,4 @@ [LibraryClasses] [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES-+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMESdiff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h index 826fdcf7db6c..d78193a0a352 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -2,8 +2,9 @@ Provides services to access PCI Configuration Space using the MMIO PCI Express window. This library is identical to the PCI Library, except the access method for performing PCI- configuration cycles must be through the 256 MB PCI Express MMIO window whose base address- is defined by PcdPciExpressBaseAddress.+ configuration cycles must be through the PCI Express MMIO window whose base address+ is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patentdiff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c index 99a166c3609b..0311ecb3025f 100644 --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c @@ -22,7 +22,8 @@ /** Assert the validity of a PCI address. A valid PCI address should contain 1's- only in the low 28 bits.+ only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real+ number of PCI busses in this segment. @param A The address to validate. @@ -79,6 +80,24 @@ GetPciExpressBaseAddress ( return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } +/**+ Gets the size of PCI Express.++ This internal functions retrieves PCI Express Base Size via a PCD entry+ PcdPciExpressBaseSize.++ @return The base size of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseSize (+ VOID+ )+{+ return (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /** Reads an 8-bit PCI configuration register. @@ -91,7 +110,8 @@ GetPciExpressBaseAddress ( @param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT8@@ -101,6 +121,9 @@ PciExpressRead8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -117,7 +140,8 @@ PciExpressRead8 ( Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT8@@ -128,6 +152,9 @@ PciExpressWrite8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -148,7 +175,8 @@ PciExpressWrite8 ( Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT8@@ -159,6 +187,9 @@ PciExpressOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -179,7 +210,8 @@ PciExpressOr8 ( Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -190,6 +222,9 @@ PciExpressAnd8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -212,7 +247,8 @@ PciExpressAnd8 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -224,6 +260,9 @@ PciExpressAndThenOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -249,7 +288,9 @@ PciExpressAndThenOr8 ( @param EndBit The ordinal of the most significant bit in the bit field. Range 0..7. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI configuration+ register. **/ UINT8@@ -261,6 +302,9 @@ PciExpressBitFieldRead8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldRead8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -289,7 +333,8 @@ PciExpressBitFieldRead8 ( Range 0..7. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -302,6 +347,9 @@ PciExpressBitFieldWrite8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldWrite8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -334,7 +382,8 @@ PciExpressBitFieldWrite8 ( Range 0..7. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -347,6 +396,9 @@ PciExpressBitFieldOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -379,7 +431,8 @@ PciExpressBitFieldOr8 ( Range 0..7. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -392,6 +445,9 @@ PciExpressBitFieldAnd8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAnd8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -442,6 +499,9 @@ PciExpressBitFieldAndThenOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -464,7 +524,8 @@ PciExpressBitFieldAndThenOr8 ( @param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT16@@ -474,6 +535,9 @@ PciExpressRead16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -491,7 +555,8 @@ PciExpressRead16 ( Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT16@@ -502,6 +567,9 @@ PciExpressWrite16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -523,7 +591,8 @@ PciExpressWrite16 ( Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -534,6 +603,9 @@ PciExpressOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -555,7 +627,8 @@ PciExpressOr16 ( Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -566,6 +639,9 @@ PciExpressAnd16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -589,7 +665,8 @@ PciExpressAnd16 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -601,6 +678,9 @@ PciExpressAndThenOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -627,7 +707,9 @@ PciExpressAndThenOr16 ( @param EndBit The ordinal of the most significant bit in the bit field. Range 0..15. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI configuration+ register. **/ UINT16@@ -639,6 +721,9 @@ PciExpressBitFieldRead16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldRead16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -668,7 +753,8 @@ PciExpressBitFieldRead16 ( Range 0..15. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -681,6 +767,9 @@ PciExpressBitFieldWrite16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldWrite16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -714,7 +803,8 @@ PciExpressBitFieldWrite16 ( Range 0..15. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -727,6 +817,9 @@ PciExpressBitFieldOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -760,7 +853,8 @@ PciExpressBitFieldOr16 ( Range 0..15. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAnd16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -824,6 +922,9 @@ PciExpressBitFieldAndThenOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -846,7 +947,8 @@ PciExpressBitFieldAndThenOr16 ( @param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT32@@ -856,6 +958,9 @@ PciExpressRead32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -873,7 +978,8 @@ PciExpressRead32 ( Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT32@@ -884,6 +990,9 @@ PciExpressWrite32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -905,7 +1014,8 @@ PciExpressWrite32 ( Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -916,6 +1026,9 @@ PciExpressOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -937,7 +1050,8 @@ PciExpressOr32 ( Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -948,6 +1062,9 @@ PciExpressAnd32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -971,7 +1088,8 @@ PciExpressAnd32 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -983,6 +1101,9 @@ PciExpressAndThenOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 ( @param EndBit The ordinal of the most significant bit in the bit field. Range 0..31. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI+ configuration register. **/ UINT32@@ -1021,6 +1144,9 @@ PciExpressBitFieldRead32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldRead32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1050,7 +1176,8 @@ PciExpressBitFieldRead32 ( Range 0..31. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1063,6 +1190,9 @@ PciExpressBitFieldWrite32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldWrite32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1096,7 +1226,8 @@ PciExpressBitFieldWrite32 ( Range 0..31. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32 ( Range 0..31. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1155,6 +1290,9 @@ PciExpressBitFieldAnd32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAnd32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd32 ( @param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1235,7 +1377,8 @@ PciExpressBitFieldAndThenOr32 ( @param Size The size in bytes of the transfer. @param Buffer The pointer to a buffer receiving the data read. - @return Size read data from StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @retval other Size read data from StartAddress. **/ UINTN@@ -1249,6 +1392,9 @@ PciExpressReadBuffer ( UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if (StartAddress >= PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); if (Size == 0) {@@ -1335,7 +1481,8 @@ PciExpressReadBuffer ( @param Size The size in bytes of the transfer. @param Buffer The pointer to a buffer containing the data to write. - @return Size written to StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @retval other Size written to StartAddress. **/ UINTN@@ -1349,6 +1496,9 @@ PciExpressWriteBuffer ( UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if (StartAddress >= PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); if (Size == 0) {-- 2.27.0 -=-=-=-=-=-= Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63115): https://edk2.groups.io/g/devel/message/63115 Mute This Topic: https://groups.io/mt/75724107/1759384 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [liming.gao@...] -=-=-=-=-=-=
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Re: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header
Liming Gao
Asharf:
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-----Original Message-----
From: Javeed, Ashraf <ashraf.javeed@...> Sent: 2020年7月22日 23:22 To: devel@edk2.groups.io Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...> Subject: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Introducing the Cxl.h as the main header file to support all versions of Compute Express Link Specification register definitions. Signed-off-by: Ashraf Javeed <ashraf.javeed@...> Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <liming.gao@...> -- V2: Indentation and double declaration fix, copyright date update V3: Copyright date fix --- MdePkg/Include/IndustryStandard/Cxl.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/IndustryStandard/Cxl.h new file mode 100644 index 0000000000..632aa146d0 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -0,0 +1,22 @@ +/** @file + Support for the latest CXL standard + + The main header to reference all versions of CXL Base specification + registers from the MDE Does MDE means MdePkg? I think "from the MDE" can be removed. With this change, Reviewed-by: Liming Gao <liming.gao@...> Thanks Liming + +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CXL_MAIN_H_ +#define _CXL_MAIN_H_ + +#include <IndustryStandard/Cxl11.h> +// +// CXL assigned new Vendor ID +// +#define CXL_DVSEC_VENDOR_ID 0x1E98 + +#endif + -- 2.21.0.windows.1
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Re: [PATCH V2 1/2] BaseTools: Add gcc flag to warn on void* pointer arithmetic
Leif Lindholm
Hi Andrew,
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Agreed. I also think this should be applied across all architectures, not just ARM/AARCH64. Since Visual Studio has never been been able to compile the affected code, I expect impact to Ia32/X64 to be minimal. Regards, Leif
On Wed, Jul 22, 2020 at 19:49:01 -0700, Andrew Fish via groups.io wrote:
Bob,
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