Date   

Re: [PATCH v2 0/3] Add EDKII CI support for DynamicTablesPkg

Alexei Fedorov
 

Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>


Re: [PATCH v2 3/3] .pytool: CI Settings to support DynamicTablesPkg

Alexei Fedorov
 

Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>


Re: [PATCH v2 4/4] .azurepipelines: Add DynamicTablesPkg to CI matrix

Alexei Fedorov
 

Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>


Re: [PATCH v2 2/3] DynamicTablesPkg: Add EDK2 Core CI support

Alexei Fedorov
 

Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>


Re: [PATCH v2 1/3] DynamicTablesPkg: Fix issues reported by EDKII CI

Alexei Fedorov
 

Reviewed-by: Alexei Fedorov <Alexei.Fedorov@...>


Re: [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations

Pankaj Bansal
 

ping!!

-----Original Message-----
From: Pankaj Bansal (OSS) <pankaj.bansal@...>
Sent: Saturday, July 4, 2020 9:22 PM
To: devel@edk2.groups.io; Eric Jin <eric.jin@...>; G Edhaya Chandran
<Edhaya.Chandran@...>
Cc: Pankaj Bansal <pankaj.bansal@...>; Paul Yang <Paul.Yang@...>;
Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; Gaurav Jain
<gaurav.jain@...>
Subject: [PATCH edk2-test 1/1] SctPkg: fix page alignment calculations

From: Pankaj Bansal <pankaj.bansal@...>

The BBTestAllocatePagesInterfaceTest tries to allocate pages for
different memory types.
While doing so, it tries to fix up the Start and PageNum for 64K
Page size. There are multiple issues with this:

1. 64K alignment is being done regardless of Processor type and Memory
type. while this is correct for ARM64 Processor, it might not be so
for other Processor types. Also 64K alignment for ARM64 Processor
is needed for some Memory types not all.
2. The Start is being incremented by 64K, even if Start is already 64K
aligned.
3. PageNum is being decreased by 16 pages indiscriminately, which might
not be needed in all cases.

fix all these issues by correctly doing the alignment in all needed
cases.

Cc: Paul Yang <Paul.Yang@...>
Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
Cc: Gaurav Jain <gaurav.jain@...>
Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../MemoryAllocationServicesBBTestFunction.c | 148 +++++++++++++-----
1 file changed, 106 insertions(+), 42 deletions(-)

diff --git a/uefi-
sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
oxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-
sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
oxTest/MemoryAllocationServicesBBTestFunction.c
index d18fe1fc2b94..9ed9e6e0de74 100644
--- a/uefi-
sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
oxTest/MemoryAllocationServicesBBTestFunction.c
+++ b/uefi-
sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB
oxTest/MemoryAllocationServicesBBTestFunction.c
@@ -354,6 +354,7 @@ BBTestAllocatePagesInterfaceTest (
EFI_TPL OldTpl;
EFI_MEMORY_DESCRIPTOR Descriptor;
UINTN PageNum;
+ UINTN Alignment;

//
// Get the Standard Library Interface
@@ -700,14 +701,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -830,14 +840,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -953,14 +972,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start + (SctLShiftU64 (PageNum/3, EFI_PAGE_SHIFT) &
0xFFFFFFFFFFFF0000);

@@ -1076,14 +1104,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start + (SctLShiftU64 (PageNum * 2 / 3, EFI_PAGE_SHIFT) &
0xFFFFFFFFFFFF0000);

@@ -1206,14 +1243,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -1329,14 +1375,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -1468,14 +1523,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

--
2.17.1


Re: [PATCH v3 1/1] ShellPkg/DynamicCommand: add HttpDynamicCommand

Laszlo Ersek
 

On 07/13/20 20:31, Vladimir Olovyannikov via groups.io wrote:
Introduce an http client utilizing EDK2 HTTP protocol, to
allow fast image downloading from http/https servers.
HTTP download speed is usually faster than tftp.
The client is based on the same approach as tftp dynamic command, and
uses the same UEFI Shell command line parameters. This makes it easy
integrating http into existing UEFI Shell scripts.
Note that to enable HTTP download, feature Pcd
gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections must
be set to TRUE.

Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@...>
Tested-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
Cc: Zhichao Gao <zhichao.gao@...>
Cc: Maciej Rabeda <maciej.rabeda@...>
Cc: Jiaxin Wu <jiaxin.wu@...>
Cc: Siyuan Fu <siyuan.fu@...>
Cc: Ray Ni <ray.ni@...>
Cc: Liming Gao <liming.gao@...>
Cc: Nd <nd@...>
---
.../DynamicCommand/HttpDynamicCommand/Http.c | 1700 +++++++++++++++++
.../DynamicCommand/HttpDynamicCommand/Http.h | 84 +
.../HttpDynamicCommand/Http.uni | 113 ++
.../HttpDynamicCommand/HttpApp.c | 53 +
.../HttpDynamicCommand/HttpApp.inf | 58 +
.../HttpDynamicCommand/HttpDynamicCommand.c | 134 ++
.../HttpDynamicCommand/HttpDynamicCommand.inf | 63 +
ShellPkg/Include/Guid/ShellLibHiiGuid.h | 5 +
ShellPkg/ShellPkg.dec | 1 +
ShellPkg/ShellPkg.dsc | 5 +
10 files changed, 2216 insertions(+)
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/Http.c
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/Http.h
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uni
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.c
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/HttpApp.inf
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.c
create mode 100644 ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
diff --git a/ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uni b/ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uni
new file mode 100644
index 000000000000..efe50e25819c
--- /dev/null
+++ b/ShellPkg/DynamicCommand/HttpDynamicCommand/Http.uni
@@ -0,0 +1,113 @@
+// /**
+//
+// (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
+// Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved. <BR>
+// Copyright (c) 2020, Broadcom. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Module Name:
+//
+// Http.uni
+//
+// Abstract:
+//
+// String definitions for UEFI Shell HTTP command
+//
+//
+// **/
+
+/=#
+
+#langdef en-US "english"
+
+#string STR_GEN_TOO_MANY #language en-US "%H%s%N: Too many arguments. Try help http.\r\n"
+#string STR_GEN_TOO_FEW #language en-US "%H%s%N: Too few arguments. Try help http.\r\n"
+#string STR_GEN_PARAM_INV #language en-US "%H%s%N: Invalid argument - '%H%s%N'. Try help http.\r\n"
+#string STR_GEN_PROBLEM #language en-US "%H%s%N: Unknown flag - '%H%s%N'. Try help http.\r\n"
+#string STR_GEN_FILE_OPEN_FAIL #language en-US "%H%s%N: Cannot open file - '%H%s%N'\r\n"
+#string STR_GEN_CRLF #language en-US "\r\n"
+
+#string STR_HTTP_ERR_NO_NIC #language en-US "No network interface card found.\r\n"
+#string STR_HTTP_ERR_NIC_NAME #language en-US "Failed to get the name of the network interface card number %d - %r\r\n"
+#string STR_HTTP_ERR_OPEN_PROTOCOL #language en-US "Unable to open HTTP protocol on '%H%s%N' - %r\r\n"
+#string STR_HTTP_ERR_CONFIGURE #language en-US "Unable to configure HTTP protocol on '%H%s%N' - %r\r\n"
+#string STR_HTTP_ERR_DOWNLOAD #language en-US "Unable to download the file '%H%s%N' on '%H%s%N' - %r\r\n"
+#string STR_HTTP_ERR_WRITE #language en-US "Unable to write into file '%H%s%N' - %r\r\n"
+#string STR_HTTP_ERR_NIC_NOT_FOUND #language en-US "Network Interface Card '%H%s%N' not found.\r\n"
+#string STR_HTTP_ERR_STATUSCODE #language en-US "\r'%H%s%N' reports '%s' for '%H%s%N' \r\n"
+#string STR_HTTP_DOWNLOADING #language en-US "Downloading '%H%s%N'\r\n"
+
+#string STR_GET_HELP_HTTP #language en-US ""
+".TH http 0 "Download a file from HTTP server."\r\n"
+".SH NAME\r\n"
+"Download a file from HTTP server.\r\n"
+".SH SYNOPSIS\r\n"
+" \r\n"
+"HTTP [-i interface] [-l port] [-t timeout] [-s size]\r\n"
+" <URL> [localfilepath]\r\n"
+".SH OPTIONS\r\n"
+" \r\n"
+" -i interface - Specifies an adapter name, i.e., eth0.\r\n"
+" -l port - Specifies the local port number. Default value is 0\r\n"
+" and the port number is automatically assigned.\r\n"
+" -s size The size of the download buffer for a chunk, in bytes.\r\n"
+" Default is 32K. Note that larger buffer does not imply\r\n"
+" better speed.\r\n"
+" -t timeout - The number of seconds to wait for completion of\r\n"
+" requests and responses. Default is 0 which is 'automatic'.\r\n"
+" %HURL%N\r\n"
+" Two types of providing of URLs are supported:\r\n"
+" 1. tftp like, where host and http_uri are separate parameters\r\n"
+" (example: host /host_uri), and\r\n\"
+" 2. wget-like, where host and host_uri is one parameter.\r\n"
+" (example: host/host_uri)\r\n"
+"\r\n"
+" host - Specifies HTTP Server address.\r\n
+ Can be either IPv4 address or 'http (or https)://addr'\r\n
+ Can use addresses resolvable by DNS as well. \r\n
+ Port can be specified after ':' if needed. \r\n
+ By default port 80 is used.\r\n"
+" http_uri - HTTP server URI to download the file.\r\n"
+"\r\n"
+" localfilepath - Local destination file path.\r\n"
+".SH DESCRIPTION\r\n"
+" \r\n"
+"NOTES:\r\n"
+" 1. The HTTP command allows geting of the file specified by its 'http_uri'\r\n"
+" path from the HTTP server specified by its 'host' IPv4 address. If the\r\n"
+" optional 'localfilepath' parameter is provided, the downloaded file is\r\n"
+" stored locally using the provided file path. If the local file path is\r\n"
+" not specified, the file is stored in the current directory using the file\r\n"
+" server's name.\r\n"
+" 2. Before using the HTTP command, the network interface intended to be\r\n"
+" used to retrieve the file must be configured. This configuration may be\r\n"
+" done by means of the 'ifconfig' command.\r\n"
+" 3. If a network interface is defined with the '-i' option then only this\r\n"
+" interface will be used to retrieve the remote file. Otherwise, all network\r\n"
+" interfaces are tried in the order they have been discovered during the\r\n"
+" DXE phase.\r\n"
+".SH EXAMPLES\r\n"
+" \r\n"
+"EXAMPLES:\r\n"
+" * To get the file "dir1/file1.dat" from the HTTP server 192.168.1.1, port 8080, and\r\n"
+" store it as file2.dat in the current directory :\r\n"
+" fs0:\> http 192.168.1.1:8080 dir1/file1.dat file2.dat\r\n"
+" * To get the file /image.bin via HTTPS from server 192.168.1.1 at port 443 \r\n"
+" (default HTTPS port), and store it in the current directory: \r\n"
+" fs0:\> http https://192.168.1.1 image.bin\r\n"
+" To get an index file from http://google.com and place it into the \r\n"
+" current directory:\r\n"
+" fs0:\> http google.com index.html"
+".SH RETURNVALUES\r\n"
The line ending with "google.com index.html" lacks the "\r\n"
terminator. Because of that, the help text is printed as follows:

To get an index file from http://google.com and place it into the
current directory:
fs0:\> http google.com index.html.SH RETURNVALUES

Thanks
Laszlo


Re: [PATCH v2 2/2] OvmfPkg: enable HttpDynamicCommand

Laszlo Ersek
 

On 07/22/20 22:54, Vladimir Olovyannikov via groups.io wrote:
Enable HttpDynamicCommand (Shell command "http") for OvmfPkg platforms.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2857

Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@...>
---
OvmfPkg/OvmfPkgIa32.dsc | 4 ++++
OvmfPkg/OvmfPkgIa32.fdf | 1 +
OvmfPkg/OvmfPkgIa32X64.dsc | 4 ++++
OvmfPkg/OvmfPkgIa32X64.fdf | 1 +
OvmfPkg/OvmfPkgX64.dsc | 4 ++++
OvmfPkg/OvmfPkgX64.fdf | 1 +
OvmfPkg/OvmfXen.dsc | 4 ++++
OvmfPkg/OvmfXen.fdf | 1 +
8 files changed, 20 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9178ffeb71cb..78413e5ecaae 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -883,6 +883,10 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+ ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf
index 2b9a6b58015f..c07b775d0a2d 100644
--- a/OvmfPkg/OvmfPkgIa32.fdf
+++ b/OvmfPkg/OvmfPkgIa32.fdf
@@ -293,6 +293,7 @@ [FV.DXEFV]

!if $(TOOL_CHAIN_TAG) != "XCODE5"
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
!endif
INF ShellPkg/Application/Shell/Shell.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a665f78f0dc7..92e08fb8c072 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -897,6 +897,10 @@ [Components.X64]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+ ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf
index 83ff6aef2e8c..9adf1525c135 100644
--- a/OvmfPkg/OvmfPkgIa32X64.fdf
+++ b/OvmfPkg/OvmfPkgIa32X64.fdf
@@ -294,6 +294,7 @@ [FV.DXEFV]

!if $(TOOL_CHAIN_TAG) != "XCODE5"
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
!endif
INF ShellPkg/Application/Shell/Shell.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 17f345acf4ee..68ed86ef53ce 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -893,6 +893,10 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+ ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf
index 83ff6aef2e8c..9adf1525c135 100644
--- a/OvmfPkg/OvmfPkgX64.fdf
+++ b/OvmfPkg/OvmfPkgX64.fdf
@@ -294,6 +294,7 @@ [FV.DXEFV]

!if $(TOOL_CHAIN_TAG) != "XCODE5"
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
!endif
INF ShellPkg/Application/Shell/Shell.inf
diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc
index 782803cb2787..1ed7176d26c5 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -675,6 +675,10 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+ ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf
index d9ee14b484a0..c7d4d1853027 100644
--- a/OvmfPkg/OvmfXen.fdf
+++ b/OvmfPkg/OvmfXen.fdf
@@ -363,6 +363,7 @@ [FV.DXEFV]

!if $(TOOL_CHAIN_TAG) != "XCODE5"
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
!endif
INF ShellPkg/Application/Shell/Shell.inf
Reviewed-by: Laszlo Ersek <lersek@...>


Re: [PATCH v2 1/2] ArmVirtPkg: enable HttpDynamiCommand

Laszlo Ersek
 

On 07/22/20 22:54, Vladimir Olovyannikov via groups.io wrote:
Enable HttpDynamicCommand (http Shell command)
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2857

Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@...>
---
ArmVirtPkg/ArmVirt.dsc.inc | 4 ++++
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 1 +
ArmVirtPkg/ArmVirtXen.fdf | 1 +
3 files changed, 6 insertions(+)

diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index cf44fc73890b..f39f7e903ff9 100644
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -377,6 +377,10 @@ [Components.common]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+ ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index a2f4bd62c846..6eade7e50ff7 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -103,6 +103,7 @@ [FV.FvMain]
#
INF ShellPkg/Application/Shell/Shell.inf
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+ INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf

#
diff --git a/ArmVirtPkg/ArmVirtXen.fdf b/ArmVirtPkg/ArmVirtXen.fdf
index f708878f4965..8fbbc2313aff 100644
--- a/ArmVirtPkg/ArmVirtXen.fdf
+++ b/ArmVirtPkg/ArmVirtXen.fdf
@@ -182,6 +182,7 @@ [FV.FvMain]
#
INF ShellPkg/Application/Shell/Shell.inf
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+ INF ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand.inf
INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf

#
Reviewed-by: Laszlo Ersek <lersek@...>


Re: [PATCH 1/1] EmbeddedPkg: fix gcc build errors in AndroidBootImgLib

Leif Lindholm
 

Series pushed as d0da48f112de..e43d0884ed93, with parentheses dropped
as per Laszlo's comment, and Pierre added as reported-by for this
flavour of this patch.

Regards,

Leif

On Wed, Jul 22, 2020 at 22:34:52 +0200, Laszlo Ersek wrote:
On 07/21/20 14:50, Leif Lindholm wrote:
Commit dbd546a32d5a
("BaseTools: Add gcc flag to warn on void* pointer arithmetic")
does its work and triggers build errors in this library.
Update the affected code to build correctly again.

Cc: Pierre Gondois <pierre.gondois@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Bob Feng<bob.c.feng@...>
Signed-off-by: Leif Lindholm <leif@...>
---

Pierre - can you please ensure to CC Arm maintainers when proposing
changes to Arm build flags? (And build test all the top-level edk2
packages *cough*.)
or we could perhaps introduce

EmbeddedPkg/EmbeddedPkg.ci.yaml


Bob - can you please ensure Arm maintainers have commented on changes to
global build flags?
(Would it be possible to break up tools_def.template into separate
arch-specific include files so we could have GetMaintainer.py be
more helpful for this?)

Laszlo - you're not formally an EmbeddedPkg reviewer, but Ard is out for
another couple of weeks. But since the Linaro CI is currently broken and
the fix is trivial, could you have a look please?

EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
index e1036954ee58..15b5bf451330 100644
--- a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
+++ b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
@@ -97,7 +97,7 @@ AndroidBootImgGetKernelInfo (
ASSERT (IS_VALID_ANDROID_PAGE_SIZE (Header->PageSize));

*KernelSize = Header->KernelSize;
- *Kernel = BootImg + Header->PageSize;
+ *Kernel = (VOID *)((UINTN)BootImg + Header->PageSize);
return EFI_SUCCESS;
}
Header->PageSize has type UINT32, so this is OK (the addition is
performed in UINTN, so the conversion back to VOID* is from UINTN).

@@ -341,7 +341,7 @@ AndroidBootImgUpdateFdt (

Status = AndroidBootImgSetProperty64 (UpdatedFdtBase, ChosenNode,
"linux,initrd-end",
- (UINTN)(RamdiskData + RamdiskSize));
+ ((UINTN)RamdiskData + RamdiskSize));
if (EFI_ERROR (Status)) {
goto Fdt_Exit;
}
RamdiskSize is a UINTN, so this is OK too.

(You could even strip the outer parentheses:

(UINTN)RamdiskData + RamdiskSize
)

Reviewed-by: Laszlo Ersek <lersek@...>

Thanks
Laszlo


Re: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header

Javeed, Ashraf
 

Liming.
Thanks for completing the review.
This is just a comment change ask and I can mend the comment to send again.

Ashraf

-----Original Message-----
From: Gao, Liming <liming.gao@...>
Sent: Thursday, July 23, 2020 3:18 PM
To: Javeed, Ashraf <ashraf.javeed@...>; devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>
Subject: RE: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL
header

Asharf:


-----Original Message-----
From: Javeed, Ashraf <ashraf.javeed@...>
Sent: 2020年7月22日 23:22
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming
<liming.gao@...>
Subject: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Introducing the Cxl.h as the main header file to support all versions of Compute
Express Link Specification register definitions.

Signed-off-by: Ashraf Javeed <ashraf.javeed@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
--

V2: Indentation and double declaration fix, copyright date update

V3: Copyright date fix
---
MdePkg/Include/IndustryStandard/Cxl.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Cxl.h
b/MdePkg/Include/IndustryStandard/Cxl.h
new file mode 100644
index 0000000000..632aa146d0
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl.h
@@ -0,0 +1,22 @@
+/** @file
+ Support for the latest CXL standard
+
+ The main header to reference all versions of CXL Base specification
+ registers from the MDE

Does MDE means MdePkg? I think "from the MDE" can be removed.
With this change, Reviewed-by: Liming Gao <liming.gao@...>

Thanks
Liming
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL_MAIN_H_
+#define _CXL_MAIN_H_
+
+#include <IndustryStandard/Cxl11.h>
+//
+// CXL assigned new Vendor ID
+//
+#define CXL_DVSEC_VENDOR_ID 0x1E98
+
+#endif
+
--
2.21.0.windows.1


Re: [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers

Javeed, Ashraf
 

Liming;
My response inline.

Thanks for the review.
Ashraf

-----Original Message-----
From: Gao, Liming <liming.gao@...>
Sent: Thursday, July 23, 2020 3:36 PM
To: devel@edk2.groups.io; Javeed, Ashraf <ashraf.javeed@...>
Cc: Kinney, Michael D <michael.d.kinney@...>
Subject: RE: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard:
CXL 1.1 Registers

Ashraf:

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed,
Ashraf
Sent: 2020年7月22日 23:22
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming
<liming.gao@...>
Subject: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1
Registers

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Register definitions from chapter 7 of Compute Express Link Specification
Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC
structure header, led to the inclusion of upgraded Pci.h.

Signed-off-by: Ashraf Javeed <ashraf.javeed@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
--

V2: Indentation and double declaration fix, copyright date update

V3: Copyright date fix
---
MdePkg/Include/IndustryStandard/Cxl11.h | 569
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++
MdePkg/Include/IndustryStandard/Pci.h | 6 ++----
2 files changed, 571 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h
b/MdePkg/Include/IndustryStandard/Cxl11.h
new file mode 100644
index 0000000000..a261bb3fae
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl11.h
@@ -0,0 +1,569 @@
+/** @file
+ CXL 1.1 Register definitions
+
+ This file contains the register definitions based on the Compute
+ Express Link
+ (CXL) Specification Revision 1.1.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL11_H_
+#define _CXL11_H_
+
+#include <IndustryStandard/Pci.h>
+//
+// DVSEC Vendor ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 -
+Table 58 // (subject to change as per CXL assigned Vendor ID) //
+#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
+
+//
+// CXL Flex Bus Device default device and function number // Compute
+Express Link Specification Revision: 1.1 - Chapter 7.1.1 //
+#define CXL_DEV_DEV 0
+#define CXL_DEV_FUNC 0
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// The PCIe DVSEC for Flex Bus Device
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 MemHwInitMode : 1; // bit 3
+ UINT16 HdmCount : 2; // bit 4..5
+ UINT16 Reserved1 : 8; // bit 6..13
+ UINT16 ViralCapable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;

This line should have one space between } and Bits. Otherwise, ECC will report
the issue.
Please fix it in this header file.

}Bits ==> } Bits

Thanks
Liming
I did run the ECC Python script and it did not report any issues.
I shall check again and make the fixed if required.

+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CacheSfCoverage : 5; // bit 3..7
+ UINT16 CacheSfGranularity : 3; // bit 8..10
+ UINT16 CacheCleanEviction : 1; // bit 11
+ UINT16 Reserved1 : 2; // bit 12..13
+ UINT16 ViralEnable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 14; // bit 0..13
+ UINT16 ViralStatus : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 1; // bit 2
+ UINT16 Reserved4 : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 14; // bit 2..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
+
+typedef union {
+ struct {
+ UINT16 ConfigLock : 1; // bit 0
+ UINT16 Reserved1 : 15; // bit 1..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
+
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
+
+//
+// Flex Bus Device DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1,
+Table 58 //
+#define FLEX_BUS_DEVICE_DVSEC_ID 0
+
+//
+// PCIe DVSEC for Flex Bus Device
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1,
+Figure 95 // typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
// offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
DesignatedVendorSpecificHeader2; // offset 8
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability;
// offset 10
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl;
// offset 12
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus;
// offset 14
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2;
// offset 16
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2;
// offset 18
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock;
// offset 20
+ UINT16 Reserved; // offset 22
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH
DeviceRange1SizeHigh; // offset 24
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW
DeviceRange1SizeLow; // offset 28
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH
DeviceRange1BaseHigh; // offset 32
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW
DeviceRange1BaseLow; // offset 36
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH
DeviceRange2SizeHigh; // offset 40
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW
DeviceRange2SizeLow; // offset 44
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH
DeviceRange2BaseHigh; // offset 48
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW
DeviceRange2BaseLow; // offset 52
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
+///@}
+
+///
+/// PCIe DVSEC for FLex Bus Port
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 Reserved : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 Retimer1Present : 1; // bit 8
+ UINT16 Retimer2Present : 1; // bit 9
+ UINT16 Reserved2 : 6; // bit 10..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
+ UINT16 Reserved2 : 5; // bit 11..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
+
+//
+// Flex Bus Port DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3,
+Table 62 //
+#define FLEX_BUS_PORT_DVSEC_ID 7
+
+//
+// PCIe DVSEC for Flex Bus Port
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3,
+Figure 99 // typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
// offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
DesignatedVendorSpecificHeader2; // offset 8
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability;
// offset 10
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl;
// offset 12
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus;
// offset 14
+} CXL_1_1_DVSEC_FLEX_BUS_PORT;
+///@}
+
+///
+/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
+///
+
+/// The CXL.Cache and CXL.Memory Architectural register definitions ///
+Based on chapter 7.2.2 of Compute Express Link Specification Revision:
+1.1 ///@{
+
+#define CXL_CAPABILITY_HEADER_OFFSET 0
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23
+ UINT32 ArraySize : 8; // bit 24..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CAPABILITY_HEADER;
+
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_RAS_CAPABILITY_HEADER;
+
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_SECURITY_CAPABILITY_HEADER;
+
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_CAPABILITY_HEADER;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParity : 1; // bit 0..0
+ UINT32 CacheAddressParity : 1; // bit 1..1
+ UINT32 CacheByteEnableParity : 1; // bit 2..2
+ UINT32 CacheDataEcc : 1; // bit 3..3
+ UINT32 MemDataParity : 1; // bit 4..4
+ UINT32 MemAddressParity : 1; // bit 5..5
+ UINT32 MemByteEnableParity : 1; // bit 6..6
+ UINT32 MemDataEcc : 1; // bit 7..7
+ UINT32 ReInitThreshold : 1; // bit 8..8
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9
+ UINT32 PoisonReceived : 1; // bit 10..10
+ UINT32 ReceiverOverflow : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParityMask : 1; // bit 0..0
+ UINT32 CacheAddressParityMask : 1; // bit 1..1
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2
+ UINT32 CacheDataEccMask : 1; // bit 3..3
+ UINT32 MemDataParityMask : 1; // bit 4..4
+ UINT32 MemAddressParityMask : 1; // bit 5..5
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6
+ UINT32 MemDataEccMask : 1; // bit 7..7
+ UINT32 ReInitThresholdMask : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
+ UINT32 PoisonReceivedMask : 1; // bit 10..10
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3
+ UINT32 MemDataParitySeverity : 1; // bit 4..4
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
+ UINT32 MemDataEccSeverity : 1; // bit 7..7
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEcc : 1; // bit 0..0
+ UINT32 MemoryDataEcc : 1; // bit 1..1
+ UINT32 CrcThreshold : 1; // bit 2..2
+ UINT32 RetryThreshold : 1; // bit 3..3
+ UINT32 CachePoisonReceived : 1; // bit 4..4
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5
+ UINT32 PhysicalLayerError : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEccMask : 1; // bit 0..0
+ UINT32 MemoryDataEccMask : 1; // bit 1..1
+ UINT32 CrcThresholdMask : 1; // bit 2..2
+ UINT32 RetryThresholdMask : 1; // bit 3..3
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 FirstErrorPointer : 4; // bit 0..3
+ UINT32 Reserved1 : 5; // bit 4..8
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
+ UINT32 Reserved2 : 3; // bit 10..12
+ UINT32 PoisonEnabled : 1; // bit 13..13
+ UINT32 Reserved3 : 18; // bit 14..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_ERROR_CAPABILITIES_AND_CONTROL;
+
+typedef struct {
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS
UncorrectableErrorStatus;
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK
UncorrectableErrorMask;
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY
UncorrectableErrorSeverity;
+ CXL_CORRECTABLE_ERROR_STATUS
CorrectableErrorStatus;
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;
+ CXL_ERROR_CAPABILITIES_AND_CONTROL
ErrorCapabilitiesAndControl;
+ UINT32 HeaderLog[16];
+} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT32 DeviceTrustLevel : 2; // bit 0..1
+ UINT32 Reserved : 30; // bit 2..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_SECURITY_POLICY;
+
+typedef struct {
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;
+} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23
+ UINT64 NumRetryReceived : 5; // bit 24..28
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33
+ UINT64 WrPtrReceived : 8; // bit 34..41
+ UINT64 EchoEseqReceived : 8; // bit 42..49
+ UINT64 NumFreeBufReceived : 8; // bit 50..57
+ UINT64 Reserved : 6; // bit 58..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 LlReset : 1; // bit 0..0
+ UINT16 LlInitStall : 1; // bit 1..1
+ UINT16 LlCrdStall : 1; // bit 2..2
+ UINT16 InitState : 2; // bit 3..4
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12
+ UINT16 Reserved : 3; // bit 13..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_LINK_LAYER_CONTROL_AND_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_TX_CREDIT_STATUS;
+
+typedef union {
+ struct {
+ UINT32 AckForceThreshold : 8; // bit 0..7
+ UINT32 AckFLushRetimer : 10; // bit 8..17
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 MdhDisable : 1; // bit 0..0
+ UINT32 Reserved : 31; // bit 1..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_DEFEATURE;
+
+typedef struct {
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;
+ CXL_LINK_LAYER_CONTROL_AND_STATUS
LinkLayerControlStatus;
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL
LinkLayerRxCreditControl;
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS
LinkLayerRxCreditReturnStatus;
+ CXL_LINK_LAYER_TX_CREDIT_STATUS
LinkLayerTxCreditStatus;
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL
LinkLayerAckTimerControl;
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;
+} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
+
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_IO_ARBITRATION_CONTROL;
+
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
+///@}
+
+/// The CXL.RCRB base register definition /// Based on chapter 7.3 of
+Compute Express Link Specification Revision: 1.1 ///@{ typedef union {
+ struct {
+ UINT64 RcrbEnable : 1; // bit 0..0
+ UINT64 Reserved : 12; // bit 1..12
+ UINT64 RcrbBaseAddress : 51; // bit 13..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_RCRB_BASE;
+///@}
+
+#pragma pack()
+
+//
+// CXL Downstream / Upstream Port RCRB space register offsets //
+Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 -
+Figure 97 //
+#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
+#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
+#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET
0x100
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci.h
b/MdePkg/Include/IndustryStandard/Pci.h
index 8ed96b992a..42c00ac762 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.

-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef
_PCI_H_ #define _PCI_H_

-#include <IndustryStandard/Pci30.h>
-#include <IndustryStandard/PciExpress21.h> -#include
<IndustryStandard/PciExpress30.h>
+#include <IndustryStandard/PciExpress50.h>
#include <IndustryStandard/PciCodeId.h>

#endif
--
2.21.0.windows.1



Re: [edk2-platforms][PATCH 1/1] Platforms/RaspberryPi: Fix BIOS Release Date and System Manufacturer

Leif Lindholm
 

On Mon, Jul 20, 2020 at 17:15:07 +0100, Pete Batard wrote:
Per SMBIOS specs, The Type 0 BIOS Release Date is not a free form field but
must be specified in a US middle-endian format (mm/dd/yyyy), so make sure
we populate it accordingly by converting gcc's __DATE__ string. This is
required for platforms like Windows, that fail to parse the date otherwise.

Also, the system manufacturer should not be set to the same value as the
board manufacturer for the Type 1 strings, as, on the Raspberry Pi, this is
not representative of the actual manufacturer of the system, which is the
Raspberry Pi Foundation always.

It should be noted that we do not expect other compilers than ones using
a __DATE__ format similar to gcc's to be used for the foreseeable future.

Signed-off-by: Pete Batard <pete@...>
---
Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 31 ++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
index d5fb843d43ce..fb775d00feba 100644
--- a/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
+++ b/Platform/RaspberryPi/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -119,11 +119,12 @@ SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {

CHAR8 mBiosVendor[128] = "EDK2";
CHAR8 mBiosVersion[128] = "EDK2-DEV";
+CHAR8 mBiosDate[12] = "00/00/0000";

CHAR8 *mBIOSInfoType0Strings[] = {
mBiosVendor, // Vendor
mBiosVersion, // Version
- __DATE__ " " __TIME__, // Release Date
+ mBiosDate, // Release Date
NULL
};

@@ -149,7 +150,7 @@ CHAR8 mSysInfoSerial[sizeof (UINT64) * 2 + 1];
CHAR8 mSysInfoSKU[sizeof (UINT64) * 2 + 1];

CHAR8 *mSysInfoType1Strings[] = {
- mSysInfoManufName,
+ "Raspberry Pi Foundation",
mSysInfoProductName,
mSysInfoVersionName,
mSysInfoSerial,
@@ -626,6 +627,28 @@ BIOSInfoUpdateSmbiosType0 (
INTN i;
INTN State = 0;
INTN Value[2];
+ INTN Year = (__DATE__[7] == '?' ? 1900 \
+ : (((__DATE__[7] - '0') * 1000 ) \
+ + (__DATE__[8] - '0') * 100 \
+ + (__DATE__[9] - '0') * 10 \
+ + __DATE__[10] - '0'));
+ INTN Month = ( __DATE__ [2] == '?' ? 1 \
+ : __DATE__ [2] == 'n' ? ( \
+ __DATE__ [1] == 'a' ? 1 : 6) \
+ : __DATE__ [2] == 'b' ? 2 \
+ : __DATE__ [2] == 'r' ? ( \
+ __DATE__ [0] == 'M' ? 3 : 4) \
+ : __DATE__ [2] == 'y' ? 5 \
+ : __DATE__ [2] == 'l' ? 7 \
+ : __DATE__ [2] == 'g' ? 8 \
+ : __DATE__ [2] == 'p' ? 9 \
+ : __DATE__ [2] == 't' ? 10 \
+ : __DATE__ [2] == 'v' ? 11 \
+ : 12);
+ INTN Day = ( __DATE__[4] == '?' ? 1 \
+ : ((__DATE__[4] == ' ' ? 0 : \
+ ((__DATE__[4] - '0') * 10)) \
+ + __DATE__[5] - '0'));
So, this hunk is very neat, but nigh-on unreviewable.
I.e. we should defintely have it - but only once.

Could you break this up into some macros to go into some generic
helper lib? (I don't have a better idea than EmbeddedPkg TimeBaseLib,
but then that is already included in this module.)

Would you be OK to break that snippet out separate?

/
Leif

// Populate the Firmware major and minor.
Status = mFwProtocol->GetFirmwareRevision (&EpochSeconds);
@@ -648,6 +671,10 @@ BIOSInfoUpdateSmbiosType0 (
mBiosVendor, sizeof (mBiosVendor));
UnicodeStrToAsciiStrS ((CHAR16*)PcdGetPtr (PcdFirmwareVersionString),
mBiosVersion, sizeof (mBiosVersion));
+ ASSERT (Year >= 0 && Year <= 9999);
+ ASSERT (Month >= 1 && Month <= 12);
+ ASSERT (Day >= 1 && Day <= 31);
+ AsciiSPrint (mBiosDate, sizeof (mBiosDate), "%02d/%02d/%04d", Month, Day, Year);

// Look for a "x.y" numeric string anywhere in mBiosVersion and
// try to parse it to populate the BIOS major and minor.
--
2.21.0.windows.1


Re: [PATCH 1/1] EmbeddedPkg: fix gcc build errors in AndroidBootImgLib

Leif Lindholm
 

On Wed, Jul 22, 2020 at 22:34:52 +0200, Laszlo Ersek wrote:
On 07/21/20 14:50, Leif Lindholm wrote:
Commit dbd546a32d5a
("BaseTools: Add gcc flag to warn on void* pointer arithmetic")
does its work and triggers build errors in this library.
Update the affected code to build correctly again.

Cc: Pierre Gondois <pierre.gondois@...>
Cc: Laszlo Ersek <lersek@...>
Cc: Bob Feng<bob.c.feng@...>
Signed-off-by: Leif Lindholm <leif@...>
---

Pierre - can you please ensure to CC Arm maintainers when proposing
changes to Arm build flags? (And build test all the top-level edk2
packages *cough*.)
or we could perhaps introduce

EmbeddedPkg/EmbeddedPkg.ci.yaml
Ah, do those get picked up automagically?
If so we should definitely do that, as well as for ArmPkg.


Bob - can you please ensure Arm maintainers have commented on changes to
global build flags?
(Would it be possible to break up tools_def.template into separate
arch-specific include files so we could have GetMaintainer.py be
more helpful for this?)

Laszlo - you're not formally an EmbeddedPkg reviewer, but Ard is out for
another couple of weeks. But since the Linaro CI is currently broken and
the fix is trivial, could you have a look please?

EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
index e1036954ee58..15b5bf451330 100644
--- a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
+++ b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
@@ -97,7 +97,7 @@ AndroidBootImgGetKernelInfo (
ASSERT (IS_VALID_ANDROID_PAGE_SIZE (Header->PageSize));

*KernelSize = Header->KernelSize;
- *Kernel = BootImg + Header->PageSize;
+ *Kernel = (VOID *)((UINTN)BootImg + Header->PageSize);
return EFI_SUCCESS;
}
Header->PageSize has type UINT32, so this is OK (the addition is
performed in UINTN, so the conversion back to VOID* is from UINTN).

@@ -341,7 +341,7 @@ AndroidBootImgUpdateFdt (

Status = AndroidBootImgSetProperty64 (UpdatedFdtBase, ChosenNode,
"linux,initrd-end",
- (UINTN)(RamdiskData + RamdiskSize));
+ ((UINTN)RamdiskData + RamdiskSize));
if (EFI_ERROR (Status)) {
goto Fdt_Exit;
}
RamdiskSize is a UINTN, so this is OK too.

(You could even strip the outer parentheses:

(UINTN)RamdiskData + RamdiskSize
)
Yes, I'll do that.
I just found the moving a single character aesthetically pleasing :)

Reviewed-by: Laszlo Ersek <lersek@...>
Thanks!

/
Leif


Re: [PATCH v1 2/2] EmbeddedPkg: Add cast from (void*) for VS2017 build

Leif Lindholm
 

On Wed, Jul 22, 2020 at 23:11:40 +0200, Laszlo Ersek wrote:
diff --git a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
index e1036954ee586dfc30266eec2897d71bfc949038..bbe0d41018b3d5665c72ee61efe737ae57b1b2eb 100644
--- a/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
+++ b/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.c
@@ -1,6 +1,6 @@
/** @file

- Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2013-2020, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2017, Linaro. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -97,7 +97,7 @@ AndroidBootImgGetKernelInfo (
ASSERT (IS_VALID_ANDROID_PAGE_SIZE (Header->PageSize));

*KernelSize = Header->KernelSize;
- *Kernel = BootImg + Header->PageSize;
+ *Kernel = (UINT8*)BootImg + Header->PageSize;
The reason I prefer my version, although this one would also solve the
compilation error, is that I really don't like casts to char * (which
this effectively is) as a workaround.

The problem I have with it is that a cast is a signal of intent (this
thing that we have been viewing as an X should now be seen as a Y) -
and the intent here is simply to get the side effect that a char has a
known size of 1 (whereas a void doesn't).
I will admit it is the first time I have seen it used for this purpose
:)
Personally I'd be OK with either fix (yours or Pierre's); to me both
express the exact same thing -- move Header->PageSize bytes past
BootImg.

Viewed from a portability perspective, Pierre's patch is actually more
portable (per C standard); as UINT8 stands for "unsigned char", and that
is called "object representation" by the C standard:
Because there was a time when C didn't have void pointers.

6.2.6 Representations of types
6.2.6.1 General

3 Values stored in unsigned bit-fields and objects of type unsigned
char shall be represented using a pure binary notation. (Footnote
40.)

4 Values stored in non-bit-field objects of any other object type
consist of n * CHAR_BIT bits, where n is the size of an object of
that type, in bytes. The value may be copied into an object of type
unsigned char [n] (e.g., by memcpy); the resulting set of bytes is
called the object representation of the value.

Footnote 40: [...] A byte contains CHAR_BIT bits, and the values of
type unsigned char range from 0 to (2^CHAR_BIT)-1.
Further references:

6.2.5 Types

27 A pointer to void shall have the same representation and alignment
requirements as a pointer to a character type. Footnote 39 [...]

Footnote 39: The same representation and alignment requirements are
meant to imply interchangeability as arguments to
functions, return values from functions, and members of
unions.
6.3.2.3 Pointers

7 [...] When a pointer to an object is converted to a pointer to a
character type, the result points to the lowest addressed byte of
the object. Successive increments of the result, up to the size of
the object, yield pointers to the remaining bytes of the object.
6.5 Expressions

6 The effective type of an object for an access to its stored value is
the declared type of the object, if any. (Footnote 75.) [...] If a
value is copied into an object having no declared type using memcpy
or memmove, or is copied as an array of character type, then the
effective type of the modified object for that access and for
subsequent accesses that do not modify the value is the effective
type of the object from which the value is copied, if it has one.
Footnote 75: Allocated objects have no declared type.
(This is one of the most exciting parts of the standard BTW: it means
that, if you malloc() 4 bytes, and copy a local uint32_t variable into
it, with an open-coded (unsigned char*) loop, then the effective type of
the dynamically allocated object becomes uint32_t for subsequent reads!
Which means for example, considering the effective type rules strictly,
that reading the dynamically allocated object post-copy, even via
*correctly aligned* (uint16_t*) pointers, is undefined behavior.)
Which is only made funnier by the fact that you cannot implement a
compliant malloc that returns a pointer with less than your largest
data type alignment requirement.

7 An object shall have its stored value accessed only by an lvalue
expression that has one of the following types (Footnote 76):
- [...]
- a character type.

Footnote 76: The intent of this list is to specify those circumstances
in which an object may or may not be aliased.
Whereas converting a (VOID*) to UINTN (and maybe back) is only covered
here (if I remember correctly):

6.3 Conversions
6.3.2 Other operands
6.3.2.3 Pointers

5 An integer may be converted to any pointer type. Except as
previously specified, the result is implementation-defined, might
not be correctly aligned, might not point to an entity of the
referenced type, and might be a trap representation. (Footnote 56)

6 Any pointer type may be converted to an integer type. Except as
previously specified, the result is implementation-defined. If the
result cannot be represented in the integer type, the behavior is
undefined. The result need not be in the range of values of any
integer type.

Footnote 56: The mapping functions for converting a pointer to an
integer or an integer to a pointer are intended to be
consistent with the addressing structure of the execution
environment.
So my only point is that (void*) --> (unsigned char *) has no
"implementation-defined" dependencies, while (VOID*) --> (UINTN) is
implementation-defined.
Sure. But (unsigned char *) still reads as "pointer to region
containing stuff with 1-byte alignment requirements", whereas (void *)
reads as pointer to region containing
...well-let's-not-worry-about-that-for now...

See also https://martinfowler.com/bliki/CodeSmell.html

(The dependency exploited in edk2 is that UINTN
is always just as wide as (VOID*).)
Yes. I wouldn't like to to try to port EDK2 to CHERI.

I actually find most of these things easier to reason about in the
context of fat pointers. But that case also emphasises the danger
presented by the special treatment of unsigned char * (for legacy
purposes) in the standard is.
In a system where pointers contained information about the
size/alignment of the element pointed to, that would now in hardware
encode "1-byte alignment" instead of "unknown alignment". And would be
dereferenced without raising an exception.

But, given both patches are for edk2, where UINTN <-> (VOID*)
interchangeability is guaranteed, I'm equally fine with both patches.
Thanks!

/
Leif


Re: [PATCH 2/2] OvmfPkg: enable HttpDynamicCommand

Laszlo Ersek
 

On 07/22/20 22:02, Vladimir Olovyannikov wrote:
Hi Laszlo,

Thank you for reviewing the patchset.
Thank *you* for submitting the set, at my request! :)

-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: Wednesday, July 22, 2020 12:52 PM
To: Vladimir Olovyannikov <vladimir.olovyannikov@...>;
devel@edk2.groups.io
Cc: Ard Biesheuvel <ard.biesheuvel@...>; Leif Lindholm
<leif@...>
Subject: Re: [PATCH 2/2] OvmfPkg: enable HttpDynamicCommand

On 07/21/20 19:23, Vladimir Olovyannikov wrote:
Enable HttpDynamicCommand (Shell command "http") for OvmfPkg
platforms

Signed-off-by: Vladimir Olovyannikov
<vladimir.olovyannikov@...>
---
OvmfPkg/OvmfPkgIa32.dsc | 6 ++++++
OvmfPkg/OvmfPkgIa32X64.dsc | 6 ++++++
OvmfPkg/OvmfPkgX64.dsc | 6 ++++++
OvmfPkg/OvmfXen.dsc | 6 ++++++
4 files changed, 24 insertions(+)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index
9178ffeb71cb..aed3a73c0172 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -883,6 +883,12 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+
+
ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand
.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellComma
nd.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc
b/OvmfPkg/OvmfPkgIa32X64.dsc
index a665f78f0dc7..6c07326cc0fe 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -897,6 +897,12 @@ [Components.X64]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+
+
ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand
.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellComma
nd.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index
17f345acf4ee..d5e5bcf8e66c 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -893,6 +893,12 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+
+
ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand
.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellComma
nd.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index
782803cb2787..fe549502863a 100644
--- a/OvmfPkg/OvmfXen.dsc
+++ b/OvmfPkg/OvmfXen.dsc
@@ -675,6 +675,12 @@ [Components]
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
+
+
ShellPkg/DynamicCommand/HttpDynamicCommand/HttpDynamicCommand
.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ }
+
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellComma
nd.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
Basically same comments as under the ArmVirtPkg patch:

(1) Please mention <https://bugzilla.tianocore.org/show_bug.cgi?id=2857>
in the commit message.
OK, will do. For future contributions related to a BZ ticket - does it mean
that mentioning of BZ id in the cover letter is not enough?
Referencing the BZ in the cover letter only is indeed not ideal; the
cover letter does not get captured in the git history. When submitting a
series for a BZ, it's best to mention the BZ in every patch in the series.

One frequently used format is

"""
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2857
"""

placed near the end of the commit message (just above the Signed-off-by
and similar tags). But other formats are fine too.


(2) Please don't introduce the extra whitespace in the DSC files.

(3) Please also add the new module to the following (FDF) files:

- OvmfPkgIa32.fdf
- OvmfPkgIa32X64.fdf
- OvmfPkgX64.fdf
- OvmfXen.fdf
OK, will do, thanks.

Once you post v2 of this series, with the above points fixed (especially
the
FDF files), I'd like to test the new command (with both ArmVirtQemu and
OVMF).
Sure, that would be great.
Thanks!
Laszlo


Re: [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers

Liming Gao
 

Ashraf:

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed, Ashraf
Sent: 2020年7月22日 23:22
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>
Subject: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1 Registers

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Register definitions from chapter 7 of Compute Express Link Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure header, led to the inclusion of upgraded Pci.h.

Signed-off-by: Ashraf Javeed <ashraf.javeed@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
--

V2: Indentation and double declaration fix, copyright date update

V3: Copyright date fix
---
MdePkg/Include/IndustryStandard/Cxl11.h | 569 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdePkg/Include/IndustryStandard/Pci.h | 6 ++----
2 files changed, 571 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/IndustryStandard/Cxl11.h
new file mode 100644
index 0000000000..a261bb3fae
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl11.h
@@ -0,0 +1,569 @@
+/** @file
+ CXL 1.1 Register definitions
+
+ This file contains the register definitions based on the Compute
+ Express Link
+ (CXL) Specification Revision 1.1.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL11_H_
+#define _CXL11_H_
+
+#include <IndustryStandard/Pci.h>
+//
+// DVSEC Vendor ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 -
+Table 58 // (subject to change as per CXL assigned Vendor ID) //
+#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086
+
+//
+// CXL Flex Bus Device default device and function number // Compute
+Express Link Specification Revision: 1.1 - Chapter 7.1.1 //
+#define CXL_DEV_DEV 0
+#define CXL_DEV_FUNC 0
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// The PCIe DVSEC for Flex Bus Device
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 MemHwInitMode : 1; // bit 3
+ UINT16 HdmCount : 2; // bit 4..5
+ UINT16 Reserved1 : 8; // bit 6..13
+ UINT16 ViralCapable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;

This line should have one space between } and Bits. Otherwise, ECC will report the issue.
Please fix it in this header file.

}Bits ==> } Bits

Thanks
Liming
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CacheSfCoverage : 5; // bit 3..7
+ UINT16 CacheSfGranularity : 3; // bit 8..10
+ UINT16 CacheCleanEviction : 1; // bit 11
+ UINT16 Reserved1 : 2; // bit 12..13
+ UINT16 ViralEnable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 14; // bit 0..13
+ UINT16 ViralStatus : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 1; // bit 2
+ UINT16 Reserved4 : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 14; // bit 2..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
+
+typedef union {
+ struct {
+ UINT16 ConfigLock : 1; // bit 0
+ UINT16 Reserved1 : 15; // bit 1..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
+
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
+
+//
+// Flex Bus Device DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1,
+Table 58 //
+#define FLEX_BUS_DEVICE_DVSEC_ID 0
+
+//
+// PCIe DVSEC for Flex Bus Device
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1,
+Figure 95 // typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20
+ UINT16 Reserved; // offset 22
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
+///@}
+
+///
+/// PCIe DVSEC for FLex Bus Port
+///@{
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 Reserved : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 Retimer1Present : 1; // bit 8
+ UINT16 Retimer2Present : 1; // bit 9
+ UINT16 Reserved2 : 6; // bit 10..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
+ UINT16 Reserved2 : 5; // bit 11..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
+
+//
+// Flex Bus Port DVSEC ID
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3,
+Table 62 //
+#define FLEX_BUS_PORT_DVSEC_ID 7
+
+//
+// PCIe DVSEC for Flex Bus Port
+// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3,
+Figure 99 // typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14
+} CXL_1_1_DVSEC_FLEX_BUS_PORT;
+///@}
+
+///
+/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
+///
+
+/// The CXL.Cache and CXL.Memory Architectural register definitions ///
+Based on chapter 7.2.2 of Compute Express Link Specification Revision:
+1.1 ///@{
+
+#define CXL_CAPABILITY_HEADER_OFFSET 0
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23
+ UINT32 ArraySize : 8; // bit 24..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CAPABILITY_HEADER;
+
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_RAS_CAPABILITY_HEADER;
+
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_SECURITY_CAPABILITY_HEADER;
+
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_CAPABILITY_HEADER;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParity : 1; // bit 0..0
+ UINT32 CacheAddressParity : 1; // bit 1..1
+ UINT32 CacheByteEnableParity : 1; // bit 2..2
+ UINT32 CacheDataEcc : 1; // bit 3..3
+ UINT32 MemDataParity : 1; // bit 4..4
+ UINT32 MemAddressParity : 1; // bit 5..5
+ UINT32 MemByteEnableParity : 1; // bit 6..6
+ UINT32 MemDataEcc : 1; // bit 7..7
+ UINT32 ReInitThreshold : 1; // bit 8..8
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9
+ UINT32 PoisonReceived : 1; // bit 10..10
+ UINT32 ReceiverOverflow : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParityMask : 1; // bit 0..0
+ UINT32 CacheAddressParityMask : 1; // bit 1..1
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2
+ UINT32 CacheDataEccMask : 1; // bit 3..3
+ UINT32 MemDataParityMask : 1; // bit 4..4
+ UINT32 MemAddressParityMask : 1; // bit 5..5
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6
+ UINT32 MemDataEccMask : 1; // bit 7..7
+ UINT32 ReInitThresholdMask : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
+ UINT32 PoisonReceivedMask : 1; // bit 10..10
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3
+ UINT32 MemDataParitySeverity : 1; // bit 4..4
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
+ UINT32 MemDataEccSeverity : 1; // bit 7..7
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEcc : 1; // bit 0..0
+ UINT32 MemoryDataEcc : 1; // bit 1..1
+ UINT32 CrcThreshold : 1; // bit 2..2
+ UINT32 RetryThreshold : 1; // bit 3..3
+ UINT32 CachePoisonReceived : 1; // bit 4..4
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5
+ UINT32 PhysicalLayerError : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEccMask : 1; // bit 0..0
+ UINT32 MemoryDataEccMask : 1; // bit 1..1
+ UINT32 CrcThresholdMask : 1; // bit 2..2
+ UINT32 RetryThresholdMask : 1; // bit 3..3
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 FirstErrorPointer : 4; // bit 0..3
+ UINT32 Reserved1 : 5; // bit 4..8
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
+ UINT32 Reserved2 : 3; // bit 10..12
+ UINT32 PoisonEnabled : 1; // bit 13..13
+ UINT32 Reserved3 : 18; // bit 14..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_ERROR_CAPABILITIES_AND_CONTROL;
+
+typedef struct {
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;
+ CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;
+ CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;
+ UINT32 HeaderLog[16];
+} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT32 DeviceTrustLevel : 2; // bit 0..1
+ UINT32 Reserved : 30; // bit 2..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_SECURITY_POLICY;
+
+typedef struct {
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;
+} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23
+ UINT64 NumRetryReceived : 5; // bit 24..28
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33
+ UINT64 WrPtrReceived : 8; // bit 34..41
+ UINT64 EchoEseqReceived : 8; // bit 42..49
+ UINT64 NumFreeBufReceived : 8; // bit 50..57
+ UINT64 Reserved : 6; // bit 58..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 LlReset : 1; // bit 0..0
+ UINT16 LlInitStall : 1; // bit 1..1
+ UINT16 LlCrdStall : 1; // bit 2..2
+ UINT16 InitState : 2; // bit 3..4
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12
+ UINT16 Reserved : 3; // bit 13..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_LINK_LAYER_CONTROL_AND_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_TX_CREDIT_STATUS;
+
+typedef union {
+ struct {
+ UINT32 AckForceThreshold : 8; // bit 0..7
+ UINT32 AckFLushRetimer : 10; // bit 8..17
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 MdhDisable : 1; // bit 0..0
+ UINT32 Reserved : 31; // bit 1..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_DEFEATURE;
+
+typedef struct {
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;
+ CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;
+ CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;
+} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
+
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_IO_ARBITRATION_CONTROL;
+
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
+///@}
+
+/// The CXL.RCRB base register definition /// Based on chapter 7.3 of
+Compute Express Link Specification Revision: 1.1 ///@{ typedef union {
+ struct {
+ UINT64 RcrbEnable : 1; // bit 0..0
+ UINT64 Reserved : 12; // bit 1..12
+ UINT64 RcrbBaseAddress : 51; // bit 13..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_RCRB_BASE;
+///@}
+
+#pragma pack()
+
+//
+// CXL Downstream / Upstream Port RCRB space register offsets //
+Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 -
+Figure 97 //
+#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010
+#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014
+#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h
index 8ed96b992a..42c00ac762 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.

-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_ #define _PCI_H_

-#include <IndustryStandard/Pci30.h>
-#include <IndustryStandard/PciExpress21.h> -#include <IndustryStandard/PciExpress30.h>
+#include <IndustryStandard/PciExpress50.h>
#include <IndustryStandard/PciCodeId.h>

#endif
--
2.21.0.windows.1


Re: [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF

Liming Gao
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Marcello Sylvester Bauer
Sent: 2020年7月22日 21:16
To: devel@edk2.groups.io
Cc: Patrick Rudolph <patrick.rudolph@...>; Christian Walter <christian.walter@...>; Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>
Subject: [edk2-devel] [PATCH v3 2/3] MdePkg/BasePciExpressLib: Support variable size MMCONF

Add support for arbitrary sized MMCONF by introducing a new PCD.

Signed-off-by: Patrick Rudolph <patrick.rudolph@...>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@...>
Cc: Patrick Rudolph <patrick.rudolph@...>
Cc: Christian Walter <christian.walter@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
---
MdePkg/MdePkg.dec | 4 +
MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +-
MdePkg/Include/Library/PciExpressLib.h | 5 +-
MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 216 +++++++++++++++++---
4 files changed, 193 insertions(+), 38 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..02e736a01126 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
# @Prompt PCI Express Base Address. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a + ## This value is used to set the size of PCI express hierarchy. The default is 256 MB.+ # @Prompt PCI Express Base Size.+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x0FFFFFFF|UINT64|0x0000000f+ ## Default current ISO 639-2 language: English & French. # @Prompt Default Value of LangCodes Variable. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001cdiff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf

[Liming] 256M is 0x10000000. PCD value is 0x0FFFFFFF. Does it mean that the default value is 256M - 1?

Thanks
Liming

index a7edb74cde71..12734b022ac7 100644
--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
@@ -1,7 +1,7 @@
## @file-# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.+# Instance of PCI Express Library using the variable size PCI Express MMIO window. #-# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform+# PCI Express Library that uses the variable size PCI Express MMIO window to perform # PCI Configuration cycles. Layers on top of an I/O Library instance. # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>@@ -38,4 +38,4 @@ [LibraryClasses]
[Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES-+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMESdiff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h
index 826fdcf7db6c..d78193a0a352 100644
--- a/MdePkg/Include/Library/PciExpressLib.h
+++ b/MdePkg/Include/Library/PciExpressLib.h
@@ -2,8 +2,9 @@
Provides services to access PCI Configuration Space using the MMIO PCI Express window. This library is identical to the PCI Library, except the access method for performing PCI- configuration cycles must be through the 256 MB PCI Express MMIO window whose base address- is defined by PcdPciExpressBaseAddress.+ configuration cycles must be through the PCI Express MMIO window whose base address+ is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patentdiff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
index 99a166c3609b..0311ecb3025f 100644
--- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
+++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c
@@ -22,7 +22,8 @@
/** Assert the validity of a PCI address. A valid PCI address should contain 1's- only in the low 28 bits.+ only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real+ number of PCI busses in this segment. @param A The address to validate. @@ -79,6 +80,24 @@ GetPciExpressBaseAddress (
return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } +/**+ Gets the size of PCI Express.++ This internal functions retrieves PCI Express Base Size via a PCD entry+ PcdPciExpressBaseSize.++ @return The base size of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseSize (+ VOID+ )+{+ return (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /** Reads an 8-bit PCI configuration register. @@ -91,7 +110,8 @@ GetPciExpressBaseAddress (
@param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT8@@ -101,6 +121,9 @@ PciExpressRead8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -117,7 +140,8 @@ PciExpressRead8 (
Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT8@@ -128,6 +152,9 @@ PciExpressWrite8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -148,7 +175,8 @@ PciExpressWrite8 (
Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT8@@ -159,6 +187,9 @@ PciExpressOr8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -179,7 +210,8 @@ PciExpressOr8 (
Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -190,6 +222,9 @@ PciExpressAnd8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -212,7 +247,8 @@ PciExpressAnd8 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -224,6 +260,9 @@ PciExpressAndThenOr8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -249,7 +288,9 @@ PciExpressAndThenOr8 (
@param EndBit The ordinal of the most significant bit in the bit field. Range 0..7. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI configuration+ register. **/ UINT8@@ -261,6 +302,9 @@ PciExpressBitFieldRead8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldRead8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -289,7 +333,8 @@ PciExpressBitFieldRead8 (
Range 0..7. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -302,6 +347,9 @@ PciExpressBitFieldWrite8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldWrite8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -334,7 +382,8 @@ PciExpressBitFieldWrite8 (
Range 0..7. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -347,6 +396,9 @@ PciExpressBitFieldOr8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -379,7 +431,8 @@ PciExpressBitFieldOr8 (
Range 0..7. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -392,6 +445,9 @@ PciExpressBitFieldAnd8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAnd8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT8@@ -442,6 +499,9 @@ PciExpressBitFieldAndThenOr8 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAndThenOr8 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -464,7 +524,8 @@ PciExpressBitFieldAndThenOr8 (
@param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT16@@ -474,6 +535,9 @@ PciExpressRead16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -491,7 +555,8 @@ PciExpressRead16 (
Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT16@@ -502,6 +567,9 @@ PciExpressWrite16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -523,7 +591,8 @@ PciExpressWrite16 (
Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -534,6 +603,9 @@ PciExpressOr16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -555,7 +627,8 @@ PciExpressOr16 (
Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -566,6 +639,9 @@ PciExpressAnd16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -589,7 +665,8 @@ PciExpressAnd16 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -601,6 +678,9 @@ PciExpressAndThenOr16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -627,7 +707,9 @@ PciExpressAndThenOr16 (
@param EndBit The ordinal of the most significant bit in the bit field. Range 0..15. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI configuration+ register. **/ UINT16@@ -639,6 +721,9 @@ PciExpressBitFieldRead16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldRead16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -668,7 +753,8 @@ PciExpressBitFieldRead16 (
Range 0..15. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -681,6 +767,9 @@ PciExpressBitFieldWrite16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldWrite16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -714,7 +803,8 @@ PciExpressBitFieldWrite16 (
Range 0..15. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -727,6 +817,9 @@ PciExpressBitFieldOr16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -760,7 +853,8 @@ PciExpressBitFieldOr16 (
Range 0..15. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAnd16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT16@@ -824,6 +922,9 @@ PciExpressBitFieldAndThenOr16 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAndThenOr16 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -846,7 +947,8 @@ PciExpressBitFieldAndThenOr16 (
@param Address The address that encodes the PCI Bus, Device, Function and Register. - @return The read value from the PCI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other The read value from the PCI configuration register. **/ UINT32@@ -856,6 +958,9 @@ PciExpressRead32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address); } @@ -873,7 +978,8 @@ PciExpressRead32 (
Register. @param Value The value to write. - @return The value written to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written to the PCI configuration register. **/ UINT32@@ -884,6 +990,9 @@ PciExpressWrite32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value); } @@ -905,7 +1014,8 @@ PciExpressWrite32 (
Register. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -916,6 +1026,9 @@ PciExpressOr32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData); } @@ -937,7 +1050,8 @@ PciExpressOr32 (
Register. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -948,6 +1062,9 @@ PciExpressAnd32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData); } @@ -971,7 +1088,8 @@ PciExpressAnd32 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -983,6 +1101,9 @@ PciExpressAndThenOr32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 (
@param EndBit The ordinal of the most significant bit in the bit field. Range 0..31. - @return The value of the bit field read from the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value of the bit field read from the PCI+ configuration register. **/ UINT32@@ -1021,6 +1144,9 @@ PciExpressBitFieldRead32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldRead32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1050,7 +1176,8 @@ PciExpressBitFieldRead32 (
Range 0..31. @param Value The new value of the bit field. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1063,6 +1190,9 @@ PciExpressBitFieldWrite32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldWrite32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1096,7 +1226,8 @@ PciExpressBitFieldWrite32 (
Range 0..31. @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32 (
Range 0..31. @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1155,6 +1290,9 @@ PciExpressBitFieldAnd32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAnd32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd32 (
@param AndData The value to AND with the PCI configuration register. @param OrData The value to OR with the result of the AND operation. - @return The value written back to the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The value written back to the PCI configuration register. **/ UINT32@@ -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 (
) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >= PcdPciExpressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAndThenOr32 ( (UINTN) GetPciExpressBaseAddress () + Address, StartBit,@@ -1235,7 +1377,8 @@ PciExpressBitFieldAndThenOr32 (
@param Size The size in bytes of the transfer. @param Buffer The pointer to a buffer receiving the data read. - @return Size read data from StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @retval other Size read data from StartAddress. **/ UINTN@@ -1249,6 +1392,9 @@ PciExpressReadBuffer (
UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if (StartAddress >= PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); if (Size == 0) {@@ -1335,7 +1481,8 @@ PciExpressReadBuffer (
@param Size The size in bytes of the transfer. @param Buffer The pointer to a buffer containing the data to write. - @return Size written to StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @retval other Size written to StartAddress. **/ UINTN@@ -1349,6 +1496,9 @@ PciExpressWriteBuffer (
UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if (StartAddress >= PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); if (Size == 0) {--
2.27.0


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Re: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header

Liming Gao
 

Asharf:

-----Original Message-----
From: Javeed, Ashraf <ashraf.javeed@...>
Sent: 2020年7月22日 23:22
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>
Subject: [PATCH V3 2/2] MdePkg/Include/IndustryStandard: Main CXL header

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Introducing the Cxl.h as the main header file to support all versions of Compute Express Link Specification register definitions.

Signed-off-by: Ashraf Javeed <ashraf.javeed@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
--

V2: Indentation and double declaration fix, copyright date update

V3: Copyright date fix
---
MdePkg/Include/IndustryStandard/Cxl.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/IndustryStandard/Cxl.h
new file mode 100644
index 0000000000..632aa146d0
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl.h
@@ -0,0 +1,22 @@
+/** @file
+ Support for the latest CXL standard
+
+ The main header to reference all versions of CXL Base specification
+ registers from the MDE

Does MDE means MdePkg? I think "from the MDE" can be removed.
With this change, Reviewed-by: Liming Gao <liming.gao@...>

Thanks
Liming
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL_MAIN_H_
+#define _CXL_MAIN_H_
+
+#include <IndustryStandard/Cxl11.h>
+//
+// CXL assigned new Vendor ID
+//
+#define CXL_DVSEC_VENDOR_ID 0x1E98
+
+#endif
+
--
2.21.0.windows.1


Re: [PATCH V2 1/2] BaseTools: Add gcc flag to warn on void* pointer arithmetic

Leif Lindholm
 

Hi Andrew,

Agreed.

I also think this should be applied across all architectures, not just
ARM/AARCH64. Since Visual Studio has never been been able to compile
the affected code, I expect impact to Ia32/X64 to be minimal.

Regards,

Leif

On Wed, Jul 22, 2020 at 19:49:01 -0700, Andrew Fish via groups.io wrote:
Bob,

It also looks like clang could use this flag as the default seems to
be to follow the GCC behavior.

Thanks,

Andrew Fish

On Jul 22, 2020, at 6:56 PM, Bob Feng <bob.c.feng@...> wrote:

Hi Leif

I agree to revert that patch for now and I sent a revert patch for review. After resolving the build break issue for ARM/AARCH64 platforms in edk2-platforms, and make sure there is no platform build break with this patch, we will push it again.

Thanks,
Bob

-----Original Message-----
From: devel@edk2.groups.io <mailto:devel@edk2.groups.io> <devel@edk2.groups.io <mailto:devel@edk2.groups.io>> On Behalf Of Leif Lindholm
Sent: Thursday, July 23, 2020 2:06 AM
To: devel@edk2.groups.io <mailto:devel@edk2.groups.io>; Feng, Bob C <bob.c.feng@... <mailto:bob.c.feng@...>>
Cc: PierreGondois <pierre.gondois@... <mailto:pierre.gondois@...>>; Gao, Liming <liming.gao@... <mailto:liming.gao@...>>; tomas@... <mailto:tomas@...>
Subject: Re: [edk2-devel] [PATCH V2 1/2] BaseTools: Add gcc flag to warn on void* pointer arithmetic

Hi Bob,

This patch also breaks about half of the ARM/AARCH64 platforms in edk2-platforms. I agree it should go in at a later stage, but for now, can we please revert it?

Regards,

Leif

On Mon, Jul 20, 2020 at 04:10:27 +0000, Bob Feng wrote:
Reviewed-by: Bob Feng<bob.c.feng@...>


-----Original Message-----
From: PierreGondois <pierre.gondois@...>
Sent: Tuesday, July 7, 2020 4:35 PM
To: devel@edk2.groups.io
Cc: Pierre Gondois <Pierre.Gondois@...>; Feng, Bob C
<bob.c.feng@...>; Gao, Liming <liming.gao@...>;
tomas.pilar@...; nd@...
Subject: [PATCH V2 1/2] BaseTools: Add gcc flag to warn on void*
pointer arithmetic

From: Pierre Gondois <pierre.gondois@...>

By default, gcc allows void* pointer arithmetic.
This is a GCC extension.
However:
- the C reference manual states that void*
pointer "cannot be operands of addition
or subtraction operators". Cf s5.3.1
"Generic Pointers";
- Visual studio compiler treat such operation as
an error.

To prevent such pointer arithmetic, the "-Wpointer-arith"
flag should be set for all GCC versions.

The "-Wpointer-arith" allows to:
"Warn about anything that depends on the "size of"
a function type or of void. GNU C assigns these
types a size of 1, for convenience in calculations
with void * pointers and pointers to functions."

This flag is available since GCC2.95.3 which came out in 2001.

Signed-off-by: Pierre Gondois <pierre.gondois@...>
---

The changes can be seen at:
https://github.com/PierreARM/edk2/commits/831_Add_gcc_flag_warning_v2

Notes:
v1:
- Add "-Wpointer-arith" gcc flag. [Pierre]
v2:
- Only add the flag for ARM and AARCH64. [Tomas]

BaseTools/Conf/tools_def.template | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Conf/tools_def.template
b/BaseTools/Conf/tools_def.template
index
8aeb8a2a6417e41c5660cda5066f52adc8cc3089..397b011ba38f97f81f314f8641ac
8bb95d5a2197 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -1,7 +1,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights
reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All
rights reserved.<BR> -# Portions copyright (c) 2011 - 2019, ARM Ltd.
All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2020, ARM Ltd. All rights
+reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR> # (C) Copyright 2020, Hewlett Packard Enterprise Development LP<BR> # Copyright (c) Microsoft Corporation
@@ -1921,9 +1921,9 @@ NOOPT_*_*_OBJCOPY_ADDDEBUGFLAG = --add-gnu-debuglink=$(DEBUG_DIR)/$(MODULE_N
DEFINE GCC_ALL_CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -include AutoGen.h -fno-common
DEFINE GCC_IA32_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -m32 -malign-double -freorder-blocks -freorder-blocks-and-partition -O2 -mno-stack-arg-probe
DEFINE GCC_X64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mno-red-zone -Wno-address -mno-stack-arg-probe
-DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft -fno-pic -fno-pie
+DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -Wpointer-arith -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft -fno-pic -fno-pie
DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
-DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
+DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -Wpointer-arith -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'