Date   

[PATCH v7 00/16] Add a plugin to check Ecc issues for edk2 on open ci

Zhang, Shenglei
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2606
As planed we will enable Ecc check for edk2 on open ci. And they are
ready now. I appreciate receiving feedback and comments if someone
find errors or false positive issues.

I created a pipline of EccCheck for my forked edk2. Welcome everyone to
create pull request to test the quality of this plugin.
My forked tree: https://github.com/shenglei10/edk2

And I also created some test cases for ECC plugin. Below are test cases.
https://github.com/shenglei10/edk2/tree/ECC
Results can be view in below azure server.
https://dev.azure.com/shengleizhang/shengleizhang/_build?definitionId=12&_a=summary

Patches
1/16: It's a lib necessary for py3 to run Ecc on azure servers.

2/16: EccCheck.py is a plugin to report Ecc issues for commits. It can be run
on azure servers for open ci, or a local virtual environment.

3/16~16/16: We consider some cases that will report out Ecc issues but they won't
be fixed, like submodule and industry standard related things. So we
add two configuration fields "Exception" and "IgnoreFiles" for people
to use. These patches add configuration in yaml files for Ecc check.

Cc: Bob Feng <bob.c.feng@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
Cc: Sean Brogan <sean.brogan@...>

v2: Update 1/17, fix the bug that the script can't hanlde multiple commits.

v3: Update 1/17, set the only workalbe workspace is edk2 root directory.
Update 2/17, designate the version of antlr4 is 4.7.1.
Add 4/17~17/17.

v4. Update 1/17, remove the function EdksetupRebuild(), instead add
function SetupEnvironment(). Update variables' format and type hints
to pass flake8 and mypy.

v5. Conver the former method to plugin solution, to align with
other check points on open ci.

v6. The 1/16 patch is missed in v5 series. Now add it in v6.

v7. Fix a bug that Ecc plugin can not be run correctly under Linux OS.

Shenglei Zhang (16):
pip-requirements.txt: Add Ecc required lib
.pytool/Plugin: Add a plugin EccCheck
MdeModulePkg/MdeModulePkg.ci.yaml: Add configuration for Ecc check
ArmVirtPkg/ArmVirtPkg.ci.yaml: Add configuration for Ecc check
CryptoPkg/CryptoPkg.ci.yaml: Add configuration for Ecc check
EmulatorPkg/EmulatorPkg.ci.yaml: Add configuration for Ecc check
FatPkg/FatPkg.ci.yaml: Add configuration for Ecc check
FmpDevicePkg/FmpDevicePkg.ci.yaml: Add configuration for Ecc check
MdePkg/MdePkg.ci.yaml: Add configuration for Ecc check
NetworkPkg/NetworkPkg.ci.yaml: Add configuration for Ecc check
OvmfPkg/OvmfPkg.ci.yaml: Add configuration for Ecc check
PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml: Add configuration for Ecc check
SecurityPkg/SecurityPkg.ci.yaml: Add configuration for Ecc check
ShellPkg/ShellPkg.ci.yaml: Add configuration for Ecc check
UefiCpuPkg/UefiCpuPkg.ci.yaml: Add configuration for Ecc check
UnitTestFrameworkPkg: Add configuration for Ecc check in yaml file

.pytool/Plugin/EccCheck/EccCheck.py | 267 ++++++++++++++++++
.pytool/Plugin/EccCheck/EccCheck_plug_in.yaml | 11 +
.pytool/Plugin/EccCheck/Readme.md | 15 +
ArmVirtPkg/ArmVirtPkg.ci.yaml | 11 +
CryptoPkg/CryptoPkg.ci.yaml | 11 +
EmulatorPkg/EmulatorPkg.ci.yaml | 11 +
FatPkg/FatPkg.ci.yaml | 11 +
FmpDevicePkg/FmpDevicePkg.ci.yaml | 11 +
MdeModulePkg/MdeModulePkg.ci.yaml | 11 +
MdePkg/MdePkg.ci.yaml | 11 +
NetworkPkg/NetworkPkg.ci.yaml | 11 +
OvmfPkg/OvmfPkg.ci.yaml | 11 +
PcAtChipsetPkg/PcAtChipsetPkg.ci.yaml | 11 +
SecurityPkg/SecurityPkg.ci.yaml | 11 +
ShellPkg/ShellPkg.ci.yaml | 11 +
UefiCpuPkg/UefiCpuPkg.ci.yaml | 11 +
.../UnitTestFrameworkPkg.ci.yaml | 10 +
pip-requirements.txt | 1 +
18 files changed, 447 insertions(+)
create mode 100644 .pytool/Plugin/EccCheck/EccCheck.py
create mode 100644 .pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
create mode 100644 .pytool/Plugin/EccCheck/Readme.md

--
2.18.0.windows.1


[PATCH edk2-platforms v2 6/6] Platform/NXP/LS1046aFrwyPkg: Add VarStore

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 1 +
Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++
2 files changed, 92 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 8da5b57cb49e..24af547729c7 100644
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -48,6 +48,7 @@ [FD.LS1046AFRWY_EFI]
FV = FVMAIN_COMPACT

!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
diff --git a/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
new file mode 100644
index 000000000000..727705feaea1
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1046aFrwyNv_EFI]
+BaseAddress = 0x40500000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0xC0
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1046AFRWY NVRAM Area
+# LS1046AFRWY NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
2.17.1


[PATCH edk2-platforms v2 5/6] Platform/NXP: Add LS1046AFRWY Platform

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

LS1046A Freeway (FRWY) is a high-performance development
platform that supports the QorIQ LS1046A Layerscape Architecture SOCs.

Co-authored-by: Pramod Kumar <pramod.kumar_1@...>
Co-authored-by: Pankaj Bansal <pankaj.bansal@...>
Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec | 23 +++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 46 ++++++
Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 168 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 4 +
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 53 +++++-
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 49 +++++-
6 files changed, 341 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
new file mode 100644
index 000000000000..a693d8262444
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
@@ -0,0 +1,23 @@
+# LS1046aFrwyPkg.dec
+# LS1046a board package.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LS1046aFrwyPkg
+ PACKAGE_GUID = 3547d88c-62c2-4fb2-a11b-80245f80928f
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
new file mode 100644
index 000000000000..3f29dadd5d1d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -0,0 +1,46 @@
+# LS1046aFrwyPkg.dsc
+#
+# LS1046AFRWY Board package.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1046aFrwyPkg
+ PLATFORM_GUID = 79adaa48-5f50-49f0-aa9a-544ac9260ef8
+ OUTPUT_DIRECTORY = Build/LS1046aFrwyPkg
+ FLASH_DEFINITION = Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+ RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+##
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
new file mode 100644
index 000000000000..8da5b57cb49e
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -0,0 +1,168 @@
+# LS1046aFrwyPkg.fdf
+#
+# FLASH layout file for LS1046a board.
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046AFRWY_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1000
+NumBlocks = 0x140
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00140000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index de93681708e3..7802696bf39b 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -18,10 +18,14 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+ Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
ArmLib
DebugLib
+ SocLib

[Sources.common]
ArmPlatformLib.c
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index f59e7aa556a3..e1f20da09337 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,8 +8,10 @@

#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>

#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>

ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
{
@@ -38,6 +40,54 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}

+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
/**
Initialize controllers that must setup in the normal world

@@ -50,7 +100,7 @@ ArmPlatformInitialize (
IN UINTN MpId
)
{
- //TODO: Implement me
+ SocInit ();

return EFI_SUCCESS;
}
@@ -71,6 +121,7 @@ PrePeiCoreGetMpCoreInfo (
}

ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };

EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index 24d949369b98..f712d5931821 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -7,7 +7,12 @@
**/

#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5

/**
Return the Virtual Memory Map of your platform
@@ -24,5 +29,47 @@ ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
- ASSERT(0);
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+ return;
+ }
+
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI
+ VirtualMemoryTable[Index].PhysicalBase = LS1046A_QSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1046A_QSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1046A_QSPI0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
+
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
}
--
2.17.1


[PATCH edk2-platforms v2 4/6] Platform/NXP/LS1046AFRWY: Add ArmPlatformLib

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Add ArmPlatformLib for LS1046AFRWY platform that is based on
ArmPlatformPkg/Library/ArmPlatformLibNull.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 38 ++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 96 ++++++++++++++++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 28 ++++++
Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S | 45 +++++++++
4 files changed, 207 insertions(+)

diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000000000000..de93681708e3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,38 @@
+# @file
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = c61c8a13-36a0-46f4-a3bc-7bab5a55db81
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ ArmPlatformLibMem.c
+
+[Sources.AArch64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index 000000000000..f59e7aa556a3
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,96 @@
+/** @file
+*
+* Copyright 2019-2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mLS1046aMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ //TODO: Implement me
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof(mLS1046aMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mLS1046aMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ if (ArmIsMpCore()) {
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+ } else {
+ *PpiListSize = 0;
+ *PpiList = NULL;
+ }
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index 000000000000..24d949369b98
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,28 @@
+/** @file
+*
+* Copyright 2019-2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ASSERT(0);
+}
diff --git a/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 000000000000..4f56a1c366ab
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,45 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
--
2.17.1


[PATCH edk2-platforms v2 3/6] Silicon/NXP: Add LS1046A Soc package

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

LS1046A is QorIq Layerscape multicore communications processor with
four Arm Cortex-A72 cores.
This SOC is based on Layerscape Chassis v2.

Co-authored-by: Vabhav Sharma <vabhav.sharma@...>
Co-authored-by: Pankaj Bansal <pankaj.bansal@...>
Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/LS1046A/LS1046A.dec | 13 +++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 42 +++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++++
Silicon/NXP/LS1046A/Include/Soc.h | 63 +++++++++++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 33 ++++++
Silicon/NXP/LS1046A/Library/SocLib/SerDes.c | 119 ++++++++++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 78 +++++++++++++
7 files changed, 375 insertions(+)

diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 000000000000..bf4863c6d89e
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,13 @@
+# LS1046A.dec
+#
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 000000000000..dbe7f408fce9
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,42 @@
+# LS1046A.dsc
+# LS1046A Soc package.
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+##
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
new file mode 100644
index 000000000000..01ed0f6592d2
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
@@ -0,0 +1,27 @@
+# @file
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ChassisLib
+ DebugLib
+
+[Sources.common]
+ SocLib.c
diff --git a/Silicon/NXP/LS1046A/Include/Soc.h b/Silicon/NXP/LS1046A/Include/Soc.h
new file mode 100644
index 000000000000..84f433d5cb94
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/Soc.h
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LS1046A_DRAM0_PHYS_ADDRESS (BASE_2GB)
+#define LS1046A_DRAM0_SIZE (SIZE_2GB)
+#define LS1046A_DRAM1_PHYS_ADDRESS (BASE_32GB + BASE_2GB)
+#define LS1046A_DRAM1_SIZE (SIZE_32GB - SIZE_2GB) // 30 GB
+
+#define LS1046A_CCSR_PHYS_ADDRESS (BASE_16MB)
+#define LS1046A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB
+
+#define LS1046A_QSPI0_PHYS_ADDRESS (BASE_1GB)
+#define LS1046A_QSPI0_SIZE (SIZE_512MB)
+
+#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0011 3:1
+ | | | 0_0100 4:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+ | | | 1_0000 16:1
+
+ which is why the RCW bits in RCWSR registers are parsed this way
+**/
+#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
+
+#endif // SOC_H__
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 000000000000..2fc5651c004c
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,33 @@
+/** SocSerDes.h
+ SoC Specific header file for SerDes
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef SOC_SERDES_H
+#define SOC_SERDES_H
+
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ SATA,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ QSGMII_FM1_A,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SERDES_PROTOCOL_COUNT
+} SERDES_PROTOCOL;
+#endif
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c b/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
new file mode 100644
index 000000000000..a50e0b61e19a
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
@@ -0,0 +1,119 @@
+/** SerDes.c
+ Provides SoC specific SerDes interface
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SerDesHelperLib.h>
+#include <SocSerDes.h>
+#include <Soc.h>
+#include <Uefi.h>
+
+// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register
+#define SERDES1_PROTOCOL_MASK 0xffff0000
+
+// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register
+#define SERDES1_PROTOCOL_SHIFT 16
+
+STATIC SERDES_CONFIG mSerDes1ConfigTable[] = {
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG *gSerDesConfig[] = {
+ mSerDes1ConfigTable
+};
+
+/**
+ Probe all SerDes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ UINT32 SerDesProtocol;
+ LS1046A_DEVICE_CONFIG *DeviceConfig;
+
+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
+
+ SerDesInstanceProbeLanes (
+ SERDES_1,
+ SerDesProtocol,
+ FixedPcdGet8 (PcdSerDesLanes),
+ SERDES_PROTOCOL_COUNT,
+ gSerDesConfig[SERDES_1],
+ SerDesLaneProbeCallback,
+ Arg
+ );
+}
+
+/**
+ Function to return SerDes protocol map for all SerDes available on board.
+
+ @param SerDesProtocolMap Pointer to SerDes protocl map.
+
+**/
+VOID
+GetSerDesProtocolMap (
+ OUT UINT64 *SerDesProtocolMap
+ )
+{
+ UINT32 SerDesProtocol;
+ LS1046A_DEVICE_CONFIG *DeviceConfig;
+ EFI_STATUS Status;
+
+ *SerDesProtocolMap = 0;
+ DeviceConfig = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+ SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK;
+ SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT;
+
+ Status = GetSerDesMap (
+ SERDES_1,
+ SerDesProtocol,
+ FixedPcdGet8 (PcdSerDesLanes),
+ SERDES_PROTOCOL_COUNT,
+ gSerDesConfig[SERDES_1],
+ SerDesProtocolMap
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__));
+ *SerDesProtocolMap = 0;
+ }
+}
diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
new file mode 100644
index 000000000000..3b15aee6ecae
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -0,0 +1,78 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multiplier/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multiplier/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1046A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 1; // 1/2 Platform Clock
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
--
2.17.1


[PATCH edk2-platforms v2 2/6] Silicon/NXP/LS1043A: Fix the RCW bits' parsing

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

For LS1043A SOC the DCFG registers are read in big endian format.
After Reading the registers in code we have the registers in Little
Endian Bit format i.e. LSBit 0.

However, the RCW bits in RCWSR registers in LS1043A SOC are in MSBit 0
format.

Currently, we are parsing the RCW bits in LE bit format i.e. LSBit 0.
Therefore, Fix the RCW bits' parsing as per MSBit 0.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/LS1043A/Include/Soc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index c694576ed18d..40619536c6fe 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -78,7 +78,7 @@ Bit(s) | Field Name | Description | Notes/comments

which is why the RCW bits in RCWSR registers are parsed this way
**/
-#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6

typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;

--
2.17.1


[PATCH edk2-platforms v2 1/6] Silicon/NXP: Add comments explaining RCW bits' parsing

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

RCW bits parsing and their interpretation varies between various SOCs.
Add the comments that explain this parsing scheme.

Based on this explanation, fix the comments for SYS_PLL_RAT parsing
in LX2160A.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/LS1043A/Include/Soc.h | 27 +++++++++++++++++++
Silicon/NXP/LX2160A/Include/Soc.h | 28 +++++++++++++++++++-
2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 21b0dafffe91..c694576ed18d 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -50,6 +50,33 @@

/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0011 3:1
+ | | | 0_0100 4:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+ | | | 1_0000 16:1
+
+ which is why the RCW bits in RCWSR registers are parsed this way
**/
#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6

diff --git a/Silicon/NXP/LX2160A/Include/Soc.h b/Silicon/NXP/LX2160A/Include/Soc.h
index d62b8adcdbe7..e8198addc966 100644
--- a/Silicon/NXP/LX2160A/Include/Soc.h
+++ b/Silicon/NXP/LX2160A/Include/Soc.h
@@ -36,8 +36,34 @@

/**
Reset Control Word (RCW) Bits
+
+ RCWSR contains the Reset Configuration Word (RCW) information written with
+ values read from flash memory by the device at power-on reset and read-only
+ upon exiting reset.
+
+ RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
+
+RCW Bits |
+in RCWSR |
+(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+------------------------------------------------------------------------------------------------
+LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+(LSBit 0)|
+
+ Moreover the RCW bits are to be interpreted in below fasion
+
+Bit(s) | Field Name | Description | Notes/comments
+----------------------------------------------------------------------
+ 6-2 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
+ | | | clock:SYSCLK ratio.
+ | | | 0_0100 4:1
+ | | | 0_0110 6:1
+ | | | 0_1000 8:1
+ | | | 0_1101 13:1
+ | | | 0_1111 15:1
+
**/
-#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 6-2

typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;

--
2.17.1


[PATCH edk2-platforms v2 0/6] Add LS1046AFRWY Platform

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance
development platform that supports the QorIQ LS1046A architecture
processor.

The LS1046A SOC is based on Layerscape Chassis2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

V1 can be referred here:
https://edk2.groups.io/g/devel/message/60577

Changes in V2 w.r.t V1:
- No functional changes
- Explaination Added for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' parsing
- Refer PATCH 1/6 Silicon/NXP: Add comments explaining RCW bits' parsing
for expalaination for PATCH 2/6 Silicon/NXP/LS1043A: Fix the RCW bits' parsing

Pankaj Bansal (6):
Silicon/NXP: Add comments explaining RCW bits' parsing
Silicon/NXP/LS1043A: Fix the RCW bits' parsing
Silicon/NXP: Add LS1046A Soc package
Platform/NXP/LS1046AFRWY: Add ArmPlatformLib
Platform/NXP: Add LS1046AFRWY Platform
Platform/NXP/LS1046aFrwyPkg: Add VarStore

.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec | 23 +++
Silicon/NXP/LS1046A/LS1046A.dec | 13 ++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 42 +++++
.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 46 +++++
.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 169 ++++++++++++++++++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 42 +++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf | 27 +++
Silicon/NXP/LS1043A/Include/Soc.h | 29 ++-
Silicon/NXP/LS1046A/Include/Soc.h | 63 +++++++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 33 ++++
Silicon/NXP/LX2160A/Include/Soc.h | 28 ++-
.../Library/ArmPlatformLib/ArmPlatformLib.c | 147 +++++++++++++++
.../ArmPlatformLib/ArmPlatformLibMem.c | 75 ++++++++
Silicon/NXP/LS1046A/Library/SocLib/SerDes.c | 119 ++++++++++++
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 78 ++++++++
.../AArch64/ArmPlatformHelper.S | 45 +++++
Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc | 91 ++++++++++
17 files changed, 1068 insertions(+), 2 deletions(-)
create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
create mode 100644 Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/LS1046A/Include/Soc.h
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SerDes.c
create mode 100644 Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LS1046aFrwyPkg/VarStore.fdf.inc

--
2.17.1


[PATCH] Using LLVM compiler set to build BaseTools in Linux

Zhiguang Liu
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2842

To use LLVM to build BaseTools, first set the CLANG_BIN environment value,
and add "CXX=3Dllvm" to choose LLVM compiler set when using make command.

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <liming.gao@...>

Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---
BaseTools/Source/C/Makefiles/header.makefile | 22 ++++++++++++++++++=
++--
BaseTools/Source/C/VfrCompile/GNUmakefile | 6 ++++--
BaseTools/Source/C/VfrCompile/Pccts/antlr/makefile | 4 ++++
BaseTools/Source/C/VfrCompile/Pccts/dlg/makefile | 4 ++++
4 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Sourc=
e/C/Makefiles/header.makefile
index 4e9b36d98b..1c105ee7d4 100644
--- a/BaseTools/Source/C/Makefiles/header.makefile
+++ b/BaseTools/Source/C/Makefiles/header.makefile
@@ -38,12 +38,19 @@ endif
CYGWIN:=3D$(findstring CYGWIN, $(shell uname -s))=0D
LINUX:=3D$(findstring Linux, $(shell uname -s))=0D
DARWIN:=3D$(findstring Darwin, $(shell uname -s))=0D
-=0D
+ifeq ($(CXX), llvm)=0D
+BUILD_CC ?=3D $(CLANG_BIN)clang=0D
+BUILD_CXX ?=3D $(CLANG_BIN)clang++=0D
+BUILD_AS ?=3D $(CLANG_BIN)clang=0D
+BUILD_AR ?=3D $(CLANG_BIN)llvm-ar=0D
+BUILD_LD ?=3D $(CLANG_BIN)llvm-ld=0D
+else=0D
BUILD_CC ?=3D gcc=0D
BUILD_CXX ?=3D g++=0D
BUILD_AS ?=3D gcc=0D
BUILD_AR ?=3D ar=0D
BUILD_LD ?=3D ld=0D
+endif=0D
LINKER ?=3D $(BUILD_CC)=0D
ifeq ($(HOST_ARCH), IA32)=0D
ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/Ia32/=0D
@@ -72,14 +79,25 @@ ifeq ($(DARWIN),Darwin)
BUILD_CFLAGS =3D -MD -fshort-wchar -fno-strict-aliasing -Wall -Werror \=0D
-Wno-deprecated-declarations -Wno-self-assign -Wno-unused-result -nostdlib=
-g=0D
else=0D
+ifeq ($(CXX), llvm)=0D
+BUILD_CFLAGS =3D -MD -fshort-wchar -fno-strict-aliasing -fwrapv \=0D
+-fno-delete-null-pointer-checks -Wall -Werror \=0D
+-Wno-deprecated-declarations -Wno-self-assign \=0D
+-Wno-unused-result -nostdlib -g=0D
+else=0D
BUILD_CFLAGS =3D -MD -fshort-wchar -fno-strict-aliasing -fwrapv \=0D
-fno-delete-null-pointer-checks -Wall -Werror \=0D
-Wno-deprecated-declarations -Wno-stringop-truncation -Wno-restrict \=0D
-Wno-unused-result -nostdlib -g=0D
endif=0D
+endif=0D
+ifeq ($(CXX), llvm)=0D
+BUILD_LFLAGS =3D=0D
+BUILD_CXXFLAGS =3D -Wno-deprecated-register -Wno-unused-result=0D
+else=0D
BUILD_LFLAGS =3D=0D
BUILD_CXXFLAGS =3D -Wno-unused-result=0D
-=0D
+endif=0D
ifeq ($(HOST_ARCH), IA32)=0D
#=0D
# Snow Leopard is a 32-bit and 64-bit environment. uname -m returns i386,=
but gcc defaults=0D
diff --git a/BaseTools/Source/C/VfrCompile/GNUmakefile b/BaseTools/Source/C=
/VfrCompile/GNUmakefile
index 42e3d7da02..fc329944b9 100644
--- a/BaseTools/Source/C/VfrCompile/GNUmakefile
+++ b/BaseTools/Source/C/VfrCompile/GNUmakefile
@@ -16,9 +16,11 @@ TOOL_INCLUDE =3D -I Pccts/h
#OBJECTS =3D VfrSyntax.o VfrServices.o DLGLexer.o EfiVfrParser.o ATokenBuf=
fer.o DLexerBase.o AParser.o=0D
OBJECTS =3D AParser.o DLexerBase.o ATokenBuffer.o EfiVfrParser.o VfrLexer.=
o VfrSyntax.o \=0D
VfrFormPkg.o VfrError.o VfrUtilityLib.o VfrCompiler.o=0D
-=0D
+ifeq ($(CXX), llvm)=0D
+VFR_CPPFLAGS =3D -Wno-deprecated-register -DPCCTS_USE_NAMESPACE_STD $(BUIL=
D_CPPFLAGS)=0D
+else=0D
VFR_CPPFLAGS =3D -DPCCTS_USE_NAMESPACE_STD $(BUILD_CPPFLAGS)=0D
-=0D
+endif=0D
# keep BUILD_OPTFLAGS last=0D
VFR_CXXFLAGS =3D $(BUILD_OPTFLAGS)=0D
=0D
diff --git a/BaseTools/Source/C/VfrCompile/Pccts/antlr/makefile b/BaseTools=
/Source/C/VfrCompile/Pccts/antlr/makefile
index 8f2cc78c59..559b1c99f1 100644
--- a/BaseTools/Source/C/VfrCompile/Pccts/antlr/makefile
+++ b/BaseTools/Source/C/VfrCompile/Pccts/antlr/makefile
@@ -164,7 +164,11 @@ PCCTS_H=3D../h
#=0D
# UNIX (default)=0D
#=0D
+ifeq ($(CXX), llvm)=0D
+BUILD_CC?=3D$(CLANG_BIN)clang=0D
+else=0D
BUILD_CC?=3Dgcc=0D
+endif=0D
COPT=3D-O=0D
ANTLR=3D${BIN_DIR}/antlr=0D
DLG=3D${BIN_DIR}/dlg=0D
diff --git a/BaseTools/Source/C/VfrCompile/Pccts/dlg/makefile b/BaseTools/S=
ource/C/VfrCompile/Pccts/dlg/makefile
index b3a34d3b46..5a3561edec 100644
--- a/BaseTools/Source/C/VfrCompile/Pccts/dlg/makefile
+++ b/BaseTools/Source/C/VfrCompile/Pccts/dlg/makefile
@@ -114,7 +114,11 @@ PCCTS_H=3D../h
#=0D
# UNIX=0D
#=0D
+ifeq ($(CXX), llvm)=0D
+BUILD_CC?=3D$(CLANG_BIN)clang=0D
+else=0D
BUILD_CC?=3Dcc=0D
+endif=0D
COPT=3D-O=0D
ANTLR=3D${BIN_DIR}/antlr=0D
DLG=3D${BIN_DIR}/dlg=0D
--=20
2.25.1.windows.1


[PATCH 01/13] SecurityPkg/Tcg2Pei: Add missing PCRIndex in FvBlob event.

Yao, Jiewen
 

From: Jiewen Yao <jiewen.yao@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2840=0D
=0D
Cc: Jian J Wang <jian.j.wang@...>
Signed-off-by: Jiewen Yao <jiewen.yao@...>
---
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c b/SecurityPkg/Tcg/Tcg2Pei/Tc=
g2Pei.c
index 4852d86906..19b8e4b318 100644
--- a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
+++ b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
@@ -633,6 +633,7 @@ MeasureFvImage (
}=0D
FvBlob2.BlobBase =3D FvBase;=0D
FvBlob2.BlobLength =3D FvLength;=0D
+ TcgEventHdr.PCRIndex =3D 0;=0D
TcgEventHdr.EventType =3D EV_EFI_PLATFORM_FIRMWARE_BLOB2;=0D
TcgEventHdr.EventSize =3D sizeof (FvBlob2);=0D
EventData =3D &FvBlob2;=0D
--=20
2.26.2.windows.1


[PATCH 01/14] SecurityPkg/Tcg2Dxe: Add PcdTcgPfpMeasurementRevision in SpecId event.

Yao, Jiewen
 

From: Jiewen Yao <jiewen.yao@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2839
=0D
Cc: Jian J Wang <jian.j.wang@...>
Signed-off-by: Jiewen Yao <jiewen.yao@...>
---
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c | 2 +-
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c b/SecurityPkg/Tcg/Tcg2Dxe/Tc=
g2Dxe.c
index 9a5f987e68..6d17616c1c 100644
--- a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
+++ b/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
@@ -1589,7 +1589,7 @@ SetupEventLog (
TcgEfiSpecIdEventStruct->platformClass =3D PcdGet8 (PcdTpmPlatform=
Class);=0D
TcgEfiSpecIdEventStruct->specVersionMajor =3D TCG_EfiSpecIDEventSt=
ruct_SPEC_VERSION_MAJOR_TPM2;=0D
TcgEfiSpecIdEventStruct->specVersionMinor =3D TCG_EfiSpecIDEventSt=
ruct_SPEC_VERSION_MINOR_TPM2;=0D
- TcgEfiSpecIdEventStruct->specErrata =3D TCG_EfiSpecIDEventStruct_S=
PEC_ERRATA_TPM2;=0D
+ TcgEfiSpecIdEventStruct->specErrata =3D (UINT8)PcdGet32(PcdTcgPfpM=
easurementRevision);=0D
TcgEfiSpecIdEventStruct->uintnSize =3D sizeof(UINTN)/sizeof(UINT32=
);=0D
NumberOfAlgorithms =3D 0;=0D
DigestSize =3D (TCG_EfiSpecIdEventAlgorithmSize *)((UINT8 *)TcgEfi=
SpecIdEventStruct + sizeof(*TcgEfiSpecIdEventStruct) + sizeof(NumberOfAlgor=
ithms));=0D
diff --git a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf b/SecurityPkg/Tcg/Tcg2Dxe/=
Tcg2Dxe.inf
index 576cf80d06..7dc7a2683d 100644
--- a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf
+++ b/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf
@@ -106,6 +106,7 @@
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev =
## CONSUMES=0D
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableLaml =
## PRODUCES=0D
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableLasa =
## PRODUCES=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTcgPfpMeasurementRevision =
## CONSUMES=0D
=0D
[Depex]=0D
# According to PcdTpm2AcpiTableRev definition in SecurityPkg.dec=0D
--=20
2.26.2.windows.1


[PATCH] .gitignore: Ignore .vscode/ directory generated by VS Code

Ni, Ray
 

From: Ray Ni <niruiyu@...>

Signed-off-by: Ray Ni <ray.ni@...>
Cc: Liming Gao <liming.gao@...>
Cc: Michael D Kinney <michael.d.kinney@...>
---
.gitignore | 1 +
1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 58200d4d73..115bbade55 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
__pycache__/=0D
+.vscode/=0D
--=20
2.26.2.windows.1


Re: [PATCH] MdeModulePkg/PartitionDxe: Seperate the Udf handler

Gao, Zhichao
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Laszlo Ersek
Sent: Thursday, July 2, 2020 5:42 PM
To: Gao, Zhichao <zhichao.gao@...>; Ni, Ray <ray.ni@...>;
devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@...>; Wang, Jian J <jian.j.wang@...>;
Gao, Liming <liming.gao@...>
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PartitionDxe: Seperate the Udf
handler

On 06/29/20 03:47, Gao, Zhichao wrote:
Hi Laszlo,

Sorry, I didn't put the detail info about the issue. Let me descript here.

The issue is not only for Red Hat. I found it with ubuntu 18.02 amd64 and
Fedora-20-x86_64 ISO image as well. I didn't view all the linux iso images.

OK. Thanks.


Here is the issue:
Using USB CD ROM with the linux ISO DVD. Run the platform and enter UEFI
shell -> plug the USB CD ROM with the ISO DVD -> run "map -r". The CD's file
system didn't show.

That's right.

And, I've always thought that's by design.

With all the ISO images I've checked in the UEFI shell before, my experience has
been consistent: in the UEFI shell, the ElTorito boot image contents are *visible*,
and the file system that the *OS* would show is *not* visible.

I've always treated these two content-sets as separate file systems.
When we "mount" the ISO under UEFI, we get the ElTorito boot image. When we
mount the disk under an OS, we get the "real" file system.

What's wrong with that?

UEFI needs to be able to boot off of a UEFI-bootable CD-ROM. That requires
support for the ElTorito boot image. That support exists.
UEFI can boot ElTorito image because it has a FAT file system. And UEFI would load the bootable image in the FAT. If the block device has FAT file system in them. It should be shown in the UEFI shell. For the above Linux ISO images, they have.



It works fine with the normal boot (such as F2, F7 and auto boot) because it
would run the *connect all* operation.

I think I disagree; ConnectAll is not the reason.

Automatic boot works OK because the ElTorito image is processed correctly even
*without* a ConnectAll, and the ElTorito image is all that's needed for
successfully booting.

I think you may be misled the fact that the ElTorito image and the OS-visible
filesystem on the disk are *similar*. They have similar contents, but they are not
identical. For UEFI booting, the OS-visible filesystem is completely ignored (and
that's how it should be).
Why I mention the *ConnectAll*, because the UEFI binding driver would be ran thru this function. That means the partition driver would run serval times. First time it runs, it would pass the MBR check. Second time it would failed the MBR because the same block already installed, and it would continue to check UDF (ElTorito compatible).

So the connect behavior should be run at least twice. Otherwise, the ElTorito image would be missed. This is an incorrect behavior mention below.

The USB hot plug handle would only connect the USB device only once. So the hot plug of USB CD ROM under shell would only show the MBR block info. If you run platform with USB CD ROM plugin all the time or hot plug USB CD ROM and run 'reconnnect -r', the CD block with FAT will appear.


That would run the partition driver serval times. First time the partition driver
would install MBR partition info protocol with the device handle and skip the UDF
check. The second time, it would fail the MBR check with *already started* and
run UDF check next. That means for such ISO the UEFI would install two partition
protocol, both MBR and UDF.

I still don't understand how UDF enters the picture. If I loop-mount the "Fedora-
20-x86_64-DVD.iso" image on my laptop, the kernel logs the
following:

ISO 9660 Extensions: Microsoft Joliet Level 3 ISO 9660 Extensions:
RRIP_1991A
Also, the "mount" and "df" commands report the filesystem on the ISO image as
"iso9660". It's not UDF.

(I do have UDF media too; when I mount it, the kernel logs

UDF-fs: INFO Mounting volume '...', timestamp ... (...)
and "mount" and "df" report "udf" as file system.)

So I would say that a UDF filesystem should *never* be exposed for "Fedora-20-
x86_64-DVD.iso" specifically, under UEFI.
Sorry for the unclear description. The UDF I mentioned is ElTorito compatible. There is one commit to merge the ElTorito into the UDF. See 01a68fd37e79c6c7e2f342d7d2c1349325110e99.


... down-thread, Ray says,

It sounds like a bug in partition driver that the second UDF check
succeeds.
And I think I agree.
I didn't aware this is a bug before. I make the patch to do the MBR and UDF check at one connect operation. Now I plan to add the check for the MBR table check to skip the one added for windows compatibility. And fix the bug: if one partition check return already started, it would continue to check next routine partition check.

Thanks,
Zhichao


Thanks
Laszlo


But for shell environment, the USB hot plug handle would connect the USB
device only once and missing the UDF check.

I don't know why linux need the MBR info. Maybe for legacy compatible thinking
(my opinion, may be wrong).

If the GPT, MBR and UDF are conflict, then the original logic is fine. But in fact,
GPT and MBR are conflict and GPT/MBR and UDF are not conflict.



Re: [PATCH v6 00/16] Add a plugin to check Ecc issues for edk2 on open ci

Zhang, Shenglei
 

Hi Lazslo,

Looks like I missed your ACK. I will add it in latter versions.

Thanks,
Shenglei

-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: Saturday, July 4, 2020 12:02 AM
To: Gao, Liming <liming.gao@...>; devel@edk2.groups.io; Zhang,
Shenglei <shenglei.zhang@...>; Leif Lindholm <leif@...>;
afish@...
Cc: Feng, Bob C <bob.c.feng@...>; Bret Barkelew
<Bret.Barkelew@...>; Kinney, Michael D
<michael.d.kinney@...>; Sean Brogan <sean.brogan@...>
Subject: Re: [edk2-devel] [PATCH v6 00/16] Add a plugin to check Ecc issues
for edk2 on open ci

Hi Liming,

On 07/03/20 17:13, Gao, Liming wrote:
Include more people and collect the comments.

ECC is the source file coding style checker. Here is its wiki page
https://github.com/tianocore/tianocore.github.io/wiki/ECC-tool.
If the changed code doesn't follow edk2 coding style, ECC will report the
error.

This patch set enables ECC checker in open CI for each patch coming into
edk2 repo. That means new changes need to follow edk2 coding style.
Otherwise, new changes can't be merged.

If you have some comments for ECC checker in open CI, please reply this
mail.


(1) The ArmVirtPkg (v6 04/16) and OvmfPkg (v6 11/16) patches already
carry my ACKs; from here:

https://edk2.groups.io/g/devel/message/61154
https://edk2.groups.io/g/devel/message/61155


(2) The UefiCpuPkg patch (v6 15/16) *should* also carry my ACK, from here:

https://edk2.groups.io/g/devel/message/61156

Shenglei picked up my ACK for v4 and v5:

https://edk2.groups.io/g/devel/message/61283
https://edk2.groups.io/g/devel/message/61852

but then dropped it for v6:

https://edk2.groups.io/g/devel/message/61894

Shenglei, can you please explain why you dropped my ACK from the
UefiCpuPkg patch, in v6?


(3) The initial discussion between Shenglei and myself are under the v2
posting:

https://edk2.groups.io/g/devel/message/60665
https://edk2.groups.io/g/devel/message/60711
https://edk2.groups.io/g/devel/message/60961

I'm happy with this work because it lets package maintainers tailor ECC
as they see appropriate.

Thanks,
Laszlo


Re: [PATCH v2 0/2] refine TPM2 operation pull down list

Yao, Jiewen
 

Thanks.
I recommend we use full name Tpm2GetCapabilityIsCommandImplemented() instead of Tpm2GetCapabilityIsCmdImpl().

With that change, reviewed-by: Jiewen Yao <Jiewen.yao@...>

-----Original Message-----
From: Zhang, Qi1 <qi1.zhang@...>
Sent: Tuesday, June 16, 2020 3:31 PM
To: devel@edk2.groups.io
Cc: Zhang, Qi1 <qi1.zhang@...>; Yao, Jiewen <jiewen.yao@...>;
Wang, Jian J <jian.j.wang@...>; Zhang, Chao B
<chao.b.zhang@...>; Kumar, Rahul1 <rahul1.kumar@...>
Subject: [PATCH v2 0/2] refine TPM2 operation pull down list

v1 change: separate the change into two patches

Cc: Jiewen Yao <jiewen.yao@...>
Cc: Jian J Wang <jian.j.wang@...>
Cc: Chao Zhang <chao.b.zhang@...>
Cc: Rahul Kumar <rahul1.kumar@...>
Signed-off-by: Qi Zhang <qi1.zhang@...>

Qi Zhang (1):
SecurityPkg/Tcg2Config: remove TPM2_ChangEPS if it is not supported.

Zhang, Qi (1):
SecurityPkg/Tpm2CommandLib: add new function
Tpm2GetCapabilityIsCmdImpl.

SecurityPkg/Include/Library/Tpm2CommandLib.h | 16 ++++++++++++++++
SecurityPkg/Library/Tpm2CommandLib/Tpm2Capability.c | 40
++++++++++++++++++++++++++++++++++++++++
SecurityPkg/Tcg/Tcg2Config/Tcg2Config.vfr | 2 ++
SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigImpl.c | 7 +++++++
SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigNvData.h | 1 +
5 files changed, 66 insertions(+)

--
2.26.2.windows.1


Upcoming Event: TianoCore Design Meeting - APAC/NAMO - Fri, 07/10/2020 9:30am-10:30am #cal-reminder

devel@edk2.groups.io Calendar <devel@...>
 

Reminder: TianoCore Design Meeting - APAC/NAMO

When: Friday, 10 July 2020, 9:30am to 10:30am, (GMT+08:00) Asia/Chongqing

Where:https://zoom.us/j/299494771

View Event

Organizer: Ray Ni ray.ni@...

Description:

For more info, see here: https://www.tianocore.org/design-meeting/

Join Zoom Meeting

https://zoom.us/j/299494771

Meeting ID: 299 494 771

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+16699009128,,299494771# US (San Jose)

+13462487799,,299494771# US (Houston)

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Meeting ID: 299 494 771

Find your local number: https://zoom.us/u/ajd9Bs4kZ


[PATCH edk2-test 1/1] SctPkg: fix page alignment calculations

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The BBTestAllocatePagesInterfaceTest tries to allocate pages for
different memory types.
While doing so, it tries to fix up the Start and PageNum for 64K
Page size. There are multiple issues with this:

1. 64K alignment is being done regardless of Processor type and Memory
type. while this is correct for ARM64 Processor, it might not be so
for other Processor types. Also 64K alignment for ARM64 Processor
is needed for some Memory types not all.
2. The Start is being incremented by 64K, even if Start is already 64K
aligned.
3. PageNum is being decreased by 16 pages indiscriminately, which might
not be needed in all cases.

fix all these issues by correctly doing the alignment in all needed
cases.

Cc: Paul Yang <Paul.Yang@...>
Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>
Cc: Gaurav Jain <gaurav.jain@...>
Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../MemoryAllocationServicesBBTestFunction.c | 148 +++++++++++++-----
1 file changed, 106 insertions(+), 42 deletions(-)

diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
index d18fe1fc2b94..9ed9e6e0de74 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
@@ -354,6 +354,7 @@ BBTestAllocatePagesInterfaceTest (
EFI_TPL OldTpl;
EFI_MEMORY_DESCRIPTOR Descriptor;
UINTN PageNum;
+ UINTN Alignment;

//
// Get the Standard Library Interface
@@ -700,14 +701,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -830,14 +840,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -953,14 +972,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start + (SctLShiftU64 (PageNum/3, EFI_PAGE_SHIFT) & 0xFFFFFFFFFFFF0000);

@@ -1076,14 +1104,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start + (SctLShiftU64 (PageNum * 2 / 3, EFI_PAGE_SHIFT) & 0xFFFFFFFFFFFF0000);

@@ -1206,14 +1243,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -1329,14 +1375,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

@@ -1468,14 +1523,23 @@ BBTestAllocatePagesInterfaceTest (
PageNum = (UINTN)Descriptor.NumberOfPages;
Start = Descriptor.PhysicalStart;

- //
- // Some memory types need more alignment than 4K, so
- //
- if (PageNum <= 0x10) {
+ Alignment = DEFAULT_PAGE_ALLOCATION_GRANULARITY;
+
+ if (AllocatePagesMemoryType[TypeIndex] == EfiACPIReclaimMemory ||
+ AllocatePagesMemoryType[TypeIndex] == EfiACPIMemoryNVS ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesCode ||
+ AllocatePagesMemoryType[TypeIndex] == EfiRuntimeServicesData) {
+
+ Alignment = RUNTIME_PAGE_ALLOCATION_GRANULARITY;
+ }
+
+ Start = (Start + Alignment - 1) & ~(Alignment - 1);
+ PageNum -= EFI_SIZE_TO_PAGES (Start - Descriptor.PhysicalStart);
+
+ PageNum &= ~(EFI_SIZE_TO_PAGES (Alignment) - 1);
+ if (PageNum <= EFI_SIZE_TO_PAGES (Alignment)) {
break;
}
- Start = (Start + 0x10000) & 0xFFFFFFFFFFFF0000;
- PageNum = PageNum - EFI_SIZE_TO_PAGES(0x10000);

Memory = Start;

--
2.17.1


Re: UefiPayloadPkg: assert error in PciHostBridgeDxe

Andrew Fish
 



On Jul 3, 2020, at 11:06 AM, Laszlo Ersek <lersek@...> wrote:

On 07/03/20 01:03, Andrew Fish via groups.io wrote:


On Jul 2, 2020, at 3:54 PM, King Sumo <kingsumos@...> wrote:

Hi,

When booting UefiPayloadPkg in my system (x86 Denverton SoC, coreboot) an assert error is generated in the PciHostBridgeDxe driver.
In the InitializePciHostBridge() function if all ASSERT's are ignored (by commenting out the code) the boot can move further on until it reaches the UEFI Shell.
Any clues?

Loading driver at 0x0007EE61000 EntryPoint=0x0007EE6CF52 PciHostBridgeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7EF1F698
ProtectUefiImageCommon - 0x7EF1F140
 - 0x000000007EE61000 - 0x0000000000013000
SetUefiImageMemoryAttributes - 0x000000007EE61000 - 0x0000000000001000 (0x0000000000004008)
SetUefiImageMemoryAttributes - 0x000000007EE62000 - 0x0000000000010000 (0x0000000000020008)
SetUefiImageMemoryAttributes - 0x000000007EE72000 - 0x0000000000002000 (0x0000000000004008)
PROGRESS CODE: V03040002 I0
InitRootBridge: populated root bus 0, with room for 7 subordinate bus(es)
RootBridge: PciRoot(0x0)
 Support/Attr: 10003 / 10003
   DmaAbove4G: No
NoExtConfSpace: No
    AllocAttr: 0 ()
          Bus: 0 - 7 Translation=0
           Io: 0 - 4FFF Translation=0
          Mem: D4000000 - FE0FFFFF Translation=0
   MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
         PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
  PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PciHostBridgeDxe: IntersectMemoryDescriptor: desc [E0000000, F0000000) type 1 cap 870000000002600F conflicts with aperture [D4000000, FE100000) cap 1


It looks like the above request for "D4000000 - FE0FFFFF” overlaps with an existing mapping (E0000000, F0000000). The edk2 has something called GCD (Global Coherency Domain) that is kind of like malloc for MMIO space, and what part of the CPU address has DRAM. So it looks like 2 device think they own (E0000000, F0000000), and there can be only one. You may be getting lucky that your hardware works, but something seems miss configured. 

PciHostBridgeDxe calls the PciHostBridgeGetRootBridges() function from
the platform's "PciHostBridgeLib" instance. The function outputs an
array of PCI_ROOT_BRIDGE structures that describe the PCI root bridges
on the system, including the various resource apertures for each bridge
(expressed as device address ranges).

Then PciHostBridgeDxe tries to allocate the described apertures from the
according resource type GCD spaces (after translating the address ranges
in question from device addresses to host addresses).

The attempt to allocate any one such aperture consists of three steps,
(1) make sure the GCD memory map covers the aperture with compatible
descriptor(s), (2) set the aperture range to uncacheable (for MMIO only;
not defined for IO), (3) actually allocate the aperture.

In step (1), there's a slight trick. We don't call gDS->AddIoSpace() /
gDS->AddMemorySpace() indiscriminately, because the platform may have
populated the GCD memory space / IO space maps before, such that there
could be a (partial or complete) overlap with the aperture being added.

Therefore the internal AddIoSpace() and AddMemoryMappedIoSpace()
functions are idempotent. They contrast every existent GCD space
descriptor with the aperture being added (including gaps, that is,
"nonexistent" type descriptors). For the case when both ranges are fully
distinct, nothing is done. If there is a partial or full overlap, and
the descriptor is "nonexistent", then the intersection is added with
gDS->AddIoSpace() / gDS->AddMemorySpace(). If there is a partial or full
overlap, and the descriptor type is *not* "nonexistent", then the
intersection's *compatibility* is checked, against the requested type
and capabilities of the aperture.

The above procedure ensures that, for any given resource aperture, the
GCD IO or memory space map covers the aperture, with nonzero (that is,
possibly more than one!) adjacent descriptor entries, such that each
descriptor intersecting with the aperture has compatible type and
capabilities with the aperture.

In turn, the error message seen above reports a platform misconfiguration.

It reports that the GCD memory space map already has an entry (a
descriptor) at [E0000000, F0000000), with type 1 (that is,
"EfiGcdMemoryTypeReserved" -- see "MdePkg/Include/Pi/PiDxeCis.h"). The
capabilities of this range are 0x8700_0000_0002_600F

At the same time, the platform's PciHostBridgeLib instance reported a
root bridge with an MMIO aperture at [D4000000, FE100000), with
capabilities 1.

This is a conflict. The capabilities don't even matter (we don't even
check whether the existent GCD descriptor's capabilities are a superset
of the aperture's), because the aperture requires GCD memory type
EfiGcdMemoryTypeMemoryMappedIo, but the GCD descriptor has type
EfiGcdMemoryTypeReserved.

In brief, the failure is due to the platform reporting a PCI root bridge
aperture such that it overlaps an area that is already listed as
"reserved" in the GCD memory space map. So this is a platform bug;
either in the "PciHostBridgeLib" instance, or in the module that
populates the GCD memory space map.


Laszlo,

Thanks for the detailed response. 

Sumo,

In your platforms DSC file you can or in 0x00100000 by hand into gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel to turn on DEBUG_GCD and get more DEBUG prints about GCD configuration. That may help you track down what is happening. 

Thanks,

Andrew Fish

Thanks
Laszlo



Thanks,

Andrew Fish

ASSERT_EFI_ERROR (Status = Invalid Parameter)
ASSERT [PciHostBridgeDxe] /home/lxuser/occ/edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c(488): !EFI_ERROR (Status)

Thanks,
Sumo






Re: UefiPayloadPkg: assert error in PciHostBridgeDxe

Laszlo Ersek
 

On 07/03/20 01:03, Andrew Fish via groups.io wrote:


On Jul 2, 2020, at 3:54 PM, King Sumo <kingsumos@...> wrote:

Hi,

When booting UefiPayloadPkg in my system (x86 Denverton SoC, coreboot) an assert error is generated in the PciHostBridgeDxe driver.
In the InitializePciHostBridge() function if all ASSERT's are ignored (by commenting out the code) the boot can move further on until it reaches the UEFI Shell.
Any clues?

Loading driver at 0x0007EE61000 EntryPoint=0x0007EE6CF52 PciHostBridgeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7EF1F698
ProtectUefiImageCommon - 0x7EF1F140
- 0x000000007EE61000 - 0x0000000000013000
SetUefiImageMemoryAttributes - 0x000000007EE61000 - 0x0000000000001000 (0x0000000000004008)
SetUefiImageMemoryAttributes - 0x000000007EE62000 - 0x0000000000010000 (0x0000000000020008)
SetUefiImageMemoryAttributes - 0x000000007EE72000 - 0x0000000000002000 (0x0000000000004008)
PROGRESS CODE: V03040002 I0
InitRootBridge: populated root bus 0, with room for 7 subordinate bus(es)
RootBridge: PciRoot(0x0)
Support/Attr: 10003 / 10003
DmaAbove4G: No
NoExtConfSpace: No
AllocAttr: 0 ()
Bus: 0 - 7 Translation=0
Io: 0 - 4FFF Translation=0
Mem: D4000000 - FE0FFFFF Translation=0
MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PciHostBridgeDxe: IntersectMemoryDescriptor: desc [E0000000, F0000000) type 1 cap 870000000002600F conflicts with aperture [D4000000, FE100000) cap 1
It looks like the above request for "D4000000 - FE0FFFFF” overlaps with an existing mapping (E0000000, F0000000). The edk2 has something called GCD (Global Coherency Domain) that is kind of like malloc for MMIO space, and what part of the CPU address has DRAM. So it looks like 2 device think they own (E0000000, F0000000), and there can be only one. You may be getting lucky that your hardware works, but something seems miss configured.
PciHostBridgeDxe calls the PciHostBridgeGetRootBridges() function from
the platform's "PciHostBridgeLib" instance. The function outputs an
array of PCI_ROOT_BRIDGE structures that describe the PCI root bridges
on the system, including the various resource apertures for each bridge
(expressed as device address ranges).

Then PciHostBridgeDxe tries to allocate the described apertures from the
according resource type GCD spaces (after translating the address ranges
in question from device addresses to host addresses).

The attempt to allocate any one such aperture consists of three steps,
(1) make sure the GCD memory map covers the aperture with compatible
descriptor(s), (2) set the aperture range to uncacheable (for MMIO only;
not defined for IO), (3) actually allocate the aperture.

In step (1), there's a slight trick. We don't call gDS->AddIoSpace() /
gDS->AddMemorySpace() indiscriminately, because the platform may have
populated the GCD memory space / IO space maps before, such that there
could be a (partial or complete) overlap with the aperture being added.

Therefore the internal AddIoSpace() and AddMemoryMappedIoSpace()
functions are idempotent. They contrast every existent GCD space
descriptor with the aperture being added (including gaps, that is,
"nonexistent" type descriptors). For the case when both ranges are fully
distinct, nothing is done. If there is a partial or full overlap, and
the descriptor is "nonexistent", then the intersection is added with
gDS->AddIoSpace() / gDS->AddMemorySpace(). If there is a partial or full
overlap, and the descriptor type is *not* "nonexistent", then the
intersection's *compatibility* is checked, against the requested type
and capabilities of the aperture.

The above procedure ensures that, for any given resource aperture, the
GCD IO or memory space map covers the aperture, with nonzero (that is,
possibly more than one!) adjacent descriptor entries, such that each
descriptor intersecting with the aperture has compatible type and
capabilities with the aperture.

In turn, the error message seen above reports a platform misconfiguration.

It reports that the GCD memory space map already has an entry (a
descriptor) at [E0000000, F0000000), with type 1 (that is,
"EfiGcdMemoryTypeReserved" -- see "MdePkg/Include/Pi/PiDxeCis.h"). The
capabilities of this range are 0x8700_0000_0002_600F

At the same time, the platform's PciHostBridgeLib instance reported a
root bridge with an MMIO aperture at [D4000000, FE100000), with
capabilities 1.

This is a conflict. The capabilities don't even matter (we don't even
check whether the existent GCD descriptor's capabilities are a superset
of the aperture's), because the aperture requires GCD memory type
EfiGcdMemoryTypeMemoryMappedIo, but the GCD descriptor has type
EfiGcdMemoryTypeReserved.

In brief, the failure is due to the platform reporting a PCI root bridge
aperture such that it overlaps an area that is already listed as
"reserved" in the GCD memory space map. So this is a platform bug;
either in the "PciHostBridgeLib" instance, or in the module that
populates the GCD memory space map.

Thanks
Laszlo



Thanks,

Andrew Fish

ASSERT_EFI_ERROR (Status = Invalid Parameter)
ASSERT [PciHostBridgeDxe] /home/lxuser/occ/edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c(488): !EFI_ERROR (Status)

Thanks,
Sumo





2nd OVMF question about why InitRootBridge does not set ResourceAssigned?

Andrew Fish
 

When tacking down the EFI_MEMORY_UC issue I noticed that InitRootBridg() [1] does not set RootBus-> ResourceAssigned = TRUE. If it was TRUE then the entire PCI aptitude would end up in the GCD map. Given it is not set (set by ZeroMem) the EFI_MEMORY_UC only ends up for the actual allocations as far as I can tell. I’m wondering why it was done this way?

I did notice if I set RootBus-> ResourceAssigned to TRUE the serial console did not come up and I did not get a chance to debug that? Maybe there was a resource conflict with the ISA bus driver or some such?

[1] https://github.com/tianocore/edk2/blob/master/OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c#L112

Thanks,

Andrew Fish