Date   

Re: [PATCH] BaseTools/Python: Add missing FatalError handling

Bob Feng
 

Hi Irene,

For this piece of code
+ self.feedback_q.put(taskname)
+ self.feedback_q.put(e.args[0])

I think there will be the case that another autogenworker process insert its taskname before the current autogenworker process do self.feedback_q.put(e.args[0]). If that case happens, the build tool will hang.

Thanks,
Bob

-----Original Message-----
From: Irene Park <ipark@...>
Sent: Friday, May 29, 2020 3:24 AM
To: devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@...>; Gao, Liming <liming.gao@...>
Subject: RE: [PATCH] BaseTools/Python: Add missing FatalError handling

A gentle reminder and adding Bob Feng and Liming Gao to CC.
Thank you,
Irene

-----Original Message-----
From: Irene Park <ipark@...>
Sent: Wednesday, May 27, 2020 3:42 PM
To: devel@edk2.groups.io
Cc: Irene Park <ipark@...>
Subject: [PATCH] BaseTools/Python: Add missing FatalError handling

From: Irene Park <ipark@...>

AutoGenWorker doesn't handle the exception from FatalError therefore the build fails to return the proper error code at the exit.

Signed-off-by: Irene Park <ipark@...>
---
BaseTools/Source/Python/AutoGen/AutoGenWorker.py | 6 ++++++
BaseTools/Source/Python/build/build.py | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/AutoGen/AutoGenWorker.py b/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
index 563d91b..2395964 100755
--- a/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
+++ b/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
@@ -24,6 +24,7 @@ import traceback
import sys
from AutoGen.DataPipe import MemoryDataPipe import logging
+from Common.BuildToolError import FatalError

def clearQ(q):
try:
@@ -101,6 +102,7 @@ class AutoGenManager(threading.Thread):
self.autogen_workers = autogen_workers
self.feedback_q = feedback_q
self.Status = True
+ self.Error = 0
self.error_event = error_event
def run(self):
try:
@@ -113,6 +115,7 @@ class AutoGenManager(threading.Thread):
fin_num += 1
else:
self.Status = False
+ self.Error = self.feedback_q.get()
self.TerminateWorkers()
if fin_num == len(self.autogen_workers):
self.clearQueue()
@@ -282,6 +285,9 @@ class AutoGenWorkerInProcess(mp.Process):

except Empty:
pass
+ except FatalError as e:
+ self.feedback_q.put(taskname)
+ self.feedback_q.put(e.args[0])
except:
self.feedback_q.put(taskname)
finally:
diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index ed3a3b9..d6e3d84 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -880,7 +880,10 @@ class Build():

self.AutoGenMgr.join()
rt = self.AutoGenMgr.Status
- return rt, 0
+ err = 0
+ if not rt:
+ err = self.AutoGenMgr.Error
+ return rt, err
except FatalError as e:
return False, e.args[0]
except:
--
2.7.4


Re: AcpiView Patches

Gao, Zhichao
 

Sorry, Pilar. I am busy at other things. Plan to review the shellpkg patch in next two weeks.

 

Thanks,

Zhichao

 

From: Tomas Pilar <Tomas.Pilar@...>
Sent: Thursday, May 28, 2020 6:55 PM
To: devel@edk2.groups.io; Ni, Ray <ray.ni@...>; Gao, Zhichao <zhichao.gao@...>
Cc: nd <nd@...>
Subject: AcpiView Patches

 

Hi,

 

Any chance you had time to look at my AcpiView patches?

 

Cheers,

Tom


Re: [edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing __init__.py files

Bjorge, Erik C
 

Reviewed-by: Erik Bjorge <erik.c.bjorge@...>

-----Original Message-----
From: Desimone, Nathaniel L <nathaniel.l.desimone@...>
Sent: Thursday, May 28, 2020 2:31 PM
To: Desimone, Ashley E <ashley.e.desimone@...>; devel@edk2.groups.io
Cc: Pandya, Puja <puja.pandya@...>; Bjorge, Erik C <erik.c.bjorge@...>; Bret Barkelew <Bret.Barkelew@...>; Agyeman, Prince <prince.agyeman@...>
Subject: RE: [edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing __init__.py files

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Desimone, Ashley E <ashley.e.desimone@...>
Sent: Thursday, May 28, 2020 2:29 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Pandya,
Puja <puja.pandya@...>; Bjorge, Erik C
<erik.c.bjorge@...>; Bret Barkelew
<Bret.Barkelew@...>; Agyeman, Prince
<prince.agyeman@...>
Subject: [edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing
__init__.py files

Signed-off-by: Ashley E Desimone <ashley.e.desimone@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Puja Pandya <puja.pandya@...>
Cc: Erik Bjorge <erik.c.bjorge@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
edkrepo/common/workspace_maintenance/__init__.py | 8 ++++++++
edkrepo/common/workspace_maintenance/humble/__init__.py | 8
++++++++
edkrepo/config/humble/__init__.py | 8 ++++++++
3 files changed, 24 insertions(+)
create mode 100644
edkrepo/common/workspace_maintenance/__init__.py
create mode 100644
edkrepo/common/workspace_maintenance/humble/__init__.py
create mode 100644 edkrepo/config/humble/__init__.py

diff --git a/edkrepo/common/workspace_maintenance/__init__.py
b/edkrepo/common/workspace_maintenance/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

diff --git a/edkrepo/common/workspace_maintenance/humble/__init__.py
b/edkrepo/common/workspace_maintenance/humble/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

diff --git a/edkrepo/config/humble/__init__.py
b/edkrepo/config/humble/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/config/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

--
2.26.2.windows.1


Re: [edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing __init__.py files

Nate DeSimone
 

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Desimone, Ashley E <ashley.e.desimone@...>
Sent: Thursday, May 28, 2020 2:29 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Pandya, Puja
<puja.pandya@...>; Bjorge, Erik C <erik.c.bjorge@...>; Bret
Barkelew <Bret.Barkelew@...>; Agyeman, Prince
<prince.agyeman@...>
Subject: [edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing __init__.py
files

Signed-off-by: Ashley E Desimone <ashley.e.desimone@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Puja Pandya <puja.pandya@...>
Cc: Erik Bjorge <erik.c.bjorge@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
edkrepo/common/workspace_maintenance/__init__.py | 8 ++++++++
edkrepo/common/workspace_maintenance/humble/__init__.py | 8
++++++++
edkrepo/config/humble/__init__.py | 8 ++++++++
3 files changed, 24 insertions(+)
create mode 100644
edkrepo/common/workspace_maintenance/__init__.py
create mode 100644
edkrepo/common/workspace_maintenance/humble/__init__.py
create mode 100644 edkrepo/config/humble/__init__.py

diff --git a/edkrepo/common/workspace_maintenance/__init__.py
b/edkrepo/common/workspace_maintenance/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

diff --git a/edkrepo/common/workspace_maintenance/humble/__init__.py
b/edkrepo/common/workspace_maintenance/humble/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

diff --git a/edkrepo/config/humble/__init__.py
b/edkrepo/config/humble/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/config/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3

+#

+## @file

+# __init__.py

+#

+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

--
2.26.2.windows.1


[edk2-staging/EdkRepo] [PATCH] EdkRepo: Add missing __init__.py files

Ashley E Desimone
 

Signed-off-by: Ashley E Desimone <ashley.e.desimone@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Puja Pandya <puja.pandya@...>
Cc: Erik Bjorge <erik.c.bjorge@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
edkrepo/common/workspace_maintenance/__init__.py | 8 ++++++++
edkrepo/common/workspace_maintenance/humble/__init__.py | 8 ++++++++
edkrepo/config/humble/__init__.py | 8 ++++++++
3 files changed, 24 insertions(+)
create mode 100644 edkrepo/common/workspace_maintenance/__init__.py
create mode 100644 edkrepo/common/workspace_maintenance/humble/__init__.py
create mode 100644 edkrepo/config/humble/__init__.py

diff --git a/edkrepo/common/workspace_maintenance/__init__.py b/edkrepo/com=
mon/workspace_maintenance/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3=0D
+#=0D
+## @file=0D
+# __init__.py=0D
+#=0D
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
diff --git a/edkrepo/common/workspace_maintenance/humble/__init__.py b/edkr=
epo/common/workspace_maintenance/humble/__init__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/common/workspace_maintenance/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3=0D
+#=0D
+## @file=0D
+# __init__.py=0D
+#=0D
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
diff --git a/edkrepo/config/humble/__init__.py b/edkrepo/config/humble/__in=
it__.py
new file mode 100644
index 0000000..0486261
--- /dev/null
+++ b/edkrepo/config/humble/__init__.py
@@ -0,0 +1,8 @@
+#!/usr/bin/env python3=0D
+#=0D
+## @file=0D
+# __init__.py=0D
+#=0D
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
--=20
2.26.2.windows.1


Re: [PATCH] uefi-sct/SctPkg: Remove gEfiFormBrowserExProtocolGuid

Irene Park
 

-----Original Message-----
From: Irene Park <ipark@...>
Sent: Thursday, May 28, 2020 3:19 PM
To: devel@edk2.groups.io
Cc: Irene Park <ipark@...>
Subject: [PATCH] uefi-sct/SctPkg: Remove gEfiFormBrowserExProtocolGuid

From: Irene Park <ipark@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2145

Replace the gEfiFormBrowserExProtocolGuid with gEdkiiFormBrowserExProtocolGuid, remove the unnecessary declaration.

Signed-off-by: Irene Park <ipark@...>
---
.../BlackBoxTest/Dependency/SampleDriver/DriverSample.c | 4 ++--
.../BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c
index d495afd..fe973a3 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/Bl
+++ ackBoxTest/Dependency/SampleDriver/DriverSample.c
@@ -1893,7 +1893,7 @@ DriverSampleInit (
EFI_STRING NameRequestHdr;
MY_EFI_VARSTORE_DATA *VarStoreConfig;
EFI_INPUT_KEY HotKey;
- EFI_FORM_BROWSER_EXTENSION_PROTOCOL *FormBrowserEx;
+ EDKII_FORM_BROWSER_EXTENSION_PROTOCOL *FormBrowserEx;
#if 1
EFI_STRING Progress;
EFI_STRING Results;
@@ -2190,7 +2190,7 @@ DriverSampleInit (
//
// Example of how to use BrowserEx protocol to register HotKey.
//
- Status = gBS->LocateProtocol (&gEfiFormBrowserExProtocolGuid, NULL, (VOID **) &FormBrowserEx);
+ Status = gBS->LocateProtocol (&gEdkiiFormBrowserExProtocolGuid, NULL,
+ (VOID **) &FormBrowserEx);
if (!EFI_ERROR (Status)) {
//
// First unregister the default hot key F9 and F10.
diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
index cfa049e..75cb6fb 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/Bl
+++ ackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
@@ -99,7 +99,7 @@
gEfiFormBrowser2ProtocolGuid ## CONSUMES
gEfiHiiDatabaseProtocolGuid ## CONSUMES
gEfiSimpleTextInputExProtocolGuid ## SOMETIMES_CONSUMES
- gEfiFormBrowserExProtocolGuid ## CONSUMES
+ gEdkiiFormBrowserExProtocolGuid ## CONSUMES
gBlackBoxEfiConfigKeywordHandlerProtocolGuid ## CONSUMES

[Depex]
--
2.7.4


Re: [PATCH v2] ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics

Laszlo Ersek
 

On 05/28/20 17:48, Gao, Liming wrote:
Leif:
BZ 2723 is a tiano feature request. This patch adds support for new GCC10. I agree with Laszlo that this change is like the enhancement instead of the critical bug fix. So, I suggest to delay it after this stable tag.
In <https://bugzilla.tianocore.org/show_bug.cgi?id=2723#c22> I mentioned
"If there's strong disagreement, we can revert these BZ field changes",
and in another mailing list thread Leif pointed out that the patch only
affects builds that would otherwise fail.

So at the moment I'm neutral on this work; I'm fine either way (merged
or postponed).

Liming: would you consider merging if we delayed the stable tag by a few
days (mid next week)?

Anyway, let me fade into the background on this topic.

Thanks
Laszlo

-----Original Message-----
From: Leif Lindholm <leif@...>
Sent: Thursday, May 28, 2020 5:49 PM
To: Gary Lin <glin@...>
Cc: devel@edk2.groups.io; ard.biesheuvel@...; lersek@...; Gao, Liming <liming.gao@...>
Subject: Re: [edk2-devel] [PATCH v2] ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics

On Thu, May 28, 2020 at 09:36:33 +0800, Gary Lin wrote:
On Wed, May 20, 2020 at 01:44:48PM +0200, Ard Biesheuvel wrote:
Gary reports the GCC 10 will emit calls to atomics intrinsics routines
unless -mno-outline-atomics is specified. This means GCC-10 introduces
new intrinsics, and even though it would be possible to work around this
by specifying the command line option, this would require a new GCC10
toolchain profile to be created, which we prefer to avoid.

So instead, add the new intrinsics to our library so they are provided
when necessary.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
After applying this patch, gcc 10 can build ArmVirtPkg without the
linking error.

Tested-by: Gary Lin <glin@...>
Thanks Gary.

Liming, can we consider this patch for stable tag please?

With an added link to
https://bugzilla.tianocore.org/show_bug.cgi?id=2723 in the commit message:
Reviewed-by: Leif Lindholm <leif@...>

/
Leif

---
v2:
- add missing .globl to export the functions from the object file
- add function end markers so the size of each is visible in the ELF metadata
- add some comments to describe what is going on

ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 3 +
ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S | 142 ++++++++++++++++++++
2 files changed, 145 insertions(+)

diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
index d5bad9467758..fcf48c678119 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
@@ -79,6 +79,9 @@ [Sources.ARM]
Arm/ldivmod.asm | MSFT
Arm/llsr.asm | MSFT

+[Sources.AARCH64]
+ AArch64/Atomics.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
new file mode 100644
index 000000000000..dc61d6bb8e52
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
@@ -0,0 +1,142 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2020, Arm, Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ /*
+ * Provide the GCC intrinsics that are required when using GCC 9 or
+ * later with the -moutline-atomics options (which became the default
+ * in GCC 10)
+ */
+ .arch armv8-a
+
+ .macro reg_alias, pfx, sz
+ r0_\sz .req \pfx\()0
+ r1_\sz .req \pfx\()1
+ tmp0_\sz .req \pfx\()16
+ tmp1_\sz .req \pfx\()17
+ .endm
+
+ /*
+ * Define register aliases of the right type for each size
+ * (xN for 8 bytes, wN for everything smaller)
+ */
+ reg_alias w, 1
+ reg_alias w, 2
+ reg_alias w, 4
+ reg_alias x, 8
+
+ .macro fn_start, name:req
+ .section .text.\name
+ .globl \name
+ .type \name, %function
+\name\():
+ .endm
+
+ .macro fn_end, name:req
+ .size \name, . - \name
+ .endm
+
+ /*
+ * Emit an atomic helper for \model with operands of size \sz, using
+ * the operation specified by \insn (which is the LSE name), and which
+ * can be implemented using the generic load-locked/store-conditional
+ * (LL/SC) sequence below, using the arithmetic operation given by
+ * \opc.
+ */
+ .macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a, l
+ fn_start __aarch64_\insn\()\sz\()\model
+ mov tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x1]
+ .ifnc \insn, swp
+ \opc tmp1_\sz, r0_\sz, tmp0_\sz
+ .else
+ \opc tmp1_\sz, tmp0_\sz
+ .endif
+ st\l\()xr\s w15, tmp1_\sz, [x1]
+ cbnz w15, 0b
+ ret
+ fn_end __aarch64_\insn\()\sz\()\model
+ .endm
+
+ /*
+ * Emit atomic helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8}, for the instruction pattern given by
+ * \insn. (This is the LSE name, but this implementation uses
+ * the generic LL/SC sequence using \opc as the arithmetic
+ * operation on the target.)
+ */
+ .macro emit_ld, insn:req, opc:req, model:req, a, l
+ emit_ld_sz 1, \insn, \opc, \model, b, \a, \l
+ emit_ld_sz 2, \insn, \opc, \model, h, \a, \l
+ emit_ld_sz 4, \insn, \opc, \model, , \a, \l
+ emit_ld_sz 8, \insn, \opc, \model, , \a, \l
+ .endm
+
+ /*
+ * Emit the compare and swap helper for \model and size \sz
+ * using LL/SC instructions.
+ */
+ .macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l
+ fn_start __aarch64_cas\sz\()\model
+ \uxt tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x2]
+ cmp r0_\sz, tmp0_\sz
+ bne 1f
+ st\l\()xr\s w15, r1_\sz, [x2]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas\sz\()\model
+ .endm
+
+ /*
+ * Emit compare-and-swap helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8, 16}.
+ */
+ .macro emit_cas, model:req, a, l
+ emit_cas_sz 1, \model, uxtb, b, \a, \l
+ emit_cas_sz 2, \model, uxth, h, \a, \l
+ emit_cas_sz 4, \model, mov , , \a, \l
+ emit_cas_sz 8, \model, mov , , \a, \l
+
+ /*
+ * We cannot use the parameterized sequence for 16 byte CAS, so we
+ * need to define it explicitly.
+ */
+ fn_start __aarch64_cas16\model
+ mov x16, x0
+ mov x17, x1
+0: ld\a\()xp x0, x1, [x4]
+ cmp x0, x16
+ ccmp x1, x17, #0, eq
+ bne 1f
+ st\l\()xp w15, x16, x17, [x4]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas16\model
+ .endm
+
+ /*
+ * Emit the set of GCC outline atomic helper functions for
+ * the memory ordering model given by \model:
+ * - relax unordered loads and stores
+ * - acq load-acquire, unordered store
+ * - rel unordered load, store-release
+ * - acq_rel load-acquire, store-release
+ */
+ .macro emit_model, model:req, a, l
+ emit_ld ldadd, add, \model, \a, \l
+ emit_ld ldclr, bic, \model, \a, \l
+ emit_ld ldeor, eor, \model, \a, \l
+ emit_ld ldset, orr, \model, \a, \l
+ emit_ld swp, mov, \model, \a, \l
+ emit_cas \model, \a, \l
+ .endm
+
+ emit_model _relax
+ emit_model _acq, a
+ emit_model _rel,, l
+ emit_model _acq_rel, a, l
--
2.17.1




Re: [PATCH v2 1/1] CryptoPkg: Fix VS2017 build problem for ARM/AARCH64

Laszlo Ersek
 

On 05/28/20 12:15, Leif Lindholm wrote:
On Wed, May 27, 2020 at 20:34:02 +0200, Laszlo Ersek wrote:
+Ard, +Leif, and maybe we should consider this for edk2-stable202005?
Hmm, if this has never worked on MSFT:ARM/AArch64, I don't think it
would qualify even during soft freeze? (Whereas if it was a question
of making it work on vs2019 afer having worked with vs2017 it would.)

Don't get me wrong, I think this is excellent, but I think it can wait
until after release.

Will have a look at the patch itself on the original thread.
Thanks for reviewing the situation!
Laszlo


Regards,

Leif

Thanks,
Laszlo

On 05/27/20 18:04, Rebecca Cran wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2029

1. CryptPkcs7VerifyEku.c contains internal/x509_int.h header file, this
file contains internal/refcount.h file, if _M_ARM or _M_ARM64
defined, it will contains (intrin.h).
So we undef these flags for MSVC. It will fix include header
dependence problem(intrin.h).

2. ARM with MSFT toolchain was not enabled in BuildOptions, So
add CC_FLAGS for ARM/AARCH64 into OpensslLib[Crypto].inf BuildOptions
section to fix build problem.

Cc: Jian J Wang <jian.j.wang@...>
Signed-off-by: Xiaoyu Lu <xiaoyux.lu@...>
---
CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf | 2 ++
CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf | 2 ++
CryptoPkg/Library/OpensslLib/OpensslLib.inf | 2 ++
CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf | 2 ++
4 files changed, 8 insertions(+)

diff --git a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
index 4aae2aba95d6..4ed5b8265563 100644
--- a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
@@ -94,6 +94,8 @@ [BuildOptions]
# C4090: 'function' : different 'const' qualifiers
#
MSFT:*_*_*_CC_FLAGS = /wd4090
+ MSFT:*_*_ARM_CC_FLAGS = /wd4090 /U_M_ARM /U_M_ARM64
+ MSFT:*_*_AARCH64_CC_FLAGS = /wd4090 /U_M_ARM /U_M_ARM64

# -JCryptoPkg/Include : To disable the use of the system includes provided by RVCT
# --diag_remark=1 : Reduce severity of "#1-D: last line of file ends without a newline"
diff --git a/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
index dc28e3a11d48..0e66d935ead8 100644
--- a/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
@@ -84,6 +84,8 @@ [BuildOptions]
# C4718: 'function call' : recursive call has no side effects, deleting
#
MSFT:*_*_*_CC_FLAGS = /wd4090 /wd4718
+ MSFT:*_*_ARM_CC_FLAGS = /wd4090 /wd4718 /U_M_ARM /U_M_ARM64
+ MSFT:*_*_AARCH64_CC_FLAGS = /wd4090 /wd4718 /U_M_ARM /U_M_ARM64

# -JCryptoPkg/Include : To disable the use of the system includes provided by RVCT
# --diag_remark=1 : Reduce severity of "#1-D: last line of file ends without a newline"
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index c8ec9454bd90..c43c7bad4982 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -619,6 +619,8 @@ [BuildOptions]
#
MSFT:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4310 /wd4389 /wd4700 /wd4702 /wd4706 /wd4819
MSFT:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819
+ MSFT:*_*_ARM_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819
+ MSFT:*_*_AARCH64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819

INTEL:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC $(OPENSSL_FLAGS) /w
INTEL:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC $(OPENSSL_FLAGS) /w
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
index 2f232e3e1289..594717331f68 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
@@ -568,6 +568,8 @@ [BuildOptions]
#
MSFT:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4310 /wd4389 /wd4700 /wd4702 /wd4706 /wd4819
MSFT:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819
+ MSFT:*_*_ARM_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819
+ MSFT:*_*_AARCH64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER $(OPENSSL_FLAGS) /wd4090 /wd4132 /wd4244 /wd4245 /wd4267 /wd4306 /wd4310 /wd4700 /wd4389 /wd4702 /wd4706 /wd4819

INTEL:*_*_IA32_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC $(OPENSSL_FLAGS) /w
INTEL:*_*_X64_CC_FLAGS = -U_WIN32 -U_WIN64 -U_MSC_VER -U__ICC $(OPENSSL_FLAGS) /w


Re: [PATCH] MdePkg/Include: AARCH64: disable outline atomics on GCC 10.2+

Laszlo Ersek
 

On 05/28/20 12:05, Leif Lindholm wrote:
On Wed, May 27, 2020 at 11:12:23 +0200, Laszlo Ersek wrote:
Oh and I think both this patch and the assembly language implementation
for the atomics should be delayed after the stable tag. gcc-10 is a new
toolchain; so even if we don't introduce a new toolchain tag such as
GCC10 for it, whatever we do in order to make it work, that's feature
enablement in my book.
Works for me. By the time the next stable tag comes around, early adopters
that are now on GCC 10.1 will likely have moved to 10.2 by that time, and so
we may not need the assembly patch at all.
I'm not ecstatic that we'll be releasing the first stable tag known to
break with current toolchains.
If this breakage affects "current toolchains", then why was
<https://bugzilla.tianocore.org/show_bug.cgi?id=2723> only reported on
2020-May-19, four days into the soft feature freeze?
I agree the timing is crap.

This isn't just affecting random crazies pulling latest toolchains
down, but people using their distro defaults (native or cross).
... "people using their distro defaults" to *not* build upstream edk2
until 2020-May-19, apparently.
Or distro defaults changing in between. I mean, we could say "Arch
is the same as any other distro's unstable", but I wouldn't want to go
down that route - I know people who use it for developing also for
qemu and linux.

Argh, I also just realised the error report I saw two days after
Ard's intrinsics patch hit the list was not a public report. Yes, if
this had affected only in-development/unstable distributions, I agree
this isn't something we should try to deal with upstream.

I don't recall if 10.1 ended up being default in F32, but it was
definitely included. In Arch, it does appear default.

Debian/Ubuntu are unaffected in their stable releases.

I agree it's a transitional issue, but I would really prefer to have
the intrinsics included in the release.
OK, let's delay the release then, by a few days. I agree the present
patch may qualify as a bugfix, but the other patch with the assembly
language intrinsics doesn't. If it's really that important to have in
the upcoming stable tag, then it's worth delaying the tag for. I'm fine
delaying the release for it; it wouldn't be without precedent.
I would argue it *is* a bugfix, since it only has an effect on builds
that would otherwise fail.
OK. That's a good argument. From my POV, feel free to merge (both patches).

Thanks
Laszlo

But I also do think it is important enough
to delay the release if we feel that is necessary.

/
Leif

Also, I think Ard's assembly language patch needs a Tested-by from Gary
at the least (reporter of TianoCore#2723). Please reach out to him in
that thread.

... More precisely, please *ping* Gary for a Tested-by in that thread,
because Ard CC'd him from the start, and even credited Gary in the
commit message.

Thanks,
Laszlo


Re: [PATCH v2 4/5] ArmPkg/PlatformBootManagerLib: hide UEFI Shell as a regular boot option

Laszlo Ersek
 

On 05/28/20 11:17, Ard Biesheuvel wrote:
Without ConnectAll() being called on the boot path, the UEFI shell will
be entered with no block devices or anything else connected, and so for
the novice user, this is not a very accommodating environment. Now that
we have made the UiApp the last resort on boot failure, and made the
UEFI Shell accessible directly via the 's' hotkey if you really need
it, let's hide it as an ordinary boot option.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
---
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
index 85cb32f6d7cd..1e9b736993d0 100644
--- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
+++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -777,9 +777,7 @@ PlatformBootManagerAfterConsole (
//
Key.ScanCode = SCAN_NULL;
Key.UnicodeChar = L's';
- PlatformRegisterFvBootOption (
- &gUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE, &Key
- );
+ PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key);
}

/**
Reviewed-by: Laszlo Ersek <lersek@...>


Re: [PATCH v2 3/5] MdeModulePkg/BootManagerUiLib: show inactive boot options

Laszlo Ersek
 

On 05/28/20 11:17, Ard Biesheuvel wrote:
UEFI boot options may exist but have the LOAD_OPTION_ACTIVE flag
cleared. This means that the boot option should not be selected
by default, but it does not mean it should be omitted from the
boot selection presented by the boot manager: for this purpose,
another flag LOAD_OPTION_HIDDEN exists.

Given that the latter flag exists solely for the purpose of omitting
boot options from the boot selection menu, and LOAD_OPTION_XXX flags
can be combined if desired, hiding inactive boot options as well is
a mistake, and violates the intent of paragraph 3.1.3 of the UEFI
specification (revision 2.8 errata A). Let's fix this by dropping
the LOAD_OPTION_ACTIVE check from the code that populates the boot
selection menu.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
---
MdeModulePkg/Library/BootManagerUiLib/BootManager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Library/BootManagerUiLib/BootManager.c b/MdeModulePkg/Library/BootManagerUiLib/BootManager.c
index 13b40e11b396..4b2c4c77a124 100644
--- a/MdeModulePkg/Library/BootManagerUiLib/BootManager.c
+++ b/MdeModulePkg/Library/BootManagerUiLib/BootManager.c
@@ -535,9 +535,9 @@ UpdateBootManager (
mKeyInput++;

//
- // Don't display the hidden/inactive boot option
+ // Don't display hidden boot options, but retain inactive ones.
//
- if (((BootOption[Index].Attributes & LOAD_OPTION_HIDDEN) != 0) || ((BootOption[Index].Attributes & LOAD_OPTION_ACTIVE) == 0)) {
+ if ((BootOption[Index].Attributes & LOAD_OPTION_HIDDEN) != 0) {
continue;
}

Reviewed-by: Laszlo Ersek <lersek@...>


Re: [PATCH 5/5] ShellPkg: add BootManager library to add UEFI Shell menu option

Laszlo Ersek
 

On 05/27/20 19:22, Ard Biesheuvel wrote:
On 5/27/20 5:57 PM, Laszlo Ersek wrote:
On 05/26/20 18:13, Ard Biesheuvel wrote:
Add a plug-in library for UiApp that creates a 'UEFI Shell' menu
option at the root level which gives access to a form that allows
the UEFI Shell to be launched.

This gives the PlatformBootManagerLib implementation of the platform
more flexibility in the way it handles boot options pointing to the
UEFI Shell, which will typically be invoked with only the boot path
connected on fast boots.

This library may be incorporated to a platform build by adding a
NULL resolution to the <LibraryClasses> section of the UiApp.inf
{} block in the platform .DSC

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
---
  ShellPkg/Library/ShellBootManagerLib/ShellBootManagerLib.inf |  45
++++
  ShellPkg/Library/ShellBootManagerLib/ShellBootManagerLib.h   |  44
++++
  ShellPkg/Library/ShellBootManagerLib/ShellBootManagerLib.c   | 258
++++++++++++++++++++
  ShellPkg/Library/ShellBootManagerLib/ShellBmStrings.uni      |  17 ++
  ShellPkg/Library/ShellBootManagerLib/ShellBmVfr.Vfr          |  37 +++
  5 files changed, 401 insertions(+)
I've had to go back to the blurb and re-read this part, to understand
the goal of this patch:

- finally, add a plugin library for UiApp to expose the UEFI Shell
via an
   ordinary main menu option (this works around the fact that patch
#3 will
   result in the UEFI Shell disappearing from the Boot Manager list).
   Entering the shell this way will resemble the old situation, given
that
   UiApp connects all devices and refreshes all boot options etc at
launch.
If I understand correctly:

- patch #3 does two things: it clears LOAD_OPTION_ACTIVE (preventing the
   boot manager from auto-booting the shell), and sets LOAD_OPTION_HIDDEN
   (hiding the boot option from UiApp),

- patch #5 undoes LOAD_OPTION_HIDDEN, in effect -- it makes sure that we
   still see the shell option "somewhere" in UiApp (not among the boot
   options, but at the root level)

Can we:

- drop patch#5, and

- pass zero (0) as "Attributes" to PlatformRegisterFvBootOption() in
   patch#3, rather than LOAD_OPTION_HIDDEN?

Because, per spec, Attributes=0 should prevent the auto-booting of the
shell *without* hiding the shell boot option from the menu.
I feel slightly silly having gone through all the trouble of writing
this patch. I tried playing with the ACTIVE and HIDDEN options, and
couldn't get this to work. If I understand these quotes correctly, this
is an error, and instead of working around this, we should apply the
following patch to correct it:

--- a/MdeModulePkg/Library/BootManagerUiLib/BootManager.c
+++ b/MdeModulePkg/Library/BootManagerUiLib/BootManager.c
@@ -537,7 +537,7 @@ UpdateBootManager (
     //
     // Don't display the hidden/inactive boot option
     //
-    if (((BootOption[Index].Attributes & LOAD_OPTION_HIDDEN) != 0) ||
((BootOption[Index].Attributes & LOAD_OPTION_ACTIVE) == 0)) {
+    if (((BootOption[Index].Attributes & LOAD_OPTION_HIDDEN) != 0)) {
       continue;
     }


With this change applied, adding the shell option without the 'active'
or 'hidden' flags works as expected: it appears in the boot manager
menu, but is not booted automatically.
I enthusiastically agree that we should apply your above
BootManagerUiLib patch. I don't see why (per spec) the UI should hide a
boot option just because it is inactive.

Thanks!
Laszlo


Re: [PATCH] BaseTools/Python: Add missing FatalError handling

Irene Park <ipark@...>
 

A gentle reminder and adding Bob Feng and Liming Gao to CC.
Thank you,
Irene

-----Original Message-----
From: Irene Park <ipark@...>
Sent: Wednesday, May 27, 2020 3:42 PM
To: devel@edk2.groups.io
Cc: Irene Park <ipark@...>
Subject: [PATCH] BaseTools/Python: Add missing FatalError handling

From: Irene Park <ipark@...>

AutoGenWorker doesn't handle the exception from FatalError therefore the build fails to return the proper error code at the exit.

Signed-off-by: Irene Park <ipark@...>
---
BaseTools/Source/Python/AutoGen/AutoGenWorker.py | 6 ++++++
BaseTools/Source/Python/build/build.py | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/AutoGen/AutoGenWorker.py b/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
index 563d91b..2395964 100755
--- a/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
+++ b/BaseTools/Source/Python/AutoGen/AutoGenWorker.py
@@ -24,6 +24,7 @@ import traceback
import sys
from AutoGen.DataPipe import MemoryDataPipe import logging
+from Common.BuildToolError import FatalError

def clearQ(q):
try:
@@ -101,6 +102,7 @@ class AutoGenManager(threading.Thread):
self.autogen_workers = autogen_workers
self.feedback_q = feedback_q
self.Status = True
+ self.Error = 0
self.error_event = error_event
def run(self):
try:
@@ -113,6 +115,7 @@ class AutoGenManager(threading.Thread):
fin_num += 1
else:
self.Status = False
+ self.Error = self.feedback_q.get()
self.TerminateWorkers()
if fin_num == len(self.autogen_workers):
self.clearQueue()
@@ -282,6 +285,9 @@ class AutoGenWorkerInProcess(mp.Process):

except Empty:
pass
+ except FatalError as e:
+ self.feedback_q.put(taskname)
+ self.feedback_q.put(e.args[0])
except:
self.feedback_q.put(taskname)
finally:
diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index ed3a3b9..d6e3d84 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -880,7 +880,10 @@ class Build():

self.AutoGenMgr.join()
rt = self.AutoGenMgr.Status
- return rt, 0
+ err = 0
+ if not rt:
+ err = self.AutoGenMgr.Error
+ return rt, err
except FatalError as e:
return False, e.args[0]
except:
--
2.7.4


[PATCH] uefi-sct/SctPkg: Remove gEfiFormBrowserExProtocolGuid

Name <ipark@...>
 

From: Irene Park <ipark@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2145

Replace the gEfiFormBrowserExProtocolGuid with
gEdkiiFormBrowserExProtocolGuid, remove the unnecessary declaration.

Signed-off-by: Irene Park <ipark@...>
---
.../BlackBoxTest/Dependency/SampleDriver/DriverSample.c | 4 ++--
.../BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c
index d495afd..fe973a3 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSample.c
@@ -1893,7 +1893,7 @@ DriverSampleInit (
EFI_STRING NameRequestHdr;
MY_EFI_VARSTORE_DATA *VarStoreConfig;
EFI_INPUT_KEY HotKey;
- EFI_FORM_BROWSER_EXTENSION_PROTOCOL *FormBrowserEx;
+ EDKII_FORM_BROWSER_EXTENSION_PROTOCOL *FormBrowserEx;
#if 1
EFI_STRING Progress;
EFI_STRING Results;
@@ -2190,7 +2190,7 @@ DriverSampleInit (
//
// Example of how to use BrowserEx protocol to register HotKey.
//
- Status = gBS->LocateProtocol (&gEfiFormBrowserExProtocolGuid, NULL, (VOID **) &FormBrowserEx);
+ Status = gBS->LocateProtocol (&gEdkiiFormBrowserExProtocolGuid, NULL, (VOID **) &FormBrowserEx);
if (!EFI_ERROR (Status)) {
//
// First unregister the default hot key F9 and F10.
diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
index cfa049e..75cb6fb 100644
--- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/ConfigKeywordHandler/BlackBoxTest/Dependency/SampleDriver/DriverSampleDxe.inf
@@ -99,7 +99,7 @@
gEfiFormBrowser2ProtocolGuid ## CONSUMES
gEfiHiiDatabaseProtocolGuid ## CONSUMES
gEfiSimpleTextInputExProtocolGuid ## SOMETIMES_CONSUMES
- gEfiFormBrowserExProtocolGuid ## CONSUMES
+ gEdkiiFormBrowserExProtocolGuid ## CONSUMES
gBlackBoxEfiConfigKeywordHandlerProtocolGuid ## CONSUMES

[Depex]
--
2.7.4


[Patch 1/1] [Edk2Platforms] FitGen: Update FitGen tool to be compliance with the FIT specification revision 1.2

Jorge Hernandez Beltran <jorge.hernandez.beltran@...>
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2687

FIT specification revision 1.2 was recently released to the open community.
Revision 1.2 updates CSE Secure Boot Rules in section 4.12, and adds 2 new entry
sub-types used to distinguish the CSE entries.

Signed-off-by: Jorge Hernandez Beltran <jorge.hernandez.beltran@...>
---
Silicon/Intel/Tools/FitGen/FitGen.c | 152 +++++++++++++++++++++++++++---------
Silicon/Intel/Tools/FitGen/FitGen.h | 2 +-
2 files changed, 114 insertions(+), 40 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitGen/FitGen.c
index 75d8932d90ac..c4006e69c822 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -226,6 +226,8 @@ typedef struct {
#define FIT_TABLE_TYPE_BOOT_POLICY_MANIFEST 12
#define FIT_TABLE_TYPE_BIOS_DATA_AREA 13
#define FIT_TABLE_TYPE_CSE_SECURE_BOOT 16
+#define FIT_TABLE_SUBTYPE_FIT_PATCH_MANIFEST 12
+#define FIT_TABLE_SUBTYPE_ACM_MANIFEST 13

//
// With OptionalModule Address isn't known until free space has been
@@ -236,6 +238,7 @@ typedef struct {
//
typedef struct {
UINT32 Type;
+ UINT32 SubType; // Used by OptionalModule only
UINT32 Address;
UINT8 *Buffer; // Used by OptionalModule only
UINT32 Size;
@@ -295,7 +298,7 @@ Returns:
--*/
{
printf (
- "%s - Tiano IA32/X64 FIT table generation Utility for FIT spec revision 1.1."" Version %i.%i\n\n",
+ "%s - Tiano IA32/X64 FIT table generation Utility for FIT spec revision 1.2."" Version %i.%i\n\n",
UTILITY_NAME,
UTILITY_MAJOR_VERSION,
UTILITY_MINOR_VERSION
@@ -334,7 +337,7 @@ Returns:
"\t[-U <DiagnstAcmAddress>|<DiagnstAcmGuid>]\n"
"\t[-B <BiosModuleAddress BiosModuleSize>] [-B ...] [-V <BiosModuleVersion>]\n"
"\t[-M <MicrocodeAddress MicrocodeSize>] [-M ...]|[-U <MicrocodeFv MicrocodeBase>|<MicrocodeRegionOffset MicrocodeRegionSize>|<MicrocodeGuid>] [-V <MicrocodeVersion>]\n"
- "\t[-O RecordType <RecordDataAddress RecordDataSize>|<RESERVE RecordDataSize>|<RecordDataGuid>|<RecordBinFile> [-V <RecordVersion>]] [-O ... [-V ...]]\n"
+ "\t[-O RecordType <RecordDataAddress RecordDataSize>|<RESERVE RecordDataSize>|<RecordDataGuid>|<RecordBinFile>|<CseRecordSubType RecordBinFile> [-V <RecordVersion>]] [-O ... [-V ...]]\n"
"\t[-P RecordType <IndexPort DataPort Width Bit Index> [-V <RecordVersion>]] [-P ... [-V ...]]\n"
, UTILITY_NAME);
printf (" Where:\n");
@@ -366,6 +369,7 @@ Returns:
printf ("\tRecordDataSize - FIT entry record data size.\n");
printf ("\tRecordDataGuid - FIT entry record data GUID.\n");
printf ("\tRecordBinFile - FIT entry record data binary file.\n");
+ printf ("\tCseRecordSubType - FIT entry record subtype. Use to further distinguish CSE entries (see FIT spec revision 1.2 chapter 4.12).\n");
printf ("\tFitEntryDefaultVersion - The default version for all FIT table entries. 0x%04x is used if this is not specified.\n", DEFAULT_FIT_ENTRY_VERSION);
printf ("\tFitHeaderVersion - The version for FIT header. (Override default version)\n");
printf ("\tStartupAcmVersion - The version for StartupAcm. (Override default version)\n");
@@ -857,6 +861,7 @@ Returns:
UINT8 *FileBuffer;
UINT32 FileSize;
UINT32 Type;
+ UINT32 SubType;
UINT8 *MicrocodeFileBuffer;
UINT8 *MicrocodeFileBufferRaw;
UINT32 MicrocodeFileSize;
@@ -1608,26 +1613,22 @@ Returns:
}
Type = xtoi (argv[Index + 1]);
//
- // 1st, try GUID
+ // 1st, try CSE entry sub-type
//
- if (IsGuidData (argv[Index + 2], &Guid)) {
- FileBuffer = FindFileFromFvByGuid (FdBuffer, FdSize, &Guid, &FileSize);
- if (FileBuffer == NULL) {
- Error (NULL, 0, 0, "-O Parameter incorrect, GUID not found!", "%s", argv[Index + 2]);
- // not found
- return 0;
- }
- if (FileSize >= 0x80000000) {
- Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
- return 0;
+ SubType = 0;
+ if (Type == FIT_TABLE_TYPE_CSE_SECURE_BOOT) {
+ if (Index + 3 >= argc) {
+ break;
}
- FileBuffer = (UINT8 *)MEMORY_TO_FLASH (FileBuffer, FdBuffer, FdSize);
- Index += 3;
- } else {
+ SubType = xtoi (argv[Index + 2]);
//
- // 2nd, try file
+ // try file
//
- Status = ReadInputFile (argv[Index + 2], &FileBuffer, &FileSize, NULL);
+ if (SubType != FIT_TABLE_SUBTYPE_FIT_PATCH_MANIFEST && SubType != FIT_TABLE_SUBTYPE_ACM_MANIFEST) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, SubType unsupported!", NULL);
+ return 0;
+ }
+ Status = ReadInputFile (argv[Index + 3], &FileBuffer, &FileSize, NULL);
if (Status == STATUS_SUCCESS) {
if (FileSize >= 0x80000000) {
Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
@@ -1640,48 +1641,90 @@ Returns:
// Assume the file size should < 2G.
//
FileSize |= 0x80000000;
+ Index += 4;
+ } else {
+ if (Status == STATUS_WARNING) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, Unable to open file", argv[Index + 3]);
+ }
+ return 0;
+ }
+ } else {
+ //
+ // 2nd, try GUID
+ //
+ if (IsGuidData (argv[Index + 2], &Guid)) {
+ FileBuffer = FindFileFromFvByGuid (FdBuffer, FdSize, &Guid, &FileSize);
+ if (FileBuffer == NULL) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, GUID not found!", "%s", argv[Index + 2]);
+ // not found
+ return 0;
+ }
+ if (FileSize >= 0x80000000) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
+ return 0;
+ }
+ FileBuffer = (UINT8 *)MEMORY_TO_FLASH (FileBuffer, FdBuffer, FdSize);
Index += 3;
} else {
//
- // 3rd, try <RESERVE, Length>
+ // 3rd, try file
//
- if (Index + 3 >= argc) {
- break;
- }
- if ((strcmp (argv[Index + 2], "RESERVE") == 0) ||
- (strcmp (argv[Index + 2], "reserve") == 0)) {
- FileSize = xtoi (argv[Index + 3]);
+ Status = ReadInputFile (argv[Index + 2], &FileBuffer, &FileSize, NULL);
+ if (Status == STATUS_SUCCESS) {
if (FileSize >= 0x80000000) {
Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
+ free (FileBuffer);
return 0;
}
- FileBuffer = malloc (FileSize);
- if (FileBuffer == NULL) {
- Error (NULL, 0, 0, "No sufficient memory to allocate!", NULL);
- return 0;
- }
- SetMem (FileBuffer, FileSize, 0xFF);
//
// Set the most significant bit
// It means the data in memory, not in flash yet.
// Assume the file size should < 2G.
//
FileSize |= 0x80000000;
- Index += 4;
+ Index += 3;
} else {
//
- // 4th, try <Address, Length>
+ // 4th, try <RESERVE, Length>
//
if (Index + 3 >= argc) {
break;
}
- FileBuffer = (UINT8 *) (UINTN) xtoi (argv[Index + 2]);
- FileSize = xtoi (argv[Index + 3]);
- if (FileSize >= 0x80000000) {
- Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
- return 0;
+ if ((strcmp (argv[Index + 2], "RESERVE") == 0) ||
+ (strcmp (argv[Index + 2], "reserve") == 0)) {
+ FileSize = xtoi (argv[Index + 3]);
+ if (FileSize >= 0x80000000) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
+ return 0;
+ }
+ FileBuffer = malloc (FileSize);
+ if (FileBuffer == NULL) {
+ Error (NULL, 0, 0, "No sufficient memory to allocate!", NULL);
+ return 0;
+ }
+ SetMem (FileBuffer, FileSize, 0xFF);
+ //
+ // Set the most significant bit
+ // It means the data in memory, not in flash yet.
+ // Assume the file size should < 2G.
+ //
+ FileSize |= 0x80000000;
+ Index += 4;
+ } else {
+ //
+ // 5th, try <Address, Length>
+ //
+ if (Index + 3 >= argc) {
+ break;
+ }
+ FileBuffer = (UINT8 *) (UINTN) xtoi (argv[Index + 2]);
+ FileSize = xtoi (argv[Index + 3]);
+ if (FileSize >= 0x80000000) {
+ Error (NULL, 0, 0, "-O Parameter incorrect, FileSize too large!", NULL);
+ return 0;
+ }
+ Index += 4;
}
- Index += 4;
}
}
}
@@ -1691,6 +1734,9 @@ Returns:
return 0;
}
gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].Type = Type;
+ if (gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].Type == FIT_TABLE_TYPE_CSE_SECURE_BOOT) {
+ gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].SubType = SubType;
+ }
gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].Address = (UINT32) (UINTN) FileBuffer;
gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].Buffer = FileBuffer;
gFitTableContext.OptionalModule[gFitTableContext.OptionalModuleNumber].Size = FileSize;
@@ -2055,6 +2101,23 @@ Returns:
return ;
}

+CHAR8 *mFitCseSubTypeStr[] = {
+ "CSE_RSVD ",
+ "CSE_K_HASH1",
+ "CSE_M_HASH ",
+ "CSE_BPOLICY",
+ "CSE_OTHR_BP",
+ "CSE_OEMSMIP",
+ "CSE_MRCDATA",
+ "CSE_IBBL_H ",
+ "CSE_IBB_H ",
+ "CSE_OEM_ID ",
+ "CSEOEMSKUID",
+ "CSE_BD_IND ",
+ "CSE_FPM ",
+ "CSE_ACMM "
+};
+
CHAR8 *mFitTypeStr[] = {
" ",
"MICROCODE ",
@@ -2103,6 +2166,14 @@ Returns:
return mFitSignatureInHeader;
}
if (FitEntry->Type < sizeof (mFitTypeStr)/sizeof(mFitTypeStr[0])) {
+ if (FitEntry->Type == FIT_TABLE_TYPE_CSE_SECURE_BOOT) {
+ //
+ // "Reserved" field is used to distinguish CSE Secure Boot entries (see FIT spec revision 1.2)
+ //
+ if (FitEntry->Rsvd < sizeof (mFitCseSubTypeStr)/sizeof(mFitCseSubTypeStr[0])) {
+ return mFitCseSubTypeStr[FitEntry->Rsvd];
+ }
+ }
return mFitTypeStr[FitEntry->Type];
} else {
return " ";
@@ -2675,6 +2746,9 @@ Returns:
*(UINT32 *)&FitEntry[FitIndex].Size[0] = gFitTableContext.OptionalModule[Index].Size;
FitEntry[FitIndex].Version = (UINT16)gFitTableContext.OptionalModule[Index].Version;
FitEntry[FitIndex].Type = (UINT8)gFitTableContext.OptionalModule[Index].Type;
+ if (FitEntry[FitIndex].Type == FIT_TABLE_TYPE_CSE_SECURE_BOOT) {
+ FitEntry[FitIndex].Rsvd = (UINT8)gFitTableContext.OptionalModule[Index].SubType;
+ }
FitEntry[FitIndex].C_V = 0;
FitEntry[FitIndex].Checksum = 0;
FitIndex++;
diff --git a/Silicon/Intel/Tools/FitGen/FitGen.h b/Silicon/Intel/Tools/FitGen/FitGen.h
index cb9274b4175e..abad2d8799c8 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.h
+++ b/Silicon/Intel/Tools/FitGen/FitGen.h
@@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Utility version information
//
#define UTILITY_MAJOR_VERSION 0
-#define UTILITY_MINOR_VERSION 61
+#define UTILITY_MINOR_VERSION 62
#define UTILITY_DATE __DATE__

//
--
2.16.2.windows.1


Re: [PATCH v2] ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics

Liming Gao
 

Leif:
BZ 2723 is a tiano feature request. This patch adds support for new GCC10. I agree with Laszlo that this change is like the enhancement instead of the critical bug fix. So, I suggest to delay it after this stable tag.

Thanks
Liming

-----Original Message-----
From: Leif Lindholm <leif@...>
Sent: Thursday, May 28, 2020 5:49 PM
To: Gary Lin <glin@...>
Cc: devel@edk2.groups.io; ard.biesheuvel@...; lersek@...; Gao, Liming <liming.gao@...>
Subject: Re: [edk2-devel] [PATCH v2] ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics

On Thu, May 28, 2020 at 09:36:33 +0800, Gary Lin wrote:
On Wed, May 20, 2020 at 01:44:48PM +0200, Ard Biesheuvel wrote:
Gary reports the GCC 10 will emit calls to atomics intrinsics routines
unless -mno-outline-atomics is specified. This means GCC-10 introduces
new intrinsics, and even though it would be possible to work around this
by specifying the command line option, this would require a new GCC10
toolchain profile to be created, which we prefer to avoid.

So instead, add the new intrinsics to our library so they are provided
when necessary.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
After applying this patch, gcc 10 can build ArmVirtPkg without the
linking error.

Tested-by: Gary Lin <glin@...>
Thanks Gary.

Liming, can we consider this patch for stable tag please?

With an added link to
https://bugzilla.tianocore.org/show_bug.cgi?id=2723 in the commit message:
Reviewed-by: Leif Lindholm <leif@...>

/
Leif

---
v2:
- add missing .globl to export the functions from the object file
- add function end markers so the size of each is visible in the ELF metadata
- add some comments to describe what is going on

ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf | 3 +
ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S | 142 ++++++++++++++++++++
2 files changed, 145 insertions(+)

diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
index d5bad9467758..fcf48c678119 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
@@ -79,6 +79,9 @@ [Sources.ARM]
Arm/ldivmod.asm | MSFT
Arm/llsr.asm | MSFT

+[Sources.AARCH64]
+ AArch64/Atomics.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
new file mode 100644
index 000000000000..dc61d6bb8e52
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S
@@ -0,0 +1,142 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2020, Arm, Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ /*
+ * Provide the GCC intrinsics that are required when using GCC 9 or
+ * later with the -moutline-atomics options (which became the default
+ * in GCC 10)
+ */
+ .arch armv8-a
+
+ .macro reg_alias, pfx, sz
+ r0_\sz .req \pfx\()0
+ r1_\sz .req \pfx\()1
+ tmp0_\sz .req \pfx\()16
+ tmp1_\sz .req \pfx\()17
+ .endm
+
+ /*
+ * Define register aliases of the right type for each size
+ * (xN for 8 bytes, wN for everything smaller)
+ */
+ reg_alias w, 1
+ reg_alias w, 2
+ reg_alias w, 4
+ reg_alias x, 8
+
+ .macro fn_start, name:req
+ .section .text.\name
+ .globl \name
+ .type \name, %function
+\name\():
+ .endm
+
+ .macro fn_end, name:req
+ .size \name, . - \name
+ .endm
+
+ /*
+ * Emit an atomic helper for \model with operands of size \sz, using
+ * the operation specified by \insn (which is the LSE name), and which
+ * can be implemented using the generic load-locked/store-conditional
+ * (LL/SC) sequence below, using the arithmetic operation given by
+ * \opc.
+ */
+ .macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a, l
+ fn_start __aarch64_\insn\()\sz\()\model
+ mov tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x1]
+ .ifnc \insn, swp
+ \opc tmp1_\sz, r0_\sz, tmp0_\sz
+ .else
+ \opc tmp1_\sz, tmp0_\sz
+ .endif
+ st\l\()xr\s w15, tmp1_\sz, [x1]
+ cbnz w15, 0b
+ ret
+ fn_end __aarch64_\insn\()\sz\()\model
+ .endm
+
+ /*
+ * Emit atomic helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8}, for the instruction pattern given by
+ * \insn. (This is the LSE name, but this implementation uses
+ * the generic LL/SC sequence using \opc as the arithmetic
+ * operation on the target.)
+ */
+ .macro emit_ld, insn:req, opc:req, model:req, a, l
+ emit_ld_sz 1, \insn, \opc, \model, b, \a, \l
+ emit_ld_sz 2, \insn, \opc, \model, h, \a, \l
+ emit_ld_sz 4, \insn, \opc, \model, , \a, \l
+ emit_ld_sz 8, \insn, \opc, \model, , \a, \l
+ .endm
+
+ /*
+ * Emit the compare and swap helper for \model and size \sz
+ * using LL/SC instructions.
+ */
+ .macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l
+ fn_start __aarch64_cas\sz\()\model
+ \uxt tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x2]
+ cmp r0_\sz, tmp0_\sz
+ bne 1f
+ st\l\()xr\s w15, r1_\sz, [x2]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas\sz\()\model
+ .endm
+
+ /*
+ * Emit compare-and-swap helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8, 16}.
+ */
+ .macro emit_cas, model:req, a, l
+ emit_cas_sz 1, \model, uxtb, b, \a, \l
+ emit_cas_sz 2, \model, uxth, h, \a, \l
+ emit_cas_sz 4, \model, mov , , \a, \l
+ emit_cas_sz 8, \model, mov , , \a, \l
+
+ /*
+ * We cannot use the parameterized sequence for 16 byte CAS, so we
+ * need to define it explicitly.
+ */
+ fn_start __aarch64_cas16\model
+ mov x16, x0
+ mov x17, x1
+0: ld\a\()xp x0, x1, [x4]
+ cmp x0, x16
+ ccmp x1, x17, #0, eq
+ bne 1f
+ st\l\()xp w15, x16, x17, [x4]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas16\model
+ .endm
+
+ /*
+ * Emit the set of GCC outline atomic helper functions for
+ * the memory ordering model given by \model:
+ * - relax unordered loads and stores
+ * - acq load-acquire, unordered store
+ * - rel unordered load, store-release
+ * - acq_rel load-acquire, store-release
+ */
+ .macro emit_model, model:req, a, l
+ emit_ld ldadd, add, \model, \a, \l
+ emit_ld ldclr, bic, \model, \a, \l
+ emit_ld ldeor, eor, \model, \a, \l
+ emit_ld ldset, orr, \model, \a, \l
+ emit_ld swp, mov, \model, \a, \l
+ emit_cas \model, \a, \l
+ .endm
+
+ emit_model _relax
+ emit_model _acq, a
+ emit_model _rel,, l
+ emit_model _acq_rel, a, l
--
2.17.1




Re: [PATCH edk2-platforms v2 8/9] Platform/NXP: Add LX2160ARDB Platform

Leif Lindholm
 

On Wed, May 27, 2020 at 14:21:34 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@...>

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Minor style comment below.

---

Notes:
V2:
- split Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ in two parts
part containing gPlatformGetClockPpi is put before PL011UartClockLib
implementation.

Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 46 ++++++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 168 ++++++++++++++++++++
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 3 +
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 4 +-
Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c | 54 ++++++-
6 files changed, 296 insertions(+), 2 deletions(-)

diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index 000000000000..03996b07fcb9
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+# LX2160aRdbPkg.dec
+# LX2160a board package.
+#
+# Copyright 2018, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LX2160aRdbPkg
+ PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index 000000000000..9b3e0386c13e
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,46 @@
+# LX2160aRdbPkg.dsc
+#
+# LX2160ARDB Board package.
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LX2160aRdbPkg
+ PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
+ OUTPUT_DIRECTORY = Build/LX2160aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+ RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index 000000000000..19d2ca9bbe58
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,168 @@
+# LX2160aRdbPkg.fdf
+#
+# FLASH layout file for LX2160a board.
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LX2160ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x10000
+NumBlocks = 0x14
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00140000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 743836e57141..692ba74ec59e 100644
--- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -19,9 +19,12 @@
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/LX2160A/LX2160A.dec
Please insert alphabetically sorted.


[LibraryClasses]
ArmLib
+ SocLib
DebugLib
Please insert alphabetically sorted.

No further comments on this set for v2.
For the patches I have not commented on:
Reviewed-by: Leif Lindholm <leif@...>

/
Leif


[Sources.common]
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 806cfd180bee..f3f1e5b3f220 100644
--- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -8,6 +8,7 @@

#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>

#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>
@@ -76,6 +77,7 @@ NxpPlatformGetClock(
case NXP_I2C_CLOCK:
case NXP_UART_CLOCK:
Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
break;
default:
break;
@@ -98,7 +100,7 @@ ArmPlatformInitialize (
IN UINTN MpId
)
{
- //TODO: Implement me
+ SocInit ();

return EFI_SUCCESS;
}
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index ad6862dd81eb..391dab265ad7 100644
--- a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -7,7 +7,12 @@
**/

#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6

/**
Return the Virtual Memory Map of your platform
@@ -24,5 +29,52 @@ ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
- ASSERT(0);
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+ return;
+ }
+
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM2_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // FlexSPI
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_FSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_FSPI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_FSPI0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
+
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
}
--
2.17.1


Re: [PATCH edk2-platforms v2 0/9] Add LX2160ARDB Platform

Leif Lindholm
 

On Wed, May 27, 2020 at 14:21:26 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@...>

LX2160A Reference Design Board (RDB) is a high-performance development
platform that supports the QorIQ LX2160A Layerscape Architecture SOCs.

This Platform is based on Layerscape Chassis3V2.

The code structure is same as Chassis2 and LS1043A SOC and LS1043ARDB
platform.

v1 of this series can be referred here:
https://edk2.groups.io/g/devel/message/59923
And what is the change in this set compared to v1?

Yes, I can find out by going through all of the individual patches,
but that defeats a large part of the point of having a cover letter.

/
Leif

Pankaj Bansal (9):
Silicon/NXP: Use Metronome implementation from MdeModulePkg
Platform/NXP: Use Monotonic counter from MdeModulePkg
Silicon/NXP: Use edk2 recommended compilation flags
Platform/NXP/LX2160ARDB: Add ArmPlatformLib
Silicon/NXP: Implement PL011UartClockLib for NXP platforms
Silicon/NXP: Add Chassis3V2 Package
Silicon/NXP: Add LX2160A Soc package
Platform/NXP: Add LX2160ARDB Platform
Platform/NXP/LX2160aRdbPkg: Add VarStore

Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +++
Silicon/NXP/Chassis3V2/Chassis3V2.dec | 22 +++
Silicon/NXP/LX2160A/LX2160A.dec | 13 ++
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 ++
Silicon/NXP/LX2160A/LX2160A.dsc.inc | 50 ++++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 13 +-
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 46 ++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 4 +-
.../LX2160aRdbPkg.fdf} | 33 ++--
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 42 +++++
.../Library/ChassisLib/ChassisLib.inf | 33 ++++
Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf | 27 ++++
.../PL011UartClockLib/PL011UartClockLib.inf | 24 +++
Silicon/NXP/Chassis3V2/Include/Chassis.h | 26 ++++
Silicon/NXP/LX2160A/Include/Soc.h | 38 +++++
.../Library/ArmPlatformLib/ArmPlatformLib.c | 147 ++++++++++++++++++
.../ArmPlatformLib/ArmPlatformLibMem.c | 80 ++++++++++
.../Library/ChassisLib/ChassisLib.c | 71 +++++++++
Silicon/NXP/LX2160A/Library/SocLib/SocLib.c | 80 ++++++++++
.../PL011UartClockLib/PL011UartClockLib.c | 22 +++
.../AArch64/ArmPlatformHelper.S | 45 ++++++
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 91 +++++++++++
22 files changed, 913 insertions(+), 27 deletions(-)
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
create mode 100644 Silicon/NXP/LX2160A/LX2160A.dec
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
create mode 100644 Silicon/NXP/LX2160A/LX2160A.dsc.inc
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
copy Platform/NXP/{LS1043aRdbPkg/LS1043aRdbPkg.fdf => LX2160aRdbPkg/LX2160aRdbPkg.fdf} (88%)
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.inf
create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
create mode 100644 Silicon/NXP/LX2160A/Include/Soc.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/LX2160A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Library/PL011UartClockLib/PL011UartClockLib.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc

--
2.17.1


Re: [PATCH edk2-platforms v2 3/9] Silicon/NXP: Use edk2 recommended compilation flags

Leif Lindholm
 

On Wed, May 27, 2020 at 14:21:29 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@...>

edk2 recommends to use MDEPKG_NDEBUG for release builds and to use
DISABLE_NEW_DEPRECATED_INTERFACES for all new platforms.

Therefore, enable these flags for NXP platforms as well

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Unfortunately, this patch now causes the RELEASE build to fail with

/work/git/edk2-platforms/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c:172:9:
error: ‘mPciHostBridgeLibAcpiAddressSpaceTypeStr’ defined but not used [-Werror=unused-variable]
CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This was caused by 5068692c82b7a
("Silicon/NXP: Implement PciHostBridgeLib support") being merged
between v1 and v2.

So we need another patch that does

--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -167,11 +167,13 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
mEfiPciRootBridgeDevicePath[] = {
}
};

+#ifndef MDEPKG_NDEBUG
STATIC
GLOBAL_REMOVE_IF_UNREFERENCED
CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
};
+#endif

preceding this one.

Best Regards,

Leif

---

Notes:
V2:
- No change

Silicon/NXP/NxpQoriqLs.dsc.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 12e2b89fac58..ee639d552483 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -173,7 +173,12 @@
NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf

[BuildOptions]
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ #
+ # Disable deprecated APIs.
+ #
+ GCC:*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES

[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
--
2.17.1


Cancelled Event: TianoCore Design Meeting - APAC/NAMO - Friday, 29 May 2020 #cal-cancelled

devel@edk2.groups.io Calendar <devel@...>
 

Cancelled: TianoCore Design Meeting - APAC/NAMO

This event has been cancelled.

When:
Friday, 29 May 2020
9:30am to 10:30am
(UTC+08:00) Asia/Chongqing

Where:
https://zoom.us/j/299494771

Organizer: Ray Ni ray.ni@...

Description:

For more info, see here: https://www.tianocore.org/design-meeting/

Join Zoom Meeting

https://zoom.us/j/299494771

Meeting ID: 299 494 771

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+16699009128,,299494771# US (San Jose)

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Meeting ID: 299 494 771

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