Date   

[PATCH edk2-platforms v3 24/24] Platform/NXP/LS1043aRdbPkg: Add PEI Phase

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Add PEI phase to LS1043aRdb. This is needed becuase we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI fimrware.
Using PEI phase we are now also dynamically setting the
PcdSystemMemoryBase and PcdSystemMemorySize depending upon the DRAM
regions detected.
This in turn would depend on the DDR DIMMs installed on board.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- Update commit description

Silicon/NXP/NxpQoriqLs.dsc.inc | 61 +++++++++++++-----
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 ---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 ++++--
Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +-
Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c | 67 +++++++++++---------
5 files changed, 98 insertions(+), 60 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 3c8b11d9e04c..14fbea72d3f8 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,30 +93,35 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf

I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf

+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf

- # 1/123 faster than Stm or Vstm version
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
- # Uncomment to turn on GDB stub in SEC.
- #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf

[LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -125,14 +130,16 @@
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf

[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf

@@ -204,6 +211,9 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480

+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0
+
[PcdsDynamicHii.common.DEFAULT]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10

@@ -224,6 +234,12 @@
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320

+ ## Base of DRAM
+ ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
+ ## for temporary ram
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
@@ -281,13 +297,26 @@
################################################################################
[Components.common]
#
- # SEC
+ # PEI Phase modules
#
- ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+
+ MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }

#
# DXE
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index d486c9b36fab..d45fd67c03b5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -30,15 +30,6 @@
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

[PcdsFixedAtBuild.common]
-
- #
- # LS1043a board Specific PCDs
- # XX (DRAM - Region 1 2GB)
- # (NOR - IFC Region 1 512MB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
-
#
# RTC Pcds
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 99fbc87e1200..931d0bb14f9b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -24,10 +24,10 @@

[FD.LS1043ARDB_EFI]
BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
-Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
-BlockSize = 0x1
-NumBlocks = 0xED000
+BlockSize = 0x40000
+NumBlocks = 0x5

################################################################################
#
@@ -44,7 +44,7 @@ NumBlocks = 0xED000
# RegionType <FV, DATA, or FILE>
#
################################################################################
-0x00000000|0x000ED000
+0x00000000|0x00140000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT

@@ -159,7 +159,15 @@ READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE

- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index ad2371115b17..a33f8cd3f743 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -13,7 +13,8 @@
FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+ LIBRARY_CLASS = MemoryInitPeiLib|PEIM
+ CONSTRUCTOR = MemoryInitPeiLibConstructor

[Sources]
MemoryInitPeiLib.c
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index ea3e7d59532e..932bdf948f6f 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -111,22 +111,17 @@ GetDramRegionsInfo (

/**
Get the installed RAM information.
- Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
+ Initialize Memory HOBs (Resource Descriptor HOBs)
+ Set the PcdSystemMemoryBase and PcdSystemMemorySize.

- @param[in] UefiMemoryBase Base address of region used by UEFI in
- permanent memory
- @param[in] UefiMemorySize Size of the region used by UEFI in permanent memory
-
- @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs.
+ @return EFI_SUCCESS Successfuly retrieved the system memory information
**/
EFI_STATUS
EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+MemoryInitPeiLibConstructor (
+ VOID
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
INT32 Index;
UINTN BaseAddress;
UINTN Size;
@@ -137,18 +132,6 @@ MemoryPeim (
UINTN FdTop;
BOOLEAN FoundSystemMem;

- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- //
- // Ensure MemoryTable[0].Length which is size of DRAM has been set
- // by ArmPlatformGetVirtualMemoryMap ()
- //
- ASSERT (MemoryTable[0].Length != 0);
-
- //
- // Now, the permanent memory has been installed, we can call AllocatePages()
- //
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
@@ -163,8 +146,8 @@ MemoryPeim (

GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions));

- FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
- FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);

// Declare memory regios to system
// The DRAM region info is sorted based on the RAM address is SOC memory map.
@@ -217,8 +200,8 @@ MemoryPeim (
);
};
// Mark the memory covering the Firmware Device as boot services data
- BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
- FixedPcdGet32 (PcdFdSize),
+ BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize),
EfiBootServicesData);
} else {
BuildResourceDescriptorHob (
@@ -236,17 +219,43 @@ MemoryPeim (
Size = DramRegions[Index].Size;

if (FdBase >= BaseAddress && FdTop <= Top) {
- Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ Size -= (UINTN)PcdGet32 (PcdFdSize);
}

- if ((UefiMemoryBase >= BaseAddress) && (Size >= UefiMemorySize)) {
+ if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
FoundSystemMem = TRUE;
+ PcdSet64S (PcdSystemMemoryBase, BaseAddress);
+ PcdSet64S (PcdSystemMemorySize, Size);
}
}

ASSERT (FoundSystemMem == TRUE);

- // Build Memory Allocation Hob
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize MMU
+
+ @param[in] UefiMemoryBase Base address of region used by UEFI in
+ permanent memory
+ @param[in] UefiMemorySize Size of the region used by UEFI in permanent memory
+
+ @return EFI_SUCCESS Successfuly Initialize MMU
+**/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ // Initialize Mmu
InitMmu (MemoryTable);

if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
--
2.17.1


[PATCH edk2-platforms v3 23/24] Silicon/NXP: move MemoryInitPeiLib as per PEIM structures

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

MemoryInitPeiLib would be linked to MemoryInitPeim, when we implement
PEI phase. therefore, move the library to directory of same name.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Silicon/NXP/NxpQoriqLs.dsc.inc | 4 ++--
Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf | 0
Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h | 0
Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c | 0
4 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 8fbd6288cfae..3c8b11d9e04c 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -98,6 +98,8 @@
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf

+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
@@ -109,7 +111,6 @@
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf

# 1/123 faster than Stm or Vstm version
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -139,7 +140,6 @@
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf

[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
similarity index 100%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
--
2.17.1


[PATCH edk2-platforms v3 22/24] Platform/NXP/LS1043aRdbPkg: Add VarStore

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Add VarStore Fd. This Fd is used to store non volatile variables in
flash.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 3 +-
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++++++++++++
2 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 8d66f36d7407..99fbc87e1200 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -3,7 +3,7 @@
# FLASH layout file for LS1043a board.
#
# Copyright (c) 2016, Freescale Ltd. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -49,6 +49,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT

!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 000000000000..391e4ae5eaf8
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1043aRdbNv_EFI]
+BaseAddress = 0x60500000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x40000
+NumBlocks = 0x3
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
2.17.1


[PATCH edk2-platforms v3 21/24] Platform/NXP: Use FV rules from ArmVirtPkg

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

FVRules.fdf.inc is being replaced by the ArmVirtPkg/ArmVirtRules.fdf.inc
at commit hash 746c5b6238f1ee55deb4b3ec32a6d732e27eeeaa

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- Modify commit description

Platform/NXP/FVRules.fdf.inc | 59 +++++++++++++-------
1 file changed, 38 insertions(+), 21 deletions(-)

diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
index c9fba65dae85..63de26abe056 100644
--- a/Platform/NXP/FVRules.fdf.inc
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -1,8 +1,7 @@
-# FvRules.fdf.inc
#
-# Rules for creating FD.
-#
-# Copyright 2017-2019 NXP
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,40 +15,49 @@
#
################################################################################

+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
}

[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}

[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
+ FILE PEIM = $(NAMED_GUID) FIXED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}

-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
- }
-
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}

-
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -62,6 +70,8 @@
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
}

[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -73,7 +83,7 @@

[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}

@@ -91,3 +101,10 @@
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ }
--
2.17.1


[PATCH edk2-platforms v3 20/24] NXP: LS1043aRdbPkg: Use ArmPlatformHelper.S from ArmPlatformPkg

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

ArmPlatformHelper.S is being replaced by the ArmPlatformPkg version at
commit hash f4dfad05dda2c7b29e8105605621f2b413f0af2b.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- Modify commit description

Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 2 +
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 8 ---
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S | 60 ++++++++++++--------
3 files changed, 39 insertions(+), 31 deletions(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 07ca6b34445f..1faf99b99c54 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -37,3 +37,5 @@

[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index a554d1377484..dc81e7ba3101 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -137,11 +137,3 @@ ArmPlatformGetPlatformPpiList (
*PpiList = gPlatformPpiTable;
}

-
-UINTN
-ArmPlatformGetCorePosition (
- IN UINTN MpId
- )
-{
- return 1;
-}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index dfbf73675a2d..b7c6dbdc2e61 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,31 +1,45 @@
-# @file
-#
-# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017, 2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//

#include <AsmMacroIoLibV8.h>
-#include <AutoGen.h>
-
-.text
-.align 2
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-ASM_FUNC(ArmPlatformIsPrimaryCore)
- tst x0, #3
- cset x0, eq
- ret
+#include <Library/ArmLib.h>

ASM_FUNC(ArmPlatformPeiBootAction)
-EL1_OR_EL2(x0)
-1:
-2:
ret

+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
- ldrh w0, [x0]
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
ret
--
2.17.1


[PATCH edk2-platforms v3 19/24] NXP/LS1043aRdbPkg/ArmPlatformLib: Remove extern SocInit

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

SocInit can be defined in SocLib.h
No need to make it extern in ArmPlatformLib

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- Moved commit three commits before in series

Silicon/NXP/Include/Library/SocLib.h | 8 ++++++++
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 2 --
2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
index 749aa230dec5..0ca68602618d 100644
--- a/Silicon/NXP/Include/Library/SocLib.h
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -41,4 +41,12 @@ SocGetClock (
IN VA_LIST Args
);

+/**
+ Function to initialize SoC specific constructs
+ **/
+VOID
+SocInit (
+ VOID
+ );
+
#endif // SOC_LIB_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 7f5872a78cfc..a554d1377484 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -16,8 +16,6 @@
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>

-extern VOID SocInit (VOID);
-
/**
Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs

--
2.17.1


[PATCH edk2-platforms v3 18/24] Silicon/NXP/LS1043A: Move SocLib to Soc Package

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The SocLib contains code specific to an Soc. it should be part of
SOC package.
Therefore, move the SocLib to Soc Package.
Since we are moving the files to Soc Package, no need to mention the
Soc name in file names. Their location is enough to indicate for which
Soc the files are.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
Silicon/NXP/{Library/SocLib/LS1043aSocLib.inf => LS1043A/Library/SocLib/SocLib.inf} | 2 +-
Silicon/NXP/{Library/SocLib/Chassis2/Soc.c => LS1043A/Library/SocLib/SocLib.c} | 0
3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index ea0854f967a3..67f5ba68dcd5 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -10,7 +10,7 @@
!include Silicon/NXP/Chassis2/Chassis2.dsc.inc

[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf

################################################################################
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
similarity index 92%
rename from Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
index 1d042bbfc4e4..3d0f988e1c67 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf
@@ -24,4 +24,4 @@
DebugLib

[Sources.common]
- Chassis2/Soc.c
+ SocLib.c
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
similarity index 100%
rename from Silicon/NXP/Library/SocLib/Chassis2/Soc.c
rename to Silicon/NXP/LS1043A/Library/SocLib/SocLib.c
--
2.17.1


[PATCH edk2-platforms v3 17/24] Silicon/NXP/LS1043A: Use ChassisLib from Chassis2 Pkg

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Now the we have added Chassis Package, move the chassis specific common
code for all SOCs belonging to same chassis to ChassisLib.

Use ChassisLib APIs in SocLib.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Silicon/NXP/NxpQoriqLs.dec | 6 --
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 9 ++-
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 +
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 1 +
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 15 +----
Silicon/NXP/Include/Chassis2/NxpSoc.h | 44 --------------
Silicon/NXP/LS1043A/Include/Soc.h | 6 +-
Silicon/NXP/Library/SocLib/NxpChassis.h | 22 -------
Silicon/NXP/Library/SocLib/Chassis.c | 61 --------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 19 +-----
10 files changed, 14 insertions(+), 170 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3e79f502c127..71e43c1ffd86 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -24,12 +24,6 @@
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

-[PcdsFixedAtBuild.common]
- #
- # Pcds to support Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
-
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 7690e4caa593..ea0854f967a3 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -7,6 +7,8 @@
#
#

+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+
[LibraryClasses.common]
SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -26,9 +28,6 @@
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500

- #
- # Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
-
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
##
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 038d48949a39..e522db81e5c0 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -24,6 +24,7 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7a43ad86d183..07ca6b34445f 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -19,6 +19,7 @@
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index bb15e0a3d710..1d042bbfc4e4 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -14,25 +14,14 @@
LIBRARY_CLASS = SocLib

[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
- BaseLib
+ ChassisLib
DebugLib
- IoAccessLib
- SerialPortLib

[Sources.common]
- Chassis.c
Chassis2/Soc.c
-
-[BuildOptions]
- GCC:*_*_*_CC_FLAGS = -DCHASSIS2
-
-[FixedPcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
deleted file mode 100644
index 3f00a2614131..000000000000
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** Soc.h
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_SOC_H_
-#define NXP_SOC_H_
-
-#define CLK_FREQ 100000000
-
-#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
-
-/* SMMU Defintions */
-#define SMMU_BASE_ADDR 0x09000000
-#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
-#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
-#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
-#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
-#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
-
-#define SCR0_USFCFG_MASK 0x00000400
-#define SCR0_CLIENTPD_MASK 0x00000001
-#define SACR_PAGESIZE_MASK 0x00010000
-#define IDR1_PAGESIZE_MASK 0x80000000
-
-/* Device Configuration and Pin Control */
-typedef struct {
- UINT8 Res0[0x100-0x00];
- UINT32 RcwSr[16]; /* Reset control word status */
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-} CCSR_GUR;
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- );
-
-#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index e62de570da8a..97a77d3f5da6 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -8,7 +8,7 @@
#ifndef SOC_H__
#define SOC_H__

-#include <Chassis2/NxpSoc.h>
+#include <Chassis.h>

/**
Soc Memory Map
@@ -43,13 +43,13 @@
#define LS1043A_I2C_SIZE 0x10000
#define LS1043A_I2C_NUM_CONTROLLERS 4

-#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
+#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS

/**
Reset Control Word (RCW) Bits
**/
#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6

-typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;

#endif // SOC_H__
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
deleted file mode 100644
index 836df103f80f..000000000000
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/** @file
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_CHASSIS_H_
-#define NXP_CHASSIS_H_
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- );
-
-#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
deleted file mode 100644
index d7bc55c9d275..000000000000
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/** @file
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#ifdef CHASSIS2
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/ArmSmcLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "NxpChassis.h"
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- )
-{
- MMIO_OPERATIONS_32 *GurOps;
-
- GurOps = GetMmioOperations32 (FixedPcdGetBool (PcdGurBigEndian));
-
- return GurOps->Read32 (Address);
-}
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- )
-{
- UINT32 Value;
-
- /* set pagesize as 64K and ssmu-500 in bypass mode */
- Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
- MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
-}
-
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index b14ada7f595d..a50c072e84d5 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -8,16 +8,8 @@
**/

#include <Base.h>
-#include <NxpChassis.h>
-#include <Chassis2/NxpSoc.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
+#include <Library/ChassisLib.h>
#include <Library/DebugLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
#include <Library/SocLib.h>
#include <Soc.h>

@@ -61,7 +53,7 @@ SocGetClock (
switch (ClockType) {
case NXP_UART_CLOCK:
case NXP_I2C_CLOCK:
- RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
break;
default:
@@ -79,12 +71,7 @@ SocInit (
VOID
)
{
- SmmuInit ();
-
- //
- // Early init serial Port to get board information.
- //
- SerialPortInitialize ();
+ ChassisInit ();

return;
}
--
2.17.1


[PATCH edk2-platforms v3 16/24] Silicon/NXP: Add Chassis2 Package

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

A Chassis is a base framework used for building SoCs.
We can think of Chassis/Soc/Platform(a.k.a Borad) in Object model terms.
Chassis is base. Soc is based on some Chassis.
Platform is based on some Soc.

SOCs that are designed around same chassis, reuse most of the components.

Therefore, add the package for Chassis2. LS1043A and LS1046A SOCs belong
to Chassis2.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- in patch description Oops -> Object model
- Sorted includes alphabetically
- removed direct calls to SwapMmio** APIs and used GetMmioOperations**

Silicon/NXP/Chassis2/Chassis2.dec | 23 +++++
Silicon/NXP/NxpQoriqLs.dec | 4 +
Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 ++
Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 34 +++++++
Silicon/NXP/Chassis2/Include/Chassis.h | 34 +++++++
Silicon/NXP/Include/Library/ChassisLib.h | 51 ++++++++++
Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 97 ++++++++++++++++++++
7 files changed, 253 insertions(+)

diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
new file mode 100644
index 000000000000..a0048bd784ea
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dec
@@ -0,0 +1,23 @@
+# @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 2ac047a89274..3e79f502c127 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
Include

[LibraryClasses]
+ ## @libraryclass Provides Chassis specific functions to other modules
+ ChassisLib|Include/Library/ChassisLib.h
+
## @libraryclass Provides services to read/write to I2c devices
I2cLib|Include/Library/I2cLib.h

@@ -29,4 +32,5 @@

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316

diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
new file mode 100644
index 000000000000..db8e5a92eacb
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 000000000000..2bb16af53134
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,34 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = Chassis2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ IoAccessLib
+ IoLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
new file mode 100644
index 000000000000..72bd97efd004
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -0,0 +1,34 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef CHASSIS_H__
+#define CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+
+/**
+ The Device Configuration Unit provides general purpose configuration and
+ status for the device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[16]; // Reset Control Word Status Register
+} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif // CHASSIS_H__
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
new file mode 100644
index 000000000000..89992a4b6fd5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -0,0 +1,51 @@
+/** @file
+ Chassis Lib to provide Chessis specific functionality to all SOCs in
+ a Chassis.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef CHASSIS_LIB_H__
+#define CHASSIS_LIB_H__
+
+#include <Chassis.h>
+
+/**
+ Read Dcfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Dcfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ );
+
+#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 000000000000..b3bb25029dd2
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,97 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Read Dcfg register
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ MMIO_OPERATIONS_32 *DcfgOps;
+
+ DcfgOps = GetMmioOperations32 (FeaturePcdGet (PcdDcfgBigEndian));
+
+ return DcfgOps->Read32 (Address);
+}
+
+/**
+ Write Dcfg register
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+ @return Value.
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ MMIO_OPERATIONS_32 *DcfgOps;
+
+ DcfgOps = GetMmioOperations32 (FeaturePcdGet (PcdDcfgBigEndian));
+
+ return DcfgOps->Write32 (Address, Value);
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+STATIC
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK);
+ Value &= ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK);
+ Value &= ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+
+ SmmuInit ();
+}
--
2.17.1


[PATCH edk2-platforms v3 15/24] Silicon: NXP: Remove direct calls to SwapMmio* APIs

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The SwapMmio** APIs are supposed to be called indirectly via
GetMmioOperations** APIs.
Therefore, remove the SwapMmio** APIs from IoAccessLib.h and make
these APIs STATIC to IoAccessLib.c, so that no accidental call can
be made to these.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- New commit

Silicon/NXP/Include/Library/IoAccessLib.h | 236 +-------------------
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 17 +-
Silicon/NXP/Library/SocLib/Chassis.c | 10 +-
3 files changed, 22 insertions(+), 241 deletions(-)

diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
index 0b708d544fa7..7b490744382c 100644
--- a/Silicon/NXP/Include/Library/IoAccessLib.h
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -1,6 +1,6 @@
/** @file
*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -89,238 +89,4 @@ GetMmioOperations64 (
IN BOOLEAN Swap
);

-/**
- MmioRead16 for Big-Endian modules.
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-SwapMmioRead16 (
- IN UINTN Address
- );
-
-/**
- MmioRead32 for Big-Endian modules.
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-SwapMmioRead32 (
- IN UINTN Address
- );
-
-/**
- MmioRead64 for Big-Endian modules.
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-SwapMmioRead64 (
- IN UINTN Address
- );
-
-/**
- MmioWrite16 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- );
-
-/**
- MmioWrite32 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- );
-
-/**
- MmioWrite64 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
- );
-
-/**
- MmioAndThenOr16 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- );
-
-/**
- MmioAndThenOr32 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- );
-
-/**
- MmioAndThenOr64 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioAndThenOr64 (
- IN UINTN Address,
- IN UINT64 AndData,
- IN UINT64 OrData
- );
-
-/**
- MmioOr16 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioOr16 (
- IN UINTN Address,
- IN UINT16 OrData
- );
-
-/**
- MmioOr32 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- );
-
-/**
- MmioOr64 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioOr64 (
- IN UINTN Address,
- IN UINT64 OrData
- );
-
-/**
- MmioAnd16 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-SwapMmioAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
- );
-
-/**
- MmioAnd32 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-SwapMmioAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
- );
-
-/**
- MmioAnd64 for Big-Endian modules.
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the read value from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-SwapMmioAnd64 (
- IN UINTN Address,
- IN UINT64 AndData
- );
-
#endif /* IO_ACCESS_LIB_H_ */
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
index 6ed83d019a6e..bb4a93b6f09a 100644
--- a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
@@ -2,7 +2,7 @@

Provide MMIO APIs for BE modules.

- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -21,6 +21,7 @@
@return The value read.

**/
+STATIC
UINT16
EFIAPI
SwapMmioRead16 (
@@ -38,6 +39,7 @@ SwapMmioRead16 (
@return The value read.

**/
+STATIC
UINT32
EFIAPI
SwapMmioRead32 (
@@ -55,6 +57,7 @@ SwapMmioRead32 (
@return The value read.

**/
+STATIC
UINT64
EFIAPI
SwapMmioRead64 (
@@ -71,6 +74,7 @@ SwapMmioRead64 (
@param Value The value to write to the MMIO register.

**/
+STATIC
UINT16
EFIAPI
SwapMmioWrite16 (
@@ -88,6 +92,7 @@ SwapMmioWrite16 (
@param Value The value to write to the MMIO register.

**/
+STATIC
UINT32
EFIAPI
SwapMmioWrite32 (
@@ -105,6 +110,7 @@ SwapMmioWrite32 (
@param Value The value to write to the MMIO register.

**/
+STATIC
UINT64
EFIAPI
SwapMmioWrite64 (
@@ -125,6 +131,7 @@ SwapMmioWrite64 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT16
EFIAPI
SwapMmioAndThenOr16 (
@@ -149,6 +156,7 @@ SwapMmioAndThenOr16 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT32
EFIAPI
SwapMmioAndThenOr32 (
@@ -173,6 +181,7 @@ SwapMmioAndThenOr32 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT64
EFIAPI
SwapMmioAndThenOr64 (
@@ -196,6 +205,7 @@ SwapMmioAndThenOr64 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT16
EFIAPI
SwapMmioOr16 (
@@ -215,6 +225,7 @@ SwapMmioOr16 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT32
EFIAPI
SwapMmioOr32 (
@@ -234,6 +245,7 @@ SwapMmioOr32 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT64
EFIAPI
SwapMmioOr64 (
@@ -253,6 +265,7 @@ SwapMmioOr64 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT16
EFIAPI
SwapMmioAnd16 (
@@ -272,6 +285,7 @@ SwapMmioAnd16 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT32
EFIAPI
SwapMmioAnd32 (
@@ -291,6 +305,7 @@ SwapMmioAnd32 (
@return The value written back to the MMIO register.

**/
+STATIC
UINT64
EFIAPI
SwapMmioAnd64 (
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 90677f0f36ca..d7bc55c9d275 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -30,11 +30,11 @@ GurRead (
IN UINTN Address
)
{
- if (FixedPcdGetBool (PcdGurBigEndian)) {
- return SwapMmioRead32 (Address);
- } else {
- return MmioRead32 (Address);
- }
+ MMIO_OPERATIONS_32 *GurOps;
+
+ GurOps = GetMmioOperations32 (FixedPcdGetBool (PcdGurBigEndian));
+
+ return GurOps->Read32 (Address);
}

/*
--
2.17.1


[PATCH edk2-platforms v3 14/24] Silicon/NXP: Use Clock retrieval PPI in modules

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- Added clock retrieval APIs to DUartPortLib

Silicon/NXP/NxpQoriqLs.dec | 5 ----
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 --
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 2 +-
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 5 ++--
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 6 ----
Silicon/NXP/Include/Chassis2/NxpSoc.h | 9 ------
Silicon/NXP/Library/DUartPortLib/DUart.h | 8 +----
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 3 +-
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 7 ++---
Silicon/NXP/Library/SocLib/Chassis.c | 15 ----------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 --------------------
12 files changed, 9 insertions(+), 85 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b478560450b3..2ac047a89274 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,11 +22,6 @@
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

[PcdsFixedAtBuild.common]
- #
- # Platform PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
-
#
# Pcds to support Big Endian IPs
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index e5383aaf0cc5..d486c9b36fab 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,8 +39,6 @@
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000

- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
#
# RTC Pcds
#
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 867376044656..3bf7a8124fc6 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -25,13 +25,13 @@

[LibraryClasses]
ArmLib
+ ArmPlatformLib
BaseMemoryLib
DevicePathLib
I2cLib
IoLib
MemoryAllocationLib
PcdLib
- SocLib
TimerLib
UefiBootServicesTableLib
UefiDriverEntryPoint
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
index 7a2fa619b027..b8a77ae05243 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -3,7 +3,7 @@
# Component description file for DUartPortLib module
#
# Copyright (c) 2013, Freescale Ltd. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,8 +20,8 @@
DUartPortLib.c

[LibraryClasses]
+ ArmPlatformLib
PcdLib
- SocLib

[Packages]
MdeModulePkg/MdeModulePkg.dec
@@ -31,4 +31,3 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3d38a7e58b91..bb15e0a3d710 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,4 +36,3 @@
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f313380..7c4a306c16a0 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -37,12 +37,6 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
EFI_STATUS
NxpI2cInit (
IN EFI_HANDLE DriverBindingHandle,
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 6812beafe447..3f00a2614131 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -27,10 +27,6 @@
#define SACR_PAGESIZE_MASK 0x00010000
#define IDR1_PAGESIZE_MASK 0x80000000

-typedef struct {
- UINTN FreqSystemBus;
-} SYS_INFO;
-
/* Device Configuration and Pin Control */
typedef struct {
UINT8 Res0[0x100-0x00];
@@ -39,11 +35,6 @@ typedef struct {
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
} CCSR_GUR;

-VOID
-GetSysInfo (
- OUT SYS_INFO *
- );
-
UINT32
EFIAPI
GurRead (
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
index c71e2ce55d1d..aca7cd8d3f01 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUart.h
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -5,7 +5,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -113,10 +113,4 @@
#define USCR 0x7
#define UDSR 0x10

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
#endif /* DUART_H_ */
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index a5aba47b3ed4..30804450d2b7 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -17,6 +17,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h>
+#include <Ppi/NxpPlatformGetClock.h>

#include "I2cDxe.h"

@@ -51,7 +52,7 @@ SetBusFrequency (

I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);

- I2cClock = GetBusFrequency ();
+ I2cClock = gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);

I2cInitialize (I2cBase, I2cClock, *BusClockHertz);

diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
index c3c738d3cca8..f9c2c44a4c3b 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -6,7 +6,7 @@
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
- Copyright 2017 NXP
+ Copyright 2017, 2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -16,6 +16,7 @@
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
+#include <Ppi/NxpPlatformGetClock.h>

#include "DUart.h"

@@ -169,10 +170,8 @@ CalculateBaudDivisor (
)
{
UINTN DUartClk;
- UINTN FreqSystemBus;

- FreqSystemBus = GetBusFrequency ();
- DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+ DUartClk = gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);

return ((DUartClk)/(BaudRate * 16));
}
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 1ef99e8de25f..90677f0f36ca 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -37,21 +37,6 @@ GurRead (
}
}

-/*
- * Return system bus frequency
- */
-UINT64
-GetBusFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSystemBus;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 480d8d18fb9f..b14ada7f595d 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -21,37 +21,6 @@
#include <Library/SocLib.h>
#include <Soc.h>

-/**
- Calculate the frequency of various controllers and
- populate the passed structure with frequuencies.
-
- @param PtrSysInfo Input structure to populate with
- frequencies.
-**/
-VOID
-GetSysInfo (
- OUT SYS_INFO *PtrSysInfo
- )
-{
- CCSR_GUR *GurBase;
- UINTN SysClk;
-
- GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
- SysClk = CLK_FREQ;
-
- SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
-
- PtrSysInfo->FreqSystemBus = SysClk;
-
- //
- // selects the platform clock:SYSCLK ratio and calculate
- // system frequency
- //
- PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-}
-
/**
Return the input clock frequency to an IP Module.
This function reads the RCW bits and calculates the PLL multipler/divider
--
2.17.1


[PATCH edk2-platforms v3 13/24] Platform/NXP/LS1043aRdbPkg: Add Clock retrieval APIs

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The SOC takes primary clocking input from the external signal (a clock
generator on board). The input (frequency) is multiplied using multiple
phase locked loops (PLL) to create a variety of frequencies which can
then be passed to a variety of internal logic, including cores and
peripheral IP modules.

Therefore, move the clock retrieval APIs to Platform Lib.
The Input clock is retrieved from board components in Platform Lib, and
passed on to SOC Lib APIs to get the correct clock for an IP (after PLL
multiplication).

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- sorted NXP_IP_CLOCK enum alphabetically

Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 +
Silicon/NXP/Include/Library/SocLib.h | 44 ++++++++++++++++
Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 53 ++++++++++++++++++++
Silicon/NXP/LS1043A/Include/Soc.h | 11 ++++
Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 51 +++++++++++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 52 +++++++++++++++++++
6 files changed, 212 insertions(+)

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 99d89498e0e2..3d38a7e58b91 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -17,6 +17,7 @@
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
new file mode 100644
index 000000000000..749aa230dec5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_LIB_H__
+#define SOC_LIB_H__
+
+#include <Uefi.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ );
+
+#endif // SOC_LIB_H__
diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
new file mode 100644
index 000000000000..bc086bc5b337
--- /dev/null
+++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
@@ -0,0 +1,53 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_PLATFORM_PPI_H__
+#define NXP_PLATFORM_PPI_H__
+
+#include <Uefi.h>
+
+typedef enum _NXP_IP_CLOCK {
+ NXP_CORE_CLOCK,
+ NXP_I2C_CLOCK,
+ NXP_SYSTEM_CLOCK,
+ NXP_UART_CLOCK
+} NXP_IP_CLOCK;
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+typedef
+UINT64
+(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
+ IN NXP_IP_CLOCK ClockType,
+ ...
+ );
+
+typedef struct {
+ NXP_PLATFORM_GET_CLOCK PlatformGetClock;
+} NXP_PLATFORM_GET_CLOCK_PPI;
+
+extern NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi;
+
+#endif // NXP_PLATFORM_PPI_H__
+
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
index 441871757d67..e62de570da8a 100644
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -8,6 +8,8 @@
#ifndef SOC_H__
#define SOC_H__

+#include <Chassis2/NxpSoc.h>
+
/**
Soc Memory Map
**/
@@ -41,4 +43,13 @@
#define LS1043A_I2C_SIZE 0x10000
#define LS1043A_I2C_NUM_CONTROLLERS 4

+#define LS1043A_DCFG_ADDRESS CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef CCSR_GUR LS1043A_DEVICE_CONFIG;
+
#endif // SOC_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 718c71bf02eb..7f5872a78cfc 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -12,10 +12,60 @@
**/

#include <Library/ArmPlatformLib.h>
+#include <Library/SocLib.h>
#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>

extern VOID SocInit (VOID);

+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC IPs
+
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] ... Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number.
+ if ClockType is NXP_CORE_CLOCK, then second argument
+ is interpreted as cluster number and third argument is
+ interpreted as core number (within the cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
/**
Return the current Boot Mode

@@ -69,6 +119,7 @@ PrePeiCoreGetMpCoreInfo (
}

ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI gPlatformGetClockPpi = { NxpPlatformGetClock };

EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 98ca2e162f7b..480d8d18fb9f 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -18,6 +18,8 @@
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
+#include <Library/SocLib.h>
+#include <Soc.h>

/**
Calculate the frequency of various controllers and
@@ -50,6 +52,56 @@ GetSysInfo (
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
}

+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider
+ values to be applied to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is
+ to be applied.
+ @param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
+ is to be retrieved.
+ @param[in] Args Variable argument list which is parsed based on
+ ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
+ the second argument will be interpreted as controller
+ number. e.g. if there are four i2c controllers in SOC,
+ then this value can be 0, 1, 2, 3
+ e.g. if ClockType is NXP_CORE_CLOCK, then second
+ argument is interpreted as cluster number and third
+ argument is interpreted as core number (within the
+ cluster)
+
+ @return Actual Clock Frequency. Return value 0 should be
+ interpreted as clock not being provided to IP.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN NXP_IP_CLOCK ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1043A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = GurRead ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
/**
Function to initialize SoC specific constructs
**/
--
2.17.1


[PATCH edk2-platforms v3 12/24] Silicon/NXP: Move RAM retrieval from SocLib

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to commom MemoryInit Pei Lib.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- sort headers alphabetically
- Moved DRAM region retrieval and Total DRAM size retrieval to separate
functions
- Fixed MemoryPeim function description
- Modified check on FoundSystemMem = TRUE to check the RAM region against
MemoryPeim function input arguments UefiMemoryBase and UefiMemorySize
- (!DramRegions[Index].Size) => (DramRegions[Index].Size == 0)
- (FoundSystemMem) => (FoundSystemMem == TRUE)
- Added explaination for starting for loop from the last DRAM region

Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 7 +-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Include/DramInfo.h | 38 ----
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h | 25 +++
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 196 ++++++++++++++++----
Silicon/NXP/Library/SocLib/Chassis.c | 67 -------
6 files changed, 188 insertions(+), 146 deletions(-)

diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415def..ad2371115b17 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -18,7 +18,6 @@
[Sources]
MemoryInitPeiLib.c

-
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
@@ -30,6 +29,7 @@
[LibraryClasses]
ArmMmuLib
ArmPlatformLib
+ ArmSmcLib
DebugLib
HobLib
PcdLib
@@ -40,6 +40,11 @@
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob

+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index b7c7fc78cc8f..99d89498e0e2 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -20,7 +20,6 @@
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
- ArmSmcLib
BaseLib
DebugLib
IoAccessLib
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1f5..000000000000
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-* Header defining the structure for Dram Information
-*
-* Copyright 2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SMC_DRAM_BANK_INFO (0xC200FF12)
-
-typedef struct {
- UINTN BaseAddress;
- UINTN Size;
-} DRAM_REGION_INFO;
-
-typedef struct {
- UINT32 NumOfDrams;
- UINT32 Reserved;
- DRAM_REGION_INFO DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- );
-
-VOID
-UpdateDpaaDram (
- IN OUT DRAM_INFO *DramInfo
- );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index 000000000000..edbf0ceaf638
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,25 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef MEMORY_INIT_PEI_LIB_H_
+#define MEMORY_INIT_PEI_LIB_H_
+
+#include <Uefi.h>
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in
+// a Platform
+#define MAX_DRAM_REGIONS 3
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+#endif // MEMORY_INIT_PEI_LIB_H_
+
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
index 3ea773678667..ea3e7d59532e 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -12,13 +12,15 @@

#include <Library/ArmMmuLib.h>
#include <Library/ArmPlatformLib.h>
+#include <Library/ArmSmcLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>

-#include <DramInfo.h>
+#include "MemoryInitPeiLib.h"
+

VOID
BuildMemoryTypeInformationHob (
@@ -44,22 +46,79 @@ InitMmu (
}
}

-/*++
+STATIC
+UINTN
+GetDramSize (
+ IN VOID
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;

-Routine Description:
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = -1;

+ ArmCallSmc (&ArmSmcArgs);

+ if (ArmSmcArgs.Arg0) {
+ return 0;
+ } else {
+ return ArmSmcArgs.Arg1;
+ }
+}

-Arguments:
+STATIC
+EFI_STATUS
+GetDramRegionsInfo (
+ OUT DRAM_REGION_INFO *DramRegions,
+ IN UINT32 NumRegions
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+ UINT32 Index;
+ UINTN RemainingDramSize;
+ UINTN BaseAddress;
+ UINTN Size;

- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
+ RemainingDramSize = GetDramSize ();
+ DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", RemainingDramSize));

-Returns:
+ // Ensure Total Dram Size is valid
+ ASSERT (RemainingDramSize != 0);

- Status - EFI_SUCCESS if the boot mode could be set
+ for (Index = 0; (RemainingDramSize != 0) && (Index < NumRegions); Index++) {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = Index;

---*/
+ ArmCallSmc (&ArmSmcArgs);
+
+ BaseAddress = ArmSmcArgs.Arg1;
+ Size = ArmSmcArgs.Arg2;
+ ASSERT (BaseAddress && Size);
+
+ DramRegions[Index].BaseAddress = BaseAddress;
+ DramRegions[Index].Size = Size;
+ RemainingDramSize -= Size;
+
+ DEBUG ((DEBUG_INFO, "DRAM Region[%d]: start 0x%lx, size 0x%lx\n",
+ Index, BaseAddress, Size));
+ }
+
+ // Ensure that all regions have been accounted for
+ ASSERT (RemainingDramSize == 0);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the installed RAM information.
+ Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
+
+ @param[in] UefiMemoryBase Base address of region used by UEFI in
+ permanent memory
+ @param[in] UefiMemorySize Size of the region used by UEFI in permanent memory
+
+ @return EFI_SUCCESS Successfuly Initialize MMU and Memory HOBs.
+**/
EFI_STATUS
EFIAPI
MemoryPeim (
@@ -67,11 +126,16 @@ MemoryPeim (
IN UINT64 UefiMemorySize
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- EFI_PEI_HOB_POINTERS NextHob;
- BOOLEAN Found;
- DRAM_INFO DramInfo;
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ INT32 Index;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS];
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;

// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@@ -94,40 +158,94 @@ MemoryPeim (
EFI_RESOURCE_ATTRIBUTE_TESTED
);

- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return EFI_UNSUPPORTED;
- }
+ FoundSystemMem = FALSE;
+ ZeroMem (DramRegions, sizeof (DramRegions));

- while (DramInfo.NumOfDrams--) {
- //
- // Check if the resource for the main system memory has been declared
- //
- Found = FALSE;
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
- if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
- (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
- (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
- {
- Found = TRUE;
- break;
+ GetDramRegionsInfo (DramRegions, ARRAY_SIZE (DramRegions));
+
+ FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+
+ // Declare memory regios to system
+ // The DRAM region info is sorted based on the RAM address is SOC memory map.
+ // i.e. DramRegions[0] is at lower address, as compared to DramRegions[1].
+ // The goal to start from last region is to find the topmost RAM region that
+ // can contain UEFI DXE region i.e. PcdSystemMemoryUefiRegionSize.
+ // If UEFI were to allocate any reserved or runtime region, it would be
+ // allocated from topmost RAM region.
+ // This ensures that maximum amount of lower RAM (32 bit addresses) are left
+ // for OS to allocate to devices that can only work with 32bit physical
+ // addresses. E.g. legacy devices that need to DMA to 32bit addresses.
+ for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
+ if (DramRegions[Index].Size == 0) {
+ continue;
+ }
+
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ // EDK2 does not have the concept of boot firmware copied into DRAM.
+ // To avoid the DXE core to overwrite this area we must create a memory
+ // allocation HOB for the region, but this only works if we split off the
+ // underlying resource descriptor as well.
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ // Update Size
+ Size = FdBase - BaseAddress;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ BaseAddress,
+ Size
+ );
}
- NextHob.Raw = GET_NEXT_HOB (NextHob);
- }
-
- if (!Found) {
- // Reserved the memory space occupied by the firmware volume
+ // create the System Memory HOB for the firmware
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
- DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ FdBase,
+ PcdGet32 (PcdFdSize)
);
+ // Create the System Memory HOB for the remaining region (top of the FD)s
+ Size = Top - FdTop;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FdTop,
+ Size
+ );
+ };
+ // Mark the memory covering the Firmware Device as boot services data
+ BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
+ FixedPcdGet32 (PcdFdSize),
+ EfiBootServicesData);
+ } else {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramRegions[Index].BaseAddress,
+ DramRegions[Index].Size
+ );
+ }
+
+ if (FoundSystemMem == TRUE) {
+ continue;
+ }
+
+ Size = DramRegions[Index].Size;
+
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ }
+
+ if ((UefiMemoryBase >= BaseAddress) && (Size >= UefiMemorySize)) {
+ FoundSystemMem = TRUE;
}
}

+ ASSERT (FoundSystemMem == TRUE);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);

diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 847331a63152..1ef99e8de25f 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -22,7 +22,6 @@
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>

-#include <DramInfo.h>
#include "NxpChassis.h"

UINT32
@@ -75,69 +74,3 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}

-UINTN
-GetDramSize (
- IN VOID
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
-
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = -1;
-
- ArmCallSmc (&ArmSmcArgs);
-
- if (ArmSmcArgs.Arg0) {
- return 0;
- } else {
- return ArmSmcArgs.Arg1;
- }
-}
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
- UINT32 I;
- UINTN DramSize;
-
- DramSize = GetDramSize ();
- DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
-
- // Ensure DramSize has been set
- ASSERT (DramSize != 0);
-
- I = 0;
-
- do {
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = I;
-
- ArmCallSmc (&ArmSmcArgs);
- if (ArmSmcArgs.Arg0) {
- if (I > 0) {
- break;
- } else {
- ASSERT (ArmSmcArgs.Arg0 == 0);
- }
- }
-
- DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
- DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
-
- DramSize -= DramInfo->DramRegion[I].Size;
-
- DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
- I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
-
- I++;
- } while (DramSize);
-
- DramInfo->NumOfDrams = I;
-
- DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
-
- return EFI_SUCCESS;
-}
--
2.17.1


[PATCH edk2-platforms v3 11/24] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsHelper.S => ArmPlatformLib/AArch64/ArmPlatformHelper.S} | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 1975f2c4c52c..e5383aaf0cc5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -26,7 +26,7 @@
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
- ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

[PcdsFixedAtBuild.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
similarity index 89%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 7563a1c43630..7a43ad86d183 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -27,8 +27,8 @@
SocLib

[Sources.common]
- NxpQoriqLsHelper.S | GCC
- NxpQoriqLsMem.c
+ AArch64/ArmPlatformHelper.S | GCC
+ ArmPlatformLibMem.c
ArmPlatformLib.c

[Ppis]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
similarity index 93%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index eac7d4aa4e47..718c71bf02eb 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
similarity index 100%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
similarity index 88%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
index 84ee8c9f9700..dfbf73675a2d 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
--
2.17.1


[PATCH edk2-platforms v3 10/24] Silicon/NXP: Move dsc file

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc.inc
rename to Silicon/NXP/NxpQoriqLs.dsc.inc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 385b6e067e26..1975f2c4c52c 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -22,7 +22,7 @@
OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf

-!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
--
2.17.1


[PATCH edk2-platforms v3 09/24] Silicon/NXP: Remove unnecessary PCDs

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The memory map of an SOC is fixed in hardware. it doesn't change with
platform that uses SOC. So, there is no need to keep PCDs for these values
and we can use macros for these in SOC header file.

Any Platform using the SOC, can make use of the SOC header file.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Silicon/NXP/NxpQoriqLs.dec | 47 ------------
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 26 -------
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 10 +--
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 21 +-----
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
Silicon/NXP/LS1043A/Include/Soc.h | 44 +++++++++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 15 ++--
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 79 +++++++++-----------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
10 files changed, 97 insertions(+), 150 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 943dbac81013..b478560450b3 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,53 +22,6 @@
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

[PcdsFixedAtBuild.common]
- #
- # Pcds for I2C Controller
- #
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
-
- #
- # Pcds for base address and size
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
- gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
- gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
-
- #
- # IFC PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
-
#
# Platform PCDs
#
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index f6ada08dad9d..7690e4caa593 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -26,32 +26,6 @@
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500

- #
- # CCSR Address Space and other attached Memories
- #
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
-
#
# Big Endian IPs
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index d689cf4db58e..038d48949a39 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -2,7 +2,7 @@
#
# Component description file for LS1043 DXE platform driver.
#
-# Copyright 2018-2019 NXP
+# Copyright 2018-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -21,9 +21,10 @@

[Packages]
ArmPkg/ArmPkg.dec
- MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
@@ -43,10 +44,5 @@
gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES

-[FixedPcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f7ae74afc6ca..7563a1c43630 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017, 2019 NXP
+# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -19,6 +19,7 @@
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
@@ -35,21 +36,3 @@

[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index f75a8d19f5a5..b7c7fc78cc8f 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,5 +36,4 @@
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 74330b6205e7..6812beafe447 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -12,6 +12,8 @@

#define CLK_FREQ 100000000

+#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
new file mode 100644
index 000000000000..441871757d67
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SOC_H__
+#define SOC_H__
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#endif // SOC_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
index f89dcdeff3c1..62c400eb1a58 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -1,7 +1,7 @@
/** @file
LS1043 DXE platform driver.

- Copyright 2018-2019 NXP
+ Copyright 2018-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -14,6 +14,7 @@
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Soc.h>

#include <Protocol/NonDiscoverableDevice.h>

@@ -22,7 +23,7 @@ typedef struct {
UINT8 EndDesc;
} ADDRESS_SPACE_DESCRIPTOR;

-STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];

STATIC
EFI_STATUS
@@ -65,19 +66,19 @@ PopulateI2cInformation (
{
UINT32 Index;

- for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
mI2cDesc[Index].StartDesc.GenFlag = 0;
mI2cDesc[Index].StartDesc.SpecificFlag = 0;
mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
- mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
- (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
+ (Index * LS1043A_I2C_SIZE);
mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
- FixedPcdGet32 (PcdI2cSize) - 1;
+ LS1043A_I2C_SIZE - 1;
mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
- mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+ mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;

mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index c6c256da0727..f5fa308551aa 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017, 2019 NXP
+* Copyright 2017, 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,7 +16,7 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
-#include <DramInfo.h>
+#include <Soc.h>

#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25

@@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
{
UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- DRAM_INFO DramInfo;

Index = 0;

@@ -51,24 +50,20 @@ ArmPlatformGetVirtualMemoryMap (
return;
}

- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

-
- for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
- // DRAM1 (Must be 1st entry)
- VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

// CCSR Space
- VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// IFC region 1
@@ -85,51 +80,51 @@ ArmPlatformGetVirtualMemoryMap (
// For write transactions from non-core masters (like system DMA), the address
// should be 16 byte aligned and the data size should be multiple of 16 bytes.
//
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// QMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// BMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// IFC region 2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe1
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe3
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// QSPI region
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// End of Table
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index d992e53546f4..98ca2e162f7b 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -34,7 +34,7 @@ GetSysInfo (
CCSR_GUR *GurBase;
UINTN SysClk;

- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
SysClk = CLK_FREQ;

SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
--
2.17.1


[PATCH edk2-platforms v3 08/24] Silicon/NXP: remove not needed components

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The structures elements and functions that are not necessary for booting
for now are being deleted.
Once the directory structure has been changed (i.e. we have clear
distinction between chassis code and header files and SOC code and header
files), we will put back the code and
structure components back at their appropriate respective place.

Also right now all the elements are being defined in structures, which are
not being used right now. So to simplify the code restructuring, I have
removed those for now. When we need to use those elements, we can define
those one by one.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- remove CpuMaskNext from this patch and put in previous patch

Silicon/NXP/NxpQoriqLs.dec | 27 --
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 6 -
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 4 -
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 7 +-
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +-------------------
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ----
Silicon/NXP/Library/SocLib/NxpChassis.h | 90 ------
Silicon/NXP/Library/SocLib/Chassis.c | 208 -------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 -----
Silicon/NXP/Library/SocLib/SerDes.c | 268 -----------------
11 files changed, 3 insertions(+), 1113 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4a1cfb3e278e..943dbac81013 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -32,10 +32,7 @@
# Pcds for base address and size
#
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
@@ -61,10 +58,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
- gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
- gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123

@@ -75,36 +68,16 @@
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
- gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
- gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
-
- #
- # NV Pcd
- #
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211

#
# Platform PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
-
- #
- # Clock PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
- gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1

#
# Pcds to support Big Endian IPs
#
- gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
- gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
- gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index d2d4133428c3..f6ada08dad9d 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -31,12 +31,10 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
@@ -47,10 +45,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
@@ -61,6 +56,5 @@
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE

##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 802cccdce63b..385b6e067e26 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,10 +39,6 @@
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000

- #
- # Board Specific Pcds
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1

#
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index cb670a12797e..f75a8d19f5a5 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -18,7 +18,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec

[LibraryClasses]
ArmSmcLib
@@ -30,16 +29,12 @@
[Sources.common]
Chassis.c
Chassis2/Soc.c
- SerDes.c

[BuildOptions]
GCC:*_*_*_CC_FLAGS = -DCHASSIS2

[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
deleted file mode 100644
index 9afbc522398a..000000000000
--- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** LsSerDes.h
- The Header file of SerDes Module for Chassis 2
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef LS_SERDES_H_
-#define LS_SERDES_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SRDS_MAX_LANES 4
-
-typedef enum {
- None = 0,
- Pcie1,
- Pcie2,
- Pcie3,
- Sata,
- SgmiiFm1Dtsec1,
- SgmiiFm1Dtsec2,
- SgmiiFm1Dtsec5,
- SgmiiFm1Dtsec6,
- SgmiiFm1Dtsec9,
- SgmiiFm1Dtsec10,
- QsgmiiFm1A,
- XfiFm1Mac9,
- XfiFm1Mac10,
- Sgmii2500Fm1Dtsec2,
- Sgmii2500Fm1Dtsec5,
- Sgmii2500Fm1Dtsec9,
- Sgmii2500Fm1Dtsec10,
- SerdesPrtclCount
-} SERDES_PROTOCOL;
-
-typedef enum {
- Srds1 = 0,
- Srds2,
- SrdsMaxNum
-} SERDES_NUMBER;
-
-typedef struct {
- UINT16 Protocol;
- UINT8 SrdsLane[SRDS_MAX_LANES];
-} SERDES_CONFIG;
-
-typedef VOID
-(*SERDES_PROBE_LANES_CALLBACK) (
- IN SERDES_PROTOCOL LaneProtocol,
- IN VOID *Arg
- );
-
-VOID
-SerDesProbeLanes(
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- );
-
-#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index f05a813750e8..74330b6205e7 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -1,7 +1,7 @@
/** Soc.h
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -10,22 +10,7 @@
#ifndef NXP_SOC_H_
#define NXP_SOC_H_

-#define HWA_CGA_M1_CLK_SEL 0xe0000000
-#define HWA_CGA_M1_CLK_SHIFT 29
-
-#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
-#define NUM_CC_PLLS 2
#define CLK_FREQ 100000000
-#define MAX_CPUS 4
-#define NUM_FMAN 1
-#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
-
-/* RCW SERDES MACRO */
-#define RCWSR_INDEX 4
-#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
-#define RCWSR_SRDS1_PRTCL_SHIFT 16
-#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
-#define RCWSR_SRDS2_PRTCL_SHIFT 0

/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
@@ -41,312 +26,17 @@
#define IDR1_PAGESIZE_MASK 0x80000000

typedef struct {
- UINTN FreqProcessor[MAX_CPUS];
UINTN FreqSystemBus;
- UINTN FreqDdrBus;
- UINTN FreqLocalBus;
- UINTN FreqSdhc;
- UINTN FreqFman[NUM_FMAN];
- UINTN FreqQman;
} SYS_INFO;

/* Device Configuration and Pin Control */
typedef struct {
- UINT32 PorSr1; /* POR status 1 */
-#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
- UINT32 PorSr2; /* POR status 2 */
- UINT8 Res008[0x20-0x8];
- UINT32 GppOrCr1; /* General-purpose POR configuration */
- UINT32 GppOrCr2;
- UINT32 DcfgFuseSr; /* Fuse status register */
- UINT8 Res02c[0x70-0x2c];
- UINT32 DevDisr; /* Device disable control */
- UINT32 DevDisr2; /* Device disable control 2 */
- UINT32 DevDisr3; /* Device disable control 3 */
- UINT32 DevDisr4; /* Device disable control 4 */
- UINT32 DevDisr5; /* Device disable control 5 */
- UINT32 DevDisr6; /* Device disable control 6 */
- UINT32 DevDisr7; /* Device disable control 7 */
- UINT8 Res08c[0x94-0x8c];
- UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
- UINT32 CoreDisrL; /* lower portion for support of 64 cores */
- UINT8 Res09c[0xa0-0x9c];
- UINT32 Pvr; /* Processor version */
- UINT32 Svr; /* System version */
- UINT32 Mvr; /* Manufacturing version */
- UINT8 Res0ac[0xb0-0xac];
- UINT32 RstCr; /* Reset control */
- UINT32 RstRqPblSr; /* Reset request preboot loader status */
- UINT8 Res0b8[0xc0-0xb8];
- UINT32 RstRqMr1; /* Reset request mask */
- UINT8 Res0c4[0xc8-0xc4];
- UINT32 RstRqSr1; /* Reset request status */
- UINT8 Res0cc[0xd4-0xcc];
- UINT32 RstRqWdTmrL; /* Reset request WDT mask */
- UINT8 Res0d8[0xdc-0xd8];
- UINT32 RstRqWdtSrL; /* Reset request WDT status */
- UINT8 Res0e0[0xe4-0xe0];
- UINT32 BrrL; /* Boot release */
- UINT8 Res0e8[0x100-0xe8];
+ UINT8 Res0[0x100-0x00];
UINT32 RcwSr[16]; /* Reset control word status */
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
- UINT8 Res140[0x200-0x140];
- UINT32 ScratchRw[4]; /* Scratch Read/Write */
- UINT8 Res210[0x300-0x210];
- UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
- UINT8 Res310[0x400-0x310];
- UINT32 CrstSr[12];
- UINT8 Res430[0x500-0x430];
- /* PCI Express n Logical I/O Device Number register */
- UINT32 DcfgCcsrPex1LiodNr;
- UINT32 DcfgCcsrPex2LiodNr;
- UINT32 DcfgCcsrPex3LiodNr;
- UINT32 DcfgCcsrPex4LiodNr;
- /* RIO n Logical I/O Device Number register */
- UINT32 DcfgCcsrRio1LiodNr;
- UINT32 DcfgCcsrRio2LiodNr;
- UINT32 DcfgCcsrRio3LiodNr;
- UINT32 DcfgCcsrRio4LiodNr;
- /* USB Logical I/O Device Number register */
- UINT32 DcfgCcsrUsb1LiodNr;
- UINT32 DcfgCcsrUsb2LiodNr;
- UINT32 DcfgCcsrUsb3LiodNr;
- UINT32 DcfgCcsrUsb4LiodNr;
- /* SD/MMC Logical I/O Device Number register */
- UINT32 DcfgCcsrSdMmc1LiodNr;
- UINT32 DcfgCcsrSdMmc2LiodNr;
- UINT32 DcfgCcsrSdMmc3LiodNr;
- UINT32 DcfgCcsrSdMmc4LiodNr;
- /* RIO Message Unit Logical I/O Device Number register */
- UINT32 DcfgCcsrRiomaintLiodNr;
- UINT8 Res544[0x550-0x544];
- UINT32 SataLiodNr[4];
- UINT8 Res560[0x570-0x560];
- UINT32 DcfgCcsrMisc1LiodNr;
- UINT32 DcfgCcsrMisc2LiodNr;
- UINT32 DcfgCcsrMisc3LiodNr;
- UINT32 DcfgCcsrMisc4LiodNr;
- UINT32 DcfgCcsrDma1LiodNr;
- UINT32 DcfgCcsrDma2LiodNr;
- UINT32 DcfgCcsrDma3LiodNr;
- UINT32 DcfgCcsrDma4LiodNr;
- UINT32 DcfgCcsrSpare1LiodNr;
- UINT32 DcfgCcsrSpare2LiodNr;
- UINT32 DcfgCcsrSpare3LiodNr;
- UINT32 DcfgCcsrSpare4LiodNr;
- UINT8 Res5a0[0x600-0x5a0];
- UINT32 DcfgCcsrPblSr;
- UINT32 PamuBypENr;
- UINT32 DmaCr1;
- UINT8 Res60c[0x610-0x60c];
- UINT32 DcfgCcsrGenSr1;
- UINT32 DcfgCcsrGenSr2;
- UINT32 DcfgCcsrGenSr3;
- UINT32 DcfgCcsrGenSr4;
- UINT32 DcfgCcsrGenCr1;
- UINT32 DcfgCcsrGenCr2;
- UINT32 DcfgCcsrGenCr3;
- UINT32 DcfgCcsrGenCr4;
- UINT32 DcfgCcsrGenCr5;
- UINT32 DcfgCcsrGenCr6;
- UINT32 DcfgCcsrGenCr7;
- UINT8 Res63c[0x658-0x63c];
- UINT32 DcfgCcsrcGenSr1;
- UINT32 DcfgCcsrcGenSr0;
- UINT8 Res660[0x678-0x660];
- UINT32 DcfgCcsrcGenCr1;
- UINT32 DcfgCcsrcGenCr0;
- UINT8 Res680[0x700-0x680];
- UINT32 DcfgCcsrSrIoPstecr;
- UINT32 DcfgCcsrDcsrCr;
- UINT8 Res708[0x740-0x708]; /* add more registers when needed */
- UINT32 TpItyp[64]; /* Topology Initiator Type Register */
- struct {
- UINT32 Upper;
- UINT32 Lower;
- } TpCluster[16];
- UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
- UINT32 DcfgCcsrQmBmWarmRst;
- UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
- UINT32 DcfgCcsrReserved0;
- UINT32 DcfgCcsrReserved1;
} CCSR_GUR;

-/* Supplemental Configuration Unit */
-typedef struct {
- UINT8 Res000[0x070-0x000];
- UINT32 Usb1Prm1Cr;
- UINT32 Usb1Prm2Cr;
- UINT32 Usb1Prm3Cr;
- UINT32 Usb2Prm1Cr;
- UINT32 Usb2Prm2Cr;
- UINT32 Usb2Prm3Cr;
- UINT32 Usb3Prm1Cr;
- UINT32 Usb3Prm2Cr;
- UINT32 Usb3Prm3Cr;
- UINT8 Res094[0x100-0x094];
- UINT32 Usb2Icid;
- UINT32 Usb3Icid;
- UINT8 Res108[0x114-0x108];
- UINT32 DmaIcid;
- UINT32 SataIcid;
- UINT32 Usb1Icid;
- UINT32 QeIcid;
- UINT32 SdhcIcid;
- UINT32 EdmaIcid;
- UINT32 EtrIcid;
- UINT32 Core0SftRst;
- UINT32 Core1SftRst;
- UINT32 Core2SftRst;
- UINT32 Core3SftRst;
- UINT8 Res140[0x158-0x140];
- UINT32 AltCBar;
- UINT32 QspiCfg;
- UINT8 Res160[0x180-0x160];
- UINT32 DmaMcr;
- UINT8 Res184[0x188-0x184];
- UINT32 GicAlign;
- UINT32 DebugIcid;
- UINT8 Res190[0x1a4-0x190];
- UINT32 SnpCnfGcr;
-#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
-#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
-#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
-#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
-#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
-#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
-#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
-#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
-#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
-#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
- UINT8 Res1a8[0x1ac-0x1a8];
- UINT32 IntpCr;
- UINT8 Res1b0[0x204-0x1b0];
- UINT32 CoreSrEnCr;
- UINT8 Res208[0x220-0x208];
- UINT32 RvBar00;
- UINT32 RvBar01;
- UINT32 RvBar10;
- UINT32 RvBar11;
- UINT32 RvBar20;
- UINT32 RvBar21;
- UINT32 RvBar30;
- UINT32 RvBar31;
- UINT32 LpmCsr;
- UINT8 Res244[0x400-0x244];
- UINT32 QspIdQScr;
- UINT32 EcgTxcMcr;
- UINT32 SdhcIoVSelCr;
- UINT32 RcwPMuxCr0;
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
- Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
-#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
- Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
-#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
- UINT32 UsbDrvVBusSelCr;
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
- UINT32 UsbPwrFaultSelCr;
-#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
-#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
-#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
-#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
-#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
-#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
- UINT32 UsbRefclkSelcr1;
- UINT32 UsbRefclkSelcr2;
- UINT32 UsbRefclkSelcr3;
- UINT8 Res424[0x600-0x424];
- UINT32 ScratchRw[4];
- UINT8 Res610[0x680-0x610];
- UINT32 CoreBCr;
- UINT8 Res684[0x1000-0x684];
- UINT32 Pex1MsiIr;
- UINT32 Pex1MsiR;
- UINT8 Res1008[0x2000-0x1008];
- UINT32 Pex2;
- UINT32 Pex2MsiR;
- UINT8 Res2008[0x3000-0x2008];
- UINT32 Pex3MsiIr;
- UINT32 Pex3MsiR;
-} CCSR_SCFG;
-
-#define USB_TXVREFTUNE 0x9
-#define USB_SQRXTUNE 0xFC7FFFFF
-#define USB_PCSTXSWINGFULL 0x47
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x8000
-#define USB_PHY_RX_EQ_VAL_3 0x8003
-#define USB_PHY_RX_EQ_VAL_4 0x800b
-
-/*USB_PHY_SS memory map*/
-typedef struct {
- UINT16 IpIdcodeLo;
- UINT16 SupIdcodeHi;
- UINT8 Res4[0x0006-0x0004];
- UINT16 RtuneDebug;
- UINT16 RtuneStat;
- UINT16 SupSsPhase;
- UINT16 SsFreq;
- UINT8 ResE[0x0020-0x000e];
- UINT16 Ateovrd;
- UINT16 MpllOvrdInLo;
- UINT8 Res24[0x0026-0x0024];
- UINT16 SscOvrdIn;
- UINT8 Res28[0x002A-0x0028];
- UINT16 LevelOvrdIn;
- UINT8 Res2C[0x0044-0x002C];
- UINT16 ScopeCount;
- UINT8 Res46[0x0060-0x0046];
- UINT16 MpllLoopCtl;
- UINT8 Res62[0x006C-0x0062];
- UINT16 SscClkCntrl;
- UINT8 Res6E[0x2002-0x006E];
- UINT16 Lane0TxOvrdInHi;
- UINT16 Lane0TxOvrdDrvLo;
- UINT8 Res2006[0x200C-0x2006];
- UINT16 Lane0RxOvrdInHi;
- UINT8 Res200E[0x2022-0x200E];
- UINT16 Lane0TxCmWaitTimeOvrd;
- UINT8 Res2024[0x202A-0x2024];
- UINT16 Lane0TxLbertCtl;
- UINT16 Lane0RxLbertCtl;
- UINT16 Lane0RxLbertErr;
- UINT8 Res2030[0x205A-0x2030];
- UINT16 Lane0TxAltBlock;
-} CCSR_USB_PHY;
-
-/* Clocking */
-typedef struct {
- struct {
- UINT32 ClkCnCSr; /* core cluster n clock control status */
- UINT8 Res004[0x0c];
- UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
- UINT8 Res014[0x0c];
- } ClkcSr[4];
- UINT8 Res040[0x780]; /* 0x100 */
- struct {
- UINT32 PllCnGSr;
- UINT8 Res804[0x1c];
- } PllCgSr[NUM_CC_PLLS];
- UINT8 Res840[0x1c0];
- UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
- UINT8 Resa04[0x1fc];
- UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
- UINT8 Resc04[0x1c];
- UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
- UINT8 Resc24[0x3dc];
-} CCSR_CLOCK;
-
VOID
GetSysInfo (
OUT SYS_INFO *
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
deleted file mode 100644
index 2d1c6f10f932..000000000000
--- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- The Header file of SerDes Module for LS1043A
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef SOC_SERDES_H_
-#define SOC_SERDES_H_
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#endif
-
-SERDES_CONFIG SerDes1ConfigTbl[] = {
- /* SerDes 1 */
- {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
- {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
- {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
- {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
- {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
- {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
- {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
- {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
- {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
- {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
- {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
- {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
- {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {}
-};
-
-SERDES_CONFIG *SerDesConfigTbl[] = {
- SerDes1ConfigTbl
-};
-
-#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
index a11acf71563e..836df103f80f 100644
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -10,58 +10,6 @@
#ifndef NXP_CHASSIS_H_
#define NXP_CHASSIS_H_

-#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
-
-#define TY_ITYP_VERSION_A7 0x1
-#define TY_ITYP_VERSION_A53 0x2
-#define TY_ITYP_VERSION_A57 0x3
-#define TY_ITYP_VERSION_A72 0x4
-
-#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879200
-#define SVR_LS1046A 0x870700
-#define SVR_LS2088A 0x870901
-
-#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
-#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-#define MHZ 1000000
-
-typedef struct {
- CHAR8 *Name;
- UINT32 SocVer;
- UINT32 NumCores;
-} CPU_TYPE;
-
-typedef struct {
- UINTN CpuClk; /* CPU clock in Hz! */
- UINTN BusClk;
- UINTN MemClk;
- UINTN PciClk;
- UINTN SdhcClk;
-} SOC_CLOCK_INFO;
-
-/*
- * Initialize Clock structure
- */
-VOID
-ClockInit (
- VOID
- );
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -71,42 +19,4 @@ SmmuInit (
VOID
);

-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- );
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- );
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- );
-
-/*
- * Return the type of initiator for core/hardware accelerator for given core index.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- );
-
-/*
- * Return the cluster of initiator for core/hardware accelerator for given core index.
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- );
-
#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index adca7b8dd413..847331a63152 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -25,16 +25,6 @@
#include <DramInfo.h>
#include "NxpChassis.h"

-/*
- * Structure to list available SOCs.
- * Name, Soc Version, Number of Cores
- */
-STATIC CPU_TYPE mCpuTypeList[] = {
- CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
-};
-
UINT32
EFIAPI
GurRead (
@@ -48,162 +38,6 @@ GurRead (
}
}

-/*
- * Return the type of initiator (core or hardware accelerator)
- */
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- )
-{
- CCSR_GUR *GurBase;
- UINT32 Idx;
- UINT32 Type;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
- Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
-
- if (Type & TP_ITYP_AV_MASK) {
- return Type;
- }
-
- return 0;
-}
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINT32 Mask;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- Mask = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
- Mask |= 1 << Count;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return Mask;
-}
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- )
-{
- UINTN Count;
- UINTN Num;
-
- Count = 0;
- Num = CpuMask ();
-
- while (Num) {
- Count += Num & 1;
- Num >>= 1;
- }
-
- return Count;
-}
-
-/*
- * Return core's cluster
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return ClusterIndex;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return -1; // cannot identify the cluster
-}
-
-/*
- * Return the type of core i.e. A53, A57 etc of inputted
- * core number.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return Type;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return EFI_NOT_FOUND; /* cannot identify the cluster */
-}
-
/*
* Return system bus frequency
*/
@@ -219,21 +53,6 @@ GetBusFrequency (
return SocSysInfo.FreqSystemBus;
}

-/*
- * Return SDXC bus frequency
- */
-UINT64
-GetSdxcFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSdhc;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -256,33 +75,6 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}

-/*
- * Return current Soc Name form mCpuTypeList
- */
-CHAR8 *
-GetSocName (
- VOID
- )
-{
- UINT8 Count;
- UINTN Svr;
- UINTN Ver;
- CCSR_GUR *GurBase;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- return (CHAR8 *)mCpuTypeList[Count].Name;
- }
- }
-
- return NULL;
-}
-
UINTN
GetDramSize (
IN VOID
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 687a1d940066..d992e53546f4 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -32,38 +32,14 @@ GetSysInfo (
)
{
CCSR_GUR *GurBase;
- CCSR_CLOCK *ClkBase;
- UINTN CpuIndex;
- UINT32 TempRcw;
- UINT32 CPllSel;
- UINT32 CplxPll;
- CONST UINT8 CoreCplxPll[8] = {
- [0] = 0, /* CC1 PPL / 1 */
- [1] = 0, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 1, /* CC2 PPL / 2 */
- };
-
- CONST UINT8 CoreCplxPllDivisor[8] = {
- [0] = 1, /* CC1 PPL / 1 */
- [1] = 2, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 2, /* CC2 PPL / 2 */
- };
-
- UINTN PllCount;
- UINTN FreqCPll[NUM_CC_PLLS];
- UINTN PllRatio[NUM_CC_PLLS];
UINTN SysClk;

GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
SysClk = CLK_FREQ;

SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);

PtrSysInfo->FreqSystemBus = SysClk;
- PtrSysInfo->FreqDdrBus = SysClk;

//
// selects the platform clock:SYSCLK ratio and calculate
@@ -72,61 +48,6 @@ GetSysInfo (
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
- //
- // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
- //
- PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-
- for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
- PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
- if (PllRatio[PllCount] > 4) {
- FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
- } else {
- FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
- }
- }
-
- //
- // Calculate Core frequency
- //
- for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
- CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
- CplxPll = CoreCplxPll[CPllSel];
-
- PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
- }
-
- //
- // Calculate FMAN frequency
- //
- TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
- switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
- case 2:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
- break;
- case 3:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
- break;
- case 4:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
- break;
- case 5:
- PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
- break;
- case 6:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
- break;
- case 7:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
- break;
- default:
- DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
- break;
- }
- PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
- PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
}

/**
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
deleted file mode 100644
index b9909d922138..000000000000
--- a/Silicon/NXP/Library/SocLib/SerDes.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/** SerDes.c
- Provides the basic interfaces for SerDes Module
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/LsSerDes.h>
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/DebugLib.h>
-#include <SocSerDes.h>
-#include <Uefi.h>
-
-/**
- Function to get serdes Lane protocol corresponding to
- serdes protocol.
-
- @param SerDes Serdes number.
- @param Cfg Serdes Protocol.
- @param Lane Serdes Lane number.
-
- @return Serdes Lane protocol.
-
-**/
-STATIC
-SERDES_PROTOCOL
-GetSerDesPrtcl (
- IN INTN SerDes,
- IN INTN Cfg,
- IN INTN Lane
- )
-{
- SERDES_CONFIG *Config;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return 0;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Cfg) {
- return Config->SrdsLane[Lane];
- }
- Config++;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if inputted protocol is a valid serdes protocol.
-
- @param SerDes Serdes number.
- @param Prtcl Serdes Protocol to be verified.
-
- @return EFI_INVALID_PARAMETER Input parameter in invalid.
- @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
- @return EFI_SUCCESS Serdes Protocol is a valid protocol.
-
-**/
-STATIC
-EFI_STATUS
-CheckSerDesPrtclValid (
- IN INTN SerDes,
- IN UINT32 Prtcl
- )
-{
- SERDES_CONFIG *Config;
- INTN Cnt;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return EFI_INVALID_PARAMETER;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Prtcl) {
- DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
- break;
- }
- Config++;
- }
-
- if (!Config->Protocol) {
- return EFI_NOT_FOUND;
- }
-
- for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
- if (Config->SrdsLane[Cnt] != None) {
- return EFI_SUCCESS;
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- Function to fill serdes map information.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Serdes Protocol Mask.
- @param SerdesProtocolShift Serdes Protocol shift value.
- @param SerDesPrtclMap Pointer to Serdes Protocol map.
-
-**/
-STATIC
-VOID
-LSSerDesMap (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- OUT UINT64 *SerDesPrtclMap
- )
-{
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
- UINT32 Flag;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- *SerDesPrtclMap = 0x0;
- Flag = 0;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
- Srds + 1, SrdsProt, SrdsProt));
-
- if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
- DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
- Srds + 1, SrdsProt));
- Flag++;
- }
-
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if (LanePrtcl >= SerdesPrtclCount) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- Flag++;
- } else {
- *SerDesPrtclMap |= (1u << LanePrtcl);
- }
- }
-
- if (Flag) {
- DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
- } else {
- DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
- }
-}
-
-/**
- Get lane protocol on provided serdes lane and execute callback function.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
- @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-STATIC
-VOID
-SerDesInstanceProbeLanes (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
-
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- /*
- * Invoke callback for all lanes in the SerDes instance:
- */
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- } else if (LanePrtcl != None) {
- SerDesLaneProbeCallback (LanePrtcl, Arg);
- }
- }
-}
-
-/**
- Probe all serdes lanes for lane protocol and execute provided callback function.
-
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-VOID
-SerDesProbeLanes (
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
- SerDesInstanceProbeLanes (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- SerDesInstanceProbeLanes (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
- }
-}
-
-/**
- Function to return Serdes protocol map for all serdes available on board.
-
- @param SerDesPrtclMap Pointer to Serdes protocl map.
-
-**/
-VOID
-GetSerdesProtocolMaps (
- OUT UINT64 *SerDesPrtclMap
- )
-{
- LSSerDesMap (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesPrtclMap);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- LSSerDesMap (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesPrtclMap);
- }
-
-}
-
-BOOLEAN
-IsSerDesLaneProtocolConfigured (
- IN UINT64 SerDesPrtclMap,
- IN SERDES_PROTOCOL Device
- )
-{
- if ((Device >= SerdesPrtclCount) || (Device < None)) {
- ASSERT ((Device > None) && (Device < SerdesPrtclCount));
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
- }
-
- return (SerDesPrtclMap & (1u << Device)) != 0 ;
-}
--
2.17.1


[PATCH edk2-platforms v3 07/24] Silicon/NXP: remove print information from Soc lib

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase implementation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
core info.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- remove CpuMaskNext definition

Silicon/NXP/Library/SocLib/NxpChassis.h | 26 +---
Silicon/NXP/Library/SocLib/Chassis.c | 144 --------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 16 +--
3 files changed, 2 insertions(+), 184 deletions(-)

diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
index 99f6439d8f35..a11acf71563e 100644
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -1,7 +1,7 @@
/** @file
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -54,14 +54,6 @@ typedef struct {
UINTN SdhcClk;
} SOC_CLOCK_INFO;

-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- );
-
/*
* Initialize Clock structure
*/
@@ -79,22 +71,6 @@ SmmuInit (
VOID
);

-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- );
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- );
-
UINT32
InitiatorType (
IN UINT32 Cluster,
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index b8a8118c5e24..adca7b8dd413 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -204,79 +204,6 @@ QoriqCoreToType (
return EFI_NOT_FOUND; /* cannot identify the cluster */
}

-STATIC
-UINTN
-CpuMaskNext (
- IN UINTN Cpu,
- IN UINTN Mask
- )
-{
- for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
-
- return Cpu;
-}
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- )
-{
- SYS_INFO SysInfo;
- UINTN CoreIndex;
- UINTN Core;
- UINT32 Type;
- UINT32 NumCpus;
- UINT32 Mask;
- CHAR8 *CoreName;
-
- GetSysInfo (&SysInfo);
- DEBUG ((DEBUG_INIT, "Clock Configuration:"));
-
- NumCpus = CpuNumCores ();
- Mask = CpuMask ();
-
- for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
- CoreIndex < NumCpus;
- CoreIndex++, Core = CpuMaskNext(Core, Mask))
- {
- if (!(CoreIndex % 3)) {
- DEBUG ((DEBUG_INIT, "\n "));
- }
-
- Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
- switch (Type) {
- case TY_ITYP_VERSION_A7:
- CoreName = "A7";
- break;
- case TY_ITYP_VERSION_A53:
- CoreName = "A53";
- break;
- case TY_ITYP_VERSION_A57:
- CoreName = "A57";
- break;
- case TY_ITYP_VERSION_A72:
- CoreName = "A72";
- break;
- default:
- CoreName = " Unknown Core ";
- }
- DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
- Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
- DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
-
- if (SysInfo.FreqFman[0] != 0) {
- DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Return system bus frequency
*/
@@ -307,77 +234,6 @@ GetSdxcFrequency (
return SocSysInfo.FreqSdhc;
}

-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- )
-{
- CHAR8 Buf[20];
- CCSR_GUR *GurBase;
- UINTN Count;
- //
- // Svr : System Version Register
- //
- UINTN Svr;
- UINTN Ver;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
-
- if (IS_E_PROCESSOR (Svr)) {
- AsciiStrCatS (Buf, sizeof (Buf), "E");
- }
- break;
- }
- }
-
- DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
- Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
-
- return;
-}
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- )
-{
- CCSR_GUR *Base;
- UINTN Count;
-
- Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- /*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
-
- DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
- for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
- UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
-
- if ((Count % 4) == 0) {
- DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
- }
-
- DEBUG ((DEBUG_INIT, " %08x", Rcw));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index bfb8b8cb339a..687a1d940066 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -1,7 +1,7 @@
/** @Soc.c
SoC specific Library containg functions to initialize various SoC components

- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -131,10 +131,6 @@ GetSysInfo (

/**
Function to initialize SoC specific constructs
- CPU Info
- SoC Personality
- Board Personality
- RCW prints
**/
VOID
SocInit (
@@ -147,16 +143,6 @@ SocInit (
// Early init serial Port to get board information.
//
SerialPortInitialize ();
- DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
- (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
-
- PrintCpuInfo ();
-
- //
- // Print Reset control Word
- //
- PrintRCW ();
- PrintSoc ();

return;
}
--
2.17.1


[PATCH edk2-platforms v3 06/24] NXP/LS1043aRdb: Move Soc specific components to soc files

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Soc specific components ought to be part of Soc files and not
platform files. move the same to SOC files

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 7 ++++++-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------
3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 25c0a41e5d4a..8fbd6288cfae 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -95,6 +95,8 @@
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index dbd680b0ad28..d2d4133428c3 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -1,12 +1,16 @@
# LS1043A.dsc
# LS1043A Soc package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#

+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
@@ -20,6 +24,7 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000

[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500

#
# CCSR Address Space and other attached Memories
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c8105593533f..802cccdce63b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -2,7 +2,7 @@
#
# LS1043ARDB Board package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -26,11 +26,7 @@
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
- ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
- SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
- IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

[PcdsFixedAtBuild.common]
@@ -46,7 +42,6 @@
#
# Board Specific Pcds
#
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1

--
2.17.1


[PATCH edk2-platforms v3 05/24] Silicon/Maxim: Add comments in Ds1307RtcLib

Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Add comments to explain the register read and write operation
on Ds1307. These comments have been referred from data sheet:

https://datasheets.maximintegrated.com/en/ds/DS1307.pdf

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
Reviewed-by: Leif Lindholm <leif@...>
---

Notes:
- No change

Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
index fd7a8696e405..444e01124811 100644
--- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;

/**
Read RTC register.
+ Data Read-Slave Transmitter Mode
+
+ <Slave Address> <Word Address (n)> <Slave Address> <Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
+
+ The first byte is received and handled as in the slave receiver mode.

@param RtcRegAddr Register offset of RTC to be read.

@@ -69,6 +74,9 @@ RtcRead (

/**
Write RTC register.
+ Data Write-Slave Receiver Mode
+
+ <Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>

@param RtcRegAddr Register offset of RTC to write.
@param Val Value to be written
--
2.17.1