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Re: [PATCH] NetworkPkg/UefiPxeBcDxe: handle competing DHCP servers (more) gracefully

Siyuan, Fu
 

Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>

-----Original Message-----
From: Laszlo Ersek <lersek@redhat.com>
Sent: 2020年3月31日 8:48
To: edk2-devel-groups-io <devel@edk2.groups.io>
Cc: Wu, Jiaxin <jiaxin.wu@intel.com>; Maciej Rabeda
<maciej.rabeda@linux.intel.com>; Philippe Mathieu-Daudé
<philmd@redhat.com>; Fu, Siyuan <siyuan.fu@intel.com>
Subject: [PATCH] NetworkPkg/UefiPxeBcDxe: handle competing DHCP servers
(more) gracefully

When DHCP is misconfigured on a network segment, such that two DHCP
servers attempt to reply to requests (and therefore race with each other),
the edk2 PXE client can confuse itself.

In PxeBcDhcp4BootInfo() / PxeBcDhcp6BootInfo(), the client may refer to a
DHCP reply packet as an "earlier" packet from the "same" DHCP server, when
in reality both packets are unrelated, and arrive from different DHCP
servers.

While the edk2 PXE client can do nothing to fix this, it should at least
not ASSERT() -- ASSERT() is for catching programming errors (violations of
invariants that are under the control of the programmer). ASSERT()s should
in particular not refer to external data (such as network packets). What's
more, in RELEASE builds, we get NULL pointer references.

Check the problem conditions with actual "if"s, and return
EFI_PROTOCOL_ERROR. This will trickle out to PxeBcLoadBootFile(), and be
reported as "PXE-E99: Unexpected network error".

Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---

Notes:
Repo: https://pagure.io/lersek/edk2.git
Branch: dhcp_assert

NetworkPkg/UefiPxeBcDxe/PxeBcBoot.c | 30 ++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcBoot.c
b/NetworkPkg/UefiPxeBcDxe/PxeBcBoot.c
index 10bbb06f7593..d062a526077b 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcBoot.c
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcBoot.c
@@ -482,7 +482,20 @@ PxeBcDhcp4BootInfo (
Cache4 = &Private->DhcpAck.Dhcp4;
}

- ASSERT (Cache4->OptList[PXEBC_DHCP4_TAG_INDEX_BOOTFILE] != NULL);
+ if (Cache4->OptList[PXEBC_DHCP4_TAG_INDEX_BOOTFILE] == NULL) {
+ //
+ // This should never happen in a correctly configured DHCP / PXE
+ // environment. One misconfiguration that can cause it is two DHCP
servers
+ // mistakenly running on the same network segment at the same time,
and
+ // racing each other in answering DHCP requests. Thus, the DHCP packets
+ // that the edk2 PXE client considers "belonging together" may actually
be
+ // entirely independent, coming from two (competing) DHCP servers.
+ //
+ // Try to deal with this gracefully. Note that this check is not
+ // comprehensive, as we don't try to identify all such errors.
+ //
+ return EFI_PROTOCOL_ERROR;
+ }

//
// Parse the boot server address.
@@ -612,7 +625,20 @@ PxeBcDhcp6BootInfo (
Cache6 = &Private->DhcpAck.Dhcp6;
}

- ASSERT (Cache6->OptList[PXEBC_DHCP6_IDX_BOOT_FILE_URL] != NULL);
+ if (Cache6->OptList[PXEBC_DHCP6_IDX_BOOT_FILE_URL] == NULL) {
+ //
+ // This should never happen in a correctly configured DHCP / PXE
+ // environment. One misconfiguration that can cause it is two DHCP
servers
+ // mistakenly running on the same network segment at the same time,
and
+ // racing each other in answering DHCP requests. Thus, the DHCP packets
+ // that the edk2 PXE client considers "belonging together" may actually
be
+ // entirely independent, coming from two (competing) DHCP servers.
+ //
+ // Try to deal with this gracefully. Note that this check is not
+ // comprehensive, as we don't try to identify all such errors.
+ //
+ return EFI_PROTOCOL_ERROR;
+ }

//
// Set the station address to IP layer.
--
2.19.1.3.g30247aa5d201


Re: [PATCH v2 03/28] Silicon/NXP/I2cDxe: Fix I2c Timeout with RTC

Leif Lindholm
 

On Fri, Mar 20, 2020 at 20:05:18 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@nxp.com>

With latest edk2 codebase, sometimes i2c timeout is observed when
Network devices are being probed.
This is happening when gRT->GetTime request is ongoing.
gRT->GetTime triggers a read request to Real Time Clock which is
connected to I2c bus.
In between read request, if an event occurs, which also triggers
gRT->GetTime (i.e. RTC read), the I2c bus goes into unrecovered state.

This state is not even recovered, when rebooting the board.
We need to power off the board completely to recover i2c bus.

To prevent this, TPL level of I2c read is being raised to high, so that
no other event can preempt this. with this solution no timeout has been
observed so far.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

---
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 12 ++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 ++-
2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 848e707c1673..a5aba47b3ed4 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -16,6 +16,7 @@
#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>

#include "I2cDxe.h"

@@ -88,6 +89,13 @@ StartRequest (
NXP_I2C_MASTER *I2c;
UINTN I2cBase;
EFI_STATUS Status;
+ EFI_TPL Tpl;
+ BOOLEAN AtRuntime;
+
+ AtRuntime = EfiAtRuntime ();
+ if (!AtRuntime) {
+ Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ }

I2c = NXP_I2C_FROM_THIS (This);

@@ -95,6 +103,10 @@ StartRequest (

Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);

+ if (!AtRuntime) {
+ gBS->RestoreTPL (Tpl);
+ }
+
return Status;
}

diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 84adb837c249..867376044656 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -13,7 +13,7 @@ [Defines]
INF_VERSION = 0x0001001A
BASE_NAME = I2cDxe
FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
- MODULE_TYPE = DXE_DRIVER
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = I2cDxeEntryPoint
UNLOAD = I2cDxeUnload
@@ -36,6 +36,7 @@ [LibraryClasses]
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiLib
+ UefiRuntimeLib

[Guids]
gNxpNonDiscoverableI2cMasterGuid
--
2.17.1


Re: [PATCH v2 2/2] Revert "NetworkPkg/TlsAuthConfigDxe: fix TlsCaCertificate attributes retrieval"

Siyuan, Fu
 

Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>

-----Original Message-----
From: michael.kubacki@outlook.com <michael.kubacki@outlook.com>
Sent: 2020年3月25日 11:00
To: devel@edk2.groups.io
Cc: Laszlo Ersek <lersek@redhat.com>; Fu, Siyuan <siyuan.fu@intel.com>;
Maciej Rabeda <maciej.rabeda@linux.intel.com>; Wu, Jiaxin
<jiaxin.wu@intel.com>
Subject: [PATCH v2 2/2] Revert "NetworkPkg/TlsAuthConfigDxe: fix
TlsCaCertificate attributes retrieval"

From: Michael Kubacki <michael.kubacki@microsoft.com>

This reverts commit 6896efdec2709e530b23c688cf0f31706709a0c5.

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2062

GetVariable() now returns attributes when it fails with
EFI_BUFFER_TOO_SMALL. Therefore, commit 6896efdec270 is
reverted since it is no longer relevant.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigImpl.c | 27 +-------------------
1 file changed, 1 insertion(+), 26 deletions(-)

diff --git a/NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigImpl.c
b/NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigImpl.c
index 715bc3a0a941..2481d1098fa3 100644
--- a/NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigImpl.c
+++ b/NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigImpl.c
@@ -657,7 +657,6 @@ EnrollX509toVariable (
EFI_SIGNATURE_LIST *CACert;
EFI_SIGNATURE_DATA *CACertData;
VOID *Data;
- VOID *CurrentData;
UINTN DataSize;
UINTN SigDataSize;
UINT32 Attr;
@@ -669,7 +668,6 @@ EnrollX509toVariable (
CACert = NULL;
CACertData = NULL;
Data = NULL;
- CurrentData = NULL;
Attr = 0;

Status = ReadFileContent (
@@ -712,30 +710,11 @@ EnrollX509toVariable (
Status = gRT->GetVariable(
VariableName,
&gEfiTlsCaCertificateGuid,
- NULL,
+ &Attr,
&DataSize,
NULL
);
if (Status == EFI_BUFFER_TOO_SMALL) {
- //
- // Per spec, we have to fetch the variable's contents, even though we're
- // only interested in the variable's attributes.
- //
- CurrentData = AllocatePool (DataSize);
- if (CurrentData == NULL) {
- Status = EFI_OUT_OF_RESOURCES;
- goto ON_EXIT;
- }
- Status = gRT->GetVariable(
- VariableName,
- &gEfiTlsCaCertificateGuid,
- &Attr,
- &DataSize,
- CurrentData
- );
- if (EFI_ERROR (Status)) {
- goto ON_EXIT;
- }
Attr |= EFI_VARIABLE_APPEND_WRITE;
} else if (Status == EFI_NOT_FOUND) {
Attr = TLS_AUTH_CONFIG_VAR_BASE_ATTR;
@@ -766,10 +745,6 @@ ON_EXIT:
FreePool (Data);
}

- if (CurrentData != NULL) {
- FreePool (CurrentData);
- }
-
if (X509Data != NULL) {
FreePool (X509Data);
}
--
2.16.3.windows.1


Re: [PATCH v2 01/28] Silicon/NXP: Add I2c lib

Leif Lindholm
 

On Fri, Mar 20, 2020 at 20:05:16 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@nxp.com>

I2c lib is going to be used in PrePeiCore sec module to get the
System clock information from devices connected to i2c (like fpga
or clock generator)

since we don't have support of DXE modules this early in boot stage,
move the i2c controller functionality in library.
This isn't moving the functionality to a library though - it is moving
the functionality to a library *and* adding new features. These are
two separate changes that should be two separate patches.

The content in this patch is mostly fine as the end result (but some
comments below).

I suggest this patch is reordered with 2/28 and all of the splitting
out part takes place in that patch. This patch can then be reduced to
... the bits that are currently impossible to see are changed (at
least the glitch fixing).

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
Silicon/NXP/Include/Library/I2cLib.h | 120 ++++
Silicon/NXP/Library/I2cLib/I2cLib.c | 576 ++++++++++++++++++++
Silicon/NXP/Library/I2cLib/I2cLib.inf | 31 ++
Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 105 ++++
Silicon/NXP/NxpQoriqLs.dec | 10 +-
6 files changed, 844 insertions(+), 2 deletions(-)
create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h

diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index fa5f30dd3909..b28e0615f7ca 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP.
+# Copyright 2017-2020 NXP.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -94,6 +94,8 @@ [LibraryClasses.common]
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

+ I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+
I think the changes to this file belong in 2/28.

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Library/I2cLib.h
new file mode 100644
index 000000000000..e39237abd3ee
--- /dev/null
+++ b/Silicon/NXP/Include/Library/I2cLib.h
@@ -0,0 +1,120 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef I2C_LIB_H__
+#define I2C_LIB_H__
+
+#include <Uefi.h>
+#include <Pi/PiI2c.h>
+
+/**
+ software reset of the entire I2C module.
+ The module is reset and disabled.
+ Status register fields (IBSR) are cleared.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly reset the I2c module
+**/
+EFI_STATUS
+I2cReset (
+ IN UINTN Base
+ );
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the
+ correct i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ );
+
+/**
+ Configure I2c bus to operate at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+
+ @return EFI_SUCCESS successfuly setup the i2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ );
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly transfer the data
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ );
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is
+ to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
+ I2c Slave for simple reads without any
+ register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave
+ register
+
+ @return EFI_SUCCESS successfuly read the registers
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT32 RegValueNumBytes
+ );
+
+#endif // I2C_LIB_H__
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cLib/I2cLib.c
new file mode 100644
index 000000000000..08bf14c490be
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
@@ -0,0 +1,576 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2017, 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/I2cLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+#include "I2cLibInternal.h"
+
+/**
+ I2C divisor and Ibfd register values when glitch filter is enabled
+
+ In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
+ has been selected. A higher MUL value results in a lower sampling rate of
+ the I2C signals. This gives the I2C module greater immunity against glitches
+ in the I2C signals.
So this comment (and the subsequent one) have been cleaned up and no
longer refers to an SoC not yet upstream. But this has also removed
any reference to where these values come from.

Has NXP (including acquisitions) only ever produced one I2C
controller?
If there is no standalone name for the controller, can something be
said about the family of devices that contains it?

+**/
+STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] = {
+ { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
+ { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
+ { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
+ { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
+ { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
+ { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
+ { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
+ { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
+ { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
+ { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
+ { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
+ { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
+ { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
+ { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
+ { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
+ { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
+ { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
+ { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
+ { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
+};
+
+/**
+ I2C divisor and Ibfd register values when glitch filter is disabled
+
+ In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
+ has been selected. A higher MUL value results in a lower sampling rate of
+ the I2C signals. This gives the I2C module greater immunity against glitches
+ in the I2C signals.
+**/
+STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] = {
+ { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
+ { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
+ { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
+ { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
+ { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
+ { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
+ { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
+ { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
+ { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
+ { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
+ { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
+ { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
+ { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
+ { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
+ { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
+ { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
+ { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
+ { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
+};
+
+/**
+ ERR009203 : I2C may not work reliably with the default setting
+
+ Description : The clocking circuitry of I2C module may not work reliably due
+ to the slow rise time of SCL signal.
+ Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN]
+ to 1.
+**/
+STATIC
+VOID
+I2cErratumA009203 (
I'm still missing an explanation of why The function contains A009203
but the comment header describes ERR009203.
I suggested an addition to the file header comment, but can't see
anything there.

+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+
+ Regs = (I2C_REGS *)Base;
+
+ MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
+}
+
+/**
+ software reset of the entire I2C module.
+ The module is reset and disabled.
+ Status register fields (IBSR) are cleared.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly reset the I2c module
+**/
+EFI_STATUS
+I2cReset (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+
+ Regs = (I2C_REGS *)Base;
+
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+ MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
+ MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the
+ correct i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+ UINT8 Ibfd;
"Ibfd" is not more CamelCase compliant than "Ibc" is, and no more
descriptive. Please, if this is a term used in official NXP
documentation, add it to a glossary in the file header comment.
If not, please name it using camel case as something I can understand
what it is intended to be used for without already knowing.

... skims ahead ...

OK, so now it's "I2c Bus Frequency Dividor" (think that should be
Divider). Sure, that can be Ibfd *if* introduced in the file header
glossary, in *every* file that contains this abbreviation.

+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
+
+ if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchEnabled).Ibfd;
+ } else {
+ Ibfd = ARRAY_LAST_ELEM (mI2cClockDivisorGlitchDisabled).Ibfd;
+ }
+
+ MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
+
+ I2cReset (Base);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure I2c bus to operate at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+
+ @return EFI_SUCCESS successfuly setup the i2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ )
+{
+ I2C_REGS *Regs;
+ UINT16 ClockDivisor;
+ UINT8 Ibfd; // I2c Bus Frequency Dividor Register
Introduction of non-standard abbreviations happen in the file header comment
block:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/v/release/2.20/5_source_files/52_spacing.html#5231-every-new-file-shall-begin-with-a-file-header-comment-block

+ CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair;
+ UINT32 ClockDivisorPairSize;
+ UINT32 Index;
+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
Is this erratum workaround intentionally invoked twice?
If so, the code could do with comments at all call sites explaining why.
I.e. "apply workaround before enabling controller", "re-apply
workaround after updating X", ...

+
+ Ibfd = 0;
+ ClockDivisor = (I2cBusClock + Speed - 1) / Speed;
+
+ if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ ClockDivisorPair = mI2cClockDivisorGlitchEnabled;
+ ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchEnabled);
+ } else {
+ ClockDivisorPair = mI2cClockDivisorGlitchDisabled;
+ ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchDisabled);
+ }
+
+ if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) {
+ Ibfd = ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd;
+ } else {
+ for (Index = 0; Index < ClockDivisorPairSize; Index++) {
+ if (ClockDivisorPair[Index].Divisor >= ClockDivisor) {
+ Ibfd = ClockDivisorPair[Index].Ibfd;
+ break;
+ }
+ }
+ }
+
+ MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
+
+ I2cReset (Base);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cBusTestBusBusy (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestBusy
+ )
+{
+ UINT32 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBAL) {
+ MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
+ return EFI_NOT_READY;
+ }
+
+ if (TestBusy && (Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == I2C_NUM_RETRIES) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cTransferComplete (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestRxAck
+)
+{
+ UINT32 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBIF) {
+ // Write 1 to clear the IBIF field
+ MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == I2C_NUM_RETRIES) {
+ return EFI_TIMEOUT;
+ }
+
+ if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
+ return EFI_NO_RESPONSE;
+ }
+
+ if (Reg & I2C_IBSR_TCF) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_DEVICE_ERROR;
+}
+
+STATIC
+EFI_STATUS
+I2cRead (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation,
+ IN BOOLEAN IsLastOperation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ // select Receive mode.
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
+ if (Operation->LengthInBytes > 1) {
+ // Set No ACK = 0
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK);
+ }
+
+ // Perform a dummy read to initiate the receive operation.
+ MmioRead8 ((UINTN)&Regs->Ibdr);
+
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if (Index == (Operation->LengthInBytes - 2)) {
+ // Set No ACK = 1
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
+ } else if (Index == (Operation->LengthInBytes - 1)) {
+ if (!IsLastOperation) {
+ // select Transmit mode (for repeat start)
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
+ } else {
+ // Generate Stop Signal
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ }
+ Operation->Buffer[Index] = MmioRead8 ((UINTN)&Regs->Ibdr);
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cWrite (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Write Data
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Reg;
+
+ Status = EFI_SUCCESS;
+ Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
+ if (Reg & I2C_IBSR_IBB) {
+ // Generate Stop Signal
+ MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ // Disable I2c Controller
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+I2cStart (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+
+ MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
+ MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
+
+ //Wait controller to be stable
+ MicroSecondDelay (1);
+
+ // Generate Start Signal
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Select Transmit Mode. set No ACK = 1
+ MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK));
+
+ return Status;
+}
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly transfer the data
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ )
+{
+ UINTN Index;
+ I2C_REGS *Regs;
+ EFI_I2C_OPERATION *Operation;
+ EFI_STATUS Status;
+ BOOLEAN IsLastOperation;
+
+ Regs = (I2C_REGS *)Base;
+ IsLastOperation = FALSE;
+
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ Status = I2cStart (Regs);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ for (Index = 0, Operation = RequestPacket->Operation;
+ Index < RequestPacket->OperationCount;
+ Index++, Operation++) {
+ if (Index == (RequestPacket->OperationCount - 1)) {
+ IsLastOperation = TRUE;
+ }
+ // Send repeat start after first transmit/recieve
+ if (Index) {
+ MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+ // Read/write data
+ if (Operation->Flags & I2C_FLAG_READ) {
+ Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
+ } else {
+ Status = I2cWrite (Regs, SlaveAddress, Operation);
+ }
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+
+ErrorExit:
+
+ I2cStop (Regs);
+
+ return Status;
+}
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is
+ to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
+ I2c Slave for simple reads without any
+ register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave
+ register
+
+ @return EFI_SUCCESS successfuly read the registers
+ @return EFI_DEVICE_ERROR There was an error while transferring data through
+ I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT32 RegValueNumBytes
+ )
+{
+ EFI_I2C_OPERATION *Operations;
+ I2C_REG_REQUEST RequestPacket;
+ UINTN OperationCount;
+ UINT8 Address[sizeof (RegAddress)];
+ UINT8 *PtrAddress;
This is too close to hungarian notation - AddressPtr works better.

/
Leif

+ EFI_STATUS Status;
+
+ ZeroMem (&RequestPacket, sizeof (RequestPacket));
+ OperationCount = 0;
+ Operations = RequestPacket.Operation;
+ PtrAddress = Address;
+
+ if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (RegAddressWidthInBytes != 0) {
+ Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
+ Operations[OperationCount].Buffer = PtrAddress;
+ while (RegAddressWidthInBytes--) {
+ *PtrAddress++ = RegAddress >> (8 * RegAddressWidthInBytes);
+ }
+ OperationCount++;
+ }
+
+ Operations[OperationCount].LengthInBytes = RegValueNumBytes;
+ Operations[OperationCount].Buffer = RegValue;
+ Operations[OperationCount].Flags = I2C_FLAG_READ;
+ OperationCount++;
+
+ RequestPacket.OperationCount = OperationCount;
+
+ Status = I2cBusXfer (
+ Base, SlaveAddress,
+ (EFI_I2C_REQUEST_PACKET *)&RequestPacket
+ );
+
+ return Status;
+}
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
new file mode 100644
index 000000000000..b9bd79ac1ef1
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Component description file for I2cLib module
+# Copyright 2017, 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = I2cLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b81f-20f7aeb0567f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2cLib
+
+[Sources.common]
+ I2cLib.c
+
+[LibraryClasses]
+ IoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
new file mode 100644
index 000000000000..2ca4a3639d2c
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
@@ -0,0 +1,105 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef I2C_LIB_INTERNAL_H__
+#define I2C_LIB_INTERNAL_H__
+
+#include <Pi/PiI2c.h>
+#include <Uefi.h>
+
+/** Module Disable
+ 0b - The module is enabled. You must clear this field before any other IBCR
+ fields have any effect.
+ 1b - The module is reset and disabled. This is the power-on reset situation.
+ When high, the interface is held in reset, but registers can still be
+ accessed. Status register fields (IBSR) are not valid when the module
+ is disabled.
+**/
+#define I2C_IBCR_MDIS BIT7
+// I2c Bus Interrupt Enable
+#define I2C_IBCR_IBIE BIT6
+/** Master / Slave Mode 0b - Slave mode 1b - Master mode
+ When you change this field from 0 to 1, the module generates a START signal
+ on the bus and selects the master mode. When you change this field from 1 to
+ 0, the module generates a STOP signal and changes the operation mode from
+ master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
+ The module clears this field without generating a STOP signal when the
+ master loses arbitration.
+*/
+#define I2C_IBCR_MSSL BIT5
+// 0b - Receive 1b - Transmit
+#define I2C_IBCR_TXRX BIT4
+/** Data acknowledge disable
+ Values written to this field are only used when the I2C module is a receiver,
+ not a transmitter.
+ 0b - The module sends an acknowledge signal to the bus at the 9th clock bit
+ after receiving one byte of data.
+ 1b - The module does not send an acknowledge-signal response (that is,
+ acknowledge bit = 1).
+**/
+#define I2C_IBCR_NOACK BIT3
+/**Repeat START
+ If the I2C module is the current bus master, and you program RSTA=1, the I2C
+ module generates a repeated START condition. This field always reads as a 0.
+ If you attempt a repeated START at the wrong time, if the bus is owned by
+ another master the result is loss of arbitration.
+**/
+#define I2C_IBCR_RSTA BIT2
+// DMA enable
+#define I2C_IBCR_DMAEN BIT1
+
+// Transfer Complete
+#define I2C_IBSR_TCF BIT7
+// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
+#define I2C_IBSR_IBB BIT5
+// Arbitration Lost. software must clear this field by writing a one to it.
+#define I2C_IBSR_IBAL BIT4
+// I2C bus interrupt flag
+#define I2C_IBSR_IBIF BIT1
+// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
+#define I2C_IBSR_RXAK BIT0
+
+//Bus idle interrupt enable
+#define I2C_IBIC_BIIE BIT7
+
+// Glitch filter enable
+#define I2C_IBDBG_GLFLT_EN BIT3
+
+#define I2C_BUS_TEST_BUSY TRUE
+#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
+#define I2C_BUS_TEST_RX_ACK TRUE
+#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
+
+#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1]
+#define I2C_NUM_RETRIES 500
+
+typedef struct _I2C_REGS {
+ UINT8 Ibad; // I2c Bus Address Register
+ UINT8 Ibfd; // I2c Bus Frequency Dividor Register
+ UINT8 Ibcr; // I2c Bus Control Register
+ UINT8 Ibsr; // I2c Bus Status Register
+ UINT8 Ibdr; // I2C Bus Data I/O Register
+ UINT8 Ibic; // I2C Bus Interrupt Config Register
+ UINT8 Ibdbg; // I2C Bus Debug Register
+} I2C_REGS;
+
+/*
+ * sorted list of clock divisor, Ibfd register value pairs
+ */
+typedef struct _I2C_CLOCK_DIVISOR_PAIR {
+ UINT16 Divisor;
+ UINT16 Ibfd; // I2c Bus Frequency Dividor Register value
+} I2C_CLOCK_DIVISOR_PAIR;
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION Operation[2];
+} I2C_REG_REQUEST;
+
+#endif // I2C_LIB_INTERNAL_H__
+
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 764b9bb0e2d3..4a1cfb3e278e 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -1,6 +1,6 @@
# @file.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -13,6 +13,10 @@ [Defines]
[Includes]
Include

+[LibraryClasses]
+ ## @libraryclass Provides services to read/write to I2c devices
+ I2cLib|Include/Library/I2cLib.h
+
[Guids.common]
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
@@ -101,3 +105,7 @@ [PcdsFixedAtBuild.common]
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+
--
2.17.1


[PATCH] OvmfPkg/PvScsiDxe: Refactor setup of rings to separate function

Liran Alon
 

Previous to this change, PvScsiFreeRings() was not undoing all
operations that was done by PvScsiInitRings().
This is because PvScsiInitRings() was both preparing rings (Allocate
memory and map it for device DMA) and setup the rings against device by
issueing a device command. While PvScsiFreeRings() only unmaps the rings
and free their memory.

Driver do not have a functional error as it makes sure to reset device
before every call site to PvScsiFreeRings(). However, this is not
intuitive.

Therefore, prefer to refactor the setup of the ring against device to a
separate function than PvScsiInitRings().

Signed-off-by: Liran Alon <liran.alon@oracle.com>
---
OvmfPkg/PvScsiDxe/PvScsi.c | 150 +++++++++++++++++++------------------
1 file changed, 76 insertions(+), 74 deletions(-)

diff --git a/OvmfPkg/PvScsiDxe/PvScsi.c b/OvmfPkg/PvScsiDxe/PvScsi.c
index 1ca50390c0e5..5b7fdcbda10b 100644
--- a/OvmfPkg/PvScsiDxe/PvScsi.c
+++ b/OvmfPkg/PvScsiDxe/PvScsi.c
@@ -991,13 +991,6 @@ PvScsiInitRings (
)
{
EFI_STATUS Status;
- union {
- PVSCSI_CMD_DESC_SETUP_RINGS Cmd;
- UINT32 Uint32;
- } AlignedCmd;
- PVSCSI_CMD_DESC_SETUP_RINGS *Cmd;
-
- Cmd = &AlignedCmd.Cmd;

Status = PvScsiAllocateSharedPages (
Dev,
@@ -1032,6 +1025,69 @@ PvScsiInitRings (
}
ZeroMem (Dev->RingDesc.RingCmps, EFI_PAGE_SIZE);

+ return EFI_SUCCESS;
+
+FreeRingReqs:
+ PvScsiFreeSharedPages (
+ Dev,
+ 1,
+ Dev->RingDesc.RingReqs,
+ &Dev->RingDesc.RingReqsDmaDesc
+ );
+
+FreeRingState:
+ PvScsiFreeSharedPages (
+ Dev,
+ 1,
+ Dev->RingDesc.RingState,
+ &Dev->RingDesc.RingStateDmaDesc
+ );
+
+ return Status;
+}
+
+STATIC
+VOID
+PvScsiFreeRings (
+ IN OUT PVSCSI_DEV *Dev
+ )
+{
+ PvScsiFreeSharedPages (
+ Dev,
+ 1,
+ Dev->RingDesc.RingCmps,
+ &Dev->RingDesc.RingCmpsDmaDesc
+ );
+
+ PvScsiFreeSharedPages (
+ Dev,
+ 1,
+ Dev->RingDesc.RingReqs,
+ &Dev->RingDesc.RingReqsDmaDesc
+ );
+
+ PvScsiFreeSharedPages (
+ Dev,
+ 1,
+ Dev->RingDesc.RingState,
+ &Dev->RingDesc.RingStateDmaDesc
+ );
+}
+
+STATIC
+EFI_STATUS
+PvScsiSetupRings (
+ IN OUT PVSCSI_DEV *Dev
+ )
+{
+ union {
+ PVSCSI_CMD_DESC_SETUP_RINGS Cmd;
+ UINT32 Uint32;
+ } AlignedCmd;
+ PVSCSI_CMD_DESC_SETUP_RINGS *Cmd;
+
+ Cmd = &AlignedCmd.Cmd;
+
ZeroMem (Cmd, sizeof (*Cmd));
Cmd->ReqRingNumPages = 1;
Cmd->CmpRingNumPages = 1;
@@ -1052,71 +1108,12 @@ PvScsiInitRings (
sizeof (*Cmd) % sizeof (UINT32) == 0,
"Cmd must be multiple of 32-bit words"
);
- Status = PvScsiWriteCmdDesc (
- Dev,
- PvScsiCmdSetupRings,
- (UINT32 *)Cmd,
- sizeof (*Cmd) / sizeof (UINT32)
- );
- if (EFI_ERROR (Status)) {
- goto FreeRingCmps;
- }
-
- return EFI_SUCCESS;
-
-FreeRingCmps:
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingCmps,
- &Dev->RingDesc.RingCmpsDmaDesc
- );
-
-FreeRingReqs:
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingReqs,
- &Dev->RingDesc.RingReqsDmaDesc
- );
-
-FreeRingState:
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingState,
- &Dev->RingDesc.RingStateDmaDesc
- );
-
- return Status;
-}
-
-STATIC
-VOID
-PvScsiFreeRings (
- IN OUT PVSCSI_DEV *Dev
- )
-{
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingCmps,
- &Dev->RingDesc.RingCmpsDmaDesc
- );
-
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingReqs,
- &Dev->RingDesc.RingReqsDmaDesc
- );
-
- PvScsiFreeSharedPages (
- Dev,
- 1,
- Dev->RingDesc.RingState,
- &Dev->RingDesc.RingStateDmaDesc
- );
+ return PvScsiWriteCmdDesc (
+ Dev,
+ PvScsiCmdSetupRings,
+ (UINT32 *)Cmd,
+ sizeof (*Cmd) / sizeof (UINT32)
+ );
}

STATIC
@@ -1157,6 +1154,10 @@ PvScsiInit (
if (EFI_ERROR (Status)) {
goto RestorePciAttributes;
}
+ Status = PvScsiSetupRings (Dev);
+ if (EFI_ERROR (Status)) {
+ goto FreeRings;
+ }

//
// Allocate DMA communication buffer
@@ -1168,7 +1169,7 @@ PvScsiInit (
&Dev->DmaBufDmaDesc
);
if (EFI_ERROR (Status)) {
- goto FreeRings;
+ goto UnsetupRings;
}

//
@@ -1202,13 +1203,14 @@ PvScsiInit (

return EFI_SUCCESS;

-FreeRings:
+UnsetupRings:
//
// Reset device to stop device usage of the rings.
// This is required to safely free the rings.
//
PvScsiResetAdapter (Dev);

+FreeRings:
PvScsiFreeRings (Dev);

RestorePciAttributes:
--
2.20.1


[PATCH edk2-platforms 1/1] Maintainers: switch to my @arm.com email address

Ard Biesheuvel
 

I no longer work for Linaro so switch to my ARM email address.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
---
Maintainers.txt | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index 475f7d530b85..0e50b6fdf36a 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -80,7 +80,7 @@ EDK II Platforms Packages:

96Boards
F: Platform/96Boards/
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

AMD Seattle
@@ -88,24 +88,24 @@ F: Platform/AMD/OverdriveBoard/
F: Platform/LeMaker/CelloBoard/
F: Platform/SoftIron/
F: Silicon/AMD/Styx/
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

ARM
F: Platform/ARM/
-R: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+R: Ard Biesheuvel <ard.biesheuvel@arm.com>
R: Thomas Abraham <thomas.abraham@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

BeagleBoard:
F: Platform/BeagleBoard/
F: Silicon/TexasInstruments/
-R: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+R: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

Comcast
F: Platform/Comcast/
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

OptionRomPkg
@@ -116,14 +116,14 @@ M: Ray Ni <ray.ni@intel.com>
DisplayLink
F: Drivers/DisplayLink/
M: Leif Lindholm <leif@nuviainc.com>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
R: Andy Hayes <andy.hayes@displaylink.com>

HiSilicon
F: Platform/Hisilicon/
F: Silicon/Hisilicon/
M: Leif Lindholm <leif@nuviainc.com>
-R: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+R: Ard Biesheuvel <ard.biesheuvel@arm.com>

Features/Intel
F: Features/Intel/
@@ -241,7 +241,7 @@ Miscellaneous drivers
F: Silicon/Atmel/
F: Silicon/Openmoko/
F: Silicon/Synopsys/DesignWare/
-R: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+R: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

NXP platforms and silicon
@@ -253,7 +253,7 @@ R: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Raspberry Pi platforms and silicon
F: Platform/RaspberryPi/
F: Silicon/Broadcom/
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>
R: Pete Batard <pete@akeo.ie>

@@ -261,5 +261,5 @@ Socionext platforms and silicon
F: Platform/Socionext/
F: Silicon/NXP/Library/Pcf8563RealTimeClockLib/
F: Silicon/Socionext/
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+M: Ard Biesheuvel <ard.biesheuvel@arm.com>
M: Leif Lindholm <leif@nuviainc.com>
--
2.17.1


[PATCH] OvmfPkg/PvScsiDxe: Fix VS2019 build error because of implicit cast

Liran Alon
 

Sean reported that VS2019 build produce the following build error:
INFO - PvScsi.c
INFO - Generating code
INFO - d:\a\1\s\OvmfPkg\PvScsiDxe\PvScsi.c(459): error C2220: the following warning is treated as an error
INFO - d:\a\1\s\OvmfPkg\PvScsiDxe\PvScsi.c(459): warning C4244: '=': conversion from 'const UINT16' to 'UINT8', possible loss of data

This result from an implicit cast from PVSCSI Response->ScsiStatus
(Which is UINT16) to Packet->TargetResponse (Which is UINT8).

Fix this issue by adding an appropriate explicit cast and verify with
assert that this truncation do not result in loss of data.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2651
Reported-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
---
OvmfPkg/PvScsiDxe/PvScsi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/PvScsiDxe/PvScsi.c b/OvmfPkg/PvScsiDxe/PvScsi.c
index 0a66c98421a9..1ca50390c0e5 100644
--- a/OvmfPkg/PvScsiDxe/PvScsi.c
+++ b/OvmfPkg/PvScsiDxe/PvScsi.c
@@ -455,8 +455,12 @@ HandleResponse (

//
// Report target status
+ // (Strangely, PVSCSI interface defines Response->ScsiStatus as UINT16.
+ // But it should de-facto always have a value that fits UINT8. To avoid
+ // unexpected behavior, verify value is in UINT8 bounds before casting)
//
- Packet->TargetStatus = Response->ScsiStatus;
+ ASSERT (Response->ScsiStatus <= MAX_UINT8);
+ Packet->TargetStatus = (UINT8)Response->ScsiStatus;

//
// Host adapter status and function return value depend on
--
2.20.1


[PATCH] Maintainers.txt: Add Liran and Nikita as OvmfPkg/PvScsiDxe reviewers

Liran Alon
 

Laszlo suggested that as I have contributed the OvmfPkg PVSCSI driver, I
will also register myself as a reviewer in Maintainers.txt.

In addition, as Nikita have assisted the development of the PVSCSI
driver and have developed another similar OvmfPkg SCSI driver, add him
as a reviewer to PVSCSI driver as-well.

Cc: Nikita Leshenko <nikita.leshchenko@oracle.com>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
---
Maintainers.txt | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 342bb8d0850c..de443ba7ba1f 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -435,6 +435,11 @@ OvmfPkg: CSM modules
F: OvmfPkg/Csm/
R: David Woodhouse <dwmw2@infradead.org>

+OvmfPkg: PVSCSI driver
+F: OvmfPkg/PvScsiDxe
+R: Liran Alon <liran.alon@oracle.com>
+R: Nikita Leshenko <nikita.leshchenko@oracle.com>
+
PcAtChipsetPkg
F: PcAtChipsetPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
--
2.20.1


Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase

Leif Lindholm
 

On Tue, Mar 31, 2020 at 10:23:48 +0000, Pankaj Bansal (OSS) wrote:
-/*++
-
-Routine Description:
-
-
-
-Arguments:
-
- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
-
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
---*/
The above line caused me an unexpected level of excitement this
morning, as my "put back the CRs SMTP strips out" script treated the
--- as a diff separator.

Now, I *have* seen the use of /*++ --*/ elsewhere in the tree, but
this syntax is *not* described in the coding style and should not be
used. While this is a delete statement, there is an addition below
using the same format. The doxygen tags to use are /** and **/.

Fortunately, I can't spot any of these in the rest of the set.

Please send an updated version of this patch - alone if it's the only
patch that needs changes, or with a v4 if such is required.
I have not received any comments on other patches so far.
Does that mean all patches are OK (except above)?
If that is the case, then I can send only this patch after update.
If some rework is needed for other patches as well, I will send this patch along with other reworked patches in v3.
No, sorry, going through them now.
Had a lot of random interruptions.

I commented on this first because it caused an error when I was
importing the set.

/
Leif


Re: [edk2-platforms][PATCH v3 9/9] Maintainers.txt: Update Arm platform

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

From: Thomas Abraham <thomas.abraham@arm.com>

Update the reviewers list for Arm platforms.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Thanks - I'll take this as a separate patch and apply it right away.


---
Maintainers.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index a19a64fc42d0..475f7d530b85 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -94,6 +94,7 @@ M: Leif Lindholm <leif@nuviainc.com>
ARM
F: Platform/ARM/
R: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+R: Thomas Abraham <thomas.abraham@arm.com>
M: Leif Lindholm <leif@nuviainc.com>

BeagleBoard:
--
2.17.1


Re: [edk2-platforms][PATCH v3 8/9] Platform/ARM/Sgi: add initial support

Ard Biesheuvel
 

Again, please don't use duplicate patch titles in the same series.

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

For RD-Daniel Config-XLR, use multichip mode information from the SGI
platform descriptor HOB to pick the correct ACPI table to be installed.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 5 +++++
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 +
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 1 +
3 files changed, 7 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
index 7e0de765f753..b1f5714b934d 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -51,6 +51,11 @@ STATIC SGI_PLATFORM_ACPI_TABLE_GUID_LOOKUP AcpiTableGuidLookup[] = {
RD_DANIEL_CFGM_CONF_ID,
MULTI_CHIP_MODE_DISABLED,
&gRdDanielCfgMAcpiTablesFileGuid),
+ ACPI_GUID_LOOKUP (
+ RD_DANIEL_PART_NUM,
+ RD_DANIEL_CFGXLR_CONF_ID,
+ MULTI_CHIP_MODE_ENABLED,
+ &gRdDanielCfgXlrAcpiTablesFileGuid),
};

VOID
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 82569820b78c..00cbe608c219 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -35,6 +35,7 @@ [Guids]
gRdN1EdgeX2AcpiTablesFileGuid
gRdE1EdgeAcpiTablesFileGuid
gRdDanielCfgMAcpiTablesFileGuid
+ gRdDanielCfgXlrAcpiTablesFileGuid

[FeaturePcd]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index b6a427b8b657..9822858f6ea0 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -73,6 +73,7 @@
//RDDANIEL Platform Identification values
#define RD_DANIEL_PART_NUM 0x78A
#define RD_DANIEL_CFGM_CONF_ID 0x1
+#define RD_DANIEL_CFGXLR_CONF_ID 0x2

#define SGI_CONFIG_MASK 0x0F
#define SGI_CONFIG_SHIFT 0x1C
--
2.17.1


Re: [edk2-platforms][PATCH v3 7/9] Platform/ARM/SgiPkg: add ACPI tables

Ard Biesheuvel
 

Please don't use the exact same subject for different patches in the
same series.

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

RD-Daniel Config-XLR is a platform in which four identical chips are
connected via a high speed CCIX link. Add Madt and Dsdt tables for the
same.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl | 125 ++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc | 150 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf | 63 ++++++++
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc | 1 +
Platform/ARM/SgiPkg/SgiPlatform.fdf | 1 +
6 files changed, 341 insertions(+)
Please include the .DSC for this platform as well.

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl
new file mode 100644
index 000000000000..23ada55ec4a1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Dsdt.asl
@@ -0,0 +1,125 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+
+ Device (CP00) { // Zeus core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Zeus core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Zeus core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Zeus core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP04) { // Zeus core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Zeus core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Zeus core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Zeus core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP08) { // Zeus core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Zeus core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Zeus core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Zeus core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP12) { // Zeus core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Zeus core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Zeus core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Zeus core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP16) { // Zeus core 16
+ Name (_HID, "ACPI0007")
+ Name (_UID, 16)
+ Name (_STA, 0xF)
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc
new file mode 100644
index 000000000000..e3784b55f2e5
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlr/Madt.aslc
@@ -0,0 +1,150 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define CLUSTER_COUNT 4
+#define CORES_PER_CLUSTER 1
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER)
+#define CHIP_COUNT 4
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_COUNT * CHIP_COUNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_COUNT];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ //Chip 0
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 1
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 2
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+
+ // Chip 3
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ {
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(0),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(1),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(2),
+ SIZE_16MB),
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase) + SGI_REMOTE_CHIP_MEM_OFFSET(3),
+ SIZE_16MB)
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
new file mode 100644
index 000000000000..6a5f77b91f3c
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
@@ -0,0 +1,63 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdDanielCfgXlrAcpiTables
+ FILE_GUID = 42d46c2e-b6ad-4a37-bb8d-c8acc350ac2b
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ SsdtRos.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdDanielCfgXlr/Dsdt.asl
+ RdDanielCfgXlr/Madt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index a89bf26365d7..b2fc8d9b790c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@ [Guids.common]
gRdN1EdgeX2AcpiTablesFileGuid = { 0x82a34150, 0x0fc6, 0x45f4, { 0x8e, 0xa0, 0xf0, 0xa4, 0x66, 0x0c, 0xf3, 0x5d } }
gRdE1EdgeAcpiTablesFileGuid = { 0x2af40815, 0xa84e, 0x4de9, { 0x8c, 0x38, 0x91, 0x40, 0xb3, 0x54, 0x40, 0x73 } }
gRdDanielCfgMAcpiTablesFileGuid = { 0x163132b3, 0x8ec1, 0x48f7, {0xb4, 0xd1, 0x49, 0x30, 0x6c, 0x3f, 0x4d, 0x51} }
+ gRdDanielCfgXlrAcpiTablesFileGuid = { 0x42d46c2e, 0xb6ad, 0x4a37, {0xbb, 0x8d, 0xc8, 0xac, 0xc3, 0x50, 0xac, 0x2b }}

[PcdsFeatureFlag.common]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index 74fe1a4533bd..80d1bf773bda 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -257,6 +257,7 @@ [Components.common]
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
+ Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
Same point as before - if the single platform build cannot execute on
all flavours of the hardware (due to the fact that the GIC
(re)distributor) addresses are different), please split them up
properly, and don't add all ACPI tables to all platform builds.

MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

#
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf
index 48192917e22e..351c2dc9b445 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -104,6 +104,7 @@ [FV.FvMain]
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
+ INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgXlrAcpiTables.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

# Required by PCI
--
2.17.1


Re: [edk2-platforms][PATCH v3 1/9] Platform/ARM/SgiPkg: create individual

Ard Biesheuvel
 

On Tue, 31 Mar 2020 at 12:33, Ard Biesheuvel <ard.biesheuvel@arm.com> wrote:

Hello Aditya,

Could you please use a meaningful subject line for this patch?

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

In preparation for adding support for Reference Design (RD) platforms
that have different base addresses for GIC distributor or redistributor,
create individual platform description files for all SGI/RD platforms
and move GIC related base addresses from the common SGI/RD platform
description file to individual platform description files.
The existing platform description is then included by individual
platform description files.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 +---
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 3 +-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 8 ++---
Platform/ARM/SgiPkg/RdE1Edge.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/RdN1Edge.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/Sgi575.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++-
Platform/ARM/SgiPkg/SgiPlatform.dsc | 25 ++-----------
8 files changed, 124 insertions(+), 35 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e36a412155ff..d87fb2b5409f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -45,11 +45,6 @@
#define SGI_SUBSYS_GENERIC_WDOG_BASE 0x2A440000
#define SGI_SUBSYS_GENERIC_WDOG_SZ SIZE_128KB

-// Sub System Peripherals - GIC
-#define SGI_SUBSYS_GENERIC_GIC_BASE 0x30000000
-#define SGI_SUBSYS_GENERIC_GICR_BASE 0x300C0000
-#define SGI_SUBSYS_GENERIC_GIC_SZ SIZE_1MB
-
// Expansion AXI - Platform Peripherals - HDLCD1
#define SGI_EXP_PLAT_PERIPH_HDLCD1_BASE 0x7FF60000
#define SGI_EXP_PLAT_PERIPH_HDLCD1_SZ SIZE_64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index 3db70e900d61..a918afef5fba 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,7 @@ [FixedPcd]

gArmSgiTokenSpaceGuid.PcdDramBlock2Base
gArmSgiTokenSpaceGuid.PcdDramBlock2Size
+ gArmSgiTokenSpaceGuid.PcdGicSize

gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index 845aeaf4dd49..8d0ad4ec9c84 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -93,9 +93,9 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// Sub System Peripherals - GIC-600
- VirtualMemoryTable[++Index].PhysicalBase = SGI_SUBSYS_GENERIC_GIC_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_SUBSYS_GENERIC_GIC_BASE;
- VirtualMemoryTable[Index].Length = SGI_SUBSYS_GENERIC_GIC_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64(PcdGicSize);
Please use a space before '('

VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// Expansion AXI - Platform Peripherals - HDLCD1
diff --git a/Platform/ARM/SgiPkg/RdE1Edge.dsc b/Platform/ARM/SgiPkg/RdE1Edge.dsc
new file mode 100644
index 000000000000..082cbb0157f7
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdE1Edge.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = c834de39-c5b0-458b-8ea3-882427179b8a
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
If you are going to split these into separate DSCs, please do this
first in a separate patch, and update the PLATFORM_NAME accordingly.

If there is no need to use separate FDFs than you can keep using a
shared one. If there is, please do the split in the same patch.

+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
Please rename that file to use a .dsc.inc extension to make it clear
this is an include file
Actually, now that I looked more closely: is it the case that
formerly, the same build could run on any SGI platforms, but after
this change, you have separate builds for separate platforms? Because
the FDF contains all the ACPI tables for all the platforms, right?

Please consider carefully whether you really want to depart from this,
and if you do, clean up all the overlap between the platforms after
you split them into separate ones.

+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/RdN1Edge.dsc b/Platform/ARM/SgiPkg/RdN1Edge.dsc
new file mode 100644
index 000000000000..6774990ad6f6
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN1Edge.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = dbc75915-03df-4640-8f3d-3d3abf7c119b
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575.dsc
new file mode 100644
index 000000000000..3c1904c2da91
--- /dev/null
+++ b/Platform/ARM/SgiPkg/Sgi575.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = 3a6b2eae-0275-4b6e-a5d1-bd2ba1ce1fae
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 9d70ec677776..4ac3dec91e3d 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -49,5 +49,8 @@ [PcdsFixedAtBuild]
gArmSgiTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x00000008
gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x00000009

+ # GIC
+ gArmSgiTokenSpaceGuid.PcdGicSize|0|UINT64|0x0000000A
Wouldn't a UINT32 be sufficient to describe the size of a MMIO block?

+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index 5226c5751e98..4e1fcefb1442 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -1,26 +1,9 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#

-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- PLATFORM_NAME = ArmSgi
- PLATFORM_GUID = 3a6b2eae-0275-4b6e-a5d1-bd2ba1ce1fae
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x0001001B
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64|ARM
- BUILD_TARGETS = NOOPT|DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
- BUILD_NUMBER = 1
-
!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc

[BuildOptions]
@@ -93,7 +76,7 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, Libr

################################################################################
#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+# Pcd Section - list of all EDK II PCD Entries common to all SGI/RD platforms
#
################################################################################

@@ -126,10 +109,6 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000

- # GIC Base Addresses
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
-
#
# PCIe
#
--
2.17.1


Re: [edk2-platforms][PATCH v3 5/9] Platform/ARM/SgiPkg: add ACPI tables

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

Add Madt and Dsdt ACPI tables for RD-Daniel Config-M platform.
OK, it seems I was reviewing the patches out of order. The DSC you add
in the next patch should be added here.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Dsdt.asl | 118 +++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Madt.aslc | 134 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf | 63 +++++++++
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc | 1 +
Platform/ARM/SgiPkg/SgiPlatform.fdf | 1 +
6 files changed, 318 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Dsdt.asl
new file mode 100644
index 000000000000..57873ef5cfa2
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Dsdt.asl
@@ -0,0 +1,118 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2020, ARM Ltd. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ Device (CP00) { // Zeus core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Zeus core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Zeus core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Zeus core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP04) { // Zeus core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Zeus core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Zeus core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Zeus core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP08) { // Zeus core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Zeus core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Zeus core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Zeus core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP12) { // Zeus core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Zeus core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Zeus core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Zeus core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Madt.aslc
new file mode 100644
index 000000000000..3027b8d223b4
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgM/Madt.aslc
@@ -0,0 +1,134 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define CLUSTER_COUNT 16
+#define CORES_PER_CLUSTER 1
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER)
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_COUNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core8
+ 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core9
+ 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core10
+ 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core11
+ 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core12
+ 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core13
+ 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core14
+ 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core15
+ 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ SIZE_16MB),
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
new file mode 100644
index 000000000000..73b6c7ffafbb
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
@@ -0,0 +1,63 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdDanielCfgMAcpiTables
+ FILE_GUID = 163132b3-8ec1-48f7-b4d1-49306c3f4d51
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ SsdtRos.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdDanielCfgM/Dsdt.asl
+ RdDanielCfgM/Madt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 4ac3dec91e3d..a89bf26365d7 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -30,6 +30,7 @@ [Guids.common]
gRdN1EdgeAcpiTablesFileGuid = { 0x4b0b91d0, 0x4a05, 0x45c4, { 0x88, 0xa7, 0x88, 0xe1, 0x70, 0xe7, 0x66, 0x94 } }
gRdN1EdgeX2AcpiTablesFileGuid = { 0x82a34150, 0x0fc6, 0x45f4, { 0x8e, 0xa0, 0xf0, 0xa4, 0x66, 0x0c, 0xf3, 0x5d } }
gRdE1EdgeAcpiTablesFileGuid = { 0x2af40815, 0xa84e, 0x4de9, { 0x8c, 0x38, 0x91, 0x40, 0xb3, 0x54, 0x40, 0x73 } }
+ gRdDanielCfgMAcpiTablesFileGuid = { 0x163132b3, 0x8ec1, 0x48f7, {0xb4, 0xd1, 0x49, 0x30, 0x6c, 0x3f, 0x4d, 0x51} }

[PcdsFeatureFlag.common]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index 7b95acb9db46..74fe1a4533bd 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -256,6 +256,7 @@ [Components.common]
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+ Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

#
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf
index 3d13998015b9..48192917e22e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -103,6 +103,7 @@ [FV.FvMain]
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+ INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdDanielCfgMAcpiTables.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

# Required by PCI
--
2.17.1


Re: [edk2-platforms][PATCH v3 6/9] Platform/ARM/Sgi: add initial support

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

Add information in the SGI platform descriptor HOB to pick the correct
ACPI table to install for RD-Daniel Config-M
This description does not make sense. You are adding a completely new
SGI flavour called 'Daniel' in this patch, right? Please make that a
separate patch.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c | 5 +++
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 +
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 4 +++
Platform/ARM/SgiPkg/RdDaniel.dsc | 37 ++++++++++++++++++++
4 files changed, 47 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
index 387397d74598..7e0de765f753 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -46,6 +46,11 @@ STATIC SGI_PLATFORM_ACPI_TABLE_GUID_LOOKUP AcpiTableGuidLookup[] = {
RD_E1_EDGE_CONF_ID,
MULTI_CHIP_MODE_DISABLED,
&gRdE1EdgeAcpiTablesFileGuid),
+ ACPI_GUID_LOOKUP (
+ RD_DANIEL_PART_NUM,
+ RD_DANIEL_CFGM_CONF_ID,
+ MULTI_CHIP_MODE_DISABLED,
+ &gRdDanielCfgMAcpiTablesFileGuid),
};

VOID
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 741dcc75ed6a..82569820b78c 100644
--- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -34,6 +34,7 @@ [Guids]
gRdN1EdgeAcpiTablesFileGuid
gRdN1EdgeX2AcpiTablesFileGuid
gRdE1EdgeAcpiTablesFileGuid
+ gRdDanielCfgMAcpiTablesFileGuid

[FeaturePcd]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index d87fb2b5409f..b6a427b8b657 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -70,6 +70,10 @@
#define RD_N1_EDGE_CONF_ID 0x1
#define RD_E1_EDGE_CONF_ID 0x2

+//RDDANIEL Platform Identification values
+#define RD_DANIEL_PART_NUM 0x78A
+#define RD_DANIEL_CFGM_CONF_ID 0x1
+
#define SGI_CONFIG_MASK 0x0F
#define SGI_CONFIG_SHIFT 0x1C
#define SGI_PART_NUM_MASK 0xFFF
diff --git a/Platform/ARM/SgiPkg/RdDaniel.dsc b/Platform/ARM/SgiPkg/RdDaniel.dsc
new file mode 100644
index 000000000000..83e7ccd0bc05
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdDaniel.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = d301ac4e-0828-4cef-b754-34ca9b6781b5
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x30140000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x200000
--
2.17.1


Re: [edk2-platforms][PATCH v3 4/9] Platform/ARM/SgiPkg: remove

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

The number of CPUs depend on the SGI/RD platform. So instead of
depends

defining a Fixed PCD to specify the value of core and cluster count,
let each platform define these values.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>

---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 7 ++++++-
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 2 --
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 7 ++++---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 2 --
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 12 ++++++------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 2 --
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 9 +++++----
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 4 +---
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 3 ---
Platform/ARM/SgiPkg/SgiPlatform.dsc | 4 ----
10 files changed, 22 insertions(+), 30 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index 987254928535..a9540f2e0374 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -14,12 +14,17 @@
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

+#define CLUSTER_COUNT 2
+#define CORES_PER_CLUSTER 8
+#define THREADS_PER_CORE 2
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER * THREADS_PER_CORE)
+
// Multiple APIC Description Table
#pragma pack (1)

typedef struct {
EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[32];
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_COUNT];
EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index b08d7c2df5c7..742ca9e68335 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -34,8 +34,6 @@ [Packages]
Platform/ARM/SgiPkg/SgiPlatform.dec

[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmPlatformTokenSpaceGuid.PcdClusterCount
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PL011UartInterrupt

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..d8ec0ce421dc 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -14,15 +14,16 @@
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

-#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
- FixedPcdGet32 (PcdCoreCount))
+#define CLUSTER_COUNT 2
+#define CORES_PER_CLUSTER 4
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER)

// Multiple APIC Description Table
#pragma pack (1)

typedef struct {
EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_COUNT];
EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 61b07bffccf3..206479f9428e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -34,8 +34,6 @@ [Packages]
Platform/ARM/SgiPkg/SgiPlatform.dec

[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmPlatformTokenSpaceGuid.PcdClusterCount
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PL011UartInterrupt

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
index 47368931e367..add972437496 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
@@ -14,19 +14,19 @@
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

-#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
- FixedPcdGet32 (PcdCoreCount))
-
-#define CHIP_CNT 2
+#define CLUSTER_COUNT 2
+#define CORES_PER_CLUSTER 4
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER)
+#define CHIP_COUNT 2

// Multiple APIC Description Table
#pragma pack (1)

typedef struct {
EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT * CHIP_CNT];
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_COUNT * CHIP_COUNT];
EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_CNT];
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[CHIP_COUNT];
} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;

#pragma pack ()
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index a4d5904f671c..8aec5e094e1a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -34,8 +34,6 @@ [Packages]
Platform/ARM/SgiPkg/SgiPlatform.dec

[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmPlatformTokenSpaceGuid.PcdClusterCount
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PL011UartInterrupt

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index dedabaaecdf4..ca259247785f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,7 +1,7 @@
/** @file
* Multiple APIC Description Table (MADT)
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -14,8 +14,9 @@
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

-#define CORES (FixedPcdGet32 (PcdClusterCount) * \
- FixedPcdGet32 (PcdCoreCount))
+#define CLUSTER_COUNT 2
+#define CORES_PER_CLUSTER 4
+#define CORE_COUNT (CLUSTER_COUNT * CORES_PER_CLUSTER)

// EFI_ACPI_6_1_GIC_STRUCTURE
#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
@@ -90,7 +91,7 @@

typedef struct {
EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORES];
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORE_COUNT];
EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
EFI_ACPI_6_1_GICR_STRUCTURE GicRedistributor;
EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicIts;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index 097ef854df42..df390c152648 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -33,8 +33,6 @@ [Packages]
Platform/ARM/SgiPkg/SgiPlatform.dec

[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdCoreCount
- gArmPlatformTokenSpaceGuid.PcdClusterCount
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PL011UartInterrupt

diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index a918afef5fba..fe96f5385d57 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -37,9 +37,6 @@ [Sources.AARCH64]
AArch64/Helper.S | GCC

[FixedPcd]
- gArmPlatformTokenSpaceGuid.PcdClusterCount
- gArmPlatformTokenSpaceGuid.PcdCoreCount
-
gArmSgiTokenSpaceGuid.PcdDramBlock2Base
gArmSgiTokenSpaceGuid.PcdDramBlock2Size
gArmSgiTokenSpaceGuid.PcdGicSize
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index 4e1fcefb1442..7b95acb9db46 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -156,10 +156,6 @@ [PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000

- # ARM Cores and Clusters
- gArmPlatformTokenSpaceGuid.PcdCoreCount|4
- gArmPlatformTokenSpaceGuid.PcdClusterCount|2
-
# Virtio Disk
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1c130000
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000
--
2.17.1


Re: [edk2-platforms][PATCH v3 3/9] Platform/ARM/SgiPkg: move common

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

Move common platform description entries in platfrom specific DSDT to
platform

a SSDT that can be reused on all SGI/RD platforms.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>

---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Dsdt.asl | 70 +-------------------
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 69 +------------------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/{RdN1Edge/Dsdt.asl => SsdtRos.asl} | 67 ++++---------------
6 files changed, 19 insertions(+), 194 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Dsdt.asl
index 5583e610973b..d66c7cbf4183 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Dsdt.asl
@@ -1,7 +1,7 @@
/** @file
* Differentiated System Description Table Fields (DSDT)
*
-* Copyright (c) 2018, ARM Ltd. All rights reserved.
+* Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -208,73 +208,5 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
Name (_STA, 0xF)
}

- // UART PL011
- Device (COM0) {
- Name (_HID, "ARMH0011")
- Name (_CID, "ARMH0011")
- Name (_UID, Zero)
- Name (_STA, 0xF)
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (
- ReadWrite,
- FixedPcdGet64 (PcdSerialDbgRegisterBase),
- 0x1000
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 }
- })
- }
-
- // SMSC 91C111
- Device (ETH0) {
- Name (_HID, "LNRO0003")
- Name (_UID, Zero)
- Name (_STA, 0xF)
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (ReadWrite, 0x18000000, 0x1000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 111 }
- })
- Name (_DSD, Package() {
- ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package () {
- Package (2) {"reg-io-width", 4 },
- }
- })
- }
-
- // VIRTIO DISK
- Device (VR00) {
- Name (_HID, "LNRO0005")
- Name (_UID, 0)
- Name (_CCA, 1) // mark the device coherent
-
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (
- ReadWrite,
- FixedPcdGet32 (PcdVirtioBlkBaseAddress),
- FixedPcdGet32 (PcdVirtioBlkSize)
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
- FixedPcdGet32 (PcdVirtioBlkInterrupt)
- }
- })
- }
-
- // VIRTIO NET
- Device (VR01) {
- Name (_HID, "LNRO0005")
- Name (_UID, 1)
- Name (_CCA, 1) // mark the device coherent
-
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (
- ReadWrite,
- FixedPcdGet32 (PcdVirtioNetBaseAddress),
- FixedPcdGet32 (PcdVirtioNetSize)
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
- FixedPcdGet32 (PcdVirtioNetInterrupt)
- }
- })
- }
} // Scope(_SB)
}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 3a4d4e7b9502..b08d7c2df5c7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,6 +16,7 @@ [Defines]

[Sources]
Dbg2.aslc
+ SsdtRos.asl
Fadt.aslc
Gtdt.aslc
Iort.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index 45316d5005f4..cb05eed35878 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -1,7 +1,7 @@
/** @file
* Differentiated System Description Table Fields (DSDT)
*
-* Copyright (c) 2018, ARM Ltd. All rights reserved.
+* Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -62,72 +62,5 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
Name (_STA, 0xF)
}

- // UART PL011
- Device (COM0) {
- Name (_HID, "ARMH0011")
- Name (_CID, "ARMH0011")
- Name (_UID, Zero)
- Name (_STA, 0xF)
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (
- ReadWrite,
- FixedPcdGet64 (PcdSerialDbgRegisterBase),
- 0x1000
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 }
- })
- }
-
- // SMSC 91C111
- Device (ETH0) {
- Name (_HID, "LNRO0003")
- Name (_UID, Zero)
- Name (_STA, 0xF)
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0x18000000, 0x1000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 111 }
- })
- Name (_DSD, Package() {
- ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
- Package() {
- Package(2) {"reg-io-width", 4 },
- }
- })
- }
-
- // VIRTIO DISK
- Device (VR00) {
- Name (_HID, "LNRO0005")
- Name (_UID, 0)
- Name (_CCA, 1) // mark the device coherent
-
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (
- ReadWrite,
- FixedPcdGet32 (PcdVirtioBlkBaseAddress),
- FixedPcdGet32 (PcdVirtioBlkSize)
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
- FixedPcdGet32 (PcdVirtioBlkInterrupt)
- }
- })
- }
-
- // VIRTIO NET
- Device (VR01) {
- Name (_HID, "LNRO0005")
- Name (_UID, 1)
- Name (_CCA, 1) // mark the device coherent
-
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (ReadWrite,
- FixedPcdGet32 (PcdVirtioNetBaseAddress),
- FixedPcdGet32 (PcdVirtioNetSize)
- )
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
- FixedPcdGet32 (PcdVirtioNetInterrupt)
- }
- })
- }
} // Scope(_SB)
}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 58c33ecb8ec2..61b07bffccf3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,6 +16,7 @@ [Defines]

[Sources]
Dbg2.aslc
+ SsdtRos.asl
Fadt.aslc
Gtdt.aslc
Iort.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 1b584b152455..a4d5904f671c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -16,6 +16,7 @@ [Defines]

[Sources]
Dbg2.aslc
+ SsdtRos.asl
Fadt.aslc
Gtdt.aslc
Iort.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
similarity index 57%
copy from Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
copy to Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
index 45316d5005f4..95ae23c1f547 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
@@ -1,67 +1,24 @@
/** @file
-* Differentiated System Description Table Fields (DSDT)
+* Secondary System Description Table Fields (SSDT)
*
-* Copyright (c) 2018, ARM Ltd. All rights reserved.
+* Copyright (c) 2020, ARM Ltd. All rights reserved.
*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/

#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"

-DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
+DefinitionBlock ("SsdtRosTable.aml", "SSDT", 1, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
-
- Device (CP00) { // Neoverse-N1: Cluster 0, Cpu 0
- Name (_HID, "ACPI0007")
- Name (_UID, 0)
- Name (_STA, 0xF)
- }
-
- Device (CP01) { // Neoverse-N1: Cluster 0, Cpu 1
- Name (_HID, "ACPI0007")
- Name (_UID, 1)
- Name (_STA, 0xF)
- }
-
- Device (CP02) { // Neoverse-N1: Cluster 0, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 2)
- Name (_STA, 0xF)
- }
-
- Device (CP03) { // Neoverse-N1: Cluster 0, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 3)
- Name (_STA, 0xF)
- }
-
- Device (CP04) { // Neoverse-N1: Cluster 1, Cpu 0
- Name (_HID, "ACPI0007")
- Name (_UID, 4)
- Name (_STA, 0xF)
- }
-
- Device (CP05) { // Neoverse-N1: Cluster 1, Cpu 1
- Name (_HID, "ACPI0007")
- Name (_UID, 5)
- Name (_STA, 0xF)
- }
-
- Device (CP06) { // Neoverse-N1: Cluster 1, Cpu 2
- Name (_HID, "ACPI0007")
- Name (_UID, 6)
- Name (_STA, 0xF)
- }
-
- Device (CP07) { // Neoverse-N1: Cluster 1, Cpu 3
- Name (_HID, "ACPI0007")
- Name (_UID, 7)
- Name (_STA, 0xF)
- }
-
// UART PL011
Device (COM0) {
Name (_HID, "ARMH0011")
@@ -73,7 +30,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
ReadWrite,
FixedPcdGet64 (PcdSerialDbgRegisterBase),
0x1000
- )
+ )
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 }
})
}
@@ -129,5 +86,5 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
}
})
}
- } // Scope(_SB)
+ }
}
--
2.17.1


Re: [edk2-platforms][PATCH v3 2/9] Platform/ARM/SgiPkg: move the GIC

Ard Biesheuvel
 

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

Move the ACPI helper macros defines related to GIC structure,
distributor, redistributor and ITS to SgiAcpiHeader.h as these are
common across ARM SGI/RD platforms.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>

---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 68 +------------------
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 68 +------------------
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 57 +---------------
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 70 +++++++++++++++++++-
4 files changed, 72 insertions(+), 191 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index 48e7a61478e8..987254928535 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,7 +1,7 @@
/** @file
* Multiple APIC Description Table (MADT)
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -14,72 +14,6 @@
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>

-// EFI_ACPI_6_2_GIC_STRUCTURE
-#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
- PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
- { \
- EFI_ACPI_6_2_GIC, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- GicId, /* CPUInterfaceNumber */ \
- AcpiCpuUid, /* AcpiProcessorUid */ \
- Flags, /* Flags */ \
- 0, /* ParkingProtocolVersion */ \
- PmuIrq, /* PerformanceInterruptGsiv */ \
- 0, /* ParkedAddress */ \
- GicBase, /* PhysicalBaseAddress */ \
- GicVBase, /* GICV */ \
- GicHBase, /* GICH */ \
- GsivId, /* VGICMaintenanceInterrupt */ \
- GicRBase, /* GICRBaseAddress */ \
- Mpidr, /* MPIDR */ \
- Efficiency, /* ProcessorPowerEfficiencyClass */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
- GicDistVector, GicVersion) \
- { \
- EFI_ACPI_6_2_GICD, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
- EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
- GicDistHwId, /* GicId */ \
- GicDistBase, /* PhysicalBaseAddress */ \
- GicDistVector, /* SystemVectorBase */ \
- GicVersion, /* GicVersion */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GICR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
- { \
- EFI_ACPI_6_2_GICR, /* Type */ \
- sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
- RedisDiscLength /* DiscoveryRangeLength */ \
- }
-
-// EFI_ACPI_6_2_GIC_ITS_STRUCTURE
-#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) \
- { \
- EFI_ACPI_6_2_GIC_ITS, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- GicItsId, /* GicItsId */ \
- GicItsBase, /* PhysicalBaseAddress */ \
- EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \
- }
-
// Multiple APIC Description Table
#pragma pack (1)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 6312743a479c..05eb78c5616a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,7 +1,7 @@
/** @file
* Multiple APIC Description Table (MADT)
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -17,72 +17,6 @@
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))

-// EFI_ACPI_6_2_GIC_STRUCTURE
-#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
- PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
- { \
- EFI_ACPI_6_2_GIC, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- GicId, /* CPUInterfaceNumber */ \
- AcpiCpuUid, /* AcpiProcessorUid */ \
- Flags, /* Flags */ \
- 0, /* ParkingProtocolVersion */ \
- PmuIrq, /* PerformanceInterruptGsiv */ \
- 0, /* ParkedAddress */ \
- GicBase, /* PhysicalBaseAddress */ \
- GicVBase, /* GICV */ \
- GicHBase, /* GICH */ \
- GsivId, /* VGICMaintenanceInterrupt */ \
- GicRBase, /* GICRBaseAddress */ \
- Mpidr, /* MPIDR */ \
- Efficiency, /* ProcessorPowerEfficiencyClass */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
- GicDistVector, GicVersion) \
- { \
- EFI_ACPI_6_2_GICD, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
- EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
- GicDistHwId, /* GicId */ \
- GicDistBase, /* PhysicalBaseAddress */ \
- GicDistVector, /* SystemVectorBase */ \
- GicVersion, /* GicVersion */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GICR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
- { \
- EFI_ACPI_6_2_GICR, /* Type */ \
- sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
- RedisDiscLength /* DiscoveryRangeLength */ \
- }
-
-// EFI_ACPI_6_2_GIC_ITS_STRUCTURE
-#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) \
- { \
- EFI_ACPI_6_2_GIC_ITS, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- GicItsId, /* GicItsId */ \
- GicItsBase, /* PhysicalBaseAddress */ \
- EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \
- }
-
// Multiple APIC Description Table
#pragma pack (1)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
index d4538233d760..47368931e367 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc
@@ -1,7 +1,7 @@
/** @file
* Multiple APIC Description Table (MADT)
*
-* Copyright (c) 2019, ARM Limited. All rights reserved.
+* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -19,61 +19,6 @@

#define CHIP_CNT 2

-// EFI_ACPI_6_2_GIC_STRUCTURE
-#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
- PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
- { \
- EFI_ACPI_6_2_GIC, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- GicId, /* CPUInterfaceNumber */ \
- AcpiCpuUid, /* AcpiProcessorUid */ \
- Flags, /* Flags */ \
- 0, /* ParkingProtocolVersion */ \
- PmuIrq, /* PerformanceInterruptGsiv */ \
- 0, /* ParkedAddress */ \
- GicBase, /* PhysicalBaseAddress */ \
- GicVBase, /* GICV */ \
- GicHBase, /* GICH */ \
- GsivId, /* VGICMaintenanceInterrupt */ \
- GicRBase, /* GICRBaseAddress */ \
- Mpidr, /* MPIDR */ \
- Efficiency, /* ProcessorPowerEfficiencyClass */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
- GicDistVector, GicVersion) \
- { \
- EFI_ACPI_6_2_GICD, /* Type */ \
- sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
- EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
- GicDistHwId, /* GicId */ \
- GicDistBase, /* PhysicalBaseAddress */ \
- GicDistVector, /* SystemVectorBase */ \
- GicVersion, /* GicVersion */ \
- { \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
- EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
- EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
- } \
- }
-
-// EFI_ACPI_6_2_GICR_STRUCTURE
-#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
- { \
- EFI_ACPI_6_2_GICR, /* Type */ \
- sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
- EFI_ACPI_RESERVED_WORD, /* Reserved */ \
- RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
- RedisDiscLength /* DiscoveryRangeLength */ \
- }
-
// Multiple APIC Description Table
#pragma pack (1)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 5083dde15dd5..ecb0d4eccf24 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -9,6 +9,8 @@
#ifndef __SGI_ACPI_HEADER__
#define __SGI_ACPI_HEADER__

+#include <IndustryStandard/Acpi.h>
+
//
// ACPI table information used to initialize tables.
//
@@ -32,4 +34,70 @@
EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
}

+// EFI_ACPI_6_2_GIC_STRUCTURE
+#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \
+ PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \
+ { \
+ EFI_ACPI_6_2_GIC, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ GicId, /* CPUInterfaceNumber */ \
+ AcpiCpuUid, /* AcpiProcessorUid */ \
+ Flags, /* Flags */ \
+ 0, /* ParkingProtocolVersion */ \
+ PmuIrq, /* PerformanceInterruptGsiv */ \
+ 0, /* ParkedAddress */ \
+ GicBase, /* PhysicalBaseAddress */ \
+ GicVBase, /* GICV */ \
+ GicHBase, /* GICH */ \
+ GsivId, /* VGICMaintenanceInterrupt */ \
+ GicRBase, /* GICRBaseAddress */ \
+ Mpidr, /* MPIDR */ \
+ Efficiency, /* ProcessorPowerEfficiencyClass */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
+ EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
+ } \
+ }
+
+// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE
+#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \
+ GicDistVector, GicVersion) \
+ { \
+ EFI_ACPI_6_2_GICD, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \
+ EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \
+ GicDistHwId, /* GicId */ \
+ GicDistBase, /* PhysicalBaseAddress */ \
+ GicDistVector, /* SystemVectorBase */ \
+ GicVersion, /* GicVersion */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \
+ EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \
+ EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \
+ } \
+ }
+
+// EFI_ACPI_6_2_GICR_STRUCTURE
+#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \
+ { \
+ EFI_ACPI_6_2_GICR, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \
+ RedisDiscLength /* DiscoveryRangeLength */ \
+ }
+
+// EFI_ACPI_6_2_GIC_ITS_STRUCTURE
+#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) \
+ { \
+ EFI_ACPI_6_2_GIC_ITS, /* Type */ \
+ sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), \
+ EFI_ACPI_RESERVED_WORD, /* Reserved */ \
+ GicItsId, /* GicItsId */ \
+ GicItsBase, /* PhysicalBaseAddress */ \
+ EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1


Re: [edk2-platforms][PATCH v3 1/9] Platform/ARM/SgiPkg: create individual

Ard Biesheuvel
 

Hello Aditya,

Could you please use a meaningful subject line for this patch?

On Wed, 25 Mar 2020 at 11:53, Aditya Angadi <aditya.angadi@arm.com> wrote:

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

In preparation for adding support for Reference Design (RD) platforms
that have different base addresses for GIC distributor or redistributor,
create individual platform description files for all SGI/RD platforms
and move GIC related base addresses from the common SGI/RD platform
description file to individual platform description files.
The existing platform description is then included by individual
platform description files.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 +---
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 3 +-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 8 ++---
Platform/ARM/SgiPkg/RdE1Edge.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/RdN1Edge.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/Sgi575.dsc | 37 ++++++++++++++++++++
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++-
Platform/ARM/SgiPkg/SgiPlatform.dsc | 25 ++-----------
8 files changed, 124 insertions(+), 35 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e36a412155ff..d87fb2b5409f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -45,11 +45,6 @@
#define SGI_SUBSYS_GENERIC_WDOG_BASE 0x2A440000
#define SGI_SUBSYS_GENERIC_WDOG_SZ SIZE_128KB

-// Sub System Peripherals - GIC
-#define SGI_SUBSYS_GENERIC_GIC_BASE 0x30000000
-#define SGI_SUBSYS_GENERIC_GICR_BASE 0x300C0000
-#define SGI_SUBSYS_GENERIC_GIC_SZ SIZE_1MB
-
// Expansion AXI - Platform Peripherals - HDLCD1
#define SGI_EXP_PLAT_PERIPH_HDLCD1_BASE 0x7FF60000
#define SGI_EXP_PLAT_PERIPH_HDLCD1_SZ SIZE_64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index 3db70e900d61..a918afef5fba 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,7 @@ [FixedPcd]

gArmSgiTokenSpaceGuid.PcdDramBlock2Base
gArmSgiTokenSpaceGuid.PcdDramBlock2Size
+ gArmSgiTokenSpaceGuid.PcdGicSize

gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index 845aeaf4dd49..8d0ad4ec9c84 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -93,9 +93,9 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// Sub System Peripherals - GIC-600
- VirtualMemoryTable[++Index].PhysicalBase = SGI_SUBSYS_GENERIC_GIC_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_SUBSYS_GENERIC_GIC_BASE;
- VirtualMemoryTable[Index].Length = SGI_SUBSYS_GENERIC_GIC_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64(PcdGicSize);
Please use a space before '('

VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// Expansion AXI - Platform Peripherals - HDLCD1
diff --git a/Platform/ARM/SgiPkg/RdE1Edge.dsc b/Platform/ARM/SgiPkg/RdE1Edge.dsc
new file mode 100644
index 000000000000..082cbb0157f7
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdE1Edge.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = c834de39-c5b0-458b-8ea3-882427179b8a
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
If you are going to split these into separate DSCs, please do this
first in a separate patch, and update the PLATFORM_NAME accordingly.

If there is no need to use separate FDFs than you can keep using a
shared one. If there is, please do the split in the same patch.

+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
Please rename that file to use a .dsc.inc extension to make it clear
this is an include file

+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/RdN1Edge.dsc b/Platform/ARM/SgiPkg/RdN1Edge.dsc
new file mode 100644
index 000000000000..6774990ad6f6
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdN1Edge.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = dbc75915-03df-4640-8f3d-3d3abf7c119b
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575.dsc
new file mode 100644
index 000000000000..3c1904c2da91
--- /dev/null
+++ b/Platform/ARM/SgiPkg/Sgi575.dsc
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmSgi
+ PLATFORM_GUID = 3a6b2eae-0275-4b6e-a5d1-bd2ba1ce1fae
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = NOOPT|DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
+ BUILD_NUMBER = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ # GIC Base Addresses
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
+ gArmSgiTokenSpaceGuid.PcdGicSize|0x100000
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 9d70ec677776..4ac3dec91e3d 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -49,5 +49,8 @@ [PcdsFixedAtBuild]
gArmSgiTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x00000008
gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x00000009

+ # GIC
+ gArmSgiTokenSpaceGuid.PcdGicSize|0|UINT64|0x0000000A
Wouldn't a UINT32 be sufficient to describe the size of a MMIO block?

+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc
index 5226c5751e98..4e1fcefb1442 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc
@@ -1,26 +1,9 @@
#
-# Copyright (c) 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#

-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- PLATFORM_NAME = ArmSgi
- PLATFORM_GUID = 3a6b2eae-0275-4b6e-a5d1-bd2ba1ce1fae
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x0001001B
- OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
- SUPPORTED_ARCHITECTURES = AARCH64|ARM
- BUILD_TARGETS = NOOPT|DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf
- BUILD_NUMBER = 1
-
!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc

[BuildOptions]
@@ -93,7 +76,7 @@ [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, Libr

################################################################################
#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+# Pcd Section - list of all EDK II PCD Entries common to all SGI/RD platforms
#
################################################################################

@@ -126,10 +109,6 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000

- # GIC Base Addresses
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x30000000
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
-
#
# PCIe
#
--
2.17.1


Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase

Pankaj Bansal
 

-----Original Message-----
From: Leif Lindholm <leif@nuviainc.com>
Sent: Monday, March 30, 2020 5:49 PM
To: Pankaj Bansal (OSS) <pankaj.bansal@oss.nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
<michael.d.kinney@intel.com>; devel@edk2.groups.io; Varun Sethi
<V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
Mahmoud@arm.com>; Jon Nettleton <jon@solid-run.com>
Subject: Re: [PATCH v2 28/28] Platform/NXP/LS1043aRdbPkg: Add PEI Phase

On Fri, Mar 20, 2020 at 20:05:43 +0530, Pankaj Bansal wrote:
From: Pankaj Bansal <pankaj.bansal@nxp.com>

Add PEI phase to LS1043aRdb. This is needed becuase we need to have
dynamic PCDs support to be able to reserve memory before reporting
memory to UEFI fimrware.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 9 ---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 18 +++--
.../MemoryInitPeiLib/MemoryInitPeiLib.c | 77 ++++++++++---------
.../MemoryInitPeiLib/MemoryInitPeiLib.inf | 3 +-
Silicon/NXP/NxpQoriqLs.dsc.inc | 59 ++++++++++----
5 files changed, 99 insertions(+), 67 deletions(-)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index d486c9b36fab..d45fd67c03b5 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -30,15 +30,6 @@ [LibraryClasses.common]
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

[PcdsFixedAtBuild.common]
-
- #
- # LS1043a board Specific PCDs
- # XX (DRAM - Region 1 2GB)
- # (NOR - IFC Region 1 512MB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
-
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
-
#
# RTC Pcds
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 99fbc87e1200..931d0bb14f9b 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -24,10 +24,10 @@

[FD.LS1043ARDB_EFI]
BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The
base address of the FLASH Device.
-Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in
bytes of the FLASH Device
+Size = 0x00140000|gArmTokenSpaceGuid.PcdFdSize #The size in
bytes of the FLASH Device
ErasePolarity = 1
-BlockSize = 0x1
-NumBlocks = 0xED000
+BlockSize = 0x40000
+NumBlocks = 0x5

#################################################################
###############
#
@@ -44,7 +44,7 @@ [FD.LS1043ARDB_EFI]
# RegionType <FV, DATA, or FILE>
#
#################################################################
###############
-0x00000000|0x000ED000
+0x00000000|0x00140000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT

@@ -159,7 +159,15 @@ [FV.FVMAIN_COMPACT]
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE

- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF
MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
PROCESSING_REQUIRED = TRUE {
diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index 54d026ef1270..7fdf9cb77a6e 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -46,30 +46,12 @@ InitMmu (
}
}

-/*++
-
-Routine Description:
-
-
-
-Arguments:
-
- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
-
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
---*/
The above line caused me an unexpected level of excitement this
morning, as my "put back the CRs SMTP strips out" script treated the
--- as a diff separator.

Now, I *have* seen the use of /*++ --*/ elsewhere in the tree, but
this syntax is *not* described in the coding style and should not be
used. While this is a delete statement, there is an addition below
using the same format. The doxygen tags to use are /** and **/.

Fortunately, I can't spot any of these in the rest of the set.

Please send an updated version of this patch - alone if it's the only
patch that needs changes, or with a v4 if such is required.
I have not received any comments on other patches so far.
Does that mean all patches are OK (except above)?
If that is the case, then I can send only this patch after update.
If some rework is needed for other patches as well, I will send this patch along with other reworked patches in v3.


EFI_STATUS
EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+MemoryInitPeiLibConstructor (
+ VOID
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
ARM_SMC_ARGS ArmSmcArgs;
INT32 Index;
UINTN DramSize;
@@ -82,18 +64,6 @@ MemoryPeim (
UINTN FdTop;
BOOLEAN FoundSystemMem;

- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- //
- // Ensure MemoryTable[0].Length which is size of DRAM has been set
- // by ArmPlatformGetVirtualMemoryMap ()
- //
- ASSERT (MemoryTable[0].Length != 0);
-
- //
- // Now, the permanent memory has been installed, we can call
AllocatePages()
- //
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
@@ -133,8 +103,8 @@ MemoryPeim (

ASSERT (!DramSize);

- FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
- FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);

// Declare memory regios to system
for (Index = MAX_DRAM_REGIONS - 1; Index >= 0; Index--) {
@@ -178,8 +148,8 @@ MemoryPeim (
);
};
// Mark the memory covering the Firmware Device as boot services data
- BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
- FixedPcdGet32 (PcdFdSize),
+ BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize),
EfiBootServicesData);
} else {
BuildResourceDescriptorHob (
@@ -199,16 +169,49 @@ MemoryPeim (
Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;

if (FdBase >= BaseAddress && FdTop <= Top) {
- Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ Size -= (UINTN)PcdGet32 (PcdFdSize);
}

if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
FoundSystemMem = TRUE;
+ PcdSet64S (PcdSystemMemoryBase, BaseAddress);
+ PcdSet64S (PcdSystemMemorySize, Size);
}
}

ASSERT (FoundSystemMem);

+ return EFI_SUCCESS;
+}
+
+/*++
Here is the incorrect addition.

(I'm not reviewing the set backwards, this was just the only patch
that wouldn't apply cleanly after conversion.)

/
Leif

+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);

diff --git a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index ad2371115b17..a33f8cd3f743 100644
--- a/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -13,7 +13,8 @@ [Defines]
FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+ LIBRARY_CLASS = MemoryInitPeiLib|PEIM
+ CONSTRUCTOR = MemoryInitPeiLibConstructor

[Sources]
MemoryInitPeiLib.c
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index b2b10ce28a93..a3f18abb37b1 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,6 +93,7 @@ [LibraryClasses.common]
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl
eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRep
ortStatusCodeLib.inf
+
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
ressLib.inf

I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetS
ystemLib.inf
@@ -106,20 +107,24 @@ [LibraryClasses.common]

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
ressLib.inf
-
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/P
rePiExtractGuidedSectionLib.inf
-
LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/Lzma
CustomDecompressLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
-
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiH
obListPointerLib.inf
-
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiM
emoryAllocationLib.inf
+
DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymb
olsBaseLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
cesTablePointerLib.inf
+
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
cationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
cationLib.inf
+
PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
.inf
+
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtrac
tGuidedSectionLib.inf
+
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepo
rtStatusCodeLib.inf
+
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/
OemHookStatusCodeLibNull.inf

- # 1/123 faster than Stm or Vstm version
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
-
- # Uncomment to turn on GDB stub in SEC.
-
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
cesTablePointerLib.inf

[LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -128,14 +133,16 @@ [LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServi
cesTablePointerLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllo
cationLib.inf
+
PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib
.inf
+
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtrac
tGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepo
rtStatusCodeLib.inf
+
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/
OemHookStatusCodeLibNull.inf

[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/D
xeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtra
ctGuidedSectionLib.inf
-
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecomp
ressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerf
ormanceLib.inf

@@ -207,6 +214,9 @@ [PcdsDynamicDefault.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480

+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0
+
[PcdsDynamicHii.common.DEFAULT]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV
ariableGuid|0x0|10

@@ -227,6 +237,12 @@ [PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320

+ ## Base of DRAM
+ ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this
space
+ ## for temporary ram
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
@@ -284,13 +300,26 @@ [PcdsFixedAtBuild.common]
#################################################################
###############
[Components.common]
#
- # SEC
+ # PEI Phase modules
#
- ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+
+ MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecom
pressLib.inf
+ }

#
# DXE
--
2.17.1