Date   

[PATCH] UnitTestFrameworkPkg/UnitTestLib: Correct dereferred pointer.

Guomin Jiang
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2609

The copied pointer (SavedState) will be updated by LoadUnitTestCache
call. But the change of SavedState will not update source pointer, which
is NewFramework->SavedState in this case.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Guomin Jiang <guomin.jiang@intel.com>
---
UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.c b/UnitT=
estFrameworkPkg/Library/UnitTestLib/UnitTestLib.c
index b136992d99..71050b5618 100644
--- a/UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.c
+++ b/UnitTestFrameworkPkg/Library/UnitTestLib/UnitTestLib.c
@@ -209,7 +209,7 @@ InitUnitTestFramework (
EFI_STATUS Status;=0D
UNIT_TEST_FRAMEWORK_HANDLE NewFrameworkHandle;=0D
UNIT_TEST_FRAMEWORK *NewFramework;=0D
- UNIT_TEST_SAVE_HEADER *SavedState;=0D
+ UNIT_TEST_SAVE_HEADER **SavedState;=0D
=0D
Status =3D EFI_SUCCESS;=0D
NewFramework =3D NULL;=0D
@@ -264,8 +264,8 @@ InitUnitTestFramework (
// If there is a persisted context, load it now.=0D
//=0D
if (DoesCacheExist (NewFrameworkHandle)) {=0D
- SavedState =3D (UNIT_TEST_SAVE_HEADER *)NewFramework->SavedState;=0D
- Status =3D LoadUnitTestCache (NewFrameworkHandle, &SavedState);=0D
+ SavedState =3D (UNIT_TEST_SAVE_HEADER **)(&NewFramework->SavedState);=
=0D
+ Status =3D LoadUnitTestCache (NewFrameworkHandle, SavedState);=0D
if (EFI_ERROR (Status)) {=0D
//=0D
// Don't actually report it as an error, but emit a warning.=0D
--=20
2.25.1.windows.1


Re: [PATCH] .azurepipelines: Enable CI for OvmfPkg and EmulatorPkg

Ard Biesheuvel
 

On Tue, 31 Mar 2020 at 08:31, Sean via Groups.Io
<sean.brogan=microsoft.com@groups.io> wrote:

@Ard -
pflash change: https://github.com/spbrogan/edk2/pull/12

Logging change - I actually switched OVMF to use stdio since the log is captured either way and now it shows up in the web log output. https://github.com/spbrogan/edk2/pull/13
Even better.

Do you have instructions for the cmdline for Qemu for Arm? Is it something you would like to run?
Not sure I follow. Which command line are we talking about?

All the builds can be seen here or clicking the icon in github:
https://dev.azure.com/tianocore/edk2-ci-play/_build?view=folders&treeState=XEFybVZpcnRQa2ckXEVtdWxhdG9yUGtnJFxPVk1G
Thanks again for the effort. This is going to help tremendously.


Re: [PATCH] .azurepipelines: Enable CI for OvmfPkg and EmulatorPkg

Sean
 

@Ard - 
pflash change: https://github.com/spbrogan/edk2/pull/12

Logging change - I actually switched OVMF to use stdio since the log is captured either way and now it shows up in the web log output.  https://github.com/spbrogan/edk2/pull/13 

Do you have instructions for the cmdline for Qemu for Arm?  Is it something you would like to run?  

All the builds can be seen here or clicking the icon in github: 
https://dev.azure.com/tianocore/edk2-ci-play/_build?view=folders&treeState=XEFybVZpcnRQa2ckXEVtdWxhdG9yUGtnJFxPVk1G


Re: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Liming Gao
 

EDKII DEC spec https://github.com/tianocore-docs/edk2-DecSpecification/tree/release/1.27/2_dec_file_overview

DEC File Overview

An EDK II Package (directory) is a directory that contains an EDK II package declaration (DEC) file. Only one DEC file is permitted per directory. EDK II Packages cannot be nested within other EDK II Packages.

Thanks
Liming

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: 2020年3月31日 13:03
To: Gao, Liming <liming.gao@intel.com>; Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Liming,
Where can I find the rule?

Thanks,
Ray

-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Tuesday, March 31, 2020 10:52 AM
To: Luo, Heng <heng.luo@intel.com>; Ni, Ray <ray.ni@intel.com>;
devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

Ray:
Package has dec file in its root directory. Package DSC file is optional.

Thanks
Liming
-----Original Message-----
From: Luo, Heng <heng.luo@intel.com>
Sent: 2020年3月31日 9:25
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming
<liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

Hi Liming,
I will apply the change below if you agree to we treat a folder that contains ".dec" and "dsc" files as a package directory:

diff --git a/Platform/Intel/build_bios.py
b/Platform/Intel/build_bios.py index b9ad980510..bb25699ed8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -16,6 +16,7 @@ imported functions from board directory import os
import re import sys
+import glob
import signal
import shutil
import argparse
@@ -123,7 +124,10 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# add all feature domains in WORKSPACE_FEATURES to package path
for filename in os.listdir(config["WORKSPACE_FEATURES"]):
filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
- if os.path.isdir(filepath):
+ # feature domains folder does not contain dec or dsc file
+ if os.path.isdir(filepath) and \
+ not glob.glob(os.path.join(filepath, "*.dec")) and \
+ not glob.glob(os.path.join(filepath, "*.dsc")):
config["PACKAGES_PATH"] += os.pathsep + filepath
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
config["PACKAGES_PATH"] += os.pathsep + \

Best Regards
Heng

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, March 30, 2020 5:01 PM
To: Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming
<liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

+ # add all feature domains in WORKSPACE_FEATURES to package path
+ for filename in os.listdir(config["WORKSPACE_FEATURES"]):
+ filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
+ if os.path.isdir(filepath):
+ config["PACKAGES_PATH"] += os.pathsep + filepath
Will this change include "AdvancedFeaturePkg" and "TemplateFeaturePkg"
folder as well?

Can you please revise the patch to skip adding folders that contains
package contents to the PACKAGES_PATH?

Liming,
What's the criteria of a package? Can we treat a folder that contains ".dec"
and "dsc" files as a package directory?

Thanks,
Ray


Re: [Patch V2 0/3] Fix build error of OpenBoard

Liming Gao
 

Reviewed-by: Liming Gao <liming.gao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Heng Luo
Sent: 2020年3月31日 11:49
To: devel@edk2.groups.io
Subject: [edk2-devel] [Patch V2 0/3] Fix build error of OpenBoard

*** BLURB HERE ***

Heng Luo (3):
Platform/Intel: Add all pathes of feature domains to package path
Features/Intel: Add LogoFeaturePkg to TemporaryBuildWorkaround
Features/Intel: Correct wrong codes and remove unnecessary codes

Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc | 4 +++- Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf | 5 ++++-
Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc | 9 ---------
Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf | 2 +-
Platform/Intel/build_bios.py | 10 +++++++++-
5 files changed, 17 insertions(+), 13 deletions(-)

--
2.24.0.windows.2


Re: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Ni, Ray
 

Liming,
Where can I find the rule?

Thanks,
Ray

-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Tuesday, March 31, 2020 10:52 AM
To: Luo, Heng <heng.luo@intel.com>; Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Ray:
Package has dec file in its root directory. Package DSC file is optional.

Thanks
Liming
-----Original Message-----
From: Luo, Heng <heng.luo@intel.com>
Sent: 2020年3月31日 9:25
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming <liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Hi Liming,
I will apply the change below if you agree to we treat a folder that contains ".dec" and "dsc" files as a package directory:

diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index b9ad980510..bb25699ed8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -16,6 +16,7 @@ imported functions from board directory import os import re import sys
+import glob
import signal
import shutil
import argparse
@@ -123,7 +124,10 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# add all feature domains in WORKSPACE_FEATURES to package path
for filename in os.listdir(config["WORKSPACE_FEATURES"]):
filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
- if os.path.isdir(filepath):
+ # feature domains folder does not contain dec or dsc file
+ if os.path.isdir(filepath) and \
+ not glob.glob(os.path.join(filepath, "*.dec")) and \
+ not glob.glob(os.path.join(filepath, "*.dsc")):
config["PACKAGES_PATH"] += os.pathsep + filepath
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
config["PACKAGES_PATH"] += os.pathsep + \

Best Regards
Heng

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, March 30, 2020 5:01 PM
To: Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming
<liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

+ # add all feature domains in WORKSPACE_FEATURES to package path
+ for filename in os.listdir(config["WORKSPACE_FEATURES"]):
+ filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
+ if os.path.isdir(filepath):
+ config["PACKAGES_PATH"] += os.pathsep + filepath
Will this change include "AdvancedFeaturePkg" and "TemplateFeaturePkg"
folder as well?

Can you please revise the patch to skip adding folders that contains
package contents to the PACKAGES_PATH?

Liming,
What's the criteria of a package? Can we treat a folder that contains ".dec"
and "dsc" files as a package directory?

Thanks,
Ray


[Patch V2 3/3] Features/Intel: Correct wrong codes and remove unnecessary codes

Heng Luo
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2644

Correct wrong codes and remove unnecessary codes in LogoFeaturePkg.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc | 9 --=
-------
Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf | 2 +-
2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeatur=
e.dsc b/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
index fca0bfd540..d2dcdeb36a 100644
--- a/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
+++ b/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
@@ -25,15 +25,6 @@
!error "DXE_ARCH must be specified to build this feature!"=0D
!endif=0D
=0D
-##########################################################################=
######=0D
-#=0D
-# Packages Section - Make sure PCD can be directly used in a conditional s=
tatement=0D
-# in a DSC which includes this DSC file.=0D
-#=0D
-##########################################################################=
######=0D
-[Packages]=0D
- LogoFeaturePkg/LogoFeaturePkg.dec=0D
-=0D
##########################################################################=
######=0D
#=0D
# Library Class section - list of all Library Classes needed by this featu=
re.=0D
diff --git a/Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory=
.fdf b/Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf
index 080c87223c..fead9f3b02 100644
--- a/Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf
+++ b/Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf
@@ -6,7 +6,7 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
-!if gSmbiosFeaturePkgTokenSpaceGuid.PcdJpgEnable =3D=3D TRUE=0D
+!if gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable =3D=3D TRUE=0D
INF LogoFeaturePkg/LogoDxe/JpegLogoDxe.inf=0D
!else=0D
INF LogoFeaturePkg/LogoDxe/LogoDxe.inf=0D
--=20
2.24.0.windows.2


[Patch V2 2/3] Features/Intel: Add LogoFeaturePkg to TemporaryBuildWorkaround

Heng Luo
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2644

Need to add LogoFeaturePkg to TemporaryBuildWorkaround because
OpenBoard still includes TemporaryBuildWorkaround for building BIOS.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildW=
orkaround.dsc | 4 +++-
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildW=
orkaround.inf | 5 ++++-
2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Tem=
poraryBuildWorkaround.dsc b/Features/Intel/AdvancedFeaturePkg/TemporaryBuil=
dWorkaround/TemporaryBuildWorkaround.dsc
index 227ae00908..c62f9ecc6e 100644
--- a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryB=
uildWorkaround.dsc
+++ b/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryB=
uildWorkaround.dsc
@@ -13,7 +13,7 @@
# When the BaseTools update is complete, this file can entirely be removed=
=0D
# from this package.=0D
#=0D
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -49,6 +49,8 @@
gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable =
|FALSE=0D
gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable =
|FALSE=0D
gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable =
|FALSE=0D
+ gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable =
|FALSE=0D
+ gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable =
|FALSE=0D
!endif=0D
=0D
#=0D
diff --git a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/Tem=
poraryBuildWorkaround.inf b/Features/Intel/AdvancedFeaturePkg/TemporaryBuil=
dWorkaround/TemporaryBuildWorkaround.inf
index 74176d1989..00818fbe0a 100644
--- a/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryB=
uildWorkaround.inf
+++ b/Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryB=
uildWorkaround.inf
@@ -13,7 +13,7 @@
# When the BaseTools update is complete, this file can entirely be removed=
=0D
# from this package.=0D
#=0D
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -40,6 +40,7 @@
PowerManagement/S3FeaturePkg/S3FeaturePkg.dec=0D
SystemInformation/SmbiosFeaturePkg/SmbiosFeaturePkg.dec=0D
UserInterface/UserAuthFeaturePkg/UserAuthFeaturePkg.dec=0D
+ UserInterface/LogoFeaturePkg/LogoFeaturePkg.dec=0D
=0D
[FeaturePcd]=0D
gAcpiDebugFeaturePkgTokenSpaceGuid.PcdAcpiDebugFeatureEnable=0D
@@ -49,6 +50,8 @@
gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable=0D
gUsb3DebugFeaturePkgTokenSpaceGuid.PcdUsb3DebugFeatureEnable=0D
gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable=0D
+ gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable=0D
+ gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable=0D
=0D
[Sources]=0D
TemporaryBuildWorkaround.c=0D
--=20
2.24.0.windows.2


[Patch V2 1/3] Platform/Intel: Add all pathes of feature domains to package path

Heng Luo
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2644

Add all pathes of feature domains to package path in build_bios.py.

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---

Notes:
v2:
- Skip adding folders that contains package contents to the PACKAGES_PATH. [Ray Ni]

Platform/Intel/build_bios.py | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index 1ef35aca0a..8f855f63eb 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -3,7 +3,7 @@
# Builds BIOS using configuration files and dynamically
# imported functions from board directory
#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#

@@ -16,6 +16,7 @@ imported functions from board directory
import os
import re
import sys
+import glob
import signal
import shutil
import argparse
@@ -120,6 +121,13 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON"]
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON_BIN"]
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_FEATURES"]
+ # add all feature domains in WORKSPACE_FEATURES to package path
+ for filename in os.listdir(config["WORKSPACE_FEATURES"]):
+ filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
+ # feature domains folder does not contain dec file
+ if os.path.isdir(filepath) and \
+ not glob.glob(os.path.join(filepath, "*.dec")):
+ config["PACKAGES_PATH"] += os.pathsep + filepath
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
config["PACKAGES_PATH"] += os.pathsep + \
os.path.join(config["WORKSPACE"], "FSP")
--
2.24.0.windows.2


[Patch V2 0/3] Fix build error of OpenBoard

Heng Luo
 

*** BLURB HERE ***

Heng Luo (3):
Platform/Intel: Add all pathes of feature domains to package path
Features/Intel: Add LogoFeaturePkg to TemporaryBuildWorkaround
Features/Intel: Correct wrong codes and remove unnecessary codes

Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc | 4 +++-
Features/Intel/AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.inf | 5 ++++-
Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc | 9 ---------
Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf | 2 +-
Platform/Intel/build_bios.py | 10 +++++++++-
5 files changed, 17 insertions(+), 13 deletions(-)

--
2.24.0.windows.2


[PATCH] UnitTestFrameworkPkg/PersistenceLib: Correct the allocated size.

Guomin Jiang
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2608

According to logic and the practice, it is need to allocate ascii length
by 2 for unicode string.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Signed-off-by: Guomin Jiang <guomin.jiang@intel.com>
---
.../UnitTestPersistenceLibSimpleFileSystem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UnitTestFrameworkPkg/Library/UnitTestPersistenceLibSimpleFileS=
ystem/UnitTestPersistenceLibSimpleFileSystem.c b/UnitTestFrameworkPkg/Libra=
ry/UnitTestPersistenceLibSimpleFileSystem/UnitTestPersistenceLibSimpleFileS=
ystem.c
index ccca9bfacb..6da85c459d 100644
--- a/UnitTestFrameworkPkg/Library/UnitTestPersistenceLibSimpleFileSystem/U=
nitTestPersistenceLibSimpleFileSystem.c
+++ b/UnitTestFrameworkPkg/Library/UnitTestPersistenceLibSimpleFileSystem/U=
nitTestPersistenceLibSimpleFileSystem.c
@@ -67,7 +67,7 @@ GetCacheFileDevicePath (
// Before we can start, change test name from ASCII to Unicode.=0D
//=0D
CacheFilePathLength =3D AsciiStrLen (Framework->ShortTitle) + 1;=0D
- TestName =3D AllocatePool (CacheFilePathLength);=0D
+ TestName =3D AllocatePool (CacheFilePathLength * sizeof(CHAR16));=0D
if (!TestName) {=0D
goto Exit;=0D
}=0D
--=20
2.25.1.windows.1


Re: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Heng Luo
 

OK, it means we just need to check dec file

Best Regards
Heng

-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Tuesday, March 31, 2020 10:52 AM
To: Luo, Heng <heng.luo@intel.com>; Ni, Ray <ray.ni@intel.com>;
devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to
package path

Ray:
Package has dec file in its root directory. Package DSC file is optional.

Thanks
Liming
-----Original Message-----
From: Luo, Heng <heng.luo@intel.com>
Sent: 2020年3月31日 9:25
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming <liming.gao@intel.com>;
Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to
package path

Hi Liming,
I will apply the change below if you agree to we treat a folder that contains
".dec" and "dsc" files as a package directory:

diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
b9ad980510..bb25699ed8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -16,6 +16,7 @@ imported functions from board directory import os
import re import sys
+import glob
import signal
import shutil
import argparse
@@ -123,7 +124,10 @@ def pre_build(build_config, build_type="DEBUG",
silent=False, toolchain=None):
# add all feature domains in WORKSPACE_FEATURES to package path
for filename in os.listdir(config["WORKSPACE_FEATURES"]):
filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
- if os.path.isdir(filepath):
+ # feature domains folder does not contain dec or dsc file
+ if os.path.isdir(filepath) and \
+ not glob.glob(os.path.join(filepath, "*.dec")) and \
+ not glob.glob(os.path.join(filepath, "*.dsc")):
config["PACKAGES_PATH"] += os.pathsep + filepath
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
config["PACKAGES_PATH"] += os.pathsep + \

Best Regards
Heng

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, March 30, 2020 5:01 PM
To: Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming
<liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

+ # add all feature domains in WORKSPACE_FEATURES to package path
+ for filename in os.listdir(config["WORKSPACE_FEATURES"]):
+ filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
+ if os.path.isdir(filepath):
+ config["PACKAGES_PATH"] += os.pathsep + filepath
Will this change include "AdvancedFeaturePkg" and "TemplateFeaturePkg"
folder as well?

Can you please revise the patch to skip adding folders that contains
package contents to the PACKAGES_PATH?

Liming,
What's the criteria of a package? Can we treat a folder that contains ".dec"
and "dsc" files as a package directory?

Thanks,
Ray


Re: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Liming Gao
 

Ray:
Package has dec file in its root directory. Package DSC file is optional.

Thanks
Liming

-----Original Message-----
From: Luo, Heng <heng.luo@intel.com>
Sent: 2020年3月31日 9:25
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming <liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Hi Liming,
I will apply the change below if you agree to we treat a folder that contains ".dec" and "dsc" files as a package directory:

diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index b9ad980510..bb25699ed8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -16,6 +16,7 @@ imported functions from board directory import os import re import sys
+import glob
import signal
import shutil
import argparse
@@ -123,7 +124,10 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# add all feature domains in WORKSPACE_FEATURES to package path
for filename in os.listdir(config["WORKSPACE_FEATURES"]):
filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
- if os.path.isdir(filepath):
+ # feature domains folder does not contain dec or dsc file
+ if os.path.isdir(filepath) and \
+ not glob.glob(os.path.join(filepath, "*.dec")) and \
+ not glob.glob(os.path.join(filepath, "*.dsc")):
config["PACKAGES_PATH"] += os.pathsep + filepath
config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
config["PACKAGES_PATH"] += os.pathsep + \

Best Regards
Heng

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, March 30, 2020 5:01 PM
To: Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@intel.com>; Gao, Liming
<liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature
domains to package path

+ # add all feature domains in WORKSPACE_FEATURES to package path
+ for filename in os.listdir(config["WORKSPACE_FEATURES"]):
+ filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
+ if os.path.isdir(filepath):
+ config["PACKAGES_PATH"] += os.pathsep + filepath
Will this change include "AdvancedFeaturePkg" and "TemplateFeaturePkg"
folder as well?

Can you please revise the patch to skip adding folders that contains
package contents to the PACKAGES_PATH?

Liming,
What's the criteria of a package? Can we treat a folder that contains ".dec"
and "dsc" files as a package directory?

Thanks,
Ray


Re: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

Dong, Eric
 

Liming,

 

Please help to provide comments for this mail. It break the open board now

 

Thanks,

Eric

From: Luo, Heng
Sent: Tuesday, March 31, 2020 9:25 AM
To: Ni, Ray <ray.ni@...>; devel@edk2.groups.io
Cc: Bi, Dandan <dandan.bi@...>; Gao, Liming <liming.gao@...>; Dong, Eric <eric.dong@...>
Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to package path

 

Hi Liming,
I will apply the change below if you agree to  we treat a folder that contains ".dec" and "dsc" files as a package directory:

diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index b9ad980510..bb25699ed8 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -16,6 +16,7 @@ imported functions from board directory
 import os
 import re
 import sys
+import glob
 import signal
 import shutil
 import argparse
@@ -123,7 +124,10 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
     # add all feature domains in WORKSPACE_FEATURES to package path
     for filename in os.listdir(config["WORKSPACE_FEATURES"]):
         filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
-        if os.path.isdir(filepath):
+        # feature domains folder does not contain dec or dsc file
+        if os.path.isdir(filepath) and \
+          not glob.glob(os.path.join(filepath, "*.dec")) and \
+          not glob.glob(os.path.join(filepath, "*.dsc")):
             config["PACKAGES_PATH"] += os.pathsep + filepath
     config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
     config["PACKAGES_PATH"] += os.pathsep + \

Best Regards
Heng

> -----Original Message-----
> From: Ni, Ray <ray.ni@...>
> Sent: Monday, March 30, 2020 5:01 PM
> To: Luo, Heng <heng.luo@...>; devel@edk2.groups.io
> Cc: Bi, Dandan <dandan.bi@...>; Gao, Liming <liming.gao@...>;
> Dong, Eric <eric.dong@...>
> Subject: RE: [PATCH 1/3] Platform/Intel: Add all pathes of feature domains to
> package path

> > +    # add all feature domains in WORKSPACE_FEATURES to package path
> > +    for filename in os.listdir(config["WORKSPACE_FEATURES"]):
> > +        filepath = os.path.join(config["WORKSPACE_FEATURES"], filename)
> > +        if os.path.isdir(filepath):
> > +            config["PACKAGES_PATH"] += os.pathsep + filepath

> Will this change include "AdvancedFeaturePkg" and "TemplateFeaturePkg"
> folder as well?

> Can you please revise the patch to skip adding folders that contains package
> contents to the PACKAGES_PATH?

> Liming,
> What's the criteria of a package? Can we treat a folder that contains ".dec"
> and "dsc" files as a package directory?

> Thanks,
> Ray


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Re: [PATCH V3 0/2] MdePkg-IndustryStandard: CXL Base Specification registers

Javeed, Ashraf
 

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed,
Ashraf
Sent: Tuesday, March 31, 2020 7:33 AM
To: devel@edk2.groups.io
Subject: [edk2-devel] [PATCH V3 0/2] MdePkg-IndustryStandard: CXL Base
Specification registers

These set of two patches introduces the CXL Base Specification register
definitions to the MDE; the Cxl11.h has the register definitions for revision
1.1, and the header Cxl.h is the main wrapper header file to support all
versions of CXL Base Specification register definitions.

Ashraf Javeed (2):
MdePkg-IndustryStandard: CXL 1.1 Base Specification registers
MdePkg-IndustryStandard: Main header for all versions of CXL registers

MdePkg/Include/IndustryStandard/Cxl.h | 18 ++++++++++++++++++
MdePkg/Include/IndustryStandard/Cxl11.h | 526
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++
MdePkg/Include/IndustryStandard/Pci.h | 6 ++----
3 files changed, 546 insertions(+), 4 deletions(-) create mode 100644
MdePkg/Include/IndustryStandard/Cxl.h
create mode 100644 MdePkg/Include/IndustryStandard/Cxl11.h

--
2.21.0.windows.1



[PATCH V3 2/2] MdePkg-IndustryStandard: Main header for all versions of CXL registers

Javeed, Ashraf
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Introducing the Cxl.h as the main header file to support all versions of
CXL Base Specification register definitions.

Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/IndustryStandard/Cxl.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/IndustryStandard/Cxl.h
new file mode 100644
index 0000000000..d945fcbda2
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl.h
@@ -0,0 +1,18 @@
+/** @file
+ Support for the latest CXL standard
+
+ The main header to reference all versions of CXL Base specification registers
+ from the MDE
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL_H_
+#define _CXL_H_
+
+#include <IndustryStandard/Cxl11.h>
+
+#endif
+
--
2.21.0.windows.1


[PATCH V3 1/2] MdePkg-IndustryStandard: CXL 1.1 Base Specification registers

Javeed, Ashraf
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Register definitions from chapter 7 of CXL Base Specification Rev.1.1
are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of upgraded Pci.h.

Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
---
MdePkg/Include/IndustryStandard/Cxl11.h | 526 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdePkg/Include/IndustryStandard/Pci.h | 6 ++----
2 files changed, 528 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/IndustryStandard/Cxl11.h
new file mode 100644
index 0000000000..65c900142e
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Cxl11.h
@@ -0,0 +1,526 @@
+/** @file
+ CXL 1.1 Register definitions
+
+ This file contains the register definitions based on the Compute Express Link
+ (CXL) Base Specification Revision 1.1.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CXL11_H_
+#define _CXL11_H_
+
+#include <IndustryStandard/Pci.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// The PCIe DVSEC for Flex Bus device
+///
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 MemHwInitMode : 1; // bit 3
+ UINT16 HdmCount : 2; // bit 4..5
+ UINT16 Reserved1 : 8; // bit 6..13
+ UINT16 ViralCapable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CacheSfCoverage : 5; // bit 3..7
+ UINT16 CacheSfGranularity : 3; // bit 8..10
+ UINT16 CacheCleanEviction : 1; // bit 11
+ UINT16 Reserved1 : 2; // bit 12..13
+ UINT16 ViralEnable : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 14; // bit 0..13
+ UINT16 ViralStatus : 1; // bit 14
+ UINT16 Reserved2 : 1; // bit 15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 1; // bit 2
+ UINT16 Reserved4 : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;
+
+typedef union {
+ struct {
+ UINT16 Reserved1 : 1; // bit 0
+ UINT16 Reserved2 : 1; // bit 1
+ UINT16 Reserved3 : 14; // bit 2..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;
+
+typedef union {
+ struct {
+ UINT16 ConfigLock : 1; // bit 0
+ UINT16 Reserved1 : 15; // bit 1..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;
+
+
+typedef union {
+ struct {
+ UINT32 MemorySizeHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 MemoryInfoValid : 1; // bit 0
+ UINT32 MemoryActive : 1; // bit 1
+ UINT32 MediaType : 3; // bit 2..4
+ UINT32 MemoryClass : 3; // bit 5..7
+ UINT32 DesiredInterleave : 3; // bit 8..10
+ UINT32 Reserved : 17; // bit 11..27
+ UINT32 MemorySizeLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;
+
+typedef union {
+ struct {
+ UINT32 MemoryBaseHigh : 32; // bit 0..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 28; // bit 0..27
+ UINT32 MemoryBaseLow : 4; // bit 28..31
+ }Bits;
+ UINT32 Uint32;
+} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DvsecFlexBusDeviceCapability; // offset 10
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DvsecFlexBusDeviceControl; // offset 12
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DvsecFlexBusDeviceStatus; // offset 14
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DvsecFlexBusDeviceControl2; // offset 16
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DvsecFlexBusDeviceStatus2; // offset 18
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DvsecFlexBusDeviceLock; // offset 20
+ UINT16 Reserved; // offset 22
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DvsecFlexBusDeviceRange1SizeHigh; // offset 24
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DvsecFlexBusDeviceRange1SizeLow; // offset 28
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DvsecFlexBusDeviceRange1BaseHigh; // offset 32
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DvsecFlexBusDeviceRange1BaseLow; // offset 36
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DvsecFlexBusDeviceRange2SizeHigh; // offset 40
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DvsecFlexBusDeviceRange2SizeLow; // offset 44
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DvsecFlexBusDeviceRange2BaseHigh; // offset 48
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DvsecFlexBusDeviceRange2BaseLow; // offset 52
+} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;
+
+///
+/// PCIe DVSEC for FLex Bus Port
+///
+typedef union {
+ struct {
+ UINT16 CacheCapable : 1; // bit 0
+ UINT16 IoCapable : 1; // bit 1
+ UINT16 MemCapable : 1; // bit 2
+ UINT16 Reserved : 13; // bit 3..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 Retimer1Present : 1; // bit 8
+ UINT16 Retimer2Present : 1; // bit 9
+ UINT16 Reserved2 : 6; // bit 10..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;
+
+typedef union {
+ struct {
+ UINT16 CacheEnable : 1; // bit 0
+ UINT16 IoEnable : 1; // bit 1
+ UINT16 MemEnable : 1; // bit 2
+ UINT16 CxlSyncBypassEnable : 1; // bit 3
+ UINT16 DriftBufferEnable : 1; // bit 4
+ UINT16 Reserved : 3; // bit 5..7
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10
+ UINT16 Reserved2 : 5; // bit 11..15
+ }Bits;
+ UINT16 Uint16;
+} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY DvsecFlexBusPortCapability; // offset 10
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL DvsecFlexBusPortControl; // offset 12
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS DvsecFlexBusPortStatus; // offset 14
+} CXL_1_1_DVSEC_FLEX_BUS_PORT;
+
+///
+/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers
+///
+
+/// The CXL.Cache and CXL.Memory Architectural register definitions
+/// Based on section 7.2.2 of CXL Base Specification Rev. 1.1
+///@{
+
+#define CXL_CAPABILITY_HEADER_OFFSET 0
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23
+ UINT32 ArraySize : 8; // bit 24..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CAPABILITY_HEADER;
+
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_RAS_CAPABILITY_HEADER;
+
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_SECURITY_CAPABILITY_HEADER;
+
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC
+typedef union {
+ struct {
+ UINT32 CxlCapabilityId : 16; // bit 0..15
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_CAPABILITY_HEADER;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParity : 1; // bit 0..0
+ UINT32 CacheAddressParity : 1; // bit 1..1
+ UINT32 CacheByteEnableParity : 1; // bit 2..2
+ UINT32 CacheDataEcc : 1; // bit 3..3
+ UINT32 MemDataParity : 1; // bit 4..4
+ UINT32 MemAddressParity : 1; // bit 5..5
+ UINT32 MemByteEnableParity : 1; // bit 6..6
+ UINT32 MemDataEcc : 1; // bit 7..7
+ UINT32 ReInitThreshold : 1; // bit 8..8
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9
+ UINT32 PoisonReceived : 1; // bit 10..10
+ UINT32 ReceiverOverflow : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParityMask : 1; // bit 0..0
+ UINT32 CacheAddressParityMask : 1; // bit 1..1
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2
+ UINT32 CacheDataEccMask : 1; // bit 3..3
+ UINT32 MemDataParityMask : 1; // bit 4..4
+ UINT32 MemAddressParityMask : 1; // bit 5..5
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6
+ UINT32 MemDataEccMask : 1; // bit 7..7
+ UINT32 ReInitThresholdMask : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9
+ UINT32 PoisonReceivedMask : 1; // bit 10..10
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3
+ UINT32 MemDataParitySeverity : 1; // bit 4..4
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6
+ UINT32 MemDataEccSeverity : 1; // bit 7..7
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11
+ UINT32 Reserved : 20; // bit 12..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEcc : 1; // bit 0..0
+ UINT32 MemoryDataEcc : 1; // bit 1..1
+ UINT32 CrcThreshold : 1; // bit 2..2
+ UINT32 RetryThreshold : 1; // bit 3..3
+ UINT32 CachePoisonReceived : 1; // bit 4..4
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5
+ UINT32 PhysicalLayerError : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_STATUS;
+
+typedef union {
+ struct {
+ UINT32 CacheDataEccMask : 1; // bit 0..0
+ UINT32 MemoryDataEccMask : 1; // bit 1..1
+ UINT32 CrcThresholdMask : 1; // bit 2..2
+ UINT32 RetryThresholdMask : 1; // bit 3..3
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CORRECTABLE_ERROR_MASK;
+
+typedef union {
+ struct {
+ UINT32 FirstErrorPointer : 4; // bit 0..3
+ UINT32 Reserved1 : 5; // bit 4..8
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9
+ UINT32 Reserved2 : 3; // bit 10..12
+ UINT32 PoisonEnabled : 1; // bit 13..13
+ UINT32 Reserved3 : 18; // bit 14..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_ERROR_CAPABILITIES_AND_CONTROL;
+
+typedef struct {
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS HeaderLog[16];
+} CXL_HEADER_LOG;
+
+typedef struct {
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus; // offset 0
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask; // offset 4
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity; // offset 8
+ CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus; // offset 12
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask; // offset 16
+ CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl; // offset 20
+ CXL_HEADER_LOG HeaderLog; // offset 24
+} CXL_1_1_RAS_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT32 DeviceTrustLevel : 2; // bit 0..1
+ UINT32 Reserved : 30; // bit 2..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_1_1_SECURITY_POLICY;
+
+typedef struct {
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;
+} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;
+
+typedef union {
+ struct {
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23
+ UINT64 NumRetryReceived : 5; // bit 24..28
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33
+ UINT64 WrPtrReceived : 8; // bit 34..41
+ UINT64 EchoEseqReceived : 8; // bit 42..49
+ UINT64 NumFreeBufReceived : 8; // bit 50..57
+ UINT64 Reserved : 6; // bit 58..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_CAPABILITY;
+
+typedef union {
+ struct {
+ UINT16 LlReset : 1; // bit 0..0
+ UINT16 LlInitStall : 1; // bit 1..1
+ UINT16 LlCrdStall : 1; // bit 2..2
+ UINT16 InitState : 2; // bit 3..4
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12
+ UINT16 Reserved : 3; // bit 13..15
+ } Bits;
+ UINT16 Uint16;
+} CXL_LINK_LAYER_CONTROL_AND_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_CONTROL;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;
+
+typedef union {
+ struct {
+ UINT64 CacheReqCredits : 10; // bit 0..9
+ UINT64 CacheRspCredits : 10; // bit 10..19
+ UINT64 CacheDataCredits : 10; // bit 20..29
+ UINT64 MemReqRspCredits : 10; // bit 30..39
+ UINT64 MemDataCredits : 10; // bit 40..49
+ } Bits;
+ UINT64 Uint64;
+} CXL_LINK_LAYER_TX_CREDIT_STATUS;
+
+typedef union {
+ struct {
+ UINT32 AckForceThreshold : 8; // bit 0..7
+ UINT32 AckFLushRetimer : 10; // bit 8..17
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_ACK_TIMER_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 MdhDisable : 1; // bit 0..0
+ UINT32 Reserved : 31; // bit 1..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_LINK_LAYER_DEFEATURE;
+
+typedef struct {
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability; // offset 0
+ CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus; // offset 8
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl; // offset 10
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus; // offset 18
+ CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus; // offset 26
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl; // offset 34
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature; // offset 38
+} CXL_1_1_LINK_CAPABILITY_STRUCTURE;
+
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_IO_ARBITRATION_CONTROL;
+
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0
+typedef union {
+ struct {
+ UINT32 Reserved1 : 4; // bit 0..3
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7
+ UINT32 Reserved2 : 24; // bit 8..31
+ } Bits;
+ UINT32 Uint32;
+} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;
+///@}
+
+typedef union {
+ struct {
+ UINT64 RcrbEnable : 1; // bit 0..0
+ UINT64 Reserved : 12; // bit 1..12
+ UINT64 RcrbBaseAddress : 51; // bit 13..63
+ } Bits;
+ UINT64 Uint64;
+} CXL_RCRB_BASE;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h
index 8ed96b992a..42c00ac762 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,7 +1,7 @@
/** @file
Support for the latest PCI standard.

-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -9,9 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _PCI_H_
#define _PCI_H_

-#include <IndustryStandard/Pci30.h>
-#include <IndustryStandard/PciExpress21.h>
-#include <IndustryStandard/PciExpress30.h>
+#include <IndustryStandard/PciExpress50.h>
#include <IndustryStandard/PciCodeId.h>

#endif
--
2.21.0.windows.1


[PATCH V3 0/2] MdePkg-IndustryStandard: CXL Base Specification registers

Javeed, Ashraf
 

These set of two patches introduces the CXL Base Specification register definitions
to the MDE; the Cxl11.h has the register definitions for revision 1.1, and the header
Cxl.h is the main wrapper header file to support all versions of CXL Base Specification
register definitions.

Ashraf Javeed (2):
MdePkg-IndustryStandard: CXL 1.1 Base Specification registers
MdePkg-IndustryStandard: Main header for all versions of CXL registers

MdePkg/Include/IndustryStandard/Cxl.h | 18 ++++++++++++++++++
MdePkg/Include/IndustryStandard/Cxl11.h | 526 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
MdePkg/Include/IndustryStandard/Pci.h | 6 ++----
3 files changed, 546 insertions(+), 4 deletions(-)
create mode 100644 MdePkg/Include/IndustryStandard/Cxl.h
create mode 100644 MdePkg/Include/IndustryStandard/Cxl11.h

--
2.21.0.windows.1


Re: [PATCH 1/1] MdeModulePkg: UART Dynamic clock freq Support

Ni, Ray
 

Leif,
Please understand that the concern of this change is all the platforms that uses
this serial port lib must be changed otherwise build breaks.

Ard,
Using Guided HOB sounds a good idea to me: )
The benefits of using HOB is:
Length field in the HOB header can be used for extension if more parameters are needed.
DXE can have the HOB access as well.

EFI_SEC_HOB_DATA_PPI can be used to return the new Guided HOB from SEC phase if needed.

Thanks,
Ray

-----Original Message-----
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Sent: Monday, March 30, 2020 3:45 PM
To: Leif Lindholm <leif@nuviainc.com>
Cc: Jiang, Guomin <guomin.jiang@intel.com>; devel@edk2.groups.io; pankaj.bansal@nxp.com; Ni, Ray <ray.ni@intel.com>;
Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>; Ma, Maurice <maurice.ma@intel.com>; Dong,
Guo <guo.dong@intel.com>; You, Benjamin <benjamin.you@intel.com>; Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
Mahmoud@arm.com>
Subject: Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: UART Dynamic clock freq Support

On Mon, 30 Mar 2020 at 09:35, Leif Lindholm <leif@nuviainc.com> wrote:

Hi Jiang,

It is not a question of effort of copying a driver, it is a question
that copying drivers is something that should be avoided wherever
practically possible. I did not think this topic was still under
debate.

If the existing 16550 SerialPortLib is overspecialised to the point
where it only works on a subset of 16550 implementations, then it
should change. There are going to be more non-PC systems turning up
with 16550 UARTs - should they each copy/modify their drivers?

If there are better ways of solving that problem, please suggest.
But more duplicated drivers is not the answer.
Could we use a GUIDed HOB? If it exists, we use its contents, and if
it doesn't, we use the default set by the FixedPCD.