Date   

Re: [edk2-platforms] [PATCH v2 2/7] CometlakeOpenBoardPkg/CometlakeURvp: Add headers

Chiu, Chasel
 

Reviewed-by: Chasel Chiu <chasel.chiu@...>

-----Original Message-----
From: Esakkithevar, Kathappan <kathappan.esakkithevar@...>
Sent: Wednesday, February 12, 2020 3:13 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@...>; Chiu, Chasel
<chasel.chiu@...>; Desimone, Nathaniel L
<nathaniel.l.desimone@...>; Kethi Reddy, Deepika
<deepika.kethi.reddy@...>; Agyeman, Prince
<prince.agyeman@...>
Subject: [edk2-platforms] [PATCH v2 2/7]
CometlakeOpenBoardPkg/CometlakeURvp: Add headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Header files for the CometlakeURvp board instance.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
.../CometlakeURvp/Include/Fdf/FlashMapInclude.fdf | 49 ++++++++
.../CometlakeURvp/Include/PeiPlatformHookLib.h | 131
+++++++++++++++++++++
.../CometlakeURvp/Include/PeiPlatformLib.h | 40 +++++++
.../CometlakeURvp/Include/PlatformBoardConfig.h | 105
+++++++++++++++++
.../CometlakeURvp/Include/PlatformInfo.h | 44 +++++++
5 files changed, 369 insertions(+)
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashM
apInclude.fdf
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatform
HookLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatform
Lib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformBo
ardConfig.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformInf
o.h

diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash
MapInclude.fdf
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Flash
MapInclude.fdf
new file mode 100644
index 0000000000..d9959a79d0
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Fla
+++ shMapInclude.fdf
@@ -0,0 +1,49 @@
+## @file
+# FDF file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> # #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+#==============================================================
========
+===========#
+# 8 M BIOS - for FSP wrapper
+#==============================================================
===================#
+DEFINE FLASH_BASE
= 0xFF800000 #
+DEFINE FLASH_SIZE
= 0x00800000 #
+DEFINE FLASH_BLOCK_SIZE
= 0x00010000 #
+DEFINE FLASH_NUM_BLOCKS
= 0x00000080 #
+#==============================================================
========
+===========#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset
= 0x00000000 # Flash addr (0xFF800000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize
= 0x00040000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =
0x00000000 # Flash addr (0xFF800000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
= 0x0001E000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset
=
+0x0001E000 # Flash addr (0xFF81E000) SET
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
0x00002000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset
= 0x00020000 # Flash addr (0xFF820000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
= 0x00020000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
= 0x00040000 # Flash addr (0xFF840000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
= 0x00050000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =
0x00090000 # Flash addr (0xFF890000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =
0x00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset
= 0x00100000 # Flash addr (0xFF900000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
= 0x00090000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset
= 0x00190000 # Flash addr (0xFF990000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
= 0x00190000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset
= 0x00320000 # Flash addr (0xFFB20000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
= 0x00170000 #
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
= 0x00490000 # Flash addr (0xFFC90000)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
= 0x000B0000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset
= 0x00540000 # Flash addr (0xFFD40000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
= 0x00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset
= 0x005B0000 # Flash addr (0xFFDB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
= 0x000EC000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset
= 0x0069C000 # Flash addr (0xFFE9C000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
= 0x00014000 #
+SET
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =
0x006B0000 # Flash addr (0xFFEB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
= 0x00010000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset
= 0x006C0000 # Flash addr (0xFFEC0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
= 0x00140000 #
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor
mHookLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfo
rmHookLib.h
new file mode 100644
index 0000000000..690054d2e9
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat
+++ formHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include <PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+
+
+//EC Command to provide one byte of debug indication #define
+BSSB_DEBUG_INDICATION 0xAE
+/**
+ Configure EC for specific devices
+
+ @param[in] PchLan - The PchLan of PCH_SETUP variable.
+ @param[in] BootMode - The current boot mode.
+**/
+VOID
+EcInit (
+ IN UINT8 PchLan,
+ IN EFI_BOOT_MODE BootMode
+ );
+
+/**
+ Checks if Premium PMIC present
+
+ @retval TRUE if present
+ @retval FALSE it discrete/other PMIC **/ BOOLEAN
+IsPremiumPmicPresent (
+ VOID
+ );
+
+/**
+ Pmic Programming to supprort LPAL Feature
+
+ @retval NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+ VOID
+ );
+
+/**
+Pmic Programming to supprort LPAL Feature
+ @retval NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+ VOID
+ );
+
+/**
+ Do platform specific programming pre-memory. For example, EC init,
+Chipset programming
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+ VOID
+ );
+
+/**
+ Do platform specific programming post-memory.
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO Before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ VOID
+ );
+
+/**
+Voltage Margining Routine
+
+@retval EFI_SUCCESS Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+ VOID
+ );
+
+/**
+ Detect recovery mode
+
+ @retval EFI_SUCCESS System in Recovery Mode
+ @retval EFI_UNSUPPORTED System doesn't support Recovery Mode
+ @retval EFI_NOT_FOUND System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+ VOID
+ );
+
+/**
+ Early board Configuration before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+ VOID
+ );
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfor
mLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlatfo
rmLib.h
new file mode 100644
index 0000000000..3443479a52
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat
+++ formLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED 1
+
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+ PCH_GPIO_DEV Use_Sel;
+ PCH_GPIO_DEV Use_Sel2;
+ PCH_GPIO_DEV Use_Sel3;
+ PCH_GPIO_DEV Io_Sel;
+ PCH_GPIO_DEV Io_Sel2;
+ PCH_GPIO_DEV Io_Sel3;
+ PCH_GPIO_DEV Lvl;
+ PCH_GPIO_DEV Lvl2;
+ PCH_GPIO_DEV Lvl3;
+ PCH_GPIO_DEV Inv;
+ PCH_GPIO_DEV Blink;
+ PCH_GPIO_DEV Rst_Sel;
+ PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platform
BoardConfig.h
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platform
BoardConfig.h
new file mode 100644
index 0000000000..4d286b897a
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor
+++ mBoardConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <GpioConfig.h>
+#include <TbtBoardInfo.h>
+
+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
+#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) &
0xFFF0))
+
+#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
#define
+BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 #define
+BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 #define
+BOARD_NO_BATTERY_SUPPORT 0 #define
BOARD_REAL_BATTERY_SUPPORTED BIT0
+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
+
+#pragma pack(1)
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
Config Block Header
+} BOARD_CONFIG_BLOCK;
+
+typedef struct {
+ UINT8 GpioSupport;
+ UINT32 WakeGpioNo;
+ UINT8 HoldRstExpanderNo;
+ UINT32 HoldRstGpioNo;
+ BOOLEAN HoldRstActive;
+ UINT8 PwrEnableExpanderNo;
+ UINT32 PwrEnableGpioNo;
+ BOOLEAN PwrEnableActive;
+} SWITCH_GRAPHIC_GPIO;
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef enum {
+ BoardGpioTypePch,
+ BoardGpioTypeExpander,
+ BoardGpioTypeNotSupported = 0xFF
+} BOARD_GPIO_TYPE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with
PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define FREE_RUNNING 0x80
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+typedef union {
+ UINT32 Blob;
+ USB20_AFE Info;
+} PCD32_BLOB;
+
+#ifndef IO_EXPANDER_DISABLED
+#define IO_EXPANDER_DISABLED 0xFF
+#endif
+
+#define SPD_DATA_SIZE 512
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformI
nfo.h
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PlatformI
nfo.h
new file mode 100644
index 0000000000..f8854485b4
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor
+++ mInfo.h
@@ -0,0 +1,44 @@
+/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PLATFORM_INFO_H_
+#define _PLATFORM_INFO_H_
+
+#pragma pack(1)
+
+///
+/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in
+GpioConfig.h /// typedef UINT32 PCH_GPIO_PAD; //Copied from
+GpioConfig.h (need to change it based on include)
+
+typedef struct {
+UINT8 Expander;
+UINT8 Pin;
+UINT16 Reserved; // Reserved for future use
+} IO_EXPANDER_PAD;
+
+typedef union {
+PCH_GPIO_PAD PchGpio;
+IO_EXPANDER_PAD IoExpGpio;
+} GPIO_PAD_CONFIG;
+
+typedef struct {
+UINT8 GpioType; // 0: Disabled (no GPIO support), 1:
PCH, 2: I/O Expander
+UINT8 Reserved[3]; // Reserved for future use
+GPIO_PAD_CONFIG GpioData;
+} PACKED_GPIO_CONFIG;
+
+typedef union {
+PACKED_GPIO_CONFIG PackedGpio;
+UINT64 Data64;
+} COMMON_GPIO_CONFIG;
+
+#pragma pack()
+
+#endif
+
--
2.16.2.windows.1


Re: [edk2-platforms] [PATCH v2 1/7] CometlakeOpenBoardPkg: Add package and headers

Chiu, Chasel
 

Reviewed-by: Chasel Chiu <chasel.chiu@...>

-----Original Message-----
From: Esakkithevar, Kathappan <kathappan.esakkithevar@...>
Sent: Wednesday, February 12, 2020 3:13 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@...>; Chiu, Chasel
<chasel.chiu@...>; Desimone, Nathaniel L
<nathaniel.l.desimone@...>; Kethi Reddy, Deepika
<deepika.kethi.reddy@...>
Subject: [edk2-platforms] [PATCH v2 1/7] CometlakeOpenBoardPkg: Add
package and headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Create the CometlakeOpenBoardPkg to provide board support code. The
package may support Cometlake boards. The package serves as a board
support package in the EDK II Minimum Platform design. Silicon support
for this package is provided in CometLakeFspBinPkg in the FSP repository
and CoffeelakeSiliconPkg in the edk2-platforms repository.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
---
.../Tbt/Include/Library/DxeCheckIommuSupportLib.h | 43 +
.../Features/Tbt/Include/Library/DxeTbtPolicyLib.h | 49 +
.../Tbt/Include/Library/DxeTbtSecurityLib.h | 131 ++
.../Tbt/Include/Library/PeiCheckIommuSupportLib.h | 21 +
.../Features/Tbt/Include/Library/PeiTbtPolicyLib.h | 43 +
.../Tbt/Include/Library/PeiTbtTaskDispatchLib.h | 61 +
.../Features/Tbt/Include/Library/TbtCommonLib.h | 261 +++
.../Features/Tbt/Include/Ppi/PeiTbtPolicy.h | 31 +
.../Tbt/Include/Private/Library/PeiDTbtInitLib.h | 130 ++
.../Include/Private/Library/PeiTbtCommonInitLib.h | 51 +
.../Tbt/Include/Protocol/DisableBmeProtocol.h | 36 +
.../Features/Tbt/Include/Protocol/DxeTbtPolicy.h | 137 ++
.../Features/Tbt/Include/Protocol/TbtNvsArea.h | 50 +
.../Features/Tbt/Include/TbtBoardInfo.h | 23 +
.../Features/Tbt/Include/TbtNvsAreaDef.h | 68 +
.../Tbt/Include/TbtPolicyCommonDefinition.h | 84 +
.../Include/Acpi/GlobalNvs.asl | 112 ++
.../Include/Acpi/GlobalNvsAreaDef.h | 118 ++
.../Include/AttemptUsbFirst.h | 51 +
.../Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h | 57 +
.../Include/FirwmareConfigurations.h | 20 +
.../CometlakeOpenBoardPkg/Include/GopConfigLib.h | 1766
++++++++++++++++++++
.../CometlakeOpenBoardPkg/Include/IoExpander.h | 68 +
.../Include/Library/DxeCpuPolicyUpdateLib.h | 75 +
.../Include/Library/DxeMePolicyUpdateLib.h | 27 +
.../Include/Library/DxePchPolicyUpdateLib.h | 25 +
.../Include/Library/DxePolicyBoardConfigLib.h | 30 +
.../Include/Library/DxeSaPolicyUpdateLib.h | 25 +
.../Include/Library/FspPolicyInitLib.h | 29 +
.../Include/Library/GpioCheckConflictLib.h | 46 +
.../Include/Library/GpioExpanderLib.h | 123 ++
.../Include/Library/HdaVerbTableLib.h | 48 +
.../Include/Library/I2cAccessLib.h | 34 +
.../Include/Library/PeiPlatformLib.h | 40 +
.../Include/Library/PeiPolicyBoardConfigLib.h | 141 ++
.../Include/Library/PeiPolicyInitLib.h | 38 +
.../Include/Library/PlatformInitLib.h | 23 +
.../Include/PchHsioPtssTables.h | 51 +
.../Include/PcieDeviceOverrideTable.h | 106 ++
.../Intel/CometlakeOpenBoardPkg/Include/Platform.h | 33 +
.../Include/PlatformBoardId.h | 29 +
.../Include/Protocol/GlobalNvsArea.h | 47 +
.../Intel/CometlakeOpenBoardPkg/Include/Setup.h | 144 ++
.../Intel/CometlakeOpenBoardPkg/Include/SioRegs.h | 157 ++
.../Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec | 564 +++++++
45 files changed, 5246 insertions(+)
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeCh
eckIommuSupportLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt
PolicyLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt
SecurityLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiChe
ckIommuSupportLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbt
PolicyLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtT
askDispatchLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCo
mmonLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolic
y.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library
/PeiDTbtInitLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Library
/PeiTbtCommonInitLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Disab
leBmeProtocol.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeT
btPolicy.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtN
vsArea.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.
h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaDef
.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCom
monDefinition.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpdat
eLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpdate
Lib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpdate
Lib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardConfi
gLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdateLi
b.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflictLi
b.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfi
gLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
create mode 100644
Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec

diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeC
heckIommuSupportLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Dxe
CheckIommuSupportLib.h
new file mode 100644
index 0000000000..d0ba236145
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/Dxe
CheckIommuSupportLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Header file for the DxeCheckIommuSupport library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+ Detect ME FW and Board Type and return the result via IommuSkuCheck.
+
+ IommuSkuCheck
+ BIT0: Indicate system has a Corporate CSME firmware
+ BIT1: Indicate BIOS is running on a CML RVP
+ BIT2: Indicate BIOS is running on a CFL-H RVP
+ BIT3: Indicate BIOS is running on a CFL-S 8+2 RVP
+
+ @retval Return 0 means not support, otherwise value is defined by
IommuSkuCheck
+**/
+UINT8
+DetectMeAndBoard (
+ VOID
+ );
+
+/**
+ DxeCheckIommuSupport
+
+ Only WHL/CFL-H/CFL-S 8+2 Crop SKUs support Iommu.
+ This function will save sku information to PcdIommuSkuCheck.
+ BIOS will use PcdIommuSkuCheck and other factors to set
PcdVTdPolicyPropertyMask on the next boot in PEI phase
+
+ This function might perform a system reset.
+**/
+EFI_STATUS
+EFIAPI
+DxeCheckIommuSupport (
+ VOID
+ );
+#endif // _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btPolicyLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btPolicyLib.h
new file mode 100644
index 0000000000..0ebffd55ea
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btPolicyLib.h
@@ -0,0 +1,49 @@
+/** @file
+ Prototype of the DxeTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_LIB_H_
+#define _DXE_TBT_POLICY_LIB_H_
+
+
+/**
+ Install TBT Policy.
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to
create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallTbtPolicy (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Update Tbt Policy Callback.
+
+ @param[in] Event A pointer to the Event that triggered the
callback.
+ @param[in] Context A pointer to private data registered with the
callback function.
+
+**/
+VOID
+EFIAPI
+UpdateTbtPolicyCallback (
+ VOID
+ );
+
+/**
+ Print DXE TBT Policy
+**/
+VOID
+TbtPrintDxePolicyConfig (
+ VOID
+ );
+#endif // _DXE_TBT_POLICY_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btSecurityLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btSecurityLib.h
new file mode 100644
index 0000000000..5468ff0bf4
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/DxeT
btSecurityLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_SECURITY_LIB_H_
+#define _TBT_SECURITY_LIB_H_
+
+#include <Protocol/Tcg2Protocol.h>
+#include <Protocol/AcpiTable.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/AslUpdateLib.h>
+#include <Library/UefiLib.h>
+#include <Uefi.h>
+#include <SetupVariable.h>
+#include <OemSetup.h>
+#include <DmaRemappingTable.h>
+#include <PcieRegs.h>
+#include <Tcg2ConfigNvData.h>
+#include <TbtPolicyCommonDefinition.h>
+#include <Library/TbtCommonLib.h>
+
+#define TBT_SECURITY_EVENT_STRING "DMA Protection
Disabled"
+#define TBT_SECURITY_EVENT_STRING_LEN (sizeof
(TBT_SECURITY_EVENT_STRING) - 1)
+
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING "Security Level
is Downgraded to 0"
+#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN (sizeof
(TBT_SECURITY_LEVEL_DOWNGRADED_STRING) - 1)
+
+#define GET_TBT_SECURITY_MODE 0
+#define SET_TBT_SECURITY_MODE 1
+
+typedef struct {
+ UINT8 EnableVtd;
+ BOOLEAN SLDowngrade;
+} PCR7_DATA;
+
+/**
+ TBT Security ExtendPCR7 CallBackFunction
+ If the firmware/BIOS has an option to enable and disable DMA
protections via a VT-d switch in BIOS options, then the shipping configuration
must be with VT-d protection enabled.
+ On every boot where VT-d/DMA protection is disabled, or will be disabled,
or configured to a lower security state, and a platform has a TPM enabled,
then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before
enabling external DMA.
+ The event string SHALL be "DMA Protection Disabled". The platform
firmware MUST log this measurement in the event log using the string "DMA
Protection Disabled" for the Event Data.
+ Measure and log launch of TBT Security, and extend the measurement
result into a specific PCR.
+ Extend an EV_EFI_ACTION event into PCR[7] before enabling external
DMA. The event string SHALL be "DMA Protection Disabled". The platform
firmware MUST log this measurement in the event log using the string "DMA
Protection Disabled" for the Event Data.
+
+ @param[in] Event - A pointer to the Event that triggered the
callback.
+ @param[in] Context - A pointer to private data registered with the
callback function.
+**/
+VOID
+EFIAPI
+ExtendPCR7CallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ TBT Security DisableBme CallBackFunction
+
+ BIOS will disable BME and tear down the Thunderbolt DMAR tables at
ExitBootServices
+ in order to hand off security of TBT hierarchies to the OS.
+ The BIOS is expected to either: Disable BME from power on till the OS
starts configuring the devices and enabling BME Enable BME only for devices
that can be protected by VT-d in preboot environment,
+ but disable BME and tear down any Thunderbolt DMAR tables at
ExitBootServices()
+
+ @param[in] Event - A pointer to the Event that triggered the
callback.
+ @param[in] Context - A pointer to private data registered with the
callback function.
+**/
+VOID
+EFIAPI
+TbtDisableBmeCallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+/**
+ TBT Security SetDmarOptIn CallBackFunction
+
+ A new security feature will be supported to protect against Physical DMA
attacks over Thunderbolt connects.
+ In order to do this, they need a new flag added to the DMAR tables that a
DMA is only permitted into RMRR at ExitBootServices(). With this flag
available, OS can then Bug Check if any DMA is requested outside of the
RMRR before OS supported device drivers are started.
+ ReadyToBoot callback routine to update DMAR BIT2
+ Bit definition: DMA_CONTROL_GUARANTEE
+ If Set, the platform supports blocking all DMA outside of the regions
defined in the RMRR structures from ExitBootServices() until OS supported
device drivers are started.
+
+ @param[in] Event - A pointer to the Event that triggered the
callback.
+ @param[in] Context - A pointer to private data registered with the
callback function.
+**/
+VOID
+EFIAPI
+SetDmarOptInCallBackFunction (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+
+/**
+ The function install DisableBme protocol for TBT Shell validation
+**/
+VOID
+InstallDisableBmeProtocol (
+ VOID
+ );
+
+/**
+ Get or set Thunderbolt(TM) security mode
+
+ @param[in] DelayTime - The delay time after do ForcePwr
+ @param[in] SecurityMode - TBT Security Level
+ @param[in] Gpio3ForcePwrEn - Force GPIO to power on or not
+ @param[in] DTbtController - Enable/Disable DTbtController
+ @param[in] MaxControllerNumber - Number of contorller
+ @param[in] Action - 0 = get, 1 = set
+
+ @retval - Return security level
+**/
+UINT8
+EFIAPI
+GetSetSecurityMode (
+ IN UINTN DelayTime,
+ IN UINT8 SecurityMode,
+ IN UINT8 Gpio3ForcePwrEn,
+ IN UINT8 *DTbtController,
+ IN UINT8 MaxControllerNumber,
+ IN UINT8 Action
+);
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiC
heckIommuSupportLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiC
heckIommuSupportLib.h
new file mode 100644
index 0000000000..e069914cb4
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiC
heckIommuSupportLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiCheckIommuSupport library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+#define _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
+/**
+ Check Iommu Ability base on SKU type, CSME FW type, Vtd and setup
options.
+**/
+VOID
+PeiCheckIommuSupport (
+ VOID
+ );
+
+#endif // _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btPolicyLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btPolicyLib.h
new file mode 100644
index 0000000000..498f684696
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btPolicyLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Prototype of the PeiTbtPolicyLib library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_LIB_H_
+#define _PEI_TBT_POLICY_LIB_H_
+
+/**
+ Install Tbt Policy
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to
create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+InstallPeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update PEI TBT Policy Callback
+**/
+VOID
+EFIAPI
+UpdatePeiTbtPolicyCallback (
+ VOID
+ );
+
+/**
+ Print PEI TBT Policy
+**/
+VOID
+EFIAPI
+TbtPrintPeiPolicyConfig (
+ VOID
+ );
+#endif // _DXE_TBT_POLICY_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btTaskDispatchLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btTaskDispatchLib.h
new file mode 100644
index 0000000000..b1370e4064
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/PeiT
btTaskDispatchLib.h
@@ -0,0 +1,61 @@
+/** @file
+ PEI TBT Task Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__
+#define __PEI_TBT_TASK_DISPATCH_LIB_H__
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/PeiTbtPolicy.h>
+
+typedef
+EFI_STATUS
+(EFIAPI *TBT_TASK) (
+ PEI_TBT_POLICY *PeiTbtConfig
+);
+
+typedef enum {
+ TBT_NULL, ///< All policy flags turned off.
+ TBT_NORMAL = (1 << 0), ///< Execute TBT function on cold reset.
+ TBT_S3 = (1 << 1), ///< Execute TBT function on S3 exit.
+ TBT_S4 = (1 << 2), ///< Execute TBT function on S4 exit.
+ TBT_ALL = MAX_UINTN ///< Execute TBT function always.
+} TBT_BOOT_MODE;
+
+typedef struct {
+ TBT_TASK TbtTask; ///< Ptr to function to execute, with
parameter list.
+ TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on
TbtBootModeFlag
+ CHAR8 *String; ///< Output string describing this
task.
+} TBT_CALL_TABLE_ENTRY;
+
+/**
+ Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE
+**/
+TBT_BOOT_MODE
+TbtGetBootMode (
+ VOID
+);
+
+/**
+ TbtTaskDistpach: Dispatch the TBT tasks according to
TBT_CALL_TABLE_ENTRY
+
+ @param[in] TBT_CALL_TABLE_ENTRY TbtCallTable
+
+**/
+VOID
+TbtTaskDistpach (
+ IN TBT_CALL_TABLE_ENTRY *TbtCallTable
+);
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtC
ommonLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtC
ommonLib.h
new file mode 100644
index 0000000000..8d61d0623b
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Library/TbtC
ommonLib.h
@@ -0,0 +1,261 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_COMMON_LIB_H_
+#define _TBT_COMMON_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP 0 // @todo :
Update when once finalized
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_RP 0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP 0x07
+
+#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0
+#define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0
+#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D
+#define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02
+
+#define DTBT_CONTROLLER 0x00
+#define DTBT_TYPE_PCH 0x01
+#define DTBT_TYPE_PEG 0x02
+#define ITBT_CONTROLLER 0x80
+#define TBT2PCIE_ITBT_R 0xEC
+#define PCIE2TBT_ITBT_R 0xF0
+#define TBT2PCIE_DTBT_R 0x548
+#define PCIE2TBT_DTBT_R 0x54C
+
+#define INVALID_RP_CONTROLLER_TYPE 0xFF
+
+//
+// Thunderbolt FW OS capability
+//
+#define NO_OS_NATIVE_SUPPORT 0
+#define OS_NATIVE_SUPPORT_ONLY 1
+#define OS_NATIVE_SUPPORT_RTD3 2
+
+#define ITBT_SAVE_STATE_OFFSET BIT4 // Bits 4-7 is for ITBT
(HIA0/1/2/Reserved)
+#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 is
in use)
+/**
+Get Tbt2Pcie Register Offset
+
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@retval Register Register Variable
+**/
+
+#define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device,
Function, RegisterAddress) \
+ if (Type == ITBT_CONTROLLER) { \
+ RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
Function, TBT2PCIE_ITBT_R); \
+ } else { \
+ RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
Function, TBT2PCIE_DTBT_R); \
+ }
+
+/**
+Get Pcie2Tbt Register Offset
+
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@retval Register Register Variable
+**/
+
+#define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device,
Function, RegisterAddress) \
+ if (Type == ITBT_CONTROLLER) { \
+ RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
Function, PCIE2TBT_ITBT_R); \
+ } else { \
+ RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device,
Function, PCIE2TBT_DTBT_R); \
+ }
+
+#define PCIE2TBT_VLD_B BIT0
+#define TBT2PCIE_DON_R BIT0
+#define TBT_MAIL_BOX_DELAY (100*1000)
+#define TBT_5S_TIMEOUT 50
+#define TBT_1S_TIMEOUT 10
+#define TBT_3S_TIMEOUT 30
+
+#define PCIE2TBT_GO2SX (0x02 << 1)
+#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
+#define PCIE2TBT_OS_UP (0x06 << 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
+#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
+#define PCIE2TBT_BOOT_ON (0x18 << 1)
+#define PCIE2TBT_BOOT_OFF (0x19 << 1)
+#define PCIE2TBT_USB_ON (0x19 << 1)
+#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
+#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
+#define PCIE2TBT_POWER_CYCLE (0x1C << 1)
+#define PCIE2TBT_PREBOOTACL (0x1E << 1)
+#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
+
+#define RESET_HR_BIT BIT0
+#define ENUMERATE_HR_BIT BIT1
+#ifndef AUTO
+#define AUTO 0x0
+#endif
+
+//
+//Thunder Bolt Device IDs
+//
+
+//
+// Alpine Ridge HR device IDs
+//
+#define AR_HR_2C 0x1576
+#define AR_HR_4C 0x1578
+#define AR_XHC 0x15B5
+#define AR_XHC_4C 0x15B6
+#define AR_HR_LP 0x15C0
+//
+// Alpine Ridge C0 HR device IDs
+//
+#define AR_HR_C0_2C 0x15DA
+#define AR_HR_C0_4C 0x15D3
+//
+// Titan Ridge HR device IDs
+//
+#define TR_HR_2C 0x15E7
+#define TR_HR_4C 0x15EA
+//
+//End of Thunderbolt(TM) Device IDs
+//
+
+typedef struct _DEV_ID {
+ UINT8 Segment;
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+} DEV_ID;
+
+//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
+//@todo should refactor this to only be present in that driver
+//@todo also definitions like this should never be in a .h file anyway
+//@todo this is a quick hack to get things compiling for now
+#ifdef __GNUC__
+#pragma GCC diagnostic warning "-Wunused-variable"
+#endif
+
+/**
+Based on the Security Mode Selection, BIOS drives FORCE_PWR.
+
+@param[in] GpioNumber
+@param[in] Value
+**/
+VOID
+ForceDtbtPower(
+ IN UINT32 GpioNumber,
+ IN BOOLEAN Value
+);
+
+/**
+ Get Security Level.
+ @param[in] Type ITBT (0x80) or DTBT (0x00)
+ @param[in] Bus Bus number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Device Device number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Function Function number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+UINT8
+GetSecLevel (
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ );
+
+/**
+ Set Security Level.
+ @param[in] Data Security State
+ @param[in] Type ITBT (0x80) or DTBT (0x00)
+ @param[in] Bus Bus number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Device Device number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Function Function number for HIA (ITBT) or Host Router
(DTBT)
+ @param[in] Timeout Time out with 100 ms garnularity
+**/
+BOOLEAN
+SetSecLevel (
+ IN UINT8 Data,
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 Command,
+ IN UINT32 Timeout
+ );
+
+/**
+Execute TBT Mail Box Command
+
+@param[in] Command TBT Command
+@param[in] Type ITBT (0x80) or DTBT (0x00)
+@param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
+@param[in] Device Device number for HIA (ITBT) or Host Router
(DTBT)
+@param[in] Function Function number for HIA (ITBT) or Host Router
(DTBT)
+@param[in] Timeout Time out with 100 ms garnularity
+@Retval true if command executes succesfully
+**/
+BOOLEAN
+TbtSetPcie2TbtCommand(
+ IN UINT8 Command,
+ IN BOOLEAN Type,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT32 Timeout
+);
+/**
+ Check connected TBT controller is supported or not by DeviceID
+
+ @param[in] DeviceID DeviceID of of TBT controller
+
+
+ @retval TRUE Valid DeviceID
+ @retval FALSE Invalid DeviceID
+**/
+
+BOOLEAN
+IsTbtHostRouter (
+ IN UINT16 DeviceID
+ );
+
+/**
+ Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root
Port physical Number
+
+ @param[in] RpNumber Root port physical number.
(0-based)
+ @param[out] RpDev Return corresponding root port
device number.
+ @param[out] RpFun Return corresponding root port
function number.
+
+ @retval EFI_SUCCESS Root port device and function is
retrieved
+**/
+EFI_STATUS
+EFIAPI
+GetDTbtRpDevFun(
+ IN BOOLEAN Type,
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFunc
+ );
+
+/**
+ Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
+ @param[in] CommandOffsetAddress Tbt2Pcie Register Address
+ @param[in] TimeOut Time out with 100 ms
garnularity
+ @param[in] Tbt2PcieDone Wait condition (wait for Bit
to Clear/Set)
+ @param[out] *Tbt2PcieValue Function Register value
+**/
+BOOLEAN
+InternalWaitforCommandCompletion (
+ IN UINT64 CommandOffsetAddress,
+ IN UINT32 TimeOut,
+ IN BOOLEAN Tbt2PcieDone,
+ OUT UINT32 *Tbt2PcieValue
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPo
licy.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPo
licy.h
new file mode 100644
index 0000000000..1d42c4c578
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPo
licy.h
@@ -0,0 +1,31 @@
+/** @file
+TBT PEI Policy
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_TBT_POLICY_H_
+#define _PEI_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define PEI_TBT_POLICY_REVISION 1
+
+/**
+ TBT PEI configuration\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct _PEI_TBT_POLICY {
+ DTBT_COMMON_CONFIG DTbtCommonConfig;
///< dTbt Common Configuration
+ DTBT_CONTROLLER_CONFIG DTbtControllerConfig
[MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt Controller Configuration
+} PEI_TBT_POLICY;
+
+#pragma pack(pop)
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiDTbtInitLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiDTbtInitLib.h
new file mode 100644
index 0000000000..450d183c7f
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiDTbtInitLib.h
@@ -0,0 +1,130 @@
+/** @file
+ PEI DTBT Init Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_DTBT_INIT_LIB_H__
+#define __PEI_DTBT_INIT_LIB_H__
+
+#include <Private/Library/PeiTbtCommonInitLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+
+extern TBT_CALL_TABLE_ENTRY DTbtCallTable[];
+
+/**
+ Get Thunderbolt(TM) (TBT) PEI Policy Data.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtGetPeiTbtPolicyData (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Toggle related GPIO pin for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtToggleGPIO (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ set tPCH25 Timing to 10 ms for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSetTPch25Timing (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Do ForcePower for DTBT Controller
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtForcePower (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Clear VGA Registers for DTBT.
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtClearVgaRegisters (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "Boot On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtBootOn (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "USB On".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtUsbOn (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+/**
+ Exectue Mail box command "Sx Exit".
+
+ @param[in] PEI_TBT_POLICY PeiTbtConfig
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_UNSUPPORTED dTBT is not supported.
+**/
+EFI_STATUS
+EFIAPI
+DTbtSxExitFlow (
+ IN PEI_TBT_POLICY *PeiTbtConfig
+);
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiTbtCommonInitLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiTbtCommonInitLib.h
new file mode 100644
index 0000000000..aae88b2992
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Private/Libra
ry/PeiTbtCommonInitLib.h
@@ -0,0 +1,51 @@
+/** @file
+ PEI TBT Common Init Dispatch library Header file
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __PEI_TBT_COMMON_INIT_LIB_H__
+#define __PEI_TBT_COMMON_INIT_LIB_H__
+
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiTbtTaskDispatchLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TbtCommonLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/PmcLib.h>
+#include <PlatformNvRamHookLib.h>
+
+BOOLEAN
+IsHostRouterPresentBeforeSleep(
+IN UINT8 ControllerType,
+IN UINT8 Controller
+);
+
+VOID
+TbtSetSxMode(
+IN BOOLEAN Type,
+IN UINT8 Bus,
+IN UINT8 Device,
+IN UINT8 Function,
+IN UINT8 TbtBootOn
+);
+
+VOID
+TbtClearVgaRegisters(
+IN UINTN Segment,
+IN UINTN Bus,
+IN UINTN Device,
+IN UINTN Function
+);
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dis
ableBmeProtocol.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dis
ableBmeProtocol.h
new file mode 100644
index 0000000000..b64973db68
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dis
ableBmeProtocol.h
@@ -0,0 +1,36 @@
+/** @file
+ Definitions for DisableBmeProtocol
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DISABLE_TBT_BME_PROTOCOL_H_
+#define _DISABLE_TBT_BME_PROTOCOL_H_
+
+typedef struct EFI_DISABLE_BME_PROTOCOL
EFI_DISABLE_TBT_BME_PROTOCOL;
+
+/**
+ This is for disable TBT BME bit under shell environment
+
+ @param[in] Event - A pointer to the Event that triggered the
callback.
+ @param[in] Context - A pointer to private data registered with the
callback function.
+**/
+typedef
+VOID
+(EFIAPI *DISABLE_BUS_MASTER_ENABLE) (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+
+struct EFI_DISABLE_BME_PROTOCOL {
+ DISABLE_BUS_MASTER_ENABLE DisableBme;
+};
+
+extern EFI_GUID gDxeDisableTbtBmeProtocolGuid;
+
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dx
eTbtPolicy.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dx
eTbtPolicy.h
new file mode 100644
index 0000000000..0528c5ea3d
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Dx
eTbtPolicy.h
@@ -0,0 +1,137 @@
+/** @file
+TBT DXE Policy
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_TBT_POLICY_H_
+#define _DXE_TBT_POLICY_H_
+
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(push, 1)
+
+#define DXE_TBT_POLICY_REVISION 1
+
+//
+// TBT Common Data Structure
+//
+typedef struct _TBT_COMMON_CONFIG{
+ /**
+ TBT Security Level
+ <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure
Connect, 3: SL3 Display Port and USB
+ **/
+ UINT32 SecurityMode : 3;
+ /**
+ BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH
GPIOs
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Gpio5Filter : 1;
+ /**
+ WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TrA0OsupWa : 1;
+ /**
+ Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtWakeupSupport : 1;
+ /**
+ SMI TBT enumeration
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtHotSMI : 1;
+ /**
+ Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtHotNotify : 1;
+ /**
+ CLK REQ for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtSetClkReq : 1;
+ /**
+ ASPM setting for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
+ **/
+ UINT32 TbtAspm : 2;
+ /**
+ L1 SubState for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: L1.1, 2: L1.1 & L1.2
+ **/
+ UINT32 TbtL1SubStates : 2;
+ /**
+ LTR for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtLtr : 1;
+ /**
+ PTM for for all the PCIe device in TBT daisy chain.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtPtm : 1;
+ /**
+ TBT Dynamic AC/DC L1.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtAcDcSwitch : 1;
+ /**
+ TBT RTD3 Support.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Rtd3Tbt : 1;
+ /**
+ TBT ClkReq for RTD3 Flow.
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 Rtd3TbtClkReq : 1;
+ /**
+ TBT Win10support for Tbt FW execution mode.
+ <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
+ **/
+ UINT32 Win10Support : 2;
+ /**
+ TbtVtdBaseSecurity
+ <b>0: Disabled</b>, 1: Enabled
+ **/
+ UINT32 TbtVtdBaseSecurity: 1;
+ /**
+ Control Iommu behavior in pre-boot
+ <b>0: Disabled Iommu</b>, 1: Enable Iommu, Disable exception list, 2:
Enable Iommu, Enable exception list
+ **/
+ UINT32 ControlIommu : 3;
+ UINT32 Rsvd0 : 8; ///< Reserved bits
+ UINT16 Rtd3TbtClkReqDelay;
+ UINT16 Rtd3TbtOffDelay;
+} TBT_COMMON_CONFIG;
+
+//
+// dTBT Resource Data Structure
+//
+typedef struct _DTBT_RESOURCE_CONFIG{
+ UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe
RP that connect to dTBT Host Router
+ UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for
PCIe RP that connect to dTBT Host Router
+ UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM
resource for PCIe RP that connect to dTBT Host Router
+ UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for
PCIe RP that connect to dTBT Host Router
+ UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve
PMEM resource for PCIe RP that connect to dTBT Host Router
+ UINT8 Reserved[1]; ///< Reserved for DWORD alignment
+} DTBT_RESOURCE_CONFIG;
+
+/**
+ TBT DXE configuration\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct _DXE_TBT_POLICY_PROTOCOL {
+ TBT_COMMON_CONFIG TbtCommonConfig;
///< Tbt Common Information
+ DTBT_RESOURCE_CONFIG
DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt
Resource Configuration
+} DXE_TBT_POLICY_PROTOCOL;
+
+#pragma pack(pop)
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Tbt
NvsArea.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Tbt
NvsArea.h
new file mode 100644
index 0000000000..c2a366f3b1
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/Protocol/Tbt
NvsArea.h
@@ -0,0 +1,50 @@
+/** @file
+ This file defines the TBT NVS Area Protocol.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_NVS_AREA_H_
+#define _TBT_NVS_AREA_H_
+
+//
+// Platform NVS Area definition
+//
+#include <TbtNvsAreaDef.h>
+
+//
+// Includes
+//
+#define TBT_NVS_DEVICE_ENABLE 1
+#define TBT_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL;
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gTbtNvsAreaProtocolGuid;
+
+/**
+ Making any TBT_NVS_AREA structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.\n
+ <b>Revision 2</b>: - Adding TBT NVS AREA Revision, Deprecated
DTbtControllerEn0, DTbtControllerEn1.\n
+**/
+#define TBT_NVS_AREA_REVISION 2
+
+//
+// Platform NVS Area Protocol
+//
+typedef struct _TBT_NVS_AREA_PROTOCOL {
+ TBT_NVS_AREA *Area;
+} TBT_NVS_AREA_PROTOCOL;
+
+#endif // _TBT_NVS_AREA_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInf
o.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInf
o.h
new file mode 100644
index 0000000000..e595867d37
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInf
o.h
@@ -0,0 +1,23 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_INFO_GUID_H_
+#define _TBT_INFO_GUID_H_
+#include <TbtPolicyCommonDefinition.h>
+
+#pragma pack(1)
+//
+// TBT Info HOB
+//
+typedef struct _TBT_INFO_HOB {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ DTBT_COMMON_CONFIG DTbtCommonConfig;
///< dTbt Common Configuration
+ DTBT_CONTROLLER_CONFIG DTbtControllerConfig
[MAX_DTBT_CONTROLLER_NUMBER]; ///< dTbt Controller Configuration
+} TBT_INFO_HOB;
+#pragma pack()
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsArea
Def.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsArea
Def.h
new file mode 100644
index 0000000000..e84a0abd94
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtNvsArea
Def.h
@@ -0,0 +1,68 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // Define TBT NVS Area operation region.
+ //
+
+#ifndef _TBT_NVS_AREA_DEF_H_
+#define _TBT_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ UINT8 ThunderboltSmiFunction; ///< Offset 0
Thunderbolt(TM) SMI Function Number
+ UINT8 ThunderboltHotSmi; ///< Offset 1
SMI on Hot Plug for TBT devices
+ UINT8 TbtWin10Support; ///< Offset 2
TbtWin10Support
+ UINT8 TbtGpioFilter; ///< Offset 3
Gpio filter to detect USB Hotplug event
+ UINT8 ThunderboltHotNotify; ///< Offset 4
Notify on Hot Plug for TBT devices
+ UINT8 TbtSelector; ///< Offset 5
Thunderbolt(TM) Root port selector
+ UINT8 WAKFinished; ///< Offset 6
WAK Finished
+ UINT8 DiscreteTbtSupport; ///< Offset 7
Thunderbolt(TM) support
+ UINT8 TbtAcpiRemovalSupport; ///< Offset 8
TbtAcpiRemovalSupport
+ UINT32 TbtFrcPwrEn; ///< Offset 9
TbtFrcPwrEn
+ UINT32 TbtFrcPwrGpioNo0; ///< Offset 13
TbtFrcPwrGpioNo
+ UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17
TbtFrcPwrGpioLevel
+ UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18
TbtCioPlugEventGpioNo
+ UINT32 TbtPcieRstGpioNo0; ///< Offset 22
TbtPcieRstGpioNo
+ UINT8 TbtPcieRstGpioLevel0; ///< Offset 26
TbtPcieRstGpioLevel
+ UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27
Current Port that has plug event
+ UINT8 RootportSelected0; ///< Offset 28
Root port Selected by the User
+ UINT8 RootportSelected0Type; ///< Offset 29
Root port Type
+ UINT8 RootportSelected1; ///< Offset 30
Root port Selected by the User
+ UINT8 RootportSelected1Type; ///< Offset 31
Root port Type
+ UINT8 RootportEnabled0; ///< Offset 32
Root port Enabled by the User
+ UINT8 RootportEnabled1; ///< Offset 33
Root port Enabled by the User
+ UINT32 TbtFrcPwrGpioNo1; ///< Offset 34
TbtFrcPwrGpioNo
+ UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38
TbtFrcPwrGpioLevel
+ UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39
TbtCioPlugEventGpioNo
+ UINT32 TbtPcieRstGpioNo1; ///< Offset 43
TbtPcieRstGpioNo
+ UINT8 TbtPcieRstGpioLevel1; ///< Offset 47
TbtPcieRstGpioLevel
+ UINT8 TBtCommonGpioSupport; ///< Offset
48 Set if Single GPIO is used for Multi/Different Controller Hot plug
support
+ UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49
Root Port type for which SCI Triggered
+ UINT8 TrOsup; ///< Offset 50
Titan Ridge Osup command
+ UINT8 TbtAcDcSwitch; ///< Offset 51
TBT Dynamic AcDc L1
+ UINT8 DTbtControllerEn0; ///< Offset 52
DTbtController0 is enabled or not. @deprecated since revision 2
+ UINT8 DTbtControllerEn1; ///< Offset 53
DTbtController1 is enabled or not. @deprecated since revision 2
+ UINT8 TbtAspm; ///< Offset 54
ASPM setting for all the PCIe device in TBT daisy chain.
+ UINT8 TbtL1SubStates; ///< Offset 55
L1 SubState for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtSetClkReq; ///< Offset 56
CLK REQ for all the PCIe device in TBT daisy chain.
+ UINT8 TbtLtr; ///< Offset 57
LTR for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtPtm; ///< Offset 58
PTM for for all the PCIe device in TBT daisy chain.
+ UINT8 TbtWakeupSupport; ///< Offset 59
Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
+ UINT16 Rtd3TbtOffDelay; ///< Offset 60
Rtd3TbtOffDelay TBT RTD3 Off Delay
+ UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62
TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH
WakeB at Sx entry point. HW logic is required.
+ UINT8 Rtd3TbtSupport; ///< Offset 63
Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
+ UINT8 Rtd3TbtClkReq; ///< Offset 64
Enable TBT RTD3 CLKREQ mask.
+ UINT16 Rtd3TbtClkReqDelay; ///< Offset 65
TBT RTD3 CLKREQ mask delay.
+ //
+ // Revision Field:
+ //
+ UINT8 TbtRevision; ///< Offset 67
Revison of TbtNvsArea
+} TBT_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCo
mmonDefinition.h
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCo
mmonDefinition.h
new file mode 100644
index 0000000000..ae9d4f7a76
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCo
mmonDefinition.h
@@ -0,0 +1,84 @@
+/** @file
+TBT Policy Common definition.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_POLICY_COMMON_H_
+#define _TBT_POLICY_COMMON_H_
+
+#include <Library/GpioLib.h>
+#include <IndustryStandard/Pci22.h>
+
+#define MAX_DTBT_CONTROLLER_NUMBER 2
+
+#define TYPE_PCIE 0x01
+#define TYPE_PEG 0x02
+
+#pragma pack(push, 1)
+
+//
+// dTBT Force Power GPIO Data Structure
+//
+typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ BOOLEAN GpioLevel; ///< 0 = Active Low; 1 =
Active High
+ UINT8 Reserved[3]; ///< Reserved for DWORD
alignment
+} DTBT_FORCE_POWER_GPIO_CONFIG;
+
+//
+// dTBT CIO Plug Event GPIO Data Structure
+//
+typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will
change the XTBT method to the _Lxx or _Exx that we assign in this item.
+ BOOLEAN AcpiGpeSignaturePorting; ///< 0 = No porting
required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier
GPI GPE event architecture)
+ UINT8 Reserved[3]; ///< Reserved for DWORD
alignment
+} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
+
+//
+// dTBT PCIE Reset GPIO Data Structure
+//
+typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
+ GPIO_PAD GpioPad; ///< GPIO Pad Number
+ BOOLEAN GpioLevel; ///< 0 = Active Low; 1 =
Active High
+ UINT8 Reserved[3]; ///< Reserved for DWORD
alignment
+} DTBT_PCIE_RESET_GPIO_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_CONTROLLER_CONFIG {
+ UINT8 DTbtControllerEn; ///<
Enable/Disable DTbtController.
+ UINT8 Type; ///< 01-Pcie
RP, 02- PEG,Reserved. <Specific according to Board Design>
+ UINT8 PcieRpNumber; ///< RP
Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according
to Board Design>
+ DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The
GPIO pin that can force dTBT Power On. <Specific according to Board Design>
+ DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO
pin that can generate Hot-Plug event. <Specific according to Board Design>
+ DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO
pin that is use to perform Reset when platform enters to Sx, it is required for
platforms where PCI_RST pin connected to Tbt is controlled with GPIO
<Specific according to Board Design>
+ GPIO_PAD PdResetGpioPad; ///< PD
HRESET GPIO Pad Number
+ GPIO_PAD PdSxEntryGpioPad; ///< PD SX
Entry GPIO Pad Number
+ GPIO_PAD PdSxAckGpioPad; ///< PD SX
Ack GPIO Pad Number
+ UINT8 Reserved[1]; ///< Reserved
for DWORD alignment
+} DTBT_CONTROLLER_CONFIG;
+
+//
+// dTBT Controller Data Structure
+//
+typedef struct _DTBT_COMMON_CONFIG {
+ UINT8 TbtBootOn; ///< Send
BootOn Mailbox command when TbtBootOn is enabled.
+ UINT8 TbtUsbOn; ///< Send UsbOn
Mailbox command when TbtBootOn is enabled.
+ UINT8 Gpio3ForcePwr; ///< Force GPIO to
power on or not
+ UINT16 Gpio3ForcePwrDly; ///< The delay
time after do ForcePwr
+ BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT
controllers share the same GPIO pin <Specific according to Board Design>
+ BOOLEAN PcieRstSupport; ///< 0 = Not
Support, 1 = Supported. it is required for platforms where PCI_RST pin
connected to Tbt is controlled with GPIO
+ UINT8 SecurityMode; ///< 0: SL0 No
Security, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port
and USB
+ UINT8 ControlIommu; ///< Control
Iommu behavior in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable
exception list, 2: Enable Iommu, Enable exception list
+ UINT8 Reserved[3]; ///< Reserved for
DWORD alignment
+} DTBT_COMMON_CONFIG;
+
+#pragma pack(pop)
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
new file mode 100644
index 0000000000..4e0ff03f5f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl
@@ -0,0 +1,112 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Define a Global region of ACPI NVS Region that may be used for any
+ // type of implementation. The starting offset and size will be fixed
+ // up by the System BIOS during POST. Note that the Size must be a word
+ // in size to be fixed up correctly.
+
+ OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
+ Field(GNVS,AnyAcc,Lock,Preserve)
+ {
+ //
+ // Miscellaneous Dynamic Registers:
+ //
+ Offset(0), OSYS, 16, // Offset(0), Operating System
+ Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SMI
via I/O Trap)
+ Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value
+ Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode = 1)
+ //
+ // Thermal Policy Registers:
+ //
+ Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable
+ Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call
+ //
+ // CPU Identification Registers:
+ //
+ Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC
Enabled = 1)
+ Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads
+ //
+ // PCIe Hot Plug
+ //
+ Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control
+ Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value
+ //
+ // Global Variables
+ //
+ Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag.
+ Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt
Mode Flag.
+ Offset(16), L01C, 8, // Offset(16), Global L01 Counter.
+ Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting
Enable
+ Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting
Enable
+ Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting
Enable
+ Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting
Enable
+ Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting
Enable
+ Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting
Enable
+ Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting
Enable
+ Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting
Enable
+ Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting
Enable
+ Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting
Enable
+ Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting
Enable
+ Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting
Enable
+ Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting
Enable
+ Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting
Enable
+ Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting
Enable
+ Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting
Enable
+ Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting
Enable
+ Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting
Enable
+ Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting
Enable
+ Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting
Enable
+ Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting
Enable
+ Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting
Enable
+ Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting
Enable
+ Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting
Enable
+ Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and
Fill
+ Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and
Fill
+ Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and
Fill
+ Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and
Fill
+ Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and
Fill
+ Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and
Fill
+ Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and
Fill
+ Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and
Fill
+ Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and
Fill
+ Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and
Fill
+ Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and
Fill
+ Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and
Fill
+ Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and
Fill
+ Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and
Fill
+ Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and
Fill
+ Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and
Fill
+ Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and
Fill
+ Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and
Fill
+ Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and
Fill
+ Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and
Fill
+ Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and
Fill
+ Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and
Fill
+ Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and
Fill
+ Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and
Fill
+ Offset(65), RTD3, 8, // Offset(65), Runtime D3 support.
+ Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable
+ Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify
Sleep State Change
+ Offset(68), PSCP, 8, // Offset(68), P-state Capping
+ Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable
+ Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse
Enable
+ //
+ // Driver Mode
+ //
+ Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ
+ Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering CS
+ Offset(76), PLVL, 16, // Offset(76), PL1 limit value
+ Offset(78), PB1E, 8, // Offset(78), 10sec Power button support
+ Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr
+ Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support
+ Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug
+ Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port
selector
+ Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port
selector
+ }
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
new file mode 100644
index 0000000000..6755554c08
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
@@ -0,0 +1,118 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Define a Global region of ACPI NVS Region that may be used for any
+ // type of implementation. The starting offset and size will be fixed
+ // up by the System BIOS during POST. Note that the Size must be a word
+ // in size to be fixed up correctly.
+
+
+#ifndef _GLOBAL_NVS_AREA_DEF_H_
+#define _GLOBAL_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ //
+ // Miscellaneous Dynamic Registers:
+ //
+ UINT16 OperatingSystem; ///< Offset 0
Operating System
+ UINT8 SmiFunction; ///< Offset 2
SMI Function Call (ASL to SMI via I/O Trap)
+ UINT32 Port80DebugValue; ///< Offset 3
Port 80 Debug Port Value
+ UINT8 PowerState; ///< Offset 7
Power State (AC Mode = 1)
+ //
+ // Thermal Policy Registers:
+ //
+ UINT8 EnableDigitalThermalSensor; ///< Offset 8
Digital Thermal Sensor Enable
+ UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9
DTS SMI Function Call
+ //
+ // CPU Identification Registers:
+ //
+ UINT8 ApicEnable; ///< Offset 10
APIC Enabled by SBIOS (APIC Enabled = 1)
+ UINT8 ThreadCount; ///< Offset 11
Number of Enabled Threads
+ //
+ // PCIe Hot Plug
+ //
+ UINT8 PcieOSCControl; ///< Offset 12
PCIE OSC Control
+ UINT8 NativePCIESupport; ///< Offset 13
Native PCIE Setup Value
+ //
+ // Global Variables
+ //
+ UINT8 DisplaySupportFlag; ///< Offset 14
_DOS Display Support Flag.
+ UINT8 InterruptModeFlag; ///< Offset 15
Global IOAPIC/8259 Interrupt Mode Flag.
+ UINT8 L01Counter; ///< Offset 16
Global L01 Counter.
+ UINT8 LtrEnable[24]; ///< Offset 17
Latency Tolerance Reporting Enable
+ ///< Offset 18
Latency Tolerance Reporting Enable
+ ///< Offset 19
Latency Tolerance Reporting Enable
+ ///< Offset 20
Latency Tolerance Reporting Enable
+ ///< Offset 21
Latency Tolerance Reporting Enable
+ ///< Offset 22
Latency Tolerance Reporting Enable
+ ///< Offset 23
Latency Tolerance Reporting Enable
+ ///< Offset 24
Latency Tolerance Reporting Enable
+ ///< Offset 25
Latency Tolerance Reporting Enable
+ ///< Offset 26
Latency Tolerance Reporting Enable
+ ///< Offset 27
Latency Tolerance Reporting Enable
+ ///< Offset 28
Latency Tolerance Reporting Enable
+ ///< Offset 29
Latency Tolerance Reporting Enable
+ ///< Offset 30
Latency Tolerance Reporting Enable
+ ///< Offset 31
Latency Tolerance Reporting Enable
+ ///< Offset 32
Latency Tolerance Reporting Enable
+ ///< Offset 33
Latency Tolerance Reporting Enable
+ ///< Offset 34
Latency Tolerance Reporting Enable
+ ///< Offset 35
Latency Tolerance Reporting Enable
+ ///< Offset 36
Latency Tolerance Reporting Enable
+ ///< Offset 37
Latency Tolerance Reporting Enable
+ ///< Offset 38
Latency Tolerance Reporting Enable
+ ///< Offset 39
Latency Tolerance Reporting Enable
+ ///< Offset 40
Latency Tolerance Reporting Enable
+ UINT8 ObffEnable[24]; ///< Offset 41
Optimized Buffer Flush and Fill
+ ///< Offset 42
Optimized Buffer Flush and Fill
+ ///< Offset 43
Optimized Buffer Flush and Fill
+ ///< Offset 44
Optimized Buffer Flush and Fill
+ ///< Offset 45
Optimized Buffer Flush and Fill
+ ///< Offset 46
Optimized Buffer Flush and Fill
+ ///< Offset 47
Optimized Buffer Flush and Fill
+ ///< Offset 48
Optimized Buffer Flush and Fill
+ ///< Offset 49
Optimized Buffer Flush and Fill
+ ///< Offset 50
Optimized Buffer Flush and Fill
+ ///< Offset 51
Optimized Buffer Flush and Fill
+ ///< Offset 52
Optimized Buffer Flush and Fill
+ ///< Offset 53
Optimized Buffer Flush and Fill
+ ///< Offset 54
Optimized Buffer Flush and Fill
+ ///< Offset 55
Optimized Buffer Flush and Fill
+ ///< Offset 56
Optimized Buffer Flush and Fill
+ ///< Offset 57
Optimized Buffer Flush and Fill
+ ///< Offset 58
Optimized Buffer Flush and Fill
+ ///< Offset 59
Optimized Buffer Flush and Fill
+ ///< Offset 60
Optimized Buffer Flush and Fill
+ ///< Offset 61
Optimized Buffer Flush and Fill
+ ///< Offset 62
Optimized Buffer Flush and Fill
+ ///< Offset 63
Optimized Buffer Flush and Fill
+ ///< Offset 64
Optimized Buffer Flush and Fill
+ UINT8 Rtd3Support; ///< Offset 65
Runtime D3 support.
+ UINT8 LowPowerS0Idle; ///< Offset 66
Low Power S0 Idle Enable
+ UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67
Virtual GPIO button Notify Sleep State Change
+ UINT8 PstateCapping; ///< Offset 68
P-state Capping
+ UINT8 Ps2MouseEnable; ///< Offset 69
Ps2 Mouse Enable
+ UINT8 Ps2KbMsEnable; ///< Offset 70
Ps2 Keyboard and Mouse Enable
+ //
+ // Driver Mode
+ //
+ UINT32 GpioIrqRoute; ///< Offset 71
GPIO IRQ
+ UINT8 PL1LimitCS; ///< Offset 75
set PL1 limit when entering CS
+ UINT16 PL1LimitCSValue; ///< Offset 76
PL1 limit value
+ UINT8 TenSecondPowerButtonEnable; ///< Offset 78
10sec Power button support
+ UINT8 PciDelayOptimizationEcr; ///< Offset 79
Pci Delay Optimization Ecr
+ UINT8 TbtSupport; ///< Offset 80
Thunderbolt(TM) support
+ UINT8 TbtNativeOsHotPlug; ///< Offset 81
TbtNativeOsHotPlug
+ UINT8 TbtSelector; ///< Offset 82
Thunderbolt(TM) Root port selector
+ UINT8 TbtSelector1; ///< Offset 83
Thunderbolt(TM) Root port selector
+} EFI_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
new file mode 100644
index 0000000000..15c7853aa2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/AttemptUsbFirst.h
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ATTEMPT_USB_FIRST_H_
+#define _ATTEMPT_USB_FIRST_H_
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
+ UINT8 RevisonId; // Structure Revision ID
+ UINT8 HotkeyTriggered; // Hot key status
+} ATTEMPT_USB_FIRST_HOTKEY_INFO;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
+ UINT8 UsbBootPrior;
+} ATTEMPT_USB_FIRST_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for Attempt USB first features
+//
+#pragma pack(1)
+typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
+ UINT8 RevisonId; // Structure Revision ID
+ UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
+} ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
+#pragma pack()
+
+//
+// Volatile variable definition for third party Default Enabling via UEFI
Variable.
+//
+#pragma pack(1)
+typedef struct _ENABLE_CUSTOM_DEFAULTS{
+ UINT32 EnableCustomDefaults;
+} ENABLE_CUSTOM_DEFAULTS;
+#pragma pack()
+
+#define COENG_DEFAULTS_UNKNOWN 0
+#define COENG_DEFAULTS_SUPPORTED 1
+#define COENG_DEFAULTS_VAR_EXITS 2
+#define COENG_DEFAULTS_VAR_SET 4
+#define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED |
COENG_DEFAULTS_VAR_EXITS |COENG_DEFAULTS_VAR_SET)
+
+extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
+extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
new file mode 100644
index 0000000000..23b58fa1a2
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/CpuSmm.h
@@ -0,0 +1,57 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPUSMM_H_
+#define _CPUSMM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, { 0x8c, 0x77, 0xc8,
0x2f, 0xf1, 0xe, 0x3c, 0x81 }}
+#define CPUSMM_SETUP_NAME L"CpuSmm"
+
+#pragma pack(1)
+typedef struct {
+ UINT8 CpuSmmMsrSaveStateEnable;
+ UINT8 CpuSmmCodeAccessCheckEnable;
+ UINT8 CpuSmmUseDelayIndication;
+ UINT8 CpuSmmUseBlockIndication;
+ UINT8 CpuSmmUseSmmEnableIndication;
+ UINT8 CpuSmmProcTraceEnable;
+} CPU_SMM;
+#pragma pack()
+
+#ifndef OFFSET_OF
+#ifdef __GNUC__
+#if __GNUC__ >= 4
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
+#endif
+#endif
+#endif
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
+#define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8
_VerifyOffset##TYPE##Field[(OFFSET_OF(TYPE, Field) == Offset) /
(OFFSET_OF(TYPE, Field) == Offset)]
+
+//
+// If TpmSupport/MorStae isn't in this offset, build failure (0 size array or
divided by 0) will be generated.
+// Platform DSC file maps the two field to HII PCD so the offset value is
critical.
+//
+VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0);
+VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3);
+VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4);
+VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5);
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
new file mode 100644
index 0000000000..21598e85d4
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/FirwmareConfigurations.h
@@ -0,0 +1,20 @@
+/** @file
+ This header file provides definitions of firmware configuration.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FIRMWARE_CONFIGURATION_H_
+#define _FIRMWARE_CONFIGURATION_H_
+
+typedef enum {
+ FwConfigDefault = 0,
+ FwConfigProduction,
+ FwConfigTest,
+ FwConfigMax
+} FW_CONFIG;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
new file mode 100644
index 0000000000..cbd325fce6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/GopConfigLib.h
@@ -0,0 +1,1766 @@
+/** @file
+Header file for GOP Configuration Library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GOP_CONFIG_LIB_H_
+#define _GOP_CONFIG_LIB_H_
+
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#pragma pack(1)
+#define GOP_CONFIG_VBT_REVISION 0xC1
+
+#define ChildStruct_MAX 8 ///<
Maximum number of child structures in VBT
+#define CompressionStruct_MAX 2 ///<
Maximum number of compression parameter structures in VBT.
+#define NO_DEVICE 0x00 ///<
Defines a null display class.
+#define DISPLAY_PORT_ONLY 0x68C6 ///<
Defines a display class of Integrated Display Port Only
+#define DISPLAY_PORT_HDMI_DVI_COMPATIBLE 0x60D6 ///<
Defines a display class of Integrated DisplayPort with HDMI/DVI Compatible
+#define DISPLAY_PORT_DVI_COMPATIBLE 0x68D6 ///<
Defines a display class of Integrated DisplayPort with DVI Compatible
+#define HDMI_DVI 0x60D2 ///<
Defines a display class of Integrated HDMI/DVI
+#define DVI_ONLY 0x68D2 ///<
Defines a display class of Integrated DVI Only
+#define MIPI_ONLY 0x1400
+#define eDP_ONLY 0x1806 ///<
Defines a display class of eDP only
+#define AUX_CHANNEL_A 0x40
+#define AUX_CHANNEL_B 0x10
+#define AUX_CHANNEL_C 0x20
+#define AUX_CHANNEL_D 0x30
+#define NO_PORT 0x00 ///<
Defines a output port NA
+#define HDMI_B 0x01 ///<
Defines a output port HDMI-B
+#define HDMI_C 0x02 ///<
Defines a output port HDMI-C
+#define HDMI_D 0x03 ///<
Defines a output port HDMI-D
+#define HDMI_F 0x0E ///<
Defines a output port HDMI-D
+#define DISPLAY_PORT_A 0x0A ///<
Defines a output port DisplayPort A
+#define DISPLAY_PORT_B 0x07 ///<
Defines a output port DisplayPort B
+#define DISPLAY_PORT_C 0x08 ///<
Defines a output port DisplayPort C
+#define DISPLAY_PORT_D 0x09 ///<
Defines a output port DisplayPort D
+#define DISPLAY_PORT_E 0x0B ///<
Defines a output port DisplayPort E
+#define DISPLAY_PORT_F 0x0D ///<
Defines a output port DisplayPort F
+#define PORT_MIPI_A 0x15 ///< Mipi
Port A
+#define PORT_MIPI_C 0x17 ///< Mipi
Port C
+
+typedef struct {
+ UINT16 Dclk; // DClk in 10 KHz
+ UINT8 HActive; // HActive [7:0]
+ UINT8 HBlank; // HBlank [7:0]
+ UINT8 HA_HB_UpperNibble; // Upper nibble = HActive
[11:8]
+ UINT8 VActive; // VActive [7:0]
+ UINT8 VBlank; // VBlank [7:0]
+ UINT8 VA_VB_UpperNibble; // Upper nibble = VActive
[11:8]
+ UINT8 HSyncOffset; // HSync offset from blank
start LSB
+ UINT8 HPulseWidth; // HSync Pulse Width, LSB
+ UINT8 VsyncOffset_VpulseWidth_LSB; // Bits 7:4 = VSync offset [3:0]
+ UINT8 HSO_HSPW_V_High; // Bits 7:6 = HSync Offset
[9:8]
+ UINT8 HorImageSize; // Horizontal Image Size
+ UINT8 VerImageSize; // Vertical Image Size
+ UINT8 HIS_VIS_High; // UpperLmtH_V Upper limits
of H. and V. image size
+ UINT8 HBorder; // Horizontal Border
+ UINT8 VBorder; // Vertical Border
+ UINT8 Flags; // Flags
+} DTD_STRUCTURE; // 18 Bytes
+
+typedef struct {
+ UINT16 XRes;
+ UINT16 YRes;
+ UINT32 SerialNo;
+ UINT8 Week;
+ UINT8 Year;
+} PID_DATA; // 10 Bytes
+
+//
+// VBT Header
+//
+/**
+ This structure defines the VBT Header.
+**/
+typedef struct {
+ UINT8 Product_String[20]; ///< "$VBT_Cannonlake" is the product
string
+ UINT16 Version_Num; ///< Defines the VBT Header version
number.
+ UINT16 Header_Size; ///< Defines the size of VBT Header.
+ UINT16 Table_Size; ///< Defines the size of complete VBT.
+ UINT8 Checksum; ///< Defines the checksum of entire VBT
+ UINT8 Reserved1; ///< Reserved field 1 of 1 byte.
+ UINT32 Bios_Data_Offset; ///< Defines the offset of VBT Data block.
+ UINT32 Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks.
+} VBT_HEADER;
+
+/**
+ This structure defines the VBT BIOS Data Block Header
+**/
+typedef struct {
+ UINT8 BDB_Signature[16]; ///< Defines the Bios Data Block signature
"BIOS_DATA_BLOCK".
+ UINT16 BDB_Version; ///< Defines the VBT (data) version.
+ UINT16 BDB_Header_Size; ///< Defines the size of VBT Bios data
block header.
+ UINT16 BDB_Size; ///< Defines the size of Bios data block.
+} VBT_BIOS_DATA_HEADER;
+
+/**
+ This structure defines the BMP Signon Message and Copyright Message
Structure
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines Block ID : 254
+ UINT16 BlockSize; ///< Defines the size of BMP Signon block.
+
+ UINT16 Bmp_BIOS_Size; ///< Defines the BIOS size 32k/48k/64k.
+ UINT8 BIOS_Type; ///< Defines the type of BIOS desktop or
mobile.
+ UINT8 RelStatus; ///< Defines the release status of the
current GOP driver.
+ UINT8 BIOS_HW; ///< Defines the Hardware i.e.
Cannonlake.
+ UINT8 INT_HW; ///< Defines the integrated hardware
supported eDP/HDMI/DP.
+ UINT8 Build_Number[4]; ///< Defines the build number string.
+ UINT8 SignOn[155]; ///< Defines the sign on message.
+ UINT8 CopyRight[61]; ///< Defines the copyright message.
+} BMP_STRUCTURE_SIGNON;
+
+/**
+ This structure defines the BMP General Bits
+**/
+typedef struct {
+ UINT16 bmp_BIOS_CS; ///< Defines the start of BIOS code
segment
+ UINT8 bmp_DOS_Boot_Mode; ///< Defines the mode number to
set when DOS is boot
+ UINT8 bmp_BW_Percent; ///< Set percentage of total memory
BW
+ UINT8 bmp_Popup_Mem_Size; ///< Default Popup memory size in
KB
+ UINT8 bmp_Resize_PCI_BIOS; ///< BIOS size granularity in 0.5 KB
+ UINT8 Switch_CRT_To_DDC2; ///< Obsolete field: Is the CRT already
switched to DDC2
+ UINT8 bmp_Allow_Config; ///< Bit 1 : 1, Enable aspect ratio for
DOS
+ ///< Bit 0 : 1, Allow boot to DVI even if
it is not attached.
+} BMPGEN;
+
+/**
+ This structure defines Block 254 (BMP structure)
+**/
+typedef struct {
+ BMP_STRUCTURE_SIGNON bmp_Signon_Message; ///< Instance of
signon and copyright message structure
+ BMPGEN bmp_General_Bytes; ///< Instance of
BMP General Bits structure.
+} BLOCK254_BMP_Structure;
+
+/**
+ This structure defines Block 1 (General Bytes Definitions)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID (1)
+ UINT16 BlockSize; ///< Defines the size of General bytes definition
block.
+
+ /**
+ BMP General Bit Definitions 1\n
+ Bit 7 = DVO A color flip bit
+ = 0, No DVO A color flip
+ = 1, Flip DVO A color
+ Bits 6:4 = Clear screen (CLS) after Signon
+ = 000, No CLS
+ = 001, 0.5 sec pause and then CLS
+ = 010, 1.0 sec pause and then CLS
+ = 011, 1.5 sec pause and then CLS
+ = 100, 2.0 sec pause and then CLS
+ = 101, 2.5 sec pause and then CLS
+ = 110, 3.0 sec pause and then CLS
+ = 111, 3.5 sec pause and then CLS
+ Bit 3 = 1 Enable Display Signon
+ Bit 2 = 1 Enable Flex-aim Support
+ Bits 1:0 = Flat panel fitting enabling
+ = 00, Centering
+ = 01, Reserved
+ = 10, Aspect scaling
+ = 11, Fullscreen
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 PanelFitterEnabling:2;
+ UINT8 FlexAimSupportEnable:1;
+ UINT8 DisplaySignonEnable:1;
+ UINT8 ClearScreenTime:3;
+ UINT8 DvoAColorFlipEnable:1;
+ } Bits;
+ } bmp_Bits_1;
+
+ /**
+ BMP General Bit Definitions\n
+ Bit 7 = Hot plug support
+ = 0, Hot plug disabled
+ = 1, Hot plug enabled
+ Bit 6 = Dynamic CD clock feature
+ = 0, Dynamic CD clock feature is disabled
+ = 1, Dynamic CD clock feature is enabled
+ Bit 5 = Underscan support for VGA timings
+ Bit 4 = Disable SSC in Dual Display Twin Mode. (This field is obsolete now.
Kept for VBIOS only.)
+ = 0, No
+ = 1, Yes
+ Bit 3 = LFP power state on override by 5f64h,08h
+ = 0, No Override
+ = 1, Override
+ Bit 2 = Internal LVDS SSC frequency. (This field is obsolete now. Kept for
VBIOS only.)
+ = 0, 96/120MHz
+ = 1, 100MHz
+ Bit 1 = internal LVDS SSC (Spread Spectrum Clock) (This field is obsolete
now. Kept for VBIOS only.)
+ = 0, Disabled
+ = 1, Enabled
+ Bit 0 = KvmrSessionEnable.
+ = 0, Disabled
+ = 1, Enabled
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 KvmrSessionEnable:1;
+ UINT8 Reserved_1:5;
+ UINT8 DynamicCdClockEnable:1;
+ UINT8 HotPlugEnable:1;
+ } Bits;
+ } bmp_Bits_2;
+
+ /**
+ BMP General Bit Definitions 3\n
+ Bit 7 = Ignore strap status
+ = 0 Do not ignore
+ = 1 Ignore
+ Bit 6 = Panel Timing algorithm
+ = 0 Preferred timings
+ = 1 Best fit timings
+ Bit 5 Copy iLFP DTD to SDVO LVDS DTD
+ = 0 Don't copy DTD
+ = 1 Copy DTD to
+ Bit 4 = VBIOS normal/extd. DT mode
+ = 0 Normal mode
+ = 1 DUAL mode
+ Bit 3 = FDI RX Polarity
+ = 0 Normal
+ = 1 Inverted
+ Bit 2 = Enable 180 Degree Rotation
+ = 0 Disable
+ = 1 Enable
+ Bit 1 = Single DVI-I connector for CRT and DVI display: Obsolete field
+ = 0 Disabled
+ = 1 Enabled
+ Bit 0 = Smooth Vision
+ = 0 Disabled
+ = 1 Enabled
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 Reserved1:1;
+ UINT8 SingleDviiCrtConnector:1;
+ UINT8 Enable180DegRotation:1;
+ UINT8 FdiRxPolarity:1;
+ UINT8 Reserved2:4;
+ } Bits;
+ } bmp_Bits_3;
+
+ UINT8 Reserved; ///< Reserved field. It was
Legacy_Monitor_Detect in previous platforms.
+
+ /**
+ Integrated display device support\n
+ Bits 7:6 = Reserved
+ Bit 5 = DP SSC Dongle Enable/Disable
+ Bit 4 = DP SSC Frequency. (This field is obsolete now. Kept for VBIOS only.)
+ = 0, 96 MHz
+ = 1, 100 MHz
+ Bit 3 = DP SSC Enable
+ = 0, Disable
+ = 1, Enable
+ Bit 2 = Integrated EFP support
+ = 0, Disable
+ = 1, Enable
+ Bit 1 = Integrated TV support. (This field is obsolete now. Kept for VBIOS
only.)
+ = 0, Disable
+ = 1, Enable
+ Bit 0 = Integrated CRT support: Obsolete field
+ = 0, Disable
+ = 1, Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 CrtSupported:1;
+ UINT8 TvSupported:1;
+ UINT8 EfpSupported:1;
+ UINT8 DpSscEnable:1;
+ UINT8 DpSscFrequency:1;
+ UINT8 DpDongleSscEnable:1;
+ UINT8 Reserved1:2;
+ } Bits;
+ } Int_Displays_Support;
+} VBT_GENERAL1_INFO;
+
+/**
+ This defines the Structure of PRD Boot Table Entry
+**/
+typedef struct {
+ UINT8 AttachBits; ///< Bitmap representing the displays attached
currently.
+ UINT8 BootDev_PipeA; ///< Bitmap representing the display to boot on
Pipe A.
+ UINT8 BootDev_PipeB; ///< Bitmap representing the display to boot on
Pipe B.
+} PRD_TABLE;
+
+/**
+ This defines the structure of Block 254 (PRD Boot Table/Child Device List)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID (254)
+ UINT16 BlockSize; ///< Defines the size of Block 254
+
+ PRD_TABLE PRDTable[16]; ///< Defines the Child
device list for enumerating child handles.
+ UINT16 PRD_Boot_Table_Number_Of_Entries; ///< Number of entries
in child device list.
+} PRD_BOOT_TABLE;
+
+/**
+ This defines the Structure for a CHILD_STRUCT (used for all the displays).
+**/
+typedef struct {
+ UINT16 DeviceHandle; ///< Unique ID indicating the group of
display device (LFP/EFP1/EFP2/EFP3/EFP4).
+ UINT16 DeviceClass; ///< Indicates the class of display
device.
+ UINT8 I2CSpeed; ///< Defines the I2C speed to be used
for I2C transaction.
+ /**
+ Defines the DP on board redriver configuration.
+ BIT[7] : Reserved
+ BIT[6] : Is On Board DP Redriver Present
+ 0 : No
+ 1 : Yes
+ BIT[5:3] : On Board Redriver VSwing Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ BIT[2:0] : On Board Redriver PreEmph Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ **/
+ union{
+ UINT8 Value;
+ struct {
+ UINT8 OnBoardPreEmphLevel:3;
+ UINT8 OnBoardVSwingLevel:3;
+ UINT8 OnBoardRedriverPresent:1;
+ UINT8 Reserved:1;
+ } Bits;
+ } DpOnBoardRedriver;
+
+ /**
+ Defines the DP on dock redriver configuration.
+ BIT[7] : Reserved
+ BIT[6] : Is On Dock DP Redriver Present
+ 0 : No
+ 1 : Yes
+ BIT[5:3] : On Dock Redriver VSwing Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ BIT[2:0] : On Dock Redriver PreEmph Level
+ 0 : Level 0
+ 1 : Level 1
+ 2 : Level 2
+ 3 : Level 3
+ Others : Reserved
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 OnDockPreEmphLevel:3;
+ UINT8 OnDockVSwingLevel:3;
+ UINT8 OnDockRedriverPresent:1;
+ UINT8 Reserved:1;
+ } Bits;
+ } DpOnDockRedriver;
+
+ /**
+
+ Defines the HDMI level shifter configuration.
+ BIT[7:5] : Hdmi Maximum data rate
+ BIT[4:0] : Hdmi Level shifter value
+
+ **/
+ union{
+ UINT8 Value;
+ struct {
+ UINT8 HdmiLevelShifterValue:5;
+ UINT8 HdmiMaxDataRateBits:3;
+ } Bits;
+ } HdmiLevelShifterConfig;
+
+ UINT16 EFPDTDBufferPointer; ///< Pointer to the DTD timing to be
used in case of edidless EFP.
+
+ /**
+ Defines the first set of flags.
+ BIT[7-4] : Reserved
+ BIT[3] : Dual pipe ganged display support
+ 0 : Display uses a single pipe/port
+ 1 : Display uses two distinct pipes/ports.
+ BIT[2] : Compression Method Select
+ 0 : Compression using picture parameter set (PPS)
+ 1 : Compression using Capability parameter set (CPS)
+ BIT[1] : Compression enable/disable for this display.
+ 0 : Disabled
+ 1 : Enabled
+ BIT[0] : EDID less EFP Enable
+ 0 : Enable support for EDID less EFP.
+ 1 : Disable support for EDID less EFP.
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 EdidlessEfpEnable:1;
+ UINT8 CompressionEnable:1;
+ UINT8 CompressionMethod:1;
+ UINT8 IsDualPortEnabled:1;
+ UINT8 Reserved:4;
+ } Bits;
+ } Flags0;
+
+ /**
+ Defines the compression index field for the display.
+ BITS[7-4] : Reserved
+ BITS[3-0] : Compression Structure index in the block 55.
+ 0x0 : Index 0 in block 55
+ 0x1 : Index 1 in block 55
+ 0xF : Not Applicable.
+ Others : Reserved
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 IndexInBlock55:4;
+ UINT8 Reserved:4;
+ } Bits;
+ } CompressionStructureIndex;
+
+ UINT8 SlaveDdiPort; ///< The DVO port number of slave DDI
to be used in case Flags0[3] = 1.
+
+ UINT8 Reserved_1; ///< Reserved and might be used in
other platforms.
+ UINT16 AddInOffset; ///< Obsolete field.
+ UINT8 DVOPort; ///< Specifies the port number of the
display device represented in the device class.
+ UINT8 I2CBus; ///< Specifies the GMBUS or I2C pin
pair for add in card.
+ UINT8 SlaveAddr; ///< Specifies the I2C address of the
add in card.
+ UINT8 DDCBus; ///< Specifies the GMBUS pin pair for
EDID read.
+ UINT16 TimingInfoPtr; ///< Pointer to the buffer where VBIOS
stores the EDID of device.
+ UINT8 DVOCfg; ///< Obsolete field.
+
+ /**
+ Flags 1\n
+ Bits 7:5 : Reserved
+ Bit 4 : HPD Sense Invert
+ 0 : Invert not required (default)
+ 1 : Invert required
+ Bit 3 : IBoost feature enable/disable.
+ 0 : IBoost feature is disabled.
+ 1 : IBoost feature is enabled.
+ Bit 2 : Hdmi 2.0 Motherboard Downsuppotred options
+ 0 : Motherboard Down chip not supported
+ 1 : Motherboard Down Chip Supported on the Board
+ Bit 1 : Lane Reversal feature.
+ 0 : Disable
+ 1 : Enable
+ Bit 0 : DP/HDMI routed to dock.
+ 0 : Disable
+ 1 : Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 DockablePort:1;
+ UINT8 EnableLaneReversal:1;
+ UINT8 OnBoardLsPconDonglePresent:1;
+ UINT8 IBoostEnable:1;
+ UINT8 IsHpdInverted:1;
+ UINT8 Reserved:3;
+ } Bits;
+ } Flags_1;
+
+ UINT8 Compatibility; ///< Compatibility is used in VBIOS only.
It was used before device class was defined.
+ UINT8 AUX_Channel; ///< Specifies the aux channel to be
used for display port devices.
+ UINT8 Dongle_Detect; ///< Indicates whether dongle detect is
enabled or not.
+ UINT8 Capabilities; ///< Bits 1-0 indicate pipe capabilities
whether display can be used on one pipe or both the pipes.
+ UINT8 DVOWiring; ///< Obsolete field.
+ UINT8 MipiBridgeType; ///< MIPI bridge type
+ UINT16 DeviceClassExtension; ///< Obsolete.
+ UINT8 DVOFunction; ///< Obsolete.
+
+ /**
+ Flags 2
+ Bits 7:4 : DP Port trace length from silicon to output port on the board
+ 0 : Default RVP length
+ 1 : Short trace length
+ 2 : Long trace length
+ Bits 3:2 : Reserved
+ Bit 1 : Indicates whether this port is Thunderbolt port or not.
+ 0 : No
+ 1 : Yes
+ Bit 0 : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP
display
+ 0 : Disable
+ 1 : Enable
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 UsbTypeCDongleEnabled:1; ///< Indicates whether this
port is USB type C.
+ UINT8 IsThunderboltPort:1; ///< Indicates whether this
port is Thunderbolt. (ICL+)
+ UINT8 Reserved:2; ///< Reserved for future use.
+ UINT8 DpPortTraceLength:4; ///< Dp port trace length from
silicon to port.
+ } Bits;
+ } Flags_2;
+ UINT8 DP2XGpioIndex; ///< GPIO index number for the USB
type C.
+ UINT16 DP2XGpioNumber; ///< GPIO number for USB type C.
+
+ /**
+ IBoost magnitude field.
+ Bits 7:4 : DP Boost magnitude
+ 0 : 1
+ 1 : 3
+ 2 : 7
+ Others : Reserved for CML.
+ Bits 3:0 : HDMI Boost magnitude
+ 0 : 1
+ 1 : 3
+ 2 : 7
+ Others : Reserved.
+ **/
+ union {
+ UINT8 Value;
+ struct {
+ UINT8 DpEdpBoostMagnitude:4;
+ UINT8 HdmiBoostMagnitude:4;
+ } Bits;
+ } BoostMagnitude;
+} CHILD_STRUCT;
+
+/**
+ This structure defines Block 2 (General Bytes Definitions)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 2.
+ UINT16 BlockSize; ///< Defines the size of VBT General
Info 2 Block.
+
+ UINT8 bmp_CRT_DDC_GMBUS_Pin; ///< Obsolete field:
Selects the CRT DDC GMBUS pin pair.
+ UINT8 bmp_DPMS_Bits; ///< BMP DPMS Bit
Definitions.
+ UINT16 bmp_Boot_Dev_Bits; ///< BMP Boot Device Bit
Definitions.
+ UINT8 SizeChild_Struct; ///< Size of the ChildStruc
structure.
+
+ CHILD_STRUCT Child_Struct[ChildStruct_MAX]; ///< This array defines
all the supported child structures.
+} VBT_GENERAL2_INFO;
+
+/**
+ This defines the structure of Block 3 (Original Display Toggle List)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 3
+ UINT16 BlockSize; ///< Defines the size of Original
Display Toggle List Block
+ UINT8 bmp_Display_Detect; ///< Display must be attached or not
+} BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST;
+
+/**
+ This defines structure of a pointer table.
+**/
+typedef struct {
+ UINT16 Offset; ///< Defines the offset of the table from start of
BIOS Data block.
+ UINT16 Size; ///< Defines the size of an entry of the table.
+} BMP_TABLE_PTR;
+
+/**
+ This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers).
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 252.
+ UINT16 BlockSize; ///< Defines the size of SBIOS
Hooks block.
+ UINT8 SbiosHooks[18]; ///< This array defines a series of
SBIOS hooks. Each entry represents one hook.
+ BMP_TABLE_PTR BmpTablePtr[26]; ///< This array defines pointers to
all the important tables in the VBT.
+} BLOCK252_SBIOS_Hook;
+
+/**
+ This defines the structure of MMIO boot table entry
+**/
+typedef struct {
+ UINT32 Register; ///< Defines the MMIO offset of the register.
+ UINT32 Value; ///< Defines the default value of the register.
+} MMIO_BOOT_TABLE;
+
+/**
+ This structure defines Block 6 (MMIO Register Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 6
+ UINT16 BlockSize; ///< Defines the size of MMIO
Register Table block.
+ UINT16 RegTableId; ///< Defines the ID for MMIO
register table (0xFFFC).
+ UINT8 AccessFlag; ///< Defines the flag for data
access size (02 for 4 byte read/write).
+ MMIO_BOOT_TABLE MMIOBootTable[14]; ///< Array containing the
MMIO register table.
+ UINT16 TableEnd; ///< Special value describing
End of table (0xFFFF).
+} BLOCK06_MMIO_REG_TABLE;
+
+/**
+ This structure defines Block 7 (IO SW Flag Register Table)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines Block ID (7).
+ UINT16 BlockSize; ///< Defines the size of IO SW Flag register
table block.
+ UINT16 RegTableId; ///< Defines the ID for IO SW Flag register
table (0xFFFE).
+ UINT8 GRIndexRegLsb; ///< Defines the read/write size. Value is
0xCE meaning 1 byte without mask.
+ UINT8 IOSWFlagReg; ///< Defines the offset for the IO SW Flag
register.
+ UINT8 Value; ///< Defines the data/value for the register.
+ UINT16 TableEnd; ///< Special value describing the end of
table (0xFFFF).
+} BLOCK07_IOSWFLAG_REG_TABLE;
+
+/**
+ This structure defines the entry of SWF table.
+**/
+typedef struct {
+ UINT32 Register; ///< Defines the MMIO offset of the SWF register.
+ UINT32 Value; ///< Defines the default value for the SWF register.
+} SWF_TABLE;
+
+/**
+ This defines the structure of Block 8 (MMIO SW Flag Block).
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the Block ID : 8.
+ UINT16 BlockSize; ///< Defines the size of MMIO SWF register
table block.
+ UINT16 RegTableId; ///< Defines the ID for MMIO SWF register
table (0xFFFC).
+ UINT8 AccessFlag; ///< Defines the data access size. Value is 0x02
meaning 4 bytes read/write.
+ SWF_TABLE SWFTable[7]; ///< Array containing the MMIO SWF register
table.
+ UINT16 TableEnd; ///< Special value describing end of table
(0xFFFF).
+} BLOCK08_MMIOSWFLAG_REG_TABLE;
+
+/**
+ This structure defines the PSR feature table entry.
+**/
+typedef struct {
+ UINT8 SRD_Enables; ///< Defines PSR features such as full link
enable/disable and whether aux is required to wake up.
+ UINT8 SRD_WaitTimes; ///< Defines lines to wait before link
standby and idle frames to wait before SRD enable.
+ UINT16 SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of
100.
+ UINT16 SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples
of 100
+} PSR_FEATURE_TABLE;
+
+/**
+ This defines the structure of Block 9 (PSR Features Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the block ID :
9
+ UINT16 BlockSize; ///< Defines the size of PSR
Feature block.
+ PSR_FEATURE_TABLE PSRFeatureTable[16]; ///< Array containing the PSR
Feature table.
+} BLOCK09_PSR_FEATURE;
+
+/**
+ This structure defines an entry of Mode Removal table.
+**/
+typedef struct {
+ UINT16 XRes; ///< X resolution of the mode.
+ UINT16 YRes; ///< Y resolution of the mode.
+ UINT8 Bpp; ///< Bits per pixel of the mode.
+ UINT16 RRate; ///< Refresh rate of the mode.
+ UINT8 RFlags; ///< Flags specifying display type and functional
area where the mode is to be removed.
+ UINT16 PanelFlags; ///< Applicable to LFP only. Indicates which LFP
panels the mode is to be removed.
+} MODE_REMOVAL_TABLE_ENTRY;
+
+/**
+ This defines the structure of Block 10 (Mode Removal Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the
Block ID : 10.
+ UINT16 BlockSize; ///< Defines the
size of Mode Removal table block.
+ UINT8 EntrySize; ///< Defines the
size of one entry of mode removal table.
+ MODE_REMOVAL_TABLE_ENTRY ModeRemovalTable[20]; ///< Array
containing the mode removal table.
+ UINT16 Terminator; ///< Special value
indicating end of mode removal table (0xFFFF).
+} BLOCK10_MODE_REMOVAL_TABLE;
+
+/**
+ This defines the structure of Block 12 (Driver Features Data Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID :
12
+ UINT16 BlockSize; ///< Defines the size of Driver
features block.
+
+ /**
+ This field defines the various driver related bits:\n
+ Bit 7 = Use 00000110h ID for Primary LFP
+ = 0, No
+ = 1, Yes
+ Bit 6 = Enable/Disable Sprite in Clone Mode
+ = 0, Disable
+ = 1, Enable
+ Bit 5 = Driver INT 15h hook
+ = 0, Disable
+ = 1, Enable
+ Bit 4 = Dual View Zoom
+ = 0, Disable
+ = 1, Enable
+ Bit 3 = Hot Plug DVO
+ = 0, Disable
+ = 1, Enable
+ Bit 2 = Allow display switching when in Full Screen DOS.
+ = 0, Block Display Switching
+ = 1, Allow Display Switching
+ Bit 1 = Block display switching when DVD active
+ = 0, No Block Display Switching
+ = 1, Block Display Switching
+ Bit 0 = Boot device algorithm
+ = 0, OS Default
+ = 1, Driver Default
+ **/
+ UINT8 bmp_Driver_Bits;
+ UINT16 bmp_Driver_Boot_Mode_X; ///< X resolution of driver boot
mode.
+ UINT16 bmp_Driver_Boot_Mode_Y; ///< Y resolution of driver boot
mode.
+ UINT8 bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot
mode.
+ UINT8 bmp_Driver_Boot_Mode_RR; ///< Refresh rate of driver boot
mode.
+
+ /**
+ This field defines the extended driver bits 1.\n
+ Bits [15:14] = Integrated HDMI configuration
+ = 00b, No Integrated HDMI
+ = 01b, Port-B Only
+ = 10b, Port-C Only
+ = 11b, Both Port-B and Port-C
+ Bits 13 = TV Hotplug
+ Bits [12:11] = LFP configuration
+ = 00b, No LVDS
+ = 01b, Integrated LVDS
+ = 10b, SDVO LVDS
+ = 11b, eDP
+ Bit 10 = Obsolete field: CRT hotplug
+ = 0, Disabled
+ = 1, Enabled (Default)
+ Bit 9 = SDVO device power down
+ = 0, Disabled (Default)
+ = 1, Enabled
+ Bit 8 = Preserve Aspect Ratio
+ = 0, Disabled (Default)
+ = 1, Enabled
+ Bit 7 = Display "Maintain Aspect Scaling" via CUI
+ = 0, No
+ = 1, Yes (Default)
+ Bit 6 = Sprite Display Assignment when Overlay is Active in Clone Mode:
+ = 0, Secondary
+ = 1, Primary
+ Bit 5 = Default Power Scheme user interface
+ = 0, CUI
+ = 1, 3rd Party Application
+ Bit 4 = NT 4.0 Dual Display Clone Support
+ = 0, Disable
+ = 1, Enable
+ Bit 3 = Default Render Clock Frequency
+ = 0, High Frequency
+ = 1, Low Frequency
+ Bit 2 = Dual-Frequency Graphics Technology
+ = 0, No
+ = 1, Yes
+ Bit 1 = Selective Mode Pruning
+ = 0, No
+ = 1, Yes
+ Bit 0 = Enable LFP as primary
+ = 0, Disable
+ = 1, Enable
+**/
+ UINT16 bmp_Ext_Driver_Bits;
+
+ /**
+ This defines the driver flags related to CUI Hot key.\n
+ Bits [7:3] - Reserved
+ Bit 2 = Display Subsystem Enable/Disable
+ = 0, Enable (default Value)
+ = 1, Disable
+ Bit 1 = Embedded Platform
+ = 0, False
+ = 1, True
+ Bit 0 = Define CUI HotK Displays Statically
+ = 0, No
+ = 1, Yes
+ **/
+ UINT8 bmp_Display_Detect_CUIHotK;
+
+ UINT16 bmp_Legacy_CRT_Max_X; ///< Obsolete field: Defines
the legacy CRT X resolution for driver boot mode.
+ UINT16 bmp_Legacy_CRT_Max_Y; ///< Obsolete field: Defines
the legacy CRT Y resolution for driver boot mode.
+ UINT8 bmp_Legacy_CRT_Max_RR; ///< Obsolete field:
Defines the legacy CRT refresh rate for driver boot mode.
+
+ /**
+ This field defines the extended driver bits 2.\n
+ Bits [7:1] - Reserved
+ Bit 0 = Enable Internal Source Termination for HDMI
+ = 0, External Termination
+ = 1, Internal Termination
+ **/
+ UINT8 bmp_Ext2_Driver_Bits;
+
+ UINT8 bmp_VBT_Customization_Version; ///< Defines the customized
VBT version number.
+
+ /**
+ This field defines all the driver feature flags.\n
+ Bit 15 = PC Features Field's Validity
+ = 0, Invalid
+ = 1, Valid
+ Bit 14 = Hpd_wake - HPD events are routed to display driver when system
is in S0ix/DC9
+ = 0, Disable
+ = 1, Enable
+ Bit 13 = Assertive Display Technology (ADT)
+ = 0, Disable
+ = 1, Enable
+ Bit 12 = Dynamic Media Refresh Rate Switching (DMRRS)
+ = 0, Disable
+ = 1, Enable
+ Bit 11 = Dynamic Frames Per Second (DFPS)
+ = 0, Disable
+ = 1, Enable
+ Bit 10 = Intermediate Pixel Storage (IPS)
+ = 0, Disable
+ = 1, Enable
+ Bit 9 = Panel Self Refresh (PSR)
+ = 0, Disable
+ = 1, Enable
+ Bit 8 = Intel Turbo Boost Technology
+ = 0, Disable
+ = 1, Enable
+ Bit 7 = Graphics Power Modulation Technology (GPMT)
+ = 0, Disable
+ = 1, Enable
+ Bit 6 = Graphics Render Standby (RS)
+ = 0, Disable
+ = 1, Enable
+ Bit 5 = Intel Display Refresh Rate Switching (DRRS)
+ = 0, Disable
+ = 1, Enable
+ Bit 4 = Intel Automatic Display Brightness (ADB)
+ = 0, Disable
+ = 1, Enable
+ Bit 3 = DxgkDDI Backlight Control (DxgkDdiBLC)
+ = 0, Disable
+ = 1, Enable
+ Bit 2 = Intel Display Power Saving Technology (DPST)
+ = 0, Disable
+ = 1, Enable
+ Bit 1 = Intel Smart 2D Display Technology (S2DDT)
+ = 0, Disable
+ = 1, Enable
+ Bit 0 = Intel Rapid Memory Power Management (RMPM)
+ = 0, Disable
+ = 1, Enable
+ **/
+ UINT16 bmp_Driver_Feature_Flags;
+} BLOCK12_DRIVER_FEATURES;
+
+/**
+ This defines the structure of Block 13 (Driver Persistence Options)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 13
+ UINT16 BlockSize; ///< Defines the size of Driver
Persistence options block.
+
+ /**
+ Defines the various persistence options.\n
+ Bits [15:10] - Reserved
+ Bit 9 = Docking Persistence Algorithm
+ = 0, OS Default
+ = 1, Driver Default
+ Bit 8 = DVO Hot Plug Persistence on Mode
+ Bit 7 = EDID Persistence on Mode
+ Bit 6 = Hot Key Persistence on Mode
+ = 0, No
+ = 1, Yes
+ Bit 5 = Hot Key Persistence on RestorePipe
+ = 0, No
+ = 1, Yes
+ Bit 4 = Hot Key Persistence on RefreshRate
+ = 0, No
+ = 1, Yes
+ Bit 3 = Hot Key Persistence on MDS/Twin
+ = 0, No
+ = 1, Yes
+ Bit 2 = Power Management Persistence Algorithm
+ = 0, OS Default
+ = 1, Driver Default
+ Bit 1 = Lid Switch Persistence Algorithm
+ = 0, OS Default
+ = 1, Driver Default
+ Bit 0 = Hot Key Persistence Algorithm
+ = 0, OS Default
+ = 1, Driver Default
+ **/
+ UINT16 PersistenceAlgorithm;
+
+ UINT8 PersistMaxconfig; ///< Maximum mode persistence
configurations (10-200)
+} BLOCK13_DRIVER_PERSISTENCE;
+
+/**
+ This defines the structure of Block 17 (SV Bits)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defnies the unique Block ID : 17
+ UINT16 BlockSize; ///< Defines the size of SV Bits block.
+
+ /**
+ Bits [7:4] = Reserved
+ Bit3 = Allow VBlank/VblankScanline timeout hang
+ = 0, Disable
+ = 1, Enable
+ Bit2 = Special GMBus support
+ = 0, Disable
+ = 1, Enable
+ Bit1 = Skip program pipe timings when set VGA modes
+ = 0, Setmode skip DVO Update
+ = 1, Setmode updates DVO
+ Bit0 = Disable VGA fast arbiter
+ = 0, Enabled
+ = 1, Disabled
+ **/
+ UINT8 SvBits1;
+ UINT8 SvBits2; ///< Reserved for future use.
+ UINT8 SvBits3; ///< Reserved for future use.
+ UINT8 SvBits4; ///< Reserved for future use.
+ UINT8 SvBits5; ///< Reserved for future use.
+ UINT8 SvBits6; ///< Reserved for future use.
+ UINT8 SvBits7; ///< Reserved for future use.
+ UINT8 SvBits8; ///< Reserved for future use.
+} BLOCK17_SV_BITS;
+
+/**
+ This defines the structure of Block 18 (Driver Rotation)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block
ID : 18
+ UINT16 BlockSize; ///< Defines the size of Driver
Rotation block.
+ UINT8 RotationFeatureSupport; ///< Rotation feature support
field used by driver.
+ UINT8 Reserved1; ///< Reserved for future use.
+ UINT16 Reserved2; ///< Reserved for future use.
+ UINT32 Reserved3; ///< Reserved for future use.
+ UINT32 Reserved4; ///< Reserved for future use.
+} BLOCK18_DRIVER_ROTATION;
+
+/**
+ This structure defines an entry of OEM mode table.
+**/
+typedef struct {
+ /**
+ Mode Flags:
+ Bits[7:3] = Reserved
+ Bit 2 = Enable/disable this OEM mode in GOP driver.
+ Bit 1 = Enable/disable this mode in Driver
+ Bit 0 = Enable/disable this mode in VBIOS
+ **/
+ UINT8 ModeFlags;
+
+ /**
+ Display Device Flags:
+ Bit 7 = LFP2
+ Bit 6 = EFP2
+ Bit 5 = EFP3
+ Bit 4 = EFP4
+ Bit 3 = LFP
+ Bit 2 = EFP
+ Bit 1 = Rsvd
+ Bit 0 = Rsvd
+ **/
+ UINT8 DisplayFlags;
+ UINT16 XRes; ///< Defines the X resolution of the mode.
+ UINT16 YRes; ///< Defines the Y resolution of the mode.
+
+ /**
+ Defines the bits per pixel of the mode.
+ Bit 7:3 = Reserved
+ Bit 2 = 32 BPP
+ Bit 1 = 16 BPP
+ Bit 0 = 8 BPP
+ **/
+ UINT8 Bpp;
+ UINT8 RRate; ///< Defines the refresh rate of the mode.
+ DTD_STRUCTURE Dtd; ///< Defines the 18 byte timing config for the
mode.
+} OEM_MODE_ENTRY;
+
+/**
+ This defines the structure of Block 20 (OEM Mode Customization Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block ID :
20
+ UINT16 BlockSize; ///< Defines the size of OEM
customization block.
+ UINT8 NumOfEntry; ///< Defines the number of
entries in OEM Mode table.
+ UINT8 EntrySize; ///< Defines the size of one entry
of OEM Mode table.
+ OEM_MODE_ENTRY OemModeTable[6]; ///< Array defining the OEM
mode table.
+} BLOCK20_OEM_CUSTOMIZATION;
+
+/**
+ This defines the structure of Block 26 (TV options)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID :
26
+ UINT16 BlockSize; ///< Defines the size of TV Options
block.
+
+ /**
+ Defines the TV options:
+ Bit 15 = D-Conector Support
+ = 0, Disable
+ = 1, Enable
+ Bit 14 = Add 1776x1000 when 1080i is selected and add 1184x666 when
720p is selected
+ = 0, Disable
+ = 1, Enable
+ Bit 13:12 Underscan/overscan for HDTV via DVI
+ = 00b, Enable Underscan and Overscan modes (Default)
+ = 01b, Enable only overscan modes
+ = 10b, Enable only underscan modes
+ Bits 11:2 = Reserved
+ Bit 1:0 = Underscan/overscan for HDTV via Component (YPrPb)
+ = 00b, Enable Underscan and Overscan modes (Default)
+ = 01b, Enable only overscan modes
+ = 10b, Enable only underscan modes
+ **/
+ UINT16 bmp_TV_Options_1;
+} BLOCK26_TV_OPTIONS;
+
+/**
+ This structure defines the eDP panel power sequencing parameters.
+**/
+typedef struct {
+ UINT16 T3; ///< Panel Power-Up Delay.
+ UINT16 T8; ///< Panel Power-On to backlight Enable Delay.
+ UINT16 T9; ///< Backlight-Off to Power-Down Delay.
+ UINT16 T10; ///< Power-Down Delay.
+ UINT16 T12; ///< Power Cycle Delay.
+} EDP_PWR_SEQ;
+
+/**
+ This structure defines the PWM<-->Backlight delays for a single eDP panel.
+**/
+typedef struct {
+ UINT16 PwmOnToBacklightEnableDelay; ///< PWM on to backight
enable delay.
+ UINT16 BacklightDisableToPwmOffDelay; ///< Backlight disable to
PWM off delay.
+} EDP_PWM_BACKLIGHT_DELAYS;
+
+/**
+ This defines FLT parameters for a single eDP panel.
+ Bits[15:12] : VSwing level
+ 0 : 0.4V (default)
+ 1 : 0.6V
+ 2 : 0.8V
+ 3 : 1.2V
+ Others : Reserved
+ Bits[11:8] : Pre-emphasis level
+ 0 : no pre-emphasis (default)
+ 1 : 3.5dB
+ 2 : 6dB
+ 3 : 9.5dB
+ Others : Reserved
+ Bits[7:4] : Lane count (port width)
+ 0 : x1 mode (default)
+ 1 : x2 mode
+ 2 : Reserved
+ 3 : x4 mode
+ Others : Reserved
+ Bits[3:0] : data rate
+ 0 : 1.62 Gbps
+ 1 : 2.7 Gbps
+ 2 : 5.4 Gbps
+ Others : Reserved
+**/
+typedef union {
+ UINT16 Value;
+ struct {
+ UINT16 DataRate:4;
+ UINT16 LaneCount:4;
+ UINT16 PreEmphasisLevel:4;
+ UINT16 VSwingLevel:4;
+ } Bits;
+} EDP_FAST_LINK_TRAINING_PARAMS;
+
+/**
+ This defines Full link training parameters for a single eDP panel.
+ Bits[7:4] : VSwing level
+ 0 : 0.4V (default)
+ 1 : 0.6V
+ 2 : 0.8V
+ 3 : 1.2V
+ Others : Reserved
+ Bits[3:0] : Pre-emphasis level
+ 0 : no pre-emphasis (default)
+ 1 : 3.5dB
+ 2 : 6dB
+ 3 : 9.5dB
+ Others : Reserved
+**/
+typedef union {
+ UINT8 Value;
+ struct {
+ UINT8 PreEmphasisLevel:4;
+ UINT8 VSwingLevel:4;
+ } Bits;
+} EDP_FULL_LINK_TRAINING_PARAMS;
+
+/**
+ This defines the structure of Apical Parameters for a single eDP panel.
+**/
+typedef struct {
+ UINT32 PanelOui; ///< Apical IP specific field for
Panel OUI
+ UINT32 DPCDBaseAddress; ///< Apical IP specific field for
DPCD Base address
+ UINT32 DPCDIrdidixControl0; ///< Apical IP specific field for DPCD
Idridix Control 0
+ UINT32 DPCDOptionSelect; ///< Apical IP specific field for
DPCD option select
+ UINT32 DPCDBacklight; ///< Apical IP specific field for
DPCD backlight
+ UINT32 AmbientLight; ///< Apical IP specific field for
Ambient light
+ UINT32 BacklightScale; ///< Apical IP specific field for
backlight scale
+} EDP_APICAL_PARAMS;
+
+/**
+ This defines the structure of Block 27 (eDP Display Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 27
+ UINT16 BlockSize; ///< Defines the size of eDP display
VBT block.
+
+ EDP_PWR_SEQ eDP_PWR_SEQ[16]; ///< Array defining the panel
power sequencing for all 16 eDP panels.
+
+ /**
+ Defines the panel color depth in bits per pixel. 2 Bits for each Panel.
+ Bits[1:0] Panel color depth for Panel #1
+ = 00, 18bpp
+ = 01, 24bpp
+ = 10, 30bpp
+ = 11, 36bpp
+ **/
+ UINT32 eDP_Panel_Color_Depth;
+
+ /**
+ Array containing the FLT parameters of 16 eDP panels.
+ **/
+ EDP_FAST_LINK_TRAINING_PARAMS
eDP_Fast_Link_Training_Params[16];
+
+ /**
+ This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels. 2
Bits for Each Panel.
+ Bits[1:0] for Panel #1
+ = 00, Line 1
+ = 01, Line 2
+ = 10, Line 3
+ = 11, Line 4
+ **/
+ UINT32 eDP_sDRRS_MSA_Delay;
+
+ /**
+ Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for Each
Panel.
+ Bits[0] for Panel #1
+ = 0, S3D disabled for this panel
+ = 1, S3D enabled for this panel
+ **/
+ UINT16 eDP_S3D_Feature;
+
+ /**
+ Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for each
panel.
+ Bits[0] = Panel #1
+ = 0, T3 optimization disabled for this panel
+ = 1, T3 optimization enabled for this panel
+ **/
+ UINT16 eDP_T3_Optmization;
+
+ /**
+ Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Each
Panel
+ Bits[3:0] = Panel #1
+ = 0, Use table 1 for this panel.
+ = 1, Use table 2 for this panel.
+ **/
+ UINT64 VswingPreEmphasisTableNum;
+
+ /**
+ Defines the Edp fast link training support on all 16 panels. 1 Bit for Each
Panel
+ Bits[0] = Panel #1
+ = 0, FastLinkTraining feature is disabled for this panel
+ = 1, FastLinkTraining feature is enabled for this panel
+ **/
+ UINT16 EdpFastLinkTrainingSupportOnPanel;
+
+ /**
+ Defines whether the Set power state at DPCD 600h is to be done in eDP
enable/disable sequence.
+ Bits[0] = Panel #1
+ = 0, Set power state at DPCD 600h feature is disabled for this panel
+ = 1, Set power state at DPCD 600h feature is enabled for this panel
+ **/
+ UINT16 SetPowerStateAtDPCD600h; //This is not used currently
+
+ /**
+ Array defining the PWM <--> Backlight related delays for 16 panels.
+ **/
+ EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16];
+
+ /**
+ Defines the Edp full link training support on all 16 panels. 1 Bit for Each
Panel.
+ \verbatim
+ Bits[0] : Panel #1
+ 0 : Initial vswing and pre-emphasis levels are not provided for Full
link training
+ 1 : Initial vswing and pre-emphasis levels are provided for Full link
training
+ Bits 1 to 15 are for panel # 2 to 16.
+ \endverbatim
+ **/
+ UINT16 InitialFullLinkTrainingParamsProvidedInVbt;
+
+ /**
+ Array containing the initial Vswing and Pre-emphasis parameters for Full
link training.
+ **/
+ EDP_FULL_LINK_TRAINING_PARAMS
eDP_Full_Link_Training_Params[16];
+
+ /**
+ Defines the Edp Apical assertive display IP support on all 16 panels. 1 Bit
for Each Panel.
+ Bit 0 : Panel #1
+ 0 : Apical assertive display IP is disabled for this panel.
+ 1 : Apical assertive display IP is enabled for this panel.
+ Bits 1 to 15 are for panel # 2 to 16.
+ **/
+ UINT16 IsApicalAssertiveDisplayIpEnable;
+
+ /**
+ Array containing the Apical parameters for all 16 panels
+ **/
+ EDP_APICAL_PARAMS eDP_Apcial_Params[16];
+} BLOCK27_EDP_FEATURES;
+
+/**
+ This defines the structure of Block 28 (Edidless EFP support DTD timings)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines
the unique Block ID : 28
+ UINT16 BlockSize; ///< Defines
the size of Edidless EFP support block.
+ DTD_STRUCTURE Edidless_EFP_DTD_Struc[4]; ///< Array
defining the DTD timing for 3 EFP devices.
+} BLOCK28_EDIDLESS_EFP;
+
+/**
+This defines the structure of toggle list entry.
+**/
+typedef struct {
+ /**
+ Defines the display device selection for toggling
+ Bit 15 = EFP4.3 (Reserved for CML)
+ Bit 14 = EFP3.3
+ Bit 13 = EFP2.3
+ Bit 12 = EFP1.3
+ Bit 11 = EFP4.2 (Reserved for CML)
+ Bit 10 = EFP3.2
+ Bit 9 = EFP2.2
+ Bit 8 = EFP1.2
+ Bit 7 = LFP2
+ Bit 6 = EFP2
+ Bit 5 = EFP3
+ Bit 4 = EFP4
+ Bit 3 = LFP
+ Bit 2 = EFP
+ Bit 1 = TV
+ Bit 0 = CRT
+ **/
+ UINT16 DisplayDevice;
+} CNL_TOGGLE_LIST_ENTRY;
+
+/**
+ This defines the structure of Block 31 (Toggle Lists for Cannonlake)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the
unique Block ID : 31
+ UINT16 BlockSize; ///< Defines the size
of Toggle List Block.
+ UINT16 NumOfEntry1; ///< Defines the
number of entries in toggle list 1.
+ UINT8 EntrySize1; ///< Defines the size
of toggle list entry present in list 1.
+ CNL_TOGGLE_LIST_ENTRY ToggleList1Entry[16]; ///< Array defining the
toggle list 1.
+ UINT16 NumOfEntry2; ///< Defines the
number of entries in toggle list 2.
+ UINT8 EntrySize2; ///< Defines the size
of toggle list entry present in list 2.
+ CNL_TOGGLE_LIST_ENTRY ToggleList2Entry[8]; ///< Array defining the
toggle list 2.
+ UINT16 NumOfEntry3; ///< Defines the
number of entries in toggle list 3.
+ UINT8 EntrySize3; ///< Defines the size
of toggle list entry present in list 3.
+ CNL_TOGGLE_LIST_ENTRY ToggleList3Entry[8]; ///< Array defining the
toggle list 3.
+ UINT16 NumOfEntry4; ///< Defines the
number of entries in toggle list 4.
+ UINT8 EntrySize4; ///< Defines the size
of toggle list entry present in list 4.
+ CNL_TOGGLE_LIST_ENTRY ToggleList4Entry[8]; ///< Array defining the
toggle list 4.
+} BLOCK31_TOGGLE_LIST;
+
+/**
+ This defines the structure of Display device removal configuration entry.
+**/
+typedef struct {
+ /**
+ Defines the display device configuration to be removed.
+ Bit 15 = EFP4.3 (Reserved for CML)
+ Bit 14 = EFP3.3
+ Bit 13 = EFP2.3
+ Bit 12 = EFP1.3
+ Bit 11 = EFP4.2 (Reserved for CML)
+ Bit 10 = EFP3.2
+ Bit 9 = EFP2.2
+ Bit 8 = EFP1.2
+ Bit 7 = LFP2
+ Bit 6 = EFP2
+ Bit 5 = EFP3
+ Bit 4 = EFP4
+ Bit 3 = LFP
+ Bit 2 = EFP
+ Bit 1 = TV
+ Bit 0 = CRT
+ **/
+ UINT16 DisplayDeviceConfiguration;
+} CNL_DISPLAY_CONFIGURATION_ENTRY;
+
+/**
+ This defines the structure of Block 32 (Display removal configuration
Block)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines
the unique Block ID = 32
+ UINT16 BlockSize; ///< Defines
the size of Display removal configuration block.
+ UINT8 NumOfEntry; ///<
Defines the number of entries in display removal configuraion table.
+ UINT8 EntrySize; ///< Defines
the size of 1 entry in display removal configuration table.
+ CNL_DISPLAY_CONFIGURATION_ENTRY
RemoveDisplayConfiguration[15]; ///< Array defining the display removal
configuration table.
+}BLOCK32_DISPLAY_CONFIGURATION_REMOVAL;
+
+/**
+ This defines the Local Flat panel basic details such as resolution and the
various registers.
+**/
+typedef struct {
+ UINT16 XRes; ///< X resolution of the panel.
+ UINT16 YRes; ///< Y resolution of the panel.
+ UINT32 LVDSDigDisReg; ///< MMIO offset of LFP digital
display port register.
+ UINT32 LVDSDigDisVal; ///< Value of LFP digital display port
register.
+ UINT32 OnSeqDelayReg; ///< MMIO offset of Panel power
on sequencing delay register.
+ UINT32 OnSeqDelayVal; ///< Value of Panel power on
sequencing delay register.
+ UINT32 OffSeqDelayReg; ///< MMIO offset of Panel power off
sequencing delay register.
+ UINT32 OffSeqDelayVal; ///< Value of Panel power off
sequencing delay register.
+ UINT32 CycleDelay_RefDivReg; ///< MMIO offset of Panel power
cycle delay and reference divider register.
+ UINT32 CycleDelay_RefDivVal; ///< Value of Panel power cycle delay
and reference divider register.
+ UINT16 Terminate; ///< Special value 0xFFFF indicating
end of data.
+} FP_DATA;
+
+/**
+ This defines the structure consisting of all details for a single Local Flat
panel.
+**/
+typedef struct {
+ FP_DATA FP_Data; ///< Instance of ::FP_DATA structure.
+ DTD_STRUCTURE DTD_Data; ///< Instance of ::DTD_STRUCTURE
which contains the DTD timings for the panel.
+ PID_DATA PID_Data; ///< Instance of ::PID_DATA structure
which contains panel related information used by driver.
+} LVDS_FP_TABLE;
+
+/**
+ This structure defines all the details regarding Backlight control for LFP.
+**/
+typedef struct {
+ /**
+ Defines the backlight features for the panel.
+ Bits 7:6 = GMBus Speed:
+ = 00, 100 KHz
+ = 01, 50 KHz
+ = 10, 400 KHz
+ = 11, 1 MHz
+ Bits 5:3 = Inverter GPIO Pins
+ = 0, None
+ = 1, I2C GPIO pins
+ = 2, Analog CRT DDC pins
+ = 3, DVI/LVDS DDC GPIO pins
+ = 5, sDVO I2C GPIO pins
+ Bit 2 = Inverter Polarity (i2c & PWM)
+ = 0, Normal (0 = Minimum brightness)
+ = 1, Inverted (0 = Maximum brightness)
+ Bits 1:0 = BLC Inverter Type
+ = 00, None/External
+ = 01, i2c
+ = 10, PWM
+ = 11, Reserved
+ **/
+ UINT8 BLC_Ftr;
+
+ UINT16 PWM_Freq; ///< PWM inverter frequency in KHz
+ UINT8 Min_Brightness; ///< Minimum brightness in the range 0-255
+ UINT8 I2C_Add; ///< I2C Inverter Slave Address
+ UINT8 I2C_Command; ///< I2C Inverter command code
+} BLC;
+
+/**
+ This defines the structure of Block 40 (LFP Features)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block ID : 40
+ UINT16 BlockSize; ///< Defines the size of LFP Features block.
+
+ UINT8 bmp_Panel_type; ///< Defines the panel type of LFP.
+ UINT8 Skip1; ///< Obsoleted.
+
+ /**
+ Capabilities byte:
+ Bit 15:7 = SW Workaround bits
+ Bit 6 = Panel EDID support
+ = 0, Disable
+ = 1, Enable
+ Bit 5 = Pixel dithering
+ = 0, Disable
+ = 1, Enable
+ Bit 4 = Panel Fitting ratio calc.
+ = 0 - Manual
+ = 1 - Automatic
+ Bit 3 = Panel Fitting Graphics mode
+ = 0, Bilinear
+ = 1, Enhanced
+ Bit 2 = Panel Fitting Text mode
+ = 0, Bilinear
+ = 1, Enhanced
+ Bit 1:0 = Panel Fitting Support
+ = 00, No panel fitting
+ = 01, Text panel fitting
+ = 10, GFX panel fitting
+ = 11, Text+GFX panel fitting
+ **/
+ UINT16 bmp_LVDS_Capabilities;
+
+ /**
+ Defines the channel type of LFP. 2 Bits for each Panel.
+ Bits [0:1] for Panel #1
+ = 00, Automatic (algorithm)
+ = 01, Single Channel
+ = 10, Dual Channel
+ = 11, Reserved
+ **/
+ UINT32 INT_LVDS_Panel_Channel_Bits;
+
+ UINT16 Enable_SSC_Bit; ///< LVDS Spread Spectrum Clock
+ UINT16 SSC_Freq_Bit; ///< LVDS Spread Spectrum Clock
Frequency
+ UINT16 Disable_SSC_DDT_Bit; ///< Disable SSC in Dual Display Twin
+
+ /**
+ Defines the panel color depth. 1 Bits for each Panel.
+ Bits[0] for Panel #01
+ = 0, 18bpp
+ = 1, 24bpp
+ **/
+ UINT16 INT_Panel_Color_Depth;
+
+ /**
+ Defines the Panel type. 2 Bits for each Panel.
+ Bits [0:1] for Panel #1
+ = 00, Static DRRS
+ = 01, D2PO
+ = 10, Seamless
+ = 11, Reserved
+ **/
+ UINT32 DPS_Panel_Type_Bits;
+
+ /**
+ Defines the type of backlight control for the LFP. 2 bits for each Panel.
+ Bits [0:1] for Panel #1
+ = 00, Default
+ = 01, CCFL backlight
+ = 10, LED backlight
+ = 11, Reserved
+ **/
+ UINT32 BLT_Control_Type_Bits;
+ /**
+ Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit for
Each Panel.
+ Bits[0] : Panel #1
+ 0 : Do not keep LCDVCC on during S0 state.
+ 1 : Keep LCDVCC on during S0 state.
+ Bits 1 to 15 are for panel # 2 to 16.
+ **/
+ UINT16 LcdvccOnDuringS0State;
+} BLOCK40_LVDS_FEATURES;
+
+/**
+ This structure defines the second type of BMP table pointers.
+ This is used to store pointers to LFP Flat panel data, DTD and PID
information.
+**/
+typedef struct {
+ UINT16 Offset; ///< Offset of the table.
+ UINT8 Size; ///< Size of the table.
+} BMP_TABLE_TYPE2_PTR;
+
+/**
+ This structure defines a set of 3 pointers for LFP display.
+ These pointers point to FP data, DTD and PID information respectively.
+**/
+typedef struct {
+ BMP_TABLE_TYPE2_PTR FpTablePtr; ///< Pointer to FP Data of the
LFP panel.
+ BMP_TABLE_TYPE2_PTR DtdTablePtr; ///< Pointer to DTD of the LFP
panel.
+ BMP_TABLE_TYPE2_PTR PidTablePtr; ///< Pointer to the PID data of
the LFP panel.
+} LFP_TABLE_POINTERS;
+
+/**
+ This defines the structure of Block 41 (LFP Table Pointers for FPDATA, DTD
and PID)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the
unique Block ID:41
+ UINT16 BlockSize; ///< Defines the size
of LFP Table Pointer Block.
+ UINT8 NumOfEntries; ///< Defines the
number of entries in the Table.
+ LFP_TABLE_POINTERS LfpTablePointers[16]; ///< Array
of ::LFP_TABLE_POINTERS for all 16 panels.
+ UINT16 LfpPanelNameTableOffset; ///< Offset of LFP
panel names table.
+ UINT8 LfpPanelNameLength; ///< Length of a
single LFP panel's name.
+} BLOCK41_LFP_TABLE_POINTERS;
+
+/**
+ This defines the structure of Block 42 (Complete LFP Panel Information)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block
ID : 42
+ UINT16 BlockSize; ///< Defines the size of
Complete LFP panel information for all 16 panels.
+ LVDS_FP_TABLE LVDS_FP_Table[16]; ///< Array of ::LVDS_FP_TABLE
containing data of 16 panels.
+ UINT8 LFP_PANEL_NAMES[16][13];///< Array defining the panel
names for all 16 panels.
+
+ /**
+ 1 Bit for Each Panel
+ Bit0 = Scaling feature for panel 1.
+ = 0, Scaling feature is disabled for this panel.
+ = 1, Scaling feature is enabled for this panel.
+ **/
+ UINT16 EnableScaling; //This is not used currently
+
+ /**
+ Array defining DRRS minimum refresh rate. 1 Byte for Each Panel.
+ **/
+ UINT8 Seamless_DRRS_Min_RR[16];
+
+ /**
+ Array defining Pixel Overlap Count. 1 Byte for Each Panel.
+ **/
+ UINT8 PixelOverlapCount[16];
+} BLOCK42_LVDS_PANEL_INFO;
+
+typedef union {
+ /**
+ Backlight control parameters.\n
+ Bits 7:4 : PWM Controller Selection
+ 0 : Controller 0
+ 1 : Controller 1
+ 2 : Controller 2
+ 3 : Controller 3
+ Others : Reserved.
+ Bits 3:0 : PWM Source Selection
+ 0 : PMIC PWM
+ 1 : LPSS PWM
+ 2 : DISPLAY PWM
+ 3 : CABC PWM
+ Others : Reserved.
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 PwmSourceSelection:4;
+ UINT8 PwmControllerSelection:4;
+ } Bits;
+} BKLT_CTRL_PARAMS;
+
+/**
+ This defines the structure of Block 43 (LFP Brightness Control)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique
Block ID : 43
+ UINT16 BlockSize; ///< Defines the size of
Brightness control block.
+
+ UINT8 SIZE_BLCStruc; ///< Defines the size of
single entry in Backlight control table for LFP.
+ BLC BLC_Struct[16]; ///< Array defining the
backlight control for 16 LFP panels.
+ UINT8 Post_Brightness[16]; ///< Array defining the
initial brightness for all 16 panels.
+ BKLT_CTRL_PARAMS Brightness_Control[16]; ///< Array defining the
brightness control method for all 16 panels
+} BLOCK43_LVDS_BLC;
+
+/**
+ This defines the structure of Block 44 (LFP Power Conservation Features)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique block ID : 44
+ UINT16 BlockSize; ///< Defines the size of LFP Power Conservation
Features block.
+ union {
+ /**
+ Bit[7] : ALS Enable/Disable
+ 0 - Disable
+ 1 - Enable
+ Bit[6] : Display LACE support
+ 0 - Not supported
+ 1 - Supported
+ Bit[5] : Default Display LACE enabled status
+ 0 - Disabled
+ 1 - Enabled
+ Bit[4] : Reserved
+ Bit[3:1] : Power conservation preference level.
+ 4 is default in a range of 1 to 6.
+ Bit[0] : Reserved
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 Reserved:1;
+ UINT8 PwrConservation:3;
+ UINT8 Reserved_1:1;
+ UINT8 DefalutDisplayLaceEnable:1;
+ UINT8 DisplayLaceSupport:1;
+ UINT8 AlsEnable:1;
+ } Bits;
+ } LfpFeatureBits;
+
+ UINT16 AlsData[10]; ///< Defines the main ALS data.
+
+ union {
+ /**
+ Bit[7:3] : Reserved
+ Bit[2:0] : Aggressiveness Level Profile.
+ 000 - Minimum
+ 001 - Moderate
+ 010 - High
+ **/
+ UINT8 Value;
+ struct {
+ UINT8 AggressionProfileLevel:3;
+ UINT8 Reserved:5;
+ } Bits;
+ } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile
+} BLOCK44_ALS;
+
+/**
+ This defines the structure of Black Frame Insertion table entry.
+**/
+typedef struct {
+ /**
+ BFI Features\n
+ Bit[7-2] : Reserved\n
+ Bit[1] : Enable Brightness control in CUI\n
+ Bit[0] : Enable BFI in driver
+ **/
+ UINT8 EnableBits;
+ UINT8 BrightnessNonBFI; ///< Brightness percentage in non
BFI mode
+} BFI;
+
+/**
+ This defines the structure of Block 45 (Black Frame insertion Support for
LFP)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the unique Block
ID : 45
+ UINT16 BlockSize; ///< Defines the size of Black
frame insertion support block.
+ UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of
black frame data.
+ BFI BFI_Struct[16]; ///< Array defining the data of
black frame insertion for all 16 panels.
+} BLOCK45_BFI_SUPPORT;
+
+/**
+ This structure defines the chromaticity information for a single LFP panel.
+**/
+typedef struct {
+ /**
+ Defines the chromaticity feature enable bits
+ Bits 7:2 = Reserved
+ Bit 1 = Override EDID values for chromaticity if enabled, Instead Use
VBT values
+ = 0, Disable, Use the EDID values
+ = 1, Enable, Use the values from the VBT
+ Bit 0 = Enable chromaticity feature. EDID values will be used when
this feature is enabled.
+ = 0, Disable
+ = 1, Enable
+ **/
+ UINT8 EnableBits;
+
+ UINT8 Red_Green_1; ///< Red/green chormaticity coordinates
at EDID offset 19h
+ UINT8 Blue_White_1; ///< Blue/white chromatiity coordinates
at EDID offset 1Ah
+ UINT8 Red_X1; ///< Red x coordinate at EDID offset 1Bh
+ UINT8 Red_Y1; ///< Red x coordinate at EDID offset 1Ch
+ UINT8 Green_X1; ///< Green x coordinate at EDID offset
1Dh
+ UINT8 Green_Y1; ///< Green x coordinate at EDID offset
1Eh
+ UINT8 Blue_X1; ///< Blue x coordinate at EDID offset 1Fh
+ UINT8 Blue_Y1; ///< Blue x coordinate at EDID offset 20h
+ UINT8 White_X1; ///< White x coordinate at EDID offset
21h
+ UINT8 White_Y1; ///< White x coordinate at EDID offset
22h
+} CHROMATICITY;
+
+/**
+ This structure defines the Luminance information for a single LFP panel.
+**/
+typedef struct {
+ /**
+ Defines the chromaticity feature enable bits
+ Bits 7:2 : Reserved
+ Bit 1 : Enable Gamma feature.
+ : if enabled, use gamma values from this block.
+ 0 : Disable
+ 1 : Enable
+ Bit 0 : Enable Luminance feature.
+ : if enabled, use values from this block.
+ 0 : Disable
+ 1 : Enable
+ **/
+ UINT8 EnableBits;
+ /**
+ Luminance info (refer DisplayID 2.0)
+ 2 byte value, encoded in IEEE 754 half-precision binary floating point
format
+ **/
+ UINT16 MinLuminance; ///< Native minimum
luminance
+ UINT16 MaxFullFrameLuminance; ///< Native maximum
luminance (Full Frame)
+ UINT16 MaxLuminance; ///< Native Maximum
Luminance (1% Rectangular Coverage)
+ /**
+ Gamma EOTF
+ Gamma values range from 00h through FFh which will come from VBT.
+ Value shall define the gamma range, from 1.00 to 3.54.
+ Field Value = (Gamma (value from VBT) + 100) / 100
+
+ FFh = No gamma information shall be provided
+ **/
+ UINT8 Gamma;
+
+}LUMINANCE_AND_GAMMA;
+
+/**
+ This defines the structure of Block 46 (Chromaticity Support)
+**/
+typedef struct {
+ UINT8 BlockId; ///< Defines the
unique Block ID : 46
+ UINT16 BlockSize; ///< Defines the size of
Chromaticity Block.
+ CHROMATICITY Chromaticity_Struct[16]; ///< Defines the
chromaticity information for all 16 panels.
+ LUMINANCE_AND_GAMMA Luminance_Gamma_Struct[16]; ///<
Defines the lumianance information for all 16 panels.
+} BLOCK46_CHROMATICITY_SUPPORT;
+
+/**
+ This defines the structure of Block 51 (Fixed Mode Set)
+**/
+typedef struct{
+ UINT8 BlockId; ///< Defines the unique block ID : 51.
+ UINT16 BlockSize; ///< Defines the size of Fixed mode set
feature block.
+ UINT8 FeatureEnable; ///< Whether the fixed mode set feature
is enabled/disabled.
+ UINT32 XRes; ///< X resolution of the fixed mode.
+ UINT32 YRes; ///< Y resolution of the fixed mode.
+} BLOCK51_FIXED_MODE_SET;
+
+/**
+ This defines the Complete VBT Structure for generation purpose
+**/
+typedef struct {
+ VBT_HEADER VbtHeader;
+ VBT_BIOS_DATA_HEADER VbtBdbHeader;
+ BLOCK254_BMP_Structure Block254BMPStructure;
+ VBT_GENERAL1_INFO VbtGen1Info;
+ PRD_BOOT_TABLE PrdBootTable;
+ VBT_GENERAL2_INFO VbtGen2Info;
+ BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST
Block03OriginalDisplayToggleList;
+ BLOCK252_SBIOS_Hook Block252SbiosHook;
+ BLOCK06_MMIO_REG_TABLE
Block06MmioRegTable;
+ BLOCK07_IOSWFLAG_REG_TABLE
Block07IoswflagRegTable;
+ BLOCK08_MMIOSWFLAG_REG_TABLE
Block08MmioswflagRegTable;
+ BLOCK09_PSR_FEATURE Block09PsrFeature;
+ BLOCK10_MODE_REMOVAL_TABLE
Block10ModeRemovalTable;
+ BLOCK12_DRIVER_FEATURES
Block12DriverFeatures;
+ BLOCK13_DRIVER_PERSISTENCE
Block13DriverPersistence;
+ BLOCK17_SV_BITS Block17SvBits;
+ BLOCK18_DRIVER_ROTATION
Block18DriverRotation;
+ BLOCK20_OEM_CUSTOMIZATION
Block20OemCustomization;
+ BLOCK26_TV_OPTIONS Block26TVOptions;
+ BLOCK27_EDP_FEATURES Block27EDPFeatures;
+ BLOCK28_EDIDLESS_EFP Block28EdidlessEFP;
+ BLOCK31_TOGGLE_LIST Block31ToggleList;
+ BLOCK32_DISPLAY_CONFIGURATION_REMOVAL
Block32DisplayConfigurationRemoval;
+ BLOCK40_LVDS_FEATURES Block40LVDSFeatures;
+ BLOCK41_LFP_TABLE_POINTERS
Block41LfpTablePointers;
+ BLOCK42_LVDS_PANEL_INFO Block42LvdsPanelInfo;
+ BLOCK43_LVDS_BLC Block43LVDSBlc;
+ BLOCK44_ALS Block44Als;
+ BLOCK46_CHROMATICITY_SUPPORT
Block46ChromaticitySupport;
+ BLOCK51_FIXED_MODE_SET
Block51FixedModeSet;
+} VBT_TABLE_DATA;
+
+#pragma pack()
+
+/**
+ This function will update the VBT checksum.
+
+ @param[in out] VbtPtr - Pointer to VBT table
+
+ @retval none
+**/
+VOID
+UpdateVbtChecksum(
+ VBT_TABLE_DATA *VbtPtr
+);
+
+/**
+ This function will update the VBT.
+
+ @param[in] VbtPtr - Pointer to VBT Table
+
+ @retval none
+**/
+VOID
+UpdateGopVbt (
+ IN VBT_TABLE_DATA *VbtPtr
+);
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
new file mode 100644
index 0000000000..fdb6b8eead
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/IoExpander.h
@@ -0,0 +1,68 @@
+/** @file
+ GPIO definition table for CometlakeURvp
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IO_EXPANDER_H_
+#define _IO_EXPANDER_H_
+
+typedef struct {
+ UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1)
+ UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23)
+ UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output)
+ UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low)
+ UINT32 GpioInversion : 1; // GPIO Pin Inversion (Enabled/Disabled)
+ UINT32 Reserved : 23; // Reserved
+} IO_EXPANDER_GPIO_CONFIG;
+
+//CML PCH LP GPIO Expander Number
+#define IO_EXPANDER_0 0
+#define IO_EXPANDER_1 1
+
+//CML PCH LP GPIO Pin Mapping
+#define IO_EXPANDER_GPIO_0 0 // P00
+#define IO_EXPANDER_GPIO_1 1 // P01
+#define IO_EXPANDER_GPIO_2 2 // P02
+#define IO_EXPANDER_GPIO_3 3 // P03
+#define IO_EXPANDER_GPIO_4 4 // P04
+#define IO_EXPANDER_GPIO_5 5 // P05
+#define IO_EXPANDER_GPIO_6 6 // P06
+#define IO_EXPANDER_GPIO_7 7 // P07
+#define IO_EXPANDER_GPIO_8 8 // P10
+#define IO_EXPANDER_GPIO_9 9 // P11
+#define IO_EXPANDER_GPIO_10 10 // P12
+#define IO_EXPANDER_GPIO_11 11 // P13
+#define IO_EXPANDER_GPIO_12 12 // P14
+#define IO_EXPANDER_GPIO_13 13 // P15
+#define IO_EXPANDER_GPIO_14 14 // P16
+#define IO_EXPANDER_GPIO_15 15 // P17
+#define IO_EXPANDER_GPIO_16 16 // P20
+#define IO_EXPANDER_GPIO_17 17 // P21
+#define IO_EXPANDER_GPIO_18 18 // P22
+#define IO_EXPANDER_GPIO_19 19 // P23
+#define IO_EXPANDER_GPIO_20 20 // P24
+#define IO_EXPANDER_GPIO_21 21 // P25
+#define IO_EXPANDER_GPIO_22 22 // P26
+#define IO_EXPANDER_GPIO_23 23 // P27
+
+//CML PCH LP GPIO Expander GPIO Direction
+#define IO_EXPANDER_GPIO_OUTPUT 0
+#define IO_EXPANDER_GPIO_INPUT 1
+
+//CML PCH LP GPIO Expaner GPIO Output Level
+#define IO_EXPANDER_GPO_LEVEL_LOW 0
+#define IO_EXPANDER_GPO_LEVEL_HIGH 1
+
+//CML PCH LP GPIO Expaner GPIO Inversion Status
+#define IO_EXPANDER_GPI_INV_DISABLED 0
+#define IO_EXPANDER_GPI_INV_ENABLED 1
+#define IO_EXPANDER_GPIO_RESERVED 0x00
+
+//GPIO Table Terminator
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpd
ateLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpd
ateLib.h
new file mode 100644
index 0000000000..a5dd731aa7
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpd
ateLib.h
@@ -0,0 +1,75 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_
+#define _DXE_CPU_POLICY_UPDATE_LIB_H_
+
+#include <PiDxe.h>
+#include <PchAccess.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/CpuPolicyProtocol.h>
+
+/**
+
+ This function prints the CPU DXE phase policy.
+
+ @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+/**
+
+Routine Description:
+
+ This function updates Dxe Cpu Policy Protocol
+
+Arguments:
+
+ @param[in] DxeCpuPolicy The Cpu Policy protocol
instance
+
+Returns:
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is
unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough
resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits
abnormally.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+ IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+/**
+
+ CpuInstallPolicyProtocol installs CPU Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please
update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] DxeCpuPolicy The pointer to CPU Policy
Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to
create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpda
teLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpda
teLib.h
new file mode 100644
index 0000000000..a873446be3
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeMePolicyUpda
teLib.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_ME_POLICY_UPDATE_LIB_H_
+#define _DXE_ME_POLICY_UPDATE_LIB_H_
+
+/**
+ Update the ME Policy Library
+
+ @param[in] DxeMePolicy The pointer to get ME Policy
protocol instance
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported
by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough
resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits
abnormally.
+
+**/
+EFI_STATUS
+UpdateDxeMePolicy (
+ IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
+ );
+
+#endif // _DXE_ME_POLICY_UPDATE_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpda
teLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpda
teLib.h
new file mode 100644
index 0000000000..fd451328bd
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePchPolicyUpda
teLib.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_
+#define _DXE_PCH_POLICY_UPDATE_LIB_H_
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] PchPolicy The pointer to get PCH Policy
protocol instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxePchPolicy (
+ IN OUT PCH_POLICY_PROTOCOL *PchPolicy
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardCo
nfigLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardCo
nfigLib.h
new file mode 100644
index 0000000000..f73da06df4
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxePolicyBoardCo
nfigLib.h
@@ -0,0 +1,30 @@
+/** @file
+ Header file for the DxePolicyBoardConfig Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_
+#define _DXE_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Protocol/MePolicy.h>
+#include <Protocol/SaPolicy.h>
+
+/**
+ This function performs DXE SA Policy update by board configuration.
+
+ @param[in, out] DxeSaPolicy DXE SA Policy
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicyBoardConfig (
+ IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdat
eLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdat
eLib.h
new file mode 100644
index 0000000000..77ca6c3f2a
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdat
eLib.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_SA_POLICY_UPDATE_LIB_H_
+#define _DXE_SA_POLICY_UPDATE_LIB_H_
+
+/**
+ Get data for platform policy from setup options.
+
+ @param[in] SaPolicy The pointer to get SA Policy
protocol instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicy (
+ IN OUT SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h
new file mode 100644
index 0000000000..bfa0f0cf3e
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h
@@ -0,0 +1,29 @@
+/** @file
+ Function prototype of FspPolicyInitLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSP_POLICY_INIT_LIB_H_
+#define _FSP_POLICY_INIT_LIB_H_
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+VOID
+EFIAPI
+FspPolicyInitPreMem (
+ IN FSPM_UPD *FspmUpdDataPtr
+ );
+
+VOID
+EFIAPI
+FspPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+#endif // _FSP_POLICY_INIT_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflict
Lib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflict
Lib.h
new file mode 100644
index 0000000000..19d16c1151
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioCheckConflict
Lib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for check Gpio PadMode conflict.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_CHECK_CONFLICT_LIB_H_
+#define _GPIO_CHECK_CONFLICT_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <GpioConfig.h>
+#include <Library/GpioLib.h>
+
+extern EFI_GUID gGpioCheckConflictHobGuid;
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ UINT32 GpioPadMode:5;
+ UINT32 Reserved:27;
+} GPIO_PAD_MODE_INFO;
+
+/**
+ Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ );
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ );
+
+#endif // _GPIO_CHECK_CONFLICT_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.
h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.
h
new file mode 100644
index 0000000000..5bd00e21fc
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/GpioExpanderLib.
h
@@ -0,0 +1,123 @@
+/** @file
+ Support for IO expander TCA6424.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_EXPANDER_LIB_H_
+#define _GPIO_EXPANDER_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+/**
+ Set the Direction value for the given Expander Gpio pin.
+
+ This function is to Set the direction value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+**/
+VOID
+GpioExpSetDirection (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Direction
+ );
+/**
+ Set the input value for the given Expander Gpio pin.
+
+ This function is to get the input value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+
+**/
+VOID
+GpioExpSetPolarity (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Polarity
+ );
+/**
+ Set the Output value for the given Expander Gpio pin.
+
+ This function is to Set the Output value for the GPIO
+ Pin within the giving Expander.
+
+ @param[in] Expander Expander Value with in the Contoller
+ @param[in] Pin Pin with in the Expnader Value
+ @param[in] Value none
+
+**/
+VOID
+GpioExpSetOutput (
+ IN UINT8 Expander,
+ IN UINT8 Pin,
+ IN UINT8 Value
+ );
+/**
+ Returns the data from register value giving in the input.
+
+ This function is to get the data from the Expander
+ Registers by following the I2C Protocol communication
+
+
+ @param[in] Bar0 Bar address of the SerialIo Controller
+ @param[in] Address Expander Value with in the Contoller
+ @param[in] Register Address of Input/Output/Configure/Polarity
+ registers with in the Expander
+
+ @retval UINT8 Value returned from the register
+**/
+UINT8
+GpioExpGetInput (
+ IN UINT8 Expander,
+ IN UINT8 Pin
+ );
+
+/**
+ Configures all registers of a single IO Expander in one go.
+
+ @param[in] Expander Expander number (0/1)
+ @param[in] Direction Bit-encoded direction values. BIT0 is for pin0,
etc. 0=output, 1=input
+ @param[in] Polarity Bit-encoded input inversion values. BIT0 is for
pin0, etc. 0=normal, 1=inversion
+ @param[in] Output Bit-encoded output state, ignores polarity,
only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
+
+**/
+VOID
+GpioExpBulkConfig (
+ IN UINT8 Expander,
+ IN UINT32 Direction,
+ IN UINT32 Polarity,
+ IN UINT32 Output
+ );
+
+/**
+ Returns the Controller on which GPIO expander is present.
+
+ This function returns the Controller value
+
+ @param[out] Controller Pointer to a Controller value on
+ which I2C expander is
configured.
+
+ @retval EFI_SUCCESS non.
+**/
+EFI_STATUS
+GpioExpGetController (
+ OUT UINT8 *Controller
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.
h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.
h
new file mode 100644
index 0000000000..7e15e959a6
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/HdaVerbTableLib.
h
@@ -0,0 +1,48 @@
+/** @file
+
+ Header file for the Intel HD Audio Verb Table library.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _HDA_VERB_TABLE_LIB_H_
+#define _HDA_VERB_TABLE_LIB_H_
+
+#include <ConfigBlock/HdAudioConfig.h>
+#include <Library/BaseLib.h>
+
+enum HDAUDIO_CODEC_SELECT {
+ PchHdaCodecPlatformOnboard = 0,
+ PchHdaCodecExternalKit = 1
+};
+
+/**
+ Add verb table function.
+ This function update the verb table number and verb table ptr of policy.
+
+ @param[in] HdAudioConfig HD Audio config block
+ @param[out] VerbTableEntryNum Number of verb table entries
+ @param[out] HdaVerbTablePtr Pointer to the verb table
+**/
+VOID
+AddPlatformVerbTables (
+ IN UINT8 CodecType,
+ OUT UINT8 *VerbTableEntryNum,
+ OUT UINT32 *HdaVerbTablePtr
+ );
+
+/**
+ HDA VerbTable init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+HdaVerbTableInit(
+ IN UINT16 BoardId
+ );
+
+#endif
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
new file mode 100644
index 0000000000..e1f00b6d96
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/I2cAccessLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Support for IO expander TCA6424.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _I2C_ACCESS_LIB_H_
+#define _I2C_ACCESS_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiLib.h>
+#include <PchAccess.h>
+#include <Library/PchSerialIoLib.h>
+
+#define WAIT_1_SECOND 1600000000 //1.6 * 10^9
+
+EFI_STATUS
+I2cWriteRead (
+ IN UINTN MmioBase,
+ IN UINT8 SlaveAddress,
+ IN UINT8 WriteLength,
+ IN UINT8 *WriteBuffer,
+ IN UINT8 ReadLength,
+ IN UINT8 *ReadBuffer,
+ IN UINT64 TimeBudget
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
new file mode 100644
index 0000000000..3443479a52
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPlatformLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED 1
+
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+ PCH_GPIO_DEV Use_Sel;
+ PCH_GPIO_DEV Use_Sel2;
+ PCH_GPIO_DEV Use_Sel3;
+ PCH_GPIO_DEV Io_Sel;
+ PCH_GPIO_DEV Io_Sel2;
+ PCH_GPIO_DEV Io_Sel3;
+ PCH_GPIO_DEV Lvl;
+ PCH_GPIO_DEV Lvl2;
+ PCH_GPIO_DEV Lvl3;
+ PCH_GPIO_DEV Inv;
+ PCH_GPIO_DEV Blink;
+ PCH_GPIO_DEV Rst_Sel;
+ PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardCon
figLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardCo
nfigLib.h
new file mode 100644
index 0000000000..7615461e1e
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyBoardCo
nfigLib.h
@@ -0,0 +1,141 @@
+/** @file
+ Header file for the PeiPolicyBoardConfig Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_
+#define _PEI_POLICY_BOARD_CONFIG_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board
configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board
configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board
configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board
configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ This function performs PEI CPU Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI PCH Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully
updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h
new file mode 100644
index 0000000000..ddcf839cfc
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h
@@ -0,0 +1,38 @@
+/** @file
+ Header file for the PolicyInitPei Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_INIT_PEI_LIB_H_
+#define _POLICY_INIT_PEI_LIB_H_
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] FirmwareConfiguration It uses to skip specific policy init
that depends
+ on the 'FirmwareConfiguration'
varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+ IN UINT8 FirmwareConfiguration
+ );
+
+/**
+ Initialize Intel PEI Platform Policy
+
+ @param[in] PeiServices General purpose services available
to every PEIM.
+ @param[in] FirmwareConfiguration It uses to skip specific policy init that
depends
+ on the 'FirmwareConfiguration'
varaible.
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+// IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT8 FirmwareConfiguration
+ );
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
new file mode 100644
index 0000000000..25ed2679d2
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Library/PlatformInitLib.h
@@ -0,0 +1,23 @@
+/** @file
+ Function prototype of PlatformInitLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INIT_LIB_H_
+#define _PLATFORM_INIT_LIB_H_
+
+VOID
+PlatformLateInit (
+ VOID
+ );
+
+VOID
+InitSerialPort (
+ VOID
+ );
+
+#endif // _PLATFORM_INIT_LIB_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
new file mode 100644
index 0000000000..3330a48e4d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/PchHsioPtssTables.h
@@ -0,0 +1,51 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef PCH_HSIO_PTSSTABLES_H_
+#define PCH_HSIO_PTSSTABLES_H_
+
+#include <PchAccess.h>
+
+///
+/// SATA PTSS Topology Types
+///
+typedef enum {
+ PchSataTopoUnknown = 0x00,
+ PchSataTopoIsata,
+ PchSataTopoDirectConnect,
+ PchSataTopoFlex,
+ PchSataTopoM2
+} PCH_SATA_TOPOLOGY;
+
+///
+/// PCIe PTSS Topology Types
+///
+typedef enum {
+ PchPcieTopoUnknown = 0x00,
+ PchPcieTopox1,
+ PchPcieTopox4,
+ PchPcieTopoSataE,
+ PchPcieTopoM2
+} PCH_PCIE_TOPOLOGY;
+
+///
+/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for
PCH.
+///
+typedef struct {
+ UINT8 LaneNum;
+ UINT8 PhyMode;
+ UINT16 Offset;
+ UINT32 Value;
+ UINT32 BitMask;
+} PCH_SBI_PTSS_HSIO_TABLE;
+
+typedef struct {
+ PCH_SBI_PTSS_HSIO_TABLE PtssTable;
+ UINT16 Topology;
+} HSIO_PTSS_TABLES;
+
+#endif // PCH_HSIO_PTSSTABLES_H_
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.
h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.
h
new file mode 100644
index 0000000000..f8f32610d1
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/PcieDeviceOverrideTable.
h
@@ -0,0 +1,106 @@
+/** @file
+ PCIe Device Override Table
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_
+#define _PCIE_DEVICE_OVERRIDE_TABLE_H_
+
+#include <ConfigBlock/PcieRpConfig.h>
+#include <IndustryStandard/Pci22.h>
+
+#define PCI_CLASS_NETWORK 0x02
+#define PCI_CLASS_NETWORK_ETHERNET 0x00
+#define PCI_CLASS_NETWORK_OTHER 0x80
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE
mPcieDeviceTable[] = {
+ //
+ // Intel PRO/Wireless
+ //
+ { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ //
+ // Intel WiMAX/WiFi Link
+ //
+ { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0,
0, 0, 0, 0, 0 },
+ //
+ // Intel Crane Peak WLAN NIC
+ //
+ { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Crane Peak w/BT WLAN NIC
+ //
+ { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Kelsey Peak WiFi, WiMax
+ //
+ { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 105
+ //
+ { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 135
+ //
+ { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2200
+ //
+ { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 2230
+ //
+ { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel Centrino Wireless-N 6235
+ //
+ { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel CampPeak 2 Wifi
+ //
+ { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+ //
+ // Intel WilkinsPeak 1 Wifi
+ //
+ { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ //
+ // Intel Wilkins Peak 2 Wifi
+ //
+ { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1,
PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 },
+ //
+ // Intel Wilkins Peak PF Wifi
+ //
+ { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK,
PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0,
0, 0, 0 },
+
+ //
+ // End of Table
+ //
+ { 0 }
+};
+
+#endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
new file mode 100644
index 0000000000..cabd0e167a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Platform.h
@@ -0,0 +1,33 @@
+/** @file
+ This header file provides platform specific definitions used
+ by other modules for platform specific initialization.
+ This is not suitable for consumption by ASL or VRF files.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+//#include "CommonDefinitions.h"
+#include "PchAccess.h"
+#include "SaAccess.h"
+
+//
+// Need minimum of 48MB during PEI phase for IAG and some buffer for
boot.
+//
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000 +
0x10000000) // 80MB + 256MB
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000 +
0x10000000) // 80MB + 256MB
+
+#define FLASH_BLOCK_SIZE 0x10000
+
+#define CPU_EXTERNAL_CLOCK_FREQ 0x64
+#define CPU_FREQUENCY_MODE_100 0x64
+#define FREQUENCY_RESOLUTION_3182 0xc6e
+#define NDIVIDER_BASE_VALUE 0x19d
+#define MDIVIDER_VALUE_13 0xd
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..9a4b156d5f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,29 @@
+/** @file
+Defines Platform BoardIds
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+#define FlavorUnknown 0x0
+#define FlavorMobile 0x1
+#define FlavorDesktop 0x2
+#define FlavorWorkstation 0x3
+#define FlavorUpServer 0x4
+#define FlavorEmbedded 0x5
+#define FlavorPlatformMax 0x6
+
+#define TypeUnknown 0x0
+#define TypeTrad 0x1
+#define TypeUltUlx 0x2
+
+#define BoardIdCometLakeULpddr3Rvp 0x1
+
+#define BoardIdUnknown1 0xffff
+
+#endif
+
diff --git
a/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 0000000000..ee927ae629
--- /dev/null
+++
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,47 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL
EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+
+#define GLOBAL_NVS_AREA_REVISION 16
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#include <Acpi/GlobalNvsAreaDef.h>
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ EFI_GLOBAL_NVS_AREA *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
new file mode 100644
index 0000000000..00863d3fa0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/Setup.h
@@ -0,0 +1,144 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __SETUP__H__
+#define __SETUP__H__
+
+#ifndef MDEPKG_NDEBUG
+#define DEBUG_INTERFACE_FORM_ENABLE
+#endif // MDEPKG_NDEBUG
+//
+// Form class guid for the forms those will be showed on first front page.
+//
+#define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88,
0x3a, 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
+//
+// Form class guid for the forms those will be showed on boot maintenance
manager menu.
+//
+#define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89,
0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } }
+
+// VFR common Definitions
+#define INVENTORY(Name,Value) \
+ text \
+ help = STRING_TOKEN(STR_EMPTY), \
+ text = Name, \
+ text = Value, \
+ flags = 0, \
+ key = 0;
+
+#define SUBTITLE(Text) subtitle text = Text;
+#define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY))
+
+#define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\
+ grayoutif TRUE;\
+ oneof varid = SETUP_DATA.InteractiveText,\
+ questionid = Key,\
+ prompt = CaptionToken,\
+ help = HelpToken,\
+ option text = ValueToken, value = 0, flags = INTERACTIVE |
DEFAULT;\
+ refresh interval = 1 \
+ endoneof;\
+ endif;
+
+#define SUPPRESS_GRAYOUT_ENDIF endif; endif;
+#define DEFAULT_FLAG
+
+#define SYSTEM_ACCESS_KEY_ID 0xF000
+//
+// System Access defintions.
+//
+#define SYSTEM_ACCESS_GUID \
+ { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE,
0xAC }}
+
+#define SYSTEM_PASSWORD_ADMIN 0
+#define SYSTEM_PASSWORD_USER 1
+#define ADMIN_PW_CLEAR 0
+#define ADMIN_PW_SET 1
+
+
+typedef struct _SYSTEM_ACCESS
+{
+ //
+ // Passwords
+ //
+ UINT8 Access;
+} SYSTEM_ACCESS;
+
+//
+// Record the password status.
+//
+typedef struct {
+ UINT8 AdminName;
+ UINT8 UserName;
+} EFI_PASSWORD_STATUS;
+
+//
+// Config Data
+//
+typedef struct {
+ UINT8 SerialDebug;
+ UINT8 SerialDebugBaudRate;
+ UINT8 RamDebugInterface;
+ UINT8 UartDebugInterface;
+ UINT8 Usb3DebugInterface;
+ UINT8 SerialIoDebugInterface;
+ UINT8 TraceHubDebugInterface;
+} DEBUG_CONFIG_DATA;
+
+//
+// Config Data Hob
+//
+#define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA
+
+//
+// Secure Boot Data
+//
+typedef struct{
+ UINT8 SecureBoot;
+} SECURE_BOOT_VARIABLE;
+
+#pragma pack()
+
+//
+// Varstore statement
+// Setup is EfiVarStore that is related to EFI variable with attribute 0x07
+// (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS)
+//
+#define SETUP_DATA_VARSTORE\
+ efivarstore SETUP_DATA, varid = 1,\
+ attribute = 0x7, name = Setup, guid = SETUP_GUID;
+#define SA_SETUP_VARSTORE\
+ efivarstore SA_SETUP, varid = 2,\
+ attribute = 0x7, name = SaSetup, guid = SA_SETUP_GUID;
+#define CPU_SETUP_VARSTORE\
+ efivarstore CPU_SETUP, varid = 3,\
+ attribute = 0x7, name = CpuSetup, guid = CPU_SETUP_GUID;
+#define ME_SETUP_VARSTORE\
+ efivarstore ME_SETUP, varid = 4,\
+ attribute = 0x7, name = MeSetup, guid = ME_SETUP_GUID;
+#define PCH_SETUP_VARSTORE\
+ efivarstore PCH_SETUP, varid = 5,\
+ attribute = 0x7, name = PchSetup, guid = PCH_SETUP_GUID;
+#define SI_SETUP_VARSTORE\
+ efivarstore SI_SETUP, varid = 6,\
+ attribute = 0x7, name = SiSetup, guid = SI_SETUP_GUID;
+#ifdef DEBUG_INTERFACE_FORM_ENABLE
+#define DEBUG_CONFIG_DATA_ID 0xF001
+#define DEBUG_CONFIG_DATA_VARSTORE\
+ efivarstore DEBUG_CONFIG_DATA, varid = DEBUG_CONFIG_DATA_ID,\
+ attribute = 0x7, name = DebugConfigData, guid =
DEBUG_CONFIG_GUID;
+#endif // DEBUG_INTERFACE_FORM_ENABLE
+#define SYSTEM_ACCESS_VARSTORE\
+ varstore SYSTEM_ACCESS, varid = SYSTEM_ACCESS_KEY_ID,\
+ name = SystemAccess, guid = SYSTEM_ACCESS_GUID;
+#define SYSTEM_PASSWORD_VARSTORE\
+ varstore EFI_PASSWORD_STATUS,\
+ name = PasswordStatus, guid = SYSTEM_ACCESS_GUID;
+
+#define BOOT_FLOW_CONDITION_RECOVERY 2
+#define BOOT_FLOW_CONDITION_FIRST_BOOT 4
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
b/Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
new file mode 100644
index 0000000000..53822a83f6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Include/SioRegs.h
@@ -0,0 +1,157 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SIO_REG_H_
+#define _SIO_REG_H_
+
+#define REG_LOGICAL_DEVICE 0x07
+#define ACTIVATE 0x30
+
+#define BASE_ADDRESS_HIGH0 0x60
+#define BASE_ADDRESS_LOW0 0x61
+#define BASE_ADDRESS_HIGH1 0x62
+#define BASE_ADDRESS_LOW1 0x63
+#define BASE_ADDRESS_HIGH2 0x64
+#define BASE_ADDRESS_LOW2 0x65
+#define BASE_ADDRESS_HIGH3 0x66
+#define BASE_ADDRESS_LOW3 0x67
+#define PRIMARY_INTERRUPT_SELECT 0x70
+#define WAKEUP_ON_IRQ_EN 0x70
+#define INTERRUPT_TYPE 0x71
+#define DMA_CHANNEL_SELECT0 0x74
+#define DMA_CHANNEL_SELECT1 0x75
+
+
+
+//
+//Port address for PILOT - III
+//
+#define PILOTIII_CHIP_ID 0x03
+#define PILOTIII_SIO_INDEX_PORT 0x04E
+#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
+
+#define PILOTIII_UNLOCK 0x5A
+#define PILOTIII_LOCK 0xA5
+
+//
+// logical device in PILOT-III
+//
+#define PILOTIII_SIO_PSR 0x00
+#define PILOTIII_SIO_COM2 0x01
+#define PILOTIII_SIO_COM1 0x02
+#define PILOTIII_SIO_SWCP 0x03
+#define PILOTIII_SIO_GPIO 0x04
+#define PILOTIII_SIO_WDT 0x05
+#define PILOTIII_SIO_KCS3 0x08
+#define PILOTIII_SIO_KCS4 0x09
+#define PILOTIII_SIO_KCS5 0x0A
+#define PILOTIII_SIO_BT 0x0B
+#define PILOTIII_SIO_SMIC 0x0C
+#define PILOTIII_SIO_MAILBOX 0x0D
+#define PILOTIII_SIO_RTC 0x0E
+#define PILOTIII_SIO_SPI 0x0F
+#define PILOTIII_SIO_TAP 0x10
+//
+// Regisgers for Pilot-III
+//
+#define PILOTIII_CHIP_ID_REG 0x20
+#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
+#define PILOTIII_ACTIVATE ACTIVATE
+#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
+#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
+#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
+#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
+#define PILOTIII_PRIMARY_INTERRUPT_SELECT
PRIMARY_INTERRUPT_SELECT
+
+//
+// Port address for PC8374
+//
+#define PC8374_SIO_INDEX_PORT 0x02E
+#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
+
+//
+// Logical device in PC8374
+//
+#define PC8374_SIO_FLOPPY 0x00
+#define PC8374_SIO_PARA 0x01
+#define PC8374_SIO_COM2 0x02
+#define PC8374_SIO_COM1 0x03
+#define PC8374_SIO_MOUSE 0x05
+#define PC8374_SIO_KYBD 0x06
+#define PC8374_SIO_GPIO 0x07
+
+//
+// Registers specific for PC8374
+//
+#define PC8374_CLOCK_SELECT 0x2D
+#define PC8374_CLOCK_CONFIG 0x29
+
+//
+// Registers for PC8374
+//
+#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
+#define PC8374_ACTIVATE ACTIVATE
+#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
+#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
+#define PC8374_PRIMARY_INTERRUPT_SELECT
PRIMARY_INTERRUPT_SELECT
+#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
+
+#define PC87427_SERVERIO_CNF2 0x22
+
+
+//
+// Pilot III Mailbox Data Register definitions
+//
+#define MBDAT00_OFFSET 0x00
+#define MBDAT01_OFFSET 0x01
+#define MBDAT02_OFFSET 0x02
+#define MBDAT03_OFFSET 0x03
+#define MBDAT04_OFFSET 0x04
+#define MBDAT05_OFFSET 0x05
+#define MBDAT06_OFFSET 0x06
+#define MBDAT07_OFFSET 0x07
+#define MBDAT08_OFFSET 0x08
+#define MBDAT09_OFFSET 0x09
+#define MBDAT10_OFFSET 0x0A
+#define MBDAT11_OFFSET 0x0B
+#define MBDAT12_OFFSET 0x0C
+#define MBDAT13_OFFSET 0x0D
+#define MBDAT14_OFFSET 0x0E
+#define MBDAT15_OFFSET 0x0F
+#define MBST0_OFFSET 0x10
+#define MBST1_OFFSET 0x11
+#define MBBINT_OFFSET 0x12
+
+//
+// Mailbox Bit definitions...
+//
+#define MBBINT_MBBIST_BIT 0x80
+// If both are there, use the default one
+//
+#define W83527_EXIST BIT2
+#define PC8374_EXIST BIT1
+#define PILOTIII_EXIST BIT0
+#define DEFAULT_SIO PILOTIII_EXIST
+#define DEFAULT_KDB PC8374_EXIST
+
+#define IPMI_DEFAULT_SMM_IO_BASE 0xca2
+//
+// For Pilot III
+//
+
+#define PILOTIII_SWC_BASE_ADDRESS 0xA00
+#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
+#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
+#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
+#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
+#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
+#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
+#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
+#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
+#define PILOTIII_MAILBOX_MASK 0xFFE0
+#define BMC_KCS_BASE_ADDRESS 0x0CA0
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
b/Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..1f8322eaeb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,564 @@
+## @file
+# Module describe the entire platform configuration.
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = 7F1FFF90-0F5F-4980-88FE-A9E683CFBB32
+
+[Includes]
+Include
+Features/Tbt/Include
+CometlakeURvp/Include
+
+[Guids]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid = {0xfe2ab368, 0x7cc1,
0x4de8, {0xb7, 0x19, 0xad, 0x56, 0xee, 0xb8, 0xcc, 0x84}}
+
+gTianoLogoGuid = {0x7BB28B99, 0x61BB,
0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+gTbtInfoHobGuid = {0x74a81eaa, 0x033c,
0x4783, {0xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}
+
+gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91,
0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+
+gMeInfoSetupGuid = {0x78259433, 0x7b6d,
0x4db3, {0x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}}
+gRealModeFileGuid = {0xdf84ed23, 0x5d53,
0x423f, {0xaa, 0x81, 0x0f, 0x0e, 0x6f, 0x55, 0xc6, 0x9b}}
+gVirtualKeyboardDriverImageGuid = {0xe4735aac, 0x9c27, 0x493f,
{0x86, 0xea, 0x9e, 0xff, 0x43, 0xd7, 0xad, 0xcd}}
+gPegConfigVariableGuid = {0xb414caf8, 0x8225, 0x4d6f,
{0xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}}
+gSaSetupVariableGuid = {0x72c5e28c, 0x7783, 0x43a1,
{0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}}
+gMeSetupVariableGuid = {0x5432122d, 0xd034,
0x49d2, {0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}}
+gCpuSetupVariableGuid = {0xb08f97ff, 0xe6e8, 0x4193,
{0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}}
+gCpuSmmGuid = {0x90d93e09, 0x4e91,
0x4b3d, {0x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81}}
+gPchSetupVariableGuid = {0x4570b7f1, 0xade8, 0x4943,
{0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}}
+gSiSetupVariableGuid = {0xAAF8E719, 0x48F8, 0x4099,
{0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}}
+gDebugConfigVariableGuid = {0xDE0A5E74, 0x4E3E,
0x3D96, {0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}}
+gDebugConfigHobGuid = {0x2f6a6bb7, 0x9dc7,
0x4bf6, {0x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}}
+gChassisIntrudeDetHobGuid = {0xdea43de2, 0x756b,
0x4b3b, {0x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}}
+
+gGpioCheckConflictHobGuid = {0x5603f872, 0xefac, 0x40ae,
{0xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}
+
+gAttemptUsbFirstHotkeyInfoHobGuid = {0x38b8e214, 0x1468, 0x4bb7,
{0x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}}
+gTianoLogoGuid = {0x7BB28B99, 0x61BB,
0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+##
+## ChipsetInitBinary
+##
+gCnlPchLpChipsetInitTableDxGuid = {0xc9505bc0, 0xaa3d,
0x4056, {0x99, 0x95, 0x87, 0x0c, 0x8d, 0xe8, 0x59, 0x4e}}
+
+
+[Protocols]
+gTbtNvsAreaProtocolGuid = {0x4d6a54d1, 0xcd56, 0x47f3,
{0x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}}
+gDxeTbtPolicyProtocolGuid = {0x196bf9e3, 0x20d7, 0x4b7b,
{0x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}
+
+[Ppis]
+gPeiTbtPolicyPpiGuid = {0xd7e7e1e6, 0xcbec, 0x4f5f,
{0xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}
+gPeiTbtPolicyBoardInitDonePpiGuid = {0x970f9c60, 0x8547, 0x49d7,
{ 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}}
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+
+[PcdsFixedAtBuild]
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|
UINT16|0x10001004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c0
3|UINT16|0x10001005
+
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT6
4|0x90000003
+gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x900
00004
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|
0x90000005
+gPlatformModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000
006
+gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress|0xFED84000|UINT6
4|0x90000007
+gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize|0x1000|UINT32|0x900
00008
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UIN
T64|0x90000009
+gPlatformModuleTokenSpaceGuid.PcdEdramMmioSize|0x4000|UINT32|0x9
000000A
+gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT6
4|0x9000000B
+gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize|0x1000|UINT32|0
x9000000C
+gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0
x9000000D
+gPlatformModuleTokenSpaceGuid.PcdApicIoMmioSize|0x1000|UINT32|0x9
000000E
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xCF000000|UINT64|
0x9000000F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xD0000000|UINT64|
0x90000010
+gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x900
00012
+gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x900
00013
+gPlatformModuleTokenSpaceGuid.PcdPcieDockBridgeResourcePatchSmi|0x4
D|UINT8|0x90000014
+gPlatformModuleTokenSpaceGuid.PcdCmosFastBootDefaultValue|0x01|UIN
T8|0x90000016
+gPlatformModuleTokenSpaceGuid.PcdCmosDebugPrintErrorLevelDefaultValu
e|0x80000046|UINT32|0x90000017
+gPlatformModuleTokenSpaceGuid.PcdOverClockingInterfaceSwSmi|0x72|UI
NT8|0x90000019
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|
UINT16|0x9000001A
+gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E
|UINT16|0x9000001B
+gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48
|UINT8|0x90000020
+gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x2000
0505
+gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT3
2|0x10001003
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|
UINT8|0x90000015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT1
6|0x90000018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x1
64E|UINT16|0x9000001C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UIN
T16|0x9000001D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16
|0x9000001F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x16
4E|UINT16|0x90000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x16
4F|UINT16|0x90000022
+
+[PcdsDynamic]
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0
x00000040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT1
6|0x00000041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|
0x00000042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT
16|0x00000043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|
UINT32|0x000000113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|
0|UINT16|0x000000114
+
+# Board Expander GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT3
2|0x00000044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UI
NT16|0x00000045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT
32|0x00000046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|
UINT16|0x00000047
+
+# TouchPanel & SDHC CD GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|
0|UINT32|0x00000048
+
+# PCH-LP HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|
UINT32|0x0000004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|
UINT32|0x0000004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
|0|UINT16|0x0000004C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
|0|UINT16|0x0000004D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|
UINT32|0x0000004E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|
UINT32|0x0000004F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
|0|UINT16|0x00000050
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
|0|UINT16|0x00000051
+
+# PCH-H HSIO PTSS Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|
UINT32|0x00000052
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|
UINT32|0x00000053
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
|0|UINT16|0x00000054
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
|0|UINT16|0x00000055
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|U
INT32|0x00000056
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|U
INT32|0x00000057
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|
0|UINT16|0x00000058
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|
0|UINT16|0x00000059
+
+# HDA Verb Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x
0000005A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0
x0000005B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|
0x0000005C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|
UINT32|0x0000005D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|
UINT32|0x0000005E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|
UINT32|0x0000005F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|
0|UINT32|0x00000060
+
+# SA Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x0
0000066
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|
0|UINT16|0x00000067
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0
x00000101
+
+# DRAM Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT3
2|0x00000068
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|
0x00000069
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0
x0000006A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT1
6|0x0000006B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UI
NT32|0x0000006C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0
|UINT16|0x0000006D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
|FALSE|BOOLEAN|0x0000006E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE
|BOOLEAN|0x0000006F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00
000070
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0
x00000071
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|
BOOLEAN|0x00000072
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE
|BOOLEAN|0x00000073
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32
|0x00000079
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|
UINT8|0x0000007A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT
32|0x0000007B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|B
OOLEAN|0x0000007C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
|0|UINT8|0x0000007D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UI
NT32|0x0000007E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE
|BOOLEAN|0x0000007F
+
+# SPD Address Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UIN
T8|0x00000099
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UIN
T8|0x0000009A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UIN
T8|0x0000009B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UIN
T8|0x0000009C
+
+# CA Vref Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0
x0000009D
+
+# USB 2.0 Port AFE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x
000000BF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x
000000C0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x
000000C1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x
000000C2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x
000000C3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x
000000C4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x
000000C5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x
000000C6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x
000000C7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x
000000C8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0
x000000C9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0
x000000CA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0
x000000CB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0
x000000CC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0
x000000CD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0
x000000CE
+
+# USB 2.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|
0|UINT8|0x000000CF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|
0|UINT8|0x000000D0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|
0|UINT8|0x000000D1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|
0|UINT8|0x000000D2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|
0|UINT8|0x000000D3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|
0|UINT8|0x000000D4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|
0|UINT8|0x000000D5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|
0|UINT8|0x000000D6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|
0|UINT8|0x000000D7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|
0|UINT8|0x000000D8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
|0|UINT8|0x000000D9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
|0|UINT8|0x000000DA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
|0|UINT8|0x000000DB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
|0|UINT8|0x000000DC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
|0|UINT8|0x000000DD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
|0|UINT8|0x000000DE
+
+# USB 3.0 Port Over Current Pin
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|
0|UINT8|0x000000DF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|
0|UINT8|0x000000E0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|
0|UINT8|0x000000E1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|
0|UINT8|0x000000E2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|
0|UINT8|0x000000E3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|
0|UINT8|0x000000E4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|
0|UINT8|0x000000E5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|
0|UINT8|0x000000E6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|
0|UINT8|0x000000E7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|
0|UINT8|0x000000E8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|B
OOLEAN|0x000000EC
+
+# TBT
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel
|0|BOOLEAN|0x000000F3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad
|0|UINT32|0x000000F4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad
|0|UINT32|0x000000F5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport
|0|UINT8|0x000000FA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI
|0|UINT8|0x000000FB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify
|0|UINT8|0x000000FC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x0
00000FD
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm
|0|UINT8|0x000000FE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8|
0x00000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch
|0|UINT8|0x000000FF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt
|0|UINT8|0x00000100
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq
|0|UINT8|0x0000010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax
|0|UINT8|0x00000107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd
|0|UINT16|0x00000108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax
|0|UINT8|0x00000109
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UIN
T32|0x000000111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|
UINT16|0x000000112
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x4
0000002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x4
0000003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0
x40000004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x400
00005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8
|0x40000006
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UI
NT8|0x4000000A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|
UINT8|0x4000000B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|U
INT8|0x4000000C
+
+# 0: Type-C
+# 1: Stacked-Jack
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0
x40000012
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|
0x40000013
+
+# gIntelPeiGraphicsVbtGuid = {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0,
0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}}
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61,
0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d,
0xb0}|VOID*|0x40000014
+#==============================================================
+#
+# The PCD which indicates the Memory Slot Population.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardT
ype|FALSE|BOOLEAN|0x00101027
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpda
te|0|UINT64|0x00000010
+
+# Board GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarl
yPreMem|0|UINT32|0x001000115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarl
yPreMemSize|0|UINT16|0x001000116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarl
yPreMem|0|UINT32|0x001000117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarl
yPreMemSize|0|UINT16|0x001000118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
|0x0|UINT32|0x0010020C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|
UINT8|0x0010022E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32
|0x0010022F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32
|0x00100230
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BO
OLEAN|0x00100231
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32
|0x00100234
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWlanRootPortNumber|0x0|
UINT8|0x00100235
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround|FAL
SE|BOOLEAN|0x00100236
+
+# UCMC GPIO Table
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable|0|UIN
T32|0x00100033
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|
UINT16|0x00100034
+
+# PEG RESET GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT3
2|0x00000074
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|
BOOLEAN|0x00000075
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT3
2|0x00000105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|
BOOLEAN|0x00000106
+
+# PCIE RTD3 GPIO
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x
00000076
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0
x00000077
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|
0x00000104
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|
0x00000078
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|
0x00000080
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32
|0x00000081
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|
UINT8|0x00000082
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT
32|0x00000083
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|B
OOLEAN|0x00000084
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
|0|UINT8|0x00000085
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UI
NT32|0x00000086
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE
|BOOLEAN|0x00000087
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|
0x00000088
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32
|0x00000089
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|
UINT8|0x0000008A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT
32|0x0000008B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|B
OOLEAN|0x0000008C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
|0|UINT8|0x0000008D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UI
NT32|0x0000008E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE
|BOOLEAN|0x0000008F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|
0x00000130
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32
|0x00000131
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|
UINT8|0x00000132
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT
32|0x00000133
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|B
OOLEAN|0x00000134
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
|0|UINT8|0x00000135
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UI
NT32|0x00000136
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE
|BOOLEAN|0x00000137
+
+# Root Port Clock Info
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x000
0009E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x000
0009F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000
000A0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000
000A1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000
000A2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000
000A3
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000
000A4
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000
000A5
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000
000A6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000
000A7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x00
0000A8
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x00
0000A9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x00
0000AA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x00
0000AB
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x00
0000AC
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x00
0000AD
+
+# GPIO Group Tier
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UIN
T32|0x000000E9
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UIN
T32|0x000000EA
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UIN
T32|0x000000EB
+
+# Board related PCH PmConfig
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FAL
SE|BOOLEAN|0x000000F6
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE
|BOOLEAN|0x000000F7
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE
|BOOLEAN|0x000000F8
+
+# Misc
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|
BOOLEAN|0x000000ED
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|
BOOLEAN|0x000000EE
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BO
OLEAN|0x000000EF
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT
64|0x000000F0
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent|FALSE|B
OOLEAN|0x000000F1
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BO
OLEAN|0x000000F2
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE
|BOOLEAN|0x000000F9
+#gCometlakeOpenBoardPkgTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLE
AN|0x000000FC
+
+#PlatformInfoPcd
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEnableVoltageMargining|FAL
SE|BOOLEAN|0x00101000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLE
AN|0x00101001
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BO
OLEAN|0x00101002
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0
x00101003
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x
00101004
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|
0x00101005
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardName|L"0123456789A
BCDEF0123456789ABCDEF"|VOID*|0x00101007
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8
|0x00101008
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8
|0x00101009
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBiosVersion|L"012345678901
2345678901234567890123456789"|VOID*|0x0010100E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseDate|L"01234567890
123456789"|VOID*|0x0010100F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdReleaseTime|L"01234567890
123456789"|VOID*|0x00101010
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformGeneration|0x0|UIN
T8|0x00101011
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN
|0x00101012
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDockAttached|FALSE|BOOLE
AN|0x00101013
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x
00101014
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0
x00101015
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x001
01016
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x0
0101017
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101
018
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00
101019
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|
0x0010101A
+
+# PCH Misc Configuration
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE
|BOOLEAN|0x00000061
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|
BOOLEAN|0x00000065
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosFabBoardName|0|UI
NT64|0x00000102
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UIN
T64|0x00000103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|
BOOLEAN|0x00000110
+
+# Control PCD to dump default silicon policy
+gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOO
LEAN|0x00010064
+
+# Pch SerialIo I2c Pads Termination
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTe
rm|0x1|UINT8|0x00000020
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTe
rm|0x1|UINT8|0x00000021
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTe
rm|0x1|UINT8|0x00000022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTe
rm|0x1|UINT8|0x00000023
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTe
rm|0x1|UINT8|0x00000030
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTe
rm|0x1|UINT8|0x00000031
+#
+# The PCD which holds the pointer of Smbios Platform Info table
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT6
4|0x0010101B
+#
+# The PCD which used to enable / disable the code to use RVP Smbios Board
Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FAL
SE|BOOLEAN|0x0010101C
+#
+# The PCD which holds the pointer of RVP Smbios Board Info
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|
0x0010101D
+#
+# CoEngineering Custom Defaults PCD
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCoEngEnableCustomDefaults
|0x0|UINT8|0x00100227
+#
+# The PCD which is defined to enable/disable the SMBus Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BO
OLEAN|0x0010101E
+#
+# The PCD which is defined to enable/disable the SATA LED function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLE
AN|0x0010101F
+#
+# The PCD which is defined to enable/disable the VR Alert function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLE
AN|0x00101020
+#
+# The PCD which is defined to enable/disable the PCH thermal hot threshold
function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable|FALSE
|BOOLEAN|0x00101021
+#
+# The PCD which is defined to enable/disable the memory thermal sensor
GPIO C/D function.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpio
CPmsyncEnable|TRUE|BOOLEAN|0x00101022
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpio
DPmsyncEnable|TRUE|BOOLEAN|0x00101023
+#
+# The PCD defines the I2C bus number to which PSS chip connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN
|0x00101024
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UIN
T8|0x00101025
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UI
NT8|0x00101026
+#
+# The PCD defines the USB port number to which BLE connected.
+#
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber
|0x0|UINT8|0x00101028
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support
|0x00|UINT8|0x00100113
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support
|0x00|UINT8|0x00100114
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support
|0x00|UINT8|0x00100115
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support
|0x00|UINT8|0x00100116
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support
|0x00|UINT8|0x00100117
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support
|0x00|UINT8|0x00100118
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupp
ort |FALSE|BOOLEAN|0x00100119
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownS
upport |FALSE|BOOLEAN|0x0010011A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSu
pport |FALSE|BOOLEAN|0x0010011B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSu
pport |FALSE|BOOLEAN|0x0010011C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport
|FALSE|BOOLEAN|0x0010011D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport
|FALSE|BOOLEAN|0x0010011F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin
|0x00|UINT32|0x00100120
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
|FALSE|BOOLEAN|0x00100121
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
|FALSE|BOOLEAN|0x00100122
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature
|FALSE|BOOLEAN|0x00100123
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent
|0x0|UINT8|0x00100124
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BO
OLEAN|0x00100212
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOO
LEAN|0x00100213
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|
UINT64|0x00100204
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile|0x0|UIN
T8|0x00100205
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UI
NT32|0x00100209
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT
32|0x0010020A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|
0x0010020B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT3
2|0x0010020F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UIN
T32|0x00100210
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio
|0x0|UINT32|0x00100126
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber
|0x0|UINT8|0x00100127
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x0
0100200
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio
|0x0|UINT32|0x00100125
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x
00100201
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALS
E|BOOLEAN|0x00100202
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride|FALSE|
BOOLEAN|0x00100203
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x0
0100215
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT
64|0x00100217
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8
|0x00100039
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UI
NT8|0x0010003A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|U
INT8|0x0010003B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8
|0x0010003C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UI
NT8|0x0010003D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|U
INT8|0x0010003E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8
|0x0010003F
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UI
NT8|0x00100040
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|U
INT8|0x00100041
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8
|0x00100042
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UI
NT8|0x00100043
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|U
INT8|0x00100044
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8
|0x00100045
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UI
NT8|0x00100046
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|U
INT8|0x00100047
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8
|0x00100048
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UI
NT8|0x00100049
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|U
INT8|0x0010004A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed
|0x0|UINT8|0x00100128
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed
|0x0|UINT8|0x00100129
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed
|0x0|UINT8|0x0010012A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed
|0x0|UINT8|0x0010012B
+
+# Super IO Pcd
+gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF
0000100
+gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0x
F0000104
+gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0
000105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport
|FALSE|BOOLEAN|0x00100112
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin
|0x00|UINT32|0x00100111
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control
|0x00|UINT8|0x00100103
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control
|0x00|UINT8|0x00100104
+
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError|FALSE
|BOOLEAN|0x00100221
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x00
10020E
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x
0010020D
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCmlURtd3TableEnable|FALSE
|BOOLEAN|0x0010022C
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported|0x00|
UINT8|0x0010004B
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor
|FALSE|BOOLEAN|0x00100105
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO
|FALSE|BOOLEAN|0x0010010A
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM
|FALSE|BOOLEAN|0x00100107
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO
|FALSE|BOOLEAN|0x00100108
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON
|FALSE|BOOLEAN|0x00100109
+
+[PcdsDynamicEx]
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
|TRUE|BOOLEAN|0xF0000062
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport
|TRUE|BOOLEAN|0xF0000000
+gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable
|FALSE|BOOLEAN|0x000000115
+
--
2.16.2.windows.1


Re: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Liming Gao
 

Reviewed-by: Liming Gao <liming.gao@...>

PR https://github.com/tianocore/edk2/pull/366

-----Original Message-----
From: Felix Polyudov <Felixp@...>
Sent: Wednesday, February 12, 2020 6:35 AM
To: Gao, Liming <liming.gao@...>; 'devel@edk2.groups.io' <devel@edk2.groups.io>
Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Liming,

Any update on this patch?

-----Original Message-----
From: Felix Polyudov
Sent: Friday, February 07, 2020 3:58 PM
To: 'Gao, Liming'; devel@edk2.groups.io
Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam
Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Yes, we did build tests on Windows/VS and Linux/GCC.

-----Original Message-----
From: Gao, Liming [mailto:liming.gao@...]
Sent: Friday, February 07, 2020 12:10 AM
To: Felix Polyudov; devel@edk2.groups.io
Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam
Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Felix:
The patch is good. Is any test for the header file, such as build?

Thanks
Liming
-----Original Message-----
From: Felix Polyudov <felixp@...>
Sent: Wednesday, February 5, 2020 5:30 AM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; manickavasakamk@...
Subject: [PATCH] MdePkg: Add PCI Express 5.0 Header File

The header includes Physical Layer PCI Express Extended Capability
definitions based on section 7.7.6 of PCI Express Base Specification 5.0.

Signed-off-by: Felix Polyudov <felixp@...>
---
MdePkg/Include/IndustryStandard/PciExpress50.h | 136 +++++++++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h

diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644
index 0000000..26eae0b
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file
+Support for the PCI Express 5.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS50_H_
+#define _PCIEXPRESS50_H_
+
+#include <IndustryStandard/PciExpress40.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
+ UINT32 Reserved2 : 16; // Reserved bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
+ UINT32 Reserved2 : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 ModifiedTSRcvd : 1; // bit 5
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
+ UINT32 TransmitterPrecodingOn : 1; // bit 8
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10
+ UINT32 Reserved : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
+///@}
+
+#pragma pack()
+
+#endif
--
2.10.0.windows.1


Please consider the environment before printing this email.

The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is
intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the
intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify
the
sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.
Please consider the environment before printing this email.

The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is
intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the
intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify the
sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.


[PATCH v3] IntelSiliconPkg: FIT based shadow microcode PPI support.

Siyuan, Fu
 

V3 Changes:
Remove the feature PCD PcdCpuShadowMicrocodeByFit because the
whole FIT microcode shadow code is moved to this PEIM so platform
could disable this feature by not include PEIM now.

V2 Changes:
Rename EDKII_PEI_CPU_MICROCODE_ID to EDKII_PEI_MICROCODE_CPU_ID.

This patch adds a platform PEIM for FIT based shadow microcode PPI
support. A detailed design doc can be found here:
https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20
the%202nd%20Microcode%20FV%20Flash%20Region.pdf

TEST: Tested on FIT enabled platform.
BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449

Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Signed-off-by: Siyuan Fu <siyuan.fu@...>
---
.../ShadowMicrocode/ShadowMicrocodePei.c | 387 ++++++++++++++++++
.../ShadowMicrocode/ShadowMicrocodePei.h | 62 +++
.../ShadowMicrocode/ShadowMicrocodePei.inf | 44 ++
.../Include/Guid/MicrocodeShadowInfoHob.h | 57 +++
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 6 +
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 3 +-
6 files changed, 558 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.h
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c
new file mode 100644
index 0000000000..c754524f41
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c
@@ -0,0 +1,387 @@
+/** @file
+ Source code file for Platform Init PEI module
+
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "ShadowMicrocodePei.h"
+
+EDKII_PEI_SHADOW_MICROCODE_PPI mPeiShadowMicrocodePpi = {
+ ShadowMicrocode
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPeiShadowMicrocodePpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEdkiiPeiShadowMicrocodePpiGuid,
+ &mPeiShadowMicrocodePpi
+ }
+};
+
+/**
+ Determine if a microcode patch matchs the specific processor signature and flag.
+
+ @param[in] CpuIdCount Number of elements in MicrocodeCpuId array.
+ @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICROCODE_CPU_ID
+ structures.
+ @param[in] ProcessorSignature The processor signature field value
+ supported by a microcode patch.
+ @param[in] ProcessorFlags The prcessor flags field value supported by
+ a microcode patch.
+
+ @retval TRUE The specified microcode patch will be loaded.
+ @retval FALSE The specified microcode patch will not be loaded.
+**/
+BOOLEAN
+IsProcessorMatchedMicrocodePatch (
+ IN UINTN CpuIdCount,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ IN UINT32 ProcessorSignature,
+ IN UINT32 ProcessorFlags
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < CpuIdCount; Index++) {
+ if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&
+ (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+/**
+ Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode
+ patch header with the CPUID and PlatformID of the processors within
+ system to decide if it will be copied into memory.
+
+ @param[in] CpuIdCount Number of elements in MicrocodeCpuId array.
+ @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICROCODE_CPU_ID
+ structures.
+ @param[in] MicrocodeEntryPoint The pointer to the microcode patch header.
+
+ @retval TRUE The specified microcode patch need to be loaded.
+ @retval FALSE The specified microcode patch dosen't need to be loaded.
+**/
+BOOLEAN
+IsMicrocodePatchNeedLoad (
+ IN UINTN CpuIdCount,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ CPU_MICROCODE_HEADER *MicrocodeEntryPoint
+ )
+{
+ BOOLEAN NeedLoad;
+ UINTN DataSize;
+ UINTN TotalSize;
+ CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
+ UINT32 ExtendedTableCount;
+ CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
+ UINTN Index;
+
+ //
+ // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcode patch header.
+ //
+ NeedLoad = IsProcessorMatchedMicrocodePatch (
+ CpuIdCount,
+ MicrocodeCpuId,
+ MicrocodeEntryPoint->ProcessorSignature.Uint32,
+ MicrocodeEntryPoint->ProcessorFlags
+ );
+
+ //
+ // If the Extended Signature Table exists, check if the processor is in the
+ // support list
+ //
+ DataSize = MicrocodeEntryPoint->DataSize;
+ TotalSize = (DataSize == 0) ? 2048 : MicrocodeEntryPoint->TotalSize;
+ if ((!NeedLoad) && (DataSize != 0) &&
+ (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) +
+ sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))) {
+ ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT8 *) (MicrocodeEntryPoint)
+ + DataSize + sizeof (CPU_MICROCODE_HEADER));
+ ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;
+ ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);
+
+ for (Index = 0; Index < ExtendedTableCount; Index ++) {
+ //
+ // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Extended
+ // Signature Table entry with the CPUID and PlatformID of the processors
+ // within system to decide if it will be copied into memory
+ //
+ NeedLoad = IsProcessorMatchedMicrocodePatch (
+ CpuIdCount,
+ MicrocodeCpuId,
+ ExtendedTable->ProcessorSignature.Uint32,
+ ExtendedTable->ProcessorFlag
+ );
+ if (NeedLoad) {
+ break;
+ }
+ ExtendedTable ++;
+ }
+ }
+
+ return NeedLoad;
+}
+
+/**
+ Actual worker function that shadows the required microcode patches into memory.
+
+ @param[in] Patches The pointer to an array of information on
+ the microcode patches that will be loaded
+ into memory.
+ @param[in] PatchCount The number of microcode patches that will
+ be loaded into memory.
+ @param[in] TotalLoadSize The total size of all the microcode patches
+ to be loaded.
+ @param[out] BufferSize Pointer to receive the total size of Buffer.
+ @param[out] Buffer Pointer to receive address of allocated memory
+ with microcode patches data in it.
+**/
+VOID
+ShadowMicrocodePatchWorker (
+ IN MICROCODE_PATCH_INFO *Patches,
+ IN UINTN PatchCount,
+ IN UINTN TotalLoadSize,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer
+ )
+{
+ UINTN Index;
+ VOID *MicrocodePatchInRam;
+ UINT8 *Walker;
+ EDKII_MICROCODE_SHADOW_INFO_HOB *MicrocodeShadowHob;
+ UINTN HobDataLength;
+ UINT64 *MicrocodeAddrInMemory;
+ UINT64 *MicrocodeAddrInFlash;
+
+ ASSERT ((Patches != NULL) && (PatchCount != 0));
+
+ //
+ // Init microcode shadow info HOB content.
+ //
+ HobDataLength = sizeof (EDKII_MICROCODE_SHADOW_INFO_HOB) +
+ sizeof (UINT64) * PatchCount * 2;
+ MicrocodeShadowHob = AllocatePool (HobDataLength);
+ if (MicrocodeShadowHob == NULL) {
+ ASSERT (FALSE);
+ return;
+ }
+ MicrocodeShadowHob->MicrocodeCount = PatchCount;
+ CopyGuid (
+ &MicrocodeShadowHob->StorageType,
+ &gEdkiiMicrocodeStorageTypeFlashGuid
+ );
+ MicrocodeAddrInMemory = (UINT64 *) (MicrocodeShadowHob + 1);
+ MicrocodeAddrInFlash = MicrocodeAddrInMemory + PatchCount;
+
+ //
+ // Allocate memory for microcode shadow operation.
+ //
+ MicrocodePatchInRam = AllocatePages (EFI_SIZE_TO_PAGES (TotalLoadSize));
+ if (MicrocodePatchInRam == NULL) {
+ ASSERT (FALSE);
+ return;
+ }
+
+ //
+ // Shadow all the required microcode patches into memory
+ //
+ for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) {
+ CopyMem (
+ Walker,
+ (VOID *) Patches[Index].Address,
+ Patches[Index].Size
+ );
+ MicrocodeAddrInMemory[Index] = (UINT64) Walker;
+ MicrocodeAddrInFlash[Index] = (UINT64) Patches[Index].Address;
+ Walker += Patches[Index].Size;
+ }
+
+ //
+ // Update the microcode patch related fields in CpuMpData
+ //
+ *Buffer = (VOID *) (UINTN) MicrocodePatchInRam;
+ *BufferSize = TotalLoadSize;
+
+ BuildGuidDataHob (
+ &gEdkiiMicrocodeShadowInfoHobGuid,
+ MicrocodeShadowHob,
+ HobDataLength
+ );
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
+ __FUNCTION__, *Buffer, *BufferSize
+ ));
+
+ return;
+}
+
+/**
+ Shadow the required microcode patches data into memory according
+ to FIT microcode entry.
+
+**/
+EFI_STATUS
+ShadowMicrocodePatchByFit (
+ IN UINTN CpuIdCount,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer
+ )
+{
+ UINT64 FitPointer;
+ FIRMWARE_INTERFACE_TABLE_ENTRY *FitEntry;
+ UINT32 EntryNum;
+ UINT32 Index;
+ MICROCODE_PATCH_INFO *PatchInfoBuffer;
+ UINTN MaxPatchNumber;
+ CPU_MICROCODE_HEADER *MicrocodeEntryPoint;
+ UINTN PatchCount;
+ UINTN TotalSize;
+ UINTN TotalLoadSize;
+
+ FitPointer = *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS;
+ if ((FitPointer == 0) ||
+ (FitPointer == 0xFFFFFFFFFFFFFFFF) ||
+ (FitPointer == 0xEEEEEEEEEEEEEEEE)) {
+ //
+ // No FIT table.
+ //
+ ASSERT (FALSE);
+ return EFI_NOT_FOUND;
+ }
+ FitEntry = (FIRMWARE_INTERFACE_TABLE_ENTRY *) (UINTN) FitPointer;
+ if ((FitEntry[0].Type != FIT_TYPE_00_HEADER) ||
+ (FitEntry[0].Address != FIT_TYPE_00_SIGNATURE)) {
+ //
+ // Invalid FIT table, treat it as no FIT table.
+ //
+ ASSERT (FALSE);
+ return EFI_NOT_FOUND;
+ }
+
+ EntryNum = *(UINT32 *)(&FitEntry[0].Size[0]) & 0xFFFFFF;
+
+ //
+ // Calculate microcode entry number
+ //
+ MaxPatchNumber = 0;
+ for (Index = 0; Index < EntryNum; Index++) {
+ if (FitEntry[Index].Type == FIT_TYPE_01_MICROCODE) {
+ MaxPatchNumber++;
+ }
+ }
+ if (MaxPatchNumber == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ PatchInfoBuffer = AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PATCH_INFO));
+ if (PatchInfoBuffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Fill up microcode patch info buffer according to FIT table.
+ //
+ PatchCount = 0;
+ TotalLoadSize = 0;
+ for (Index = 0; Index < EntryNum; Index++) {
+ if (FitEntry[Index].Type == FIT_TYPE_01_MICROCODE) {
+ MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[Index].Address;
+ TotalSize = (MicrocodeEntryPoint->DataSize == 0) ? 2048 : MicrocodeEntryPoint->TotalSize;
+ if (IsMicrocodePatchNeedLoad (CpuIdCount, MicrocodeCpuId, MicrocodeEntryPoint)) {
+ PatchInfoBuffer[PatchCount].Address = (UINTN) MicrocodeEntryPoint;
+ PatchInfoBuffer[PatchCount].Size = TotalSize;
+ TotalLoadSize += TotalSize;
+ PatchCount++;
+ }
+ }
+ }
+
+ if (PatchCount != 0) {
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",
+ __FUNCTION__, PatchCount, TotalLoadSize
+ ));
+
+ ShadowMicrocodePatchWorker (PatchInfoBuffer, PatchCount, TotalLoadSize, BufferSize, Buffer);
+ }
+
+ FreePool (PatchInfoBuffer);
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Shadow microcode update patches to memory.
+
+ The function is used for shadowing microcode update patches to a continuous memory.
+ It shall allocate memory buffer and only shadow the microcode patches for those
+ processors specified by MicrocodeCpuId array. The checksum verification may be
+ skiped in this function so the caller must perform checksum verification before
+ using the microcode patches in returned memory buffer.
+
+ @param[in] This The PPI instance pointer.
+ @param[in] CpuIdCount Number of elements in MicrocodeCpuId array.
+ @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICROCODE_CPU_ID
+ structures.
+ @param[out] BufferSize Pointer to receive the total size of Buffer.
+ @param[out] Buffer Pointer to receive address of allocated memory
+ with microcode patches data in it.
+
+ @retval EFI_SUCCESS The microcode has been shadowed to memory.
+ @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.
+
+**/
+EFI_STATUS
+ShadowMicrocode (
+ IN EDKII_PEI_SHADOW_MICROCODE_PPI *This,
+ IN UINTN CpuIdCount,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer
+ )
+{
+ if (BufferSize == NULL || Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return ShadowMicrocodePatchByFit (CpuIdCount, MicrocodeCpuId, BufferSize, Buffer);
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+ShadowMicrocodePeimInit (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Install EDKII Shadow Microcode PPI
+ //
+ Status = PeiServicesInstallPpi(mPeiShadowMicrocodePpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.h b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.h
new file mode 100644
index 0000000000..04fe7cbfd3
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.h
@@ -0,0 +1,62 @@
+/** @file
+ Source code file for Platform Init PEI module
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SHADOW_MICROCODE_PEI_H__
+#define __SHADOW_MICROCODE_PEI_H__
+
+
+#include <PiPei.h>
+#include <Ppi/ShadowMicrocode.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Register/Intel/Microcode.h>
+#include <Register/Intel/Cpuid.h>
+#include <Guid/MicrocodeShadowInfoHob.h>
+//
+// Data structure for microcode patch information
+//
+typedef struct {
+ UINTN Address;
+ UINTN Size;
+} MICROCODE_PATCH_INFO;
+
+/**
+ Shadow microcode update patches to memory.
+
+ The function is used for shadowing microcode update patches to a continuous memory.
+ It shall allocate memory buffer and only shadow the microcode patches for those
+ processors specified by MicrocodeCpuId array. The checksum verification may be
+ skiped in this function so the caller must perform checksum verification before
+ using the microcode patches in returned memory buffer.
+
+ @param[in] This The PPI instance pointer.
+ @param[in] CpuIdCount Number of elements in MicrocodeCpuId array.
+ @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICROCODE_CPU_ID
+ structures.
+ @param[out] BufferSize Pointer to receive the total size of Buffer.
+ @param[out] Buffer Pointer to receive address of allocated memory
+ with microcode patches data in it.
+
+ @retval EFI_SUCCESS The microcode has been shadowed to memory.
+ @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of resources.
+
+**/
+EFI_STATUS
+ShadowMicrocode (
+ IN EDKII_PEI_SHADOW_MICROCODE_PPI *This,
+ IN UINTN CpuIdCount,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer
+ );
+
+#endif
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf
new file mode 100644
index 0000000000..b2773998ce
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf
@@ -0,0 +1,44 @@
+### @file
+# Component information file for the Platform Init PEI module.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = ShadowMicrocodePei
+ FILE_GUID = 8af4cf68-ebe4-4b21-a008-0cb3da277be5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = ShadowMicrocodePeimInit
+
+[Sources]
+ ShadowMicrocodePei.c
+ ShadowMicrocodePei.h
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Ppis]
+ gEdkiiPeiShadowMicrocodePpiGuid ## PRODUCES
+
+[Guids]
+ gEdkiiMicrocodeShadowInfoHobGuid
+ gEdkiiMicrocodeStorageTypeFlashGuid
+
+[Depex]
+ TRUE
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h
new file mode 100644
index 0000000000..59a38cee74
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h
@@ -0,0 +1,57 @@
+/** @file
+ The definition for VTD PMR Regions Information Hob.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#ifndef _MICROCODE_SHADOW_INFO_HOB_H_
+#define _MICROCODE_SHADOW_INFO_HOB_H_
+
+///
+/// The Global ID of a GUIDed HOB used to pass microcode shadow info to DXE Driver.
+///
+#define EDKII_MICROCODE_SHADOW_INFO_HOB_GUID \
+ { \
+ 0x658903f9, 0xda66, 0x460d, { 0x8b, 0xb0, 0x9d, 0x2d, 0xdf, 0x65, 0x44, 0x59 } \
+ }
+
+extern EFI_GUID gEdkiiMicrocodeShadowInfoHobGuid;
+
+typedef struct {
+ //
+ // Number of the microcode patches which have been
+ // relocated to memory.
+ //
+ UINT64 MicrocodeCount;
+ //
+ // An EFI_GUID that defines the contents of StorageContext.
+ //
+ GUID StorageType;
+ //
+ // An array with MicrocodeCount elements that stores
+ // the shadowed microcode patch address in memory.
+ //
+ UINT64 MicrocodeAddrInMemory[0];
+ //
+ // A buffer which contains details about the storage information
+ // specific to StorageType.
+ //
+ // UINT8 StorageContext[];
+} EDKII_MICROCODE_SHADOW_INFO_HOB;
+
+//
+// An EDKII_MICROCODE_SHADOW_INFO_HOB with StorageType set to below GUID will
+// have the StorageContext of an array with MicrocodeCount of UINT64 elements
+// that stores the original microcode patch address on flash. This address is
+// placed in same order as the microcode patches in MicrocodeAddrInMemory.
+//
+#define EFI_MICROCODE_STORAGE_TPYE_FLASH_GUID \
+ { \
+ 0x2cba01b3, 0xd391, 0x4598, { 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } \
+ }
+
+extern EFI_GUID gEdkiiMicrocodeStorageTypeFlashGuid;
+
+#endif
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 22ebf19c4e..2d8e40f0b8 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -48,6 +48,12 @@
## HOB GUID to get memory information after MRC is done. The hob data will be used to set the PMR ranges
gVtdPmrInfoDataHobGuid = {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } }

+ ## Include/Guid/MicrocodeShadowInfoHob.h
+ gEdkiiMicrocodeShadowInfoHobGuid = { 0x658903f9, 0xda66, 0x460d, { 0x8b, 0xb0, 0x9d, 0x2d, 0xdf, 0x65, 0x44, 0x59 } }
+
+ ## Include/Guid/MicrocodeShadowInfoHob.h
+ gEdkiiMicrocodeStorageTypeFlashGuid = { 0x2cba01b3, 0xd391, 0x4598, { 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } }
+
[Ppis]
gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }

diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
index 0a6509d8b3..f995883691 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -1,7 +1,7 @@
## @file
# This package provides common open source Intel silicon modules.
#
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -84,6 +84,7 @@
IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf
IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
+ IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf
IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf
IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib.inf

--
2.19.1.windows.1


Re: [EXTERNAL] [edk2-devel] [Patch 0/2] Disable EBC for unit tests

Bret Barkelew <bret.barkelew@...>
 

Reviewed-by: Bret Barkelew <bret.barkelew@...>

 

- Bret

 


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Michael D Kinney via Groups.Io <michael.d.kinney@...>
Sent: Monday, February 10, 2020 12:24:39 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Sean Brogan <sean.brogan@...>; Bret Barkelew <Bret.Barkelew@...>
Subject: [EXTERNAL] [edk2-devel] [Patch 0/2] Disable EBC for unit tests
 
https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2514&amp;data=02%7C01%7Cbret.barkelew%40microsoft.com%7C63ad9885002b4558953a08d7ae6744e3%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637169630884257799&amp;sdata=OYyaAI0jpK0TfrHA9G9mqZf8Nsp%2BYQoDjMWNAKBh3AA%3D&amp;reserved=0

Cc: Sean Brogan <sean.brogan@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Signed-off-by: Michael D Kinney <michael.d.kinney@...>

Michael D Kinney (2):
  UnitTestFrameworkPkg: Disable EBC in DSC file
  MdePkg: Disable EBC for unit tests in MdePkg.dsc

 MdePkg/MdePkg.dsc                             | 1 +
 UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

--
2.21.0.windows.1





Re: [EXTERNAL] [edk2-devel] [Patch 1/2] UnitTestFrameworkPkg: Disable EBC in DSC file

Bret Barkelew <bret.barkelew@...>
 

Reviewed-by: Bret Barkelew <Bret.Barkelew@...>

 

- Bret

 


From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Michael D Kinney via Groups.Io <michael.d.kinney@...>
Sent: Monday, February 10, 2020 12:24:40 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Sean Brogan <sean.brogan@...>; Bret Barkelew <Bret.Barkelew@...>
Subject: [EXTERNAL] [edk2-devel] [Patch 1/2] UnitTestFrameworkPkg: Disable EBC in DSC file
 
https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D2514&amp;data=02%7C01%7Cbret.barkelew%40microsoft.com%7C9e9da4e9e08b40dca06308d7ae67455a%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637169630879174350&amp;sdata=ye%2FQPMZgnrj8BE3spu07pO5optLKsh%2F%2Fa8YRZruZZ94%3D&amp;reserved=0

Remove EBC as one of the supported architectures
in the UnitTestFrameworkPkg DSC file.  The EBC
compiler does not support cararg macros and the
UnitTestLib class uses this feature.

Cc: Sean Brogan <sean.brogan@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Signed-off-by: Michael D Kinney <michael.d.kinney@...>
---
 UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
index 0ad4482273..53d8f52754 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
@@ -13,7 +13,7 @@ [Defines]
   PLATFORM_VERSION        = 1.00
   DSC_SPECIFICATION       = 0x00010005
   OUTPUT_DIRECTORY        = Build/UnitTestFrameworkPkg
-  SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64
+  SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64
   BUILD_TARGETS           = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER        = DEFAULT
 
--
2.21.0.windows.1





Re: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Felix Polyudov
 

Liming,

Any update on this patch?

-----Original Message-----
From: Felix Polyudov
Sent: Friday, February 07, 2020 3:58 PM
To: 'Gao, Liming'; devel@edk2.groups.io
Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam
Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Yes, we did build tests on Windows/VS and Linux/GCC.

-----Original Message-----
From: Gao, Liming [mailto:liming.gao@...]
Sent: Friday, February 07, 2020 12:10 AM
To: Felix Polyudov; devel@edk2.groups.io
Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam
Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File

Felix:
The patch is good. Is any test for the header file, such as build?

Thanks
Liming
-----Original Message-----
From: Felix Polyudov <felixp@...>
Sent: Wednesday, February 5, 2020 5:30 AM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@...>; Gao, Liming <liming.gao@...>; manickavasakamk@...
Subject: [PATCH] MdePkg: Add PCI Express 5.0 Header File

The header includes Physical Layer PCI Express Extended Capability
definitions based on section 7.7.6 of PCI Express Base Specification 5.0.

Signed-off-by: Felix Polyudov <felixp@...>
---
MdePkg/Include/IndustryStandard/PciExpress50.h | 136 +++++++++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h

diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644
index 0000000..26eae0b
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file
+Support for the PCI Express 5.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS50_H_
+#define _PCIEXPRESS50_H_
+
+#include <IndustryStandard/PciExpress40.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
+ UINT32 Reserved2 : 16; // Reserved bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1
+ UINT32 Reserved1 : 6; // Reserved bit 2:7
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
+ UINT32 Reserved2 : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 ModifiedTSRcvd : 1; // bit 5
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
+ UINT32 TransmitterPrecodingOn : 1; // bit 8
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10
+ UINT32 Reserved : 21; // Reserved bit 11:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
+
+typedef union {
+ struct {
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+ UINT32 Reserved : 6; // Reserved bit 26:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
+///@}
+
+#pragma pack()
+
+#endif
--
2.10.0.windows.1


Please consider the environment before printing this email.

The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is
intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the
intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify the
sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.
Please consider the environment before printing this email.

The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify the sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.


Re: Shell feature?

Jim Dailey <jim.dailey@...>
 

Andrew,

Granted such a feature would be nice, but it seems like it might be a
fair amount of trouble just to avoid typing "python3", which could be
aliased to something as short a "p".

Jim

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Tim Lewis
Sent: Tuesday, February 11, 2020 2:28 PM
To: devel@edk2.groups.io; afish@...
Subject: Re: [edk2-devel] Shell feature?


[EXTERNAL EMAIL]

Andrew --

I think this is a good idea, but I think this is probably a shell spec issue
because I don't want competing, incompatible implementations.

A few other issues: I think there is a persistence issue (similar to shell
variables) so that the change could be installed and survive a reboot. I
also think there can be a simple shell command that manages extensions (so
that they can be installed by a script)

Tim

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Andrew Fish
via Groups.Io
Sent: Monday, February 10, 2020 12:12 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] Shell feature?

I wanted to start a conversation on the mailing list prior to writing up a
BZ, to make sure I'm not missing anything, or in case there is a better way
to implement this.

I was thinking it would be good to have a Shell API that lets you associate
a file type with an internal or external shell command. The Idea would be to
pre-pend the internal/external shell command to the file name and also pass
the arguments.

So this:
fs0:>dump.py 1 2 3

Becomes:
fs0:>python3.efi dump.py 1 2 3

Basically you just need an API like:

ShellAddScriptingLanguage (L".py", L"python3.efi");

Seems like this could just plug into the Shell via a ShellExecute(). So for
example you could make Python a UEFI Shell command via a library and that
library constructor could also teach the shell that a .py file could be an
executable?

Thanks,

Andrew Fish


Re: Shell feature?

Tim Lewis
 

Andrew --

I think this is a good idea, but I think this is probably a shell spec issue
because I don't want competing, incompatible implementations.

A few other issues: I think there is a persistence issue (similar to shell
variables) so that the change could be installed and survive a reboot. I
also think there can be a simple shell command that manages extensions (so
that they can be installed by a script)

Tim

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Andrew Fish
via Groups.Io
Sent: Monday, February 10, 2020 12:12 PM
To: devel@edk2.groups.io
Subject: [edk2-devel] Shell feature?

I wanted to start a conversation on the mailing list prior to writing up a
BZ, to make sure I'm not missing anything, or in case there is a better way
to implement this.

I was thinking it would be good to have a Shell API that lets you associate
a file type with an internal or external shell command. The Idea would be to
pre-pend the internal/external shell command to the file name and also pass
the arguments.

So this:
fs0:>dump.py 1 2 3

Becomes:
fs0:>python3.efi dump.py 1 2 3

Basically you just need an API like:

ShellAddScriptingLanguage (L".py", L"python3.efi");

Seems like this could just plug into the Shell via a ShellExecute(). So for
example you could make Python a UEFI Shell command via a library and that
library constructor could also teach the shell that a .py file could be an
executable?

Thanks,

Andrew Fish


Re: A problem with live migration of UEFI virtual machines

Alex Bennée <alex.bennee@...>
 

wuchenye1995 <wuchenye1995@...> writes:

Hi all,
We found a problem with live migration of UEFI virtual machines due to size of OVMF.fd changes.
Specifically, the size of OVMF.fd in edk with low version such as edk-2.0-25 is 2MB while the size of it in higher version such as edk-2.0-30 is 4MB.
When we migrate a UEFI virtual machine from the host with low version of edk2 to the host with higher one, qemu component will report an error in function qemu_ram_resize while
checking size of ovmf_pcbios: Length mismatch: pc.bios: 0x200000 in != 0x400000: Invalid argument.
We want to know how to solve this problem after updating the
version of edk2.
You can only migrate a machine that is identical - so instantiating a
empty machine with a different EDK image is bound to cause a problem
because the machines don't match.

--
Alex Bennée


[RFC PATCH 1/1] OvmfPkg: add 'initrd' shell command to expose Linux initrd via device path

Ard Biesheuvel <ard.biesheuvel@...>
 

Add a new 'initrd' command to the UEFI Shell that allows any file that is
accessible to the shell to be registered as the initrd that is returned
when Linux's EFI stub loader invokes the LoadFile2 protocol on its special
vendor media device path.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@...>
---
Note that the vendor media device path initrd loading method is still
under review on the Linux side, so this is for discussion only for now.

ArmVirtPkg/ArmVirt.dsc.inc | 1 +
OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.c | 269 ++++++++++++++++++++
OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf | 49 ++++
OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.uni | 37 +++
OvmfPkg/OvmfPkg.dec | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 1 +
OvmfPkg/OvmfPkgIa32X64.dsc | 1 +
OvmfPkg/OvmfPkgX64.dsc | 1 +
8 files changed, 360 insertions(+)

diff --git a/ArmVirtPkg/ArmVirt.dsc.inc b/ArmVirtPkg/ArmVirt.dsc.inc
index 10037c938eb8..0570eba6ed0c 100644
--- a/ArmVirtPkg/ArmVirt.dsc.inc
+++ b/ArmVirtPkg/ArmVirt.dsc.inc
@@ -382,6 +382,7 @@ [Components.common]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
diff --git a/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.c b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.c
new file mode 100644
index 000000000000..cfa4526df6d8
--- /dev/null
+++ b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.c
@@ -0,0 +1,269 @@
+/** @file
+ Provides initrd command to load a Linux initrd via its GUIDed vendor media
+ path
+
+ Copyright (c) 2020, Arm, Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ShellCommandLib.h>
+#include <Library/ShellLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/LoadFile2.h>
+
+#pragma pack(1)
+typedef struct {
+ VENDOR_DEVICE_PATH VenMediaNode;
+ EFI_DEVICE_PATH_PROTOCOL EndNode;
+} SINGLE_NODE_VENDOR_MEDIA_DEVPATH;
+#pragma pack()
+
+STATIC CONST CHAR16 mFileName[] = L"<unspecified>";
+STATIC EFI_HII_HANDLE gLinuxInitrdShellCommandHiiHandle;
+STATIC SHELL_FILE_HANDLE mInitrdFileHandle;
+STATIC EFI_HANDLE mInitrdLoadFile2Handle;
+
+STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
+ {L"-u", TypeFlag},
+ {NULL, TypeMax}
+ };
+
+/**
+ Get the filename to get help text from if not using HII.
+
+ @retval The filename.
+**/
+STATIC
+CONST CHAR16*
+EFIAPI
+ShellCommandGetManFileNameInitrd (
+ VOID
+ )
+{
+ return mFileName;
+}
+
+STATIC CONST SINGLE_NODE_VENDOR_MEDIA_DEVPATH mInitrdDevicePath = {
+ {
+ {
+ MEDIA_DEVICE_PATH, MEDIA_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH) }
+ },
+ {
+ // LINUX_EFI_INITRD_MEDIA_GUID
+ 0x5568e427, 0x68fc, 0x4f3d,
+ { 0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68 }
+ }
+ },
+
+ {
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ { sizeof (EFI_DEVICE_PATH_PROTOCOL) }
+ }
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+InitrdLoadFile2 (
+ IN EFI_LOAD_FILE2_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *FilePath,
+ IN BOOLEAN BootPolicy,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer OPTIONAL
+ )
+{
+ UINTN InitrdSize;
+ EFI_STATUS Status;
+
+ if (BootPolicy) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (BufferSize == NULL || !IsDevicePathValid (FilePath, 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FilePath->Type != END_DEVICE_PATH_TYPE ||
+ FilePath->SubType != END_ENTIRE_DEVICE_PATH_SUBTYPE ||
+ mInitrdFileHandle == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = gEfiShellProtocol->GetFileSize (mInitrdFileHandle, &InitrdSize);
+ ASSERT_EFI_ERROR(Status);
+
+ if (Buffer == NULL || *BufferSize < InitrdSize) {
+ *BufferSize = InitrdSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ return gEfiShellProtocol->ReadFile (mInitrdFileHandle, BufferSize, Buffer);
+}
+
+STATIC CONST EFI_LOAD_FILE2_PROTOCOL mInitrdLoadFile2 = {
+ InitrdLoadFile2,
+};
+
+/**
+ Function for 'initrd' command.
+
+ @param[in] ImageHandle Handle to the Image (NULL if Internal).
+ @param[in] SystemTable Pointer to the System Table (NULL if Internal).
+**/
+SHELL_STATUS
+EFIAPI
+ShellCommandRunInitrd (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ LIST_ENTRY *Package;
+ CHAR16 *ProblemParam;
+ CONST CHAR16 *Param;
+ CONST CHAR16 *Filename;
+ SHELL_STATUS ShellStatus;
+
+ ProblemParam = NULL;
+ ShellStatus = SHELL_SUCCESS;
+
+ Status = ShellInitialize ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // parse the command line
+ //
+ Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
+ if (EFI_ERROR (Status)) {
+ if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM),
+ gLinuxInitrdShellCommandHiiHandle, L"initrd", ProblemParam);
+ FreePool (ProblemParam);
+ ShellStatus = SHELL_INVALID_PARAMETER;
+ } else {
+ ASSERT(FALSE);
+ }
+ } else {
+ if (ShellCommandLineGetCount (Package) > 2) {
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY),
+ gLinuxInitrdShellCommandHiiHandle, L"initrd");
+ ShellStatus = SHELL_INVALID_PARAMETER;
+ } else if (ShellCommandLineGetCount (Package) < 2) {
+ if (ShellCommandLineGetFlag(Package, L"-u")) {
+ if (mInitrdFileHandle != NULL) {
+ ShellCloseFile (&mInitrdFileHandle);
+ mInitrdFileHandle = NULL;
+ }
+ if (mInitrdLoadFile2Handle) {
+ gBS->UninstallMultipleProtocolInterfaces (mInitrdLoadFile2Handle,
+ &gEfiDevicePathProtocolGuid, &mInitrdDevicePath,
+ &gEfiLoadFile2ProtocolGuid, &mInitrdLoadFile2,
+ NULL);
+ mInitrdLoadFile2Handle = NULL;
+ }
+ } else {
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW),
+ gLinuxInitrdShellCommandHiiHandle, L"initrd");
+ ShellStatus = SHELL_INVALID_PARAMETER;
+ }
+ } else {
+ Param = ShellCommandLineGetRawValue (Package, 1);
+ ASSERT (Param != NULL);
+
+ Filename = ShellFindFilePath (Param);
+ if (Filename == NULL) {
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_FIND_FAIL),
+ gLinuxInitrdShellCommandHiiHandle, L"initrd", Param);
+ ShellStatus = SHELL_NOT_FOUND;
+ } else {
+ if (mInitrdFileHandle != NULL) {
+ ShellCloseFile (&mInitrdFileHandle);
+ mInitrdFileHandle = NULL;
+ }
+ Status = ShellOpenFileByName (Filename, &mInitrdFileHandle,
+ EFI_FILE_MODE_READ, 0);
+ if (EFI_ERROR (Status)) {
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_FILE_OPEN_FAIL),
+ gLinuxInitrdShellCommandHiiHandle, L"initrd", Param);
+ ShellStatus = SHELL_NOT_FOUND;
+ }
+ if (mInitrdLoadFile2Handle == NULL) {
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mInitrdLoadFile2Handle,
+ &gEfiDevicePathProtocolGuid, &mInitrdDevicePath,
+ &gEfiLoadFile2ProtocolGuid, &mInitrdLoadFile2,
+ NULL);
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ }
+ }
+
+ return ShellStatus;
+}
+
+/**
+ Constructor for the 'initrd' UEFI Shell command library
+
+ @param ImageHandle the image handle of the process
+ @param SystemTable the EFI System Table pointer
+
+ @retval EFI_SUCCESS the shell command handlers were installed sucessfully
+ @retval EFI_UNSUPPORTED the shell level required was not found.
+**/
+EFI_STATUS
+EFIAPI
+LinuxInitrdShellCommandLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ gLinuxInitrdShellCommandHiiHandle = HiiAddPackages (&gShellInitrdHiiGuid,
+ gImageHandle, LinuxInitrdShellCommandLibStrings, NULL);
+ if (gLinuxInitrdShellCommandHiiHandle == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ ShellCommandRegisterCommandName (L"initrd", ShellCommandRunInitrd,
+ ShellCommandGetManFileNameInitrd, 0, L"initrd", TRUE,
+ gLinuxInitrdShellCommandHiiHandle, STRING_TOKEN(STR_GET_HELP_INITRD));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Destructor for the library. free any resources.
+
+ @param ImageHandle The image handle of the process.
+ @param SystemTable The EFI System Table pointer.
+
+ @retval EFI_SUCCESS Always returned.
+**/
+EFI_STATUS
+EFIAPI
+LinuxInitrdShellCommandLibDestructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ if (gLinuxInitrdShellCommandHiiHandle != NULL) {
+ HiiRemovePackages (gLinuxInitrdShellCommandHiiHandle);
+ }
+
+ if (mInitrdLoadFile2Handle) {
+ gBS->UninstallMultipleProtocolInterfaces (mInitrdLoadFile2Handle,
+ &gEfiDevicePathProtocolGuid, &mInitrdDevicePath,
+ &gEfiLoadFile2ProtocolGuid, &mInitrdLoadFile2,
+ NULL);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
new file mode 100644
index 000000000000..ed8a0ca85e85
--- /dev/null
+++ b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
@@ -0,0 +1,49 @@
+## @file
+# Provides initrd command to load a Linux initrd via its GUIDed vendor media
+# path
+#
+# Copyright (c) 2020, Arm, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = LinuxInitrdShellCommandLib
+ FILE_GUID = 2f30da26-f51b-4b6f-85c4-31873c281bca
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER
+ CONSTRUCTOR = LinuxInitrdShellCommandLibConstructor
+ DESTRUCTOR = LinuxInitrdShellCommandLibDestructor
+
+#
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64
+#
+
+[Sources.common]
+ LinuxInitrdShellCommandLib.c
+ LinuxInitrdShellCommandLib.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ShellPkg/ShellPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ OvmfPkg/OvmfPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ HiiLib
+ MemoryAllocationLib
+ ShellCommandLib
+ ShellLib
+ UefiBootServicesTableLib
+
+[Protocols]
+ gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES
+
+[Guids]
+ gShellInitrdHiiGuid ## SOMETIMES_CONSUMES ## HII
diff --git a/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.uni b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.uni
new file mode 100644
index 000000000000..d4fe798b1ea2
--- /dev/null
+++ b/OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.uni
@@ -0,0 +1,37 @@
+// /**
+//
+// Copyright (c) 2020, Arm, Ltd. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// Module Name:
+//
+// LinuxInitrdShellCommandLib.uni
+//
+// Abstract:
+//
+// String definitions for 'initrd' UEFI Shell command
+//
+// **/
+
+/=#
+
+#langdef en-US "english"
+
+#string STR_GEN_PROBLEM #language en-US "%H%s%N: Unknown flag - '%H%s%N'\r\n"
+#string STR_GEN_TOO_MANY #language en-US "%H%s%N: Too many arguments.\r\n"
+#string STR_GEN_TOO_FEW #language en-US "%H%s%N: Too few arguments.\r\n"
+#string STR_GEN_FIND_FAIL #language en-US "%H%s%N: File not found - '%H%s%N'\r\n"
+#string STR_GEN_FILE_OPEN_FAIL #language en-US "%H%s%N: Cannot open file - '%H%s%N'\r\n"
+
+#string STR_GET_HELP_INITRD #language en-US ""
+".TH vol 0 "Registers or unregisters a file as Linux initrd."\r\n"
+".SH NAME\r\n"
+"Registers or unregisters a file as Linux initrd.\r\n"
+".SH SYNOPSIS\r\n"
+" \r\n"
+"initrd <FileName>\r\n"
+"initrd -u\r\n"
+".SH OPTIONS\r\n"
+" \r\n"
+" FileName - Specifies a file to register as initrd.\r\n"
+" -u - Unregisters any previously registered initrd files.\r\n"
diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index d5fee805ef4a..437b1d248895 100644
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -86,6 +86,7 @@ [Guids]
gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}
gEfiLegacyBiosGuid = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}
gEfiLegacyDevOrderVariableGuid = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}
+ gShellInitrdHiiGuid = {0xeda423e2, 0xf434, 0x4cdd, {0x8d, 0x5d, 0xb5, 0xb0, 0xc7, 0x2c, 0x56, 0xd9}}

[Protocols]
gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9a60eb8fe2b0..3ffaa9b3388f 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -817,6 +817,7 @@ [Components]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1d1480b50b02..691ba204a6ac 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -830,6 +830,7 @@ [Components.X64]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index c287a436f8ec..8df5390de132 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -828,6 +828,7 @@ [Components]
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|OvmfPkg/Library/LinuxInitrdShellCommandLib/LinuxInitrdShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
--
2.17.1


[edk2-platforms] [PATCH v2 7/7] Update Maintainers.txt for CometlakeOpenBoardPkg

Kathappan Esakkithevar
 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

This change adds owners to the the Maintainers.txt for CometlakeOpenBoardPkg.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
Maintainers.txt | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index e97ea5b343..96c2f2757c 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -178,6 +178,14 @@ M: Chasel Chiu <chasel.chiu@...>
M: Michael Kubacki <michael.a.kubacki@...>
M: Nate DeSimone <nathaniel.l.desimone@...>

+Platform/Intel/CometlakeOpenBoardPkg
+F: Platform/Intel/CometlakeOpenBoardPkg/
+M: Chasel Chiu <chasel.chiu@...>
+M: Nate DeSimone <nathaniel.l.desimone@...>
+M: Rangasai V Chaganty <rangasai.v.chaganty@...>
+R: Deepika Kethi Reddy <deepika.kethi.reddy@...>
+R: Kathappan Esakkithevar <kathappan.esakkithevar@...>
+
Platform/Intel/SimicsOpenBoardPkg
F: Platform/Intel/SimicsOpenBoardPkg/
M: Agyeman Prince <prince.agyeman@...>
--
2.16.2.windows.1


[edk2-platforms] [PATCH v2 6/7] CometlakeOpenBoardPkg/CometlakeURvp: Add DSC and build files

Kathappan Esakkithevar
 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Adds the DSC and build files necessary to build the
CometlakeURvp board instance.

Key files
=========
* build_config.cfg - Board-specific build configuration file.
* OpenBoardPkg.dsc - The CometlakeURvp board description file.
* OpenBoardPkgPcd.dsc - Used for other PCD customization.
* OpenBoardPkg.fdf - The CometlakeURvp board flash file.
* OpenBoardPkgBuildOption.dsc - Sets build options Based
on PCD values.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
.../CometlakeURvp/OpenBoardPkg.dsc | 454 +++++++++++++
.../CometlakeURvp/OpenBoardPkg.fdf | 702 +++++++++++++++++++++
.../CometlakeURvp/OpenBoardPkgBuildOption.dsc | 154 +++++
.../CometlakeURvp/OpenBoardPkgPcd.dsc | 404 ++++++++++++
.../CometlakeURvp/build_config.cfg | 34 +
5 files changed, 1748 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgBuildOption.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 0000000000..14e82ba34d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,454 @@
+## @file
+# The main build description file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEFINE PLATFORM_PACKAGE = MinPlatformPkg
+ DEFINE PLATFORM_SI_PACKAGE = CoffeelakeSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = CoffeelakeSiliconBinPkg
+ DEFINE PLATFORM_FSP_BIN_PACKAGE = CometLakeFspBinPkg/CometLake1
+ DEFINE PLATFORM_BOARD_PACKAGE = CometlakeOpenBoardPkg
+ DEFINE BOARD = CometlakeURvp
+ DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
+ DEFINE PEI_ARCH = IA32
+ DEFINE DXE_ARCH = X64
+ DEFINE TOP_MEMORY_ADDRESS = 0x0
+
+ #
+ # Default value for OpenBoardPkg.fdf use
+ #
+ DEFINE BIOS_SIZE_OPTION = SIZE_70
+
+ PLATFORM_NAME = $(PLATFORM_PACKAGE)
+ PLATFORM_GUID = 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA5C5E
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PROJECT)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = ALL
+
+ FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf
+ FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
+
+ #
+ # Include PCD configuration for this board.
+ #
+ !include AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWorkaround.dsc
+ !include OpenBoardPkgPcd.dsc
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this board.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # 0|DEFAULT is reserved and always required.
+ 0x1|CometlakeURvp
+
+################################################################################
+#
+# Includes section - other DSC file contents included for this board build.
+#
+################################################################################
+
+#######################################
+# Library Includes
+#######################################
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+
+#######################################
+# Component Includes
+#######################################
+# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed
+[Components.IA32]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
+
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed
+[Components.X64]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
+
+#######################################
+# Build Option Includes
+#######################################
+!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+!include OpenBoardPkgBuildOption.dsc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this board.
+#
+################################################################################
+
+[LibraryClasses.common]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
+ MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
+ PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxeSmmPchHsioLib.inf
+ PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+
+ #####################################
+ # Platform Package
+ #####################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
+ PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
+ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+ PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
+ HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
+ I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+ TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
+!endif
+
+ #######################################
+ # Board-specific
+ #######################################
+ PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+
+[LibraryClasses.IA32.SEC]
+ #######################################
+ # Platform Package
+ #######################################
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+ SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+[LibraryClasses.common.PEIM]
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+!endif
+ SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+ PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
+ PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
+!endif
+ PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf
+ PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+ #######################################
+ # Board-specific
+ #######################################
+ PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
+
+!if $(TARGET) == DEBUG
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
+!else
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
+!endif
+
+[LibraryClasses.common.DXE_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf
+ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
+
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf
+ DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
+
+ #######################################
+ # Board-specific
+ #######################################
+ DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+!endif
+
+#######################################
+# PEI Components
+#######################################
+# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed
+[Components.IA32]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ UefiCpuPkg/SecCore/SecCore.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+
+ #
+ # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD.
+ # Add policy as dependency for FSP Wrapper
+ #
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+ IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+ !endif
+ NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
+ !endif
+ }
+
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+ $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+
+#######################################
+# DXE Components
+#######################################
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed
+[Components.X64]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+ MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{
+ <LibraryClasses>
+ NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf
+ }
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
+ <PcdsPatchableInModule>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
+ <LibraryClasses>
+ !if $(TARGET) == DEBUG
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ !endif
+ }
+!endif
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+ $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
+ $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+
+ $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ !if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
+ !endif
+ }
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
+ }
+
+ # Thunderbolt
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+!endif
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
new file mode 100644
index 0000000000..e2d40bcbb6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.fdf
@@ -0,0 +1,702 @@
+## @file
+# FDF file of Platform.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.CometlakeURvp]
+#
+# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
+# assigned with PCD values. Instead, it uses the definitions for its variety, which
+# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
+#
+BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the FLASH Device.
+Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = $(FLASH_BLOCK_SIZE)
+NumBlocks = $(FLASH_NUM_BLOCKS)
+
+DEFINE SIPKG_DXE_SMM_BIN = INF
+DEFINE SIPKG_PEI_BIN = INF
+
+# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
+# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
+SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdBiosSize
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted
+#
+################################################################################
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x40000
+ 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ #
+ # Be careful on CheckSum field.
+ #
+ 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
+ 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+ # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+ #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xDF, 0x01, 0x00,
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+FV = FvAdvanced
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+FV = FvSecurity
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+FV = FvOsBoot
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+FV = FvUefiBoot
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+FV = FvPostMemory
+
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+#Microcode
+FV = FvMicrocode
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+# FSP_S Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+# FSP_M Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+# FSP_T Section
+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
+FV = FvAdvancedPreMemory
+
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+FV = FvPreMemory
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.FvMicrocode]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = FALSE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin
+}
+
+[FV.FvPreMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
+
+INF UefiCpuPkg/SecCore/SecCore.inf
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
+
+[FV.FvPostMemoryUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
+
+# Init Board Config PCD
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+
+FILE RAW = C9505BC0-AA3D-4056-9995-870C8DE8594E {
+ $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
+ }
+!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
+FILE FREEFORM =PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
+ SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
+ SECTION UI = "Vbt"
+}
+FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp
+}
+!endif # PcdPeiDisplayEnable
+
+
+[FV.FvPostMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
+
+FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompact
+ }
+}
+
+[FV.FvUefiBootUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
+INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
+
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
+INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+
+INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
+
+
+[FV.FvUefiBoot]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompact
+ }
+ }
+
+[FV.FvOsBootUncompact]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
+
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+!endif
+
+[FV.FvLateSilicon]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
+
+INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
+INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
+
+!endif
+
+[FV.FvOsBoot]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
+
+FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompact
+ }
+ }
+
+FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvLateSilicon
+ }
+ }
+
+[FV.FvSecurityPreMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+
+INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+
+[FV.FvSecurityPostMemory]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif
+
+[FV.FvSecurityLate]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
+INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+!endif
+
+[FV.FvSecurity]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
+
+FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityPostMemory
+ }
+ }
+
+FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityLate
+ }
+ }
+
+#
+# Pre-memory Advanced Features
+#
+[FV.FvAdvancedPreMemory]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
+
+!include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif
+
+#
+# Post-Memory Advanced Features
+#
+[FV.FvAdvancedUncompact]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
+
+!include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+!if gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+!endif
+
+#
+# Compressed FV with Post-Memory Advanced Features
+#
+[FV.FvAdvanced]
+BlockSize = $(FLASH_BLOCK_SIZE)
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
+
+FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompact
+ }
+ }
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgBuildOption.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgBuildOption.dsc
new file mode 100644
index 0000000000..f77ca32343
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgBuildOption.dsc
@@ -0,0 +1,154 @@
+## @file
+# platform build option configuration file.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+
+ DEFINE DSC_S3_BUILD_OPTIONS =
+
+ DEFINE DSC_CSM_BUILD_OPTIONS =
+
+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
+ DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
+!else
+ DEFINE DSC_ACPI_BUILD_OPTIONS =
+!endif
+
+ DEFINE BIOS_GUARD_BUILD_OPTIONS =
+
+ DEFINE OVERCLOCKING_BUILD_OPTION =
+
+ DEFINE FSP_BINARY_BUILD_OPTIONS =
+
+ DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG
+
+ DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
+
+ DEFINE RESTRICTED_OPTION =
+
+
+ DEFINE SV_BUILD_OPTIONS =
+
+ DEFINE TEST_MENU_BUILD_OPTION =
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
+!else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+ DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
+
+
+ DEFINE TPM_BUILD_OPTION =
+
+ DEFINE TPM2_BUILD_OPTION =
+
+ DEFINE DSC_TBT_BUILD_OPTIONS =
+
+ DEFINE DSC_DCTT_BUILD_OPTIONS =
+
+ DEFINE EMB_BUILD_OPTIONS =
+
+ DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
+
+ DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
+
+ DEFINE BOOT_GUARD_BUILD_OPTIONS =
+
+ DEFINE SECURE_BOOT_BUILD_OPTIONS =
+
+ DEFINE USBTYPEC_BUILD_OPTION =
+
+ DEFINE CAPSULE_BUILD_OPTIONS =
+
+ DEFINE PERFORMANCE_BUILD_OPTION =
+
+ DEFINE DEBUGUSEUSB_BUILD_OPTION =
+
+ DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION = -DDISABLE_NEW_DEPRECATED_INTERFACES=1
+
+ DEFINE SINITBIN_BUILD_OPTION =
+
+ DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
+
+ DEFINE CPUTYPE_BUILD_OPTION = -DCPU_CFL=1
+
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(CPUTYPE_BUILD_OPTION)
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_NASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+#
+# For X64 Specific Build Flag
+#
+GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection
+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection
+[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION]
+ #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+ #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
new file mode 100644
index 0000000000..1ccdb28f12
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -0,0 +1,404 @@
+## @file
+# PCD configuration build description file for the CometlakeURvp board.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all PCD Entries used by this board.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
+ #
+ # Please select the Boot Stage here.
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+ #
+ # 0: FSP Wrapper is running in Dispatch mode.
+ # 1: FSP Wrapper is running in API mode.
+ # Note: Dispatch mode is currently NOT supported for this board.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+
+ #
+ # FALSE: The board is not a FSP wrapper (FSP binary not used)
+ # TRUE: The board is a FSP wrapper (FSP binary is used)
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+
+ #
+ # When sharing stack with boot loader, FSP only needs a small temp ram for heap
+ #
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000
+
+ #
+ # Boot loader stack size has to be large enough for FSP execution
+ #
+ gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ #
+ # PCIe Reserved Memory Space Range
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0xA0000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF
+[PcdsFeatureFlag.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(TARGET) == RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ # Build switches
+ gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
+
+ # CPU
+ gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
+
+ # SA
+ gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
+
+ # ME
+ gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
+
+ # Others
+ gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+!if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+!endif
+
+ ######################################
+ # Board Configuration
+ ######################################
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+!if $(TARGET) == DEBUG
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+
+ # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+ #
+ # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
+ # (They will be DynamicEx in FSP Dispatch mode)
+ #
+
+ ## Specifies the size of the microcode Region.
+ # @Prompt Microcode Region size.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
+
+ ## Specifies the AP wait loop state during POST phase.
+ # The value is defined as below.
+ # 1: Place AP in the Hlt-Loop state.
+ # 2: Place AP in the Mwait-Loop state.
+ # 3: Place AP in the Run-Loop state.
+ # @Prompt The AP wait loop state.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
+
+ #
+ # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
+ #
+ # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
+ # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
+ # that lie entirely within the expected fixed memory regions.
+ # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
+ # BIT3-31: Reserved
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+!if $(TARGET) == RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
+!if $(TARGET) == RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+!endif
+
+ ######################################
+ # Board Configuration
+ ######################################
+ gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, 0x1F, 0x00}
+
+[PcdsFixedAtBuild.IA32]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+ gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
+
+[PcdsFixedAtBuild.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+
+ # Default platform supported RFC 4646 languages: (American) English
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
+
+[PcdsPatchableInModule.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+!if $(TARGET) == DEBUG
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
+!endif
+
+[PcdsDynamicDefault]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
+ #
+ # Set video to native resolution as Windows 8 WHCK requirement.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
+
+ # Platform will pre-allocate UPD buffer and pass it to FspWrapper
+ # Those dummy address will be patched before FspWrapper executing
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
+
+ ######################################
+ # Board Configuration
+ ######################################
+
+ # Thunderbolt Configuration
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
+
+[PcdsDynamicHii.X64.DEFAULT]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+!endif
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
new file mode 100644
index 0000000000..1e01ae7ea7
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
@@ -0,0 +1,34 @@
+# @ build_config.cfg
+# This is the CometlakeURvp board specific build settings
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN =
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = CometlakeOpenBoardPkg
+PROJECT = CometlakeOpenBoardPkg/CometlakeURvp
+BOARD = CometlakeURvp
+FLASH_MAP_FDF = CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/FlashMapInclude.fdf
+PROJECT_DSC = CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
+BOARD_PKG_PCD_DSC = CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS =
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = CometLakeFspBinPkg/CometLake1
+FSP_PKG_NAME = CoffeelakeSiliconPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = A842B2D2-5C88-44E9-A9E2-4830F26662B7
--
2.16.2.windows.1


[edk2-platforms] [PATCH v2 5/7] CometlakeOpenBoardPkg: Add modules

Kathappan Esakkithevar
 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Modules shared across board instances.

* BoardAcpiDxe - Performs DXE board ACPI initialization.
* PciHotPlug - Performs PCI-e resource configuration.
* PeiTbtInit - Initializes Thunderbolt policy in PEI.
* PolicyInitDxe - Initializes policy in DXE.
* TbtDxe - Performs Thunderbolt initialization in DXE.
* TbtSmm - Performs Thunderbolt initialization in SMM.
* BiosInfo - Provides the BIOS informations in PEI.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
.../Acpi/BoardAcpiDxe/AcpiGnvsInit.c | 96 +
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 290 +++
.../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 73 +
.../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 20 +
.../Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL | 37 +
.../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 516 ++++++
.../Acpi/BoardAcpiDxe/Dsdt/PciTree.asl | 309 ++++
.../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 76 +
.../CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 93 +
.../CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf | 49 +
.../Features/PciHotPlug/PciHotPlug.c | 353 ++++
.../Features/PciHotPlug/PciHotPlug.h | 130 ++
.../Features/PciHotPlug/PciHotPlug.inf | 63 +
.../Features/Tbt/AcpiTables/Rtd3PcieTbt.asl | 405 +++++
.../Features/Tbt/AcpiTables/Tbt.asl | 1877 ++++++++++++++++++++
.../Features/Tbt/TbtInit/Dxe/TbtDxe.c | 228 +++
.../Features/Tbt/TbtInit/Dxe/TbtDxe.inf | 51 +
.../Features/Tbt/TbtInit/Pei/PeiTbtInit.c | 211 +++
.../Features/Tbt/TbtInit/Pei/PeiTbtInit.inf | 47 +
.../Features/Tbt/TbtInit/Smm/TbtSmiHandler.c | 1609 +++++++++++++++++
.../Features/Tbt/TbtInit/Smm/TbtSmiHandler.h | 180 ++
.../Features/Tbt/TbtInit/Smm/TbtSmm.c | 1765 ++++++++++++++++++
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 80 +
.../Policy/PolicyInitDxe/BoardInitLib.c | 608 +++++++
.../Policy/PolicyInitDxe/BoardInitLib.h | 32 +
.../Policy/PolicyInitDxe/CpuPolicyInitDxe.c | 46 +
.../Policy/PolicyInitDxe/CpuPolicyInitDxe.h | 38 +
.../Policy/PolicyInitDxe/GopPolicyInitDxe.c | 174 ++
.../Policy/PolicyInitDxe/GopPolicyInitDxe.h | 41 +
.../Policy/PolicyInitDxe/PchPolicyInitDxe.c | 55 +
.../Policy/PolicyInitDxe/PchPolicyInitDxe.h | 52 +
.../Policy/PolicyInitDxe/PolicyInitDxe.c | 88 +
.../Policy/PolicyInitDxe/PolicyInitDxe.h | 45 +
.../Policy/PolicyInitDxe/PolicyInitDxe.inf | 176 ++
.../Policy/PolicyInitDxe/SaPolicyInitDxe.c | 60 +
.../Policy/PolicyInitDxe/SaPolicyInitDxe.h | 56 +
.../Policy/PolicyInitDxe/SiliconPolicyInitDxe.c | 46 +
.../Policy/PolicyInitDxe/SiliconPolicyInitDxe.h | 37 +
38 files changed, 10112 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3PcieTbt.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.h

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
new file mode 100644
index 0000000000..452b300690
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c
@@ -0,0 +1,96 @@
+/** @file
+ Acpi Gnvs Init Library.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <PchAccess.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/MpService.h>
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+ UINTN NumberOfCPUs;
+ UINTN NumberOfEnabledCPUs;
+
+ Pages = EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA));
+ Address = 0xffffffff; // allocate address below 4G.
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Determine the number of processors
+ //
+ MpService->GetNumberOfProcessors (
+ MpService,
+ &NumberOfCPUs,
+ &NumberOfEnabledCPUs
+ );
+
+ *GlobalNvs = (VOID *) (UINTN) Address;
+ SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0);
+
+ //
+ // GNVS default value init here...
+ //
+ GNVS = (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address;
+
+ GNVS->Area->ThreadCount = (UINT8)NumberOfEnabledCPUs;
+
+ //
+ // Miscellaneous
+ //
+ GNVS->Area->PL1LimitCS = 0;
+ GNVS->Area->PL1LimitCSValue = 4500;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
new file mode 100644
index 0000000000..7fc71bca64
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
@@ -0,0 +1,290 @@
+/** @file
+ ACPI Platform Driver
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] GlobalNvs - Pointer of Global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **GlobalNvs
+ );
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of the protocol.
+ @param[in] Type TRUE if the desired protocol is a FV protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiBoard (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area);
+
+ //
+ // This PCD set must be done before PublishAcpiTablesFromFv.
+ // The PCD data will be used there.
+ //
+ PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area);
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+
+ //
+ // This protocol publish must be done after PublishAcpiTablesFromFv.
+ // The NVS data is be updated there.
+ //
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiGlobalNvsAreaProtocolGuid,
+ &mGlobalNvsArea,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
new file mode 100644
index 0000000000..09b67376fb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
@@ -0,0 +1,73 @@
+## @file
+# Component information file for AcpiPlatform module
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BoardAcpiDxe
+ FILE_GUID = E269E77D-6163-4F5D-8E59-21EAF114D307
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiBoard
+
+[Sources.common]
+ BoardAcpiDxe.c
+ AcpiGnvsInit.c
+ Dsdt/DSDT.ASL
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ HobLib
+ AslUpdateLib
+ BoardAcpiTableLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiGlobalNvsAreaProtocolGuid
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
new file mode 100644
index 0000000000..db9d0f7062
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
@@ -0,0 +1,20 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
new file mode 100644
index 0000000000..e2482489a3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL
@@ -0,0 +1,37 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformBoardId.h"
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL", // OEM ID (6 byte string)
+ "CML ",// OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ // Miscellaneous services enabled in Project
+ Include ("AMLUPD.asl")
+ Include ("PciTree.asl")
+ Include ("Platform.asl")
+
+ Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state
+ if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})}
+ if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})}
+ if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})}
+ Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state
+
+}// End of ASL File
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
new file mode 100644
index 0000000000..1fc89728c1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
@@ -0,0 +1,516 @@
+/** @file
+ This file contains the SystemAgent PCI Configuration space
+ definition.
+ It defines various System Agent PCI Configuration Space registers
+ which will be used to dynamically produce all resources in the Host Bus.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Define various System Agent (SA) PCI Configuration Space
+// registers which will be used to dynamically produce all
+// resources in the Host Bus _CRS.
+//
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+ Offset(0x40), // EPBAR (0:0:0:40)
+ EPEN, 1, // Enable
+ , 11,
+ EPBR, 20, // EPBAR [31:12]
+
+ Offset(0x48), // MCHBAR (0:0:0:48)
+ MHEN, 1, // Enable
+ , 14,
+ MHBR, 17, // MCHBAR [31:15]
+
+ Offset(0x50), // GGC (0:0:0:50)
+ GCLK, 1, // GGCLCK
+
+ Offset(0x54), // DEVEN (0:0:0:54)
+ D0EN, 1, // DEV0 Enable
+ D1F2, 1, // DEV1 FUN2 Enable
+ D1F1, 1, // DEV1 FUN1 Enable
+ D1F0, 1, // DEV1 FUN0 Enable
+
+ Offset(0x60), // PCIEXBAR (0:0:0:60)
+ PXEN, 1, // Enable
+ PXSZ, 2, // PCI Express Size
+ , 23,
+ PXBR, 6, // PCI Express BAR [31:26]
+
+ Offset(0x68), // DMIBAR (0:0:0:68)
+ DIEN, 1, // Enable
+ , 11,
+ DIBR, 20, // DMIBAR [31:12]
+
+ Offset(0x70), // MESEG_BASE (0:0:0:70)
+ , 20,
+ MEBR, 12, // MESEG_BASE [31:20]
+
+ Offset(0x80), // PAM0 Register (0:0:0:80)
+ PMLK, 1, // PAM Lock bit.
+ , 3,
+ PM0H, 2, // PAM 0, High Nibble
+ , 2,
+
+ Offset(0x81), // PAM1 Register (0:0:0:81)
+ PM1L, 2, // PAM1, Low Nibble
+ , 2,
+ PM1H, 2, // PAM1, High Nibble
+ , 2,
+
+ Offset(0x82), // PAM2 Register (0:0:0:82)
+ PM2L, 2, // PAM2, Low Nibble
+ , 2,
+ PM2H, 2, // PAM2, High Nibble
+ , 2,
+
+ Offset(0x83), // PAM3 Register (0:0:0:83)
+ PM3L, 2, // PAM3, Low Nibble
+ , 2,
+ PM3H, 2, // PAM3, High Nibble
+ , 2,
+
+ Offset(0x84), // PAM4 Register (0:0:0:84)
+ PM4L, 2, // PAM4, Low Nibble
+ , 2,
+ PM4H, 2, // PAM4, High Nibble
+ , 2,
+
+ Offset(0x85), // PAM5 Register (0:0:0:85)
+ PM5L, 2, // PAM5, Low Nibble
+ , 2,
+ PM5H, 2, // PAM5, High Nibble
+ , 2,
+
+ Offset(0x86), // PAM6 Register (0:0:0:86)
+ PM6L, 2, // PAM6, Low Nibble
+ , 2,
+ PM6H, 2, // PAM6, High Nibble
+ , 2,
+
+ Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
+ , 20,
+ TUUD, 19, // TOUUD [38:20]
+
+ Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
+ , 20,
+ TLUD, 12, // TOLUD [31:20]
+
+ Offset(0xC8), // ERRSTS register (0:0:0:C8)
+ , 7,
+ HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
+}
+
+//
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus. This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+//
+Name(BUF0,ResourceTemplate()
+{
+ //
+ // Bus Number Allocation: Bus 0 to 0xFF
+ //
+ WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+ 0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+ //
+ // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+ //
+ // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+ //
+ // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+ //
+ // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+ //
+ // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+ //
+ // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+ //
+ // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+ //
+ // BIOS Area ( 0xF0000 - 0xFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+// //
+// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+// //
+// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+ //
+ // PCI Memory Region ( TOLUD - 0xDFFFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01)
+
+ //
+ // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
+ // (This is dummy range for OS compatibility, will patch it in _CRS)
+ //
+ QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
+
+ //
+ // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03)
+})
+
+Name(EP_B, 0) // to store EP BAR
+Name(MH_B, 0) // to store MCH BAR
+Name(PC_B, 0) // to store PCIe BAR
+Name(PC_L, 0) // to store PCIe BAR Length
+Name(DM_B, 0) // to store DMI BAR
+
+//
+// Get EP BAR
+//
+Method(GEPB,0,Serialized)
+{
+ if(LEqual(EP_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.EPBR,12,EP_B)
+ }
+ Return(EP_B)
+}
+
+//
+// Get MCH BAR
+//
+Method(GMHB,0,Serialized)
+{
+ if(LEqual(MH_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.MHBR,15,MH_B)
+ }
+ Return(MH_B)
+}
+
+//
+// Get PCIe BAR
+//
+Method(GPCB,0,Serialized)
+{
+ if(LEqual(PC_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.PXBR,26,PC_B)
+ }
+ Return(PC_B)
+}
+
+//
+// Get PCIe Length
+//
+Method(GPCL,0,Serialized)
+{
+ if(LEqual(PC_L,0)) {
+ ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L)
+ }
+ Return(PC_L)
+}
+
+//
+// Get DMI BAR
+//
+Method(GDMB,0,Serialized)
+{
+ if(LEqual(DM_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.DIBR,12,DM_B)
+ }
+ Return(DM_B)
+}
+
+
+Method(_CRS,0,Serialized)
+{
+ //
+ // Fix up Max Bus Number and Length
+ //
+ Store(\_SB.PCI0.GPCL(),Local0)
+ CreateWordField(BUF0, ^PB00._MAX, PBMX)
+ Store(Subtract(ShiftRight(Local0,20),2), PBMX)
+ CreateWordField(BUF0, ^PB00._LEN, PBLN)
+ Store(Subtract(ShiftRight(Local0,20),1), PBLN)
+ //
+ // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
+ //
+ If(PM1L) // \_SB.PCI0
+ {
+ // PAMx != 0. Set length = 0.
+
+ CreateDwordField(BUF0, ^C000._LEN,C0LN)
+ Store(Zero,C0LN)
+ }
+
+ If(LEqual(PM1L,1))
+ {
+ CreateBitField(BUF0, ^C000._RW,C0RW)
+ Store(Zero,C0RW)
+ }
+
+ If(PM1H)
+ {
+ CreateDwordField(BUF0, ^C400._LEN,C4LN)
+ Store(Zero,C4LN)
+ }
+
+ If(LEqual(PM1H,1))
+ {
+ CreateBitField(BUF0, ^C400._RW,C4RW)
+ Store(Zero,C4RW)
+ }
+
+ If(PM2L)
+ {
+ CreateDwordField(BUF0, ^C800._LEN,C8LN)
+ Store(Zero,C8LN)
+ }
+
+ If(LEqual(PM2L,1))
+ {
+ CreateBitField(BUF0, ^C800._RW,C8RW)
+ Store(Zero,C8RW)
+ }
+
+ If(PM2H)
+ {
+ CreateDwordField(BUF0, ^CC00._LEN,CCLN)
+ Store(Zero,CCLN)
+ }
+
+ If(LEqual(PM2H,1))
+ {
+ CreateBitField(BUF0, ^CC00._RW,CCRW)
+ Store(Zero,CCRW)
+ }
+
+ If(PM3L)
+ {
+ CreateDwordField(BUF0, ^D000._LEN,D0LN)
+ Store(Zero,D0LN)
+ }
+
+ If(LEqual(PM3L,1))
+ {
+ CreateBitField(BUF0, ^D000._RW,D0RW)
+ Store(Zero,D0RW)
+ }
+
+ If(PM3H)
+ {
+ CreateDwordField(BUF0, ^D400._LEN,D4LN)
+ Store(Zero,D4LN)
+ }
+
+ If(LEqual(PM3H,1))
+ {
+ CreateBitField(BUF0, ^D400._RW,D4RW)
+ Store(Zero,D4RW)
+ }
+
+ If(PM4L)
+ {
+ CreateDwordField(BUF0, ^D800._LEN,D8LN)
+ Store(Zero,D8LN)
+ }
+
+ If(LEqual(PM4L,1))
+ {
+ CreateBitField(BUF0, ^D800._RW,D8RW)
+ Store(Zero,D8RW)
+ }
+
+ If(PM4H)
+ {
+ CreateDwordField(BUF0, ^DC00._LEN,DCLN)
+ Store(Zero,DCLN)
+ }
+
+ If(LEqual(PM4H,1))
+ {
+ CreateBitField(BUF0, ^DC00._RW,DCRW)
+ Store(Zero,DCRW)
+ }
+
+ If(PM5L)
+ {
+ CreateDwordField(BUF0, ^E000._LEN,E0LN)
+ Store(Zero,E0LN)
+ }
+
+ If(LEqual(PM5L,1))
+ {
+ CreateBitField(BUF0, ^E000._RW,E0RW)
+ Store(Zero,E0RW)
+ }
+
+ If(PM5H)
+ {
+ CreateDwordField(BUF0, ^E400._LEN,E4LN)
+ Store(Zero,E4LN)
+ }
+
+ If(LEqual(PM5H,1))
+ {
+ CreateBitField(BUF0, ^E400._RW,E4RW)
+ Store(Zero,E4RW)
+ }
+
+ If(PM6L)
+ {
+ CreateDwordField(BUF0, ^E800._LEN,E8LN)
+ Store(Zero,E8LN)
+ }
+
+ If(LEqual(PM6L,1))
+ {
+ CreateBitField(BUF0, ^E800._RW,E8RW)
+ Store(Zero,E8RW)
+ }
+
+ If(PM6H)
+ {
+ CreateDwordField(BUF0, ^EC00._LEN,ECLN)
+ Store(Zero,ECLN)
+ }
+
+ If(LEqual(PM6H,1))
+ {
+ CreateBitField(BUF0, ^EC00._RW,ECRW)
+ Store(Zero,ECRW)
+ }
+
+ If(PM0H)
+ {
+ CreateDwordField(BUF0, ^F000._LEN,F0LN)
+ Store(Zero,F0LN)
+ }
+
+ If(LEqual(PM0H,1))
+ {
+ CreateBitField(BUF0, ^F000._RW,F0RW)
+ Store(Zero,F0RW)
+ }
+
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Add (Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase)), 1, M1LN)
+ Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+ Store (FixedPcdGet32(PcdPciReservedMemLimit), M1MX)
+
+ //
+ // Create pointers to Memory Sizing values.
+ // Patch PM02 range basing on memory size and OS type
+ //
+ CreateQwordField(BUF0, ^PM02._LEN,MSLN)
+ //
+ // Set resource length to 0
+ //
+ Store (0, MSLN)
+
+ D8XH (0, 0xC5)
+ D8XH (1, 0xAA)
+
+ Return(BUF0)
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
new file mode 100644
index 0000000000..111f120d89
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl
@@ -0,0 +1,309 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Scope(\_SB) {
+ Name(PD00, Package(){
+// If the setting changed in PCH PxRcConfig policy, platform should also update static assignment here.
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, 0, 11 },
+ Package(){0x001FFFFF, 1, 0, 10 },
+ Package(){0x001FFFFF, 2, 0, 11 },
+ Package(){0x001FFFFF, 3, 0, 11 },
+// D30: SerialIo and SCS - can't use PIC
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, 0, 11 },
+ Package(){0x001DFFFF, 1, 0, 10 },
+ Package(){0x001DFFFF, 2, 0, 11 },
+ Package(){0x001DFFFF, 3, 0, 11 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, 0, 11 },
+ Package(){0x001CFFFF, 1, 0, 10 },
+ Package(){0x001CFFFF, 2, 0, 11 },
+ Package(){0x001CFFFF, 3, 0, 11 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, 0, 11 },
+ Package(){0x001BFFFF, 1, 0, 10 },
+ Package(){0x001BFFFF, 2, 0, 11 },
+ Package(){0x001BFFFF, 3, 0, 11 },
+// D25: SerialIo - can't use PIC
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, 0, 11 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, 0, 11 },
+ Package(){0x0016FFFF, 1, 0, 10 },
+ Package(){0x0016FFFF, 2, 0, 11 },
+ Package(){0x0016FFFF, 3, 0, 11 },
+// D21: SerialIo - can't use PIC
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+// D20: xHCI, OTG, CNVi WiFi, SDcard
+ Package(){0x0014FFFF, 0, 0, 11 },
+ Package(){0x0014FFFF, 1, 0, 10 },
+ Package(){0x0014FFFF, 2, 0, 11 },
+ Package(){0x0014FFFF, 3, 0, 11 },
+// D19: Integrated Sensor Hub - can't use PIC
+// D18: Thermal, UFS, SerialIo SPI2 - can't use PIC
+ Package(){0x0012FFFF, 0, 0, 11 },
+ Package(){0x0012FFFF, 1, 0, 10 },
+ Package(){0x0012FFFF, 2, 0, 11 },
+ Package(){0x0012FFFF, 3, 0, 11 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, 0, 11 },
+ Package(){0x0001FFFF, 1, 0, 10 },
+ Package(){0x0001FFFF, 2, 0, 11 },
+ Package(){0x0001FFFF, 3, 0, 11 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, 0, 11 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, 0, 11 },
+// SA IPU Device
+ Package(){0x0005FFFF, 0, 0, 11 },
+// SA GNA Device
+ Package(){0x0008FFFF, 0, 0, 11 },
+ })
+ Name(AR00, Package(){
+// PCI Bridge
+// D31: cAVS, SMBus, GbE, Nothpeak
+ Package(){0x001FFFFF, 0, 0, 16 },
+ Package(){0x001FFFFF, 1, 0, 17 },
+ Package(){0x001FFFFF, 2, 0, 18 },
+ Package(){0x001FFFFF, 3, 0, 19 },
+// D30: SerialIo and SCS
+ Package(){0x001EFFFF, 0, 0, 20 },
+ Package(){0x001EFFFF, 1, 0, 21 },
+ Package(){0x001EFFFF, 2, 0, 22 },
+ Package(){0x001EFFFF, 3, 0, 23 },
+// D29: PCI Express Port 9-16
+ Package(){0x001DFFFF, 0, 0, 16 },
+ Package(){0x001DFFFF, 1, 0, 17 },
+ Package(){0x001DFFFF, 2, 0, 18 },
+ Package(){0x001DFFFF, 3, 0, 19 },
+// D28: PCI Express Port 1-8
+ Package(){0x001CFFFF, 0, 0, 16 },
+ Package(){0x001CFFFF, 1, 0, 17 },
+ Package(){0x001CFFFF, 2, 0, 18 },
+ Package(){0x001CFFFF, 3, 0, 19 },
+// D27: PCI Express Port 17-20
+ Package(){0x001BFFFF, 0, 0, 16 },
+ Package(){0x001BFFFF, 1, 0, 17 },
+ Package(){0x001BFFFF, 2, 0, 18 },
+ Package(){0x001BFFFF, 3, 0, 19 },
+// D26: eMMC
+ Package(){0x001AFFFF, 0, 0, 16 },
+ Package(){0x001AFFFF, 1, 0, 17 },
+ Package(){0x001AFFFF, 2, 0, 18 },
+ Package(){0x001AFFFF, 3, 0, 19 },
+// D25: SerialIo
+ Package(){0x0019FFFF, 0, 0, 32 },
+ Package(){0x0019FFFF, 1, 0, 33 },
+ Package(){0x0019FFFF, 2, 0, 34 },
+// D23: SATA controller
+ Package(){0x0017FFFF, 0, 0, 16 },
+// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
+ Package(){0x0016FFFF, 0, 0, 16 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+ Package(){0x0016FFFF, 2, 0, 18 },
+ Package(){0x0016FFFF, 3, 0, 19 },
+// D21: SerialIo
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
+// D20: xHCI, OTG, CNVi WiFi, SDcard
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+// D19: Integrated Sensor Hub
+ Package(){0x0013FFFF, 0, 0, 20 },
+// D18: Thermal, UFS, SerialIo SPI 2
+ Package(){0x0012FFFF, 0, 0, 16 },
+ Package(){0x0012FFFF, 1, 0, 24 },
+ Package(){0x0012FFFF, 2, 0, 18 },
+ Package(){0x0012FFFF, 3, 0, 19 },
+
+// Host Bridge
+// P.E.G. Root Port D1F0
+ Package(){0x0001FFFF, 0, 0, 16 },
+ Package(){0x0001FFFF, 1, 0, 17 },
+ Package(){0x0001FFFF, 2, 0, 18 },
+ Package(){0x0001FFFF, 3, 0, 19 },
+// P.E.G. Root Port D1F1
+// P.E.G. Root Port D1F2
+// SA IGFX Device
+ Package(){0x0002FFFF, 0, 0, 16 },
+// SA Thermal Device
+ Package(){0x0004FFFF, 0, 0, 16 },
+// SA IPU Device
+ Package(){0x0005FFFF, 0, 0, 16 },
+// SA GNA Device
+ Package(){0x0008FFFF, 0, 0, 16 },
+ })
+ Name(PD04, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR04, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD05, Package(){
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR05, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD06, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR06, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PD07, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 10 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR07, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PD08, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR08, Package(){
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD09, Package(){
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR09, Package(){
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD0E, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR0E, Package(){
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+ Name(PD0F, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 10 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR0F, Package(){
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+ Name(PD02, Package(){
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 10 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR02, Package(){
+// P.E.G. Port Slot x16
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+ Name(PD0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, 0, 10 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 11 },
+ })
+ Name(AR0A, Package(){
+// P.E.G. Port Slot x8
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+ Name(PD0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, 0, 11 },
+ Package(){0x0000FFFF, 1, 0, 11 },
+ Package(){0x0000FFFF, 2, 0, 11 },
+ Package(){0x0000FFFF, 3, 0, 10 },
+ })
+ Name(AR0B, Package(){
+// P.E.G. Port Slot x4
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+ Name(_SEG, 0)
+ Name(_ADR, 0x00000000)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Method(_PRT,0) {
+ If(PICM) {Return(AR00)} // APIC mode
+ Return (PD00) // PIC Mode
+ } // end _PRT
+
+ Include("HostBus.asl")
+ } // end PCI0 Bridge "Host Bridge"
+} // end _SB scope
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
new file mode 100644
index 0000000000..ad3e560b0d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
@@ -0,0 +1,76 @@
+/** @file
+ ACPI DSDT table
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+// Define Port 80 as an ACPI Operating Region to use for debugging. Please
+// note that the Intel CRBs have the ability to ouput a Word to
+// Port 80h for debugging purposes, so the model implemented here may not be
+// able to be used on OEM Designs.
+
+OperationRegion(PRT0,SystemIO,0x80,2)
+Field(PRT0,WordAcc,Lock,Preserve)
+{
+ P80B, 16
+}
+
+// Port 80h Update:
+// Update 2 bytes of Port 80h.
+//
+// Arguments:
+// Arg0: 0 = Write Port 80h
+// 1 = Write Port 81h
+// Arg1: 8-bit Value to write
+//
+// Return Value:
+// None
+
+Name(P80T, 0) // temp buffer for P80
+
+Method(D8XH,2,Serialized)
+{
+ If(LEqual(Arg0,0)) // Write Port 80h
+ {
+ Store(Or(And(P80T,0xFF00),Arg1),P80T)
+ }
+ If(LEqual(Arg0,1)) // Write Port 81h
+ {
+ Store(Or(And(P80T,0x00FF),ShiftLeft(Arg1,8)),P80T)
+ }
+ Store(P80T,P80B)
+}
+
+//
+// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
+//
+OperationRegion(SPRT,SystemIO, 0xB2,2)
+Field (SPRT, ByteAcc, Lock, Preserve) {
+ SSMP, 8
+}
+
+// The _PIC Control Method is optional for ACPI design. It allows the
+// OS to inform the ASL code which interrupt controller is being used,
+// the 8259 or APIC. The reference code in this document will address
+// PCI IRQ Routing and resource allocation for both cases.
+//
+// The values passed into _PIC are:
+// 0 = 8259
+// 1 = IOAPIC
+
+Method(\_PIC,1)
+{
+ Store(Arg0,PICM)
+}
+
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+ Name(PICM, 0)
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..c49dd4ed32
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,93 @@
+/** @file
+ Driver for BIOS Info support.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+
+#define INDEXPORT_TO_ADDRESS(x) (x)
+#define DATAPORT_TO_ADDRESS(x) ((x) << 16)
+#define PORTWIDTH_TO_ADDRESS(x) ((x) << 32)
+#define PORTBITNUMBER_TO_ADDRESS(x) ((x) << 40)
+#define PORTINDEXNUMBER_TO_ADDRESS(x) ((x) << 48)
+
+//
+// Internal
+//
+#pragma pack (1)
+
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[1];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ 1,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi and builds BiosInfo HOB .
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi and HOB successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..9208aeda5d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,49 @@
+### @file
+# Module Information description file for BIOS Info Driver
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = A842B2D2-5C88-44E9-A9E2-4830F26662B7
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ HobLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometLakeFspBinPkg/CometLake1/CometLakeFspBinPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
new file mode 100644
index 0000000000..7124c1496d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
@@ -0,0 +1,353 @@
+/** @file
+ Pci Hotplug Driver : This file will perform specific PCI-EXPRESS
+ Devics resource configuration.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include "PciHotPlug.h"
+#include <Ppi/SiPolicy.h>
+#include <TbtBoardInfo.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/TbtCommonLib.h>
+
+#define PCIE_NUM (20)
+#define PEG_NUM (3)
+#define PADDING_BUS (1)
+#define PADDING_NONPREFETCH_MEM (1)
+#define PADDING_PREFETCH_MEM (1)
+#define PADDING_IO (1)
+#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFETCH_MEM + PADDING_IO)
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE_NUM + PEG_NUM];
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevicePathTemplate = {
+ ACPI,
+ PCI(0xFF, 0xFF), // Dummy Device no & Function no
+ END
+};
+
+/**
+ Entry point for the driver.
+
+ This routine reads the PlatformType GPI on FWH and produces a protocol
+ to be consumed by the chipset driver to effect those settings.
+
+ @param[in] ImageHandle An image handle.
+ @param[in] SystemTable A pointer to the system table.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+PciHotPlug (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ PCI_HOT_PLUG_INSTANCE *PciHotPlug;
+ UINTN Index;
+ UINTN RpDev;
+ UINTN RpFunc;
+ PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
+ UINT32 PcieRootPortHpeData = 0;
+
+ DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));
+
+ PcieRootPortHpeData = PcdGet32 (PcdPchPcieRootPortHpe);
+ //
+ // PCH Rootports Hotplug device path creation
+ //
+ for (Index = 0; Index < PCIE_NUM; Index++) {
+ if (((PcieRootPortHpeData >> Index) & BIT0) == BIT0) { // Check the Rootport no's hotplug is set
+ Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the actual device/function no corresponding to the Rootport no provided
+ ASSERT_EFI_ERROR (Status);
+
+ HotplugPcieDevicePath = NULL;
+ HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
+ ASSERT (HotplugPcieDevicePath != NULL);
+ if (HotplugPcieDevicePath == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
+ HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
+ HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
+
+ mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
+ mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
+ mHpcCount++;
+
+ DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
+ }
+ }
+
+
+ PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
+ ASSERT (PciHotPlug != NULL);
+ if (PciHotPlug == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Initialize driver private data.
+ //
+ ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
+
+ PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
+ PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
+ PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
+ PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding;
+
+ Status = gBS->InstallProtocolInterface (
+ &PciHotPlug->Handle,
+ &gEfiPciHotPlugInitProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &PciHotPlug->HotPlugInitProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This procedure returns a list of Root Hot Plug controllers that require
+ initialization during boot process
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+ @param[out] HpcCount The number of Root HPCs returned.
+ @param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetRootHpcList (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ OUT UINTN *HpcCount,
+ OUT EFI_HPC_LOCATION **HpcList
+ )
+{
+ *HpcCount = mHpcCount;
+ *HpcList = mPcieLocation;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This procedure Initializes one Root Hot Plug Controller
+ This process may casue initialization of its subordinate buses
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+ @param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
+ @param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
+ @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRootHpc (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ IN UINT64 HpcPciAddress,
+ IN EFI_EVENT Event, OPTIONAL
+ OUT EFI_HPC_STATE *HpcState
+ )
+{
+ if (Event) {
+ gBS->SignalEvent (Event);
+ }
+
+ *HpcState = EFI_HPC_STATE_INITIALIZED;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
+ @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
+ @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
+ @param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
+ @param[out] Attribute Describes how padding is accounted for.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetResourcePadding (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
+ IN UINT64 HpcPciAddress,
+ OUT EFI_HPC_STATE *HpcState,
+ OUT VOID **Padding,
+ OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
+ EFI_STATUS Status;
+ UINT8 RsvdExtraBusNum = 0;
+ UINT16 RsvdPcieMegaMem = 10;
+ UINT8 PcieMemAddrRngMax = 0;
+ UINT16 RsvdPciePMegaMem = 10;
+ UINT8 PciePMemAddrRngMax = 0;
+ UINT8 RsvdTbtExtraBusNum = 0;
+ UINT16 RsvdTbtPcieMegaMem = 10;
+ UINT8 TbtPcieMemAddrRngMax = 0;
+ UINT16 RsvdTbtPciePMegaMem = 10;
+ UINT8 TbtPciePMemAddrRngMax = 0;
+ UINT8 RsvdPcieKiloIo = 4;
+ BOOLEAN SetResourceforTbt = FALSE;
+ UINTN RpIndex;
+ UINTN RpDev;
+ UINTN RpFunc;
+
+DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));
+
+ PaddingResource = AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ ASSERT (PaddingResource != NULL);
+ if (PaddingResource == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ *Padding = (VOID *) PaddingResource;
+
+ RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
+ RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
+
+ // Get the actual Rootport no corresponding to the device/function no provided
+ if (RpDev == SA_PEG_DEV_NUM) {
+ // PEG
+ RpIndex = PCIE_NUM + RpFunc;
+ DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc));
+ } else {
+ // PCH
+ Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
+ DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
+ }
+
+ GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPcieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRngMax, &SetResourceforTbt);
+ if (SetResourceforTbt) {
+ RsvdExtraBusNum = RsvdTbtExtraBusNum;
+ RsvdPcieMegaMem = RsvdTbtPcieMegaMem;
+ PcieMemAddrRngMax = TbtPcieMemAddrRngMax;
+ RsvdPciePMegaMem = RsvdTbtPciePMegaMem;
+ PciePMemAddrRngMax = TbtPciePMemAddrRngMax;
+ }
+
+ //
+ // Padding for bus
+ //
+ ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
+ *Attributes = EfiPaddingPciBus;
+
+ PaddingResource->Desc = 0x8A;
+ PaddingResource->Len = 0x2B;
+ PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
+ PaddingResource->GenFlag = 0x0;
+ PaddingResource->SpecificFlag = 0;
+ PaddingResource->AddrRangeMin = 0;
+ PaddingResource->AddrRangeMax = 0;
+ PaddingResource->AddrLen = RsvdExtraBusNum;
+
+ //
+ // Padding for non-prefetchable memory
+ //
+ PaddingResource++;
+ PaddingResource->Desc = 0x8A;
+ PaddingResource->Len = 0x2B;
+ PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ PaddingResource->GenFlag = 0x0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrSpaceGranularity = 32;
+ } else {
+ PaddingResource->AddrSpaceGranularity = 32;
+ }
+ PaddingResource->SpecificFlag = 0;
+ //
+ // Pad non-prefetchable
+ //
+ PaddingResource->AddrRangeMin = 0;
+ PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
+ } else {
+ PaddingResource->AddrRangeMax = 1;
+ }
+
+ //
+ // Padding for prefetchable memory
+ //
+ PaddingResource++;
+ PaddingResource->Desc = 0x8A;
+ PaddingResource->Len = 0x2B;
+ PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ PaddingResource->GenFlag = 0x0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrSpaceGranularity = 32;
+ } else {
+ PaddingResource->AddrSpaceGranularity = 32;
+ }
+ PaddingResource->SpecificFlag = 06;
+ //
+ // Padding for prefetchable memory
+ //
+ PaddingResource->AddrRangeMin = 0;
+ if (SetResourceforTbt) {
+ PaddingResource->AddrLen = RsvdPciePMegaMem * 0x100000;
+ } else {
+ PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
+ }
+ //
+ // Pad 16 MB of MEM
+ //
+ if (SetResourceforTbt) {
+ PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
+ } else {
+ PaddingResource->AddrRangeMax = 1;
+ }
+ //
+ // Alignment
+ //
+ // Padding for I/O
+ //
+ PaddingResource++;
+ PaddingResource->Desc = 0x8A;
+ PaddingResource->Len = 0x2B;
+ PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
+ PaddingResource->GenFlag = 0x0;
+ PaddingResource->SpecificFlag = 0;
+ PaddingResource->AddrRangeMin = 0;
+ PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
+ //
+ // Pad 4K of IO
+ //
+ PaddingResource->AddrRangeMax = 1;
+ //
+ // Alignment
+ //
+ // Terminate the entries.
+ //
+ PaddingResource++;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR;
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;
+
+ *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
new file mode 100644
index 0000000000..09465b2757
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
@@ -0,0 +1,130 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCI_HOT_PLUG_H_
+#define _PCI_HOT_PLUG_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Base.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <IndustryStandard/Acpi10.h>
+#include <Protocol/PciHotPlugInit.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Guid/HobList.h>
+#include <Library/HobLib.h>
+#include <Protocol/SaPolicy.h>
+
+#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U', 'L', 'P')
+
+#define ACPI \
+ { \
+ { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \
+ ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 \
+ }
+
+#define PCI(device, function) \
+ { \
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof (PCI_DEVICE_PATH)), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \
+ (UINTN) function, (UINTN) device \
+ }
+
+#define END \
+ { \
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \
+ }
+
+#define LPC(eisaid, function) \
+ { \
+ { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \
+ ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid), function \
+ }
+
+typedef struct PCIE_HOT_PLUG_DEVICE_PATH {
+ ACPI_HID_DEVICE_PATH PciRootBridgeNode;
+ PCI_DEVICE_PATH PciRootPortNode;
+ EFI_DEVICE_PATH_PROTOCOL EndDeviceNode;
+} PCIE_HOT_PLUG_DEVICE_PATH;
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle; // Handle for protocol this driver installs on
+ EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol;
+} PCI_HOT_PLUG_INSTANCE;
+
+/**
+ This procedure returns a list of Root Hot Plug controllers that require
+ initialization during boot process
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+ @param[out] HpcCount The number of Root HPCs returned.
+ @param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetRootHpcList (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ OUT UINTN *PhpcCount,
+ OUT EFI_HPC_LOCATION **PhpcList
+ );
+
+/**
+ This procedure Initializes one Root Hot Plug Controller
+ This process may casue initialization of its subordinate buses
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
+ @param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
+ @param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
+ @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRootHpc (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
+ IN UINT64 PhpcPciAddress,
+ IN EFI_EVENT Event, OPTIONAL
+ OUT EFI_HPC_STATE *PhpcState
+ );
+
+/**
+ Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
+
+ @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
+ @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
+ @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
+ @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
+ @param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
+ @param[out] Attribute Describes how padding is accounted for.
+
+ @retval EFI_SUCCESS.
+**/
+EFI_STATUS
+EFIAPI
+GetResourcePadding (
+ IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
+ IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath,
+ IN UINT64 PhpcPciAddress,
+ OUT EFI_HPC_STATE *PhpcState,
+ OUT VOID **Padding,
+ OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
new file mode 100644
index 0000000000..903e681443
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
@@ -0,0 +1,63 @@
+## @file
+# This module will perform specific PCI-Express devices
+# resource configuration.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PciHotPlug
+ FILE_GUID = 3022E512-B94A-4F12-806D-7EF1177899D8
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = PciHotPlug
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DevicePathLib
+ DebugLib
+ UefiLib
+ HobLib
+ PchPcieRpLib
+ ConfigBlockLib
+ TbtCommonLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PciHotPlug.c
+ PciHotPlug.h
+
+[Protocols]
+ gEfiPciHotPlugInitProtocolGuid ## PRODUCES
+ gSaPolicyProtocolGuid ## CONSUMES
+
+[Guids]
+ gEfiHobListGuid ## CONSUMES
+ gPcieRpConfigGuid ## CONSUMES
+
+[Pcd]
+
+[Depex]
+ gDxeTbtPolicyProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3PcieTbt.asl b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3PcieTbt.asl
new file mode 100644
index 0000000000..804c947f7c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3PcieTbt.asl
@@ -0,0 +1,405 @@
+/** @file
+ ACPI RTD3 SSDT table for SPT PCIe
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#define PID_ICC 0xDC
+#define R_PCH_PCR_ICC_MSKCKRQ 0x100C ///< Mask Control CLKREQ
+
+External(PCRA,MethodObj)
+External(PCRO,MethodObj)
+External(\MMRP, MethodObj)
+External(\MMTB, MethodObj)
+External(\TRDO, IntObj)
+External(\TRD3, IntObj)
+External(\TBPE, IntObj)
+External(\TOFF, IntObj)
+External(\TBSE, IntObj)
+External(\TBOD, IntObj)
+External(\TBRP, IntObj)
+External(\TBHR, IntObj)
+External(\RTBC, IntObj)
+External(\TBCD, IntObj)
+
+Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON
+
+Name(WKEN, 0)
+
+ Method(_S0W, 0)
+ {
+ /// This method returns the lowest D-state supported by PCIe root port during S0 state
+
+ ///- PMEs can be generated from D3hot for ULT
+ Return(4)
+
+ /** @defgroup pcie_s0W PCIE _S0W **/
+ } // End _S0W
+
+ Method (_DSD, 0) {
+ Return (
+ Package () {
+ ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
+ Package () {
+ Package (2) {"HotPlugSupportInD3", 1},
+ }
+ }
+ ) // End of Return ()
+ }
+
+ Method(_DSW, 3)
+ {
+ /// This method is used to enable/disable wake from PCIe (WKEN)
+ If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WAKE# from generating runtime PME
+ /// Also set 2 to TOFF.
+ Store(0, WKEN)
+ Store (2, TOFF)
+ } Else { /// If Staying in S0
+ If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
+ { ///- Set PME
+ Store(1, WKEN)
+ Store (1, TOFF)
+ } Else { ///- Disable runtime PME, either because staying in D0 or disabling wake
+ Store(0, WKEN)
+ Store(0, TOFF)
+ }
+ }
+
+ /** @defgroup pcie_dsw PCIE _DSW **/
+ } // End _DSW
+
+
+ PowerResource(PXP, 0, 0)
+ {
+ /// Define the PowerResource for PCIe slot
+ /// Method: _STA(), _ON(), _OFF()
+ /** @defgroup pcie_pxp PCIE Power Resource **/
+
+ Method(_STA, 0)
+ {
+ Return(PSTA())
+ } /** @defgroup pcie_sta PCIE _STA method **/
+
+ Method(_ON) /// Turn on core power to PCIe Slot
+ {
+ Store(1, TRDO)
+ PON()
+ Store(0, TRDO)
+ } /** @defgroup pcie_on PCIE _ON method **/
+
+ Method(_OFF) /// Turn off core power to PCIe Slot
+ {
+ Store(1, TRD3)
+ POFF()
+ Store(0, TRD3)
+ } // End of Method_OFF
+ } // End PXP
+
+ Method(PSTA, 0)
+ {
+ /// Returns the status of PCIe slot core power
+ // detect power pin status
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) {
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // IOEX mode
+ }
+ // detect reset pin status
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // GPIO mode
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
+ Return (1)
+ } Else {
+ Return (0)
+ }
+ } // IOEX mode
+ }
+ Return (0)
+ } /** @defgroup pcie_sta PCIE _STA method **/
+
+ Method (SXEX, 0, Serialized) {
+
+ Store(\MMTB(TBSE), Local7)
+ OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG MMIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(100, Local1)
+ Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT
+ While (LGreater(Local1, 0)) {
+
+ Store(Subtract(Local1, 1), Local1)
+ Store(TB2P, Local2)
+ If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone
+ Return()
+ }
+ If (And(Local2, 1)) { // Done
+ break
+ }
+ Sleep(5)
+ }
+ Store(0x0, P2TB) // Write 0 to PCIe2TBT
+
+ // Fast Link bring-up flow
+ Store(500, Local1)
+ While (LGreater(Local1, 0)) {
+ Store(Subtract(Local1, 1), Local1)
+ Store(TB2P, Local2)
+ If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone
+ Return()
+ }
+ If (LNotEqual(DIVI, 0xFFFFFFFF)) {
+ break
+ }
+ Sleep(10)
+ }
+ } // End of Method(SXEX, 0, Serialized)
+
+ Method(PON) /// Turn on core power to PCIe Slot
+ {
+
+ Store(\MMRP(\TBSE), Local7)
+ OperationRegion(L23P,SystemMemory,Local7,0xE4)
+ Field(L23P,WordAcc, NoLock, Preserve)
+ {
+ Offset(0xA4),// PMCSR
+ PSD0, 2, // PowerState
+ Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ }
+
+ Store(\MMTB(\TBSE), Local6)
+ OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0xA4),
+ TBPS, 2, // PowerState of TBT
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(0, TOFF)
+ // Check RTD3 power enable, if already ON, no need to execute sx_exit
+ If (TBPE) {
+ Return()
+ }
+
+ Store(0,G2SD)
+ If (\RTBC) {
+ /// de-assert CLK_REQ MSK
+ if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enabled
+ PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1)))) // And ~SCLK to clear bit
+ }
+ Sleep(\TBCD)
+ }
+
+ /// Turn ON Power for PCIe Slot
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
+ Store(1, TBPE)
+ Sleep(PEP0) /// Sleep for programmable delay
+ }
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
+ Store(1, TBPE)
+ Sleep(PEP0) /// Sleep for programmable delay
+ }
+ }
+
+ /// De-Assert Reset Pin
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
+ }
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
+ }
+ }
+
+ /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition (L23R2DT)
+ Store(0, DPGE)
+ Store(1, L2TR)
+ Sleep(16)
+ Store(0, Local0)
+ /// Wait up to 12 ms for transition to Detect
+ While(L2TR) {
+ If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ /// Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms)
+ /// Worst case per PCIe spec from Detect to Link Active is:
+ /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2)
+ Store(1, DPGE)
+ Store(0, Local0)
+ While(LEqual(LASX,0)) {
+ If(Lgreater(Local0, 8))
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) = 0
+
+ // TBT special sleep.
+ Store(PSD0, Local1)
+ Store(0, PSD0)// D0
+ Store(20, Local2) // Poll for TBT, up to 200 ms
+
+ While (LGreater(Local2, 0)) {
+ Store(Subtract(Local2, 1), Local2)
+ Store(TB2P, Local3)
+ If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done
+ break
+ }
+ Sleep(10)
+ }
+
+ If (LLessEqual(Local2, 0)) {
+ }
+ SXEX()
+ Store(Local1, PSD0) // Back to Local1
+ } /** @defgroup pcie_on PCIE _ON method **/
+
+ Method(POFF) { /// Turn off core power to PCIe Slot
+ If (LEqual(TOFF, 0)) {
+ Return()
+ }
+ Store(\MMRP(\TBSE), Local7)
+ OperationRegion(L23P, SystemMemory, Local7, 0xE4)
+ Field(L23P,WordAcc, NoLock, Preserve)
+ {
+ Offset(0xA4),// PMCSR
+ PSD0, 2, // PowerState
+ Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ }
+
+ Store(\MMTB(TBSE), Local6)
+ OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
+ Field(TBDI,DWordAcc, NoLock, Preserve) {
+ DIVI, 32,
+ CMDR, 32,
+ Offset(0xA4),
+ TBPS, 2, // PowerState of TBT
+ Offset(0x548),
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(PSD0, Local1)
+ Store(0, PSD0)// D0
+
+ Store(P2TB, Local3)
+
+ If (Lgreater(TOFF, 1)) {
+ Sleep(10)
+ Store(Local1, PSD0) // Back to Local1
+ Return()
+ }
+ Store(0, TOFF)
+
+ Store(Local1, PSD0) // Back to Local1
+
+ /// Set L23_Rdy Entry Request (L23ER)
+ Store(1, L2TE)
+ Sleep(16)
+ Store(0, Local0)
+ While(L2TE) {
+ If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms
+ {
+ Break
+ }
+ Sleep(16)
+ Increment(Local0)
+ }
+ Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) = 1
+
+ /// Assert Reset Pin
+ if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
+ if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
+ }
+ if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
+ }
+ }
+ If (\RTBC) {
+ /// assert CLK_REQ MSK
+ if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enabled
+ PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK, 1))) // Or SCLK to set bit
+ Sleep(16)
+ }
+ }
+
+ /// Power OFF for TBT
+ if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
+ if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
+ }
+ if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
+ }
+ }
+
+ Store(0, TBPE)
+
+ Store(1, LDIS) /// Set Link Disable
+ Store(0, LDIS) /// Toggle link disable
+
+ /// enable WAKE
+ If (WKEN) {
+ If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating enabled
+ If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode
+ \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
+ \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to ACPI(0=ACPI mode, 1=GPIO mode)
+ }
+ If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode
+ \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG, 1)),DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
+ }
+ }
+ }
+ Sleep(\TBOD)
+ /** @defgroup pcie_off PCIE _OFF method **/
+ } // End of Method_OFF
+
+ Name(_PR0, Package(){PXP})
+ Name(_PR3, Package(){PXP})
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
new file mode 100644
index 0000000000..12685e57bf
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
@@ -0,0 +1,1877 @@
+/** @file
+ Thunderbolt ACPI methods
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#define DTBT_CONTROLLER 0x00
+#define DTBT_TYPE_PCH 0x01
+#define DTBT_TYPE_PEG 0x02
+#define DTBT_SMI_HANDLER_NUMBER 0xF7
+#define TBT_SMI_ENUMERATION_FUNCTION 21
+#define TBT_SMI_RESET_SWITCH_FUNCTION 22
+#define TBT_SMI_DISABLE_MSI_FUNCTION 23
+#ifndef BIT29
+#define BIT29 0x20000000
+#endif
+
+Name(LDLY, 300) //300 ms
+Name (TNVB, 0xFFFF0000) // TBT NVS Base address
+Name (TNVL, 0xAA55) // TBT NVS Length
+Include ("Acpi/TbtNvs.asl")
+
+External(\_SB.PCI0.RP02.L23D, MethodObj)
+External(\_SB.PCI0.RP03.L23D, MethodObj)
+External(\_SB.PCI0.RP04.L23D, MethodObj)
+External(\_SB.PCI0.RP05.L23D, MethodObj)
+External(\_SB.PCI0.RP06.L23D, MethodObj)
+External(\_SB.PCI0.RP07.L23D, MethodObj)
+External(\_SB.PCI0.RP08.L23D, MethodObj)
+External(\_SB.PCI0.RP09.L23D, MethodObj)
+External(\_SB.PCI0.RP10.L23D, MethodObj)
+External(\_SB.PCI0.RP11.L23D, MethodObj)
+External(\_SB.PCI0.RP12.L23D, MethodObj)
+External(\_SB.PCI0.RP13.L23D, MethodObj)
+External(\_SB.PCI0.RP14.L23D, MethodObj)
+External(\_SB.PCI0.RP15.L23D, MethodObj)
+External(\_SB.PCI0.RP16.L23D, MethodObj)
+External(\_SB.PCI0.RP17.L23D, MethodObj)
+External(\_SB.PCI0.RP18.L23D, MethodObj)
+External(\_SB.PCI0.RP19.L23D, MethodObj)
+External(\_SB.PCI0.RP20.L23D, MethodObj)
+External(\_SB.PCI0.RP21.L23D, MethodObj)
+External(\_SB.PCI0.RP22.L23D, MethodObj)
+External(\_SB.PCI0.RP23.L23D, MethodObj)
+External(\_SB.PCI0.RP24.L23D, MethodObj)
+
+External(\_SB.PCI0.RP01.DL23, MethodObj)
+External(\_SB.PCI0.RP02.DL23, MethodObj)
+External(\_SB.PCI0.RP03.DL23, MethodObj)
+External(\_SB.PCI0.RP04.DL23, MethodObj)
+External(\_SB.PCI0.RP05.DL23, MethodObj)
+External(\_SB.PCI0.RP06.DL23, MethodObj)
+External(\_SB.PCI0.RP07.DL23, MethodObj)
+External(\_SB.PCI0.RP08.DL23, MethodObj)
+External(\_SB.PCI0.RP09.DL23, MethodObj)
+External(\_SB.PCI0.RP10.DL23, MethodObj)
+External(\_SB.PCI0.RP11.DL23, MethodObj)
+External(\_SB.PCI0.RP12.DL23, MethodObj)
+External(\_SB.PCI0.RP13.DL23, MethodObj)
+External(\_SB.PCI0.RP14.DL23, MethodObj)
+External(\_SB.PCI0.RP15.DL23, MethodObj)
+External(\_SB.PCI0.RP16.DL23, MethodObj)
+External(\_SB.PCI0.RP17.DL23, MethodObj)
+External(\_SB.PCI0.RP18.DL23, MethodObj)
+External(\_SB.PCI0.RP19.DL23, MethodObj)
+External(\_SB.PCI0.RP20.DL23, MethodObj)
+External(\_SB.PCI0.RP21.DL23, MethodObj)
+External(\_SB.PCI0.RP22.DL23, MethodObj)
+External(\_SB.PCI0.RP23.DL23, MethodObj)
+External(\_SB.PCI0.RP24.DL23, MethodObj)
+
+External(\_SB.PCI0.RTEN, MethodObj)
+External(\_SB.PCI0.RTDS, MethodObj)
+External(\_SB.PCI0.RP01.PON, MethodObj)
+External(\_SB.PCI0.RP02.PON, MethodObj)
+External(\_SB.PCI0.RP03.PON, MethodObj)
+External(\_SB.PCI0.RP04.PON, MethodObj)
+External(\_SB.PCI0.RP05.PON, MethodObj)
+External(\_SB.PCI0.RP06.PON, MethodObj)
+External(\_SB.PCI0.RP07.PON, MethodObj)
+External(\_SB.PCI0.RP08.PON, MethodObj)
+External(\_SB.PCI0.RP09.PON, MethodObj)
+External(\_SB.PCI0.RP10.PON, MethodObj)
+External(\_SB.PCI0.RP11.PON, MethodObj)
+External(\_SB.PCI0.RP12.PON, MethodObj)
+External(\_SB.PCI0.RP13.PON, MethodObj)
+External(\_SB.PCI0.RP14.PON, MethodObj)
+External(\_SB.PCI0.RP15.PON, MethodObj)
+External(\_SB.PCI0.RP16.PON, MethodObj)
+External(\_SB.PCI0.RP17.PON, MethodObj)
+External(\_SB.PCI0.RP18.PON, MethodObj)
+External(\_SB.PCI0.RP19.PON, MethodObj)
+External(\_SB.PCI0.RP20.PON, MethodObj)
+External(\_SB.PCI0.RP21.PON, MethodObj)
+External(\_SB.PCI0.RP22.PON, MethodObj)
+External(\_SB.PCI0.RP23.PON, MethodObj)
+External(\_SB.PCI0.RP24.PON, MethodObj)
+External(\_SB.PCI0.PEG0.PG00._ON, MethodObj)
+External(\_SB.PCI0.PEG1.PG01._ON, MethodObj)
+External(\_SB.PCI0.PEG2.PG02._ON, MethodObj)
+
+Name(TRDO, 0) // 1 during TBT RTD3 _ON
+Name(TRD3, 0) // 1 during TBT RTD3 _OFF
+Name(TBPE, 0) // Reflects RTD3_PWR_EN value
+Name(TOFF, 0) // param to TBT _OFF method
+
+ Method (TBON, 0, Serialized) {
+ // TBT On process before entering Sx state.
+ Store(1, TRDO)
+ Switch (ToInteger(\RPS0)) { // TBT Root port Selector
+ Case (1) {
+ If (CondRefOf(\_SB.PCI0.RP01.PON)) {
+ \_SB.PCI0.RP01.PON()
+ }
+ }
+ Case (2) {
+ If (CondRefOf(\_SB.PCI0.RP02.PON)) {
+ \_SB.PCI0.RP02.PON()
+ }
+ }
+ Case (3) {
+ If (CondRefOf(\_SB.PCI0.RP03.PON)) {
+ \_SB.PCI0.RP03.PON()
+ }
+ }
+ Case (4) {
+ If (CondRefOf(\_SB.PCI0.RP04.PON)) {
+ \_SB.PCI0.RP04.PON()
+ }
+ }
+ Case (5) {
+ If (CondRefOf(\_SB.PCI0.RP05.PON)) {
+ \_SB.PCI0.RP05.PON()
+ }
+ }
+ Case (6) {
+ If (CondRefOf(\_SB.PCI0.RP06.PON)) {
+ \_SB.PCI0.RP06.PON()
+ }
+ }
+ Case (7) {
+ If (CondRefOf(\_SB.PCI0.RP07.PON)) {
+ \_SB.PCI0.RP07.PON()
+ }
+ }
+ Case (8) {
+ If (CondRefOf(\_SB.PCI0.RP08.PON)) {
+ \_SB.PCI0.RP08.PON()
+ }
+ }
+ Case (9) {
+ If (CondRefOf(\_SB.PCI0.RP09.PON)) {
+ \_SB.PCI0.RP09.PON()
+ }
+ }
+ Case (10) {
+ If (CondRefOf(\_SB.PCI0.RP10.PON)) {
+ \_SB.PCI0.RP10.PON()
+ }
+ }
+ Case (11) {
+ If (CondRefOf(\_SB.PCI0.RP11.PON)) {
+ \_SB.PCI0.RP11.PON()
+ }
+ }
+ Case (12) {
+ If (CondRefOf(\_SB.PCI0.RP12.PON)) {
+ \_SB.PCI0.RP12.PON()
+ }
+ }
+ Case (13) {
+ If (CondRefOf(\_SB.PCI0.RP13.PON)) {
+ \_SB.PCI0.RP13.PON()
+ }
+ }
+ Case (14) {
+ If (CondRefOf(\_SB.PCI0.RP14.PON)) {
+ \_SB.PCI0.RP14.PON()
+ }
+ }
+ Case (15) {
+ If (CondRefOf(\_SB.PCI0.RP15.PON)) {
+ \_SB.PCI0.RP15.PON()
+ }
+ }
+ Case (16) {
+ If (CondRefOf(\_SB.PCI0.RP16.PON)) {
+ \_SB.PCI0.RP16.PON()
+ }
+ }
+ Case (17) {
+ If (CondRefOf(\_SB.PCI0.RP17.PON)) {
+ \_SB.PCI0.RP17.PON()
+ }
+ }
+ Case (18) {
+ If (CondRefOf(\_SB.PCI0.RP18.PON)) {
+ \_SB.PCI0.RP18.PON()
+ }
+ }
+ Case (19) {
+ If (CondRefOf(\_SB.PCI0.RP19.PON)) {
+ \_SB.PCI0.RP19.PON()
+ }
+ }
+ Case (20) {
+ If (CondRefOf(\_SB.PCI0.RP20.PON)) {
+ \_SB.PCI0.RP20.PON()
+ }
+ }
+ Case (21) {
+ If (CondRefOf(\_SB.PCI0.RP21.PON)) {
+ \_SB.PCI0.RP21.PON()
+ }
+ }
+ Case (22) {
+ If (CondRefOf(\_SB.PCI0.RP22.PON)) {
+ \_SB.PCI0.RP22.PON()
+ }
+ }
+ Case (23) {
+ If (CondRefOf(\_SB.PCI0.RP23.PON)) {
+ \_SB.PCI0.RP23.PON()
+ }
+ }
+ Case (24) {
+ If (CondRefOf(\_SB.PCI0.RP24.PON)) {
+ \_SB.PCI0.RP24.PON()
+ }
+ }
+ }//Switch(ToInteger(RPS0)) // TBT Selector
+ Store(0, TRDO)
+ } // End of TBON
+ //
+ // Name: TBTD
+ // Description: Function to return the TBT RP# device no
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: TBT RP# device no
+ //
+ Method(TBTD,2)
+ {
+ ADBG("TBTD")
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (Package () {1, 2, 3, 4, 5, 6, 7, 8})
+ {
+ Store(0x1C, Local0) //Device28-Function0...Function7 = 11100.000...111
+ }
+ Case (Package () {9, 10, 11, 12, 13, 14, 15, 16})
+ {
+ Store(0x1D, Local0) //Device29-Function0...Function7 = 11101.000...111
+ }
+ Case (Package () {17, 18, 19, 20, 21, 22, 23, 24})
+ {
+ Store(0x1B, Local0) //Device27-Function0...Function3 = 11011.000...011
+ }
+ }
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (Package () {1, 2, 3})
+ {
+ Store(0x1, Local0) //Device1-Function0...Function2 = 00001.000...010
+ }
+ }
+ } Else {
+ Store(0xFF, Local0)
+ }
+
+ ADBG("Device no")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(TBTD,1)
+
+ //
+ // Name: TBTF
+ // Description: Function to return the TBT RP# function no
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: TBT RP# function no
+ //
+ Method(TBTF,2)
+ {
+ ADBG("TBTF")
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ Store(And(\RPA1,0xF), Local0) //Device28-Function0 = 11100.000
+ }
+ Case (2)
+ {
+ Store(And(\RPA2,0xF), Local0) //Device28-Function1 = 11100.001
+ }
+ Case (3)
+ {
+ Store(And(\RPA3,0xF), Local0) //Device28-Function2 = 11100.010
+ }
+ Case (4)
+ {
+ Store(And(\RPA4,0xF), Local0) //Device28-Function3 = 11100.011
+ }
+ Case (5)
+ {
+ Store(And(\RPA5,0xF), Local0) //Device28-Function4 = 11100.100
+ }
+ Case (6)
+ {
+ Store(And(\RPA6,0xF), Local0) //Device28-Function5 = 11100.101
+ }
+ Case (7)
+ {
+ Store(And(\RPA7,0xF), Local0) //Device28-Function6 = 11100.110
+ }
+ Case (8)
+ {
+ Store(And(\RPA8,0xF), Local0) //Device28-Function7 = 11100.111
+ }
+ Case (9)
+ {
+ Store(And(\RPA9,0xF), Local0) //Device29-Function0 = 11101.000
+ }
+ Case (10)
+ {
+ Store(And(\RPAA,0xF), Local0) //Device29-Function1 = 11101.001
+ }
+ Case (11)
+ {
+ Store(And(\RPAB,0xF), Local0) //Device29-Function2 = 11101.010
+ }
+ Case (12)
+ {
+ Store(And(\RPAC,0xF), Local0) //Device29-Function3 = 11101.011
+ }
+ Case (13)
+ {
+ Store(And(\RPAD,0xF), Local0) //Device29-Function4 = 11101.100
+ }
+ Case (14)
+ {
+ Store(And(\RPAE,0xF), Local0) //Device29-Function5 = 11101.101
+ }
+ Case (15)
+ {
+ Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110
+ }
+ Case (16)
+ {
+ Store(And(\RPAG,0xF), Local0) //Device29-Function7 = 11101.111
+ }
+ Case (17)
+ {
+ Store(And(\RPAH,0xF), Local0) //Device27-Function0 = 11011.000
+ }
+ Case (18)
+ {
+ Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001
+ }
+ Case (19)
+ {
+ Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010
+ }
+ Case (20)
+ {
+ Store(And(\RPAK,0xF), Local0) //Device27-Function3 = 11011.011
+ }
+ Case (21)
+ {
+ Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100
+ }
+ Case (22)
+ {
+ Store(And(\RPAM,0xF), Local0) //Device27-Function5 = 11011.101
+ }
+ Case (23)
+ {
+ Store(And(\RPAN,0xF), Local0) //Device27-Function6 = 11011.110
+ }
+ Case (24)
+ {
+ Store(And(\RPAO,0xF), Local0) //Device27-Function7 = 11011.111
+ }
+ }
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ Store(0x0, Local0) //Device1-Function0 = 00001.000
+ }
+ Case (2)
+ {
+ Store(0x1, Local0) //Device1-Function1 = 00001.001
+ }
+ Case (3)
+ {
+ Store(0x2, Local0) //Device1-Function2 = 00001.010
+ }
+ }
+ } Else {
+ Store(0xFF, Local0)
+ }
+
+ ADBG("Function no")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(TBTF,1)
+
+ //
+ // Name: MMRP
+ // Description: Function to return the Pci base address of TBT rootport
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(MMRP, 2, Serialized)
+ {
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ Return(Local0)
+ } // End of Method(MMRP)
+
+ //
+ // Name: MMRP
+ // Description: Function to return the Pci base address of TBT Up stream port
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+ Method(MMTB, 2, Serialized)
+ {
+ ADBG("MMTB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x19),
+ SBUS, 8
+ }
+ Store(SBUS, Local2)
+ Store(\_SB.PCI0.GPCB(), Local0)
+ Multiply(Local2, 0x100000, Local2)
+ Add(Local2, Local0, Local0) // TBT HR US port
+
+ ADBG("TBT-US-ADR")
+ ADBG(Local0)
+
+ Return(Local0)
+ } // End of Method(MMTB, 1, Serialized)
+ //
+ // Name: FFTB
+ // Description: Function to Check for FFFF in TBT PCIe
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ // Return: 1 if TBT PCIe space has value FFFF, 0 if not
+ //
+ Method(FFTB, 2, Serialized)
+ {
+ ADBG("FFTB")
+
+ Add(MMTB(Arg0, Arg1), 0x548, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x08)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(TB2P, Local1)
+
+ If(LEqual(Local1, 0xFFFFFFFF))
+ {
+ ADBG("FFTb 1")
+ Return (1)
+ }
+ Else
+ {
+ ADBG("FFTb 0")
+ Return (0)
+ }
+ } // End of Method(FFTB)
+
+Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, fixed up during POST
+
+Scope(\_GPE)
+{
+ //
+ //
+ //OS up Mail Box command execution to host router upstream port each time
+ //exiting from Sx State .Avoids intermediate
+ //PCIe Scan by OS during resorce allocation
+ // Arg0 : PCIe Base address
+ // Arg1 : Controller Type 0x00 : DTBT
+ //Developer notes: Called twice
+ // 1. During OS INIT (booting to OS from S3-S5/Reboot)
+ // 2. Up on Hot plug
+ //
+ Method(OSUP, 2, Serialized)
+ {
+ ADBG("OSUP")
+
+ Add(Arg0, 0x540, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x10)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ IT2P, 32,
+ IP2T, 32,
+ DT2P, 32,
+ DP2T, 32
+ }
+
+ Store(100, Local1)
+ Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT
+
+ While(LGreater(Local1, 0))
+ {
+ Store(Subtract(Local1, 1), Local1)
+ Store(DT2P, Local2)
+
+ If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))// Device gone
+ {
+ ADBG("Dev gone")
+ Return(2)
+ }
+ If(And(Local2, 1)) // Done
+ {
+ ADBG("Cmd acknowledged")
+ break
+ }
+ Sleep(50)
+ }
+ If(LEqual(TRWA,1))
+ {
+ Store(0xC, DP2T) // Write OSUP to PCIe2TBT
+ }
+ Else
+ {
+ Store(0x0, DP2T) // Write 0 to PCIe2TBT
+ }
+
+ //Store(0x00, P2TB) // Write 0 to PCIe2TBT
+
+ ADBG("End-of-OSUP")
+
+ Return(1)
+ } // End of Method(OSUP, 1, Serialized)
+
+ //
+ // Check for FFFF in TBT
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TBFF, 2, Serialized)
+ {
+ ADBG("TBFF")
+
+ Store(MMTB(Arg0, Arg1), Local0)
+ OperationRegion (PXVD, SystemMemory, Local0, 0x8)
+ Field (PXVD, DWordAcc, NoLock, Preserve) {
+ VEDI, 32, // Vendor/Device ID
+ CMDR, 32 // CMD register
+ }
+
+ Store(VEDI, Local1)
+
+ If (LEqual(Local1, 0xFFFFFFFF)) {
+ If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode?
+ If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone
+ Return (2)// Notify only
+ }
+ Return (1)// Exit w/o notify
+ } Else {
+ Return (OSUP(Local0, DTBT_CONTROLLER))
+ }
+ } Else
+ {
+ ADBG("Dev Present")
+ Return (0)
+ }
+ } // End of Method(TBFF, 1, Serialized)
+
+ //
+ // Secondary bus of TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TSUB, 2, Serialized)
+ {
+ ADBG("TSUB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ ADBG("ADR")
+ ADBG(Local0)
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x19),
+ SBUS, 8
+ }
+
+ ADBG("Sec Bus")
+ ADBG(SBUS)
+
+ Return(SBUS)
+ } // End of Method(TSUB, 0, Serialized)
+
+ //
+ // Pmem of TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(TSUP, 2, Serialized)
+ {
+ ADBG("TSUB")
+
+ Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
+
+ Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
+ Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
+
+ ADBG("ADR:")
+ ADBG(Local0)
+
+ OperationRegion (MMMM, SystemMemory, Local0, 0x30)
+ Field (MMMM, AnyAcc, NoLock, Preserve)
+ {
+ CMDS, 32,
+ Offset(0x19),
+ SBUS, 8,
+ SBU5, 8,
+ Offset(0x1C),
+ SEIO, 32,
+ MMBL, 32,
+ PMBL, 32,
+
+ }
+
+ ADBG("Pmem of TBT RP:")
+ ADBG(PMBL)
+
+ Return(PMBL)
+ } // End of Method(TSUP, 0, Serialized)
+
+ //
+ // Wait for secondary bus in TBT RP
+ // Input: Arg0 -> Tbt Root Port value from Tbt NVS
+ // Input: Arg1 -> Tbt port type value from Tbt NVS
+ //
+
+ Method(WSUB, 2, Serialized)
+ {
+ ADBG(Concatenate("WSUB=", ToHexString(Arg0)))
+ ADBG(ToHexString(Timer))
+
+ Store(0, Local0)
+ Store(0, Local1)
+ While(1)
+ {
+ Store(TSUP(Arg0, Arg1), Local1)
+ If(LGreater(Local1, 0x1FFF1))
+ {
+ ADBG("WSUB-Finished")
+ Break
+ }
+ Else
+ {
+ Add(Local0, 1, Local0)
+ If(LGreater(Local0, 1000))
+ {
+ Sleep(1000)
+ ADBG("WSUB-Deadlock")
+ }
+ Else
+ {
+ Sleep(16)
+ }
+ }
+ }
+ ADBG(Concatenate("WSUb=", ToHexString(Local1)))
+ } // End of Method(WSUB)
+
+ // Wait for _WAK finished
+ Method(WWAK)
+ {
+ ADBG("WWAK")
+
+ Wait(WFEV, 0xFFFF)
+ Signal(WFEV) // Set it, to enter on next HP
+ } // End of Method(WWAK)
+
+ Method(NTFY, 2, Serialized)
+ {
+ ADBG("NTFY")
+
+ If(LEqual(NOHP,1))
+ {
+ If (LEqual(Arg1, DTBT_TYPE_PCH)) {
+ Switch(ToInteger(Arg0)) // TBT Selector
+ {
+ Case (1)
+ {
+ ADBG("Notify RP01")
+ Notify(\_SB.PCI0.RP01,0)
+ }
+ Case (2)
+ {
+ ADBG("Notify RP02")
+ Notify(\_SB.PCI0.RP02,0)
+ }
+ Case (3)
+ {
+ ADBG("Notify RP03")
+ Notify(\_SB.PCI0.RP03,0)
+ }
+ Case (4)
+ {
+ ADBG("Notify RP04")
+ Notify(\_SB.PCI0.RP04,0)
+ }
+ Case (5)
+ {
+ ADBG("Notify RP05")
+ Notify(\_SB.PCI0.RP05,0)
+ }
+ Case (6)
+ {
+ ADBG("Notify RP06")
+ Notify(\_SB.PCI0.RP06,0)
+ }
+ Case (7)
+ {
+ ADBG("Notify RP07")
+ Notify(\_SB.PCI0.RP07,0)
+ }
+ Case (8)
+ {
+ ADBG("Notify RP08")
+ Notify(\_SB.PCI0.RP08,0)
+ }
+ Case (9)
+ {
+ ADBG("Notify RP09")
+ Notify(\_SB.PCI0.RP09,0)
+ }
+ Case (10)
+ {
+ ADBG("Notify RP10")
+ Notify(\_SB.PCI0.RP10,0)
+ }
+ Case (11)
+ {
+ ADBG("Notify RP11")
+ Notify(\_SB.PCI0.RP11,0)
+ }
+ Case (12)
+ {
+ ADBG("Notify RP12")
+ Notify(\_SB.PCI0.RP12,0)
+ }
+ Case (13)
+ {
+ ADBG("Notify RP13")
+ Notify(\_SB.PCI0.RP13,0)
+ }
+ Case (14)
+ {
+ ADBG("Notify RP14")
+ Notify(\_SB.PCI0.RP14,0)
+ }
+ Case (15)
+ {
+ ADBG("Notify RP15")
+ Notify(\_SB.PCI0.RP15,0)
+ }
+ Case (16)
+ {
+ ADBG("Notify RP16")
+ Notify(\_SB.PCI0.RP16,0)
+ }
+ Case (17)
+ {
+ ADBG("Notify RP17")
+ Notify(\_SB.PCI0.RP17,0)
+ }
+ Case (18)
+ {
+ ADBG("Notify RP18")
+ Notify(\_SB.PCI0.RP18,0)
+ }
+ Case (19)
+ {
+ ADBG("Notify RP19")
+ Notify(\_SB.PCI0.RP19,0)
+ }
+ Case (20)
+ {
+ ADBG("Notify RP20")
+ Notify(\_SB.PCI0.RP20,0)
+ }
+ Case (21)
+ {
+ ADBG("Notify RP21")
+ Notify(\_SB.PCI0.RP21,0)
+ }
+ Case (22)
+ {
+ ADBG("Notify RP22")
+ Notify(\_SB.PCI0.RP22,0)
+ }
+ Case (23)
+ {
+ ADBG("Notify RP23")
+ Notify(\_SB.PCI0.RP23,0)
+ }
+ Case (24)
+ {
+ ADBG("Notify RP24")
+ Notify(\_SB.PCI0.RP24,0)
+ }
+ }//Switch(ToInteger(TBSS)) // TBT Selector
+ } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
+ Switch(ToInteger(Arg0))
+ {
+ Case (1)
+ {
+ ADBG("Notify PEG0")
+ Notify(\_SB.PCI0.PEG0,0)
+ }
+ Case (2)
+ {
+ ADBG("Notify PEG1")
+ Notify(\_SB.PCI0.PEG1,0)
+ }
+ Case (3)
+ {
+ ADBG("Notify PEG2")
+ Notify(\_SB.PCI0.PEG2,0)
+ }
+ }
+ }//Switch(ToInteger(TBSS)) // TBT Selector
+ }//If(NOHP())
+ P8XH(0,0xC2)
+ P8XH(1,0xC2)
+ }// End of Method(NTFY)
+
+//
+// TBT BIOS, GPIO 5 filtering,
+// Hot plug of 12V USB devices, into TBT host router, cause electrical noise on PCH GPIOs,
+// This noise cause false hot-plug events, and negatively influence BIOS assisted hot-plug.
+// WHL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS) on any GPIO pad. Native functions have to implement their own digital glitch-filter logic
+// if needed. As HW filter was not implemented on WHL PCH, because of that SW workaround should be implemented in BIOS.
+// Register 0x544(Bios mailbox) bit 0 definition:
+// if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if bit is 0 BIOS will exit from method
+//
+
+ Method(GNIS,2, Serialized)
+ {
+
+ ADBG("GNIS")
+ If(LEqual(GP5F, 0))
+ {
+ ADBG("GNIS_Dis=0")
+ Return(0)
+ }
+ //
+ // BIOS mailbox command for GPIO filter
+ //
+ Add(MMTB(Arg0, Arg1), 0x544, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x08)
+
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ HPFI, 1,
+ Offset(0x4),
+ TB2P, 32
+ }
+ Store(TB2P, Local1)
+ ADBG(Concatenate("TB2P=", ToHexString(Local1)))
+ If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect?
+ {
+ ADBG("GNIS=0")
+ Return(0)
+ }
+ Store(HPFI, Local2)
+ ADBG(Concatenate("HPFI=", ToHexString(Local2)))
+ If(LEqual(Local2, 0x01))
+ {
+ Store(0x00, HPFI)
+ ADBG("GNIS=0")
+ Return(0)
+ }
+ // Any other values treated as a GPIO noise
+ ADBG("GNIS=1")
+ Return(1)
+ }
+
+ Method(CHKP,2, Serialized)
+ {
+ Add(MMTB(Arg0, Arg1), 0x544, Local0)
+ OperationRegion(PXVE,SystemMemory,Local0,0x08)
+
+ Field(PXVE,DWordAcc, NoLock, Preserve)
+ {
+ HPFI, 1,
+ Offset(0x4),
+ TB2P, 32
+ }
+ Store(TB2P, Local1)
+ And(Local1,BIT29,Local1)
+ ADBG(Concatenate("Local1=", ToHexString(Local1)))
+ //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29))))
+ If(LEqual(Local1, BIT29))
+ {
+ Return(1)
+ }
+ Else
+ {
+ Return(0)
+ }
+ }
+
+ //
+ // Method to Handle enumerate PCIe structure through
+ // SMI for Thunderbolt(TM) devices
+ //
+ Method(XTBT,2, Serialized)
+ {
+ ADBG("XTBT")
+ ADBG("RP :")
+ ADBG(Arg0)
+ Store(Arg0, DTCP) // Root port to enumerate
+ Store(Arg1, DTPT) // Root port Type
+ If(LEqual(Arg0, RPS0)) {
+ Store (1, Local0)
+ } ElseIf (LEqual(Arg0, RPS1)) {
+ Store (2, Local0)
+ } Else {
+ Store (0, Local0)
+ Return ()
+ }
+
+ If (TRDO) {
+ ADBG("Durng TBT_ON")
+ Return ()
+ }
+
+ If (TRD3) {
+ ADBG("During TBT_OFF")
+ Return ()
+ }
+ WWAK()
+ WSUB(Arg0, Arg1)
+ If(GNIS(Arg0, Arg1))
+ {
+ Return()
+ }
+
+ OperationRegion(SPRT,SystemIO, 0xB2,2)
+ Field (SPRT, ByteAcc, Lock, Preserve)
+ {
+ SSMP, 8
+ }
+
+ ADBG("TBT-HP-Handler")
+
+ Acquire(OSUM, 0xFFFF)
+ Store(TBFF(Arg0, Arg1), Local1)
+ If(LEqual(Local1, 1))// Only HR
+ {
+ Sleep(16)
+ Release(OSUM)
+ ADBG("OS_Up_Received")
+ Return ()
+ }
+ If(LEqual(Local1, 2)) // Disconnect
+ {
+ NTFY(Arg0, Arg1)
+ Sleep(16)
+ Release(OSUM)
+ ADBG("Disconnect")
+ Return ()
+ }
+
+ // HR and EP
+ If(LEqual(SOHP, 1))
+ {
+ // Trigger SMI to enumerate PCIe Structure
+ ADBG("TBT SW SMI")
+ Store(21, TBSF)
+ Store(0xF7, SSMP)
+ }
+ NTFY(Arg0, Arg1)
+ Sleep(16)
+ Release(OSUM)
+
+ ADBG("End-of-XTBT")
+ } // End of Method(XTBT)
+
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs
+ // Used in Two ways ,
+ // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1 Tier GPIO Handler for 1st controller
+ // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1 Tier GPIO Handler for All the controllers
+ //
+ Method(ATBT)
+ {
+ ADBG("ATBT")
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ //
+ If(LEqual(CGST,0)) { // If GPIO is Different for each controller
+ If(LEqual(RPN0,1))
+ {
+ XTBT(RPS0, RPT0)
+ }
+ } Else {
+ If(LEqual(RPN0,1))
+ {
+ XTBT(RPS0, RPT0)
+ }
+ ElseIf(LEqual(RPN1,1))
+ {
+ XTBT(RPS1, RPT1)
+ }
+ }
+ ADBG("End-of-ATBT")
+ } // End of Method(ATBT)
+
+ Method(BTBT)
+ {
+ ADBG("BTBT")
+ //
+ // Calling Method to Handle enumerate PCIe structure through
+ //
+ If(LEqual(CGST,0)) { // If GPIO is Different for each controller
+ If(LEqual(RPN1,1))
+ {
+ XTBT(RPS1, RPT1)
+ }
+ }
+ ADBG("End-of-BTBT")
+ } // End of Method(BTBT)
+ //
+ // Method to call OSPU Mail box command
+ // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT
+ // Arg1 : TBT RP Selector / DMA
+ // Arg2 : TBT Type (PCH or PEG)
+ //
+ Method(TINI, 3, Serialized)
+ {
+ ADBG("TINI")
+ If(Lequal (Arg0, DTBT_CONTROLLER))
+ {
+ //ADBG("DTBT")
+ Store(MMRP(Arg1, Arg2), Local0)
+ OperationRegion(RP_X,SystemMemory,Local0,0x20)
+ Field(RP_X,DWordAcc, NoLock, Preserve)
+ {
+ REG0, 32,
+ REG1, 32,
+ REG2, 32,
+ REG3, 32,
+ REG4, 32,
+ REG5, 32,
+ REG6, 32,
+ REG7, 32
+ }
+ Store(REG6, Local1)
+ Store(0x00F0F000, REG6)
+ Store(MMTB(Arg1, Arg2), Local2)
+ OSUP(Local2, DTBT_CONTROLLER)
+ Store(Local1, REG6)
+ }
+ ADBG("End-of-TINI")
+ }
+
+} // End of Scope (\_GPE)
+
+Scope (\_SB)
+{
+ //
+ // The code needs to be executed for TBT Hotplug Handler event (2-tier GPI GPE event architecture) is presented here
+ //
+ Method(THDR, 3, Serialized)
+ {
+ ADBG("THDR")
+ \_SB.CAGS(Arg0)
+ \_GPE.XTBT(Arg1, Arg2)
+ } // End of Method(THDR, 3, Serialized)
+} // End of Scope(\_SB)
+
+Scope (\_SB)
+{
+ //
+ // Name: CGWR [Combined GPIO Write]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> GpioPad / Expander pin
+ // Arg1 -> Value
+ // Return: Nothing
+ //
+ Method(CGWR, 2, Serialized)
+ {
+ // PCH
+ If (CondRefOf(\_SB.SGOV))
+ {
+ \_SB.SGOV(Arg0, Arg1)
+ }
+ } // End of Method(CGWR, 4, Serialized)
+
+ //
+ // Name: CGRD [Combined GPIO Read]
+ // Description: Function to read from GPIO
+ // Input: Arg0 -> GpioPad / Expander pin
+ // Arg1 -> 0: GPO [GPIO TX State]
+ // 1: GPI [GPIO RX State]
+ // Return: Value
+ //
+ Method(CGRD, 2, Serialized)
+ {
+ Store(1, Local0)
+ // PCH
+ If (LEqual(Arg1, 0))
+ {
+ // GPIO TX State
+ If (CondRefOf(\_SB.GGOV))
+ {
+ Store(\_SB.GGOV(Arg0), Local0)
+ }
+ }
+ ElseIf (LEqual(Arg1, 1))
+ {
+ // GPIO RX State
+ If (CondRefOf(\_SB.GGIV))
+ {
+ Store(\_SB.GGIV(Arg0), Local0)
+ }
+ }
+ Return(Local0)
+ } // End of Method(CGRD, 4, Serialized)
+ //
+ // Name: WRGP [GPIO Write]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
+ // Arg1 -> Value
+ // Return: Nothing
+ //
+ Method(WRGP, 2, Serialized)
+ {
+ Store(Arg0, Local0)
+ Store(Arg0, Local1)
+ And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
+ ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
+ If (LEqual(And(Local0, 0xFF), 1))
+ {
+ // PCH
+ \_SB.CGWR(Local1, Arg1)
+ }
+ } // End of Method(WRGP, 2, Serialized)
+
+ //
+ // Name: RDGP [GPIO Read]
+ // Description: Function to write into GPIO
+ // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
+ // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indicator}
+ // Return: Value
+ //
+ Method(RDGP, 2, Serialized)
+ {
+ Store(1, Local7)
+ Store(Arg0, Local0)
+ Store(Arg0, Local1)
+ And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
+ ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
+ If (LEqual(And(Local0, 0xFF), 1))
+ {
+ // PCH
+ Store(\_SB.CGRD(Local1, Arg1), Local7)
+ }
+ Return(Local7)
+ } // End of Method(RDGP, 2, Serialized)
+
+} // End of Scope(\_SB)
+
+Scope(\_SB)
+{
+ // Asserts/De-asserts TBT force power
+ Method(TBFP, 2)
+ {
+ If(Arg0)
+ {
+ // Implementation dependent way to assert TBT force power
+ If(LEqual(Arg1, 1)) {
+ CGWR(FPG0, FP0L)
+ }
+ Else {
+ CGWR(FPG1, FP1L)
+ }
+ }
+ Else
+ {
+ // Implementation dependent way to de-assert TBT force power
+ If(LEqual(Arg1, 1)) {
+ CGWR(FPG0, LNot(FP0L))
+ }
+ Else {
+ CGWR(FPG1, LNot(FP1L))
+ }
+ }
+ }
+
+ // WMI ACPI device to control TBT force power
+ Device(WMTF)
+ {
+ // pnp0c14 is pnp id assigned to WMI mapper
+ Name(_HID, "PNP0C14")
+ Name(_UID, "TBFP")
+
+ Name(_WDG, Buffer() {
+ // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
+ 0x48, 0xFD, 0xCC, 0x86,
+ 0x5E, 0x20,
+ 0x77, 0x4A,
+ 0x9C, 0x48,
+ 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
+ 84, 70, // Object Id (TF)
+ 1, // Instance Count
+ 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
+ })
+
+ // Set TBT force power
+ // Arg2 is force power value
+ Method(WMTF, 3)
+ {
+ CreateByteField(Arg2,0,FP)
+
+ If(FP)
+ {
+ TBFP(1, 1)
+ }
+ Else
+ {
+ TBFP(0, 1)
+ }
+ }
+ }
+} // End of Scope(\_SB)
+
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1))))
+{
+ Scope(\_SB.PCI0.RP01)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP01)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2))))
+{
+ Scope(\_SB.PCI0.RP02)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP02)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3))))
+{
+ Scope(\_SB.PCI0.RP03)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP03)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4))))
+{
+ Scope(\_SB.PCI0.RP04)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP04)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5))))
+{
+ Scope(\_SB.PCI0.RP05)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP05)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6))))
+{
+ Scope(\_SB.PCI0.RP06)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP06)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7))))
+{
+ Scope(\_SB.PCI0.RP07)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP07)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8))))
+{
+ Scope(\_SB.PCI0.RP08)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP08)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9))))
+{
+ Scope(\_SB.PCI0.RP09)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP09)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10))))
+{
+ Scope(\_SB.PCI0.RP10)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP10)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11))))
+{
+ Scope(\_SB.PCI0.RP11)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP11)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12))))
+{
+ Scope(\_SB.PCI0.RP12)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP12)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13))))
+{
+ Scope(\_SB.PCI0.RP13)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP13)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14))))
+{
+ Scope(\_SB.PCI0.RP14)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP14)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15))))
+{
+ Scope(\_SB.PCI0.RP15)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP15)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16))))
+{
+ Scope(\_SB.PCI0.RP16)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP16)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17))))
+{
+ Scope(\_SB.PCI0.RP17)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP17)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18))))
+{
+ Scope(\_SB.PCI0.RP18)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP18)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19))))
+{
+ Scope(\_SB.PCI0.RP19)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP19)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20))))
+{
+ Scope(\_SB.PCI0.RP20)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.RP20)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21))))
+{
+ Scope(\_SB.PCI0.PEG0)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG0)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22))))
+{
+ Scope(\_SB.PCI0.PEG1)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG1)
+}
+
+If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23))))
+{
+ Scope(\_SB.PCI0.PEG2)
+ {
+ Device(HRUS)// Host router Upstream port
+ {
+ Name(_ADR, 0x00000000)
+
+ Method(_RMV)
+ {
+ Return(TARS)
+ } // end _RMV
+ }
+ }//End of Scope(\_SB.PCI0.PEG2)
+}
+
+Scope(\_SB)
+{
+ //
+ // Name: PERB
+ // Description: Function to read a Byte from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Byte data read from PCIE-MMIO
+ //
+ Method(PERB,5,Serialized)
+ {
+ ADBG("PERB")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 1)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 8
+ }
+
+ Return(TEMP)
+ } // End of Method(PERB,5,Serialized)
+
+ //
+ // Name: PEWB
+ // Description: Function to write a Byte into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWB,6,Serialized)
+ {
+ ADBG("PEWB")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 1)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 8
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWB,6,Serialized)
+
+ //
+ // Name: PERW
+ // Description: Function to read a Word from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Word data read from PCIE-MMIO
+ //
+ Method(PERW,5,Serialized)
+ {
+ ADBG("PERW")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 2)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 16
+ }
+
+ Return(TEMP)
+ } // End of Method(PERW,5,Serialized)
+
+ //
+ // Name: PEWW
+ // Description: Function to write a Word into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWW,6,Serialized)
+ {
+ ADBG("PEWW")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 2)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 16
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWW,6,Serialized)
+
+ //
+ // Name: PERD
+ // Description: Function to read a Dword from PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Return: Dword data read from PCIE-MMIO
+ //
+ Method(PERD,5,Serialized)
+ {
+ ADBG("PERD")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 4)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 32
+ }
+
+ Return(TEMP)
+ } // End of Method(PERD,5,Serialized)
+
+ //
+ // Name: PEWD
+ // Description: Function to write a Dword into PCIE-MMIO
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Register offset
+ // Arg5 -> Data
+ // Return: Nothing
+ //
+ Method(PEWD,6,Serialized)
+ {
+ ADBG("PEWD")
+
+ Store(Arg0, Local7)
+ Or(Local7, ShiftLeft(Arg1, 20), Local7)
+ Or(Local7, ShiftLeft(Arg2, 15), Local7)
+ Or(Local7, ShiftLeft(Arg3, 12), Local7)
+ Or(Local7, Arg4, Local7)
+
+ OperationRegion(PCI0, SystemMemory, Local7, 4)
+ Field(PCI0, ByteAcc,NoLock,Preserve)
+ {
+ TEMP, 32
+ }
+
+ Store(Arg5,TEMP)
+ } // End of Method(PEWD,6,Serialized)
+
+ //
+ // Name: STDC
+ // Description: Function to get Standard Capability Register Offset
+ // Input: Arg0 -> PCIE base address
+ // Arg1 -> Bus
+ // Arg2 -> Device
+ // Arg3 -> Function
+ // Arg4 -> Capability ID
+ // Return: Capability Register Offset data
+ //
+ Method(STDC,5,Serialized)
+ {
+ ADBG("STDC")
+
+ //Check for Referenced device is present or not
+ Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID register
+ If(LEqual(Local7, 0xFFFF))
+ {
+ ADBG("Referenced device is not present")
+ Return(0)
+ }
+
+ Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status register
+ If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List
+ {
+ //No Capabilities linked list is available
+ ADBG("No Capabilities linked list is available")
+ Return(0)
+ }
+
+ //Local1 is for storing CapabilityID
+ //Local2 is for storing CapabilityPtr
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr
+
+ While(1)
+ {
+ And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned
+
+ If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the last capability in the list
+ {
+ ADBG("Capability ID is not found")
+ Return(0)
+ }
+
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID
+
+ If(LEqual(Arg4, Local1)) //CapabilityID match
+ {
+ ADBG("Capability ID is found")
+ ADBG("Capability Offset : ")
+ ADBG(Local2)
+ Return(Local2)
+ }
+ Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //CapabilityPtr
+ Return(0)
+ }
+ } // End of Method(STDC,5,Serialized)
+
+} // End Scope(\_SB)
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
new file mode 100644
index 0000000000..ef6201de94
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
@@ -0,0 +1,228 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/TbtCommonLib.h>
+#include <Library/DxeTbtPolicyLib.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Protocol/TbtNvsArea.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/PcdLib.h>
+#include <Library/AslUpdateLib.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA_PROTOCOL mTbtNvsAreaProtocol;
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob = NULL;
+
+/**
+ TBT NVS Area Initialize
+
+**/
+
+VOID
+TbtNvsAreaInit (
+ IN VOID **mTbtNvsAreaPtr
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
+ DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "TbtNvsAreaInit Start\n"));
+ Status = gBS->LocateProtocol (
+ &gDxeTbtPolicyProtocolGuid,
+ NULL,
+ (VOID **) &DxeTbtConfig
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Pages = EFI_SIZE_TO_PAGES (sizeof (TBT_NVS_AREA));
+ Address = 0xffffffff; // allocate address below 4G.
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ *mTbtNvsAreaPtr = (VOID *) (UINTN) Address;
+ SetMem (*mTbtNvsAreaPtr, sizeof (TBT_NVS_AREA), 0);
+
+ //
+ // TBTNvsAreaProtocol default value init here
+ //
+ TbtNvsAreaProtocol = (TBT_NVS_AREA_PROTOCOL *) &Address;
+
+ //
+ // Initialize default values
+ //
+ TbtNvsAreaProtocol->Area->WAKFinished = 0;
+ TbtNvsAreaProtocol->Area->DiscreteTbtSupport = ((gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn == 1 ) ? TRUE : FALSE);
+ TbtNvsAreaProtocol->Area->TbtAcpiRemovalSupport = 0;
+ TbtNvsAreaProtocol->Area->TbtGpioFilter = (UINT8) DxeTbtConfig->TbtCommonConfig.Gpio5Filter;
+// TbtNvsAreaProtocol->Area->TrOsup = (UINT8) DxeTbtConfig->TbtCommonConfig.TrA0OsupWa;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrEn = gTbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr;
+ TbtNvsAreaProtocol->Area->TbtAspm = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtAspm;
+// TbtNvsAreaProtocol->Area->TbtL1SubStates = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtL1SubStates;
+ TbtNvsAreaProtocol->Area->TbtSetClkReq = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtSetClkReq;
+ TbtNvsAreaProtocol->Area->TbtLtr = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtLtr;
+// TbtNvsAreaProtocol->Area->TbtPtm = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtPtm;
+ TbtNvsAreaProtocol->Area->TbtWakeupSupport = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport;
+ TbtNvsAreaProtocol->Area->TbtAcDcSwitch = (UINT8) DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch;
+ TbtNvsAreaProtocol->Area->Rtd3TbtSupport = (UINT8) DxeTbtConfig->TbtCommonConfig.Rtd3Tbt; // TBT RTD3 Enable.
+ TbtNvsAreaProtocol->Area->Rtd3TbtOffDelay = (UINT16) DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay; // TBT RTD3 Off delay in ms.
+ TbtNvsAreaProtocol->Area->Rtd3TbtClkReq = (UINT8) DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq; // TBT RTD3 ClkReq Mask Enable.
+ TbtNvsAreaProtocol->Area->Rtd3TbtClkReqDelay = (UINT16) DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay; // TBT RTD3 ClkReq mask delay in ms.
+ TbtNvsAreaProtocol->Area->TbtWin10Support = (UINT8) DxeTbtConfig->TbtCommonConfig.Win10Support; // TBT FW Execution Mode
+
+ //
+ // DTBT Controller 1
+ //
+ TbtNvsAreaProtocol->Area->DTbtControllerEn0 = gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn;
+ TbtNvsAreaProtocol->Area->RootportSelected0 = gTbtInfoHob-> DTbtControllerConfig.PcieRpNumber;
+ TbtNvsAreaProtocol->Area->RootportSelected0Type = gTbtInfoHob-> DTbtControllerConfig.Type;
+ TbtNvsAreaProtocol->Area->RootportEnabled0 = gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrGpioNo0 = gTbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtFrcPwrGpioLevel0 = gTbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel;
+ TbtNvsAreaProtocol->Area->TbtCioPlugEventGpioNo0 = gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtPcieRstGpioNo0 = gTbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad;
+ TbtNvsAreaProtocol->Area->TbtPcieRstGpioLevel0 = gTbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel;
+
+ TbtNvsAreaProtocol->Area->TBtCommonGpioSupport = gTbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration;
+
+ DEBUG ((DEBUG_INFO, "TbtNvsAreaInit End\n"));
+}
+
+/**
+ This function gets registered as a callback to patch TBT ASL code
+
+ @param[in] Event - A pointer to the Event that triggered the callback.
+ @param[in] Context - A pointer to private data registered with the callback function.
+ can we put this also in read me
+**/
+VOID
+EFIAPI
+TbtAcpiEndOfDxeCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Address;
+ UINT16 Length;
+ UINT32 Signature;
+
+ Status = InitializeAslUpdateLib ();
+ ASSERT_EFI_ERROR (Status);
+
+ Address = (UINT32) (UINTN) mTbtNvsAreaProtocol.Area;
+ Length = (UINT16) sizeof (TBT_NVS_AREA);
+ DEBUG ((DEBUG_INFO, "Patch TBT NvsAreaAddress: TBT NVS Address %x Length %x\n", Address, Length));
+ Status = UpdateNameAslCode (SIGNATURE_32 ('T','N','V','B'), &Address, sizeof (Address));
+ ASSERT_EFI_ERROR (Status);
+ Status = UpdateNameAslCode (SIGNATURE_32 ('T','N','V','L'), &Length, sizeof (Length));
+ ASSERT_EFI_ERROR (Status);
+
+ if (gTbtInfoHob != NULL) {
+ if (gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn == 1) {
+ if (gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting == TRUE) {
+ DEBUG ((DEBUG_INFO, "Patch ATBT Method Name\n"));
+ Signature = gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature;
+ Status = UpdateNameAslCode (SIGNATURE_32 ('A','T','B','T'), &Signature, sizeof (Signature));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ }
+
+ return;
+}
+
+/**
+ Initialize Thunderbolt(TM) SSDT ACPI tables
+
+ @retval EFI_SUCCESS ACPI tables are initialized successfully
+ @retval EFI_NOT_FOUND ACPI tables not found
+**/
+
+EFI_STATUS
+EFIAPI
+TbtDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ // EFI_EVENT EndOfDxeEvent;
+
+ DEBUG ((DEBUG_INFO, "TbtDxeEntryPoint \n"));
+
+ //
+ // Get TBT INFO HOB
+ //
+ gTbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+ if (gTbtInfoHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ InstallTbtPolicy (ImageHandle);
+ //
+ // Update DXE TBT Policy
+ //
+ UpdateTbtPolicyCallback ();
+
+ //
+ // Print DXE TBT Policy
+ //
+ TbtPrintDxePolicyConfig ();
+
+ //
+ // Initialize Tbt Nvs Area
+ //
+ TbtNvsAreaInit ((VOID **) &mTbtNvsAreaProtocol.Area);
+
+
+ //
+ // [ACPI] Thunderbolt ACPI table
+ //
+
+
+ Handle = NULL;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gTbtNvsAreaProtocolGuid,
+ &mTbtNvsAreaProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register an end of DXE event for TBT ACPI to do some patch can be put as description
+ //
+ /**
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ TbtAcpiEndOfDxeCallback,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+**/
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
new file mode 100644
index 0000000000..75da20fcb1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
@@ -0,0 +1,51 @@
+## @file
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = TbtDxe
+ FILE_GUID = 19C9762C-3A88-41B0-906F-8C4C2895A887
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = TbtDxeEntryPoint
+
+[LibraryClasses]
+ DebugLib
+ BaseMemoryLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiDriverEntryPoint
+ HobLib
+ UefiLib
+ TbtCommonLib
+ DxeTbtPolicyLib
+ AslUpdateLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ TbtDxe.c
+
+[Protocols]
+ gTbtNvsAreaProtocolGuid ## CONSUMES
+ gDxeTbtPolicyProtocolGuid
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Depex]
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiVariableArchProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
new file mode 100644
index 0000000000..5aaf600795
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
@@ -0,0 +1,211 @@
+/** @file
+ Source code file for TBT Init PEI module
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiTbtPolicyLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/PeiTbtPolicy.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <TbtBoardInfo.h>
+#include <Private/Library/PeiDTbtInitLib.h>
+/*
+/**
+ This function Update and Print PEI TBT Policy after TbtPolicyBoardInitDone
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+
+/**
+ This function pass PEI TBT Policy to Hob at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+
+EFI_STATUS
+EFIAPI
+PassTbtPolicyToHob (
+VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ TBT_INFO_HOB *TbtInfoHob;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "PassTbtPolicyToHob\n"));
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+ if (BootMode == BOOT_ON_S3_RESUME ) {
+ return EFI_SUCCESS;
+ }
+
+ Status = PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Create HOB for TBT Data
+ //
+ Status = PeiServicesCreateHob (
+ EFI_HOB_TYPE_GUID_EXTENSION,
+ sizeof (TBT_INFO_HOB),
+ (VOID **) &TbtInfoHob
+ );
+ DEBUG ((DEBUG_INFO, "TbtInfoHob Created \n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize the TBT INFO HOB data.
+ //
+ TbtInfoHob->EfiHobGuidType.Name = gTbtInfoHobGuid;
+
+ //
+ // Update DTBT Policy
+ //
+ TbtInfoHob-> DTbtControllerConfig.DTbtControllerEn = PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn;
+ TbtInfoHob-> DTbtControllerConfig.Type = PeiTbtConfig-> DTbtControllerConfig.Type;
+ TbtInfoHob-> DTbtControllerConfig.PcieRpNumber = PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber;
+ TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad = PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel = PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad = PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature;
+ TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting = PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting;
+ TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad = PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad;
+ TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel = PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel;
+
+ TbtInfoHob->DTbtCommonConfig.TbtBootOn = PeiTbtConfig->DTbtCommonConfig.TbtBootOn;
+ TbtInfoHob->DTbtCommonConfig.TbtUsbOn = PeiTbtConfig->DTbtCommonConfig.TbtUsbOn;
+ TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr = PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr;
+ TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwrDly = PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly;
+ TbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration = PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration;
+ TbtInfoHob->DTbtCommonConfig.PcieRstSupport = PeiTbtConfig->DTbtCommonConfig.PcieRstSupport;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function handles TbtInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+
+EFI_STATUS
+EFIAPI
+TbtInitEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN DTbtExisted;
+ PEI_TBT_POLICY *PeiTbtConfig;
+
+ DEBUG ((DEBUG_INFO, "TbtInitEndOfPei Entry\n"));
+
+ Status = EFI_SUCCESS;
+ PeiTbtConfig = NULL;
+ DTbtExisted = FALSE;
+
+ Status = PeiServicesLocatePpi (
+ &gPeiTbtPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PeiTbtConfig
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
+ }
+ ASSERT_EFI_ERROR (Status);
+
+ if (PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn == 1) {
+ DTbtExisted = TRUE;
+ }
+
+ if (DTbtExisted == TRUE) {
+ //
+ // Call Init function
+ //
+ Status = TbtInit ();
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ TBT Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+TbtInitEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "TBT PEI EntryPoint\n"));
+
+ //
+ // Install PEI TBT Policy
+ //
+ Status = InstallPeiTbtPolicy ();
+ ASSERT_EFI_ERROR (Status);
+
+
+ UpdatePeiTbtPolicy ();
+
+ TbtPrintPeiPolicyConfig ();
+ //
+ // Performing PassTbtPolicyToHob and TbtInitEndOfPei
+ //
+ Status = PassTbtPolicyToHob ();
+
+ Status = TbtInitEndOfPei ();
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
new file mode 100644
index 0000000000..c9a09e1095
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
@@ -0,0 +1,47 @@
+## @file
+# Component information file for the TBT Init PEI module.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiTbtInit
+ FILE_GUID = 90BF2BFB-F998-4cbc-AD72-008D4D047A4B
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = TbtInitEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ HobLib
+ PeiServicesLib
+ PeiTbtPolicyLib
+ PeiDTbtInitLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiTbtInit.c
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gPeiTbtPolicyBoardInitDonePpiGuid ## CONSUMES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c
new file mode 100644
index 0000000000..f80215b4b5
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c
@@ -0,0 +1,1609 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "TbtSmiHandler.h"
+#include <Library/IoLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/SmmVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#define MEM_PER_SLOT (DEF_RES_MEM_PER_DEV << 4)
+#define PMEM_PER_SLOT (DEF_RES_PMEM_PER_DEV << 4)
+#define IO_PER_SLOT (DEF_RES_IO_PER_DEV << 2)
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN gDeviceBaseAddress;
+//
+//US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0)
+//
+GLOBAL_REMOVE_IF_UNREFERENCED BRDG_CONFIG HrConfigs[MAX_CFG_PORTS];
+
+extern UINT8 gCurrentDiscreteTbtRootPort;
+extern UINT8 gCurrentDiscreteTbtRootPortType;
+
+BOOLEAN isLegacyDevice = FALSE;
+STATIC UINT8 TbtSegment = 0;
+
+STATIC
+VOID
+PortInfoInit (
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ PortInfo->BusNumLimit = 4;
+}
+
+STATIC
+VOID
+UnsetVesc (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun
+ )
+{
+ UINT8 Dbus;
+ UINT32 Data32;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+
+ //
+ // Check for abcence of DS bridge
+ //
+ if(0xFFFF == PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET)) {
+ return;
+ }
+
+ //
+ // Unset vesc_reg2[23] bit (to have an option to access below DS)
+ //
+ Data32 = PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
+ Data32 &= 0xFF7FFFFF;
+ PciSegmentWrite32(gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
+ //
+ // Go to Device behind DS
+ //
+ Dbus = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ DEBUG((DEBUG_INFO, "Dbus = %d\n",Dbus));
+ //
+ // Check if there is something behind this Downstream Port (Up or Ep)
+ // If there nothing behind Downstream Port Set vesc_reg2[23] bit -> this will flush all future MemWr
+ //
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, 0x00, 0);
+ if(0xFFFF == PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET))
+ {
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ Data32 = PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2);
+ Data32 |= 0x00800000;
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32);
+ }
+}// Unset_VESC_REG2
+
+STATIC
+UINT16
+MemPerSlot (
+ IN UINT16 CurrentUsage
+ )
+{
+ if (CurrentUsage == 0) {
+ return 0;
+ }
+
+ if (CurrentUsage <= 16) {
+ return 16;
+ }
+
+ if (CurrentUsage <= 64) {
+ return 64;
+ }
+
+ if (CurrentUsage <= 128) {
+ return 128;
+ }
+
+ if (CurrentUsage <= 256) {
+ return 256;
+ }
+
+ if (CurrentUsage <= 512) {
+ return 512;
+ }
+
+ if (CurrentUsage <= 1024) {
+ return 1024;
+ }
+
+ return CurrentUsage;
+} // MemPerSlot
+
+STATIC
+UINT64
+PMemPerSlot (
+ IN UINT64 CurrentUsage
+ )
+{
+ if (CurrentUsage == 0) {
+ return 0;
+ }
+
+ if (CurrentUsage <= 1024ULL) {
+ return 1024ULL;
+ }
+
+ if (CurrentUsage <= 4096ULL) {
+ return 4096ULL;
+ }
+
+ return CurrentUsage;
+} // PMemPerSlot
+
+STATIC
+VOID
+SetPhyPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 SubBus,
+ IN INT8 Depth,
+ IN PORT_INFO *CurrentPi,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Cmd;
+ UINT16 DeltaMem;
+ UINT64 DeltaPMem;
+
+ Cmd = CMD_BUS_MASTER;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x00, 0);
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, SubBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+
+ DeltaMem = PortInfo->MemBase - CurrentPi->MemBase;
+ if (isLegacyDevice) {
+ if (Depth >= 0 && (DeltaMem < MEM_PER_SLOT)) {
+ PortInfo->MemBase += MEM_PER_SLOT - DeltaMem;
+ }
+ } else {
+ if (DeltaMem < MemPerSlot (DeltaMem)) {
+ PortInfo->MemBase += MemPerSlot (DeltaMem) - DeltaMem;
+ }
+ }
+
+ if (PortInfo->MemBase > CurrentPi->MemBase && (PortInfo->MemBase - 0x10) <= PortInfo->MemLimit) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), CurrentPi->MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), PortInfo->MemBase - 0x10);
+ Cmd |= CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), DISBL_MEM32_REG20);
+ PortInfo->MemBase = CurrentPi->MemBase;
+ }
+
+ DeltaPMem = PortInfo->PMemBase64 - CurrentPi->PMemBase64;
+ if (isLegacyDevice) {
+ if ((Depth >= 0) && ((UINTN)DeltaPMem < (UINTN)PMEM_PER_SLOT)) {
+ PortInfo->PMemBase64 += PMEM_PER_SLOT - DeltaPMem;
+ }
+ } else {
+ if (DeltaPMem < PMemPerSlot (DeltaPMem)) {
+ PortInfo->PMemBase64 += PMemPerSlot (DeltaPMem) - DeltaPMem;
+ }
+ }
+
+ if (PortInfo->PMemBase64 > CurrentPi->PMemBase64 && (PortInfo->PMemBase64 - 0x10) <= PortInfo->PMemLimit64) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), (UINT16) (CurrentPi->PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit), (UINT16) ((PortInfo->PMemBase64 - 0x10) & 0xFFFF));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), (UINT32) (CurrentPi->PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32), (UINT32) ((PortInfo->PMemBase64 - 0x10) >> 16));
+ Cmd |= CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32), 0);
+ PortInfo->PMemBase64 = CurrentPi->PMemBase64;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CACHE_LINE_SIZE);
+} // SetPhyPortResources
+
+STATIC
+UINT32
+SaveSetGetRestoreBar (
+ IN UINTN Bar
+ )
+{
+ UINT32 BarReq;
+ UINT32 OrigBar;
+
+ OrigBar = PciSegmentRead32(Bar); // Save BAR
+ PciSegmentWrite32(Bar, 0xFFFFFFFF); // Set BAR
+ BarReq = PciSegmentRead32(Bar); // Get BAR
+ PciSegmentWrite32(Bar, OrigBar); // Restore BAR
+
+ return BarReq;
+} // SaveSetGetRestoreBar
+
+STATIC
+VOID
+SetIoBar (
+ IN UINTN BAR,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT IO_REGS *IoReg
+ )
+{
+ UINT16 Alignment;
+ UINT16 Size;
+ UINT16 NewBase;
+
+ Alignment = ~(BarReq & 0xFFFC);
+ Size = Alignment + 1;
+
+ if (IoReg->Base > IoReg->Limit || !Size) {
+ return ;
+
+ }
+
+ NewBase = BAR_ALIGN (IoReg->Base, Alignment);
+ if (NewBase > IoReg->Limit || NewBase + Size - 1 > IoReg->Limit) {
+ return ;
+
+ }
+ PciSegmentWrite16(BAR, NewBase);
+ IoReg->Base = NewBase + Size; // Advance to new position
+ *Cmd |= CMD_BM_IO; // Set Io Space Enable
+} // SetIoBar
+
+STATIC
+VOID
+SetMemBar (
+ IN UINTN BAR,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT MEM_REGS *MemReg
+ )
+{
+ UINT32 Alignment;
+ UINT32 Size;
+ UINT32 NewBase;
+
+ Alignment = ~(BarReq & 0xFFFFFFF0);
+ Size = Alignment + 1;
+
+ if (MemReg->Base > MemReg->Limit || !Size) {
+ return ;
+
+ }
+
+ NewBase = BAR_ALIGN (MemReg->Base, Alignment);
+ if (NewBase > MemReg->Limit || NewBase + Size - 1 > MemReg->Limit) {
+ return ;
+
+ }
+
+ PciSegmentWrite32(BAR, NewBase);
+ MemReg->Base = NewBase + Size; // Advance to new position
+ *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
+} // SetMemBar
+
+STATIC
+VOID
+SetPMem64Bar (
+ IN UINTN BAR,
+ IN BOOLEAN IsMaxBar,
+ IN UINT32 BarReq,
+ IN OUT UINT8 *Cmd,
+ IN OUT PMEM_REGS *MemReg
+ )
+{
+ UINT32 Alignment;
+ UINT32 Size;
+ UINT64 NewBase;
+
+ Alignment = ~(BarReq & 0xFFFFFFF0);
+ Size = Alignment + 1;
+
+ if (MemReg->Base64 > MemReg->Limit64 || !Size) {
+ return ;
+ }
+
+ NewBase = BAR_ALIGN (MemReg->Base64, Alignment);
+ if (NewBase > MemReg->Limit64 || NewBase + Size - 1 > MemReg->Limit64) {
+ return ;
+ }
+ PciSegmentWrite32(BAR, (UINT32)(NewBase & 0xFFFFFFFF));
+ if (!IsMaxBar) {
+ BAR++;
+ PciSegmentWrite32(BAR, (UINT32)(NewBase >> 32));
+ }
+ MemReg->Base64 = NewBase + Size; // Advance to new position
+ *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
+} // SetPMem64Bar
+
+STATIC
+VOID
+SetDevResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 MaxFun, // PCI_MAX_FUNC for devices, 1 for bridge
+ IN UINT8 MaxBar, // PCI_BAR5 for devices, PCI_BAR1 for bridge
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Fun;
+ UINT8 Reg;
+ UINT32 BarReq;
+ IO_REGS Io;
+ MEM_REGS Mem;
+ PMEM_REGS PMem;
+ UINT8 Cmd;
+
+ Io.Base = PortInfo->IoBase << 8;
+ Io.Limit = (PortInfo->IoLimit << 8) | 0xFF;
+ Mem.Base = PortInfo->MemBase << 16;
+ Mem.Limit = (PortInfo->MemLimit << 16) | 0xFFFF;
+ PMem.Base64 = PortInfo->PMemBase64 << 16;
+ PMem.Limit64 = (PortInfo->PMemLimit64 << 16) | 0xFFFF;
+
+ for (Fun = 0; Fun < MaxFun; ++Fun) {
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MASTER);
+ Cmd = PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET);
+ if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET)) {
+ continue;
+
+ }
+
+ for (Reg = PCI_BASE_ADDRESSREG_OFFSET; Reg <= MaxBar; Reg += 4) {
+ BarReq = SaveSetGetRestoreBar(gDeviceBaseAddress + Reg); // Perform BAR sizing
+
+ if (BarReq & BIT0) {
+ //
+ // I/O BAR
+ //
+ SetIoBar (
+ (gDeviceBaseAddress + Reg),
+ BarReq,
+ &Cmd,
+ &Io
+ );
+ continue;
+ }
+
+ if (BarReq & BIT3) {
+ //
+ // P-Memory BAR
+ //
+ SetPMem64Bar ((gDeviceBaseAddress + Reg), MaxBar == Reg, BarReq, &Cmd, &PMem);
+ } else {
+ SetMemBar ((gDeviceBaseAddress + Reg), BarReq, &Cmd, &Mem);
+ }
+
+ if (BIT2 == (BarReq & (BIT2 | BIT1))) {
+ //
+ // Base address is 64 bits wide
+ //
+ Reg += 4;
+ if (!(BarReq & BIT3)) {
+ //
+ // 64-bit memory bar
+ //
+ PciSegmentWrite32 (gDeviceBaseAddress + Reg, 0);
+ }
+ }
+ }
+
+ if (Cmd & BIT1) {
+ //
+ // If device uses I/O and MEM mapping use only MEM mepping
+ //
+ Cmd &= ~BIT0;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CACHE_LINE_SIZE);
+ }
+ //
+ // Update PortInfo if any changes
+ //
+ if (Io.Base > ((UINT32) PortInfo->IoBase << 8)) {
+ PortInfo->IoBase = (UINT8) (BAR_ALIGN (Io.Base, 0xFFF) >> 8);
+ }
+
+ if (Mem.Base > ((UINT32) PortInfo->MemBase << 16)) {
+ PortInfo->MemBase = (UINT16) (BAR_ALIGN (Mem.Base, 0xFFFFF) >> 16);
+ }
+
+ if (PMem.Base64 > (PortInfo->PMemBase64 << 16)) {
+ PortInfo->PMemBase64 = (BAR_ALIGN (PMem.Base64, 0xFFFFF) >> 16);
+ }
+} // SetDevResources
+
+STATIC
+VOID
+InitARHRConfigs(
+ IN HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG* HrResConf
+)
+{
+ UINT8 i,j;
+
+ //
+ // DS port for USB device
+ //
+ HrConfigs[AR_DS_PORT2].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[AR_DS_PORT2].DevId.Dev = 2;
+ HrConfigs[AR_DS_PORT2].DevId.Fun = 0;
+ HrConfigs[AR_DS_PORT2].PBus = HrConfigs[AR_DS_PORT2].DevId.Bus;
+ HrConfigs[AR_DS_PORT2].SBus = HrConfigs[AR_DS_PORT2].PBus + 1;
+ HrConfigs[AR_DS_PORT2].SubBus = HrConfigs[AR_DS_PORT2].PBus + 1;
+ //
+ // CIO port
+ //
+ HrConfigs[AR_DS_PORT1].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[AR_DS_PORT1].DevId.Dev = 1;
+ HrConfigs[AR_DS_PORT1].DevId.Fun = 0;
+ HrConfigs[AR_DS_PORT1].PBus = HrConfigs[AR_DS_PORT1].DevId.Bus;
+ HrConfigs[AR_DS_PORT1].SBus = HrConfigs[HR_DS_PORT0].SubBus + 1;
+ HrConfigs[AR_DS_PORT1].SubBus = BusNumLimit;
+
+ switch(Hr_Config->DeviceId)
+ {
+ //
+ // HR with 1 DS and 1 USB
+ //
+ case AR_HR_2C:
+ case AR_HR_LP:
+ case AR_HR_C0_2C:
+ case TR_HR_2C:
+ Hr_Config->MinDSNumber = HrConfigs[AR_DS_PORT1].DevId.Dev;
+ Hr_Config->MaxDSNumber = HrConfigs[AR_DS_PORT2].DevId.Dev;
+ Hr_Config->BridgeLoops = 4;
+ break;
+ //
+ // HR with 2 DS and 1 USB
+ //
+ case AR_HR_4C:
+ case TR_HR_4C:
+ case AR_HR_C0_4C:
+ Hr_Config->MinDSNumber = 1;
+ Hr_Config->MaxDSNumber = 4;
+ Hr_Config->BridgeLoops = 6;
+ for(j = 2, i = Hr_Config->MinDSNumber; j < count(HrConfigs) && i <= Hr_Config->MaxDSNumber; ++j, ++i)
+ {
+ HrConfigs[j].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[j].DevId.Dev = i;
+ HrConfigs[j].DevId.Fun = 0;
+ HrConfigs[j].PBus = HrConfigs[j].DevId.Bus;
+ HrConfigs[j].Res.Cls = DEF_CACHE_LINE_SIZE;
+ }
+ break;
+ }
+}//InitARHRConfigs
+
+
+STATIC
+VOID
+InitCommonHRConfigs (
+ IN HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG *HrResConf
+ )
+{
+ UINT8 i;
+
+ UINT8 j;
+ for(i = 0; i < count(HrConfigs); ++i) {
+ HrConfigs[i].IsDSBridge = TRUE;
+ }
+ //
+ // US(HRBus:0:0)
+ //
+ HrConfigs[HR_US_PORT].DevId.Bus = Hr_Config->HRBus;
+ HrConfigs[HR_US_PORT].DevId.Dev = 0;
+ HrConfigs[HR_US_PORT].DevId.Fun = 0;
+ HrConfigs[HR_US_PORT].Res = *HrResConf;
+ HrConfigs[HR_US_PORT].Res.IoBase = 0xF1;
+ HrConfigs[HR_US_PORT].Res.IoLimit = 0x01;
+ HrConfigs[HR_US_PORT].PBus = HrConfigs[HR_US_PORT].DevId.Bus;
+ HrConfigs[HR_US_PORT].SBus = HrConfigs[HR_US_PORT].PBus + 1;
+ HrConfigs[HR_US_PORT].SubBus = BusNumLimit;
+ HrConfigs[HR_US_PORT].IsDSBridge = FALSE;
+
+ //
+ // HIA resides here
+ //
+ HrConfigs[HR_DS_PORT0].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[HR_DS_PORT0].DevId.Dev = 0;
+ HrConfigs[HR_DS_PORT0].DevId.Fun = 0;
+ HrConfigs[HR_DS_PORT0].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[HR_DS_PORT0].Res.MemBase = HrResConf->MemLimit;
+ HrConfigs[HR_DS_PORT0].Res.MemLimit = HrResConf->MemLimit;
+ HrResConf->MemLimit -= 0x10; //This 1 MB chunk will be used by HIA
+ HrConfigs[HR_DS_PORT0].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[HR_DS_PORT0].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[HR_DS_PORT0].PBus = HrConfigs[HR_DS_PORT0].DevId.Bus;
+ HrConfigs[HR_DS_PORT0].SBus = HrConfigs[HR_DS_PORT0].PBus + 1;
+ HrConfigs[HR_DS_PORT0].SubBus = HrConfigs[HR_DS_PORT0].PBus + 1;
+
+ switch (Hr_Config->DeviceId) {
+ //
+ // Alpine Ridge
+ //
+ case AR_HR_2C:
+ case AR_HR_C0_2C:
+ case AR_HR_LP:
+ case AR_HR_4C:
+ case AR_HR_C0_4C:
+ //
+ // Titan Ridge
+ //
+ case TR_HR_2C:
+ case TR_HR_4C:
+ InitARHRConfigs(Hr_Config, BusNumLimit, HrResConf);
+ break;
+
+ default:
+ //
+ // DS(HRBus+2:3-6:0)
+ //
+ Hr_Config->MinDSNumber = 3;
+ Hr_Config->MaxDSNumber = 6;
+ Hr_Config->BridgeLoops = count (HrConfigs);
+
+ for (j = 2, i = Hr_Config->MinDSNumber; j < count (HrConfigs) && i <= Hr_Config->MaxDSNumber; ++j, ++i) {
+ HrConfigs[j].DevId.Bus = HrConfigs[HR_US_PORT].DevId.Bus + 1;
+ HrConfigs[j].DevId.Dev = i;
+ HrConfigs[j].DevId.Fun = 0;
+ HrConfigs[j].PBus = HrConfigs[j].DevId.Bus;
+ HrConfigs[j].Res.Cls = DEF_CACHE_LINE_SIZE;
+ }
+ }
+} // InitCommonHRConfigs
+
+STATIC
+VOID
+InitHRDSPort_Disable (
+ IN UINT8 id,
+ IN OUT BRDG_CONFIG *BrdgConf
+ )
+{
+ HrConfigs[id].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[id].SBus = BrdgConf->SBus;
+ HrConfigs[id].SubBus = BrdgConf->SBus;
+
+ BrdgConf->SBus++;
+} // InitHRDSPort_Disable
+
+//AR only
+
+STATIC
+VOID
+InitARDSPort_1Port(
+ IN OUT BRDG_CONFIG* BrdgConf
+)
+{
+ UINT16 MemBase = BrdgConf->Res.MemBase & 0xFFF0;
+ UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
+ UINT8 BusRange = BrdgConf->SubBus - BrdgConf->PBus - 2;
+
+ HrConfigs[AR_DS_PORT1].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT1].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT1].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT1].Res.MemBase = MemBase;
+ HrConfigs[AR_DS_PORT1].Res.MemLimit = BrdgConf->Res.MemLimit - 1;
+ HrConfigs[AR_DS_PORT1].Res.PMemBase64 = PMemBase64;
+ HrConfigs[AR_DS_PORT1].Res.PMemLimit64 = BrdgConf->Res.PMemLimit64;
+ HrConfigs[AR_DS_PORT1].SBus = BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT1].SubBus = BrdgConf->SBus + BusRange;
+
+ BrdgConf->SBus = HrConfigs[AR_DS_PORT1].SubBus + 1;
+
+ HrConfigs[AR_DS_PORT2].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT2].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT2].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT2].Res.MemBase = BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT2].Res.MemLimit = BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT2].SBus = BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT2].SubBus = BrdgConf->SBus;
+
+ BrdgConf->SBus = HrConfigs[AR_DS_PORT2].SubBus + 1;
+}//InitARDSPort_1Port
+
+STATIC
+VOID
+InitARDSPort_2Port(
+ IN OUT BRDG_CONFIG* BrdgConf
+)
+{
+ UINT16 MemBase = BrdgConf->Res.MemBase & 0xFFF0;
+ UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
+ UINT8 BusRange = BrdgConf->SubBus - BrdgConf->PBus - 3;
+
+ // Busses are split between ports 1 and 4
+ BusRange /= 2;
+
+ HrConfigs[AR_DS_PORT1].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT1].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT1].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT1].Res.MemBase = MemBase;
+ HrConfigs[AR_DS_PORT1].Res.MemLimit = MemBase + 0x17F0 - 1;
+ HrConfigs[AR_DS_PORT1].Res.PMemBase64 = PMemBase64;
+ HrConfigs[AR_DS_PORT1].Res.PMemLimit64 = PMemBase64 + 0x2000 - 1;
+ HrConfigs[AR_DS_PORT1].SBus = BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT1].SubBus = BrdgConf->SBus + BusRange;
+
+ BrdgConf->SBus = HrConfigs[AR_DS_PORT1].SubBus + 1;
+
+ HrConfigs[AR_DS_PORT2].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT2].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT2].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT2].Res.MemBase = MemBase + 0x17F0;
+ HrConfigs[AR_DS_PORT2].Res.MemLimit = MemBase + 0x1800 - 1;
+ HrConfigs[AR_DS_PORT2].SBus = BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT2].SubBus = BrdgConf->SBus;
+
+ BrdgConf->SBus = HrConfigs[AR_DS_PORT2].SubBus + 1;
+
+
+ HrConfigs[AR_DS_PORT4].Res = NOT_IN_USE_BRIDGE;
+ HrConfigs[AR_DS_PORT4].Res.Cls = DEF_CACHE_LINE_SIZE;
+ HrConfigs[AR_DS_PORT4].Res.Cmd = CMD_BM_MEM;
+ HrConfigs[AR_DS_PORT4].Res.MemBase = MemBase + 0x1800;
+ HrConfigs[AR_DS_PORT4].Res.MemLimit = BrdgConf->Res.MemLimit;
+ HrConfigs[AR_DS_PORT4].Res.PMemBase64 = PMemBase64 + 0x2000;
+ HrConfigs[AR_DS_PORT4].Res.PMemLimit64 = BrdgConf->Res.PMemLimit64;
+ HrConfigs[AR_DS_PORT4].SBus = BrdgConf->SBus;
+ HrConfigs[AR_DS_PORT4].SubBus = BrdgConf->SubBus;
+
+ BrdgConf->SBus = HrConfigs[AR_DS_PORT4].SubBus + 1;
+}//InitARDSPort_2Port
+
+
+STATIC
+BOOLEAN
+CheckLimits (
+ IN BOOLEAN Is2PortDev,
+ IN BRDG_RES_CONFIG *HrResConf,
+ IN UINT8 BusRange
+ )
+{
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+
+ MemBase = HrResConf->MemBase & 0xFFF0;
+ MemLimit = HrResConf->MemLimit & 0xFFF0;
+ PMemBase64 = HrResConf->PMemBase64 & 0xFFF0;
+ PMemLimit64 = HrResConf->PMemLimit64 & 0xFFF0;
+ //
+ // Check memoty alignment
+ //
+ if (MemBase & 0x3FF) {
+ DEBUG((DEBUG_INFO, "M alig\n"));
+ return FALSE;
+ }
+
+ if (PMemBase64 & 0xFFF) {
+ DEBUG((DEBUG_INFO, "PM alig\n"));
+ return FALSE;
+ }
+
+ if (Is2PortDev) {
+ //
+ // Check mem size
+ //
+ if (MemLimit + 0x10 - MemBase < 0x2E00) {
+ DEBUG((DEBUG_INFO, "M size\n"));
+ return FALSE;
+ }
+ //
+ // Check P-mem size
+ //
+ if (PMemLimit64 + 0x10 - PMemBase64 < 0x4A00) {
+ DEBUG((DEBUG_INFO, "PM size\n"));
+ return FALSE;
+ }
+ //
+ // Check bus range
+ //
+ if (BusRange < 106) {
+ DEBUG((DEBUG_INFO, "Bus range\n"));
+ return FALSE;
+ }
+ } else {
+ //
+ // Check mem size
+ //
+ if (MemLimit + 0x10 - MemBase < 0x1600) {
+ DEBUG((DEBUG_INFO, "M size\n"));
+ return FALSE;
+ }
+ //
+ // Check P-mem size
+ //
+ if (PMemLimit64 + 0x10 - PMemBase64 < 0x2200) {
+ DEBUG((DEBUG_INFO, "PM size\n"));
+ return FALSE;
+ }
+ //
+ // Check bus range
+ //
+ if (BusRange < 56) {
+ DEBUG((DEBUG_INFO, "Bus range\n"));
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+} // CheckLimits
+
+STATIC
+BOOLEAN
+InitHRResConfigs (
+ IN OUT HR_CONFIG *Hr_Config,
+ IN UINT8 BusNumLimit,
+ IN OUT BRDG_RES_CONFIG*HrResConf
+ )
+{
+ BRDG_CONFIG BrdgConf = { { 0 } };
+
+ InitCommonHRConfigs (Hr_Config, BusNumLimit, HrResConf);
+ BrdgConf.PBus = Hr_Config->HRBus + 2;// Take into account busses
+ BrdgConf.SBus = Hr_Config->HRBus + 3;// for US and DS of HIA
+ BrdgConf.SubBus = BusNumLimit;
+ BrdgConf.Res = *HrResConf;
+ while (TRUE) {
+ switch (Hr_Config->DeviceId) {
+ case AR_HR_4C:
+ case TR_HR_4C:
+ case AR_HR_C0_4C:
+ //
+ // 2 Port host
+ //
+ if (CheckLimits (TRUE, HrResConf, BusNumLimit - Hr_Config->HRBus)) {
+
+
+ InitARDSPort_2Port(&BrdgConf);
+ DEBUG((DEBUG_INFO, "AR2\n"));
+
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ // AR only
+ case AR_HR_2C: // 1 port host
+ case AR_HR_C0_2C:
+ case AR_HR_LP:
+ case TR_HR_2C:
+ DEBUG((DEBUG_INFO, "AR1\n"));
+ InitARDSPort_1Port(&BrdgConf);
+ return TRUE;
+
+ default:
+ InitHRDSPort_Disable (HR_DS_PORT3, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT4, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT5, &BrdgConf);
+ InitHRDSPort_Disable (HR_DS_PORT6, &BrdgConf);
+ return FALSE;
+ }
+ }
+} // InitHRResConfigs
+
+STATIC
+BOOLEAN
+InitializeHostRouter (
+ OUT HR_CONFIG *Hr_Config,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 BusNumLimit;
+ BRDG_RES_CONFIG HrResConf = { 0 };
+ UINT8 i;
+ BOOLEAN Ret;
+
+ Ret = TRUE;
+
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, 0);
+ Hr_Config->HRBus = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment, Hr_Config->HRBus, 0x00, 0x00, 0);
+ Hr_Config->DeviceId = PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+ if (!(IsTbtHostRouter (Hr_Config->DeviceId))) {
+ return FALSE;
+ }
+ TbtSegment = (UINT8)RpSegment;
+
+ HrResConf.Cmd = CMD_BM_MEM;
+ HrResConf.Cls = DEF_CACHE_LINE_SIZE;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, 0);
+ HrResConf.IoBase = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
+ HrResConf.IoLimit = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
+ HrResConf.MemBase = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase));
+ HrResConf.MemLimit = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit));
+ HrResConf.PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase));
+ HrResConf.PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit));
+ HrResConf.PMemBase64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ HrResConf.PMemLimit64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+
+ Ret = InitHRResConfigs (Hr_Config, BusNumLimit, &HrResConf);
+
+ for (i = 0; i < Hr_Config->BridgeLoops; ++i) {
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ Bus = HrConfigs[i].DevId.Bus;
+ Dev = HrConfigs[i].DevId.Dev;
+ Fun = HrConfigs[i].DevId.Fun;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0);
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, HrConfigs[i].Res.Cls);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, HrConfigs[i].PBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, HrConfigs[i].SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, HrConfigs[i].SubBus);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), HrConfigs[i].Res.MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), HrConfigs[i].Res.MemLimit);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), (UINT16) (HrConfigs[i].Res.PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit), (UINT16) (HrConfigs[i].Res.PMemLimit64 & 0xFFFF));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), (UINT32) (HrConfigs[i].Res.PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32), (UINT32) (HrConfigs[i].Res.PMemLimit64 >> 16));
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase), HrConfigs[i].Res.IoBase);
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit), HrConfigs[i].Res.IoLimit);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16), 0x00000000);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, HrConfigs[i].Res.Cmd);
+ }
+ if (Hr_Config->DeviceId == AR_HR_2C || Hr_Config->DeviceId == AR_HR_4C || Hr_Config->DeviceId == AR_HR_LP) {
+ for (i = 0; i < Hr_Config->BridgeLoops; ++i) {
+ if(HrConfigs[i].IsDSBridge) {
+ UnsetVesc(HrConfigs[i].DevId.Bus, HrConfigs[i].DevId.Dev, HrConfigs[i].DevId.Fun);
+ }
+ }
+ }
+
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,(Hr_Config->HRBus + 2), 0x00, 0x00, 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX0 * 4), HrConfigs[HR_DS_PORT0].Res.MemLimit << 16);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX1 * 4), (HrConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CACHE_LINE_SIZE);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM);
+ return Ret;
+} // InitializeHostRouter
+STATIC
+UINT8
+ConfigureSlot (
+ IN UINT8 Bus,
+ IN UINT8 MAX_DEVICE,
+ IN INT8 Depth,
+ IN BOOLEAN ArPcie,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Device;
+ UINT8 SBus;
+ UINT8 UsedBusNumbers;
+ UINT8 RetBusNum;
+ PORT_INFO CurrentSlot;
+
+ RetBusNum = 0;
+
+ for (Device = 0; Device < MAX_DEVICE; Device++) {
+ //
+ // Continue if device is absent
+ //
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, 0x00, 0);
+ if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET)) {
+ continue;
+
+ }
+
+ if (P2P_BRIDGE != PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSCODE_OFFSET + 1))) {
+ SetDevResources (
+ Bus,
+ Device,
+ PCI_MAX_FUNC,
+ PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4),
+ PortInfo
+ );
+ continue;
+ }
+ //
+ // Else Bridge
+ //
+ CopyMem (&CurrentSlot, PortInfo, sizeof (PORT_INFO));
+
+ ++RetBusNum; // UP Bridge
+ SBus = Bus + RetBusNum; // DS Bridge
+
+ if (SBus + 1 >= PortInfo->BusNumLimit) {
+ continue;
+
+ }
+
+ SetDevResources (Bus, Device, 1, PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX1 * 4), PortInfo);
+
+ //
+ // Init UP Bridge to reach DS Bridge
+ //
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM);
+
+ if(ArPcie) {
+ UnsetVesc(Bus, Device, 0x00);
+ }
+
+ UsedBusNumbers = ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo);
+ RetBusNum += UsedBusNumbers;
+
+ SetPhyPortResources (
+ Bus,
+ Device,
+ SBus + UsedBusNumbers,
+ Depth,
+ &CurrentSlot,
+ PortInfo
+ );
+ }
+ //
+ // for (Device = 0; Device <= PCI_MAX_DEVICE; Device++)
+ //
+ return RetBusNum;
+} // ConfigureSlot
+
+STATIC
+VOID
+SetCioPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 SBus,
+ IN UINT8 SubBus,
+ IN PORT_INFO *portInfoBeforeChange,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Cmd;
+ Cmd = CMD_BUS_MASTER;
+
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x00, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, SBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, SubBus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+
+ if (PortInfo->IoBase <= PortInfo->IoLimit) {
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase), PortInfo->IoBase);
+ PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit), PortInfo->IoLimit);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16), 0x00000000);
+ Cmd |= CMD_BM_IO;
+ } else {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase), DISBL_IO_REG1C);
+ }
+
+ if (PortInfo->MemBase <= PortInfo->MemLimit) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), PortInfo->MemBase);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit), PortInfo->MemLimit);
+ Cmd |= CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), DISBL_MEM32_REG20);
+ }
+
+ if (PortInfo->PMemBase64 <= PortInfo->PMemLimit64) {
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), (UINT16) (PortInfo->PMemBase64 & 0xFFFF));
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit), (UINT16) (PortInfo->PMemLimit64 & 0xFFFF));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), (UINT32) (PortInfo->PMemBase64 >> 16));
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32), (UINT32) (PortInfo->PMemLimit64 >> 16));
+ Cmd |= CMD_BM_MEM;
+ } else {
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32), 0);
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CACHE_LINE_SIZE);
+} // SetCioPortResources
+
+STATIC
+VOID
+SetSlotsAsUnused (
+ IN UINT8 Bus,
+ IN UINT8 MaxSlotNum,
+ IN UINT8 CioSlot,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 Slot;
+ for (Slot = MaxSlotNum; Slot > CioSlot; --Slot) {
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Slot, 0x00, 0);
+ if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET)) {
+ continue;
+ }
+
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CACHE_LINE_SIZE);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Bus);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, PortInfo->BusNumLimit);
+ PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase), DISBL_IO_REG1C);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase), DISBL_MEM32_REG20);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase), DISBL_PMEM_REG24);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MASTER);
+ PortInfo->BusNumLimit--;
+ }
+} // SetSlotsAsUnused
+
+STATIC
+UINT16
+FindVendorSpecificHeader(
+ IN UINT8 Bus
+)
+{
+ PCI_EXP_EXT_HDR *ExtHdr;
+ UINT32 ExtHdrValue;
+ UINT16 ExtendedRegister;
+
+ ExtHdr = (PCI_EXP_EXT_HDR*) &ExtHdrValue;
+ ExtendedRegister = 0x100;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x00, 0);
+ while (ExtendedRegister) {
+ ExtHdrValue = PciSegmentRead32 (gDeviceBaseAddress + ExtendedRegister);
+ if (ExtHdr->CapabilityId == 0xFFFF) {
+ return 0x0000; // No Vendor-Specific Extended Capability header
+ }
+
+ if (PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID == ExtHdr->CapabilityId) {
+ return ExtendedRegister;
+ }
+
+ ExtendedRegister = (UINT16) ExtHdr->NextCapabilityOffset;
+ }
+ return 0x0000; // No Vendor-Specific Extended Capability header
+}
+
+STATIC
+UINT8
+FindSsid_SsvidHeader (
+ IN UINT8 Bus
+ )
+{
+ UINT8 CapHeaderId;
+ UINT8 CapHeaderOffset;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x00, 0);
+ CapHeaderOffset = PciSegmentRead8 (gDeviceBaseAddress + PCI_CAPBILITY_POINTER_OFFSET);
+
+ while (CapHeaderOffset != 0) {
+ CapHeaderId = PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOffset);
+
+ if (CapHeaderId == PCIE_CAP_ID_SSID_SSVID) {
+ return CapHeaderOffset;
+ }
+
+ CapHeaderOffset = PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOffset + 1);
+ }
+
+ DEBUG((DEBUG_INFO, "SID0\n"));
+ return 0;
+} // FindSsid_SsvidHeader
+
+STATIC
+BOOLEAN
+GetCioSlotByDevId (
+ IN UINT8 Bus,
+ OUT UINT8 *CioSlot,
+ OUT UINT8 *MaxSlotNum,
+ OUT BOOLEAN *ArPcie
+ )
+{
+ UINT16 VSECRegister;
+ BRDG_CIO_MAP_REG BridgMap;
+ UINT32 BitScanRes;
+ UINT16 DevId;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, 0x00, 0x00, 0);
+ DevId = PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+
+ //
+ // Init out params in case device is not recognised
+ //
+ *CioSlot = 4;
+ *MaxSlotNum = 7;
+ *ArPcie = FALSE;
+
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1578:
+ *ArPcie = TRUE;
+ }
+
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1513:
+ case 0x151A:
+ case 0x151B:
+ case 0x1547:
+ case 0x1548:
+ return TRUE; // Just return
+ case 0x1549:
+ return FALSE; // Just return
+ }
+
+ VSECRegister = FindVendorSpecificHeader(Bus);
+ if (!VSECRegister) {
+ return TRUE; // Just return
+ }
+ //
+ // Go to Bridge/CIO map register
+ //
+ VSECRegister += 0x18;
+ BridgMap.AB_REG = PciSegmentRead32(gDeviceBaseAddress + VSECRegister);
+ //
+ // Check for range
+ //
+ if (BridgMap.Bits.NumOfDSPorts < 1 || BridgMap.Bits.NumOfDSPorts > 27) {
+ return TRUE;
+ //
+ // Not a valid register
+ //
+ }
+ //
+ // Set OUT params
+ //
+ *MaxSlotNum = (UINT8) BridgMap.Bits.NumOfDSPorts;
+
+#ifdef _MSC_VER
+ if(!_BitScanForward(&BitScanRes, BridgMap.Bits.CioPortMap)) { // No DS bridge which is CIO port
+ return FALSE;
+ }
+#else
+#ifdef __GNUC__
+ if (BridgMap.Bits.CioPortMap == 0) {
+ return FALSE;
+ }
+ BitScanRes = __builtin_ctz (BridgMap.Bits.CioPortMap);
+#else
+#error Unsupported Compiler
+#endif
+#endif
+
+ *CioSlot = (UINT8)BitScanRes;
+ return TRUE;
+} // GetCioSlotByDevId
+
+#define TBT_LEGACY_SUB_SYS_ID 0x11112222
+
+STATIC
+BOOLEAN
+IsLegacyDevice (
+ IN UINT8 Bus
+ )
+{
+ UINT32 Sid;
+ UINT8 SidRegister;
+ UINT16 DevId;
+
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x00, 0);
+ DevId = PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+ switch (DevId) {
+ //
+ // For known device IDs
+ //
+ case 0x1513:
+ case 0x151A:
+ case 0x151B:
+ DEBUG((DEBUG_INFO, "Legacy "));
+ DEBUG((DEBUG_INFO, "DevId = %d\n",DevId));
+ return TRUE;
+ //
+ // Legacy device by Device Id
+ //
+ }
+
+ SidRegister = FindSsid_SsvidHeader(Bus);
+
+ if (!SidRegister) {
+ return TRUE; // May be absent for legacy devices
+ }
+ //
+ // Go to register
+ //
+ SidRegister += 0x4;
+ Sid = PciSegmentRead32(gDeviceBaseAddress + SidRegister);
+ DEBUG((DEBUG_INFO, "SID"));
+ DEBUG((DEBUG_INFO, " = %d\n", Sid));
+
+return TBT_LEGACY_SUB_SYS_ID == Sid || 0 == Sid;
+} // IsLegacyDevice
+
+STATIC
+VOID
+UnsetVescEp(
+ IN UINT8 Bus,
+ IN UINT8 MaxSlotNum
+ )
+{
+ UINT8 i;
+
+ for (i = 0; i <= MaxSlotNum; ++i)
+ {
+ UnsetVesc(Bus, i, 0);
+ }
+}// Unset_VESC_REG2_EP
+
+STATIC
+BOOLEAN
+ConfigureEP (
+ IN INT8 Depth,
+ IN OUT UINT8 *Bus,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ UINT8 SBus;
+ UINT8 CioSlot;
+ UINT8 MaxSlotNum;
+ BOOLEAN ArPcie;
+ UINT8 MaxPHYSlots;
+ UINT8 UsedBusNumbers;
+ UINT8 cmd;
+ BOOLEAN CioSlotPresent;
+ BOOLEAN Continue;
+ PORT_INFO PortInfoOrg;
+ UINT8 CioBus;
+
+ CioSlot = 4;
+ MaxSlotNum = 7;
+ CopyMem (&PortInfoOrg, PortInfo, sizeof (PORT_INFO));
+
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, *Bus, 0x00, 0x00, 0);
+ cmd = PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET);
+ // AR ONLY
+ // Endpoint on CIO slot, but not a bridge device
+ if (P2P_BRIDGE != PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSCODE_OFFSET + 1))) {
+ DEBUG((DEBUG_INFO, "UEP\n"));
+ // Check whether EP already configured by examining CMD register
+ if(cmd & CMD_BUS_MASTER) // Yes, no need to touch this EP
+ {
+ DEBUG((DEBUG_INFO, "BMF\n"));
+ return FALSE;
+ }
+ // Configure it as regular PCIe device
+ ConfigureSlot(*Bus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo);
+
+ return FALSE;
+ }
+
+ //
+ // Based on Device ID assign Cio slot and max number of PHY slots to scan
+ //
+ CioSlotPresent = GetCioSlotByDevId(*Bus, &CioSlot, &MaxSlotNum, &ArPcie);
+ MaxPHYSlots = MaxSlotNum;
+ //
+ // Check whether EP already configured by examining CMD register
+ //
+
+ if (cmd & CMD_BUS_MASTER) {
+ //
+ // Yes no need to touch this EP, just move to next one in chain
+ //
+ CioBus = *Bus + 1;
+ if(ArPcie){
+ UnsetVescEp(CioBus, MaxSlotNum);
+ }
+ if (!CioSlotPresent) {
+ //
+ // Cio slot is not present in EP, just return FALSE
+ //
+ DEBUG((DEBUG_INFO, "BMF\n"));
+ return FALSE;
+ }
+ //
+ // Take all resources from Cio slot and return
+ //
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,CioBus, CioSlot, 0x00, 0);
+ PortInfo->BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ PortInfo->IoBase = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
+ PortInfo->IoLimit = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
+ PortInfo->MemBase = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase));
+ PortInfo->MemLimit = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit));
+ PortInfo->PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
+ PortInfo->PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ PortInfo->PMemLimit64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ PortInfo->PMemLimit64 |= 0xF;
+ //
+ // Jump to next EP
+ //
+ *Bus = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ //
+ // Should we continue?
+ //
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00, 0x00, 0);
+ Continue = 0xFFFF != PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+ return Continue;
+ }
+ //
+ // Set is legacy dvice
+ //
+ isLegacyDevice = IsLegacyDevice (*Bus);
+
+ SetCioPortResources (
+ *Bus,
+ 0, // Assign all available resources to US port of EP
+ *Bus + 1,
+ PortInfo->BusNumLimit,
+ 0,
+ PortInfo
+ );
+
+ SBus = *Bus + 1;// Jump to DS port
+
+ if (CioSlotPresent) {
+ MaxPHYSlots = CioSlot;
+ }
+
+ UsedBusNumbers = ConfigureSlot(SBus, MaxPHYSlots, Depth, ArPcie, PortInfo);
+ if (!CioSlotPresent) {
+ return FALSE;
+ //
+ // Stop resource assignment on this chain
+ //
+ }
+ //
+ // Set rest of slots us unused
+ //
+ SetSlotsAsUnused (SBus, MaxSlotNum, CioSlot, PortInfo);
+
+ SetCioPortResources (
+ SBus,
+ CioSlot,
+ SBus + UsedBusNumbers + 1,
+ PortInfo->BusNumLimit,
+ &PortInfoOrg,
+ PortInfo
+ );
+ *Bus = SBus + UsedBusNumbers + 1;// Go to next EP
+ if(ArPcie) {
+ UnsetVesc(SBus, CioSlot, 0x00);
+ }
+ if (*Bus > PortInfo->BusNumLimit - 2) {
+ //
+ // In case of bus numbers are exhausted stop enumeration
+ //
+ return FALSE;
+ }
+ //
+ // Check whether we should continue on this chain
+ //
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00, 0x00, 0);
+ Continue = 0xFFFF != PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+ return Continue;
+} // ConfigureEP
+
+STATIC
+VOID
+GetPortResources (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0);
+ PortInfo->BusNumLimit = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ PortInfo->IoBase = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase)) & 0xF0;
+ PortInfo->IoLimit = PciSegmentRead8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit)) & 0xF0;
+ PortInfo->MemBase = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xFFF0;
+ PortInfo->MemLimit = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0;
+ PortInfo->PMemLimit64 = PciSegmentRead16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0;
+ PortInfo->PMemBase64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16;
+ PortInfo->PMemLimit64 |= (UINT64)(PciSegmentRead32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16;
+ PortInfo->IoLimit |= 0xF;
+ PortInfo->MemLimit |= 0xF;
+ PortInfo->PMemLimit64 |= 0xF;
+} // GetPortResources
+
+STATIC
+VOID
+ConfigurePort (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN OUT PORT_INFO *PortInfo
+ )
+{
+ INT8 i;
+ UINT8 USBusNum;
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0);
+ USBusNum = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, USBusNum, 0x00, 0x00, 0);
+ if (0xFFFF == PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET)) {
+ //
+ // Nothing to do if TBT device is not connected
+ //
+ return ;
+ }
+
+ GetPortResources(Bus, Dev, Fun, PortInfo);// Take reserved resources from DS port
+ //
+ // Assign resources to EPs
+ //
+ for (i = 0; i < MAX_TBT_DEPTH; ++i) {
+ PortInfo->ConfedEP++;
+ if (!ConfigureEP (i, &USBusNum, PortInfo)) {
+ return ;
+ }
+ }
+} // ConfigurePort
+
+VOID
+ThunderboltCallback (
+ IN UINT8 Type
+ )
+{
+ PORT_INFO PortInfoOrg = { 0 };
+ HR_CONFIG HrConfig = { 0 };
+ UINT8 i;
+ UINTN Segment = 0;
+ UINTN Bus = 0;
+ UINTN Device;
+ UINTN Function;
+
+ DEBUG((DEBUG_INFO, "ThunderboltCallback.Entry\n"));
+
+ DEBUG((DEBUG_INFO, "PortInfo Initialization\n"));
+ PortInfoInit (&PortInfoOrg);
+ if(Type == DTBT_CONTROLLER) {
+ if (gCurrentDiscreteTbtRootPort == 0) {
+ DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
+ return;
+ }
+ GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRootPort - 1, &Device, &Function);
+ DEBUG((DEBUG_INFO, "InitializeHostRouter. \n"));
+ if (!InitializeHostRouter (&HrConfig, Segment, Bus, Device, Function)) {
+ return ;
+ }
+ //
+ // Configure DS ports
+ //
+ for (i = HrConfig.MinDSNumber; i <= HrConfig.MaxDSNumber; ++i) {
+ DEBUG((DEBUG_INFO, "ConfigurePort. \n"));
+ ConfigurePort (HrConfig.HRBus + 1, i,0, &PortInfoOrg);
+ }
+
+ DEBUG((DEBUG_INFO, "EndOfThunderboltCallback.\n"));
+ EndOfThunderboltCallback (Segment, Bus, Device, Function);
+
+ }
+ DEBUG((DEBUG_INFO, "ThunderboltCallback.Exit\n"));
+} // ThunderboltCallback
+
+VOID
+DisablePCIDevicesAndBridges (
+ IN UINT8 MinBus,
+ IN UINT8 MaxBus
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RegVal;
+ //
+ // Disable PCI device First, and then Disable PCI Bridge
+ //
+ for (Bus = MaxBus; Bus > MinBus; --Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0);
+ if (INVALID_PCI_DEVICE == PciSegmentRead32 (gDeviceBaseAddress + PCI_VENDOR_ID_OFFSET)) {
+ if (Fun == 0) {
+ break;
+
+ }
+
+ continue;
+ }
+
+ RegVal = PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_OFFSET);
+ if (HEADER_TYPE_DEVICE == (RegVal & 1)) {
+ //
+ // ******** Disable PCI Device ********
+ // BIT0 I/O Space Enabled BIT1 Memory Space Enabled
+ // BIT2 Bus Master Enabled BIT4 Memory Write and Invalidation Enable
+ //
+ PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)~(BIT0 | BIT1 | BIT2 | BIT4));
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX0 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX1 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX2 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX3 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX4 * 4), 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4), 0);
+ }
+ }
+ }
+ }
+ //
+ // now no more PCI dev on another side of PCI Bridge can safty disable PCI Bridge
+ //
+ for (Bus = MaxBus; Bus > MinBus; --Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0);
+ if (INVALID_PCI_DEVICE == PciSegmentRead32 (gDeviceBaseAddress + PCI_VENDOR_ID_OFFSET)) {
+ if (Fun == 0) {
+ break;
+ }
+
+ continue;
+ }
+
+ RegVal = PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_OFFSET);
+ if (HEADER_TYPE_PCI_TO_PCI_BRIDGE == (RegVal & BIT0)) {
+ PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)~(BIT0 | BIT1 | BIT2 | BIT4));
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0);
+ PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0);
+ PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32), 0);
+ }
+ } // for ( Fun .. )
+ } // for ( Dev ... )
+ } // for ( Bus ... )
+} // DisablePCIDevicesAndBridges
+
+VOID
+TbtDisablePCIDevicesAndBridges (
+ IN UINT8 Type
+ )
+{
+ UINTN Segment = 0;
+ UINTN Bus = 0;
+ UINTN Device;
+ UINTN Function;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+
+ MinBus = 1;
+ if(Type == DTBT_CONTROLLER) {
+ //
+ // for(Dev = 0; Dev < 8; ++Dev)
+ // {
+ // PciOr8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET), 0x40);
+ // gBS->Stall(2000); // 2msec
+ // PciAnd8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET), 0xBF);
+ // }
+ // gBS->Stall(200 * 1000); // 200 msec
+ //
+ if (gCurrentDiscreteTbtRootPort == 0) {
+ DEBUG((DEBUG_ERROR, "Invalid RP Input\n"));
+ return;
+ }
+ GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRootPort - 1, &Device, &Function);
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
+ MinBus = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ MaxBus = PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (Segment, MinBus, 0x00, 0x00, 0);
+ DeviceId = PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_OFFSET);
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+ TbtSegment = (UINT8)Segment;
+ MinBus++;
+ //
+ // @todo : Move this out when we dont have Loop for ITBT
+ //
+ DisablePCIDevicesAndBridges(MinBus, MaxBus);
+
+ }
+} // DisablePCIDevicesAndBridges
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
new file mode 100644
index 0000000000..fa768f8279
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
@@ -0,0 +1,180 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TBT_SMI_HANDLER_H_
+#define _TBT_SMI_HANDLER_H_
+
+#include <Library/TbtCommonLib.h>
+#include <Library/IoLib.h>
+#include <IndustryStandard/Pci.h>
+
+#ifdef PROGRESS_CODE
+#undef PROGRESS_CODE
+#endif
+
+#define MAX_TBT_DEPTH 6
+
+#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
+
+#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1)
+
+#define CMD_BUS_MASTER BIT2
+#define CMD_BM_IO (CMD_BUS_MASTER | BIT0)
+#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1)
+#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
+
+#define DEF_CACHE_LINE_SIZE 0x20
+#define DEF_RES_IO_PER_DEV 4
+#define DEF_RES_MEM_PER_DEV 32
+#define DEF_RES_PMEM_PER_DEV 32
+
+#define DOCK_BUSSES 8
+
+#define DISBL_IO_REG1C 0x01F1
+#define DISBL_MEM32_REG20 0x0000FFF0
+#define DISBL_PMEM_REG24 0x0001FFF1
+
+#define count(x) (sizeof (x) / sizeof ((x)[0]))
+
+#define PCIE_CAP_ID_SSID_SSVID 0x0D
+#define INVALID_PCI_DEVICE 0xFFFFFFFF
+#define PCI_TBT_VESC_REG2 0x510
+
+typedef struct _PortInfo {
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+ UINT8 BusNumLimit;
+ UINT8 ConfedEP;
+} PORT_INFO;
+
+typedef struct _MEM_REGS {
+ UINT32 Base;
+ UINT32 Limit;
+} MEM_REGS;
+
+typedef struct _PMEM_REGS {
+ UINT64 Base64;
+ UINT64 Limit64;
+} PMEM_REGS;
+
+typedef struct _IO_REGS {
+ UINT16 Base;
+ UINT16 Limit;
+} IO_REGS;
+
+typedef struct _BRDG_RES_CONFIG {
+ UINT8 Cmd;
+ UINT8 Cls;
+ UINT8 IoBase;
+ UINT8 IoLimit;
+ UINT16 MemBase;
+ UINT16 MemLimit;
+ UINT64 PMemBase64;
+ UINT64 PMemLimit64;
+} BRDG_RES_CONFIG;
+
+typedef struct _BRDG_CONFIG {
+ DEV_ID DevId;
+ UINT8 PBus;
+ UINT8 SBus;
+ UINT8 SubBus;
+ BOOLEAN IsDSBridge;
+ BRDG_RES_CONFIG Res;
+} BRDG_CONFIG;
+
+enum {
+ HR_US_PORT,
+ HR_DS_PORT0,
+ HR_DS_PORT3,
+ HR_DS_PORT4,
+ HR_DS_PORT5,
+ HR_DS_PORT6,
+ MAX_CFG_PORTS
+};
+
+enum {
+ HR_DS_PORT1 = HR_DS_PORT3
+};
+
+//
+// Alpine Ridge
+//
+enum {
+ AR_DS_PORT1 = HR_DS_PORT3,
+ AR_DS_PORT2,
+ AR_DS_PORT3,
+ AR_DS_PORT4
+};
+
+typedef struct _HR_CONFIG {
+ UINT16 DeviceId;
+ UINT8 HRBus;
+ UINT8 MinDSNumber;
+ UINT8 MaxDSNumber;
+ UINT8 BridgeLoops;
+} HR_CONFIG;
+
+STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE = {
+ CMD_BUS_MASTER,
+ 0,
+ DISBL_IO_REG1C & 0xFF,
+ DISBL_IO_REG1C >> 8,
+ DISBL_MEM32_REG20 & 0xFFFF,
+ DISBL_MEM32_REG20 >> 16,
+ DISBL_PMEM_REG24 & 0xFFFF,
+ DISBL_PMEM_REG24 >> 16
+};
+
+typedef union _BRDG_CIO_MAP_REG {
+ UINT32 AB_REG;
+ struct {
+ UINT32 NumOfDSPorts : 5;
+ UINT32 CioPortMap : 27;
+ } Bits;
+} BRDG_CIO_MAP_REG;
+
+//
+// Functions
+//
+VOID
+ThunderboltCallback (
+ IN UINT8 Type
+ );
+
+VOID
+TbtDisablePCIDevicesAndBridges (
+ IN UINT8 Type
+ );
+
+VOID
+EndOfThunderboltCallback(
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+);
+
+VOID
+ConfigureTbtAspm(
+ IN UINT8 Type,
+ IN UINT16 Aspm
+);
+
+UINT8
+PcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
new file mode 100644
index 0000000000..40de64297d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
@@ -0,0 +1,1765 @@
+/** @file
+
+` Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Module specific Includes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/BaseLib.h>
+#include <Library/GpioLib.h>
+#include <TbtBoardInfo.h>
+#include <Protocol/TbtNvsArea.h>
+#include <PchAccess.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/IoLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Protocol/SmmSxDispatch2.h>
+#include <Protocol/SmmSwDispatch2.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include "TbtSmiHandler.h"
+#include <PcieRegs.h>
+#include <Protocol/SaPolicy.h>
+#include <Protocol/DxeTbtPolicy.h>
+#include <Library/PchPmcLib.h>
+#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
+
+#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
+
+#define DISBL_IO_REG1C 0x01F1
+#define DISBL_MEM32_REG20 0x0000FFF0
+#define DISBL_PMEM_REG24 0x0001FFF1
+
+#define DOCK_BUSSES 8
+
+#define PCI_CAPABILITY_ID_PCIEXP 0x10
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34
+
+#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Snoop Latency can we put like this ?
+#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Non-Snoop Latency can we put like this ?
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA *mTbtNvsAreaPtr;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscreteTbtRootPort;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscreteTbtRootPortType;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxSnoopLatency;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxNoSnoopLatency;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gDTbtPcieRstSupport;
+GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob = NULL;
+STATIC UINTN mPciExpressBaseAddress;
+STATIC UINT8 TbtSegment = 0;
+VOID
+GpioWrite (
+ IN UINT32 GpioNumber,
+ IN BOOLEAN Value
+ )
+{
+ GpioSetOutputValue (GpioNumber, (UINT32)Value);
+}
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 = Advanced Error Reporting Capability
+ 0x0002 = Virtual Channel Capability
+ 0x0003 = Device Serial Number Capability
+ 0x0004 = Power Budgeting Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieFindExtendedCapId (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ )
+{
+ UINT16 CapHeaderOffset;
+ UINT16 CapHeaderId;
+ UINT64 DeviceBase;
+
+ DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
+
+ ///
+ /// Start to search at Offset 0x100
+ /// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
+ ///
+ CapHeaderId = 0;
+ CapHeaderOffset = 0x100;
+ while (CapHeaderOffset != 0 && CapHeaderId != 0xFFFF) {
+ CapHeaderId = PciSegmentRead16 (DeviceBase + CapHeaderOffset);
+ if (CapHeaderId == CapId) {
+ return CapHeaderOffset;
+ }
+ ///
+ /// Each capability must be DWORD aligned.
+ /// The bottom two bits of all pointers are reserved and must be implemented as 00b
+ /// although software must mask them to allow for future uses of these bits.
+ ///
+ CapHeaderOffset = (PciSegmentRead16 (DeviceBase + CapHeaderOffset + 2) >> 4) & ((UINT16) ~(BIT0 | BIT1));
+ }
+
+ return 0;
+}
+
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 = PCI Power Management Interface
+ 0x04 = Slot Identification
+ 0x05 = MSI Capability
+ 0x10 = PCI Express Capability
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ )
+{
+ UINT8 CapHeaderOffset;
+ UINT8 CapHeaderId;
+ UINT64 DeviceBase;
+
+ DeviceBase = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
+
+ if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_STATUS_CAPABILITY) == 0x00) {
+ ///
+ /// Function has no capability pointer
+ ///
+ return 0;
+ }
+
+ ///
+ /// Check the header layout to determine the Offset of Capabilities Pointer Register
+ ///
+ if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) {
+ ///
+ /// If CardBus bridge, start at Offset 0x14
+ ///
+ CapHeaderOffset = 0x14;
+ } else {
+ ///
+ /// Otherwise, start at Offset 0x34
+ ///
+ CapHeaderOffset = 0x34;
+ }
+ ///
+ /// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
+ ///
+ CapHeaderId = 0;
+ CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((UINT8) ~(BIT0 | BIT1));
+ while (CapHeaderOffset != 0 && CapHeaderId != 0xFF) {
+ CapHeaderId = PciSegmentRead8 (DeviceBase + CapHeaderOffset);
+ if (CapHeaderId == CapId) {
+ return CapHeaderOffset;
+ }
+ ///
+ /// Each capability must be DWORD aligned.
+ /// The bottom two bits of all pointers (including the initial pointer at 34h) are reserved
+ /// and must be implemented as 00b although software must mask them to allow for future uses of these bits.
+ ///
+ CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset + 1) & ((UINT8) ~(BIT0 | BIT1));
+ }
+
+ return 0;
+}
+/**
+ This function configures the L1 Substates.
+ It can be used for Rootport and endpoint devices.
+
+ @param[in] DownstreamPort Indicates if the device about to be programmed is a downstream port
+ @param[in] DeviceBase Device PCI configuration base address
+ @param[in] L1SubstateExtCapOffset Pointer to L1 Substate Capability Structure
+ @param[in] PortL1SubstateCapSupport L1 Substate capability setting
+ @param[in] PortCommonModeRestoreTime Common Mode Restore Time
+ @param[in] PortTpowerOnValue Tpower_on Power On Wait Time
+ @param[in] PortTpowerOnScale Tpower-on Scale
+
+ @retval none
+**/
+VOID
+ConfigureL1s (
+ IN UINTN DeviceBase,
+ IN UINT16 L1SubstateExtCapOffset,
+ IN UINT32 PortL1SubstateCapSupport,
+ IN UINT32 PortCommonModeRestoreTime,
+ IN UINT32 PortTpowerOnValue,
+ IN UINT32 PortTpowerOnScale,
+ IN UINT16 MaxLevel
+ )
+{
+
+ PciSegmentAndThenOr32 (
+ DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) ~(0xFF00),
+ (UINT32) PortCommonModeRestoreTime << 8
+ );
+
+ PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_OFFSET, 0xFFFFFF04);
+
+ PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_OFFSET,(UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerOnScale));
+
+ PciSegmentAndThenOr32 (
+ DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) ~(0xE3FF0000),
+ (UINT32) (BIT30 | BIT23 | BIT21)
+ );
+
+}
+
+VOID
+RootportL1sSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT16 RootL1SubstateExtCapOffset,
+ IN UINT16 MaxL1Level
+ )
+{
+ UINTN ComponentABaseAddress;
+ UINTN ComponentBBaseAddress;
+ UINT8 SecBus;
+ UINT32 PortL1SubstateCapSupport;
+ UINT32 PortCommonModeRestoreTime;
+ UINT32 PortTpowerOnValue;
+ UINT32 PortTpowerOnScale;
+ UINT16 ComponentBL1SubstateExtCapOffset;
+ UINT32 ComponentBL1Substates;
+ UINT32 ComponentBCommonModeRestoreTime;
+ UINT32 ComponentBTpowerOnValue;
+ UINT32 ComponentBTpowerOnScale;
+ UINT32 Data32;
+
+ PortL1SubstateCapSupport = 0;
+ PortCommonModeRestoreTime = 0;
+ PortTpowerOnValue = 0;
+ PortTpowerOnScale = 0;
+ Data32 = 0;
+
+ ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (RootL1SubstateExtCapOffset != 0) {
+ Data32 = PciSegmentRead32 (ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
+ PortL1SubstateCapSupport = (Data32) & 0x0F;
+ PortCommonModeRestoreTime = (Data32 >> 8) & 0xFF;
+ PortTpowerOnScale = (Data32 >> 16) & 0x3;
+ PortTpowerOnValue = (Data32 >> 19) & 0x1F;
+ } else {
+ MaxL1Level = 0; // If L1 Substates from Root Port side is disable, then Disable from Device side also.
+ }
+
+ SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
+
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ ComponentBL1SubstateExtCapOffset = PcieFindExtendedCapId (
+ SecBus,
+ 0,
+ 0,
+ V_PCIE_EX_L1S_CID
+ );
+ if (ComponentBL1SubstateExtCapOffset != 0) {
+ ComponentBL1Substates = PciSegmentRead32 (ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET);
+ ComponentBCommonModeRestoreTime = (ComponentBL1Substates >> 8) & 0xFF;
+ ComponentBTpowerOnScale = (ComponentBL1Substates >> 16) & 0x3;
+ ComponentBTpowerOnValue = (ComponentBL1Substates >> 19) & 0x1F;
+
+ if (MaxL1Level == 3) {
+ if (Data32 >= ComponentBL1Substates) {
+ if (~(Data32 | BIT2)) {
+ MaxL1Level = 1;
+ }
+ }
+ else {
+ if (~(ComponentBL1Substates | BIT2)) {
+ MaxL1Level = 1;
+ }
+ }
+ }
+
+ if (MaxL1Level == 3) {
+ ConfigureL1s (
+ ComponentABaseAddress,
+ RootL1SubstateExtCapOffset,
+ PortL1SubstateCapSupport,
+ ComponentBCommonModeRestoreTime,
+ ComponentBTpowerOnValue,
+ ComponentBTpowerOnScale,
+ MaxL1Level
+ );
+
+ ConfigureL1s (
+ ComponentBBaseAddress,
+ ComponentBL1SubstateExtCapOffset,
+ ComponentBL1Substates,
+ PortCommonModeRestoreTime,
+ PortTpowerOnValue,
+ PortTpowerOnScale,
+ MaxL1Level
+ );
+ }
+
+ if (MaxL1Level == 1) {
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+ }
+ else {
+ if (RootL1SubstateExtCapOffset != 0) {
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT2 | BIT0)
+ );
+ }
+ if (ComponentBL1SubstateExtCapOffset != 0) {
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT3 | BIT1)
+ );
+
+ PciSegmentOr32 (
+ ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET,
+ (UINT32) (BIT2 | BIT0)
+ );
+ }
+ }
+ }
+ }
+}
+
+VOID
+MultiFunctionDeviceAspm (
+ IN UINT8 Bus,
+ IN UINT8 Dev
+ )
+{
+ UINT16 LowerAspm;
+ UINT16 AspmVal;
+ UINT8 Fun;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+
+ LowerAspm = 3; // L0s and L1 Supported
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ // Device not present
+ continue;
+ }
+
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+
+ AspmVal = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
+ if (LowerAspm > AspmVal) {
+ LowerAspm = AspmVal;
+ }
+ } //Fun
+
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, LowerAspm);
+ } //Fun
+}
+
+UINT16
+LimitAspmLevel (
+ IN UINT16 SelectedAspm,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ SelectedAspm = SelectedAspm & MaxAspmLevel;
+
+ return SelectedAspm;
+}
+
+UINT16
+FindOptimalAspm (
+ IN UINT16 ComponentAaspm,
+ IN UINT16 ComponentBaspm
+ )
+{
+ UINT16 SelectedAspm;
+
+ SelectedAspm = ComponentAaspm & ComponentBaspm;
+
+ return SelectedAspm;
+}
+
+UINT16
+FindComponentBaspm (
+ IN UINT8 Bus,
+ IN UINT8 MaxBus
+ )
+{
+ UINT8 BusNo;
+ UINT8 DevNo;
+ UINT8 FunNo;
+ UINT64 DevBaseAddress;
+ UINT8 RegVal;
+ UINT8 SecBusNo;
+ UINT16 SelectedAspm; // No ASPM Support
+ UINT8 CapHeaderOffset_B;
+ BOOLEAN AspmFound;
+
+ SelectedAspm = 0;
+ AspmFound = FALSE;
+
+ for (BusNo = MaxBus; (BusNo != 0xFF) && (!AspmFound); --BusNo) {
+ for (DevNo = 0; (DevNo <= PCI_MAX_DEVICE) && (!AspmFound); ++DevNo) {
+ for (FunNo = 0; (FunNo <= PCI_MAX_FUNC) && (!AspmFound); ++FunNo) {
+ //
+ // Check for Device availability
+ //
+ DevBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, BusNo, DevNo, FunNo, 0);
+ if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ RegVal = PciSegmentRead8 (DevBaseAddress + PCI_HEADER_TYPE_OFFSET);
+ if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) != 0x01) {
+ //
+ // Not a PCI-to-PCI bridges device
+ //
+ continue;
+ }
+
+ SecBusNo = PciSegmentRead8 (DevBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+
+ if (SecBusNo == Bus) {
+ //
+ // This is the Rootbridge for the given 'Bus' device
+ //
+ CapHeaderOffset_B = PcieFindCapId (TbtSegment, BusNo, DevNo, FunNo, 0x10);
+ SelectedAspm = (PciSegmentRead16 (DevBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
+ AspmFound = TRUE;
+ }
+ } //FunNo
+ } //DevNo
+ } //BusNo
+
+ return (SelectedAspm);
+}
+
+VOID
+NoAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset
+ )
+{
+ UINT64 DeviceBaseAddress;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, 0x00);
+}
+
+VOID
+EndpointAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT8 MaxBus,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
+ ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
+ SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
+}
+
+VOID
+UpstreamAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT8 MaxBus,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ ComponentAaspm = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
+ ComponentBaspm = FindComponentBaspm (Bus, MaxBus);
+ SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
+}
+
+VOID
+DownstreamAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 ComponentABaseAddress;
+ UINT64 ComponentBBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+ UINT8 SecBus;
+ UINT8 CapHeaderOffset_B;
+
+ ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ ComponentAaspm = (PciSegmentRead16 (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
+
+ SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
+ ComponentBaspm = 0; // No ASPM Support
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
+ CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
+ ComponentBaspm = (PciSegmentRead16 (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
+ }
+
+ SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
+}
+
+VOID
+RootportAspmSupport (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT8 CapHeaderOffset,
+ IN UINT16 MaxAspmLevel
+ )
+{
+ UINT64 ComponentABaseAddress;
+ UINT64 ComponentBBaseAddress;
+ UINT16 ComponentAaspm;
+ UINT16 ComponentBaspm;
+ UINT16 SelectedAspm;
+ UINT8 SecBus;
+ UINT8 CapHeaderOffset_B;
+
+ ComponentABaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ ComponentAaspm = (PciSegmentRead16 (ComponentABaseAddress + CapHeaderOffset + 0x00C) >> 10) & 3;
+
+ SecBus = PciSegmentRead8 (ComponentABaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ ComponentBBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0, 0, 0);
+ ComponentBaspm = 0; // No ASPM Support
+ if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) != 0xFFFF) {
+ CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10);
+ ComponentBaspm = (PciSegmentRead16 (ComponentBBaseAddress + CapHeaderOffset_B + 0x00C) >> 10) & 3;
+ }
+
+ SelectedAspm = FindOptimalAspm (ComponentAaspm, ComponentBaspm);
+ SelectedAspm = LimitAspmLevel (SelectedAspm, MaxAspmLevel);
+ PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0xFFFC, SelectedAspm);
+}
+
+VOID
+ThunderboltEnableAspmWithoutLtr (
+ IN UINT16 MaxAspmLevel,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RootBus;
+ UINT8 RootDev;
+ UINT8 RootFun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 RegVal;
+ UINT8 CapHeaderOffset;
+ UINT16 DevicePortType;
+
+ MinBus = 0;
+ MaxBus = 0;
+
+ MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment = (UINT8)RpSegment;
+
+ RootBus = (UINT8)RpBus;
+ RootDev = (UINT8)RpDevice;
+ RootFun = (UINT8)RpFunction;
+
+ //
+ // Enumerate all the bridges and devices which are available on TBT host controller
+ //
+ for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ RegVal = PciSegmentRead8 (DeviceBaseAddress + PCI_HEADER_TYPE_OFFSET);
+ if ((RegVal & BIT7) == 0) {
+ //
+ // Not a multi-function device
+ //
+ continue;
+ }
+
+ MultiFunctionDeviceAspm(Bus, Dev);
+ } //Dev
+ } //Bus
+
+
+ for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+ DevicePortType = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x002) >> 4) & 0xF;
+ if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET) == PCI_CLASS_SERIAL) {
+ MaxAspmLevel = (UINT16) 0x1;
+ }
+
+ switch (DevicePortType) {
+ case 0:
+ //
+ // PCI Express Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
+ break;
+
+ case 1:
+ //
+ // Legacy PCI Express Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
+ break;
+
+ case 4:
+ //
+ // Root Port of PCI Express Root Complex
+ //
+ RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLevel);
+ break;
+
+ case 5:
+ //
+ // Upstream Port of PCI Express Switch
+ //
+ UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
+ break;
+
+ case 6:
+ //
+ // Downstream Port of PCI Express Switch
+ //
+ DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLevel);
+ break;
+
+ case 7:
+ //
+ // PCI Express to PCI/PCI-X Bridge
+ //
+ NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
+ break;
+
+ case 8:
+ //
+ // PCI/PCI-X to PCI Express Bridge
+ //
+ NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset);
+ break;
+
+ case 9:
+ //
+ // Root Complex Integrated Endpoint
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
+ break;
+
+ case 10:
+ //
+ // Root Complex Event Collector
+ //
+ EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, MaxAspmLevel);
+ break;
+
+ default:
+ break;
+ }
+ //
+ // switch(DevicePortType)
+ //
+ }
+ //
+ // Fun
+ //
+ }
+ //
+ // Dev
+ //
+ }
+ //
+ // Bus
+ //
+ CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun, 0x10);
+ RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset, MaxAspmLevel);
+}
+
+
+
+VOID
+ThunderboltEnableL1Sub (
+ IN UINT16 MaxL1Level,
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT16 CapHeaderOffsetExtd;
+
+ RpBus = 0;
+
+ CapHeaderOffsetExtd = PcieFindExtendedCapId ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, V_PCIE_EX_L1S_CID);
+ RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, CapHeaderOffsetExtd, MaxL1Level);
+}
+
+VOID
+ThunderboltDisableAspmWithoutLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 RootBus;
+ UINT8 RootDev;
+ UINT8 RootFun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+
+ MinBus = 0;
+ MaxBus = 0;
+
+ MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment = (UINT8)RpSegment;
+ RootBus = (UINT8)RpBus;
+ RootDev = (UINT8)RpDevice;
+ RootFun = (UINT8)RpFunction;
+
+ //
+ // Enumerate all the bridges and devices which are available on TBT host controller
+ //
+ for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+ PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFFC, 0x00);
+ } //Fun
+ } //Dev
+ } //Bus
+
+ CapHeaderOffset = PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun, 0x10);
+ NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset);
+}
+
+VOID
+TbtProgramClkReq (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 ClkReqSetup
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINT16 Data16;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function, 0x10);
+
+ //
+ // Check if CLKREQ# is supported
+ //
+ if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) & BIT18) != 0) {
+ Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x010);
+
+ if (ClkReqSetup) {
+ Data16 = Data16 | BIT8; // Enable Clock Power Management
+ } else {
+ Data16 = Data16 & (UINT16)(~BIT8); // Disable Clock Power Management
+ }
+
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010, Data16);
+ }
+}
+VOID
+TbtProgramPtm(
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 PtmSetup,
+ IN BOOLEAN IsRoot
+)
+{
+ UINT64 DeviceBaseAddress;
+ UINT16 CapHeaderOffset;
+ UINT16 PtmControlRegister;
+ UINT16 PtmCapabilityRegister;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus, Device, Function, 0);
+ CapHeaderOffset = PcieFindExtendedCapId(Bus, Device, Function, 0x001F /*V_PCIE_EX_PTM_CID*/);
+ if(CapHeaderOffset != 0) {
+ PtmCapabilityRegister = PciSegmentRead16(DeviceBaseAddress + CapHeaderOffset + 0x04);
+ //
+ // Check if PTM Requester/ Responder capability for the EP/Down stream etc
+ //
+ if ((PtmCapabilityRegister & (BIT1 | BIT0)) != 0) {
+ PtmControlRegister = PciSegmentRead16(DeviceBaseAddress + CapHeaderOffset + 0x08);
+
+ if (PtmSetup) {
+ PtmControlRegister = PtmControlRegister | BIT0; // Enable PTM
+ if(IsRoot) {
+ PtmControlRegister = PtmControlRegister | BIT1; // Enable PTM
+ }
+ PtmControlRegister = PtmControlRegister | (PtmCapabilityRegister & 0xFF00); // Programm Local Clock Granularity
+ } else {
+ PtmControlRegister = PtmControlRegister & (UINT16)(~(BIT0 | BIT1)); // Disable Clock Power Management
+ }
+
+ PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08, PtmControlRegister);
+ }
+ }
+}
+
+VOID
+ConfigureTbtPm (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction,
+ IN UINT8 Configuration // 1- Clk Request , 2- PTM ,
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+
+ MinBus = 0;
+ MaxBus = 0;
+
+ if ((Configuration != 1) && (Configuration != 2)) {
+ return;
+ }
+ MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment = (UINT8)RpSegment;
+ //
+ // Enumerate all the bridges and devices which are available on TBT host controller
+ //
+ for (Bus = MaxBus; Bus >= MinBus; --Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ if (Fun == 0) {
+ //
+ // IF Fun is zero, stop enumerating other functions of the particular bridge
+ //
+ break;
+ }
+ //
+ // otherwise, just skip checking for CLKREQ support
+ //
+ continue;
+ }
+ switch (Configuration) {
+ case 1:
+ TbtProgramClkReq (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtSetClkReq);
+ break;
+ case 2:
+ TbtProgramPtm (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtPtm, FALSE);
+ TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE);
+ break;
+ default:
+ break;
+ }
+ } //Fun
+ } // Dev
+ } // Bus
+}
+
+/**
+ 1) Check LTR support in device capabilities 2 register (bit 11).
+ 2) If supported enable LTR in device control 2 register (bit 10).
+
+**/
+VOID
+TbtProgramLtr (
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 LtrSetup
+ )
+{
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINT16 Data16;
+
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0);
+ CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Device, Function, 0x10);
+
+ //
+ // Check if LTR# is supported
+ //
+ if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) & BIT11) != 0) {
+ Data16 = PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x028);
+
+ if (LtrSetup) {
+ Data16 = Data16 | BIT10; // LTR Mechanism Enable
+ } else {
+ Data16 = Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable
+ }
+
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028, Data16);
+ }
+}
+
+VOID
+ConfigureLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+
+ MinBus = 0;
+ MaxBus = 0;
+
+ MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment = (UINT8)RpSegment;
+ //
+ // Enumerate all the bridges and devices which are available on TBT host controller
+ //
+ for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ if (Fun == 0) {
+ //
+ // IF Fun is zero, stop enumerating other functions of the particular bridge
+ //
+ break;
+ }
+ //
+ // otherwise, just skip checking for LTR support
+ //
+ continue;
+ }
+
+ TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr);
+
+ } //Fun
+ } // Dev
+ } // Bus
+ TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UINT8) mTbtNvsAreaPtr->TbtLtr);
+}
+
+/*
+ US ports and endpoints which declare support must also have the LTR capability structure (cap ID 18h).
+ In this structure you need to enter the max snoop latency and max non-snoop latency in accordance with the format specified in the PCIe spec.
+ The latency value itself is platform specific so you'll need to get it from the platform architect or whatever.
+*/
+VOID
+ThunderboltGetLatencyLtr (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+
+ if(gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PEG) {
+ // PEG selector
+ TbtLtrMaxSnoopLatency = LTR_MAX_SNOOP_LATENCY_VALUE;
+ TbtLtrMaxNoSnoopLatency = LTR_MAX_NON_SNOOP_LATENCY_VALUE;
+ } else if (gCurrentDiscreteTbtRootPortType == DTBT_TYPE_PCH) {
+ // PCH selector
+
+ if (PchSeries == PchLp) {
+ TbtLtrMaxSnoopLatency = 0x1003;
+ TbtLtrMaxNoSnoopLatency = 0x1003;
+ }
+ if (PchSeries == PchH) {
+ TbtLtrMaxSnoopLatency = 0x0846;
+ TbtLtrMaxNoSnoopLatency = 0x0846;
+ }
+ }
+}
+
+VOID
+SetLatencyLtr (
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun,
+ IN UINT16 CapHeaderOffsetExtd,
+ IN UINT16 LtrMaxSnoopLatency,
+ IN UINT16 LtrMaxNoSnoopLatency
+ )
+{
+ UINT64 DeviceBaseAddress;
+ if(CapHeaderOffsetExtd == 0) {
+ return;
+ }
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004, LtrMaxSnoopLatency);
+ PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006, LtrMaxNoSnoopLatency);
+}
+
+VOID
+ThunderboltSetLatencyLtr (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT8 MinBus;
+ UINT8 MaxBus;
+ UINT16 DeviceId;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffsetStd;
+ UINT16 CapHeaderOffsetExtd;
+ UINT16 DevicePortType;
+
+ MinBus = 0;
+ MaxBus = 0;
+
+ MinBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET));
+ MaxBus = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET));
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinBus, 0x00, 0x00, PCI_DEVICE_ID_OFFSET));
+ if (!(IsTbtHostRouter (DeviceId))) {
+ return;
+ }
+
+ TbtSegment = (UINT8)RpSegment;
+
+ for (Bus = MinBus; Bus <= MaxBus; ++Bus) {
+ for (Dev = 0; Dev <= PCI_MAX_DEVICE; ++Dev) {
+ for (Fun = 0; Fun <= PCI_MAX_FUNC; ++Fun) {
+ //
+ // Check for Device availability
+ //
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0);
+ if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
+ //
+ // Device not present
+ //
+ continue;
+ }
+
+ CapHeaderOffsetStd = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10);
+ DevicePortType = (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffsetStd + 0x002) >> 4) & 0xF;
+
+ CapHeaderOffsetExtd = PcieFindExtendedCapId (Bus, Dev, Fun, 0x0018);
+
+ switch (DevicePortType) {
+ case 0:
+ //
+ // PCI Express Endpoint
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 1:
+ //
+ // Legacy PCI Express Endpoint
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 4:
+ //
+ // Root Port of PCI Express Root Complex
+ //
+ // Do-nothing
+ break;
+
+ case 5:
+ //
+ // Upstream Port of PCI Express Switch
+ //
+ SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoopLatency, TbtLtrMaxNoSnoopLatency);
+ break;
+
+ case 6:
+ //
+ // Downstream Port of PCI Express Switch
+ //
+ // Do-nothing
+ break;
+
+ case 7:
+ //
+ // PCI Express to PCI/PCI-X Bridge
+ //
+ // Do-nothing
+ break;
+
+ case 8:
+ //
+ // PCI/PCI-X to PCI Express Bridge
+ //
+ // Do-nothing
+ break;
+
+ case 9:
+ //
+ // Root Complex Integrated Endpoint
+ //
+ // Do-nothing
+ break;
+
+ case 10:
+ //
+ // Root Complex Event Collector
+ //
+ // Do-nothing
+ break;
+
+ default:
+ break;
+ }
+ //
+ // switch(DevicePortType)
+ //
+ }
+ //
+ // Fun
+ //
+ }
+ //
+ // Dev
+ //
+ }
+ //
+ // Bus
+ //
+}
+
+static
+VOID
+Stall (
+ UINTN Usec
+ )
+{
+ UINTN Index;
+ UINT32 Data32;
+ UINT32 PrevData;
+ UINTN Counter;
+
+ Counter = (UINTN) ((Usec * 10) / 3);
+ //
+ // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter tick
+ // periods, thus attempting to ensure Microseconds of stall time.
+ //
+ if (Counter != 0) {
+
+ PrevData = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_TMR);
+ for (Index = 0; Index < Counter;) {
+ Data32 = IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_TMR);
+ if (Data32 < PrevData) {
+ //
+ // Reset if there is a overlap
+ //
+ PrevData = Data32;
+ continue;
+ }
+
+ Index += (Data32 - PrevData);
+ PrevData = Data32;
+ }
+ }
+
+ return ;
+}
+/**
+ Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set GO2SX_NO_WAKE
+ for Tbt devices if WakeupSupport is not present.
+
+ @param[in] DispatchHandle - The unique handle assigned to this handler by SmiHandlerRegister().
+ @param[in] DispatchContext - Points to an optional handler context which was specified when the
+ handler was registered.
+ @param[in, out] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in, out] CommBufferSize - The size of the CommBuffer.
+
+ @retval EFI_SUCCESS - The interrupt was handled successfully.
+**/
+EFI_STATUS
+EFIAPI
+SxDTbtEntryCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT16 DeviceId;
+ UINT8 CableConnected;
+ UINT8 RootportSelected;
+ UINT8 HoustRouteBus;
+ volatile UINT32 *PowerState;
+ UINT32 PowerStatePrev;
+ BOOLEAN SecSubBusAssigned;
+ UINT64 DeviceBaseAddress;
+ UINT8 CapHeaderOffset;
+ UINTN RpDev;
+ UINTN RpFunc;
+ EFI_STATUS Status;
+ UINT32 Timeout;
+ UINT32 RegisterValue;
+ UINT64 Tbt2Pcie;
+ UINTN Index;
+ UINT32 TbtCioPlugEventGpioNo;
+ UINT32 TbtFrcPwrGpioNo;
+ UINT8 TbtFrcPwrGpioLevel;
+ UINT32 TbtPcieRstGpioNo;
+ UINT8 TbtPcieRstGpioLevel;
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext;
+
+ CableConnected = 0;
+ HoustRouteBus = 3;
+ SecSubBusAssigned = FALSE;
+ Timeout = 600;
+ RootportSelected = 0;
+ TbtCioPlugEventGpioNo = 0;
+ TbtFrcPwrGpioNo = 0;
+ TbtFrcPwrGpioLevel = 0;
+ TbtPcieRstGpioNo = 0;
+ TbtPcieRstGpioLevel = 0;
+ Index = 0;
+
+ EntryDispatchContext = (EFI_SMM_SX_REGISTER_CONTEXT*) DispatchContext;
+
+// CableConnected = GetTbtHostRouterStatus ();
+ //SaveTbtHostRouterStatus (CableConnected & 0xF0);
+ //
+ // Get the Power State and Save
+ //
+ if (((mTbtNvsAreaPtr->DTbtControllerEn0 == 0) && (Index == 0))) {
+
+ RootportSelected = mTbtNvsAreaPtr->RootportSelected0;
+ TbtCioPlugEventGpioNo = mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0;
+ TbtFrcPwrGpioNo = mTbtNvsAreaPtr->TbtFrcPwrGpioNo0;
+ TbtFrcPwrGpioLevel = mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0;
+ TbtPcieRstGpioNo = mTbtNvsAreaPtr->TbtPcieRstGpioNo0;
+ TbtPcieRstGpioLevel = mTbtNvsAreaPtr->TbtPcieRstGpioLevel0;
+ }
+
+ Status = GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType, RootportSelected - 1, &RpDev, &RpFunc);
+ ASSERT_EFI_ERROR (Status);
+ CapHeaderOffset = PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev, (UINT8)RpFunc, 0x01);
+ DeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00, (UINT32)RpDev, (UINT32)RpFunc, 0);
+ PowerState = &*((volatile UINT32 *) (mPciExpressBaseAddress + DeviceBaseAddress + CapHeaderOffset + 4)); //PMCSR
+ PowerStatePrev = *PowerState;
+ *PowerState &= 0xFFFFFFFC;
+
+ HoustRouteBus = PciSegmentRead8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ //
+ // Check the Subordinate bus .If it is Zero ,assign temporary bus to
+ // find the device presence .
+ //
+ if (HoustRouteBus == 0) {
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0xF0);
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0xF0);
+ HoustRouteBus = 0xF0;
+ SecSubBusAssigned = TRUE;
+ }
+ //
+ // Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no SCI is getting generated,
+ // This GPIO will be reprogrammed while resuming as part of Platform GPIO Programming.
+ //
+ GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis);
+ //
+ // Read the TBT Host router DeviceID
+ //
+ DeviceId = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment, HoustRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET));
+
+ //
+ // Check For HostRouter Presence
+ //
+ if (IsTbtHostRouter (DeviceId)) {
+ // CableConnected = GetTbtHostRouterStatus ();
+ if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) == (DTBT_SAVE_STATE_OFFSET << Index))) {
+ CableConnected = CableConnected | (DTBT_SAVE_STATE_OFFSET << Index);
+ // SaveTbtHostRouterStatus (CableConnected);
+ }
+ }
+
+ //
+ // Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to apply force power prior to sending mailbox command
+ //
+ GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00, 0x00, Tbt2Pcie)
+ RegisterValue = PciSegmentRead32 (Tbt2Pcie);
+ if (0xFFFFFFFF == RegisterValue) {
+
+ GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel);
+
+ while (Timeout -- > 0) {
+ RegisterValue = PciSegmentRead32 (Tbt2Pcie);
+ if (0xFFFFFFFF != RegisterValue) {
+ break;
+ }
+ Stall(1* (UINTN)1000);
+ }
+ //
+ // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox command for AIC.
+ // However BIOS shall not execute go2sx mailbox command on S5/reboot cycle.
+ //
+
+ if( (EntryDispatchContext->Type == SxS3) || (EntryDispatchContext->Type == SxS4))
+ {
+ if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
+ //Wake Disabled, GO2SX_NO_WAKE Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
+ } else {
+ //Wake Enabled, GO2SX Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
+ }
+ }
+ if (mTbtNvsAreaPtr->TbtFrcPwrEn == 0) {
+ GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel));
+ }
+ } else {
+ //
+ // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox command for AIC.
+ // However BIOS shall not execute go2sx mailbox command on S5/reboot cycle.
+ //
+ if( (EntryDispatchContext->Type == SxS3) || (EntryDispatchContext->Type == SxS4))
+ {
+ if(!mTbtNvsAreaPtr->TbtWakeupSupport) {
+ //Wake Disabled, GO2SX_NO_WAKE Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
+ } else {
+ //Wake Enabled, GO2SX Command
+ TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S_TIMEOUT);
+ }
+ }
+ }
+ *PowerState = PowerStatePrev;
+ //
+ // Restore the bus number in case we assigned temporarily
+ //
+ if (SecSubBusAssigned) {
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 0x00);
+ PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET, 0x00);
+ }
+ if (gDTbtPcieRstSupport) {
+ GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel);
+ }
+ return EFI_SUCCESS;
+}
+
+VOID
+ThunderboltSwSmiCallback (
+ IN UINT8 Type
+ )
+{
+ UINT8 ThunderboltSmiFunction;
+
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n"));
+ ThunderboltSmiFunction = mTbtNvsAreaPtr->ThunderboltSmiFunction;
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback. ThunderboltSmiFunction=%d\n", ThunderboltSmiFunction));
+ if (Type == DTBT_CONTROLLER) {
+ gCurrentDiscreteTbtRootPort = mTbtNvsAreaPtr->CurrentDiscreteTbtRootPort;
+ gCurrentDiscreteTbtRootPortType = mTbtNvsAreaPtr->CurrentDiscreteTbtRootPortType;
+ }
+
+ switch (ThunderboltSmiFunction) {
+ case 21:
+ ThunderboltCallback (Type);
+ break;
+
+ case 22:
+ TbtDisablePCIDevicesAndBridges (Type);
+ break;
+
+ case 23:
+ ConfigureTbtAspm (Type, (UINT16) 0x02);
+ break;
+
+ case 24:
+ ConfigureTbtAspm (Type, (UINT16) 0x01);
+ break;
+
+ default:
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n"));
+}
+STATIC
+EFI_STATUS
+EFIAPI
+DiscreteThunderboltSwSmiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ ThunderboltSwSmiCallback(DTBT_CONTROLLER);
+ return EFI_SUCCESS;
+}
+EFI_STATUS
+TbtRegisterHandlers (
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ UINTN SmiInputValue;
+ EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler;
+ EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler;
+ EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol;
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
+ EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext;
+ EFI_SMM_SW_REGISTER_CONTEXT SwContext;
+ EFI_HANDLE SwDispatchHandle;
+ EFI_HANDLE S3DispatchHandle;
+ EFI_HANDLE S4DispatchHandle;
+ EFI_HANDLE S5DispatchHandle;
+
+ Status = EFI_UNSUPPORTED;
+
+ if(Type == DTBT_CONTROLLER) {
+ SxHandler = SxDTbtEntryCallback;
+ SwHandler = DiscreteThunderboltSwSmiCallback;
+ SmiInputValue = PcdGet8 (PcdSwSmiDTbtEnumerate);
+ gDTbtPcieRstSupport = gTbtInfoHob->DTbtCommonConfig.PcieRstSupport;
+ Status = EFI_SUCCESS;
+ }
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ SwDispatchHandle = NULL;
+ S3DispatchHandle = NULL;
+ S4DispatchHandle = NULL;
+ S5DispatchHandle = NULL;
+
+ Status = gSmst->SmmLocateProtocol (
+ &gEfiSmmSxDispatch2ProtocolGuid,
+ NULL,
+ (VOID **) &SxDispatchProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S3 entry phase call back function
+ //
+ EntryDispatchContext.Type = SxS3;
+ EntryDispatchContext.Phase = SxEntry;
+ Status = SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S3DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S4 entry phase call back function
+ //
+ EntryDispatchContext.Type = SxS4;
+ EntryDispatchContext.Phase = SxEntry;
+ Status = SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S4DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register S5 entry phase call back function
+ //
+ EntryDispatchContext.Type = SxS5;
+ EntryDispatchContext.Phase = SxEntry;
+ Status = SxDispatchProtocol->Register (
+ SxDispatchProtocol,
+ SxHandler,
+ &EntryDispatchContext,
+ &S5DispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Locate the SMM SW dispatch protocol
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gEfiSmmSwDispatch2ProtocolGuid,
+ NULL,
+ (VOID **) &SwDispatch
+ );
+
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register SWSMI handler
+ //
+ SwContext.SwSmiInputValue = SmiInputValue;
+ Status = SwDispatch->Register (
+ SwDispatch,
+ SwHandler,
+ &SwContext,
+ &SwDispatchHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+EFI_STATUS
+InSmmFunction (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ Status = TbtRegisterHandlers(DTBT_CONTROLLER);
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+TbtSmmEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n"));
+
+ mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
+ //
+ // Locate Tbt shared data area
+ //
+ Status = gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **) &TbtNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ mTbtNvsAreaPtr = TbtNvsAreaProtocol->Area;
+
+ //
+ // Get TBT INFO HOB
+ //
+ gTbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+ if (gTbtInfoHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+
+ return InSmmFunction (ImageHandle, SystemTable);
+}
+
+VOID
+EndOfThunderboltCallback (
+ IN UINTN RpSegment,
+ IN UINTN RpBus,
+ IN UINTN RpDevice,
+ IN UINTN RpFunction
+ )
+{
+ if(mTbtNvsAreaPtr->TbtL1SubStates != 0) {
+ ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates, RpSegment, RpBus, RpDevice, RpFunction);
+ }
+ ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1);
+ if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
+ ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ } else { //Aspm enable case
+ ThunderboltEnableAspmWithoutLtr ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSegment, RpBus, RpDevice, RpFunction);
+ }
+
+ if (mTbtNvsAreaPtr->TbtLtr) {
+ ThunderboltGetLatencyLtr ();
+ ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ }
+ ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2);
+} // EndOfThunderboltCallback
+
+VOID
+ConfigureTbtAspm (
+ IN UINT8 Type,
+ IN UINT16 Aspm
+ )
+{
+ UINTN RpSegment = 0;
+ UINTN RpBus = 0;
+ UINTN RpDevice;
+ UINTN RpFunction;
+
+ if(Type == DTBT_CONTROLLER) {
+ if (gCurrentDiscreteTbtRootPort == 0) {
+ return;
+ }
+ GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1, &RpDevice, &RpFunction);
+
+ ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1);
+ if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case
+ ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ } else { //Aspm enable case
+ ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment, RpBus, RpDevice, RpFunction);
+ }
+
+ if (mTbtNvsAreaPtr->TbtLtr) {
+ ThunderboltGetLatencyLtr ();
+ ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ }
+ ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction);
+ } // EndOfThunderboltCallback
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
new file mode 100644
index 0000000000..e3fdd39816
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -0,0 +1,80 @@
+## @file
+# Component information file for the ThunderBolt Smm module.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = TbtSmm
+ FILE_GUID = 5BDCD685-D80A-42E6-9867-A84CCE7F828E
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ PI_SPECIFICATION_VERSION = 1.10
+ ENTRY_POINT = TbtSmmEntryPoint
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ UefiRuntimeServicesTableLib
+ UefiBootServicesTableLib
+ IoLib
+ PciExpressLib
+ HobLib
+ ReportStatusCodeLib
+ PciSegmentLib
+ UefiLib
+ SmmServicesTableLib
+ GpioLib
+ PchInfoLib
+ TbtCommonLib
+ PchPmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+
+[Sources]
+ TbtSmiHandler.h
+ TbtSmiHandler.c
+ TbtSmm.c
+
+[Protocols]
+ gTbtNvsAreaProtocolGuid ## CONSUMES
+ gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES
+ gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
+ gEfiSmmVariableProtocolGuid ## CONSUMES
+ gDxeTbtPolicyProtocolGuid
+
+[Guids]
+ gTbtInfoHobGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[Depex]
+ gEfiSmmBase2ProtocolGuid AND
+ gEfiSmmSxDispatch2ProtocolGuid AND
+ gEfiSmmSwDispatch2ProtocolGuid AND
+ gEfiGlobalNvsAreaProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiSmmVariableProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
new file mode 100644
index 0000000000..e8a160e2af
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c
@@ -0,0 +1,608 @@
+/** @file
+ Source code for the board configuration init function in DXE init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardInitLib.h"
+#include <Library/HobLib.h>
+#include <MemInfoHob.h>
+#include <Library/PchSerialIoLib.h>
+#include <PlatformBoardConfig.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchEspiLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <TbtBoardInfo.h>
+#include <Library/CpuPlatformLib.h>
+#include <GopConfigLib.h>
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+GopVbtSpecificUpdateNull(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+
+//
+// for CFL U DDR4
+//
+VOID
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+
+/**
+ Updates DIMM slots status for Desktop,server and workstation boards
+
+**/
+VOID
+UpdateDimmPopulationConfig(
+ VOID
+ )
+{
+ MEMORY_INFO_DATA_HOB *MemInfo;
+ UINT8 Slot0;
+ UINT8 Slot1;
+ UINT8 Slot2;
+ UINT8 Slot3;
+ CONTROLLER_INFO *ControllerInfo;
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ GuidHob = NULL;
+ MemInfo = NULL;
+
+ GuidHob = GetFirstGuidHob (&gSiMemoryInfoDataGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob != NULL) {
+ MemInfo = (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob);
+ }
+ if (MemInfo != NULL) {
+ if (PcdGet8 (PcdPlatformFlavor) == FlavorDesktop ||
+ PcdGet8 (PcdPlatformFlavor) == FlavorUpServer ||
+ PcdGet8 (PcdPlatformFlavor) == FlavorWorkstation) {
+ ControllerInfo = &MemInfo->Controller[0];
+ Slot0 = ControllerInfo->ChannelInfo[0].DimmInfo[0].Status;
+ Slot1 = ControllerInfo->ChannelInfo[0].DimmInfo[1].Status;
+ Slot2 = ControllerInfo->ChannelInfo[1].DimmInfo[0].Status;
+ Slot3 = ControllerInfo->ChannelInfo[1].DimmInfo[1].Status;
+
+ //
+ // Channel 0 Channel 1
+ // Slot0 Slot1 Slot0 Slot1 - Population AIO board
+ // 0 0 0 0 - Invalid - Invalid
+ // 0 0 0 1 - Valid - Invalid
+ // 0 0 1 0 - Invalid - Valid
+ // 0 0 1 1 - Valid - Valid
+ // 0 1 0 0 - Valid - Invalid
+ // 0 1 0 1 - Valid - Invalid
+ // 0 1 1 0 - Invalid - Invalid
+ // 0 1 1 1 - Valid - Invalid
+ // 1 0 0 0 - Invalid - Valid
+ // 1 0 0 1 - Invalid - Invalid
+ // 1 0 1 0 - Invalid - Valid
+ // 1 0 1 1 - Invalid - Valid
+ // 1 1 0 0 - Valid - Valid
+ // 1 1 0 1 - Valid - Invalid
+ // 1 1 1 0 - Invalid - Valid
+ // 1 1 1 1 - Valid - Valid
+ //
+
+ if ((Slot0 && (Slot1 == 0)) || (Slot2 && (Slot3 == 0))) {
+ PcdSetBoolS (PcdDimmPopulationError, TRUE);
+ }
+ }
+ }
+}
+
+/**
+ Init Misc Platform Board Config Block.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInit (
+ IN UINT16 BoardId
+ )
+{
+// PcdSet64S (PcdFuncBoardHookPlatformSetupOverride, (UINT64) (UINTN) BoardHookPlatformSetup);
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdPssReadSN, TRUE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x04);
+ break;
+ default:
+ PcdSetBoolS (PcdPssReadSN, FALSE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x04);
+ break;
+ }
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Init Platform Board Config Block for ACPI platform.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+InitAcpiPlatformPcd (
+ IN UINT16 BoardId
+ )
+{
+ TBT_INFO_HOB *TbtInfoHob = NULL;
+
+ TbtInfoHob = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
+
+ //
+ // Update OEM table ID
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ if ((TbtInfoHob != NULL) && (TbtInfoHob->DTbtControllerConfig[0].DTbtControllerEn == 1)) {
+ PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', 'c', 'm', 'u', 't', '3'));
+ } else {
+ PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', 'c', 'm', 'u', 'l', '3'));
+ }
+ break;
+ default:
+ PcdSet64S (PcdXhciAcpiTableSignature, 0);
+ break;
+ }
+
+ //
+ // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
+ //
+ PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_MOBILE);
+
+ //
+ // Assign FingerPrint, Gnss, TouchPanel, Audio related GPIO.
+ //
+ switch(BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdFingerPrintSleepGpio, GPIO_CNL_LP_GPP_B17);
+ PcdSet32S (PcdFingerPrintIrqGpio, GPIO_CNL_LP_GPP_B16);
+ //
+ // Configure WWAN Reset pin
+ //
+ PcdSet32S (PcdGnssResetGpio, GPIO_CNL_LP_GPP_F1);
+ PcdSet32S (PcdTouchpanelIrqGpio, GPIO_CNL_LP_GPP_D10);
+ PcdSet32S (PcdTouchpadIrqGpio, GPIO_CNL_LP_GPP_B3);
+ PcdSet32S (PcdHdaI2sCodecIrqGpio, GPIO_CNL_LP_GPP_C8);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Configure GPIOs for discrete USB BT module
+ //
+ switch(BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdBtIrqGpio, GPIO_CNL_LP_GPP_C11);
+ PcdSet32S (PcdBtRfKillGpio, GPIO_CNL_LP_GPP_B4);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Board Specific Init
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS(PcdCmlURtd3TableEnable, TRUE);
+ PcdSet8S (PcdHdaI2sCodecI2cBusNumber, 0); // I2S Audio Codec conntected to I2C0
+ PcdSet8S (PcdBleUsbPortNumber, 9);
+ break;
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Init Common Platform Board Config Block.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+InitCommonPlatformPcd (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB Data64;
+
+ //
+ // Enable EC SMI# for SMI
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdEcSmiGpio, GPIO_CNL_LP_GPP_E3);
+ PcdSet32S (PcdEcLowPowerExitGpio, GPIO_CNL_LP_GPP_B23);
+ break;
+ };
+
+ //
+ // HID I2C Interrupt GPIO.
+ //
+ switch (BoardId) {
+ default:
+ // on all supported boards interrupt input is on same GPIO pad. How convenient.
+ PcdSet32S (PcdHidI2cIntPad, GPIO_CNL_LP_GPP_D10);
+ break;
+ }
+
+ //
+ // PS2 KB Specific Init for Sds Serial platform.
+ //
+ if (BoardId == BoardIdCometLakeULpddr3Rvp) {
+ PcdSetBoolS (PcdDetectPs2KbOnCmdAck, TRUE);
+ } else {
+ PcdSetBoolS (PcdDetectPs2KbOnCmdAck, FALSE);
+ }
+
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdSpdAddressOverride, FALSE);
+ break;
+ }
+
+ //
+ // DDISelection
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdDDISelection, 1);
+ break;
+ default:
+ PcdSet8S (PcdDDISelection, 0);
+ break;
+ }
+
+ //
+ // GFX Detect
+ //
+ switch (BoardId) {
+ default:
+ // Not all the boards support GFX_CRB_DET. This is not an error.
+ Data64.BoardGpioConfig.Type = BoardGpioTypeNotSupported;
+ break;
+ }
+
+ PcdSet64S (PcdGfxCrbDetectGpio, Data64.Blob);
+
+ //
+ // USB Type-C
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS(PcdUsbTypeCSupport, TRUE);
+ // Discete Ports
+ PcdSet8S(PcdTypeCPortsSupported, 2);
+ // TBT Port 1 mapping and properties [TBT AIC]
+ PcdSet8S(PcdUsbTypeCPort1, 1);
+ PcdSet8S(PcdUsbTypeCPort1Pch, 5);
+ // TBT Port 2 mapping and properties [TBT AIC]
+ PcdSet8S(PcdUsbTypeCPort2, 2);
+ PcdSet8S(PcdUsbTypeCPort2Pch, 7);
+ break;
+ default:
+ PcdSetBoolS (PcdUsbTypeCSupport, FALSE);
+ break;
+ }
+
+ //
+ // Battery Present
+ //
+ switch (BoardId) {
+ default:
+ PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VIRTUAL_BATTERY_SUPPORTED);
+ break;
+ }
+
+ //
+ // TS-on-DIMM temperature
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdTsOnDimmTemperature, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdTsOnDimmTemperature, FALSE);
+ break;
+ }
+ //
+ // Real Battery 1 Control & Real Battery 2 Control
+ //
+ PcdSet8S (PcdRealBattery1Control, 1);
+ PcdSet8S (PcdRealBattery2Control, 2);
+
+ //
+ // Mipi Camera Sensor
+ //
+ PcdSetBoolS (PcdMipiCamSensor, FALSE);
+ //
+ // Mipi Camera Sensor Link Used
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdMipiCam0LinkUsed, 3);
+ PcdSet8S (PcdMipiCam1LinkUsed, 6);
+ PcdSet8S (PcdMipiCam2LinkUsed, 9);
+ PcdSet8S (PcdMipiCam3LinkUsed, 7);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // H8S2113 SIO
+ //
+ switch(BoardId) {
+ default:
+ PcdSetBoolS (PcdH8S2113SIO, FALSE);
+ break;
+ }
+
+
+ //
+ // NCT6776F COM, SIO & HWMON
+ //
+ PcdSetBoolS (PcdNCT6776FCOM, FALSE);
+ PcdSetBoolS (PcdNCT6776FSIO, FALSE);
+ PcdSetBoolS (PcdNCT6776FHWMON, FALSE);
+
+ //
+ // SMC Runtime Sci Pin
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdSmcRuntimeSciPin, (UINT32) GPIO_CNL_LP_GPP_E16);
+ break;
+ default:
+ PcdSet32S (PcdSmcRuntimeSciPin, 0x00);
+ break;
+ }
+
+ //
+ // Convertable Dock Support
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdConvertableDockSupport, FALSE);
+ break;
+ }
+
+ //
+ // Ec Hotkey F3, F4, F5, F6, F7 and F8 Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdEcHotKeyF3Support, 1);
+ PcdSet8S (PcdEcHotKeyF4Support, 1);
+ PcdSet8S (PcdEcHotKeyF5Support, 1);
+ PcdSet8S (PcdEcHotKeyF6Support, 1);
+ PcdSet8S (PcdEcHotKeyF7Support, 1);
+ PcdSet8S (PcdEcHotKeyF8Support, 1);
+ break;
+ default:
+ PcdSet8S (PcdEcHotKeyF3Support, 0);
+ PcdSet8S (PcdEcHotKeyF4Support, 0);
+ PcdSet8S (PcdEcHotKeyF5Support, 0);
+ PcdSet8S (PcdEcHotKeyF6Support, 0);
+ PcdSet8S (PcdEcHotKeyF7Support, 0);
+ PcdSet8S (PcdEcHotKeyF8Support, 0);
+ break;
+ }
+
+ //
+ // Virtual Button Volume Up & Done Support
+ // Virtual Button Home Button Support
+ // Virtual Button Rotation Lock Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
+ break;
+ default:
+ PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE);
+ PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE);
+ break;
+ }
+
+ //
+ // Slate Mode Switch Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdSlateModeSwitchSupport, FALSE);
+ break;
+ }
+
+ //
+ // Ac Dc Auto Switch Support
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdAcDcAutoSwitchSupport, TRUE);
+ break;
+ }
+
+ //
+ // Pm Power Button Gpio Pin
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdPmPowerButtonGpioPin, (UINT32) GPIO_CNL_LP_GPD3);
+ break;
+ default:
+ PcdSet32S (PcdPmPowerButtonGpioPin, 0x00);
+ break;
+ }
+
+ //
+ // Acpi Enable All Button Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdAcpiEnableAllButtonSupport, FALSE);
+ break;
+ }
+
+ //
+ // Acpi Hid Driver Button Support
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE);
+ break;
+ default:
+ PcdSetBoolS (PcdAcpiHidDriverButtonSupport, FALSE);
+ break;
+ }
+
+ //
+ // USB Type C EC less
+ //
+ switch (BoardId) {
+ default:
+ PcdSetBoolS (PcdUsbTypeCEcLess, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Check if given rootport has device connected and enable wake capability
+
+ @param[in] RpNum An unsigned integer represent the root port number.
+
+ @retval TRUE if endpoint was connected
+ @retval FALSE if no endpoint was detected
+**/
+BOOLEAN
+IsPcieEndPointPresent (
+ IN UINT8 RpNum
+ )
+{
+ EFI_STATUS Status;
+ UINTN RpDev;
+ UINTN RpFun;
+ UINT64 RpBaseAddress;
+
+ Status = GetPchPcieRpDevFun (RpNum, &RpDev, &RpFun);
+ if (!EFI_ERROR (Status)) {
+ //
+ // check if device is present
+ //
+ RpBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ RpDev,
+ RpFun,
+ 0
+ );
+
+ if ((PciSegmentRead16 (RpBaseAddress) != 0xFFFF) &&
+ (PciSegmentRead16 (RpBaseAddress + R_PCH_PCIE_CFG_SLSTS) & B_PCIE_SLSTS_PDS)) {
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+
+}
+
+/**
+ Enable Tier2 GPIO Sci wake capability.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+Tier2GpioWakeSupport (
+ IN UINT16 BoardId
+ )
+{
+ BOOLEAN Tier2GpioWakeEnable;
+
+ Tier2GpioWakeEnable = FALSE;
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ //
+ // Root port #14: M.2 WLAN
+ //
+ if (IsPcieEndPointPresent (13)) {
+ Tier2GpioWakeEnable = TRUE;
+ }
+ break;
+ default:
+ break;
+ }
+ PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board configuration init function for DXE phase.
+
+ @param Content pointer to the buffer contain init information for board init.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardConfigInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId = BoardIdCometLakeULpddr3Rvp;
+
+ Status = InitAcpiPlatformPcd (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = InitCommonPlatformPcd (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = BoardMiscInit (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = Tier2GpioWakeSupport (BoardId);
+ ASSERT_EFI_ERROR(Status);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.h
new file mode 100644
index 0000000000..f2eb75b9f3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for board Init function for DXE Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_BOARD_INIT_LIB_H_
+#define _DXE_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <Register/PchRegs.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Platform.h>
+
+EFI_STATUS
+EFIAPI
+BoardConfigInit (
+ VOID
+ );
+
+#endif // _DXE_BOARD_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.c
new file mode 100644
index 0000000000..0d58b73063
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.c
@@ -0,0 +1,46 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <CpuPolicyInitDxe.h>
+
+DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
+
+/**
+ Initialize Intel CPU DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ ZeroMem(&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
+ mCpuPolicyData.Revision = DXE_CPU_POLICY_PROTOCOL_REVISION;
+
+ UpdateDxeSiCpuPolicy(&mCpuPolicyData);
+
+ //
+ // Install CpuInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = CpuInstallPolicyProtocol(ImageHandle, &mCpuPolicyData);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.h
new file mode 100644
index 0000000000..0857ca6f0e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitDxe.h
@@ -0,0 +1,38 @@
+/** @file
+ Header file for the SiliconPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_POLICY_INIT_DXE_H_
+#define _CPU_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <Protocol/CpuPolicyProtocol.h>
+#include <Library/DxeCpuPolicyUpdateLib.h>
+
+
+/**
+ Initialize Intel CPU DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c
new file mode 100644
index 0000000000..7dcae32069
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c
@@ -0,0 +1,174 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "GopPolicyInitDxe.h"
+#include <Protocol/GopPolicy.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0;
+
+//
+// Function implementations
+//
+
+/**
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ @param[out] CurrentDockStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+GetPlatformDockStatus (
+ OUT DOCK_STATUS CurrentDockStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+
+ @param[out] VbtAddress
+ @param[out] VbtSize
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+**/
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_STATUS Status;
+ UINTN FvProtocolCount;
+ EFI_HANDLE *FvHandles;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINTN Index;
+ UINT32 AuthenticationStatus;
+ UINT8 *Buffer;
+ UINTN VbtBufferSize;
+
+ Status = EFI_NOT_FOUND;
+ if ( mVbtAddress == 0) {
+ Fv = NULL;
+ Buffer = 0;
+ FvHandles = NULL;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvProtocolCount,
+ &FvHandles
+ );
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < FvProtocolCount; Index++) {
+ Status = gBS->HandleProtocol (
+ FvHandles[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+ VbtBufferSize = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
+ EFI_SECTION_RAW,
+ 0,
+ (VOID **) &Buffer,
+ &VbtBufferSize,
+ &AuthenticationStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
+ *VbtSize = (UINT32)VbtBufferSize;
+ mVbtAddress = *VbtAddress;
+ mVbtSize = *VbtSize;
+ Status = EFI_SUCCESS;
+ break;
+ }
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+
+ if (FvHandles != NULL) {
+ FreePool (FvHandles);
+ FvHandles = NULL;
+ }
+ } else {
+ *VbtAddress = mVbtAddress;
+ *VbtSize = mVbtSize;
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle Image handle of this driver.
+
+@retval EFI_SUCCESS Initialization complete.
+@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Initialize the EFI Driver Library
+ //
+ SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
+
+ mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03;
+ mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
+ mGOPPolicy.GetVbtData = GetVbtData;
+ mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus;
+
+ //
+ // Install protocol to allow access to this Policy.
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gGopPolicyProtocolGuid,
+ &mGOPPolicy,
+ NULL
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h
new file mode 100644
index 0000000000..0c90e68d38
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h
@@ -0,0 +1,41 @@
+/** @file
+Header file for the GopPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GOP_POLICY_INIT_DXE_H_
+#define _GOP_POLICY_INIT_DXE_H_
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <Library/PcdLib.h>
+
+/**
+Initialize GOP DXE Policy
+
+@param[in] ImageHandle Image handle of this driver.
+
+@retval EFI_SUCCESS Initialization complete.
+@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe(
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.c
new file mode 100644
index 0000000000..9de7d6b446
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.c
@@ -0,0 +1,55 @@
+/** @file
+ This file is SampleCode for PCH DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PchPolicyInitDxe.h"
+
+//
+// Function implementations
+//
+
+/**
+ Initialize PCH DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PchPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ PCH_POLICY_PROTOCOL *PchPolicy;
+
+ //
+ // Call CreatePchDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreatePchDxeConfigBlocks (&PchPolicy);
+ DEBUG((DEBUG_INFO, "PchPolicy->TableHeader.NumberOfBlocks = 0x%x\n", PchPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ if (mFirmwareConfiguration != FwConfigDefault) {
+ UpdateDxePchPolicy (PchPolicy);
+ }
+
+ //
+ // Install PchInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = PchInstallPolicyProtocol (ImageHandle, PchPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.h
new file mode 100644
index 0000000000..479e7434e3
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitDxe.h
@@ -0,0 +1,52 @@
+/** @file
+ Header file for the PchPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_POLICY_INIT_DXE_H_
+#define _PCH_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <FirwmareConfigurations.h>
+#include <Protocol/PchPolicy.h>
+#include <Library/DxePchPolicyLib.h>
+#include <Library/DxePchPolicyUpdateLib.h>
+
+extern UINT8 mFirmwareConfiguration;
+
+/**
+ <b>PCH DXE Policy Driver Entry Point</b> \n
+ - <b>Introduction</b> \n
+ Pch DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
+ Platform policy Protocol is initialized with default settings in this funciton.
+ This policy Protocol has to be initialized prior to PCH initialization DXE drivers execution.
+
+ - @pre
+ - Runtime variable service should be ready if policy initialization required.
+
+ - @result
+ PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch reference code use.
+
+ - <b>Porting Recommendations</b> \n
+ Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PchPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c
new file mode 100644
index 0000000000..27bd7fb9ae
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c
@@ -0,0 +1,88 @@
+/** @file
+ This file is a wrapper for Platform Policy driver. Get Setup
+ Value to initialize Intel DXE Platform Policy.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PolicyInitDxe.h"
+#include <CpuSmm.h>
+#include "BoardInitLib.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFirmwareConfiguration = 0;
+
+/**
+ Initialize DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = BoardConfigInit();
+
+ mFirmwareConfiguration = FwConfigProduction;
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status = SaPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // PCH Dxe Platform Policy Initialization
+ //
+ Status = PchPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "PCH Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Silicon Dxe Platform Policy Initialization
+ //
+ Status = SiliconPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // CPU DXE Platform Policy Initialization
+ //
+ Status = CpuPolicyInitDxe (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization done\n"));
+ ASSERT_EFI_ERROR (Status);
+
+
+ if (PcdGetBool(PcdIntelGopEnable)) {
+ //
+ // GOP Dxe Policy Initialization
+ //
+ Status = GopPolicyInitDxe(ImageHandle);
+ DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
+ ASSERT_EFI_ERROR(Status);
+ }
+ if (PcdGetBool(PcdTbtEnable)) {
+ //
+ // Update TBT Policy
+ //
+ Status = InstallTbtPolicy (ImageHandle);
+ DEBUG ((DEBUG_INFO, "Install Tbt Policy done\n"));
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return Status;
+
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h
new file mode 100644
index 0000000000..5a03dff12e
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for the PolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _POLICY_INIT_DXE_H_
+#define _POLICY_INIT_DXE_H_
+
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#include "SaPolicyInitDxe.h"
+#include "PchPolicyInitDxe.h"
+#include "SiliconPolicyInitDxe.h"
+#include "GopPolicyInitDxe.h"
+#include "CpuPolicyInitDxe.h"
+
+#include <Library/DxeTbtPolicyLib.h>
+/**
+ Initialize DXE Platform Policy
+
+ @param[in] ImageHandle - Image handle of this driver.
+ @param[in] SystemTable - Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+
+EFI_STATUS
+EFIAPI
+PolicyInitDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
new file mode 100644
index 0000000000..1d09b990b1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
@@ -0,0 +1,176 @@
+## @file
+# Module Information file for the PolicyInit DXE driver.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PolicyInitDxe
+ FILE_GUID = 490D0119-4448-440D-8F5C-F58FB53EE057
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = PolicyInitDxeEntryPoint
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ CpuPlatformLib
+ DebugLib
+ DxeServicesTableLib
+ IoLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ DxePchPolicyLib
+ PcdLib
+ DxePolicyBoardConfigLib
+ DxePolicyUpdateLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ UefiRuntimeServicesTableLib
+ ConfigBlockLib
+ DevicePathLib
+ DxeTbtPolicyLib
+ PchPcieRpLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable
+ gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication ## CONSUMES
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support
+
+ #
+ # PSS Board Configuration.
+ #
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio
+
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed
+ gPlatformModuleTokenSpaceGuid.PcdH8S2113Present
+ gPlatformModuleTokenSpaceGuid.PcdNat87393Present
+ gPlatformModuleTokenSpaceGuid.PcdNct677FPresent
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCmlURtd3TableEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate
+
+[Sources]
+ PolicyInitDxe.c
+ SaPolicyInitDxe.c
+ SiliconPolicyInitDxe.c
+ GopPolicyInitDxe.c
+ PchPolicyInitDxe.c
+ CpuPolicyInitDxe.c
+ BoardInitLib.c
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gDxeMePolicyGuid ## PRODUCES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gPchPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+ gDxeCpuPolicyProtocolGuid ## PRODUCES
+
+[Guids]
+ gCpuSmmGuid ## CONSUMES
+ gSiMemoryInfoDataGuid
+
+[Depex]
+ gEfiVariableArchProtocolGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c
new file mode 100644
index 0000000000..4cef26d297
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c
@@ -0,0 +1,60 @@
+/** @file
+ This file is SampleCode for SA DXE Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SaPolicyInitDxe.h"
+
+
+//
+// Function implementations
+//
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks(&SaPolicy);
+ DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR(Status);
+
+ UpdateDxeSaPolicyBoardConfig (SaPolicy);
+
+ if (mFirmwareConfiguration != FwConfigDefault) {
+
+ UpdateDxeSaPolicy (SaPolicy);
+ }
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h
new file mode 100644
index 0000000000..c9f042b40a
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h
@@ -0,0 +1,56 @@
+/** @file
+ Header file for the SaPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SA_POLICY_INIT_DXE_H_
+#define _SA_POLICY_INIT_DXE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <FirwmareConfigurations.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/DxeSaPolicyLib.h>
+#include <Library/DxePolicyBoardConfigLib.h>
+#include <Library/DxeSaPolicyUpdateLib.h>
+
+#include <SaAccess.h>
+
+extern UINT8 mFirmwareConfiguration;
+
+/**
+ <b>SA DXE Policy Driver Entry Point</b> \n
+ - <b>Introduction</b> \n
+ System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
+ Platform policy Protocol is initialized with default settings in this funciton.
+ This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
+
+ - @pre
+ - Runtime variable service should be ready if policy initialization required.
+
+ - @result
+ SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
+
+ - <b>Porting Recommendations</b> \n
+ Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.c b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.c
new file mode 100644
index 0000000000..24e165f645
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.c
@@ -0,0 +1,46 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <SiliconPolicyInitDxe.h>
+#include <Library/BaseLib.h>
+
+DXE_SI_POLICY_PROTOCOL mSiPolicyData = { 0 };
+
+/**
+ Initilize Intel Cpu DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ mSiPolicyData.Revision = DXE_SI_POLICY_PROTOCOL_REVISION;
+
+ ///
+ /// Install the DXE_SI_POLICY_PROTOCOL interface
+ ///
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeSiPolicyProtocolGuid,
+ &mSiPolicyData,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.h b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.h
new file mode 100644
index 0000000000..1324ad0808
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyInitDxe.h
@@ -0,0 +1,37 @@
+/** @file
+ Header file for the SiliconPolicyInitDxe Driver.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SILICON_POLICY_INIT_DXE_H_
+#define _SILICON_POLICY_INIT_DXE_H_
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+#include <Protocol/SiPolicyProtocol.h>
+
+/**
+ Initilize Intel CPU DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
+
--
2.16.2.windows.1


[edk2-platforms] [PATCH v2 4/7] CometlakeOpenBoardPkg/CometlakeURvp: Add library instances

Kathappan Esakkithevar
 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

CometlakeURvp library instances.

* BaseFuncLib - Board-specific VBT update routines.
* BaseGpioCheckConflictLib - Identifies GPIO pad conflicts.
* BaseGpioCheckConflictLibNull - NULL library instance.
* BasePlatformHookLib - Serial port initialization support.
* DxePolicyBoardConfigLib - Board-specific silicon policy configuration
in DXE.
* PeiBoardInitPostMemLib - PEI post-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization.
This library implements board APIs declared in MinPlatformPkg.
* PeiPlatformHookLib - PEI board instance-specifc GPIO init.
* PeiPolicyBoardConfigLib - Board instance-specific policy init in PEI.
* SmmBoardAcpiEnableLib - Board instance-specific SMM ACPI enable support.
* SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@...>
Cc: Prince Agyeman <prince.agyeman@...>
---
.../Library/BaseFuncLib/BaseFuncLib.inf | 33 +
.../CometlakeURvp/Library/BaseFuncLib/Gop.c | 41 +
.../BaseGpioCheckConflictLib.c | 137 +
.../BaseGpioCheckConflictLib.inf | 35 +
.../BaseGpioCheckConflictLibNull.c | 37 +
.../BaseGpioCheckConflictLibNull.inf | 32 +
.../BasePlatformHookLib/BasePlatformHookLib.c | 156 +
.../BasePlatformHookLib/BasePlatformHookLib.inf | 53 +
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 +
.../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 +
.../BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c | 40 +
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 82 +
.../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 50 +
.../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 ++
.../CometlakeURvp/Library/BoardInitLib/BoardFunc.c | 19 +
.../CometlakeURvp/Library/BoardInitLib/BoardFunc.h | 20 +
.../Library/BoardInitLib/BoardFuncInit.c | 26 +
.../Library/BoardInitLib/BoardFuncInitPreMem.c | 40 +
.../Library/BoardInitLib/BoardInitLib.h | 20 +
.../Library/BoardInitLib/BoardPchInitPreMemLib.c | 398 +++
.../Library/BoardInitLib/BoardSaConfigPreMem.h | 83 +
.../Library/BoardInitLib/BoardSaInitPreMemLib.c | 383 +++
.../BoardInitLib/CometlakeURvpHsioPtssTables.c | 32 +
.../Library/BoardInitLib/CometlakeURvpInit.h | 41 +
.../BoardInitLib/GpioTableCmlUlpddr3PreMem.c | 43 +
.../BoardInitLib/GpioTableCometlakeULpddr3Rvp.c | 254 ++
.../Library/BoardInitLib/GpioTableDefault.c | 213 ++
.../Library/BoardInitLib/PchHdaVerbTables.h | 3014 ++++++++++++++++++++
.../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 40 +
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 57 +
.../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 106 +
.../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 118 +
.../Library/BoardInitLib/PeiCometlakeURvpDetect.c | 63 +
.../BoardInitLib/PeiCometlakeURvpInitPostMemLib.c | 436 +++
.../BoardInitLib/PeiCometlakeURvpInitPreMemLib.c | 562 ++++
.../BoardInitLib/PeiMultiBoardInitPostMemLib.c | 41 +
.../BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 207 ++
.../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 +
.../BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 300 ++
.../DxePolicyBoardConfigLib/DxePolicyBoardConfig.h | 19 +
.../DxePolicyBoardConfigLib.inf | 45 +
.../DxeSaPolicyBoardConfig.c | 36 +
.../PeiPlatformHookLib/PeiPlatformHooklib.c | 299 ++
.../PeiPlatformHookLib/PeiPlatformHooklib.inf | 95 +
.../PeiCpuPolicyBoardConfig.c | 49 +
.../PeiCpuPolicyBoardConfigPreMem.c | 29 +
.../PeiMePolicyBoardConfig.c | 36 +
.../PeiMePolicyBoardConfigPreMem.c | 37 +
.../PeiPchPolicyBoardConfig.c | 36 +
.../PeiPchPolicyBoardConfigPreMem.c | 37 +
.../PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h | 22 +
.../PeiPolicyBoardConfigLib.inf | 71 +
.../PeiSaPolicyBoardConfig.c | 36 +
.../PeiSaPolicyBoardConfigPreMem.c | 37 +
.../PeiSiPolicyBoardConfig.c | 27 +
55 files changed, 8489 insertions(+)
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/BaseFuncLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/Gop.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInit.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardInitLib.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpInit.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableDefault.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PchHdaVerbTables.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpDetect.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/BaseFuncLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/BaseFuncLib.inf
new file mode 100644
index 0000000000..2dad67a1e5
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/BaseFuncLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component information file for Board Functions Library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseBoardFuncInitLib
+ FILE_GUID = 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Packages]
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ Gop.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/Gop.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/Gop.c
new file mode 100644
index 0000000000..8b8089c3c0
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLib/Gop.c
@@ -0,0 +1,41 @@
+/** @file
+ Others Board's PCD function hook.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <GopConfigLib.h>
+
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+EFIAPI
+GopVbtSpecificUpdateNull (
+ IN CHILD_STRUCT **ChildStructPtr
+ )
+{
+ return;
+}
+
+//
+// for CFL U DDR4
+//
+VOID
+EFIAPI
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+)
+{
+ ChildStructPtr[1]->DeviceClass = DISPLAY_PORT_ONLY;
+ ChildStructPtr[1]->DVOPort = DISPLAY_PORT_B;
+ ChildStructPtr[2]->DeviceClass = DISPLAY_PORT_HDMI_DVI_COMPATIBLE;
+ ChildStructPtr[2]->DVOPort = DISPLAY_PORT_C;
+ ChildStructPtr[2]->AUX_Channel = AUX_CHANNEL_C;
+ ChildStructPtr[3]->DeviceClass = NO_DEVICE;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
new file mode 100644
index 0000000000..e42bb7cb91
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
@@ -0,0 +1,137 @@
+/** @file
+ Implementation of BaseGpioCheckConflictLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Private/Library/GpioPrivateLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+
+ @retval none.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ EFI_HOB_GUID_TYPE *GpioCheckConflictHob;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT32 HobDataSize;
+ UINT32 GpioCount;
+ UINT32 GpioIndex;
+ GPIO_CONFIG GpioActualConfig;
+
+ GpioCheckConflictHob = NULL;
+ GpioCheckConflictHobData = NULL;
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n"));
+
+ //
+ //Use Guid to find HOB.
+ //
+ GpioCheckConflictHob = (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCheckConflictHobGuid);
+ if (GpioCheckConflictHob == NULL) {
+ DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n"));
+ } else {
+ while (GpioCheckConflictHob != NULL) {
+ //
+ // Find the Data area pointer and Data size from the Hob
+ //
+ GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DATA (GpioCheckConflictHob);
+ HobDataSize = GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob);
+
+ GpioCount = HobDataSize / sizeof (GPIO_PAD_MODE_INFO);
+ DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount = %d\n", GpioCount));
+
+ //
+ // Probe Gpio entries in Hob and compare which are conflicted
+ //
+ for (GpioIndex = 0; GpioIndex < GpioCount ; GpioIndex++) {
+ GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &GpioActualConfig);
+ if (GpioCheckConflictHobData[GpioIndex].GpioPadMode != GpioActualConfig.PadMode) {
+ DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad)));
+ }
+ }
+ //
+ // Find next Hob and return the Hob pointer by the specific Hob Guid
+ //
+ GpioCheckConflictHob = GET_NEXT_HOB (GpioCheckConflictHob);
+ GpioCheckConflictHob = GetNextGuidHob (&gGpioCheckConflictHobGuid, GpioCheckConflictHob);
+ }
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n"));
+ }
+
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+ @retval none.
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+
+ UINT32 Index;
+ UINT32 GpioIndex;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT16 GpioCount;
+
+ GpioCount = 0;
+ GpioIndex = 0;
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n"));
+
+ for (Index = 0; Index < GpioTableCount ; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
+ continue;
+ } else {
+ //
+ // Calculate how big size the Hob Data needs
+ //
+ GpioCount++;
+ }
+ }
+
+ //
+ // Build a HOB tagged with a GUID for identification and returns
+ // the start address of GUID HOB data.
+ //
+ GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpioCheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO));
+
+ //
+ // Record Non Default Gpio entries to the Hob
+ //
+ for (Index = 0; Index < GpioTableCount; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
+ continue;
+ } else {
+ GpioCheckConflictHobData[GpioIndex].GpioPad = GpioDefinition[Index].GpioPad;
+ GpioCheckConflictHobData[GpioIndex].GpioPadMode = GpioDefinition[Index].GpioConfig.PadMode;
+ GpioIndex++;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n"));
+ return;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
new file mode 100644
index 0000000000..a95faa200f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BaseGpioCheckConflictLib
+ FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLib.c
+
+[Guids]
+ gGpioCheckConflictHobGuid
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
new file mode 100644
index 0000000000..525a9b3e0f
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
@@ -0,0 +1,37 @@
+/** @file
+ Implementation of BaseGpioCheckConflicLibNull.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ return;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
new file mode 100644
index 0000000000..0a028ef0ca
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
@@ -0,0 +1,32 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BaseGpioCheckConflictLibNull
+ FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLibNull.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..a80e790a86
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,156 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <SystemAgent/Include/SaAccess.h>
+#include <SioRegs.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PchRegsLpc.h>
+#include <PchAccess.h>
+
+#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E
+#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F
+
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55
+#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55
+#define IT8628_EXIT_CONFIG 0x2
+#define IT8628_CHIPID_BYTE1 0x86
+#define IT8628_CHIPID_BYTE2 0x28
+
+typedef struct {
+ UINT8 Register;
+ UINT8 Value;
+} EFI_SIO_TABLE;
+
+//
+// IT8628
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = {
+ {0x023, 0x09}, // Clock Selection register
+ {0x007, 0x01}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register
+ {0x060, 0x03}, // Serial Port 1 Base Address LSB Register
+ {0x070, 0x04}, // Serial Port 1 Interrupt Level Select
+ {0x030, 0x01}, // Serial Port 1 Activate
+ {0x007, 0x02}, // Com1 Logical Device Number select
+ {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register
+ {0x060, 0x02}, // Serial Port 2 Base Address MSB Register
+ {0x070, 0x03}, // Serial Port 2 Interrupt Level Select
+ {0x030, 0x01} // Serial Port 2 Activate
+};
+
+/**
+ Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports
+**/
+STATIC
+VOID
+It8628SioSerialPortInit (
+ VOID
+ )
+{
+ UINT8 ChipId0;
+ UINT8 ChipId1;
+ UINT16 LpcIoDecondeRangeSet;
+ UINT16 LpcIoDecoodeSet;
+ UINT8 Index;
+ UINT64 LpcBaseAddr;
+
+ ChipId0 = 0;
+ ChipId1 = 0;
+ LpcIoDecondeRangeSet = 0;
+ LpcIoDecoodeSet = 0;
+
+ //
+ // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh.
+ //
+ LpcBaseAddr = PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+
+ LpcIoDecondeRangeSet = (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOD);
+ LpcIoDecoodeSet = (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOE);
+ PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet | ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8)));
+ PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE)));
+
+ //
+ // Enter MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2);
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3);
+
+ //
+ // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);
+ ChipId0 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);
+ ChipId1 = IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);
+
+ //
+ // Enable Serial Port 1, Port 2
+ //
+ if ((ChipId0 == IT8628_CHIPID_BYTE1) && (ChipId1 == IT8628_CHIPID_BYTE2)) {
+ for (Index = 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof (EFI_SIO_TABLE); Index++) {
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Register);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Index].Value);
+ }
+ }
+
+ //
+ // Exit MB PnP Mode
+ //
+ IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);
+ IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);
+
+ return;
+}
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ // Configure Sio IT8628
+ It8628SioSerialPortInit ();
+
+ return RETURN_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..ca723a92cb
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Platform Hook Library instance for Cometlake Mobile/Desktop CRB.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSUMES
+
+[FixedPcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
new file mode 100644
index 0000000000..a1ed0230ed
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
@@ -0,0 +1,63 @@
+/** @file
+ Comet Lake U LP3 SMM Board ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return CometlakeURvpBoardEnableAcpi(EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return CometlakeURvpBoardDisableAcpi(DisableSci);
+}
+
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
new file mode 100644
index 0000000000..d67ac1885c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
@@ -0,0 +1,50 @@
+## @file
+# Comet Lake U LP3 SMM Board ACPI Enable library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmBoardAcpiEnableLib
+ FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = BoardAcpiEnableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ MmPciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmCometlakeURvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmBoardAcpiEnableLib.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c
new file mode 100644
index 0000000000..b0d431a08c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c
@@ -0,0 +1,40 @@
+/** @file
+ Comet Lake LP3 SMM Board ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi(
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi(
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..e0d8645f29
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,82 @@
+/** @file
+ Comet Lake U LP3 SMM Multi-Board ACPI Support library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardEnableAcpi(
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpBoardDisableAcpi(
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return CometlakeURvpBoardEnableAcpi(EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+CometlakeURvpMultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return CometlakeURvpBoardDisableAcpi(DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mCometlakeURvpBoardAcpiEnableFunc = {
+ CometlakeURvpMultiBoardEnableAcpi,
+ CometlakeURvpMultiBoardDisableAcpi,
+};
+
+EFI_STATUS
+EFIAPI
+SmmCometlakeURvpMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdCometLakeULpddr3Rvp) {
+ return RegisterBoardAcpiEnableFunc (&mCometlakeURvpBoardAcpiEnableFunc);
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..b23485be2b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,50 @@
+## @file
+# Comet Lake U LP3 SMM Multi-Board ACPI Support library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmCometlakeURvpMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmCometlakeURvpMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CometlakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmCometlakeURvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..ffa8738d6b
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,170 @@
+/** @file
+ Comet Lake U LP3 SMM Silicon ACPI Enable library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PchAccess.h>
+#include <Library/MmPciLib.h>
+#include <Library/PmcLib.h>
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS(
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.c
new file mode 100644
index 0000000000..fa6a186045
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.c
@@ -0,0 +1,19 @@
+/** @file
+ Board's PCD function hook.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+EFI_STATUS
+PeiBoardSpecificInitPostMemNull (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.h
new file mode 100644
index 0000000000..9e8930755d
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFunc.h
@@ -0,0 +1,20 @@
+/** @file
+ Header file for Board Hook function intance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BOARD_FUNC_H_
+#define _BOARD_FUNC_H_
+
+#include <Uefi.h>
+
+EFI_STATUS
+PeiBoardSpecificInitPostMemNull (
+ VOID
+ );
+
+#endif // _BOARD_FUNC_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInit.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInit.c
new file mode 100644
index 0000000000..43896af760
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInit.c
@@ -0,0 +1,26 @@
+/** @file
+ Source code for the board configuration init function in Post Memory init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardFunc.h"
+
+/**
+ Board's PCD function hook init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardFunctionInit (
+ IN UINT16 BoardId
+)
+{
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
new file mode 100644
index 0000000000..6181cf45ff
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
@@ -0,0 +1,40 @@
+/** @file
+ Source code for the board configuration init function in Post Memory init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GopConfigLib.h>
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+GopVbtSpecificUpdateNull(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+//
+// for CFL U DDR4
+//
+VOID
+CflUDdr4GopVbtSpecificUpdate(
+ IN CHILD_STRUCT **ChildStructPtr
+);
+/**
+ Board's PCD function hook init function for PEI post memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardFunctionInitPreMem (
+ IN UINT16 BoardId
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardInitLib.h
new file mode 100644
index 0000000000..758cbaa0b6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardInitLib.h
@@ -0,0 +1,20 @@
+/** @file
+ Header file for board Init function for Post Memory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_LIB_H_
+#define _PEI_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+#endif // _PEI_BOARD_INIT_LIB_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..f9e7aeecb9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
@@ -0,0 +1,398 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "CometlakeURvpInit.h"
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <PlatformBoardConfig.h> // for USB 20 AFE & Root Port Clk Info.
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+RootPortClkInfoInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB *Clock;
+ UINT32 Index;
+
+ Clock = AllocateZeroPool (16 * sizeof (PCD64_BLOB));
+ ASSERT (Clock != NULL);
+ if (Clock == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ //
+ // The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified
+ // This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board,
+ // the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will
+ // continue to draw power. To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < 16; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
+ }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0)
+ /// For LP, Set 0 - 5
+ /// For H, Set 0 - 15
+ /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
+ ///
+ switch (BoardId) {
+ // CLKREQ
+ case BoardIdCometLakeULpddr3Rvp:
+ Clock[0].PcieClock.ClockUsage = PCIE_PCH + 1;
+ Clock[1].PcieClock.ClockUsage = PCIE_PCH + 8;
+ Clock[2].PcieClock.ClockUsage = LAN_CLOCK;
+ Clock[3].PcieClock.ClockUsage = PCIE_PCH + 13;
+ Clock[4].PcieClock.ClockUsage = PCIE_PCH + 4;
+ Clock[5].PcieClock.ClockUsage = PCIE_PCH + 14;
+ break;
+
+ default:
+ break;
+ }
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board USB related configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+UsbConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD32_BLOB *UsbPort20Afe;
+
+ UsbPort20Afe = AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BLOB));
+ ASSERT (UsbPort20Afe != NULL);
+ if (UsbPort20Afe == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // USB2 AFE settings.
+ //
+ UsbPort20Afe[0].Info.Petxiset = 7;
+ UsbPort20Afe[0].Info.Txiset = 5;
+ UsbPort20Afe[0].Info.Predeemp = 3;
+ UsbPort20Afe[0].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[1].Info.Petxiset = 7;
+ UsbPort20Afe[1].Info.Txiset = 5;
+ UsbPort20Afe[1].Info.Predeemp = 3;
+ UsbPort20Afe[1].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[2].Info.Petxiset = 7;
+ UsbPort20Afe[2].Info.Txiset = 5;
+ UsbPort20Afe[2].Info.Predeemp = 3;
+ UsbPort20Afe[2].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[3].Info.Petxiset = 7;
+ UsbPort20Afe[3].Info.Txiset = 5;
+ UsbPort20Afe[3].Info.Predeemp = 3;
+ UsbPort20Afe[3].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[4].Info.Petxiset = 7;
+ UsbPort20Afe[4].Info.Txiset = 5;
+ UsbPort20Afe[4].Info.Predeemp = 3;
+ UsbPort20Afe[4].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[5].Info.Petxiset = 7;
+ UsbPort20Afe[5].Info.Txiset = 5;
+ UsbPort20Afe[5].Info.Predeemp = 3;
+ UsbPort20Afe[5].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[6].Info.Petxiset = 7;
+ UsbPort20Afe[6].Info.Txiset = 5;
+ UsbPort20Afe[6].Info.Predeemp = 3;
+ UsbPort20Afe[6].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[7].Info.Petxiset = 7;
+ UsbPort20Afe[7].Info.Txiset = 5;
+ UsbPort20Afe[7].Info.Predeemp = 3;
+ UsbPort20Afe[7].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[8].Info.Petxiset = 7;
+ UsbPort20Afe[8].Info.Txiset = 5;
+ UsbPort20Afe[8].Info.Predeemp = 3;
+ UsbPort20Afe[8].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[9].Info.Petxiset = 7;
+ UsbPort20Afe[9].Info.Txiset = 5;
+ UsbPort20Afe[9].Info.Predeemp = 3;
+ UsbPort20Afe[9].Info.Pehalfbit = 0;
+
+ //
+ // USB Port Over Current Pin
+ //
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax);
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip);
+
+ // USB2.0 AFE settings
+ UsbPort20Afe[0].Info.Petxiset = 4;
+ UsbPort20Afe[0].Info.Txiset = 0;
+ UsbPort20Afe[0].Info.Predeemp = 3;
+ UsbPort20Afe[0].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[1].Info.Petxiset = 4;
+ UsbPort20Afe[1].Info.Txiset = 0;
+ UsbPort20Afe[1].Info.Predeemp = 3;
+ UsbPort20Afe[1].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[2].Info.Petxiset = 4;
+ UsbPort20Afe[2].Info.Txiset = 0;
+ UsbPort20Afe[2].Info.Predeemp = 3;
+ UsbPort20Afe[2].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[3].Info.Petxiset = 4;
+ UsbPort20Afe[3].Info.Txiset = 0;
+ UsbPort20Afe[3].Info.Predeemp = 3;
+ UsbPort20Afe[3].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[4].Info.Petxiset = 4;
+ UsbPort20Afe[4].Info.Txiset = 0;
+ UsbPort20Afe[4].Info.Predeemp = 3;
+ UsbPort20Afe[4].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[5].Info.Petxiset = 4;
+ UsbPort20Afe[5].Info.Txiset = 0;
+ UsbPort20Afe[5].Info.Predeemp = 3;
+ UsbPort20Afe[5].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[6].Info.Petxiset = 4;
+ UsbPort20Afe[6].Info.Txiset = 0;
+ UsbPort20Afe[6].Info.Predeemp = 3;
+ UsbPort20Afe[6].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[7].Info.Petxiset = 4;
+ UsbPort20Afe[7].Info.Txiset = 0;
+ UsbPort20Afe[7].Info.Predeemp = 3;
+ UsbPort20Afe[7].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[8].Info.Petxiset = 4;
+ UsbPort20Afe[8].Info.Txiset = 0;
+ UsbPort20Afe[8].Info.Predeemp = 3;
+ UsbPort20Afe[8].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[9].Info.Petxiset = 4;
+ UsbPort20Afe[9].Info.Txiset = 0;
+ UsbPort20Afe[9].Info.Predeemp = 3;
+ UsbPort20Afe[9].Info.Pehalfbit = 0;
+ break;
+ }
+
+ //
+ // Save USB2.0 AFE blobs
+ //
+ PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob);
+ PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob);
+ PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob);
+ PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob);
+ PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob);
+ PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob);
+ PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob);
+ PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob);
+ PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob);
+ PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob);
+ PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob);
+ PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob);
+ PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob);
+ PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob);
+ PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob);
+ PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioGroupTierInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G);
+ PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI);
+ PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E);
+ break;
+
+ default:
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GPIO init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioTablePreMemInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Table Init.
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableCmlULpddr3PreMem);
+ PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableCmlULpddr3PreMemSize);
+ PcdSet32S(PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableCmlULpddr3WwanOnEarlyPreMem);
+ PcdSet16S(PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableCmlULpddr3WwanOnEarlyPreMemSize);
+ PcdSet32S(PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableCmlULpddr3WwanOffEarlyPreMem);
+ PcdSet16S(PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableCmlULpddr3WwanOffEarlyPreMemSize);
+ break;
+
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ PmConfig init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PchPmConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0# is asserted based on board HW design
+ // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport)
+ // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeControl)
+ // Only applys to board with PCH-LP. Board with Discrete PCH doesn't need this setting.
+ //
+ switch (BoardId) {
+ // Discrete VR solution
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE);
+ break;
+
+ default:
+ PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..9ab340c7e1
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h
@@ -0,0 +1,83 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h> // for MRC Configuration
+#include <ConfigBlock/SwitchableGraphicsConfig.h> // for PCIE RTD3 GPIO
+#include <GpioPinsCnlLp.h> // for GPIO definition
+#include <GpioPinsCnlH.h>
+#include <SaAccess.h> // for Root Port number
+#include <PchAccess.h> // for Root Port number
+
+//
+// The following section contains board-specific CMD/CTL/CLK and DQ/DQS mapping, needed for LPDDR3/LPDDR4
+//
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+// If clock is per rank, program to [0xFF, 0xFF]
+// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+// If clock is shared by 2 ranks but does not go to all bytes,
+// Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+// For DDR, DQByteMap[3:1] = [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+// Variable only exists to make the code easier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+// Variable only exists to make the code easier to use
+//
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for BoardIdCometLakeULpddr3Rvp
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapCmlULpddr3Rvp[2][6][2] = {
+ // Channel 0:
+ {
+ { 0xF0, 0x0F },
+ { 0x00, 0x0F },
+ { 0xF0, 0x0F },
+ { 0xF0, 0x00 },
+ { 0xFF, 0x00 },
+ { 0xFF, 0x00 }
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 },
+ { 0x00, 0xF0 },
+ { 0x0F, 0xF0 },
+ { 0x0F, 0x00 },
+ { 0xFF, 0x00 },
+ { 0xFF, 0x00 }
+ }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for CML-U LPDDR3 RVP
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqsMapCpu2DramCmlULpddr3Rvp[2][8] = {
+ { 5, 6, 7, 4, 1, 0, 2, 3 }, // Channel 0
+ { 2, 3, 1, 0, 6, 4, 5, 7 } // Channel 1
+};
+
+
+//
+// Reference RCOMP resistors on motherboard - for CML-U LPDDR3 RVP
+//
+const UINT16 RcompResistorCmlULpKc[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for CML-U LPDDR3 RVP
+//
+const UINT16 RcompTargetCmlULpKc[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..3d5fce20d9
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
@@ -0,0 +1,383 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include "SaPolicyCommon.h"
+#include "CometlakeURvpInit.h"
+#include <PlatformBoardConfig.h>
+#include <Library/CpuPlatformLib.h>
+//
+// LPDDR3 178b 8Gb die, DDP, x32
+// Micron MT52L512M32D2PF-093
+// 2133, 16-20-20-45
+// 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb = 4GB total per channel
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr3Ddp8Gb178b2133Spd[] = {
+ 0x24, // 512 SPD bytes used, 512 total
+ 0x01, // SPD Revision 0.1
+ 0x0F, // DRAM Type: LPDDR3 SDRAM
+ 0x0E, // Module Type: Non-DIMM Solution
+ 0x15, // 8 Banks, 8 Gb SDRAM density
+ 0x19, // 15 Rows, 10 Columns
+ 0x90, // SDRAM Package Type: DDP, 1 Channel per package
+ 0x00, // SDRAM Optional Features: none, tMAW = 8192 * tREFI
+ 0x00, // SDRAM Thermal / Refresh options: none
+ 0x00, // Other SDRAM Optional Features: none
+ 0x00, // Reserved
+ 0x0B, // Module Nominal Voltage, VDD = 1.2v
+ 0x0B, // SDRAM width: 32 bits, 2 Ranks
+ 0x03, // SDRAM bus width: 1 Channel, 64 bits channel width
+ 0x00, // Module Thermal Sensor: none
+ 0x00, // Extended Module Type: Reserved
+ 0x00, // Signal Loading: Unspecified
+ 0x00, // MTB = 0.125ns, FTB = 1 ps
+ 0x08, // tCKmin = 0.938 ns (LPDDR3-2133)
+ 0xFF, // tCKmax = 32.002 ns
+ 0xD4, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (First Byte)
+ 0x01, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Second Byte)
+ 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Third Byte)
+ 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Fourth Byte)
+ 0x78, // Minimum CAS Latency (tAAmin) = 15.008 ns
+ 0x00, // Read and Write Latency Set options: none
+ 0x90, // Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, // Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, // Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, // tRFCab = 210 ns (8 Gb)
+ 0x06, // tRFCab MSB
+ 0xD0, // tRFCpb = 90 ns (8 Gb)
+ 0x02, // tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, // 33-39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 40-49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 50-59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 60-69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 70-79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80-89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 90-99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 100-109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 110-119
+ 0x00, // FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, // FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, // FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x08, // FTB for tAAmin = 15.008 ns (LPDDR3-2133)
+ 0x7F, // FTB for tCKmax = 32.002 ns
+ 0xC2, // FTB for tCKmin = 0.938 ns (LPDDR3-2133)
+ 0, 0, 0, 0, // 126-129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 130-139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 140-149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 150-159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 160-169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 170-179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 180-189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 190-199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 200-209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 210-219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 220-229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 230-239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 240-249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 250-259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 260-269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 270-279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 280-289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 290-299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 300-309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 310-319
+ 0, 0, 0, 0, 0, // 320-324
+ 0x55, 0, 0, 0, // 325-328: Module ID: Module Serial Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 329-333: Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 334-338: Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 339-343: Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, // 344-348: Module Part Number
+ 0x00, // 349 Module Revision Code
+ 0x00, // 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, // 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00, // 352 DRAM Stepping
+ 0, 0, 0, 0, 0, 0, 0, // 353 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 430 - 439
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 440 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 500 - 509
+ 0, 0 // 510 - 511
+};
+
+//
+// Display DDI settings for WHL ERB
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = {
+ DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaMiscConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // UserBd
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ //
+ // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
+ // This is required to skip Memory voltage programming based on GPIO's in MRC
+ //
+ PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform
+ break;
+
+ default:
+ // MiscPeiPreMemConfig.UserBd = 0 by default.
+ break;
+ }
+
+ PcdSet16S (PcdSaDdrFreqLimit, 0);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+MrcConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ CPU_FAMILY CpuFamilyId;
+
+ CpuFamilyId = GetCpuFamily();
+
+ if (CpuFamilyId == EnumCpuCflDtHalo) {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
+ } else {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
+ }
+
+ //
+ // Example policy for DIMM slots implementation boards:
+ // 1. Assign Smbus address of DIMMs and SpdData will be updated later
+ // by reading from DIMM SPD.
+ // 2. No need to apply hardcoded SpdData buffers here for such board.
+ //
+ // Comet Lake U LP3 has removable DIMM slots.
+ // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
+ // Example:
+ // PcdMrcSpdData = 0
+ // PcdMrcSpdDataSize = 0
+ // PcdMrcSpdAddressTable0 = 0xA0
+ // PcdMrcSpdAddressTable1 = 0xA2
+ // PcdMrcSpdAddressTable2 = 0xA4
+ // PcdMrcSpdAddressTable3 = 0xA6
+ //
+ // If a board has soldered down memory. It should use the following settings.
+ // Example:
+ // PcdMrcSpdAddressTable0 = 0
+ // PcdMrcSpdAddressTable1 = 0
+ // PcdMrcSpdAddressTable2 = 0
+ // PcdMrcSpdAddressTable3 = 0
+ // PcdMrcSpdData = static data buffer
+ // PcdMrcSpdDataSize = sizeof (static data buffer)
+ //
+
+ //
+ // SPD Address Table
+ //
+ PcdSet32S (PcdMrcSpdData, (UINTN)mLpddr3Ddp8Gb178b2133Spd);
+ PcdSet16S (PcdMrcSpdDataSize, sizeof(mLpddr3Ddp8Gb178b2133Spd));
+ PcdSet8S (PcdMrcSpdAddressTable0, 0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0);
+
+ //
+ // DRAM SPD Data & related configuration
+ //
+ // Setting the PCD's to default value (CML LP3). It will be overriden to board specific settings below.
+ PcdSet32S(PcdMrcDqByteMap, (UINTN) DqByteMapCmlULpddr3Rvp);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapCmlULpddr3Rvp));
+ PcdSet32S(PcdMrcDqsMapCpu2Dram, (UINTN) DqsMapCpu2DramCmlULpddr3Rvp);
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (DqsMapCpu2DramCmlULpddr3Rvp));
+
+ switch (BoardId) {
+
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorCmlULpKc);
+ PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetCmlULpKc);
+ PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
+ PcdSetBoolS(PcdMrcDqPinsInterleaved, FALSE);
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // CA Vref routing: board-dependent
+ // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
+ // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
+ // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
+ break;
+
+ default:
+ PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board SA related GPIO configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaGpioConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update board's GPIO for PEG slot reset
+ //
+ PcdSetBoolS (PcdPegGpioResetControl, TRUE);
+ PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
+ PcdSet32S (PcdPeg0ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
+ PcdSet32S (PcdPeg3ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
+
+ //
+ // PCIE RTD3 GPIO
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet8S(PcdRootPortIndex, 4);
+ PcdSet8S (PcdPcie0GpioSupport, PchGpio);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+
+ default:
+ PcdSet8S(PcdRootPortIndex, 0xFF);
+ PcdSet8S (PcdPcie0GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaDisplayConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update Display DDI Config
+ //
+ switch (BoardId) {
+ case BoardIdCometLakeULpddr3Rvp:
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdiConfig));
+ break;
+
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c
new file mode 100644
index 0000000000..15fc18c7ae
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c
@@ -0,0 +1,32 @@
+/** @file
+ CometlakeURvp HSIO PTSS H File
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef COMETLAKE_RVP3_HSIO_PTSS_H_
+#define COMETLAKE_RVP3_HSIO_PTSS_H_
+
+#include <PchHsioPtssTables.h>
+
+#ifndef HSIO_PTSS_TABLE_SIZE
+#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES)
+#endif
+
+//BoardId CometlakeURvp
+HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[] = {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}
+};
+
+UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size = sizeof(PchLpHsioPtss_Cx_CometlakeURvp) / sizeof(HSIO_PTSS_TABLES);
+
+HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[] = {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0},
+};
+
+UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size = sizeof(PchLpHsioPtss_Bx_CometlakeURvp) / sizeof(HSIO_PTSS_TABLES);
+
+#endif // COMETLAKE_RVP_HSIO_PTSS_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpInit.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpInit.h
new file mode 100644
index 0000000000..cbfa60907c
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpInit.h
@@ -0,0 +1,41 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _COMET_LAKE_U_RVP_INIT_H_
+#define _COMET_LAKE_U_RVP_INIT_H_
+
+#include <Uefi.h>
+#include <IoExpander.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/SiliconInitLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[];
+extern UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[];
+extern UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size;
+
+
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[];
+extern UINT16 mGpioTableCmlULpddr3PreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[];
+extern UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[];
+extern UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize;
+
+extern GPIO_INIT_CONFIG mGpioTableDefault[];
+extern UINT16 mGpioTableDefaultSize;
+extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3[];
+extern UINT16 mGpioTableCmlULpddr3Size;
+
+#endif // _COMET_LAKE_U_LP3_INIT_H_
+
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c
new file mode 100644
index 0000000000..9becd139e6
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c
@@ -0,0 +1,43 @@
+/** @file
+ GPIO definition table for Comet Lake U LP3 RVP Pre-Memory
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[] =
+{
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N
+ {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N
+ {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N
+};
+UINT16 mGpioTableCmlULpddr3PreMemSize = sizeof (mGpioTableCmlULpddr3PreMem) / sizeof (GPIO_INIT_CONFIG);
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[] =
+{
+ // Turn on WWAN power and de-assert reset pins by default
+ {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock}}, //WWAN_WAKE_N
+ {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_FCP_OFF
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS
+ {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL
+ {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_DISABLE_N
+};
+UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize = sizeof(mGpioTableCmlULpddr3WwanOnEarlyPreMem) / sizeof(GPIO_INIT_CONFIG);
+
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[] =
+{
+ // Assert reset pins and then turn off WWAN power
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioOutputStateUnlock}}, //WWAN_PERST
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone, GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS
+};
+UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize = sizeof(mGpioTableCmlULpddr3WwanOffEarlyPreMem) / sizeof(GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c
new file mode 100644
index 0000000000..a0b466ba01
--- /dev/null
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c
@@ -0,0 +1,254 @@
+/** @file
+ GPIO definition table for Comet Lake U LP3 RVP
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableCmlULpddr3[] =
+{
+// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, GPIRoutConfig, PadRstCfg, Term,
+ //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_0
+ //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_1
+ //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CSB
+ //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPPC_A6_SERIRQ
+ // TPM interrupt
+ {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N
+ //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CLK
+ //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N
+ // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SLATEMODE_HALLOUT
+ {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL_SLOT1
+ //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_Reset
+ {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPKR_PD_N
+ //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SD_PWREN
+ //A18-A23 -> Under GPIO table for GPIO Termination -20K WPU
+ {GPIO_CNL_LP_GPP_A18, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //ACCEL_INT
+ {GPIO_CNL_LP_GPP_A19, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //ALS_INT
+ {GPIO_CNL_LP_GPP_A20, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //HUMAN_PRESENCE_INT
+ {GPIO_CNL_LP_GPP_A21, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //HALL_SENSOR_INT
+ {GPIO_CNL_LP_GPP_A22, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //IVCAM_WAKE
+ {GPIO_CNL_LP_GPP_A23, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //SHARED_INT
+ //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0
+ //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0
+ {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //FORCE_PAD_INT
+ {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioOutputStateUnlock} }, //BT_DISABLE_N
+ //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WWAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_NAND_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //LAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WLAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ
+ {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S0_N
+ //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PLT_RST_N
+ {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_PWR_EN
+ //B15 -Unused pin -> Under GPIO table for GPIO Termination - Input sensing disable
+ {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock } }, //FPS_INT_N
+ {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock} }, //FPS_RESET_N
+ // B15 -Unused pin -> No Reboot Straps
+ //{GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // NO_REBOOT
+ //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CS_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CLK_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MISO_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MOSI_FPS
+ {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone, GpioPadUnlock }}, //EC_SLP_S0_CS_N
+ //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_DATA
+ {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioOutputStateUnlock }}, //WIFI_RF_KILL_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_CLK
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_DATA
+ {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N
+ //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio , GpioDirIn , GpioOutDefault , GpioIntLevel | GpioIntApic , GpioPlatformReset, GpioTermWpu20K }}, //CODEC_INT_N
+ {GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N
+ {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //TB