Date   

[Patch 1/1] BaseTools: Fixed a Incremental build issue

Bob Feng
 

The .map file is not update to FFS_OUTPUT_DIR folder
in the incremental build.

Signed-off-by: Guo Dong <guo.dong@...>
Signed-off-by: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <liming.gao@...>
---
BaseTools/Source/Python/AutoGen/GenMake.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/AutoGen/GenMake.py b/BaseTools/Source/Python/AutoGen/GenMake.py
index ba199c1aa73d..9ae09c47caf8 100755
--- a/BaseTools/Source/Python/AutoGen/GenMake.py
+++ b/BaseTools/Source/Python/AutoGen/GenMake.py
@@ -718,11 +718,11 @@ cleanlib:
Src = self.ReplaceMacro(Src)
Dst = self.ReplaceMacro(Dst)
if Dst not in self.ResultFileList:
self.ResultFileList.append(Dst)
if '%s :' %(Dst) not in self.BuildTargetList:
- self.BuildTargetList.append("%s :" %(Dst))
+ self.BuildTargetList.append("%s : %s" %(Dst,Src))
self.BuildTargetList.append('\t' + self._CP_TEMPLATE_[self._FileType] %{'Src': Src, 'Dst': Dst})

FfsCmdList = Cmd[0]
for index, Str in enumerate(FfsCmdList):
if '-o' == Str:
--
2.18.0.windows.1


[Patch 1/1] BaseTools: Fixed a Incremental build issue

Bob Feng
 

From: Bob Feng <bob.c.feng@...>

The .map file is not update to FFS_OUTPUT_DIR folder
in the incremental build.

Signed-off-by: Guo Dong <guo.dong@...>
Signed-off-by: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <liming.gao@...>
---
BaseTools/Source/Python/AutoGen/GenMake.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/AutoGen/GenMake.py b/BaseTools/Source/Python/AutoGen/GenMake.py
index ba199c1aa73d..9ae09c47caf8 100755
--- a/BaseTools/Source/Python/AutoGen/GenMake.py
+++ b/BaseTools/Source/Python/AutoGen/GenMake.py
@@ -718,11 +718,11 @@ cleanlib:
Src = self.ReplaceMacro(Src)
Dst = self.ReplaceMacro(Dst)
if Dst not in self.ResultFileList:
self.ResultFileList.append(Dst)
if '%s :' %(Dst) not in self.BuildTargetList:
- self.BuildTargetList.append("%s :" %(Dst))
+ self.BuildTargetList.append("%s : %s" %(Dst,Src))
self.BuildTargetList.append('\t' + self._CP_TEMPLATE_[self._FileType] %{'Src': Src, 'Dst': Dst})

FfsCmdList = Cmd[0]
for index, Str in enumerate(FfsCmdList):
if '-o' == Str:
--
2.18.0.windows.1


[PATCH V2] MdePkg/SmBios.h: Add two additional DWORD for smbios 3.3.0 type17

Gao, Zhichao
 

From: Matthew Carlson <macarl@...>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2482

Refer to DSP0134_3.3.0.pdf, there are two additional DWORD added
for type 17. One is "Extended Speed", the other is "Extended
Configured Memory Speed". The lack of these field may cause strange
error in some operating systems.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <liming.gao@...>
Signed-off-by: Zhichao Gao <zhichao.gao@...>
---
V2:

1. fix some typo.
2. Do not update the copyright.

MdePkg/Include/IndustryStandard/SmBios.h | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index 8b3c4d7ba9..def874be28 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1843,6 +1843,11 @@ typedef struct {
UINT64 VolatileSize;
UINT64 CacheSize;
UINT64 LogicalSize;
+ //
+ // Add for smbios 3.3.0
+ //
+ UINT32 ExtendedSpeed;
+ UINT32 ExtendedConfiguredMemorySpeed;
} SMBIOS_TABLE_TYPE17;

///
--
2.16.2.windows.1


Re: [edk2-rfc] [edk2-devel] [RFC] VariablePolicy - Protocol, Libraries, and Implementation for VariableLock Alternative

Yao, Jiewen
 

Maybe I jump to an implementation too soon. I should have shared more about my thought at first. I am sorry about that.

 

When I first saw the DisableVarPolicy() API, I felt it is a backdoor. This is a brand-new feature that does not exist today.

(I don’t treat VarPolicy as something new, it is an enhancement of VarCheck or VarLock. I have no concern at all.)

Also disabling UEFI secure boot requires either authenticated variable or physical user presence before.

With this feature, the UEFI secure boot can be disabled by a simple function call. (Maybe that can be considered as a feature)

 

It also reminds me that when UEFI secure boot was introduced. Almost all attacks are just to figure out a way to disable UEFI secure boot via different ways, such as other variable or jumper.

As such, my first reaction is that I want to have a way to eliminate the DisableVarPolicy() and always enforce policy. I believe it should be a *platform choice* to support DisableVarPolicy() or not.

Maybe in MSFT platform, this is required in MFG mode. Not a problem. As long as you have SDL process to review the MFG code and make you can do the right thing when the var policy and secure boot is disabled.

Maybe for my platform, I have no confidence on that. What I want to do is just to remove this DisableVarPolicy() feature at all. Instead of review all the MFG code to make sure they are not calling DisableVarPolicy, I can just do a simple check - This function does not exist. Done! That is the simplest way for me. Many EDKII feature uses the similar way – use a PCD to control a feature on/off.

 

Yes, I fully agree with you that “Our recommendation would be to make sure that "lock" is called prior to leaving TCB, similar to SMM or other hardware locks (which the platform already has to coordinate).”

That is good practice everyone should follow. However, if there is a call DisableVarPolicy() in the code, it must be before Lock. (Otherwise it does not work)

What if an attack can find a path to trigger DisableVarPolicy() before lock? This recommendation does not help.

 

If you don’t like splitting the protocol, that is fine.

I can offer another implementation choice. Defining a PCD – PcdSupportDisableVarPolicy. Pseudo code below:

EFI_STATUS

DisableVarPolicy()

{

  If (!FeaturePcdGet(PcdSupportDisableVarPolicy)) {

    Return UNSUPPORTED

  }

  // Follow existing way

}

With those 3 lines of code, you may configure TRUE for MSFT platform, with detail SDL review in MFG mode.

I may configure FALSE for my platform with confident that no one can violate the policy in any boot mode. Simple for me. J

 

 

Now let’s talk about Test.

I think the unit tests and system test MSFT did are very good. We learn a lot from that.

I do appreciate your great work.

On the other hand, the test only shows the *final system state*. The attacker may find another path to bypass the protection by triggering DisableVarPolicy() to unlock the system.

(I still remember the stupid mistake I made years ago that caused a RO variable not locked in S4 resume path. Also another mistake that a system state is unlocked in S3 resume path. L)

It is hard to design test to catch *all possible special path*. That is my headache. If there is such function existing in my firmware, I have to keep my eye on every possible path.

That is why I would like to have a way to eliminate this function in my firmware at all (keep it simple), but leave the flexibility to keep it enabled in other firmware.

 

Anyway, I like your idea to extend the security state to PCR. Just in case there is violation it can be recorded.

 

Thank you

Yao Jiewen

 

From: bret.barkelew via [] <bret.barkelew=microsoft.com@[]>
Sent: Friday, February 7, 2020 2:00 PM
To: Yao; Yao, Jiewen <jiewen.yao@...>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [edk2-rfc] [edk2-devel] [RFC] VariablePolicy - Protocol, Libraries, and Implementation for VariableLock Alternative

 

I agree with you that this function is extremely sensitive and important, and I kinda like your idea of splitting the protocol into a "policy" and "policy control", but I don't think it make practical sense to split them this way. At the very least, you end up with a chicken and egg problem where we would need to read mfg state to decide whether we need to publish the other protocol, but mfg state would also determine whether we used the protocol to disable the protection.

Furthermore, there may be architectural (e.g. off-Soc) implementations of this that would still require a "lock" signal to disable their ability to receive the disable command. These solutions wouldn't have a concept of building with a "I want more security" PCD.

Our recommendation would be to make sure that "lock" is called prior to leaving TCB, similar to SMM or other hardware locks (which the platform already has to coordinate).

Two points to help manage this:
1) We would be willing to discuss adding a HSTI bit or DeviceState flag to indicate to an OS or attestation authority that the protections are disabled for the current boot.
2) We would recommend running the VarLockAudit test that we've provided with the release to make sure that not only are protections enabled, but the parameters of your policies are configured the way the platform wants them. It was very useful to us when trying to understand the overall system state we wanted.
https://github.com/corthon/edk2/tree/personal/brbarkel/var_policy_rfc_extra/UefiTestingPkg/AuditTests/UefiVarLockAudit

Looking forward to your thoughts.
Thanks!
- Bret


Re: [Patch 08/11] MdePkg/Test: Add SafeIntLib and BaseLib Base64 unit tests

Liming Gao
 

Mike:
Is there the ready UEFI shell environment to run target based tests? Is Emulator used?

Thanks
Liming

-----Original Message-----
From: Kinney, Michael D <michael.d.kinney@...>
Sent: Friday, January 24, 2020 10:10 AM
To: devel@edk2.groups.io
Cc: Sean Brogan <sean.brogan@...>; Bret Barkelew <Bret.Barkelew@...>; Gao, Liming <liming.gao@...>
Subject: [Patch 08/11] MdePkg/Test: Add SafeIntLib and BaseLib Base64 unit tests

* Add unit tests for SafeIntLib class
* Add unit tests for BaseLib Base64 conversion APIs.
* Add Test/MdePkgHostTest.dsc -to build host based unit
tests
* Update MdePkg.dsc to build target based tests for
SafeIntLib and BaseLib
* Update MdePkg.ci.yaml to build and run host based
tests for SafeIntLib and BaseLib

Cc: Sean Brogan <sean.brogan@...>
Cc: Bret Barkelew <Bret.Barkelew@...>
Cc: Liming Gao <liming.gao@...>
Signed-off-by: Michael D Kinney <michael.d.kinney@...>
---
MdePkg/MdePkg.ci.yaml | 19 +-
MdePkg/MdePkg.dsc | 18 +
MdePkg/Test/MdePkgHostTest.dsc | 30 +
.../UnitTest/Library/BaseLib/Base64UnitTest.c | 404 +++
.../Library/BaseLib/BaseLibUnitTestsHost.inf | 32 +
.../Library/BaseLib/BaseLibUnitTestsUefi.inf | 33 +
.../SafeIntLibUintnIntnUnitTests32.c | 540 +++
.../SafeIntLibUintnIntnUnitTests64.c | 544 +++
.../BaseSafeIntLib/TestBaseSafeIntLib.c | 3064 +++++++++++++++++
.../BaseSafeIntLib/TestBaseSafeIntLib.h | 123 +
.../BaseSafeIntLib/TestBaseSafeIntLib.uni | 13 +
.../BaseSafeIntLib/TestBaseSafeIntLibDxe.inf | 45 +
.../BaseSafeIntLib/TestBaseSafeIntLibHost.inf | 40 +
.../BaseSafeIntLib/TestBaseSafeIntLibPei.inf | 45 +
.../BaseSafeIntLib/TestBaseSafeIntLibSmm.inf | 45 +
.../TestBaseSafeIntLibUefiShell.inf | 42 +
16 files changed, 5034 insertions(+), 3 deletions(-)
create mode 100644 MdePkg/Test/MdePkgHostTest.dsc
create mode 100644 MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c
create mode 100644 MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsUefi.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests32.c
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests64.c
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.h
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.uni
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibDxe.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibPei.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
create mode 100644 MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 65c4ec3bec..88e490fcb6 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -10,8 +10,13 @@
"DscPath": "MdePkg.dsc"
},

+ ## options defined ci/Plugin/HostUnitTestCompilerPlugin
+ "HostUnitTestCompilerPlugin": {
+ "DscPath": "Test/MdePkgHostTest.dsc"
+ },
+
## options defined ci/Plugin/CharEncodingCheck
-"CharEncodingCheck": {
+ "CharEncodingCheck": {
"IgnoreFiles": []
},

@@ -21,7 +26,9 @@
"MdePkg/MdePkg.dec"
],
# For host based unit tests
- "AcceptableDependencies-HOST_APPLICATION":[],
+ "AcceptableDependencies-HOST_APPLICATION":[
+ "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
+ ],
# For UEFI shell based apps
"AcceptableDependencies-UEFI_APPLICATION":[],
"IgnoreInf": []
@@ -29,10 +36,16 @@

## options defined ci/Plugin/DscCompleteCheck
"DscCompleteCheck": {
- "IgnoreInf": [],
+ "IgnoreInf": [""],
"DscPath": "MdePkg.dsc"
},

+ ## options defined ci/Plugin/HostUnitTestDscCompleteCheck
+ "HostUnitTestDscCompleteCheck": {
+ "IgnoreInf": [""],
+ "DscPath": "Test/MdePkgHostTest.dsc"
+ },
+
## options defined ci/Plugin/GuidCheck
"GuidCheck": {
"IgnoreGuidName": [
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 0aeafaaacc..87af740853 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -18,6 +18,8 @@ [Defines]
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT

+!include UnitTestFrameworkPkg/UnitTestFrameworkPkgTarget.dsc.inc
+
[PcdsFeatureFlag]
gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|TRUE

@@ -26,6 +28,9 @@ [PcdsFixedAtBuild]
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000

+[LibraryClasses]
+ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+
[Components]
MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -115,6 +120,19 @@ [Components]
MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf
MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf

+ #
+ # Add UEFI Target Based Unit Tests
+ #
+ MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsUefi.inf
+
+ #
+ # Build PEIM, DXE_DRIVER, SMM_DRIVER, UEFI Shell components that test SafeIntLib
+ #
+ MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibPei.inf
+ MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibDxe.inf
+ MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
+ MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf
+
[Components.IA32, Components.X64]
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
diff --git a/MdePkg/Test/MdePkgHostTest.dsc b/MdePkg/Test/MdePkgHostTest.dsc
new file mode 100644
index 0000000000..3d677ee75c
--- /dev/null
+++ b/MdePkg/Test/MdePkgHostTest.dsc
@@ -0,0 +1,30 @@
+## @file
+# MdePkg DSC file used to build host-based unit tests.
+#
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (C) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ PLATFORM_NAME = MdePkgHostTest
+ PLATFORM_GUID = 50652B4C-88CB-4481-96E8-37F2D0034440
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/MdePkg/HostTest
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+!include UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
+
+[LibraryClasses]
+ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+
+[Components]
+ #
+ # Build HOST_APPLICATION that tests the SafeIntLib
+ #
+ MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
+ MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
diff --git a/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c b/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c
new file mode 100644
index 0000000000..0ad078155c
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseLib/Base64UnitTest.c
@@ -0,0 +1,404 @@
+/** @file
+ Unit tests of Base64 conversion APIs in BaseLib.
+
+ Copyright (C) Microsoft Corporation.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UnitTestLib.h>
+
+#define UNIT_TEST_APP_NAME "BaseLib Unit Test Application"
+#define UNIT_TEST_APP_VERSION "1.0"
+
+/**
+ RFC 4648 https://tools.ietf.org/html/rfc4648 test vectors
+
+ BASE64("") = ""
+ BASE64("f") = "Zg=="
+ BASE64("fo") = "Zm8="
+ BASE64("foo") = "Zm9v"
+ BASE64("foob") = "Zm9vYg=="
+ BASE64("fooba") = "Zm9vYmE="
+ BASE64("foobar") = "Zm9vYmFy"
+
+ The test vectors are using ascii strings for the binary data
+ */
+
+typedef struct {
+ CHAR8 *TestInput;
+ CHAR8 *TestOutput;
+ EFI_STATUS ExpectedStatus;
+ VOID *BufferToFree;
+ UINTN ExpectedSize;
+} BASIC_TEST_CONTEXT;
+
+#define B64_TEST_1 ""
+#define BIN_TEST_1 ""
+
+#define B64_TEST_2 "Zg=="
+#define BIN_TEST_2 "f"
+
+#define B64_TEST_3 "Zm8="
+#define BIN_TEST_3 "fo"
+
+#define B64_TEST_4 "Zm9v"
+#define BIN_TEST_4 "foo"
+
+#define B64_TEST_5 "Zm9vYg=="
+#define BIN_TEST_5 "foob"
+
+#define B64_TEST_6 "Zm9vYmE="
+#define BIN_TEST_6 "fooba"
+
+#define B64_TEST_7 "Zm9vYmFy"
+#define BIN_TEST_7 "foobar"
+
+// Adds all white space - also ends the last quantum with only spaces afterwards
+#define B64_TEST_8_IN " \t\v Zm9\r\nvYmFy \f "
+#define BIN_TEST_8 "foobar"
+
+// Not a quantum multiple of 4
+#define B64_ERROR_1 "Zm9vymFy="
+
+// Invalid characters in the string
+#define B64_ERROR_2 "Zm$vymFy"
+
+// Too many '=' characters
+#define B64_ERROR_3 "Z==="
+
+// Poorly placed '='
+#define B64_ERROR_4 "Zm=vYmFy"
+
+#define MAX_TEST_STRING_SIZE (200)
+
+// ------------------------------------------------ Input----------Output-----------Result-------Free--Expected Output Size
+static BASIC_TEST_CONTEXT mBasicEncodeTest1 = {BIN_TEST_1, B64_TEST_1, EFI_SUCCESS, NULL, sizeof(B64_TEST_1)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest2 = {BIN_TEST_2, B64_TEST_2, EFI_SUCCESS, NULL, sizeof(B64_TEST_2)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest3 = {BIN_TEST_3, B64_TEST_3, EFI_SUCCESS, NULL, sizeof(B64_TEST_3)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest4 = {BIN_TEST_4, B64_TEST_4, EFI_SUCCESS, NULL, sizeof(B64_TEST_4)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest5 = {BIN_TEST_5, B64_TEST_5, EFI_SUCCESS, NULL, sizeof(B64_TEST_5)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest6 = {BIN_TEST_6, B64_TEST_6, EFI_SUCCESS, NULL, sizeof(B64_TEST_6)};
+static BASIC_TEST_CONTEXT mBasicEncodeTest7 = {BIN_TEST_7, B64_TEST_7, EFI_SUCCESS, NULL, sizeof(B64_TEST_7)};
+static BASIC_TEST_CONTEXT mBasicEncodeError1 = {BIN_TEST_7, B64_TEST_1, EFI_BUFFER_TOO_SMALL, NULL,
sizeof(B64_TEST_7)};
+
+static BASIC_TEST_CONTEXT mBasicDecodeTest1 = {B64_TEST_1, BIN_TEST_1, EFI_SUCCESS, NULL, sizeof(BIN_TEST_1)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest2 = {B64_TEST_2, BIN_TEST_2, EFI_SUCCESS, NULL, sizeof(BIN_TEST_2)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest3 = {B64_TEST_3, BIN_TEST_3, EFI_SUCCESS, NULL, sizeof(BIN_TEST_3)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest4 = {B64_TEST_4, BIN_TEST_4, EFI_SUCCESS, NULL, sizeof(BIN_TEST_4)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest5 = {B64_TEST_5, BIN_TEST_5, EFI_SUCCESS, NULL, sizeof(BIN_TEST_5)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest6 = {B64_TEST_6, BIN_TEST_6, EFI_SUCCESS, NULL, sizeof(BIN_TEST_6)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest7 = {B64_TEST_7, BIN_TEST_7, EFI_SUCCESS, NULL, sizeof(BIN_TEST_7)-1};
+static BASIC_TEST_CONTEXT mBasicDecodeTest8 = {B64_TEST_8_IN, BIN_TEST_8, EFI_SUCCESS, NULL, sizeof(BIN_TEST_8)-1};
+
+static BASIC_TEST_CONTEXT mBasicDecodeError1 = {B64_ERROR_1, B64_ERROR_1, EFI_INVALID_PARAMETER, NULL, 0};
+static BASIC_TEST_CONTEXT mBasicDecodeError2 = {B64_ERROR_2, B64_ERROR_2, EFI_INVALID_PARAMETER, NULL, 0};
+static BASIC_TEST_CONTEXT mBasicDecodeError3 = {B64_ERROR_3, B64_ERROR_3, EFI_INVALID_PARAMETER, NULL, 0};
+static BASIC_TEST_CONTEXT mBasicDecodeError4 = {B64_ERROR_4, B64_ERROR_4, EFI_INVALID_PARAMETER, NULL, 0};
+static BASIC_TEST_CONTEXT mBasicDecodeError5 = {B64_TEST_7, BIN_TEST_1, EFI_BUFFER_TOO_SMALL, NULL,
sizeof(BIN_TEST_7)-1};
+
+/**
+ Simple clean up method to make sure tests clean up even if interrupted and fail
+ in the middle.
+**/
+STATIC
+VOID
+EFIAPI
+CleanUpB64TestContext (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ BASIC_TEST_CONTEXT *Btc;
+
+ Btc = (BASIC_TEST_CONTEXT *)Context;
+ if (Btc != NULL) {
+ //free string if set
+ if (Btc->BufferToFree != NULL) {
+ FreePool (Btc->BufferToFree);
+ Btc->BufferToFree = NULL;
+ }
+ }
+}
+
+/**
+ Unit test for Base64 encode APIs of BaseLib.
+
+ @param[in] Context [Optional] An optional paramter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot. This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that may
+ consume it.
+
+ @retval UNIT_TEST_PASSED The Unit test has completed and the test
+ case was successful.
+ @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed.
+**/
+STATIC
+UNIT_TEST_STATUS
+EFIAPI
+RfcEncodeTest (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ BASIC_TEST_CONTEXT *Btc;
+ CHAR8 *b64String;
+ CHAR8 *binString;
+ UINTN b64StringSize;
+ EFI_STATUS Status;
+ UINT8 *BinData;
+ UINTN BinSize;
+ CHAR8 *b64WorkString;
+ UINTN ReturnSize;
+ INTN CompareStatus;
+ UINTN indx;
+
+ Btc = (BASIC_TEST_CONTEXT *) Context;
+ binString = Btc->TestInput;
+ b64String = Btc->TestOutput;
+
+ //
+ // Only testing the the translate functionality, so preallocate the proper
+ // string buffer.
+ //
+
+ b64StringSize = AsciiStrnSizeS(b64String, MAX_TEST_STRING_SIZE);
+ BinSize = AsciiStrnLenS(binString, MAX_TEST_STRING_SIZE);
+ BinData = (UINT8 *) binString;
+
+ b64WorkString = (CHAR8 *) AllocatePool(b64StringSize);
+ UT_ASSERT_NOT_NULL(b64WorkString);
+
+ Btc->BufferToFree = b64WorkString;
+ ReturnSize = b64StringSize;
+
+ Status = Base64Encode(BinData, BinSize, b64WorkString, &ReturnSize);
+
+ UT_ASSERT_STATUS_EQUAL(Status, Btc->ExpectedStatus);
+
+ UT_ASSERT_EQUAL(ReturnSize, Btc->ExpectedSize);
+
+ if (!EFI_ERROR (Btc->ExpectedStatus)) {
+ if (ReturnSize != 0) {
+ CompareStatus = AsciiStrnCmp (b64String, b64WorkString, ReturnSize);
+ if (CompareStatus != 0) {
+ UT_LOG_ERROR ("b64 string compare error - size=%d\n", ReturnSize);
+ for (indx = 0; indx < ReturnSize; indx++) {
+ UT_LOG_ERROR (" %2.2x", 0xff & b64String[indx]);
+ }
+ UT_LOG_ERROR ("\n b64 work string:\n");
+ for (indx = 0; indx < ReturnSize; indx++) {
+ UT_LOG_ERROR (" %2.2x", 0xff & b64WorkString[indx]);
+ }
+ UT_LOG_ERROR ("\n");
+ }
+ UT_ASSERT_EQUAL (CompareStatus, 0);
+ }
+ }
+
+ Btc->BufferToFree = NULL;
+ FreePool (b64WorkString);
+ return UNIT_TEST_PASSED;
+}
+
+/**
+ Unit test for Base64 decode APIs of BaseLib.
+
+ @param[in] Context [Optional] An optional paramter that enables:
+ 1) test-case reuse with varied parameters and
+ 2) test-case re-entry for Target tests that need a
+ reboot. This parameter is a VOID* and it is the
+ responsibility of the test author to ensure that the
+ contents are well understood by all test cases that may
+ consume it.
+
+ @retval UNIT_TEST_PASSED The Unit test has completed and the test
+ case was successful.
+ @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed.
+**/
+STATIC
+UNIT_TEST_STATUS
+EFIAPI
+RfcDecodeTest(
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ BASIC_TEST_CONTEXT *Btc;
+ CHAR8 *b64String;
+ CHAR8 *binString;
+ EFI_STATUS Status;
+ UINTN b64StringLen;
+ UINTN ReturnSize;
+ UINT8 *BinData;
+ UINTN BinSize;
+ INTN CompareStatus;
+ UINTN indx;
+
+ Btc = (BASIC_TEST_CONTEXT *)Context;
+ b64String = Btc->TestInput;
+ binString = Btc->TestOutput;
+
+ //
+ // Only testing the the translate functionality
+ //
+
+ b64StringLen = AsciiStrnLenS (b64String, MAX_TEST_STRING_SIZE);
+ BinSize = AsciiStrnLenS (binString, MAX_TEST_STRING_SIZE);
+
+ BinData = AllocatePool (BinSize);
+ Btc->BufferToFree = BinData;
+
+ ReturnSize = BinSize;
+ Status = Base64Decode (b64String, b64StringLen, BinData, &ReturnSize);
+
+ UT_ASSERT_STATUS_EQUAL (Status, Btc->ExpectedStatus);
+
+ // If an error is not expected, check the results
+ if (EFI_ERROR (Btc->ExpectedStatus)) {
+ if (Btc->ExpectedStatus == EFI_BUFFER_TOO_SMALL) {
+ UT_ASSERT_EQUAL (ReturnSize, Btc->ExpectedSize);
+ }
+ } else {
+ UT_ASSERT_EQUAL (ReturnSize, Btc->ExpectedSize);
+ if (ReturnSize != 0) {
+ CompareStatus = CompareMem (binString, BinData, ReturnSize);
+ if (CompareStatus != 0) {
+ UT_LOG_ERROR ("bin string compare error - size=%d\n", ReturnSize);
+ for (indx = 0; indx < ReturnSize; indx++) {
+ UT_LOG_ERROR (" %2.2x", 0xff & binString[indx]);
+ }
+ UT_LOG_ERROR ("\nBinData:\n");
+ for (indx = 0; indx < ReturnSize; indx++) {
+ UT_LOG_ERROR (" %2.2x", 0xff & BinData[indx]);
+ }
+ UT_LOG_ERROR ("\n");
+ }
+ UT_ASSERT_EQUAL (CompareStatus, 0);
+ }
+ }
+
+ Btc->BufferToFree = NULL;
+ FreePool (BinData);
+ return UNIT_TEST_PASSED;
+}
+
+/**
+ Initialze the unit test framework, suite, and unit tests for the
+ Base64 conversion APIs of BaseLib and run the unit tests.
+
+ @retval EFI_SUCCESS All test cases were dispached.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources available to
+ initialize the unit tests.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+UnitTestingEntry (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UNIT_TEST_FRAMEWORK_HANDLE Fw;
+ UNIT_TEST_SUITE_HANDLE b64EncodeTests;
+ UNIT_TEST_SUITE_HANDLE b64DecodeTests;
+
+ Fw = NULL;
+
+ DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION));
+
+ //
+ // Start setting up the test framework for running the tests.
+ //
+ Status = InitUnitTestFramework (&Fw, UNIT_TEST_APP_NAME, gEfiCallerBaseName, UNIT_TEST_APP_VERSION);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));
+ goto EXIT;
+ }
+
+ //
+ // Populate the B64 Encode Unit Test Suite.
+ //
+ Status = CreateUnitTestSuite (&b64EncodeTests, Fw, "b64 Encode binary to Ascii string", "BaseLib.b64Encode", NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for b64EncodeTests\n"));
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+
+ // --------------Suite-----------Description--------------Class Name----------Function--------Pre---Post-------------------Context-----------
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - Empty", "Test1", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest1);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - f", "Test2", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest2);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - fo", "Test3", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest3);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - foo", "Test4", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest4);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - foob", "Test5", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest5);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - fooba", "Test6", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest6);
+ AddTestCase (b64EncodeTests, "RFC 4686 Test Vector - foobar", "Test7", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeTest7);
+ AddTestCase (b64EncodeTests, "Too small of output buffer", "Error1", RfcEncodeTest, NULL, CleanUpB64TestContext,
&mBasicEncodeError1);
+ //
+ // Populate the B64 Decode Unit Test Suite.
+ //
+ Status = CreateUnitTestSuite (&b64DecodeTests, Fw, "b64 Decode Ascii string to binary", "BaseLib.b64Decode", NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for b64Decode Tests\n"));
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - Empty", "Test1", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest1);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - f", "Test2", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest2);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fo", "Test3", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest3);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foo", "Test4", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest4);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foob", "Test5", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest5);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fooba", "Test6", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest6);
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foobar", "Test7", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest7);
+ AddTestCase (b64DecodeTests, "Ignore Whitespace test", "Test8", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeTest8);
+
+ AddTestCase (b64DecodeTests, "Not a quantum multiple of 4", "Error1", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeError1);
+ AddTestCase (b64DecodeTests, "Invalid characters in the string", "Error2", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeError2);
+ AddTestCase (b64DecodeTests, "Too many padding characters", "Error3", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeError3);
+ AddTestCase (b64DecodeTests, "Incorrectly placed padding character", "Error4", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeError4);
+ AddTestCase (b64DecodeTests, "Too small of output buffer", "Error5", RfcDecodeTest, NULL, CleanUpB64TestContext,
&mBasicDecodeError5);
+
+ //
+ // Execute the tests.
+ //
+ Status = RunAllTestSuites (Fw);
+
+EXIT:
+ if (Fw) {
+ FreeUnitTestFramework (Fw);
+ }
+
+ return Status;
+}
+
+/**
+ Standard UEFI entry point for target based unit test execution from UEFI Shell.
+**/
+EFI_STATUS
+EFIAPI
+BaseLibUnitTestAppEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return UnitTestingEntry ();
+}
+
+/**
+ Standard POSIX C entry point for host based unit test execution.
+**/
+int
+main (
+ int argc,
+ char *argv[]
+ )
+{
+ return UnitTestingEntry ();
+}
diff --git a/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
b/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
new file mode 100644
index 0000000000..b31afae633
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
@@ -0,0 +1,32 @@
+## @file
+# Unit tests of Base64 conversion APIs in BaseLib that are run from host
+# environment.
+#
+# Copyright (C) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010006
+ BASE_NAME = BaseLibUnitTestsHost
+ FILE_GUID = 1d005f4c-4dfa-41b5-ab0c-be91fe121459
+ MODULE_TYPE = HOST_APPLICATION
+ VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ Base64UnitTest.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ UnitTestLib
diff --git a/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsUefi.inf
b/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsUefi.inf
new file mode 100644
index 0000000000..907503898a
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsUefi.inf
@@ -0,0 +1,33 @@
+## @file
+# Unit tests of Base64 conversion APIs in BaseLib that are run from UEFI Shell.
+#
+# Copyright (C) Microsoft Corporation.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010006
+ BASE_NAME = BaseLibUnitTestsUefi
+ FILE_GUID = df5a6fed-8786-4a9d-9d02-eab39497b4a1
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ ENTRY_POINT = BaseLibUnitTestAppEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ Base64UnitTest.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ UefiApplicationEntryPoint
+ DebugLib
+ UnitTestLib
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests32.c
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests32.c
new file mode 100644
index 0000000000..be5c0e15d3
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests32.c
@@ -0,0 +1,540 @@
+/** @file
+ IA32-specific functions for unit-testing INTN and UINTN functions in
+ SafeIntLib.
+
+ Copyright (c) Microsoft Corporation.<BR>
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TestBaseSafeIntLib.h"
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt32ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeInt32ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ INTN Result;
+
+ //
+ // If Operand is <= MAX_INTN, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUint32ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUint32ToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ INT32 Result;
+
+ //
+ // INTN is same as INT32 in IA32, so this is just a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeIntnToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeIntnToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeIntnToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ UINT32 Result;
+
+ //
+ // UINTN is same as UINT32 in IA32, so this is just a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUintnToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INTN Result;
+
+ //
+ // If Operand is <= MAX_INTN, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUintnToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUintnToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INT64 Result;
+
+ //
+ // UINTN is same as UINT32 in IA32, and UINT32 is a subset of
+ // INT64, so this is just a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUintnToInt64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ INTN Result;
+
+ //
+ // If Operand is between MIN_INTN and MAX_INTN2 inclusive, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt64ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ Operand = (-1537977259);
+ Status = SafeInt64ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-1537977259), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is between 0 and MAX_UINTN inclusive, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeInt64ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INTN Result;
+
+ //
+ // If Operand is <= MAX_INTN, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUint64ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is <= MAX_UINTN, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUint64ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnAdd (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Augend;
+ UINTN Addend;
+ UINTN Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINTN, then it's addition
+ //
+ Augend = 0x3a3a3a3a;
+ Addend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeUintnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74747474, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xabababab;
+ Addend = 0xbcbcbcbc;
+ Status = SafeUintnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnAdd (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Augend;
+ INTN Addend;
+ INTN Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INTN
+ // and doesn't underflow MIN_INTN, then it's addition
+ //
+ Augend = 0x3a3a3a3a;
+ Addend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74747474, Result);
+
+ Augend = (-976894522);
+ Addend = (-976894522);
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-1953789044), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a5a5a5a;
+ Addend = 0x5a5a5a5a;
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-1515870810);
+ Addend = (-1515870810);
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnSub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Minuend;
+ UINTN Subtrahend;
+ UINTN Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x3b3b3b3b;
+ Result = 0;
+ Status = SafeUintnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f1f1f1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x6d6d6d6d;
+ Status = SafeUintnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnSub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Minuend;
+ INTN Subtrahend;
+ INTN Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INTN or
+ // underflow MIN_INTN, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x20202020, Result);
+
+ Minuend = 0x3a3a3a3a;
+ Subtrahend = 0x5a5a5a5a;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-538976288), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-2054847098);
+ Subtrahend = 2054847098;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (2054847098);
+ Subtrahend = (-2054847098);
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnMult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Multiplicand;
+ UINTN Multiplier;
+ UINTN Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINTN, it will succeed
+ //
+ Multiplicand = 0xa122a;
+ Multiplier = 0xd23;
+ Result = 0;
+ Status = SafeUintnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x844c9dbe, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0xa122a;
+ Multiplier = 0xed23;
+ Status = SafeUintnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnMult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Multiplicand;
+ INTN Multiplier;
+ INTN Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INTN and doesn't
+ // underflow MIN_UINTN, it will succeed
+ //
+ Multiplicand = 0x123456;
+ Multiplier = 0x678;
+ Result = 0;
+ Status = SafeIntnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x75c28c50, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456;
+ Multiplier = 0xabc;
+ Status = SafeIntnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests64.c
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests64.c
new file mode 100644
index 0000000000..0fee298172
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/SafeIntLibUintnIntnUnitTests64.c
@@ -0,0 +1,544 @@
+/** @file
+ x64-specific functions for unit-testing INTN and UINTN functions in
+ SafeIntLib.
+
+ Copyright (c) Microsoft Corporation.<BR>
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TestBaseSafeIntLib.h"
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt32ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeInt32ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ INTN Result;
+
+ //
+ // For x64, INTN is same as INT64 which is a superset of INT32
+ // This is just a cast then, and it'll never fail
+ //
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUint32ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ INT32 Result;
+
+ //
+ // If Operand is between MIN_INT32 and MAX_INT32 inclusive, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeIntnToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-1537977259), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeIntnToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeIntnToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT32 inclusive, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeIntnToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeIntnToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeIntnToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is <= MAX_UINT32, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUintnToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUintnToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INTN Result;
+
+ //
+ // If Operand is <= MAX_INTN (0x7fff_ffff_ffff_ffff), then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeUintnToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUintnToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INT64 Result;
+
+ //
+ // If Operand is <= MAX_INT64, then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeUintnToInt64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUintnToInt64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ INTN Result;
+
+ //
+ // INTN is same as INT64 in x64, so this is just a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeInt64ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeInt64ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToIntn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INTN Result;
+
+ //
+ // If Operand is <= MAX_INTN (0x7fff_ffff_ffff_ffff), then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeUint64ToIntn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToIntn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ UINTN Result;
+
+ //
+ // UINTN is same as UINT64 in x64, so this is just a cast
+ //
+ Operand = 0xababababefefefef;
+ Result = 0;
+ Status = SafeUint64ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xababababefefefef, Result);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnAdd (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Augend;
+ UINTN Addend;
+ UINTN Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINTN, then it's addition
+ //
+ Augend = 0x3a3a3a3a12121212;
+ Addend = 0x3a3a3a3a12121212;
+ Result = 0;
+ Status = SafeUintnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474747424242424, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xababababefefefef;
+ Addend = 0xbcbcbcbcdededede;
+ Status = SafeUintnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnAdd (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Augend;
+ INTN Addend;
+ INTN Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INTN
+ // and doesn't underflow MIN_INTN, then it's addition
+ //
+ Augend = 0x3a3a3a3a3a3a3a3a;
+ Addend = 0x3a3a3a3a3a3a3a3a;
+ Result = 0;
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474747474747474, Result);
+
+ Augend = (-4195730024608447034);
+ Addend = (-4195730024608447034);
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-8391460049216894068), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a5a5a5a5a5a5a5a;
+ Addend = 0x5a5a5a5a5a5a5a5a;
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-6510615555426900570);
+ Addend = (-6510615555426900570);
+ Status = SafeIntnAdd(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnSub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Minuend;
+ UINTN Subtrahend;
+ UINTN Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x3b3b3b3b3b3b3b3b;
+ Result = 0;
+ Status = SafeUintnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f1f1f1f1f1f1f1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x6d6d6d6d6d6d6d6d;
+ Status = SafeUintnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnSub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Minuend;
+ INTN Subtrahend;
+ INTN Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INTN or
+ // underflow MIN_INTN, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x3a3a3a3a3a3a3a3a;
+ Result = 0;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x2020202020202020, Result);
+
+ Minuend = 0x3a3a3a3a3a3a3a3a;
+ Subtrahend = 0x5a5a5a5a5a5a5a5a;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-2314885530818453536), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-8825501086245354106);
+ Subtrahend = 8825501086245354106;
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (8825501086245354106);
+ Subtrahend = (-8825501086245354106);
+ Status = SafeIntnSub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnMult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Multiplicand;
+ UINTN Multiplier;
+ UINTN Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINTN, it will succeed
+ //
+ Multiplicand = 0x123456789a;
+ Multiplier = 0x1234567;
+ Result = 0;
+ Status = SafeUintnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x14b66db9745a07f6, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456789a;
+ Multiplier = 0x12345678;
+ Status = SafeUintnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnMult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Multiplicand;
+ INTN Multiplier;
+ INTN Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INTN and doesn't
+ // underflow MIN_UINTN, it will succeed
+ //
+ Multiplicand = 0x123456789;
+ Multiplier = 0x6789abcd;
+ Result = 0;
+ Status = SafeIntnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x75cd9045220d6bb5, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456789;
+ Multiplier = 0xa789abcd;
+ Status = SafeIntnMult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c
new file mode 100644
index 0000000000..2b1a2223a0
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c
@@ -0,0 +1,3064 @@
+/** @file
+ UEFI OS based application for unit testing the SafeIntLib.
+
+ Copyright (c) Microsoft Corporation.<BR>
+ Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "TestBaseSafeIntLib.h"
+
+#define UNIT_TEST_NAME "Int Safe Lib Unit Test Application"
+#define UNIT_TEST_VERSION "0.1"
+
+//
+// Conversion function tests:
+//
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Operand;
+ UINT8 Result;
+
+ //
+ // Positive UINT8 should result in just a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt8ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Negative number should result in an error status
+ //
+ Operand = (-56);
+ Status = SafeInt8ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Operand;
+ UINT16 Result;
+
+ //
+ // Positive UINT8 should result in just a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt8ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Negative number should result in an error status
+ //
+ Operand = (-56);
+ Status = SafeInt8ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8ToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Operand;
+ UINT32 Result;
+
+ //
+ // Positive UINT8 should result in just a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt8ToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Negative number should result in an error status
+ //
+ Operand = (-56);
+ Status = SafeInt8ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Operand;
+ UINTN Result;
+
+ //
+ // Positive UINT8 should result in just a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt8ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Negative number should result in an error status
+ //
+ Operand = (-56);
+ Status = SafeInt8ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8ToUint64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Operand;
+ UINT64 Result;
+
+ //
+ // Positive UINT8 should result in just a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt8ToUint64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Negative number should result in an error status
+ //
+ Operand = (-56);
+ Status = SafeInt8ToUint64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint8ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Operand;
+ INT8 Result;
+
+ //
+ // Operand <= 0x7F (MAX_INT8) should result in a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint8ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Operand larger than 0x7f should result in an error status
+ //
+ Operand = 0xaf;
+ Status = SafeUint8ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint8ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Operand;
+ CHAR8 Result;
+
+ //
+ // CHAR8 is typedefed as char, which by default is signed, thus
+ // CHAR8 is same as INT8, so same tests as above:
+ //
+
+ //
+ // Operand <= 0x7F (MAX_INT8) should result in a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint8ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Operand larger than 0x7f should result in an error status
+ //
+ Operand = 0xaf;
+ Status = SafeUint8ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt16ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = (-35);
+ Status = SafeInt16ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-35), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = 0x1234;
+ Status = SafeInt16ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-17835);
+ Status = SafeInt16ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ CHAR8 Result;
+
+ //
+ // CHAR8 is typedefed as char, which may be signed or unsigned based
+ // on the compiler. Thus, for compatibility CHAR8 should be between 0 and MAX_INT8.
+ //
+
+ //
+ // If Operand is between 0 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = 0;
+ Result = 0;
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0, Result);
+
+ Operand = MAX_INT8;
+ Result = 0;
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(MAX_INT8, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-35);
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = 0x1234;
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-17835);
+ Status = SafeInt16ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is between 0 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt16ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = 0x1234;
+ Status = SafeInt16ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-17835);
+ Status = SafeInt16ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand = 0x5b5b;
+ UINT16 Result = 0;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Status = SafeInt16ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-17835);
+ Status = SafeInt16ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5b5b;
+ Result = 0;
+ Status = SafeInt16ToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-17835);
+ Status = SafeInt16ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ UINTN Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5b5b;
+ Result = 0;
+ Status = SafeInt16ToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-17835);
+ Status = SafeInt16ToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16ToUint64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Operand;
+ UINT64 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5b5b;
+ Result = 0;
+ Status = SafeInt16ToUint64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-17835);
+ Status = SafeInt16ToUint64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is <= MAX_INT8, it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint16ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5b5b);
+ Status = SafeUint16ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Operand;
+ CHAR8 Result;
+
+ // CHAR8 is typedefed as char, which by default is signed, thus
+ // CHAR8 is same as INT8, so same tests as above:
+
+ //
+ // If Operand is <= MAX_INT8, it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint16ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5b5b);
+ Status = SafeUint16ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is <= MAX_UINT8 (0xff), it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeUint16ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5b5b);
+ Status = SafeUint16ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16ToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Operand;
+ INT16 Result;
+
+ //
+ // If Operand is <= MAX_INT16 (0x7fff), it's a cast
+ //
+ Operand = 0x5b5b;
+ Result = 0;
+ Status = SafeUint16ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabab);
+ Status = SafeUint16ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt32ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = (-57);
+ Status = SafeInt32ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-57), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeInt32ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeInt32ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ CHAR8 Result;
+
+ //
+ // CHAR8 is typedefed as char, which may be signed or unsigned based
+ // on the compiler. Thus, for compatibility CHAR8 should be between 0 and MAX_INT8.
+ //
+
+ //
+ // If Operand is between 0 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = 0;
+ Result = 0;
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0, Result);
+
+ Operand = MAX_INT8;
+ Result = 0;
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(MAX_INT8, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-57);
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (0x5bababab);
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeInt32ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is between 0 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt32ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-57);
+ Status = SafeInt32ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (0x5bababab);
+ Status = SafeInt32ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeInt32ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ INT16 Result;
+
+ //
+ // If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast
+ //
+ Operand = 0x5b5b;
+ Result = 0;
+ Status = SafeInt32ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b5b, Result);
+
+ Operand = (-17857);
+ Status = SafeInt32ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-17857), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeInt32ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeInt32ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeInt32ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-17857);
+ Status = SafeInt32ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (0x5bababab);
+ Status = SafeInt32ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeInt32ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt32ToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeInt32ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUint64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Operand;
+ UINT64 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt32ToUint64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeInt32ToUint64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint32ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeUint32ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ CHAR8 Result;
+
+ // CHAR8 is typedefed as char, which by default is signed, thus
+ // CHAR8 is same as INT8, so same tests as above:
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint32ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeUint32ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is <= MAX_UINT8, then it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeUint32ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUint32ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ INT16 Result;
+
+ //
+ // If Operand is <= MAX_INT16, then it's a cast
+ //
+ Operand = 0x5bab;
+ Result = 0;
+ Status = SafeUint32ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUint32ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is <= MAX_UINT16, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeUint32ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUint32ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Operand;
+ INT32 Result;
+
+ //
+ // If Operand is <= MAX_INT32, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUint32ToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUint32ToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ INT8 Result;
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeIntnToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = (-53);
+ Status = SafeIntnToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-53), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeIntnToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ CHAR8 Result;
+
+ //
+ // CHAR8 is typedefed as char, which may be signed or unsigned based
+ // on the compiler. Thus, for compatibility CHAR8 should be between 0 and MAX_INT8.
+ //
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = 0;
+ Result = 0;
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0, Result);
+
+ Operand = MAX_INT8;
+ Result = 0;
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(MAX_INT8, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-53);
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (0x5bababab);
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT8 inclusive, then it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeIntnToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeIntnToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ INT16 Result;
+
+ //
+ // If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast
+ //
+ Operand = 0x5bab;
+ Result = 0;
+ Status = SafeIntnToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bab, Result);
+
+ Operand = (-23467);
+ Status = SafeIntnToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-23467), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeIntnToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeIntnToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5bababab);
+ Status = SafeIntnToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-1537977259);
+ Status = SafeIntnToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUintn (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINTN Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeIntnToUintn(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeIntnToUintn(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INTN Operand;
+ UINT64 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeIntnToUint64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-1537977259);
+ Status = SafeIntnToUint64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INT8 Result;
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUintnToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabab);
+ Status = SafeUintnToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ CHAR8 Result;
+
+ // CHAR8 is typedefed as char, which by default is signed, thus
+ // CHAR8 is same as INT8, so same tests as above:
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUintnToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabab);
+ Status = SafeUintnToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is <= MAX_UINT8, then it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeUintnToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabab);
+ Status = SafeUintnToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INT16 Result;
+
+ //
+ // If Operand is <= MAX_INT16, then it's a cast
+ //
+ Operand = 0x5bab;
+ Result = 0;
+ Status = SafeUintnToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabab);
+ Status = SafeUintnToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is <= MAX_UINT16, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeUintnToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUintnToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINTN Operand;
+ INT32 Result;
+
+ //
+ // If Operand is <= MAX_INT32, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUintnToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xabababab);
+ Status = SafeUintnToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt64ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = (-37);
+ Status = SafeInt64ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-37), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ CHAR8 Result;
+
+ //
+ // CHAR8 is typedefed as char, which may be signed or unsigned based
+ // on the compiler. Thus, for compatibility CHAR8 should be between 0 and MAX_INT8.
+ //
+
+ //
+ // If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ Operand = 0;
+ Result = 0;
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0, Result);
+
+ Operand = MAX_INT8;
+ Result = 0;
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(MAX_INT8, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-37);
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT8 inclusive, then it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeInt64ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ INT16 Result;
+
+ //
+ // If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast
+ //
+ Operand = 0x5bab;
+ Result = 0;
+ Status = SafeInt64ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bab, Result);
+
+ Operand = (-23467);
+ Status = SafeInt64ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-23467), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeInt64ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ INT32 Result;
+
+ //
+ // If Operand is between MIN_INT32 and MAX_INT32 inclusive, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeInt64ToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ Operand = (-1537977259);
+ Status = SafeInt64ToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-1537977259), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is between 0 and MAX_UINT32 inclusive, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeInt64ToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0x5babababefefefef);
+ Status = SafeInt64ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUint64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Operand;
+ UINT64 Result;
+
+ //
+ // If Operand is non-negative, then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeInt64ToUint64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (-6605562033422200815);
+ Status = SafeInt64ToUint64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToInt8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INT8 Result;
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint64ToInt8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToInt8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToChar8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ CHAR8 Result;
+
+ // CHAR8 is typedefed as char, which by default is signed, thus
+ // CHAR8 is same as INT8, so same tests as above:
+
+ //
+ // If Operand is <= MAX_INT8, then it's a cast
+ //
+ Operand = 0x5b;
+ Result = 0;
+ Status = SafeUint64ToChar8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5b, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToChar8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUint8 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ UINT8 Result;
+
+ //
+ // If Operand is <= MAX_UINT8, then it's a cast
+ //
+ Operand = 0xab;
+ Result = 0;
+ Status = SafeUint64ToUint8(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToUint8(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToInt16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INT16 Result;
+
+ //
+ // If Operand is <= MAX_INT16, then it's a cast
+ //
+ Operand = 0x5bab;
+ Result = 0;
+ Status = SafeUint64ToInt16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToInt16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUint16 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ UINT16 Result;
+
+ //
+ // If Operand is <= MAX_UINT16, then it's a cast
+ //
+ Operand = 0xabab;
+ Result = 0;
+ Status = SafeUint64ToUint16(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToUint16(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToInt32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INT32 Result;
+
+ //
+ // If Operand is <= MAX_INT32, then it's a cast
+ //
+ Operand = 0x5bababab;
+ Result = 0;
+ Status = SafeUint64ToInt32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5bababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToInt32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUint32 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ UINT32 Result;
+
+ //
+ // If Operand is <= MAX_UINT32, then it's a cast
+ //
+ Operand = 0xabababab;
+ Result = 0;
+ Status = SafeUint64ToUint32(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xabababab, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToUint32(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToInt64 (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Operand;
+ INT64 Result;
+
+ //
+ // If Operand is <= MAX_INT64, then it's a cast
+ //
+ Operand = 0x5babababefefefef;
+ Result = 0;
+ Status = SafeUint64ToInt64(Operand, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x5babababefefefef, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Operand = (0xababababefefefef);
+ Status = SafeUint64ToInt64(Operand, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+//
+// Addition function tests:
+//
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint8Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Augend;
+ UINT8 Addend;
+ UINT8 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINT8, then it's addition
+ //
+ Augend = 0x3a;
+ Addend = 0x3a;
+ Result = 0;
+ Status = SafeUint8Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xab;
+ Addend = 0xbc;
+ Status = SafeUint8Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Augend = 0x3a3a;
+ UINT16 Addend = 0x3a3a;
+ UINT16 Result = 0;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINT16, then it's addition
+ //
+ Status = SafeUint16Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xabab;
+ Addend = 0xbcbc;
+ Status = SafeUint16Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Augend;
+ UINT32 Addend;
+ UINT32 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINT32, then it's addition
+ //
+ Augend = 0x3a3a3a3a;
+ Addend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeUint32Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74747474, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xabababab;
+ Addend = 0xbcbcbcbc;
+ Status = SafeUint32Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Augend;
+ UINT64 Addend;
+ UINT64 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_UINT64, then it's addition
+ //
+ Augend = 0x3a3a3a3a12121212;
+ Addend = 0x3a3a3a3a12121212;
+ Result = 0;
+ Status = SafeUint64Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474747424242424, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0xababababefefefef;
+ Addend = 0xbcbcbcbcdededede;
+ Status = SafeUint64Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Augend;
+ INT8 Addend;
+ INT8 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INT8
+ // and doesn't underflow MIN_INT8, then it's addition
+ //
+ Augend = 0x3a;
+ Addend = 0x3a;
+ Result = 0;
+ Status = SafeInt8Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74, Result);
+
+ Augend = (-58);
+ Addend = (-58);
+ Status = SafeInt8Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-116), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a;
+ Addend = 0x5a;
+ Status = SafeInt8Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-90);
+ Addend = (-90);
+ Status = SafeInt8Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Augend;
+ INT16 Addend;
+ INT16 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INT16
+ // and doesn't underflow MIN_INT16, then it's addition
+ //
+ Augend = 0x3a3a;
+ Addend = 0x3a3a;
+ Result = 0;
+ Status = SafeInt16Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474, Result);
+
+ Augend = (-14906);
+ Addend = (-14906);
+ Status = SafeInt16Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-29812), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a5a;
+ Addend = 0x5a5a;
+ Status = SafeInt16Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-23130);
+ Addend = (-23130);
+ Status = SafeInt16Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Augend;
+ INT32 Addend;
+ INT32 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INT32
+ // and doesn't underflow MIN_INT32, then it's addition
+ //
+ Augend = 0x3a3a3a3a;
+ Addend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeInt32Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x74747474, Result);
+
+ Augend = (-976894522);
+ Addend = (-976894522);
+ Status = SafeInt32Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-1953789044), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a5a5a5a;
+ Addend = 0x5a5a5a5a;
+ Status = SafeInt32Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-1515870810);
+ Addend = (-1515870810);
+ Status = SafeInt32Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64Add (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Augend;
+ INT64 Addend;
+ INT64 Result;
+
+ //
+ // If the result of addition doesn't overflow MAX_INT64
+ // and doesn't underflow MIN_INT64, then it's addition
+ //
+ Augend = 0x3a3a3a3a3a3a3a3a;
+ Addend = 0x3a3a3a3a3a3a3a3a;
+ Result = 0;
+ Status = SafeInt64Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7474747474747474, Result);
+
+ Augend = (-4195730024608447034);
+ Addend = (-4195730024608447034);
+ Status = SafeInt64Add(Augend, Addend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-8391460049216894068), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Augend = 0x5a5a5a5a5a5a5a5a;
+ Addend = 0x5a5a5a5a5a5a5a5a;
+ Status = SafeInt64Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Augend = (-6510615555426900570);
+ Addend = (-6510615555426900570);
+ Status = SafeInt64Add(Augend, Addend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+//
+// Subtraction function tests:
+//
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint8Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Minuend;
+ UINT8 Subtrahend;
+ UINT8 Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a;
+ Subtrahend = 0x3b;
+ Result = 0;
+ Status = SafeUint8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a;
+ Subtrahend = 0x6d;
+ Status = SafeUint8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Minuend;
+ UINT16 Subtrahend;
+ UINT16 Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a5a;
+ Subtrahend = 0x3b3b;
+ Result = 0;
+ Status = SafeUint16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a5a;
+ Subtrahend = 0x6d6d;
+ Status = SafeUint16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Minuend;
+ UINT32 Subtrahend;
+ UINT32 Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x3b3b3b3b;
+ Result = 0;
+ Status = SafeUint32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f1f1f1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x6d6d6d6d;
+ Status = SafeUint32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Minuend;
+ UINT64 Subtrahend;
+ UINT64 Result;
+
+ //
+ // If Minuend >= Subtrahend, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x3b3b3b3b3b3b3b3b;
+ Result = 0;
+ Status = SafeUint64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x1f1f1f1f1f1f1f1f, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x6d6d6d6d6d6d6d6d;
+ Status = SafeUint64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Minuend;
+ INT8 Subtrahend;
+ INT8 Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INT8 or
+ // underflow MIN_INT8, then it's subtraction
+ //
+ Minuend = 0x5a;
+ Subtrahend = 0x3a;
+ Result = 0;
+ Status = SafeInt8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x20, Result);
+
+ Minuend = 58;
+ Subtrahend = 78;
+ Status = SafeInt8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-20), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-80);
+ Subtrahend = 80;
+ Status = SafeInt8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (80);
+ Subtrahend = (-80);
+ Status = SafeInt8Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Minuend;
+ INT16 Subtrahend;
+ INT16 Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INT16 or
+ // underflow MIN_INT16, then it's subtraction
+ //
+ Minuend = 0x5a5a;
+ Subtrahend = 0x3a3a;
+ Result = 0;
+ Status = SafeInt16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x2020, Result);
+
+ Minuend = 0x3a3a;
+ Subtrahend = 0x5a5a;
+ Status = SafeInt16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-8224), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-31354);
+ Subtrahend = 31354;
+ Status = SafeInt16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (31354);
+ Subtrahend = (-31354);
+ Status = SafeInt16Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Minuend;
+ INT32 Subtrahend;
+ INT32 Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INT32 or
+ // underflow MIN_INT32, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a;
+ Subtrahend = 0x3a3a3a3a;
+ Result = 0;
+ Status = SafeInt32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x20202020, Result);
+
+ Minuend = 0x3a3a3a3a;
+ Subtrahend = 0x5a5a5a5a;
+ Status = SafeInt32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-538976288), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-2054847098);
+ Subtrahend = 2054847098;
+ Status = SafeInt32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (2054847098);
+ Subtrahend = (-2054847098);
+ Status = SafeInt32Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64Sub (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Minuend;
+ INT64 Subtrahend;
+ INT64 Result;
+
+ //
+ // If the result of subtractions doesn't overflow MAX_INT64 or
+ // underflow MIN_INT64, then it's subtraction
+ //
+ Minuend = 0x5a5a5a5a5a5a5a5a;
+ Subtrahend = 0x3a3a3a3a3a3a3a3a;
+ Result = 0;
+ Status = SafeInt64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x2020202020202020, Result);
+
+ Minuend = 0x3a3a3a3a3a3a3a3a;
+ Subtrahend = 0x5a5a5a5a5a5a5a5a;
+ Status = SafeInt64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL((-2314885530818453536), Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Minuend = (-8825501086245354106);
+ Subtrahend = 8825501086245354106;
+ Status = SafeInt64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ Minuend = (8825501086245354106);
+ Subtrahend = (-8825501086245354106);
+ Status = SafeInt64Sub(Minuend, Subtrahend, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+//
+// Multiplication function tests:
+//
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint8Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Multiplicand;
+ UINT8 Multiplier;
+ UINT8 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINT8, it will succeed
+ //
+ Multiplicand = 0x12;
+ Multiplier = 0xa;
+ Result = 0;
+ Status = SafeUint8Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xb4, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x12;
+ Multiplier = 0x23;
+ Status = SafeUint8Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint16Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Multiplicand;
+ UINT16 Multiplier;
+ UINT16 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINT16, it will succeed
+ //
+ Multiplicand = 0x212;
+ Multiplier = 0x7a;
+ Result = 0;
+ Status = SafeUint16Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0xfc94, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x1234;
+ Multiplier = 0x213;
+ Status = SafeUint16Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Multiplicand;
+ UINT32 Multiplier;
+ UINT32 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINT32, it will succeed
+ //
+ Multiplicand = 0xa122a;
+ Multiplier = 0xd23;
+ Result = 0;
+ Status = SafeUint32Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x844c9dbe, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0xa122a;
+ Multiplier = 0xed23;
+ Status = SafeUint32Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Multiplicand;
+ UINT64 Multiplier;
+ UINT64 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_UINT64, it will succeed
+ //
+ Multiplicand = 0x123456789a;
+ Multiplier = 0x1234567;
+ Result = 0;
+ Status = SafeUint64Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x14b66db9745a07f6, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456789a;
+ Multiplier = 0x12345678;
+ Status = SafeUint64Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt8Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT8 Multiplicand;
+ INT8 Multiplier;
+ INT8 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INT8 and doesn't
+ // underflow MIN_UINT8, it will succeed
+ //
+ Multiplicand = 0x12;
+ Multiplier = 0x7;
+ Result = 0;
+ Status = SafeInt8Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7e, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x12;
+ Multiplier = 0xa;
+ Status = SafeInt8Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt16Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT16 Multiplicand;
+ INT16 Multiplier;
+ INT16 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INT16 and doesn't
+ // underflow MIN_UINT16, it will succeed
+ //
+ Multiplicand = 0x123;
+ Multiplier = 0x67;
+ Result = 0;
+ Status = SafeInt16Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x7515, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123;
+ Multiplier = 0xab;
+ Status = SafeInt16Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT32 Multiplicand;
+ INT32 Multiplier;
+ INT32 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INT32 and doesn't
+ // underflow MIN_UINT32, it will succeed
+ //
+ Multiplicand = 0x123456;
+ Multiplier = 0x678;
+ Result = 0;
+ Status = SafeInt32Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x75c28c50, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456;
+ Multiplier = 0xabc;
+ Status = SafeInt32Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64Mult (
+ IN UNIT_TEST_CONTEXT Context
+ )
+{
+ EFI_STATUS Status;
+ INT64 Multiplicand;
+ INT64 Multiplier;
+ INT64 Result;
+
+ //
+ // If the result of multiplication doesn't overflow MAX_INT64 and doesn't
+ // underflow MIN_UINT64, it will succeed
+ //
+ Multiplicand = 0x123456789;
+ Multiplier = 0x6789abcd;
+ Result = 0;
+ Status = SafeInt64Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_NOT_EFI_ERROR(Status);
+ UT_ASSERT_EQUAL(0x75cd9045220d6bb5, Result);
+
+ //
+ // Otherwise should result in an error status
+ //
+ Multiplicand = 0x123456789;
+ Multiplier = 0xa789abcd;
+ Status = SafeInt64Mult(Multiplicand, Multiplier, &Result);
+ UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);
+
+ return UNIT_TEST_PASSED;
+}
+
+/**
+
+ Main fuction sets up the unit test environment
+
+**/
+EFI_STATUS
+EFIAPI
+UefiTestMain (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UNIT_TEST_FRAMEWORK_HANDLE Framework;
+ UNIT_TEST_SUITE_HANDLE ConversionTestSuite;
+ UNIT_TEST_SUITE_HANDLE AdditionSubtractionTestSuite;
+ UNIT_TEST_SUITE_HANDLE MultiplicationTestSuite;
+
+ Framework = NULL;
+ ConversionTestSuite = NULL;
+ AdditionSubtractionTestSuite = NULL;
+ MultiplicationTestSuite = NULL;
+
+ DEBUG((DEBUG_INFO, "%a v%a\n", UNIT_TEST_NAME, UNIT_TEST_VERSION));
+
+ //
+ // Start setting up the test framework for running the tests.
+ //
+ Status = InitUnitTestFramework (&Framework, UNIT_TEST_NAME, gEfiCallerBaseName, UNIT_TEST_VERSION);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));
+ goto EXIT;
+ }
+
+ ///
+ // Test the conversion functions
+ //
+ Status = CreateUnitTestSuite (&ConversionTestSuite, Framework, "Int Safe Conversions Test Suite", "Common.SafeInt.Convert", NULL,
NULL);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Conversions Test Suite\n"));
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+ AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint8", "TestSafeInt8ToUint8", TestSafeInt8ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint16", "TestSafeInt8ToUint16", TestSafeInt8ToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint32", "TestSafeInt8ToUint32", TestSafeInt8ToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt8ToUintn", "TestSafeInt8ToUintn", TestSafeInt8ToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint64", "TestSafeInt8ToUint64", TestSafeInt8ToUint64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint8ToInt8", "TestSafeUint8ToInt8", TestSafeUint8ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint8ToChar8", "TestSafeUint8ToChar8", TestSafeUint8ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToInt8", "TestSafeInt16ToInt8", TestSafeInt16ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToChar8", "TestSafeInt16ToChar8", TestSafeInt16ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint8", "TestSafeInt16ToUint8", TestSafeInt16ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint16", "TestSafeInt16ToUint16", TestSafeInt16ToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint32", "TestSafeInt16ToUint32", TestSafeInt16ToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToUintn", "TestSafeInt16ToUintn", TestSafeInt16ToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint64", "TestSafeInt16ToUint64", TestSafeInt16ToUint64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint16ToInt8", "TestSafeUint16ToInt8", TestSafeUint16ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint16ToChar8", "TestSafeUint16ToChar8", TestSafeUint16ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint16ToUint8", "TestSafeUint16ToUint8", TestSafeUint16ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint16ToInt16", "TestSafeUint16ToInt16", TestSafeUint16ToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToInt8", "TestSafeInt32ToInt8", TestSafeInt32ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToChar8", "TestSafeInt32ToChar8", TestSafeInt32ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint8", "TestSafeInt32ToUint8", TestSafeInt32ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToInt16", "TestSafeInt32ToInt16", TestSafeInt32ToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint16", "TestSafeInt32ToUint16", TestSafeInt32ToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint32", "TestSafeInt32ToUint32", TestSafeInt32ToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToUintn", "TestSafeInt32ToUintn", TestSafeInt32ToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint64", "TestSafeInt32ToUint64", TestSafeInt32ToUint64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt8", "TestSafeUint32ToInt8", TestSafeUint32ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToChar8", "TestSafeUint32ToChar8", TestSafeUint32ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToUint8", "TestSafeUint32ToUint8", TestSafeUint32ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt16", "TestSafeUint32ToInt16", TestSafeUint32ToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToUint16", "TestSafeUint32ToUint16", TestSafeUint32ToUint16, NULL, NULL,
NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt32", "TestSafeUint32ToInt32", TestSafeUint32ToInt32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint32ToIntn", "TestSafeUint32ToIntn", TestSafeUint32ToIntn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToInt8", "TestSafeIntnToInt8", TestSafeIntnToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToChar8", "TestSafeIntnToChar8", TestSafeIntnToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToUint8", "TestSafeIntnToUint8", TestSafeIntnToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToInt16", "TestSafeIntnToInt16", TestSafeIntnToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToUint16", "TestSafeIntnToUint16", TestSafeIntnToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToInt32", "TestSafeIntnToInt32", TestSafeIntnToInt32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToUint32", "TestSafeIntnToUint32", TestSafeIntnToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToUintn", "TestSafeIntnToUintn", TestSafeIntnToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeIntnToUint64", "TestSafeIntnToUint64", TestSafeIntnToUint64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToInt8", "TestSafeUintnToInt8", TestSafeUintnToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToChar8", "TestSafeUintnToChar8", TestSafeUintnToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToUint8", "TestSafeUintnToUint8", TestSafeUintnToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToInt16", "TestSafeUintnToInt16", TestSafeUintnToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToUint16", "TestSafeUintnToUint16", TestSafeUintnToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToInt32", "TestSafeUintnToInt32", TestSafeUintnToInt32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToUint32", "TestSafeUintnToUint32", TestSafeUintnToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToIntn", "TestSafeUintnToIntn", TestSafeUintnToIntn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUintnToInt64", "TestSafeUintnToInt64", TestSafeUintnToInt64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt8", "TestSafeInt64ToInt8", TestSafeInt64ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToChar8", "TestSafeInt64ToChar8", TestSafeInt64ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint8", "TestSafeInt64ToUint8", TestSafeInt64ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt16", "TestSafeInt64ToInt16", TestSafeInt64ToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint16", "TestSafeInt64ToUint16", TestSafeInt64ToUint16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt32", "TestSafeInt64ToInt32", TestSafeInt64ToInt32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint32", "TestSafeInt64ToUint32", TestSafeInt64ToUint32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToIntn", "TestSafeInt64ToIntn", TestSafeInt64ToIntn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToUintn", "TestSafeInt64ToUintn", TestSafeInt64ToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint64", "TestSafeInt64ToUint64", TestSafeInt64ToUint64, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt8", "TestSafeUint64ToInt8", TestSafeUint64ToInt8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToChar8", "TestSafeUint64ToChar8", TestSafeUint64ToChar8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint8", "TestSafeUint64ToUint8", TestSafeUint64ToUint8, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt16", "TestSafeUint64ToInt16", TestSafeUint64ToInt16, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint16", "TestSafeUint64ToUint16", TestSafeUint64ToUint16, NULL, NULL,
NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt32", "TestSafeUint64ToInt32", TestSafeUint64ToInt32, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint32", "TestSafeUint64ToUint32", TestSafeUint64ToUint32, NULL, NULL,
NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToIntn", "TestSafeUint64ToIntn", TestSafeUint64ToIntn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToUintn", "TestSafeUint64ToUintn", TestSafeUint64ToUintn, NULL, NULL, NULL);
+ AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt64", "TestSafeUint64ToInt64", TestSafeUint64ToInt64, NULL, NULL, NULL);
+
+ //
+ // Test the addition and subtraction functions
+ //
+ Status = CreateUnitTestSuite(&AdditionSubtractionTestSuite, Framework, "Int Safe Add/Subtract Test Suite",
"Common.SafeInt.AddSubtract", NULL, NULL);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Add/Subtract Test Suite\n"));
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint8Add", "TestSafeUint8Add", TestSafeUint8Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint16Add", "TestSafeUint16Add", TestSafeUint16Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint32Add", "TestSafeUint32Add", TestSafeUint32Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUintnAdd", "TestSafeUintnAdd", TestSafeUintnAdd, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint64Add", "TestSafeUint64Add", TestSafeUint64Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt8Add", "TestSafeInt8Add", TestSafeInt8Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt16Add", "TestSafeInt16Add", TestSafeInt16Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt32Add", "TestSafeInt32Add", TestSafeInt32Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeIntnAdd", "TestSafeIntnAdd", TestSafeIntnAdd, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt64Add", "TestSafeInt64Add", TestSafeInt64Add, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint8Sub", "TestSafeUint8Sub", TestSafeUint8Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint16Sub", "TestSafeUint16Sub", TestSafeUint16Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint32Sub", "TestSafeUint32Sub", TestSafeUint32Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUintnSub", "TestSafeUintnSub", TestSafeUintnSub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint64Sub", "TestSafeUint64Sub", TestSafeUint64Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt8Sub", "TestSafeInt8Sub", TestSafeInt8Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt16Sub", "TestSafeInt16Sub", TestSafeInt16Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt32Sub", "TestSafeInt32Sub", TestSafeInt32Sub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeIntnSub", "TestSafeIntnSub", TestSafeIntnSub, NULL, NULL, NULL);
+ AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt64Sub", "TestSafeInt64Sub", TestSafeInt64Sub, NULL, NULL, NULL);
+
+ //
+ // Test the multiplication functions
+ //
+ Status = CreateUnitTestSuite(&MultiplicationTestSuite, Framework, "Int Safe Multiply Test Suite", "Common.SafeInt.Multiply", NULL,
NULL);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Multiply Test Suite\n"));
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+ AddTestCase(MultiplicationTestSuite, "Test SafeUint8Mult", "TestSafeUint8Mult", TestSafeUint8Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeUint16Mult", "TestSafeUint16Mult", TestSafeUint16Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeUint32Mult", "TestSafeUint32Mult", TestSafeUint32Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeUintnMult", "TestSafeUintnMult", TestSafeUintnMult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeUint64Mult", "TestSafeUint64Mult", TestSafeUint64Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeInt8Mult", "TestSafeInt8Mult", TestSafeInt8Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeInt16Mult", "TestSafeInt16Mult", TestSafeInt16Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeInt32Mult", "TestSafeInt32Mult", TestSafeInt32Mult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeIntnMult", "TestSafeIntnMult", TestSafeIntnMult, NULL, NULL, NULL);
+ AddTestCase(MultiplicationTestSuite, "Test SafeInt64Mult", "TestSafeInt64Mult", TestSafeInt64Mult, NULL, NULL, NULL);
+
+ //
+ // Execute the tests.
+ //
+ Status = RunAllTestSuites(Framework);
+
+EXIT:
+ if (Framework != NULL) {
+ FreeUnitTestFramework(Framework);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+PeiEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ return UefiTestMain ();
+}
+
+EFI_STATUS
+EFIAPI
+DxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return UefiTestMain ();
+}
+
+int
+main (
+ int argc,
+ char *argv[]
+ )
+{
+ return UefiTestMain ();
+}
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.h
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.h
new file mode 100644
index 0000000000..7957c99a85
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.h
@@ -0,0 +1,123 @@
+/** @file
+ UEFI OS based application for unit testing the SafeIntLib.
+
+ Copyright (c) Microsoft Corporation.<BR>
+ Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TEST_BASE_SAFE_INT_LIB_H_
+#define _TEST_BASE_SAFE_INT_LIB_H_
+
+#include <PiPei.h>
+#include <Uefi.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UnitTestLib.h>
+#include <Library/SafeIntLib.h>
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt32ToUintn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint32ToIntn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToInt32(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnToUint32(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToUint32(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToIntn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnToInt64(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToIntn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeInt64ToUintn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToIntn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUint64ToUintn(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnAdd(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnAdd(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnSub(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnSub(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeUintnMult(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+UNIT_TEST_STATUS
+EFIAPI
+TestSafeIntnMult(
+ IN UNIT_TEST_CONTEXT Context
+ );
+
+#endif
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.uni
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.uni
new file mode 100644
index 0000000000..956835c30d
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.uni
@@ -0,0 +1,13 @@
+// /** @file
+// Application that Unit Tests the SafeIntLib
+//
+// Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "Application that Unit Tests the SafeIntLib"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Application that Unit Tests the SafeIntLib."
+
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibDxe.inf
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibDxe.inf
new file mode 100644
index 0000000000..de67b04bd5
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibDxe.inf
@@ -0,0 +1,45 @@
+## @file
+# DXE Driver that Unit Tests the SafeIntLib
+#
+# Copyright (c) Microsoft Corporation.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TestBaseSafeIntLibDxe
+ MODULE_UNI_FILE = TestBaseSafeIntLib.uni
+ FILE_GUID = 9729DB60-FB9D-4625-9EE1-93B21EC246B8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = DxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ TestBaseSafeIntLib.c
+ TestBaseSafeIntLib.h
+
+[Sources.Ia32, Sources.ARM]
+ SafeIntLibUintnIntnUnitTests32.c
+
+[Sources.X64, Sources.AARCH64]
+ SafeIntLibUintnIntnUnitTests64.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ SafeIntLib
+ UnitTestLib
+
+[Depex]
+ TRUE
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
new file mode 100644
index 0000000000..35c93fdeac
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
@@ -0,0 +1,40 @@
+## @file
+# Host OS based Application that Unit Tests the SafeIntLib
+#
+# Copyright (c) Microsoft Corporation.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TestBaseSafeIntLibHost
+ MODULE_UNI_FILE = TestBaseSafeIntLib.uni
+ FILE_GUID = 95487689-9E30-41AD-B773-3650C94BCBE2
+ MODULE_TYPE = HOST_APPLICATION
+ VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ TestBaseSafeIntLib.c
+ TestBaseSafeIntLib.h
+
+[Sources.Ia32, Sources.ARM]
+ SafeIntLibUintnIntnUnitTests32.c
+
+[Sources.X64, Sources.AARCH64]
+ SafeIntLibUintnIntnUnitTests64.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ SafeIntLib
+ UnitTestLib
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibPei.inf
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibPei.inf
new file mode 100644
index 0000000000..c8ba4f44ef
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibPei.inf
@@ -0,0 +1,45 @@
+## @file
+# PEIM that Unit Tests the SafeIntLib
+#
+# Copyright (c) Microsoft Corporation.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TestBaseSafeIntLibPei
+ MODULE_UNI_FILE = TestBaseSafeIntLib.uni
+ FILE_GUID = 7D910602-ED53-45E6-826E-8266705B9734
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PeiEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ TestBaseSafeIntLib.c
+ TestBaseSafeIntLib.h
+
+[Sources.Ia32, Sources.ARM]
+ SafeIntLibUintnIntnUnitTests32.c
+
+[Sources.X64, Sources.AARCH64]
+ SafeIntLibUintnIntnUnitTests64.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ BaseLib
+ DebugLib
+ SafeIntLib
+ UnitTestLib
+
+[Depex]
+ TRUE
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
new file mode 100644
index 0000000000..df7288501d
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
@@ -0,0 +1,45 @@
+## @file
+# SMM Driver that Unit Tests the SafeIntLib
+#
+# Copyright (c) Microsoft Corporation.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TestBaseSafeIntLibSmm
+ MODULE_UNI_FILE = TestBaseSafeIntLib.uni
+ FILE_GUID = 2F2A1907-B1B4-4E33-8B83-62A60AB4F0D4
+ MODULE_TYPE = DXE_SMM_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = DxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ TestBaseSafeIntLib.c
+ TestBaseSafeIntLib.h
+
+[Sources.Ia32, Sources.ARM]
+ SafeIntLibUintnIntnUnitTests32.c
+
+[Sources.X64, Sources.AARCH64]
+ SafeIntLibUintnIntnUnitTests64.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ SafeIntLib
+ UnitTestLib
+
+[Depex]
+ TRUE
diff --git a/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf
b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf
new file mode 100644
index 0000000000..5a13c1c845
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf
@@ -0,0 +1,42 @@
+## @file
+# UEFI Shell based Application that Unit Tests the SafeIntLib
+#
+# Copyright (c) Microsoft Corporation.<BR>
+# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TestBaseSafeIntLibUefiShell
+ MODULE_UNI_FILE = TestBaseSafeIntLib.uni
+ FILE_GUID = 1F91B73E-5B6A-4317-80E8-E7C36A3C7AF4
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ ENTRY_POINT = DxeEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ TestBaseSafeIntLib.c
+ TestBaseSafeIntLib.h
+
+[Sources.Ia32, Sources.ARM]
+ SafeIntLibUintnIntnUnitTests32.c
+
+[Sources.X64, Sources.AARCH64]
+ SafeIntLibUintnIntnUnitTests64.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiApplicationEntryPoint
+ BaseLib
+ DebugLib
+ SafeIntLib
+ UnitTestLib
--
2.21.0.windows.1


[PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG

Pankaj Bansal
 

Add LX2160ARDBPKG

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/Include/Qixis.h | 40 ++++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 54 ++++++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 172 ++++++++++++++++++
.../AArch64/ArmPlatformHelper.S | 46 +++++
.../Library/ArmPlatformLib/ArmPlatformLib.c | 168 +++++++++++++++++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 45 +++++
.../ArmPlatformLib/ArmPlatformLibInternal.h | 26 +++
.../ArmPlatformLib/ArmPlatformLibMem.c | 80 ++++++++
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 90 +++++++++
Platform/NXP/NxpQoriqLsPlatform.dec | 23 +++
11 files changed, 767 insertions(+)
create mode 100644 Platform/NXP/Include/Qixis.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/NxpQoriqLsPlatform.dec

diff --git a/Platform/NXP/Include/Qixis.h b/Platform/NXP/Include/Qixis.h
new file mode 100644
index 0000000000..116e4c1b30
--- /dev/null
+++ b/Platform/NXP/Include/Qixis.h
@@ -0,0 +1,40 @@
+/** @file
+ Qixis Layout.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __QIXIS_H__
+#define __QIXIS_H__
+
+#include <Uefi.h>
+
+typedef struct _QIXIS_MIN_LAYOUT {
+ UINT8 Id;
+ UINT8 Ver;
+ UINT8 Qver;
+ UINT8 Model;
+ UINT8 Minor;
+ UINT8 Ctl;
+ UINT8 Aux;
+ UINT8 Reserved007[0x040 - 0x007];
+ UINT8 ResetCtl;
+ UINT8 ResetStat;
+ UINT8 ResetReason;
+ UINT8 ResetForce[3];
+ UINT8 Reserved046[0x04B - 0x046];
+ UINT8 ResetMask[3];
+ UINT8 Reserved04E[0x050 - 0x04E];
+ UINT8 BoardConfig[16];
+ UINT8 DutConfig[16];
+ UINT8 Reserved070[0x090 - 0x070];
+ UINT8 IrqStat[4];
+ UINT8 IrqCtl[4];
+ UINT8 IrqDrv[8];
+ UINT8 Reserved0A0[0x0D8 - 0x0A0];
+} QIXIS_MIN_LAYOUT;
+
+#endif
+
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index 0000000000..192eabc5b3
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+# LX2160aRdbPkg.dec
+# LX2160a board package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LX2160aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index 0000000000..773b211b7d
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,54 @@
+# LX2160aRdbPkg.dsc
+#
+# LX2160ARDB Board package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LX2160aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LX2160aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+!include Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+ RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+[PcdsFixedAtBuild.common]
+ #
+ # RTC Pcds
+ #
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index 0000000000..ed7c39365c
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,172 @@
+# LX2160aRdbPkg.fdf
+#
+# FLASH layout file for LX2160aRdb board.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LX2160ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0x100000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include VarStore.fdf.inc
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000000..d1b9f1debb
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,46 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000000..adcc3315dd
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,168 @@
+/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Soc.h>
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <Library/DebugLib.h>
+#include <Library/I2cLib.h>
+#include <Library/SocLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+#include "ArmPlatformLibInternal.h"
+
+ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0, 0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINT8 Reg;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Status = I2cBusReadReg (
+ LX2160A_I2C0_PHYS_ADDRESS, QIXIS_I2C_ADDRESS,
+ OFFSET_OF (QIXIS_LAYOUT, BoardConfig[1]),
+ 1, &Reg, sizeof (Reg)
+ );
+ ASSERT_EFI_ERROR (Status);
+ switch (Reg & 0x03) {
+ case 0x00:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ default:
+ ASSERT(0); // All other values are reserved
+ break;
+ }
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ UINT64 Clock;
+
+ TimerConstructor ();
+
+ I2cEarlyInitialize (LX2160A_I2C0_PHYS_ADDRESS);
+
+ Clock = NxpPlatformGetClock (NXP_I2C_CLOCK, 0);
+
+ // Set I2c Clock 100 KHz
+ I2cInitialize (LX2160A_I2C0_PHYS_ADDRESS, Clock, 100 * 1000);
+
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = mArmPlatformMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000000..24258e1502
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,45 @@
+#/* @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = ArmPlatformLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
+ Platform/NXP/NxpQoriqLsPlatform.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+ I2cLib
+ DebugLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ ArmPlatformLibMem.c
+
+[Sources.AArch64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
new file mode 100644
index 0000000000..fefbd273c8
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
@@ -0,0 +1,26 @@
+/** @file
+ Platform Specific data.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_PLATFORM_LIB_INTERNAL_H__
+#define __ARM_PLATFORM_LIB_INTERNAL_H__
+
+#include <Qixis.h>
+
+// This function should be better located into TimerLib implementation
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ );
+
+#define QIXIS_I2C_ADDRESS 0x66
+
+typedef QIXIS_MIN_LAYOUT QIXIS_LAYOUT;
+
+#endif
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index 0000000000..85bd7e6307
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,80 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 10
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT32 Index;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+ return;
+ }
+
+ Index = 0;
+ // DRAM
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // FlexSPI region
+ // TODO: check if we can change attributes for better performance
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_FLEXSPI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000000..215d73dd8f
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,90 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[FD.LX2160ARDBNV_EFI]
+
+BaseAddress = 0x20500000
+Size = 0x000C0000
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Platform/NXP/NxpQoriqLsPlatform.dec b/Platform/NXP/NxpQoriqLsPlatform.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLsPlatform.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
--
2.17.1


[PATCH 18/19] Silicon/NXP: Add LX2160A SocLib

Pankaj Bansal
 

Add LX2160A SocLib

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h | 39 +++++++++
Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec | 23 ++++++
.../NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc | 34 ++++++++
.../LX2160A/Library/SocLib/SocLib.c | 79 +++++++++++++++++++
.../LX2160A/Library/SocLib/SocLib.inf | 31 ++++++++
5 files changed, 206 insertions(+)
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf

diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
new file mode 100644
index 0000000000..cc1f91272d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LX2160A_CCSR_PHYS_ADDRESS 0x1000000
+#define LX2160A_CCSR_SIZE 0xF000000
+
+#define LX2160A_FLEXSPI_PHYS_ADDRESS 0x20000000
+#define LX2160A_FLEXSPI_SIZE SIZE_256MB
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+#define LX2160A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LX2160A_DRAM0_SIZE SIZE_2GB
+#define LX2160A_DRAM1_PHYS_ADDRESS 0x2080000000
+#define LX2160A_DRAM1_SIZE 0x1F80000000 // 128 GB
+
+#define LX2160A_I2C0_PHYS_ADDRESS 0x2000000
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
+
+#endif
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
new file mode 100644
index 0000000000..f786a57ebc
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,34 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+[PcdsFixedAtBuild.common]
+## PL011 Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|16
+
+[PcdsDynamicDefault.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x20000000
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0c0c0000
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
new file mode 100644
index 0000000000..2c19c72b5f
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
@@ -0,0 +1,79 @@
+/** @file
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+#include <Soc.h>
+#include <Library/ChassisLib.h>
+#include <Library/SocLib.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ )
+{
+ LX2160A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 3; // platform pll / 8
+ break;
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 4; // platform pll / 16
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index 0000000000..ea9d45a021
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,31 @@
+#@file
+#
+# Component description file for SocLib module
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = SocLib
+ FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Sources.common]
+ SocLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
+
+[LibraryClasses]
+ ChassisLib
--
2.17.1


[PATCH 17/19] Silicon/NXP: Add Chassis3V2

Pankaj Bansal
 

Add Chassis3V2

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +++
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +
Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 ++++
.../Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
.../Library/ChassisLib/ChassisLib.inf | 41 ++++
5 files changed, 302 insertions(+)
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf

diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index 0000000000..dabe2ae230
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index 0000000000..2771f26fe3
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
+
+#define TP_CLUSTER_ITYPE_IDX 0x3f
+#define TP_CLUSTER_EOC BIT31
+#define TP_ITYPE_AVAILABLE BIT0
+#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
+#define TP_ITYPE_ARM 0x0
+#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
+
+#define TP_ITYPE_VERSION_A53 0x2
+#define TP_ITYPE_VERSION_A72 0x4
+
+/**
+ The Device Configuration Unit provides general purpose configuration and status for the
+ device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[32]; // Reset Control Word Status Register
+ UINT8 Reserved180[0x200 - 0x180];
+ UINT32 ScratchRw[16]; /// Scratch Read / Write Register
+ UINT8 Reserved240[0x740-0x240];
+ UINT32 TpItyp[65]; /// Topology Initiator Type Register
+ struct {
+ UINT32 Lower;
+ UINT32 Upper;
+ }TpCluster[8];
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 0000000000..99567bb76f
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,186 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+/**
+ Get the type of core in cluster
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
+ @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
+ These cores are identified based on their codes like TP_ITYPE_VERSION_A72
+
+ @return EFI_NOT_FOUND No enabled ARM core found
+ @return EFI_SUCCESS An enabled ARM core found
+**/
+STATIC
+EFI_STATUS
+SocGetCoreType (
+ IN UINT8 TpItypeIdx,
+ OUT UINT8 *CoreType
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpItype;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
+ TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
+ if (TpItype & TP_ITYPE_AVAILABLE) {
+ if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
+ *CoreType = TP_ITYPE_VERSION (TpItype);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ } else {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned
+ value number of entries in ArmCoreTable are valid entries.
+**/
+UINTN
+__attribute__((weak))
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN CoreTableSize
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpClusterLower;
+ UINT8 TpClusterParser;
+ UINT8 ClusterIndex;
+ UINT8 CoreIndex;
+ UINTN CoreCount;
+ UINT8 CoreType;
+ EFI_STATUS Status;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
+ ClusterIndex = 0;
+ CoreCount = 0;
+ while (TRUE) {
+ TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
+ for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
+ TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
+ Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
+ if (Status != EFI_NOT_FOUND) {
+ ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
+ ArmCoreTable[CoreCount].CoreId = CoreIndex;
+ ArmCoreTable[CoreCount].MailboxSetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxGetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearValue = ~0;
+
+ NxpCoreTable[CoreCount] = CoreType;
+ CoreCount++;
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ }
+ }
+ if (TpClusterLower & TP_CLUSTER_EOC) {
+ break;
+ }
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ ClusterIndex++;
+ }
+
+ return CoreCount;
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+}
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 0000000000..302296bf65
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Chassis3V2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+
+[LibraryClasses]
+ IoLib
+ IoAccessLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
+
--
2.17.1


[PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib

Pankaj Bansal
 

Use ArmPlatformPkg/PL011SerialPortLib with some changes:
1. add Get clock API to get the UART clock from ArmPlatformLib
2. remove SerialPortInitalize functionality

This is same as being done in Silicon/NXP/Library/BaseSerialPortLib16550.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../PL011SerialPortLib/PL011SerialPortLib.c | 229 ++++++++++++++++++
.../PL011SerialPortLib/PL011SerialPortLib.inf | 42 ++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 1 +
3 files changed, 272 insertions(+)
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf

diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
new file mode 100644
index 0000000000..35cfe8e324
--- /dev/null
+++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
@@ -0,0 +1,229 @@
+/** @file
+ Serial I/O Port library functions with no library constructor/destructor
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012 - 2016, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PL011UartClockLib.h>
+#include <Library/PL011UartLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
+
+/** Initialise the serial device hardware with default settings.
+
+ @retval RETURN_SUCCESS The serial device was initialised.
+ @retval RETURN_INVALID_PARAMETER One or more of the default settings
+ has an unsupported value.
+ **/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
+}
+
+/**
+ Read data from serial device and save the data in buffer.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
+}
+
+/**
+ Check to see if any data is available to be read from the debug device.
+
+ @retval TRUE At least one byte of data is available to be read
+ @retval FALSE No data is available to be read
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase));
+}
+/**
+ Set new attributes to PL011.
+
+ @param BaudRate The baud rate of the serial device. If the
+ baud rate is not supported, the speed will
+ be reduced down to the nearest supported one
+ and the variable's value will be updated
+ accordingly.
+ @param ReceiveFifoDepth The number of characters the device will
+ buffer on input. If the specified value is
+ not supported, the variable's value will
+ be reduced down to the nearest supported one.
+ @param Timeout If applicable, the number of microseconds the
+ device will wait before timing out a Read or
+ a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE
+ that is computed or checked as each character
+ is transmitted or received. If the device
+ does not support parity, the value is the
+ default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
+ of stop bits per character. If the device
+ does not support stop bits, the value is the
+ default stop bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly.
+ @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
+ value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ UINT64 SerialClock;
+
+ SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+ if (SerialClock == 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return PL011UartInitializePort (
+ (UINTN)PcdGet64 (PcdSerialRegisterBase),
+ SerialClock,
+ BaudRate,
+ ReceiveFifoDepth,
+ Parity,
+ DataBits,
+ StopBits
+ );
+}
+
+/**
+
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval RETURN_SUCCESS The new control bits were set on the device.
+ @retval RETURN_UNSUPPORTED The device does not support this operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ return PL011UartSetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
+}
+
+/**
+
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the output feeds
+ the receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
+ if a loopback is accomplished by software, else 0.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval RETURN_SUCCESS The control bits were read from the device.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ return PL011UartGetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
+}
diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
new file mode 100644
index 0000000000..29f234027f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
@@ -0,0 +1,42 @@
+#/** @file
+#
+# Component description file for PL011SerialPortLib module
+#
+# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL011SerialPortLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ PL011SerialPortLib.c
+
+[LibraryClasses]
+ PL011UartLib
+ PcdLib
+ ArmPlatformLib
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 9922686304..2ab6ee1920 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -100,6 +100,7 @@
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
--
2.17.1


[PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase

Pankaj Bansal
 

Added PEI phase to LS1043ARDB.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/FVRules.fdf.inc | 60 ++++---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 13 --
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 19 ++-
.../AArch64/ArmPlatformHelper.S | 46 +++++
.../ArmPlatformLib/AArch64/NxpQoriqLsHelper.S | 31 ----
.../Library/ArmPlatformLib/ArmPlatformLib.c | 86 +++++-----
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 19 ++-
.../ArmPlatformLib/ArmPlatformLibMem.c | 27 ++-
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++
.../MemoryInitPeiLib.c | 160 +++++++++---------
.../MemoryInitPeiLib.h | 1 -
.../MemoryInitPeiLib.inf | 24 +--
.../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 50 ++++++
Silicon/NXP/NxpQoriqLs.dec | 21 +--
Silicon/NXP/NxpQoriqLs.dsc.inc | 67 +++++---
16 files changed, 481 insertions(+), 264 deletions(-)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c (82%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h (94%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (80%)
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf

diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
index c9fba65dae..598262e045 100644
--- a/Platform/NXP/FVRules.fdf.inc
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -1,8 +1,8 @@
-# FvRules.fdf.inc
#
-# Rules for creating FD.
-#
-# Copyright 2017-2019 NXP
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,40 +16,49 @@
#
################################################################################

+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
}

[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}

[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
+ FILE PEIM = $(NAMED_GUID) FIXED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}

-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
- }
-
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}

-
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -62,6 +71,8 @@
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
}

[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -73,7 +84,7 @@

[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}

@@ -91,3 +102,10 @@
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ }
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 4bc7f6ef97..c9f828668f 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -32,19 +32,6 @@

[PcdsFixedAtBuild.common]

- #
- # LS1043a board Specific PCDs
- # XX (DRAM - Region 1 2GB)
- # (NOR - IFC Region 1 512MB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
-
- #
- # Board Specific Pcds
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
#
# RTC Pcds
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 8d66f36d74..22391899b7 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -3,7 +3,7 @@
# FLASH layout file for LS1043a board.
#
# Copyright (c) 2016, Freescale Ltd. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,10 +24,10 @@

[FD.LS1043ARDB_EFI]
BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
-Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x1
-NumBlocks = 0xED000
+NumBlocks = 0x100000

################################################################################
#
@@ -44,10 +44,11 @@ NumBlocks = 0xED000
# RegionType <FV, DATA, or FILE>
#
################################################################################
-0x00000000|0x000ED000
+0x00000000|0x00100000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT

+!include VarStore.fdf.inc
!include Platform/NXP/FVRules.fdf.inc
################################################################################
#
@@ -158,7 +159,15 @@ READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE

- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000000..d1b9f1debb
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,46 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
deleted file mode 100644
index dfbf73675a..0000000000
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
+++ /dev/null
@@ -1,31 +0,0 @@
-# @file
-#
-# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017, 2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-#include <AsmMacroIoLibV8.h>
-#include <AutoGen.h>
-
-.text
-.align 2
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-ASM_FUNC(ArmPlatformIsPrimaryCore)
- tst x0, #3
- cset x0, eq
- ret
-
-ASM_FUNC(ArmPlatformPeiBootAction)
-EL1_OR_EL2(x0)
-1:
-2:
- ret
-
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
- ldrh w0, [x0]
- ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 821d413a3e..f1d67d6c7d 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -1,8 +1,4 @@
-/** ArmPlatformLib.c
-*
-* Contains board initialization functions.
-*
-* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
@@ -19,19 +15,18 @@
#include <Library/SocLib.h>
#include <Ppi/NxpPlatformGetClock.h>

-/**
- Return the current Boot Mode
-
- This function returns the boot reason on the platform
+ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0, 0,

-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};

/**
Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
@@ -77,11 +72,29 @@ NxpPlatformGetClock(
}

/**
- Placeholder for Platform Initialization
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
**/
-EFI_STATUS
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
ArmPlatformInitialize (
- IN UINTN MpId
+ IN UINTN MpId
)
{
SocInit ();
@@ -89,29 +102,19 @@ ArmPlatformInitialize (
return EFI_SUCCESS;
}

-ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
- {
- // Cluster 0, Core 0
- 0x0, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)0,
- (EFI_PHYSICAL_ADDRESS)0,
- (EFI_PHYSICAL_ADDRESS)0,
- (UINT64)0xFFFFFFFF
- },
-};
-
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
- *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
- *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
-
- return EFI_SUCCESS;
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = mArmPlatformMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
}

ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
@@ -125,6 +128,7 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
}
};

+
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
@@ -135,11 +139,3 @@ ArmPlatformGetPlatformPpiList (
*PpiList = gPlatformPpiTable;
}

-
-UINTN
-ArmPlatformGetCorePosition (
- IN UINTN MpId
- )
-{
- return 1;
-}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 8b79fd7490..beb94fba64 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -1,24 +1,24 @@
-# @file
-#
+#/* @file
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
+#*/

[Defines]
INF_VERSION = 0x0001001A
- BASE_NAME = PlatformLib
+ BASE_NAME = ArmPlatformLib
FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib

[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
@@ -30,13 +30,14 @@
DebugLib

[Sources.common]
- AArch64/NxpQoriqLsHelper.S | GCC
+ AArch64/ArmPlatformHelper.S | GCC
ArmPlatformLibMem.c
ArmPlatformLib.c

+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
[Ppis]
gArmMpCoreInfoPpiGuid

-[FixedPcd]
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index 3a72c8bdd8..822afb2188 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -1,8 +1,4 @@
-/** NxpQoriqLsMem.c
-*
-* Board memory specific Library.
-*
-* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
@@ -14,10 +10,11 @@

#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Soc.h>

+// Number of Virtual Memory Map Descriptors
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25

/**
@@ -25,28 +22,28 @@

This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.

- @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
- Virtual Memory mapping. This array must be ended by a zero-filled
- entry
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry

**/
-
VOID
ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
- UINTN Index;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT32 Index;

Index = 0;

ASSERT (VirtualMemoryMap != NULL);

- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
- EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);

if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
return;
}

diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000000..c6cb3339d9
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1043ARDBNV_EFI]
+BaseAddress = 0x60500000
+Size = 0x000C0000
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
similarity index 82%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index eb1983bdbc..3d04e05283 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -1,7 +1,6 @@
/** @file
*
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*
* Copyright 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,42 +9,18 @@

#include <PiPei.h>

+#include <Library/ArmSmcLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmPlatformLib.h>
-#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
-#include <Library/ArmSmcLib.h>

#include "MemoryInitPeiLib.h"

-
-VOID
-BuildMemoryTypeInformationHob (
- VOID
- );
-
-VOID
-InitMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
- )
-{
-
- VOID *TranslationTableBase;
- UINTN TranslationTableSize;
- RETURN_STATUS Status;
-
- //Note: Because we called PeiServicesInstallPeiMemory() before
- //to call InitMmu() the MMU Page Table resides in DRAM
- //(even at the top of DRAM as it is the first permanent memory allocation)
- Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
- }
-}
-
STATIC
UINTN
CalculateReservedMemBase (
@@ -62,7 +37,7 @@ CalculateReservedMemBase (
UINTN ReservedBaseAddress;
INTN Index2;

- ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
+ ReservedMemAlignment = PcdGet64 (PcdReservedMemAlignment);
//
// Compute alignment bit mask
//
@@ -125,56 +100,26 @@ CalculateReservedMemBase (
}
}

-/*++
-
-Routine Description:
-
-
-
-Arguments:
-
- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
-
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
---*/
-EFI_STATUS
+RETURN_STATUS
EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+MemoryInitPeiLibConstructor (
+ VOID
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
- ARM_SMC_ARGS ArmSmcArgs;
- INT32 Index;
- UINTN DramSize;
- UINTN BaseAddress;
- UINTN Size;
- UINTN Top;
+ ARM_SMC_ARGS ArmSmcArgs;
+ INT32 Index;
+ UINTN DramSize;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
// Extra region gets created if we want to reserve a memory region and that creates a memory hole
// because of alignement requirements
- DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- UINTN FdBase;
- UINTN FdTop;
- BOOLEAN FoundSystemMem;
-
- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- //
- // Ensure MemoryTable[0].Length which is size of DRAM has been set
- // by ArmPlatformGetVirtualMemoryMap ()
- //
- ASSERT (MemoryTable[0].Length != 0);
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;

- //
- // Now, the permanent memory has been installed, we can call AllocatePages()
- //
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
@@ -214,16 +159,17 @@ MemoryPeim (
ASSERT (!DramSize);

// Get the reserved memory size from non volatile storage
- Size = FixedPcdGet64 (PcdReservedMemSize);
+ Size = PcdGet64 (PcdReservedMemSize);
if (Size) {
BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
if (BaseAddress) {
DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
+ PcdSet64S (PcdReservedMemBase, BaseAddress);
}
}

- FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
- FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);

// Declare memory regios to system
for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
@@ -266,8 +212,8 @@ MemoryPeim (
);
};
// Mark the memory covering the Firmware Device as boot services data
- BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
- FixedPcdGet32 (PcdFdSize),
+ BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize),
EfiBootServicesData);
}else {
BuildResourceDescriptorHob (
@@ -287,16 +233,72 @@ MemoryPeim (
Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;

if (FdBase >= BaseAddress && FdTop <= Top) {
- Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ Size -= (UINTN)PcdGet32 (PcdFdSize);
}

if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
FoundSystemMem = TRUE;
+ PcdSet64S (PcdSystemMemoryBase, BaseAddress);
+ PcdSet64S (PcdSystemMemorySize, Size);
}
}

ASSERT (FoundSystemMem);

+ return EFI_SUCCESS;
+}
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+STATIC
+VOID
+InitMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ )
+{
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);

diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
similarity index 94%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
index e563b2ba8d..c3c42ed8a3 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
@@ -21,4 +21,3 @@ typedef struct {
} DRAM_REGION_INFO;

#endif
-
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
similarity index 80%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index 9adddcaf8c..4d932444a3 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -8,32 +8,32 @@
#**/

[Defines]
- INF_VERSION = 0x0001001A
+ INF_VERSION = 0x00010005
BASE_NAME = ArmMemoryInitPeiLib
FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+ LIBRARY_CLASS = MemoryInitPeiLib|PEIM
+ CONSTRUCTOR = MemoryInitPeiLibConstructor

[Sources]
MemoryInitPeiLib.c

-
[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
- ArmMmuLib
- ArmPlatformLib
DebugLib
HobLib
- PcdLib
+ ArmMmuLib
+ ArmPlatformLib
ArmSmcLib
+ PcdLib

[Guids]
gEfiMemoryTypeInformationGuid
@@ -44,13 +44,15 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
+
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment

[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase

[Depex]
TRUE
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
new file mode 100644
index 0000000000..f64e564469
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
@@ -0,0 +1,30 @@
+/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#define XPRINT(x) PRINT(x)
+#define PRINT(x) #x
+
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+ VOID
+ )
+{
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
+ DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
+ DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
new file mode 100644
index 0000000000..b0481dece0
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformPeiLib
+ FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformPeiLib
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
+ GCC:*_*_*_CC_FLAGS = -DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
+
+[Sources]
+ PlatformPeiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ PcdLib
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFvSize
+
+[depex]
+ TRUE
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index c327e738cc..0a90334c02 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -27,21 +27,12 @@
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

-[PcdsFixedAtBuild.common]
- #
- # Platform PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
-
- #
- # Pcds to support Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
-
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
+[PcdsDynamic,PcdsPatchableInModule]
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0|UINT64|0x00000001
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000002
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000003

[PcdsFeatureFlag]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
- gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000004
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000005

diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 94d3e53a04..9922686304 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,29 +93,35 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf

I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf

[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf

- # 1/123 faster than Stm or Vstm version
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf

- # Uncomment to turn on GDB stub in SEC.
- #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf

[LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -124,14 +130,16 @@
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf

[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf

@@ -139,7 +147,6 @@
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf

[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -204,6 +211,10 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480

+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0
+
[PcdsDynamicHii.common.DEFAULT]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10

@@ -214,7 +225,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
@@ -224,6 +234,12 @@
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320

+ ## Base of DRAM
+ ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
+ ## for temporary ram
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
@@ -281,13 +297,26 @@
################################################################################
[Components.common]
#
- # SEC
+ # PEI Phase modules
#
- ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+
+ MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }

#
# DXE
--
2.17.1


[PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib

Pankaj Bansal
 

Replace SocLib with new SocLib in which code structure has been
changed.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
.../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
.../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
.../LS1043A/Library/SocLib/SocLib.inf | 8 ++
.../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
Silicon/NXP/Include/Library/ChassisLib.h | 2 -
Silicon/NXP/Include/Library/SocLib.h | 1 -
Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
.../BaseSerialPortLib16550.c | 11 +-
.../BaseSerialPortLib16550.inf | 3 +-
Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
23 files changed, 142 insertions(+), 521 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h

diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 126a1174fa..95f60b00f0 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -25,7 +25,8 @@
MdeModulePkg/MdeModulePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec

[LibraryClasses]
BaseLib
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index bc6fa4f19d..4bc7f6ef97 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -23,7 +23,8 @@
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf

!include Silicon/NXP/NxpQoriqLs.dsc.inc
-!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 718c71bf02..821d413a3e 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -14,7 +14,10 @@
#include <Library/ArmPlatformLib.h>
#include <Ppi/ArmMpCoreInfo.h>

-extern VOID SocInit (VOID);
+#include <Library/DebugLib.h>
+#include <Library/I2cLib.h>
+#include <Library/SocLib.h>
+#include <Ppi/NxpPlatformGetClock.h>

/**
Return the current Boot Mode
@@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}

+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
/**
Placeholder for Platform Initialization
**/
@@ -38,9 +84,9 @@ ArmPlatformInitialize (
IN UINTN MpId
)
{
- SocInit ();
+ SocInit ();

- return EFI_SUCCESS;
+ return EFI_SUCCESS;
}

ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
@@ -69,6 +115,7 @@ PrePeiCoreGetMpCoreInfo (
}

ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };

EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 6396d2982b..8b79fd7490 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -20,11 +20,14 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec

[LibraryClasses]
ArmLib
SocLib
+ I2cLib
+ DebugLib

[Sources.common]
AArch64/NxpQoriqLsHelper.S | GCC
@@ -36,3 +39,4 @@

[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 48ba2e7bfb..8f26faf297 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -20,6 +20,18 @@
#define TP_ITYPE_VERSION_A53 0x2
#define TP_ITYPE_VERSION_A72 0x4

+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+
/**
The Device Configuration Unit provides general purpose configuration and status for the
device. These registers only support 32-bit accesses.
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
index 4511203443..8440e5f0f3 100644
--- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
@@ -8,6 +8,7 @@

[LibraryClasses.common]
SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf

################################################################################
#
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
index 2a08ad87db..24241e9b02 100644
--- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
@@ -4,8 +4,10 @@

SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include <Soc.h>
#include <Library/ChassisLib.h>
#include <Library/SocLib.h>
+#include <Library/SerialPortLib.h>

/**
Return the input clock frequency to an IP Module.
@@ -66,8 +68,34 @@ SocInit (
VOID
)
{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
ChassisInit ();

+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+
return;
}

diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
index c9a4fbc01f..fb39424bc5 100644
--- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
@@ -29,4 +29,12 @@

[LibraryClasses]
ChassisLib
+ PcdLib
+ SerialPortLib

+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index fa6a36e96f..e7573a0e06 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -150,6 +150,29 @@ SocGetMpCoreInfo (
return CoreCount;
}

+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+STATIC
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
/**
Function to initialize Chassis Specific functions
**/
@@ -183,4 +206,6 @@ ChassisInit (
&DataBits,
&StopBits
);
+
+ SmmuInit();
}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 8e3a82efca..e79b106c8d 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -50,7 +50,7 @@ SetBusFrequency (

I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);

- I2cClock = GetBusFrequency ();
+ I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);

I2cInitialize (I2cBase, I2cClock, *BusClockHertz);

diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f3133..f446f0d4f9 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -13,6 +13,7 @@
#include <Library/UefiLib.h>
#include <Uefi.h>

+#include <Ppi/NxpPlatformGetClock.h>
#include <Protocol/I2cMaster.h>
#include <Protocol/NonDiscoverableDevice.h>

@@ -37,11 +38,7 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;

EFI_STATUS
NxpI2cInit (
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
deleted file mode 100644
index 6812beafe4..0000000000
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/** Soc.h
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_SOC_H_
-#define NXP_SOC_H_
-
-#define CLK_FREQ 100000000
-
-#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
-
-/* SMMU Defintions */
-#define SMMU_BASE_ADDR 0x09000000
-#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
-#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
-#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
-#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
-#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
-
-#define SCR0_USFCFG_MASK 0x00000400
-#define SCR0_CLIENTPD_MASK 0x00000001
-#define SACR_PAGESIZE_MASK 0x00010000
-#define IDR1_PAGESIZE_MASK 0x80000000
-
-typedef struct {
- UINTN FreqSystemBus;
-} SYS_INFO;
-
-/* Device Configuration and Pin Control */
-typedef struct {
- UINT8 Res0[0x100-0x00];
- UINT32 RcwSr[16]; /* Reset control word status */
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-} CCSR_GUR;
-
-VOID
-GetSysInfo (
- OUT SYS_INFO *
- );
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- );
-
-#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index b51b024374..d07c59b82d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -9,8 +9,6 @@
#ifndef __CHASSIS_LIB_H__
#define __CHASSIS_LIB_H__

-#include <Chassis.h>
-
/**
Read Dcfg register
**/
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
index 3def396171..700e877bdf 100644
--- a/Silicon/NXP/Include/Library/SocLib.h
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -8,7 +8,6 @@
#ifndef __SOC_LIB_H__
#define __SOC_LIB_H__

-#include <Soc.h>
#include <Uefi.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
deleted file mode 100644
index c1e00394af..0000000000
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file
-
- Copyright 2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef __SOC_H__
-#define __SOC_H__
-
-/**
- Soc Memory Map
-**/
-#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
-#define LS1043A_DRAM0_SIZE SIZE_2GB
-#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
-#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
-
-#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
-#define LS1043A_CCSR_SIZE 0xF000000
-
-#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
-#define LS1043A_IFC0_SIZE SIZE_512MB
-#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
-#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
-
-#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
-#define LS1043A_QSPI_SIZE SIZE_512MB
-
-#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
-#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
-#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
-#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
-
-#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
-#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
-#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
-#define LS1043A_PCI_SIZE SIZE_32GB
-
-#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
-#define LS1043A_I2C_SIZE 0x10000
-#define LS1043A_I2C_NUM_CONTROLLERS 4
-
-#endif
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
deleted file mode 100644
index cd79949790..0000000000
--- a/Silicon/NXP/LS1043A/LS1043A.dec
+++ /dev/null
@@ -1,16 +0,0 @@
-# LS1043A.dec
-#
-# Copyright 2017-2019 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[Defines]
- DEC_SPECIFICATION = 0x0001001A
-
-[Guids.common]
- gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
-
-[Includes]
- Include
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
deleted file mode 100644
index 7ebbb1a495..0000000000
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-# LS1043A.dsc
-# LS1043A Soc package.
-#
-# Copyright 2017-2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
- SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-[PcdsDynamicDefault.common]
-
- #
- # ARM General Interrupt Controller
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
-
-[PcdsFixedAtBuild.common]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
-
- #
- # Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
-##
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index 6b2aa46ff6..2e35f09d8f 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -15,6 +15,9 @@
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;

//
// 16550 UART register offsets and bitfields
@@ -42,12 +45,6 @@
#define B_UART_MSR_RI BIT6
#define B_UART_MSR_DCD BIT7

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
/**
Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
@@ -577,7 +574,7 @@ SerialPortSetAttributes (
return RETURN_UNSUPPORTED;
}

- SerialClock = GetBusFrequency ();
+ SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
if (SerialClock == 0) {
return EFI_DEVICE_ERROR;
}
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
index 45ae9dc0af..7823bc5be5 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
@@ -19,11 +19,12 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec

[LibraryClasses]
PcdLib
IoLib
- SocLib
+ ArmPlatformLib

[Sources]
BaseSerialPortLib16550.c
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
deleted file mode 100644
index 1ef99e8de2..0000000000
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/** @file
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#ifdef CHASSIS2
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/ArmSmcLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "NxpChassis.h"
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- )
-{
- if (FixedPcdGetBool (PcdGurBigEndian)) {
- return SwapMmioRead32 (Address);
- } else {
- return MmioRead32 (Address);
- }
-}
-
-/*
- * Return system bus frequency
- */
-UINT64
-GetBusFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSystemBus;
-}
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- )
-{
- UINT32 Value;
-
- /* set pagesize as 64K and ssmu-500 in bypass mode */
- Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
- MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
-}
-
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
deleted file mode 100644
index a3dabc93d1..0000000000
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/** @Soc.c
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <NxpChassis.h>
-#include <Chassis2/NxpSoc.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-/**
- Calculate the frequency of various controllers and
- populate the passed structure with frequuencies.
-
- @param PtrSysInfo Input structure to populate with
- frequencies.
-**/
-VOID
-GetSysInfo (
- OUT SYS_INFO *PtrSysInfo
- )
-{
- CCSR_GUR *GurBase;
- UINTN SysClk;
-
- GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
- SysClk = CLK_FREQ;
-
- SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
-
- PtrSysInfo->FreqSystemBus = SysClk;
-
- //
- // selects the platform clock:SYSCLK ratio and calculate
- // system frequency
- //
- PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-}
-
-/**
- Function to initialize SoC specific constructs
- CPU Info
- SoC Personality
- Board Personality
- RCW prints
- **/
-VOID
-SocInit (
- VOID
- )
-{
- UINT64 BaudRate;
- UINT32 ReceiveFifoDepth;
- EFI_PARITY_TYPE Parity;
- UINT8 DataBits;
- EFI_STOP_BITS_TYPE StopBits;
- UINT32 Timeout;
-
- BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
- ReceiveFifoDepth = 0; // Use default FIFO depth
- Timeout = 0;
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
- StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
-
- SmmuInit ();
-
- //
- // Early init serial Port to get board information.
- //
- SerialPortSetAttributes (
- &BaudRate,
- &ReceiveFifoDepth,
- &Timeout,
- &Parity,
- &DataBits,
- &StopBits
- );
- DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
- (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
-
- return;
-}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
deleted file mode 100644
index d8707927b7..0000000000
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ /dev/null
@@ -1,44 +0,0 @@
-# @file
-#
-# Copyright 2017-2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = SocLib
- FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SocLib
-
-[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
-
-[LibraryClasses]
- ArmSmcLib
- BaseLib
- DebugLib
- IoAccessLib
- SerialPortLib
-
-[Sources.common]
- Chassis.c
- Chassis2/Soc.c
-
-[BuildOptions]
- GCC:*_*_*_CC_FLAGS = -DCHASSIS2
-
-[FixedPcd]
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
deleted file mode 100644
index 99f6439d8f..0000000000
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/** @file
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_CHASSIS_H_
-#define NXP_CHASSIS_H_
-
-#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
-
-#define TY_ITYP_VERSION_A7 0x1
-#define TY_ITYP_VERSION_A53 0x2
-#define TY_ITYP_VERSION_A57 0x3
-#define TY_ITYP_VERSION_A72 0x4
-
-#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879200
-#define SVR_LS1046A 0x870700
-#define SVR_LS2088A 0x870901
-
-#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
-#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-#define MHZ 1000000
-
-typedef struct {
- CHAR8 *Name;
- UINT32 SocVer;
- UINT32 NumCores;
-} CPU_TYPE;
-
-typedef struct {
- UINTN CpuClk; /* CPU clock in Hz! */
- UINTN BusClk;
- UINTN MemClk;
- UINTN PciClk;
- UINTN SdhcClk;
-} SOC_CLOCK_INFO;
-
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- );
-
-/*
- * Initialize Clock structure
- */
-VOID
-ClockInit (
- VOID
- );
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- );
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- );
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- );
-
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- );
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- );
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- );
-
-/*
- * Return the type of initiator for core/hardware accelerator for given core index.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- );
-
-/*
- * Return the cluster of initiator for core/hardware accelerator for given core index.
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- );
-
-#endif /* NXP_CHASSIS_H_ */
--
2.17.1


[PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib

Pankaj Bansal
 

RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to commom MemoryInit Pei Lib.

Also added provision to reserve a portion of RAM.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Include/DramInfo.h | 38 ---
.../Library/MemoryInitPei/MemoryInitPeiLib.c | 235 +++++++++++++++---
.../Library/MemoryInitPei/MemoryInitPeiLib.h | 24 ++
.../MemoryInitPei/MemoryInitPeiLib.inf | 8 +
Silicon/NXP/Library/SocLib/Chassis.c | 67 -----
Silicon/NXP/NxpQoriqLs.dec | 7 +-
6 files changed, 239 insertions(+), 140 deletions(-)
delete mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h

diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1..0000000000
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-* Header defining the structure for Dram Information
-*
-* Copyright 2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SMC_DRAM_BANK_INFO (0xC200FF12)
-
-typedef struct {
- UINTN BaseAddress;
- UINTN Size;
-} DRAM_REGION_INFO;
-
-typedef struct {
- UINT32 NumOfDrams;
- UINT32 Reserved;
- DRAM_REGION_INFO DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- );
-
-VOID
-UpdateDpaaDram (
- IN OUT DRAM_INFO *DramInfo
- );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
index 3ea7736786..eb1983bdbc 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -17,8 +17,10 @@
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
+#include <Library/ArmSmcLib.h>
+
+#include "MemoryInitPeiLib.h"

-#include <DramInfo.h>

VOID
BuildMemoryTypeInformationHob (
@@ -44,6 +46,85 @@ InitMmu (
}
}

+STATIC
+UINTN
+CalculateReservedMemBase (
+ IN DRAM_REGION_INFO *DramRegions,
+ IN UINT32 NumRegions,
+ IN UINTN ReservedMemSize
+)
+{
+ UINTN ReservedMemAlignment;
+ INTN Index;
+ EFI_PHYSICAL_ADDRESS AlignmentMask;
+ UINTN RegionBaseAddress;
+ UINTN RegionSize;
+ UINTN ReservedBaseAddress;
+ INTN Index2;
+
+ ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
+ //
+ // Compute alignment bit mask
+ //
+ if (ReservedMemAlignment) {
+ AlignmentMask = LShiftU64 (1, LowBitSet64(ReservedMemAlignment)) - 1;
+ } else {
+ AlignmentMask = 0;
+ }
+ Index = NumRegions;
+ while (Index--) {
+ RegionBaseAddress = DramRegions[Index].BaseAddress;
+ RegionSize = DramRegions[Index].Size;
+
+ if (ReservedMemSize > RegionSize) {
+ continue;
+ }
+
+ ReservedBaseAddress = (RegionBaseAddress + RegionSize - ReservedMemSize) & (~AlignmentMask);
+ if (ReservedBaseAddress < RegionBaseAddress) {
+ continue;
+ }
+
+ // found the region from which reserved mem is to be carved out
+ // Need to modify the region size and create/delete region if need be
+ RegionSize -= ReservedMemSize;
+ if (!RegionSize) {
+ for (Index2 = Index; Index2 < NumRegions; Index2++) {
+ CopyMem (&DramRegions[Index2], &DramRegions[Index2 + 1], sizeof (DRAM_REGION_INFO));
+ }
+ break;
+ }
+
+ if (ReservedBaseAddress - RegionBaseAddress) {
+ DramRegions[Index].Size = ReservedBaseAddress - RegionBaseAddress;
+ RegionSize -= DramRegions[Index].Size;
+ } else {
+ DramRegions[Index].BaseAddress = ReservedBaseAddress + ReservedMemSize;
+ DramRegions[Index].Size = RegionSize;
+ RegionSize = 0;
+ }
+
+ if (!RegionSize) {
+ break;
+ }
+
+ for (Index2 = NumRegions; Index2 > (Index + 1); Index2--) {
+ CopyMem (&DramRegions[Index2], &DramRegions[Index2 - 1], sizeof (DRAM_REGION_INFO));
+ }
+ DramRegions[Index2].BaseAddress = ReservedBaseAddress + ReservedMemSize;
+ DramRegions[Index2].Size = RegionSize;
+ RegionSize = 0;
+
+ break;
+ }
+
+ if (Index == -1) {
+ return 0;
+ } else {
+ return ReservedBaseAddress;
+ }
+}
+
/*++

Routine Description:
@@ -68,10 +149,19 @@ MemoryPeim (
)
{
ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ ARM_SMC_ARGS ArmSmcArgs;
+ INT32 Index;
+ UINTN DramSize;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
+ // Extra region gets created if we want to reserve a memory region and that creates a memory hole
+ // because of alignement requirements
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- EFI_PEI_HOB_POINTERS NextHob;
- BOOLEAN Found;
- DRAM_INFO DramInfo;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;

// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@@ -86,48 +176,127 @@ MemoryPeim (
// Now, the permanent memory has been installed, we can call AllocatePages()
//
ResourceAttributes = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED
);

- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return EFI_UNSUPPORTED;
- }
+ FoundSystemMem = FALSE;
+ ZeroMem (DramRegions, sizeof (DramRegions));
+
+ Index = -1;
+ do {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = Index++;

- while (DramInfo.NumOfDrams--) {
- //
- // Check if the resource for the main system memory has been declared
- //
- Found = FALSE;
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
- if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
- (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
- (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
- {
- Found = TRUE;
- break;
+ ArmCallSmc (&ArmSmcArgs);
+ ASSERT (!(ArmSmcArgs.Arg0 && !Index));
+ if (!Index) {
+ DramSize = ArmSmcArgs.Arg1;
+ } else {
+ if (!ArmSmcArgs.Arg0) {
+ BaseAddress = ArmSmcArgs.Arg1;
+ Size = ArmSmcArgs.Arg2;
+ ASSERT (BaseAddress && Size);
+
+ DramRegions[Index - 1].BaseAddress = BaseAddress;
+ DramRegions[Index - 1].Size = Size;
+ DramSize -= Size;
+
+ DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", Index, BaseAddress, Size));
}
- NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+ } while (DramSize && Index < MAX_DRAM_REGIONS);
+
+ ASSERT (!DramSize);
+
+ // Get the reserved memory size from non volatile storage
+ Size = FixedPcdGet64 (PcdReservedMemSize);
+ if (Size) {
+ BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
+ if (BaseAddress) {
+ DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
+ }
+ }
+
+ FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+
+ // Declare memory regios to system
+ for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
+ if (!DramRegions[Index].Size) {
+ continue;
}

- if (!Found) {
- // Reserved the memory space occupied by the firmware volume
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ // EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
+ // core to overwrite this area we must create a memory allocation HOB for the region,
+ // but this only works if we split off the underlying resource descriptor as well.
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ // Update Size
+ Size = FdBase - BaseAddress;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ BaseAddress,
+ Size
+ );
+ }
+ // create the System Memory HOB for the firmware
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
- DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ FdBase,
+ PcdGet32 (PcdFdSize)
+ );
+ // Create the System Memory HOB for the remaining region (top of the FD)s
+ Size = Top - FdTop;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FdTop,
+ Size
+ );
+ };
+ // Mark the memory covering the Firmware Device as boot services data
+ BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
+ FixedPcdGet32 (PcdFdSize),
+ EfiBootServicesData);
+ }else {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramRegions[Index].BaseAddress,
+ DramRegions[Index].Size
);
}
+
+ if (FoundSystemMem) {
+ continue;
+ }
+
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Size = DramRegions[Index].Size;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ }
+
+ if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
+ FoundSystemMem = TRUE;
+ }
}

+ ASSERT (FoundSystemMem);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);

diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index 0000000000..e563b2ba8d
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,24 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef _MEMORY_INIT_PEI_LIB_H_
+#define _MEMORY_INIT_PEI_LIB_H_
+
+#include <Uefi.h>
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in a Platform
+#define MAX_DRAM_REGIONS 3
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+#endif
+
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415d..9adddcaf8c 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -33,6 +33,7 @@
DebugLib
HobLib
PcdLib
+ ArmSmcLib

[Guids]
gEfiMemoryTypeInformationGuid
@@ -40,6 +41,13 @@
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob

+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
+
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 847331a631..1ef99e8de2 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -22,7 +22,6 @@
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>

-#include <DramInfo.h>
#include "NxpChassis.h"

UINT32
@@ -75,69 +74,3 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}

-UINTN
-GetDramSize (
- IN VOID
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
-
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = -1;
-
- ArmCallSmc (&ArmSmcArgs);
-
- if (ArmSmcArgs.Arg0) {
- return 0;
- } else {
- return ArmSmcArgs.Arg1;
- }
-}
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
- UINT32 I;
- UINTN DramSize;
-
- DramSize = GetDramSize ();
- DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
-
- // Ensure DramSize has been set
- ASSERT (DramSize != 0);
-
- I = 0;
-
- do {
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = I;
-
- ArmCallSmc (&ArmSmcArgs);
- if (ArmSmcArgs.Arg0) {
- if (I > 0) {
- break;
- } else {
- ASSERT (ArmSmcArgs.Arg0 == 0);
- }
- }
-
- DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
- DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
-
- DramSize -= DramInfo->DramRegion[I].Size;
-
- DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
- I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
-
- I++;
- } while (DramSize);
-
- DramInfo->NumOfDrams = I;
-
- DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4f14cc9848..c327e738cc 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -38,7 +38,10 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311

+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
+
[PcdsFeatureFlag]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
- gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318

--
2.17.1


[PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib

Pankaj Bansal
 

Add SocLib for LS1043A as per new directory structure

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Chassis2/LS1043A/Include/Soc.h | 56 +++++++++++++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dec | 23 ++++++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 30 +++++++
.../Chassis2/LS1043A/Library/SocLib/SocLib.c | 73 +++++++++++++++++
.../LS1043A/Library/SocLib/SocLib.inf | 32 ++++++++
Silicon/NXP/Include/Library/SocLib.h | 81 +++++++++++++++++++
Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 47 +++++++++++
Silicon/NXP/NxpQoriqLs.dec | 3 +
8 files changed, 345 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/Include/Library/SocLib.h
create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h

diff --git a/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
new file mode 100644
index 0000000000..3b11b2b126
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
@@ -0,0 +1,56 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
+
+#endif
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
new file mode 100644
index 0000000000..4511203443
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
@@ -0,0 +1,30 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+[PcdsFixedAtBuild.common]
+## ns16550 Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0500
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+
+[PcdsDynamicDefault.common]
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x1401000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1402000
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
new file mode 100644
index 0000000000..2a08ad87db
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
@@ -0,0 +1,73 @@
+/** @file
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+#include <Library/ChassisLib.h>
+#include <Library/SocLib.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1043A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
new file mode 100644
index 0000000000..c9a4fbc01f
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
@@ -0,0 +1,32 @@
+#@file
+#
+# Component description file for SocLib module
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = SocLib
+ FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Sources.common]
+ SocLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ ChassisLib
+
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
new file mode 100644
index 0000000000..3def396171
--- /dev/null
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -0,0 +1,81 @@
+/** @file
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SOC_LIB_H__
+#define __SOC_LIB_H__
+
+#include <Soc.h>
+#include <Uefi.h>
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned value number of
+ entries in ArmCoreTable are valid entries.
+**/
+UINTN
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN ArmCoreTableSize
+ );
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ );
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ );
+
+#endif // __SOC_LIB_H__
diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
new file mode 100644
index 0000000000..2c8c97987d
--- /dev/null
+++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
@@ -0,0 +1,47 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __NXP_PLATFORM_PPI_H__
+#define __NXP_PLATFORM_PPI_H__
+
+#include <Uefi.h>
+
+#define NXP_PLATFORM_GET_CLOCK_PPI_GUID \
+ { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
+
+typedef enum _NXP_IP_CLOCK {
+ NXP_SYSTEM_CLOCK,
+ NXP_UART_CLOCK,
+ NXP_I2C_CLOCK
+} NXP_IP_CLOCK;
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+typedef
+UINT64
+(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
+ IN UINT32 ClockType,
+ ...
+ );
+
+typedef struct {
+ NXP_PLATFORM_GET_CLOCK PlatformGetClock;
+} NXP_PLATFORM_GET_CLOCK_PPI;
+
+extern EFI_GUID gNxpPlatformGetClockPpiGuid;
+
+#endif
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index d8989657e6..4f14cc9848 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
Include

[LibraryClasses]
+ ## @libraryclass Provides Soc specific functions to other modules
+ SocLib|Include/Library/SocLib.h
+
## @libraryclass Provides Chassis specific functions to other modules
ChassisLib|Include/Library/ChassisLib.h

--
2.17.1


[PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2

Pankaj Bansal
 

Add ChassisLib for Chassis2.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Chassis2/Chassis2.dec | 23 +++
Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
Silicon/NXP/Chassis2/Include/Chassis.h | 42 ++++
.../Chassis2/Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
.../Library/ChassisLib/ChassisLib.inf | 41 ++++
Silicon/NXP/Include/Library/ChassisLib.h | 41 ++++
Silicon/NXP/NxpQoriqLs.dec | 4 +
7 files changed, 347 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h

diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
new file mode 100644
index 0000000000..db8e5a92ea
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
new file mode 100644
index 0000000000..48ba2e7bfb
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
+#define TP_CLUSTER_ITYPE_IDX 0x3f
+#define TP_CLUSTER_EOC BIT31
+#define TP_ITYPE_AVAILABLE BIT0
+#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
+#define TP_ITYPE_ARM 0x0
+#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
+
+#define TP_ITYPE_VERSION_A53 0x2
+#define TP_ITYPE_VERSION_A72 0x4
+
+/**
+ The Device Configuration Unit provides general purpose configuration and status for the
+ device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[16]; // Reset Control Word Status Register
+ UINT8 Reserved140[0x200 - 0x140];
+ UINT32 ScratchRw[16]; /// Scratch Read / Write Register
+ UINT8 Reserved240[0x740-0x240];
+ UINT32 TpItyp[65]; /// Topology Initiator Type Register
+ struct {
+ UINT32 Lower;
+ UINT32 Upper;
+ }TpCluster[8];
+} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 0000000000..fa6a36e96f
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,186 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+/**
+ Get the type of core in cluster
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
+ @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
+ These cores are identified based on their codes like TP_ITYPE_VERSION_A72
+
+ @return EFI_NOT_FOUND No enabled ARM core found
+ @return EFI_SUCCESS An enabled ARM core found
+**/
+STATIC
+EFI_STATUS
+SocGetCoreType (
+ IN UINT8 TpItypeIdx,
+ OUT UINT8 *CoreType
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpItype;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
+ TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
+ if (TpItype & TP_ITYPE_AVAILABLE) {
+ if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
+ *CoreType = TP_ITYPE_VERSION (TpItype);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ } else {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned value number of
+ entries in ArmCoreTable are valid entries.
+**/
+UINTN
+__attribute__((weak))
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN CoreTableSize
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpClusterLower;
+ UINT8 TpClusterParser;
+ UINT8 ClusterIndex;
+ UINT8 CoreIndex;
+ UINTN CoreCount;
+ UINT8 CoreType;
+ EFI_STATUS Status;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
+ ClusterIndex = 0;
+ CoreCount = 0;
+ while (TRUE) {
+ TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
+ for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
+ TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
+ Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
+ if (Status != EFI_NOT_FOUND) {
+ ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
+ ArmCoreTable[CoreCount].CoreId = CoreIndex;
+ ArmCoreTable[CoreCount].MailboxSetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxGetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearValue = ~0;
+
+ NxpCoreTable[CoreCount] = CoreType;
+ CoreCount++;
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ }
+ }
+ if (TpClusterLower & TP_CLUSTER_EOC) {
+ break;
+ }
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ ClusterIndex++;
+ }
+
+ return CoreCount;
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+}
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 0000000000..4964bb4e82
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Chassis2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+
+[LibraryClasses]
+ IoLib
+ IoAccessLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
+
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
new file mode 100644
index 0000000000..b51b024374
--- /dev/null
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -0,0 +1,41 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __CHASSIS_LIB_H__
+#define __CHASSIS_LIB_H__
+
+#include <Chassis.h>
+
+/**
+ Read Dcfg register
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Dcfg register
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b478560450..d8989657e6 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
Include

[LibraryClasses]
+ ## @libraryclass Provides Chassis specific functions to other modules
+ ChassisLib|Include/Library/ChassisLib.h
+
## @libraryclass Provides services to read/write to I2c devices
I2cLib|Include/Library/I2cLib.h

@@ -34,4 +37,5 @@

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316

--
2.17.1


[PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg

Pankaj Bansal
 

Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
.../AArch64}/NxpQoriqLsHelper.S | 2 +-
.../Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
.../{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
.../NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
5 files changed, 5 insertions(+), 5 deletions(-)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib/AArch64}/NxpQoriqLsHelper.S (88%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (93%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf (89%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (100%)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 7cffd09d7d..bc6fa4f19d 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -26,7 +26,7 @@
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
- ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf

[PcdsFixedAtBuild.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
similarity index 88%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
index 84ee8c9f97..dfbf73675a 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
similarity index 93%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index eac7d4aa4e..718c71bf02 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
similarity index 89%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 054dc4d003..6396d2982b 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -27,8 +27,8 @@
SocLib

[Sources.common]
- NxpQoriqLsHelper.S | GCC
- NxpQoriqLsMem.c
+ AArch64/NxpQoriqLsHelper.S | GCC
+ ArmPlatformLibMem.c
ArmPlatformLib.c

[Ppis]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
similarity index 100%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
--
2.17.1


[PATCH 09/19] Silicon/NXP: Move dsc file

Pankaj Bansal
 

As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (100%)

diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 74a1948fc6..7cffd09d7d 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -22,7 +22,7 @@
OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf

-!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc

[LibraryClasses.common]
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc.inc
rename to Silicon/NXP/NxpQoriqLs.dsc.inc
--
2.17.1


[PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs

Pankaj Bansal
 

There is no need to keep SOC specific PCDs defined for each SOC.
we can do away with these PCDs.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 15 +--
.../Drivers/PlatformDxe/PlatformDxe.inf | 8 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 -
.../Library/PlatformLib/ArmPlatformLib.inf | 21 +---
.../Library/PlatformLib/NxpQoriqLsMem.c | 103 +++++++++---------
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 6 -
Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
Silicon/NXP/LS1043A/Include/Soc.h | 44 ++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 32 ------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 4 -
Silicon/NXP/NxpQoriqLs.dec | 74 -------------
12 files changed, 108 insertions(+), 204 deletions(-)
create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h

diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
index f89dcdeff3..62c400eb1a 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -1,7 +1,7 @@
/** @file
LS1043 DXE platform driver.

- Copyright 2018-2019 NXP
+ Copyright 2018-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -14,6 +14,7 @@
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Soc.h>

#include <Protocol/NonDiscoverableDevice.h>

@@ -22,7 +23,7 @@ typedef struct {
UINT8 EndDesc;
} ADDRESS_SPACE_DESCRIPTOR;

-STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];

STATIC
EFI_STATUS
@@ -65,19 +66,19 @@ PopulateI2cInformation (
{
UINT32 Index;

- for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
mI2cDesc[Index].StartDesc.GenFlag = 0;
mI2cDesc[Index].StartDesc.SpecificFlag = 0;
mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
- mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
- (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
+ (Index * LS1043A_I2C_SIZE);
mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
- FixedPcdGet32 (PcdI2cSize) - 1;
+ LS1043A_I2C_SIZE - 1;
mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
- mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+ mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;

mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
}
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index d689cf4db5..126a1174fa 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -2,7 +2,7 @@
#
# Component description file for LS1043 DXE platform driver.
#
-# Copyright 2018-2019 NXP
+# Copyright 2018-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +25,7 @@
MdeModulePkg/MdeModulePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec

[LibraryClasses]
BaseLib
@@ -43,10 +44,5 @@
gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES

-[FixedPcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 802cccdce6..74a1948fc6 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -42,7 +42,6 @@
#
# Board Specific Pcds
#
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1

#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f7ae74afc6..054dc4d003 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017, 2019 NXP
+# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,6 +20,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec

[LibraryClasses]
ArmLib
@@ -35,21 +36,3 @@

[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index c6c256da07..3a72c8bdd8 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017, 2019 NXP
+* Copyright 2017, 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,7 +16,7 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
-#include <DramInfo.h>
+#include <Soc.h>

#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25

@@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
{
UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- DRAM_INFO DramInfo;

Index = 0;

@@ -51,25 +50,21 @@ ArmPlatformGetVirtualMemoryMap (
return;
}

- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

-
- for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
- // DRAM1 (Must be 1st entry)
- VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

// CCSR Space
- VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// IFC region 1
//
@@ -85,60 +80,60 @@ ArmPlatformGetVirtualMemoryMap (
// For write transactions from non-core masters (like system DMA), the address
// should be 16 byte aligned and the data size should be multiple of 16 bytes.
//
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// QMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// BMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// IFC region 2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe1
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// PCIe3
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

// QSPI region
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

// End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+ VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;

- ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);

*VirtualMemoryMap = VirtualMemoryTable;
}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 784139065f..fc4bb618fa 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -49,11 +49,5 @@
gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
gEfiI2cMasterProtocolGuid ## BY_START

-[Pcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 74330b6205..6812beafe4 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -12,6 +12,8 @@

#define CLK_FREQ 100000000

+#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
new file mode 100644
index 0000000000..c1e00394af
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#endif
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 754eff396a..7ebbb1a495 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -26,40 +26,8 @@
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500

- #
- # CCSR Address Space and other attached Memories
- #
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
-
#
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 9baeb17ecf..a3dabc93d1 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -34,7 +34,7 @@ GetSysInfo (
CCSR_GUR *GurBase;
UINTN SysClk;

- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
SysClk = CLK_FREQ;

SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index fe77717337..d8707927b7 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -40,9 +40,5 @@
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4a1cfb3e27..b478560450 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,89 +22,15 @@
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

[PcdsFixedAtBuild.common]
- #
- # Pcds for I2C Controller
- #
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
-
- #
- # Pcds for base address and size
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
- gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
- gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
- gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
- gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
- gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
-
- #
- # IFC PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
- gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
- gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
-
- #
- # NV Pcd
- #
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
-
#
# Platform PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
-
- #
- # Clock PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
- gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1

#
# Pcds to support Big Endian IPs
#
- gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
- gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
- gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314

[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
--
2.17.1


[PATCH 07/19] Silicon/NXP: remove not needed components

Pankaj Bansal
 

We are changing the directory structure of code.
After PEI phase impelmentation this info would be put back
into appropriate location.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +---------------------
Silicon/NXP/Library/SocLib/Chassis.c | 15 --
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ------
3 files changed, 2 insertions(+), 406 deletions(-)

diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index f05a813750..74330b6205 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -1,7 +1,7 @@
/** Soc.h
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -10,22 +10,7 @@
#ifndef NXP_SOC_H_
#define NXP_SOC_H_

-#define HWA_CGA_M1_CLK_SEL 0xe0000000
-#define HWA_CGA_M1_CLK_SHIFT 29
-
-#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
-#define NUM_CC_PLLS 2
#define CLK_FREQ 100000000
-#define MAX_CPUS 4
-#define NUM_FMAN 1
-#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
-
-/* RCW SERDES MACRO */
-#define RCWSR_INDEX 4
-#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
-#define RCWSR_SRDS1_PRTCL_SHIFT 16
-#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
-#define RCWSR_SRDS2_PRTCL_SHIFT 0

/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
@@ -41,312 +26,17 @@
#define IDR1_PAGESIZE_MASK 0x80000000

typedef struct {
- UINTN FreqProcessor[MAX_CPUS];
UINTN FreqSystemBus;
- UINTN FreqDdrBus;
- UINTN FreqLocalBus;
- UINTN FreqSdhc;
- UINTN FreqFman[NUM_FMAN];
- UINTN FreqQman;
} SYS_INFO;

/* Device Configuration and Pin Control */
typedef struct {
- UINT32 PorSr1; /* POR status 1 */
-#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
- UINT32 PorSr2; /* POR status 2 */
- UINT8 Res008[0x20-0x8];
- UINT32 GppOrCr1; /* General-purpose POR configuration */
- UINT32 GppOrCr2;
- UINT32 DcfgFuseSr; /* Fuse status register */
- UINT8 Res02c[0x70-0x2c];
- UINT32 DevDisr; /* Device disable control */
- UINT32 DevDisr2; /* Device disable control 2 */
- UINT32 DevDisr3; /* Device disable control 3 */
- UINT32 DevDisr4; /* Device disable control 4 */
- UINT32 DevDisr5; /* Device disable control 5 */
- UINT32 DevDisr6; /* Device disable control 6 */
- UINT32 DevDisr7; /* Device disable control 7 */
- UINT8 Res08c[0x94-0x8c];
- UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
- UINT32 CoreDisrL; /* lower portion for support of 64 cores */
- UINT8 Res09c[0xa0-0x9c];
- UINT32 Pvr; /* Processor version */
- UINT32 Svr; /* System version */
- UINT32 Mvr; /* Manufacturing version */
- UINT8 Res0ac[0xb0-0xac];
- UINT32 RstCr; /* Reset control */
- UINT32 RstRqPblSr; /* Reset request preboot loader status */
- UINT8 Res0b8[0xc0-0xb8];
- UINT32 RstRqMr1; /* Reset request mask */
- UINT8 Res0c4[0xc8-0xc4];
- UINT32 RstRqSr1; /* Reset request status */
- UINT8 Res0cc[0xd4-0xcc];
- UINT32 RstRqWdTmrL; /* Reset request WDT mask */
- UINT8 Res0d8[0xdc-0xd8];
- UINT32 RstRqWdtSrL; /* Reset request WDT status */
- UINT8 Res0e0[0xe4-0xe0];
- UINT32 BrrL; /* Boot release */
- UINT8 Res0e8[0x100-0xe8];
+ UINT8 Res0[0x100-0x00];
UINT32 RcwSr[16]; /* Reset control word status */
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
- UINT8 Res140[0x200-0x140];
- UINT32 ScratchRw[4]; /* Scratch Read/Write */
- UINT8 Res210[0x300-0x210];
- UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
- UINT8 Res310[0x400-0x310];
- UINT32 CrstSr[12];
- UINT8 Res430[0x500-0x430];
- /* PCI Express n Logical I/O Device Number register */
- UINT32 DcfgCcsrPex1LiodNr;
- UINT32 DcfgCcsrPex2LiodNr;
- UINT32 DcfgCcsrPex3LiodNr;
- UINT32 DcfgCcsrPex4LiodNr;
- /* RIO n Logical I/O Device Number register */
- UINT32 DcfgCcsrRio1LiodNr;
- UINT32 DcfgCcsrRio2LiodNr;
- UINT32 DcfgCcsrRio3LiodNr;
- UINT32 DcfgCcsrRio4LiodNr;
- /* USB Logical I/O Device Number register */
- UINT32 DcfgCcsrUsb1LiodNr;
- UINT32 DcfgCcsrUsb2LiodNr;
- UINT32 DcfgCcsrUsb3LiodNr;
- UINT32 DcfgCcsrUsb4LiodNr;
- /* SD/MMC Logical I/O Device Number register */
- UINT32 DcfgCcsrSdMmc1LiodNr;
- UINT32 DcfgCcsrSdMmc2LiodNr;
- UINT32 DcfgCcsrSdMmc3LiodNr;
- UINT32 DcfgCcsrSdMmc4LiodNr;
- /* RIO Message Unit Logical I/O Device Number register */
- UINT32 DcfgCcsrRiomaintLiodNr;
- UINT8 Res544[0x550-0x544];
- UINT32 SataLiodNr[4];
- UINT8 Res560[0x570-0x560];
- UINT32 DcfgCcsrMisc1LiodNr;
- UINT32 DcfgCcsrMisc2LiodNr;
- UINT32 DcfgCcsrMisc3LiodNr;
- UINT32 DcfgCcsrMisc4LiodNr;
- UINT32 DcfgCcsrDma1LiodNr;
- UINT32 DcfgCcsrDma2LiodNr;
- UINT32 DcfgCcsrDma3LiodNr;
- UINT32 DcfgCcsrDma4LiodNr;
- UINT32 DcfgCcsrSpare1LiodNr;
- UINT32 DcfgCcsrSpare2LiodNr;
- UINT32 DcfgCcsrSpare3LiodNr;
- UINT32 DcfgCcsrSpare4LiodNr;
- UINT8 Res5a0[0x600-0x5a0];
- UINT32 DcfgCcsrPblSr;
- UINT32 PamuBypENr;
- UINT32 DmaCr1;
- UINT8 Res60c[0x610-0x60c];
- UINT32 DcfgCcsrGenSr1;
- UINT32 DcfgCcsrGenSr2;
- UINT32 DcfgCcsrGenSr3;
- UINT32 DcfgCcsrGenSr4;
- UINT32 DcfgCcsrGenCr1;
- UINT32 DcfgCcsrGenCr2;
- UINT32 DcfgCcsrGenCr3;
- UINT32 DcfgCcsrGenCr4;
- UINT32 DcfgCcsrGenCr5;
- UINT32 DcfgCcsrGenCr6;
- UINT32 DcfgCcsrGenCr7;
- UINT8 Res63c[0x658-0x63c];
- UINT32 DcfgCcsrcGenSr1;
- UINT32 DcfgCcsrcGenSr0;
- UINT8 Res660[0x678-0x660];
- UINT32 DcfgCcsrcGenCr1;
- UINT32 DcfgCcsrcGenCr0;
- UINT8 Res680[0x700-0x680];
- UINT32 DcfgCcsrSrIoPstecr;
- UINT32 DcfgCcsrDcsrCr;
- UINT8 Res708[0x740-0x708]; /* add more registers when needed */
- UINT32 TpItyp[64]; /* Topology Initiator Type Register */
- struct {
- UINT32 Upper;
- UINT32 Lower;
- } TpCluster[16];
- UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
- UINT32 DcfgCcsrQmBmWarmRst;
- UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
- UINT32 DcfgCcsrReserved0;
- UINT32 DcfgCcsrReserved1;
} CCSR_GUR;

-/* Supplemental Configuration Unit */
-typedef struct {
- UINT8 Res000[0x070-0x000];
- UINT32 Usb1Prm1Cr;
- UINT32 Usb1Prm2Cr;
- UINT32 Usb1Prm3Cr;
- UINT32 Usb2Prm1Cr;
- UINT32 Usb2Prm2Cr;
- UINT32 Usb2Prm3Cr;
- UINT32 Usb3Prm1Cr;
- UINT32 Usb3Prm2Cr;
- UINT32 Usb3Prm3Cr;
- UINT8 Res094[0x100-0x094];
- UINT32 Usb2Icid;
- UINT32 Usb3Icid;
- UINT8 Res108[0x114-0x108];
- UINT32 DmaIcid;
- UINT32 SataIcid;
- UINT32 Usb1Icid;
- UINT32 QeIcid;
- UINT32 SdhcIcid;
- UINT32 EdmaIcid;
- UINT32 EtrIcid;
- UINT32 Core0SftRst;
- UINT32 Core1SftRst;
- UINT32 Core2SftRst;
- UINT32 Core3SftRst;
- UINT8 Res140[0x158-0x140];
- UINT32 AltCBar;
- UINT32 QspiCfg;
- UINT8 Res160[0x180-0x160];
- UINT32 DmaMcr;
- UINT8 Res184[0x188-0x184];
- UINT32 GicAlign;
- UINT32 DebugIcid;
- UINT8 Res190[0x1a4-0x190];
- UINT32 SnpCnfGcr;
-#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
-#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
-#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
-#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
-#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
-#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
-#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
-#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
-#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
-#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
- UINT8 Res1a8[0x1ac-0x1a8];
- UINT32 IntpCr;
- UINT8 Res1b0[0x204-0x1b0];
- UINT32 CoreSrEnCr;
- UINT8 Res208[0x220-0x208];
- UINT32 RvBar00;
- UINT32 RvBar01;
- UINT32 RvBar10;
- UINT32 RvBar11;
- UINT32 RvBar20;
- UINT32 RvBar21;
- UINT32 RvBar30;
- UINT32 RvBar31;
- UINT32 LpmCsr;
- UINT8 Res244[0x400-0x244];
- UINT32 QspIdQScr;
- UINT32 EcgTxcMcr;
- UINT32 SdhcIoVSelCr;
- UINT32 RcwPMuxCr0;
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
- Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
-#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
- Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
-#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
- UINT32 UsbDrvVBusSelCr;
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
- UINT32 UsbPwrFaultSelCr;
-#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
-#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
-#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
-#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
-#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
-#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
- UINT32 UsbRefclkSelcr1;
- UINT32 UsbRefclkSelcr2;
- UINT32 UsbRefclkSelcr3;
- UINT8 Res424[0x600-0x424];
- UINT32 ScratchRw[4];
- UINT8 Res610[0x680-0x610];
- UINT32 CoreBCr;
- UINT8 Res684[0x1000-0x684];
- UINT32 Pex1MsiIr;
- UINT32 Pex1MsiR;
- UINT8 Res1008[0x2000-0x1008];
- UINT32 Pex2;
- UINT32 Pex2MsiR;
- UINT8 Res2008[0x3000-0x2008];
- UINT32 Pex3MsiIr;
- UINT32 Pex3MsiR;
-} CCSR_SCFG;
-
-#define USB_TXVREFTUNE 0x9
-#define USB_SQRXTUNE 0xFC7FFFFF
-#define USB_PCSTXSWINGFULL 0x47
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x8000
-#define USB_PHY_RX_EQ_VAL_3 0x8003
-#define USB_PHY_RX_EQ_VAL_4 0x800b
-
-/*USB_PHY_SS memory map*/
-typedef struct {
- UINT16 IpIdcodeLo;
- UINT16 SupIdcodeHi;
- UINT8 Res4[0x0006-0x0004];
- UINT16 RtuneDebug;
- UINT16 RtuneStat;
- UINT16 SupSsPhase;
- UINT16 SsFreq;
- UINT8 ResE[0x0020-0x000e];
- UINT16 Ateovrd;
- UINT16 MpllOvrdInLo;
- UINT8 Res24[0x0026-0x0024];
- UINT16 SscOvrdIn;
- UINT8 Res28[0x002A-0x0028];
- UINT16 LevelOvrdIn;
- UINT8 Res2C[0x0044-0x002C];
- UINT16 ScopeCount;
- UINT8 Res46[0x0060-0x0046];
- UINT16 MpllLoopCtl;
- UINT8 Res62[0x006C-0x0062];
- UINT16 SscClkCntrl;
- UINT8 Res6E[0x2002-0x006E];
- UINT16 Lane0TxOvrdInHi;
- UINT16 Lane0TxOvrdDrvLo;
- UINT8 Res2006[0x200C-0x2006];
- UINT16 Lane0RxOvrdInHi;
- UINT8 Res200E[0x2022-0x200E];
- UINT16 Lane0TxCmWaitTimeOvrd;
- UINT8 Res2024[0x202A-0x2024];
- UINT16 Lane0TxLbertCtl;
- UINT16 Lane0RxLbertCtl;
- UINT16 Lane0RxLbertErr;
- UINT8 Res2030[0x205A-0x2030];
- UINT16 Lane0TxAltBlock;
-} CCSR_USB_PHY;
-
-/* Clocking */
-typedef struct {
- struct {
- UINT32 ClkCnCSr; /* core cluster n clock control status */
- UINT8 Res004[0x0c];
- UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
- UINT8 Res014[0x0c];
- } ClkcSr[4];
- UINT8 Res040[0x780]; /* 0x100 */
- struct {
- UINT32 PllCnGSr;
- UINT8 Res804[0x1c];
- } PllCgSr[NUM_CC_PLLS];
- UINT8 Res840[0x1c0];
- UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
- UINT8 Resa04[0x1fc];
- UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
- UINT8 Resc04[0x1c];
- UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
- UINT8 Resc24[0x3dc];
-} CCSR_CLOCK;
-
VOID
GetSysInfo (
OUT SYS_INFO *
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 18a1f5e4e1..847331a631 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -53,21 +53,6 @@ GetBusFrequency (
return SocSysInfo.FreqSystemBus;
}

-/*
- * Return SDXC bus frequency
- */
-UINT64
-GetSdxcFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSdhc;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 3d803716c9..9baeb17ecf 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -32,38 +32,14 @@ GetSysInfo (
)
{
CCSR_GUR *GurBase;
- CCSR_CLOCK *ClkBase;
- UINTN CpuIndex;
- UINT32 TempRcw;
- UINT32 CPllSel;
- UINT32 CplxPll;
- CONST UINT8 CoreCplxPll[8] = {
- [0] = 0, /* CC1 PPL / 1 */
- [1] = 0, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 1, /* CC2 PPL / 2 */
- };
-
- CONST UINT8 CoreCplxPllDivisor[8] = {
- [0] = 1, /* CC1 PPL / 1 */
- [1] = 2, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 2, /* CC2 PPL / 2 */
- };
-
- UINTN PllCount;
- UINTN FreqCPll[NUM_CC_PLLS];
- UINTN PllRatio[NUM_CC_PLLS];
UINTN SysClk;

GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
SysClk = CLK_FREQ;

SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);

PtrSysInfo->FreqSystemBus = SysClk;
- PtrSysInfo->FreqDdrBus = SysClk;

//
// selects the platform clock:SYSCLK ratio and calculate
@@ -72,61 +48,6 @@ GetSysInfo (
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
- //
- // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
- //
- PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-
- for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
- PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
- if (PllRatio[PllCount] > 4) {
- FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
- } else {
- FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
- }
- }
-
- //
- // Calculate Core frequency
- //
- for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
- CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
- CplxPll = CoreCplxPll[CPllSel];
-
- PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
- }
-
- //
- // Calculate FMAN frequency
- //
- TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
- switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
- case 2:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
- break;
- case 3:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
- break;
- case 4:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
- break;
- case 5:
- PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
- break;
- case 6:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
- break;
- case 7:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
- break;
- default:
- DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
- break;
- }
- PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
- PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
}

/**
--
2.17.1


[PATCH 06/19] Silicon/NXP: remove print information from Soc lib

Pankaj Bansal
 

The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase impelmentation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
core info.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---
Silicon/NXP/Library/SocLib/Chassis.c | 337 -------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 8 -
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Library/SocLib/SerDes.c | 268 ---------------
6 files changed, 727 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c

diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
deleted file mode 100644
index 9afbc52239..0000000000
--- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** LsSerDes.h
- The Header file of SerDes Module for Chassis 2
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef LS_SERDES_H_
-#define LS_SERDES_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SRDS_MAX_LANES 4
-
-typedef enum {
- None = 0,
- Pcie1,
- Pcie2,
- Pcie3,
- Sata,
- SgmiiFm1Dtsec1,
- SgmiiFm1Dtsec2,
- SgmiiFm1Dtsec5,
- SgmiiFm1Dtsec6,
- SgmiiFm1Dtsec9,
- SgmiiFm1Dtsec10,
- QsgmiiFm1A,
- XfiFm1Mac9,
- XfiFm1Mac10,
- Sgmii2500Fm1Dtsec2,
- Sgmii2500Fm1Dtsec5,
- Sgmii2500Fm1Dtsec9,
- Sgmii2500Fm1Dtsec10,
- SerdesPrtclCount
-} SERDES_PROTOCOL;
-
-typedef enum {
- Srds1 = 0,
- Srds2,
- SrdsMaxNum
-} SERDES_NUMBER;
-
-typedef struct {
- UINT16 Protocol;
- UINT8 SrdsLane[SRDS_MAX_LANES];
-} SERDES_CONFIG;
-
-typedef VOID
-(*SERDES_PROBE_LANES_CALLBACK) (
- IN SERDES_PROTOCOL LaneProtocol,
- IN VOID *Arg
- );
-
-VOID
-SerDesProbeLanes(
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- );
-
-#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
deleted file mode 100644
index 2d1c6f10f9..0000000000
--- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- The Header file of SerDes Module for LS1043A
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef SOC_SERDES_H_
-#define SOC_SERDES_H_
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#endif
-
-SERDES_CONFIG SerDes1ConfigTbl[] = {
- /* SerDes 1 */
- {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
- {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
- {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
- {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
- {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
- {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
- {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
- {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
- {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
- {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
- {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
- {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
- {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {}
-};
-
-SERDES_CONFIG *SerDesConfigTbl[] = {
- SerDes1ConfigTbl
-};
-
-#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index b8a8118c5e..18a1f5e4e1 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -25,16 +25,6 @@
#include <DramInfo.h>
#include "NxpChassis.h"

-/*
- * Structure to list available SOCs.
- * Name, Soc Version, Number of Cores
- */
-STATIC CPU_TYPE mCpuTypeList[] = {
- CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
-};
-
UINT32
EFIAPI
GurRead (
@@ -48,235 +38,6 @@ GurRead (
}
}

-/*
- * Return the type of initiator (core or hardware accelerator)
- */
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- )
-{
- CCSR_GUR *GurBase;
- UINT32 Idx;
- UINT32 Type;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
- Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
-
- if (Type & TP_ITYP_AV_MASK) {
- return Type;
- }
-
- return 0;
-}
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINT32 Mask;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- Mask = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
- Mask |= 1 << Count;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return Mask;
-}
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- )
-{
- UINTN Count;
- UINTN Num;
-
- Count = 0;
- Num = CpuMask ();
-
- while (Num) {
- Count += Num & 1;
- Num >>= 1;
- }
-
- return Count;
-}
-
-/*
- * Return core's cluster
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return ClusterIndex;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return -1; // cannot identify the cluster
-}
-
-/*
- * Return the type of core i.e. A53, A57 etc of inputted
- * core number.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return Type;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return EFI_NOT_FOUND; /* cannot identify the cluster */
-}
-
-STATIC
-UINTN
-CpuMaskNext (
- IN UINTN Cpu,
- IN UINTN Mask
- )
-{
- for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
-
- return Cpu;
-}
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- )
-{
- SYS_INFO SysInfo;
- UINTN CoreIndex;
- UINTN Core;
- UINT32 Type;
- UINT32 NumCpus;
- UINT32 Mask;
- CHAR8 *CoreName;
-
- GetSysInfo (&SysInfo);
- DEBUG ((DEBUG_INIT, "Clock Configuration:"));
-
- NumCpus = CpuNumCores ();
- Mask = CpuMask ();
-
- for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
- CoreIndex < NumCpus;
- CoreIndex++, Core = CpuMaskNext(Core, Mask))
- {
- if (!(CoreIndex % 3)) {
- DEBUG ((DEBUG_INIT, "\n "));
- }
-
- Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
- switch (Type) {
- case TY_ITYP_VERSION_A7:
- CoreName = "A7";
- break;
- case TY_ITYP_VERSION_A53:
- CoreName = "A53";
- break;
- case TY_ITYP_VERSION_A57:
- CoreName = "A57";
- break;
- case TY_ITYP_VERSION_A72:
- CoreName = "A72";
- break;
- default:
- CoreName = " Unknown Core ";
- }
- DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
- Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
- DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
-
- if (SysInfo.FreqFman[0] != 0) {
- DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Return system bus frequency
*/
@@ -307,77 +68,6 @@ GetSdxcFrequency (
return SocSysInfo.FreqSdhc;
}

-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- )
-{
- CHAR8 Buf[20];
- CCSR_GUR *GurBase;
- UINTN Count;
- //
- // Svr : System Version Register
- //
- UINTN Svr;
- UINTN Ver;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
-
- if (IS_E_PROCESSOR (Svr)) {
- AsciiStrCatS (Buf, sizeof (Buf), "E");
- }
- break;
- }
- }
-
- DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
- Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
-
- return;
-}
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- )
-{
- CCSR_GUR *Base;
- UINTN Count;
-
- Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- /*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
-
- DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
- for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
- UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
-
- if ((Count % 4) == 0) {
- DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
- }
-
- DEBUG ((DEBUG_INIT, " %08x", Rcw));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -400,33 +90,6 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}

-/*
- * Return current Soc Name form mCpuTypeList
- */
-CHAR8 *
-GetSocName (
- VOID
- )
-{
- UINT8 Count;
- UINTN Svr;
- UINTN Ver;
- CCSR_GUR *GurBase;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- return (CHAR8 *)mCpuTypeList[Count].Name;
- }
- }
-
- return NULL;
-}
-
UINTN
GetDramSize (
IN VOID
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 5a1a7376cd..3d803716c9 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -171,13 +171,5 @@ SocInit (
DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
(CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));

- PrintCpuInfo ();
-
- //
- // Print Reset control Word
- //
- PrintRCW ();
- PrintSoc ();
-
return;
}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3334d4d4f1..fe77717337 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -30,7 +30,6 @@
[Sources.common]
Chassis.c
Chassis2/Soc.c
- SerDes.c

[BuildOptions]
GCC:*_*_*_CC_FLAGS = -DCHASSIS2
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
deleted file mode 100644
index b9909d9221..0000000000
--- a/Silicon/NXP/Library/SocLib/SerDes.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/** SerDes.c
- Provides the basic interfaces for SerDes Module
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/LsSerDes.h>
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/DebugLib.h>
-#include <SocSerDes.h>
-#include <Uefi.h>
-
-/**
- Function to get serdes Lane protocol corresponding to
- serdes protocol.
-
- @param SerDes Serdes number.
- @param Cfg Serdes Protocol.
- @param Lane Serdes Lane number.
-
- @return Serdes Lane protocol.
-
-**/
-STATIC
-SERDES_PROTOCOL
-GetSerDesPrtcl (
- IN INTN SerDes,
- IN INTN Cfg,
- IN INTN Lane
- )
-{
- SERDES_CONFIG *Config;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return 0;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Cfg) {
- return Config->SrdsLane[Lane];
- }
- Config++;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if inputted protocol is a valid serdes protocol.
-
- @param SerDes Serdes number.
- @param Prtcl Serdes Protocol to be verified.
-
- @return EFI_INVALID_PARAMETER Input parameter in invalid.
- @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
- @return EFI_SUCCESS Serdes Protocol is a valid protocol.
-
-**/
-STATIC
-EFI_STATUS
-CheckSerDesPrtclValid (
- IN INTN SerDes,
- IN UINT32 Prtcl
- )
-{
- SERDES_CONFIG *Config;
- INTN Cnt;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return EFI_INVALID_PARAMETER;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Prtcl) {
- DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
- break;
- }
- Config++;
- }
-
- if (!Config->Protocol) {
- return EFI_NOT_FOUND;
- }
-
- for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
- if (Config->SrdsLane[Cnt] != None) {
- return EFI_SUCCESS;
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- Function to fill serdes map information.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Serdes Protocol Mask.
- @param SerdesProtocolShift Serdes Protocol shift value.
- @param SerDesPrtclMap Pointer to Serdes Protocol map.
-
-**/
-STATIC
-VOID
-LSSerDesMap (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- OUT UINT64 *SerDesPrtclMap
- )
-{
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
- UINT32 Flag;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- *SerDesPrtclMap = 0x0;
- Flag = 0;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
- Srds + 1, SrdsProt, SrdsProt));
-
- if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
- DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
- Srds + 1, SrdsProt));
- Flag++;
- }
-
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if (LanePrtcl >= SerdesPrtclCount) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- Flag++;
- } else {
- *SerDesPrtclMap |= (1u << LanePrtcl);
- }
- }
-
- if (Flag) {
- DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
- } else {
- DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
- }
-}
-
-/**
- Get lane protocol on provided serdes lane and execute callback function.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
- @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-STATIC
-VOID
-SerDesInstanceProbeLanes (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
-
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- /*
- * Invoke callback for all lanes in the SerDes instance:
- */
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- } else if (LanePrtcl != None) {
- SerDesLaneProbeCallback (LanePrtcl, Arg);
- }
- }
-}
-
-/**
- Probe all serdes lanes for lane protocol and execute provided callback function.
-
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-VOID
-SerDesProbeLanes (
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
- SerDesInstanceProbeLanes (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- SerDesInstanceProbeLanes (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
- }
-}
-
-/**
- Function to return Serdes protocol map for all serdes available on board.
-
- @param SerDesPrtclMap Pointer to Serdes protocl map.
-
-**/
-VOID
-GetSerdesProtocolMaps (
- OUT UINT64 *SerDesPrtclMap
- )
-{
- LSSerDesMap (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesPrtclMap);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- LSSerDesMap (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesPrtclMap);
- }
-
-}
-
-BOOLEAN
-IsSerDesLaneProtocolConfigured (
- IN UINT64 SerDesPrtclMap,
- IN SERDES_PROTOCOL Device
- )
-{
- if ((Device >= SerdesPrtclCount) || (Device < None)) {
- ASSERT ((Device > None) && (Device < SerdesPrtclCount));
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
- }
-
- return (SerDesPrtclMap & (1u << Device)) != 0 ;
-}
--
2.17.1


[PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality

Pankaj Bansal
 

SerialPortInitalize is called from DebugLib constructor. so this gets
called for each of the module in system. now, during SerialPortInitalize,
we need the Uart clock to set it's baud rate.

This Uart clock retrieval is implemented in SocLib and it usually involves
reading SysClock information (from FPGA or from clock generator)

so it's an unnecessary overhead, that can be avoided because we have
already initalized SerialPort in SEC phase.

Therefore, return SUCCESS from SerialPortInitalize everytime, without doing
anything.

In SEC phase we use SerialPortSetAttributes with default parameters to
mimic SerialPortInitalize.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../BaseSerialPortLib16550.c | 109 ++++--------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 25 +++-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 6 +-
3 files changed, 51 insertions(+), 89 deletions(-)

diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index 2c5c54ac7d..6b2aa46ff6 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -176,92 +176,6 @@ SerialPortInitialize (
VOID
)
{
- UINTN SerialRegisterBase;
- UINT32 Divisor;
- UINT32 CurrentDivisor;
- BOOLEAN Initialized;
- UINT64 SerialClock;
-
- //
- // Perform platform specific initialization required to enable use of the 16550 device
- // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
- //
- SerialClock = GetBusFrequency ();
- if (SerialClock == 0) {
- return EFI_DEVICE_ERROR;
- }
-
- //
- // Calculate divisor for baud generator
- // Ref_Clk_Rate / Baud_Rate / 16
- //
- Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
- if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
- Divisor++;
- }
-
- //
- // Get the base address of the serial port in either I/O or MMIO space
- //
- SerialRegisterBase = GetSerialRegisterBase ();
- if (SerialRegisterBase == 0) {
- return RETURN_DEVICE_ERROR;
- }
-
- //
- // See if the serial port is already initialized
- //
- Initialized = TRUE;
- if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
- Initialized = FALSE;
- }
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
- CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
- CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
- if (CurrentDivisor != Divisor) {
- Initialized = FALSE;
- }
- if (Initialized) {
- return RETURN_SUCCESS;
- }
-
- //
- // Wait for the serial port to be ready.
- // Verify that both the transmit FIFO and the shift register are empty.
- //
- while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
-
- //
- // Configure baud rate
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
-
- //
- // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
- // Strip reserved bits from PcdSerialLineControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
-
- //
- // Enable and reset FIFOs
- // Strip reserved bits from PcdSerialFifoControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
-
- //
- // Set FIFO Polled Mode by clearing IER after setting FCR
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
-
- //
- // Put Modem Control Register(MCR) into its reset state of 0x00.
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
-
return RETURN_SUCCESS;
}

@@ -785,6 +699,12 @@ SerialPortSetAttributes (
Divisor++;
}

+ //
+ // Wait for the serial port to be ready.
+ // Verify that both the transmit FIFO and the shift register are empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
//
// Configure baud rate
//
@@ -799,6 +719,23 @@ SerialPortSetAttributes (
Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));

+ //
+ // Enable and reset FIFOs
+ // Strip reserved bits from PcdSerialFifoControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+
+ //
+ // Set FIFO Polled Mode by clearing IER after setting FCR
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
+
+ //
+ // Put Modem Control Register(MCR) into its reset state of 0x00.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
+
return RETURN_SUCCESS;
}

diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index bfb8b8cb33..5a1a7376cd 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -1,7 +1,7 @@
/** @Soc.c
SoC specific Library containg functions to initialize various SoC components

- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -141,12 +141,33 @@ SocInit (
VOID
)
{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = 0; // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
SmmuInit ();

//
// Early init serial Port to get board information.
//
- SerialPortInitialize ();
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
(CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index cb670a1279..3334d4d4f1 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -36,6 +36,10 @@
GCC:*_*_*_CC_FLAGS = -DCHASSIS2

[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
--
2.17.1