Date   

[RFC PATCH v3 08/43] UefiCpuPkg/CpuExceptionHandler: Add base support for the #VC exception #vc

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Add base support to handle #VC exceptions. This includes a stub routine
to invoke when a #VC exception occurs and special checks in the common
exception handlers to invoke the #VC exception handler routine.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
OvmfPkg/OvmfPkgIa32.dsc | 5 ++
OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++
OvmfPkg/OvmfPkgX64.dsc | 5 ++
UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 2 +
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 2 +
.../DxeCpuExceptionHandlerLib.inf | 5 ++
.../PeiCpuExceptionHandlerLib.inf | 5 ++
.../SecPeiCpuExceptionHandlerLib.inf | 8 +++
.../CpuExceptionHandlerLib/AMDSevVcCommon.h | 26 ++++++++++
.../CpuExceptionCommon.h | 2 +
.../CpuExceptionCommon.c | 2 +-
.../Ia32/AMDSevVcCommon.c | 20 ++++++++
.../PeiDxeAMDSevVcHandler.c | 29 +++++++++++
.../PeiDxeSmmCpuException.c | 16 ++++++
.../SecAMDSevVcHandler.c | 50 +++++++++++++++++++
.../SecPeiCpuException.c | 16 ++++++
.../X64/AMDSevVcCommon.c | 35 +++++++++++++
17 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/AMDSevVcCommon.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeAMDSevVcHandler.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/SecAMDSevVcHandler.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index d350b756304e..0e17de188cd6 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -236,6 +236,7 @@ [LibraryClasses.common.SEC]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -274,6 +275,7 @@ [LibraryClasses.common.PEIM]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -299,6 +301,7 @@ [LibraryClasses.common.DXE_CORE]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
@@ -349,6 +352,7 @@ [LibraryClasses.common.DXE_DRIVER]
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SMM_REQUIRE) == TRUE
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
!else
@@ -392,6 +396,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SOURCE_DEBUG_ENABLE) == TRUE
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
!endif
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 1ef82cafe4aa..c8708c90f695 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -241,6 +241,7 @@ [LibraryClasses.common.SEC]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -279,6 +280,7 @@ [LibraryClasses.common.PEIM]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -304,6 +306,7 @@ [LibraryClasses.common.DXE_CORE]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
@@ -354,6 +357,7 @@ [LibraryClasses.common.DXE_DRIVER]
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SMM_REQUIRE) == TRUE
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
!else
@@ -397,6 +401,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SOURCE_DEBUG_ENABLE) == TRUE
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
!endif
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 232815c08e11..85f817b86130 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -241,6 +241,7 @@ [LibraryClasses.common.SEC]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -279,6 +280,7 @@ [LibraryClasses.common.PEIM]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -304,6 +306,7 @@ [LibraryClasses.common.DXE_CORE]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
@@ -354,6 +357,7 @@ [LibraryClasses.common.DXE_DRIVER]
PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SMM_REQUIRE) == TRUE
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
!else
@@ -397,6 +401,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
!if $(SOURCE_DEBUG_ENABLE) == TRUE
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
!endif
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
index 11cf17ca0647..8428da45a45a 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
@@ -233,6 +233,7 @@ [LibraryClasses.common.DXE_CORE]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -244,6 +245,7 @@ [LibraryClasses.common.DXE_DRIVER]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
index 5b7994a62cda..b88aa8ede04f 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
@@ -233,6 +233,7 @@ [LibraryClasses.common.DXE_CORE]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -244,6 +245,7 @@ [LibraryClasses.common.DXE_DRIVER]
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf

[LibraryClasses.common.DXE_RUNTIME_DRIVER]
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index e41383573043..dc328e230de3 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -26,17 +26,21 @@ [Sources.Ia32]
Ia32/ExceptionTssEntryAsm.nasm
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
+ Ia32/AMDSevVcCommon.c

[Sources.X64]
X64/ExceptionHandlerAsm.nasm
X64/ArchExceptionHandler.c
X64/ArchInterruptDefs.h
+ X64/AMDSevVcCommon.c

[Sources.common]
CpuExceptionCommon.h
CpuExceptionCommon.c
PeiDxeSmmCpuException.c
DxeException.c
+ PeiDxeAMDSevVcHandler.c
+ AMDSevVcCommon.h

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
@@ -57,3 +61,4 @@ [LibraryClasses]
PeCoffGetEntryPointLib
MemoryAllocationLib
DebugLib
+ VmgExitLib
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index f31423ac0f91..37dbbdb35711 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -26,17 +26,21 @@ [Sources.Ia32]
Ia32/ExceptionTssEntryAsm.nasm
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
+ Ia32/AMDSevVcCommon.c

[Sources.X64]
X64/ExceptionHandlerAsm.nasm
X64/ArchExceptionHandler.c
X64/ArchInterruptDefs.h
+ X64/AMDSevVcCommon.c

[Sources.common]
CpuExceptionCommon.h
CpuExceptionCommon.c
PeiCpuException.c
PeiDxeSmmCpuException.c
+ PeiDxeAMDSevVcHandler.c
+ AMDSevVcCommon.h

[Packages]
MdePkg/MdePkg.dec
@@ -52,6 +56,7 @@ [LibraryClasses]
HobLib
MemoryAllocationLib
SynchronizationLib
+ VmgExitLib

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index 6d25cafe2ca3..28b9a78c6be5 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -26,16 +26,20 @@ [Sources.Ia32]
Ia32/ExceptionTssEntryAsm.nasm
Ia32/ArchExceptionHandler.c
Ia32/ArchInterruptDefs.h
+ Ia32/AMDSevVcCommon.c

[Sources.X64]
X64/ExceptionHandlerAsm.nasm
X64/ArchExceptionHandler.c
X64/ArchInterruptDefs.h
+ X64/AMDSevVcCommon.c

[Sources.common]
CpuExceptionCommon.h
CpuExceptionCommon.c
SecPeiCpuException.c
+ SecAMDSevVcHandler.c
+ AMDSevVcCommon.h

[Packages]
MdePkg/MdePkg.dec
@@ -48,3 +52,7 @@ [LibraryClasses]
PrintLib
LocalApicLib
PeCoffGetEntryPointLib
+ VmgExitLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecGhcbBase
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h
new file mode 100644
index 000000000000..c0a2ecd17d4c
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h
@@ -0,0 +1,26 @@
+/** @file
+ Common header file for SEV-ES #VC Exception Handler Support.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _AMD_SEV_VC_COMMON_H_
+#define _AMD_SEV_VC_COMMON_H_
+
+#include <Protocol/DebugSupport.h>
+#include <Register/Amd/Ghcb.h>
+
+UINTN
+DoVcException(
+ EFI_SYSTEM_CONTEXT Context
+ );
+
+UINTN
+DoVcCommon(
+ GHCB *Ghcb,
+ EFI_SYSTEM_CONTEXT Context
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 805dd9cbb4ff..0f274e7ea328 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -24,6 +24,8 @@
#define CPU_INTERRUPT_NUM 256
#define HOOKAFTER_STUB_SIZE 16

+#define VC_EXCEPTION 29
+
//
// Exception Error Code of Page-Fault Exception
//
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 8adbd43fefb4..39e4dd9e9417 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -14,7 +14,7 @@
//
// 1 means an error code will be pushed, otherwise 0
//
-CONST UINT32 mErrorCodeFlag = 0x00227d00;
+CONST UINT32 mErrorCodeFlag = 0x20227d00;

//
// Define the maximum message length
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/AMDSevVcCommon.c
new file mode 100644
index 000000000000..595d9c2ba04e
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/AMDSevVcCommon.c
@@ -0,0 +1,20 @@
+/** @file
+ IA32 SEV-ES #VC Exception Handler functons.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include "AMDSevVcCommon.h"
+
+UINTN
+DoVcCommon (
+ GHCB *Ghcb,
+ EFI_SYSTEM_CONTEXT Context
+ )
+{
+ return GP_EXCEPTION;
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeAMDSevVcHandler.c
new file mode 100644
index 000000000000..68baaa7c6a89
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeAMDSevVcHandler.c
@@ -0,0 +1,29 @@
+/** @file
+ PEI and DXE SEV-ES #VC Exception Handler functons.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Register/Amd/Msr.h>
+#include "CpuExceptionCommon.h"
+#include "AMDSevVcCommon.h"
+
+UINTN
+DoVcException (
+ EFI_SYSTEM_CONTEXT Context
+ )
+{
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+ GHCB *Ghcb;
+
+ Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
+ ASSERT(Msr.Bits.GhcbNegotiateBit == FALSE);
+
+ Ghcb = Msr.Ghcb;
+
+ return DoVcCommon (Ghcb, Context);
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
index 72c2aeca4c13..0c248e7eb904 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
@@ -7,6 +7,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/

#include "CpuExceptionCommon.h"
+#include "AMDSevVcCommon.h"
#include <Library/DebugLib.h>

/**
@@ -86,6 +87,21 @@ CommonExceptionHandlerWorker (
break;
}

+ if (ExceptionType == VC_EXCEPTION) {
+ UINTN Status;
+ //
+ // #VC must be handled for an SEV-ES guest
+ //
+ Status = DoVcException(SystemContext);
+ if (Status) {
+ // Exception not handled - Status contains the desired exception now
+ ExceptionType = Status;
+ } else {
+ // Exception handled
+ return;
+ }
+ }
+
if (ExternalInterruptHandler != NULL &&
ExternalInterruptHandler[ExceptionType] != NULL) {
(ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecAMDSevVcHandler.c
new file mode 100644
index 000000000000..a68b178d2236
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecAMDSevVcHandler.c
@@ -0,0 +1,50 @@
+/** @file
+ SEC SEV-ES #VC Exception Handler functons.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Register/Amd/Msr.h>
+#include "CpuExceptionCommon.h"
+#include "AMDSevVcCommon.h"
+
+
+UINTN
+DoVcException(
+ EFI_SYSTEM_CONTEXT Context
+ )
+{
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+ GHCB *Ghcb;
+
+ Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
+ Ghcb = Msr.Ghcb;
+
+ if (Msr.Bits.GhcbNegotiateBit) {
+ if (Msr.GhcbProtocol.SevEsProtocolMin > Msr.GhcbProtocol.SevEsProtocolMax) {
+ ASSERT (0);
+ return GP_EXCEPTION;
+ }
+
+ if ((Msr.GhcbProtocol.SevEsProtocolMin > GHCB_VERSION_MAX) ||
+ (Msr.GhcbProtocol.SevEsProtocolMax < GHCB_VERSION_MIN)) {
+ ASSERT (0);
+ return GP_EXCEPTION;
+ }
+
+ Msr.GhcbPhysicalAddress = FixedPcdGet32 (PcdSecGhcbBase);
+ AsmWriteMsr64(MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress);
+
+ Ghcb = Msr.Ghcb;
+ SetMem (Ghcb, sizeof (*Ghcb), 0);
+
+ /* Set the version to the maximum that can be supported */
+ Ghcb->ProtocolVersion = MIN (Msr.GhcbProtocol.SevEsProtocolMax, GHCB_VERSION_MAX);
+ Ghcb->GhcbUsage = GHCB_STANDARD_USAGE;
+ }
+
+ return DoVcCommon(Ghcb, Context);
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
index 20148db74cf8..998a90ba61a6 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
@@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

#include <PiPei.h>
#include "CpuExceptionCommon.h"
+#include "AMDSevVcCommon.h"

CONST UINTN mDoFarReturnFlag = 0;

@@ -24,6 +25,21 @@ CommonExceptionHandler (
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
+ if (ExceptionType == VC_EXCEPTION) {
+ UINTN Status;
+ //
+ // #VC must be handled for an SEV-ES guest
+ //
+ Status = DoVcException(SystemContext);
+ if (Status) {
+ // Exception not handled - Status contains the desired exception now
+ ExceptionType = Status;
+ } else {
+ // Exception handled
+ return;
+ }
+ }
+
//
// Initialize the serial port before dumping.
//
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c
new file mode 100644
index 000000000000..4b56767f9374
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c
@@ -0,0 +1,35 @@
+/** @file
+ X64 SEV-ES #VC Exception Handler functons.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/VmgExitLib.h>
+#include "AMDSevVcCommon.h"
+
+UINTN
+DoVcCommon (
+ GHCB *Ghcb,
+ EFI_SYSTEM_CONTEXT Context
+ )
+{
+ EFI_SYSTEM_CONTEXT_X64 *Regs = Context.SystemContextX64;
+ UINTN ExitCode;
+ UINTN Status;
+
+ VmgInit (Ghcb);
+
+ ExitCode = Regs->ExceptionData;
+ switch (ExitCode) {
+ default:
+ Status = VmgExit (Ghcb, SvmExitUnsupported, ExitCode, 0);
+ }
+
+ VmgDone (Ghcb);
+
+ return Status;
+}
--
2.17.1


[RFC PATCH v3 07/43] UefiCpuPkg: Implement library support for VMGEXIT

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

To support issuing a VMGEXIT instruction, create a library that can be
used to perform GHCB and VMGEXIT related operations and to issue the
actual VMGEXIT instruction when using the GHCB.

Additionally, two VMGEXIT / MMIO related functions are created to support
flash emulation. Flash emulation currently is done by marking the flash
area as read-only and taking a nested page fault to perform the emulation
of the instruction. However, emulation cannot be performed because there
is no instruction decode assist support when SEV-ES is enabled. Provide
routines to initiate an MMIO request to perform actual writes to flash.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
UefiCpuPkg/UefiCpuPkg.dec | 3 +
UefiCpuPkg/UefiCpuPkg.dsc | 5 +
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf | 33 +++++
UefiCpuPkg/Include/Library/VmgExitLib.h | 96 ++++++++++++++
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c | 132 +++++++++++++++++++
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni | 15 +++
6 files changed, 284 insertions(+)
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 12f4413ea5b0..90feb9166dc8 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -53,6 +53,9 @@ [LibraryClasses.IA32, LibraryClasses.X64]
##
MpInitLib|Include/Library/MpInitLib.h

+ ## @libraryclass Provides function to support VMGEXIT processing.
+ VmgExitLib|Include/Library/VmgExitLib.h
+
[Guids]
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index d28cb5cccb52..5ab7e423e8ab 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -63,6 +63,7 @@ [LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.PEIM]
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -74,6 +75,7 @@ [LibraryClasses.common.PEIM]
[LibraryClasses.IA32.PEIM, LibraryClasses.X64.PEIM]
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.DXE_DRIVER]
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -81,12 +83,14 @@ [LibraryClasses.common.DXE_DRIVER]
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.DXE_SMM_DRIVER]
SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf

[LibraryClasses.common.UEFI_APPLICATION]
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
@@ -136,6 +140,7 @@ [Components.IA32, Components.X64]
UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
+ UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
UefiCpuPkg/SecCore/SecCore.inf
diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
new file mode 100644
index 000000000000..6acfa779e75a
--- /dev/null
+++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
@@ -0,0 +1,33 @@
+## @file
+# VMGEXIT Support Library.
+#
+# Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = VmgExitLib
+ MODULE_UNI_FILE = VmgExitLib.uni
+ FILE_GUID = 3cd7368f-ef9b-4a9b-9571-2ed93813677e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = VmgExitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ VmgExitLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+
diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/Library/VmgExitLib.h
new file mode 100644
index 000000000000..b5639fbfa1a5
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/VmgExitLib.h
@@ -0,0 +1,96 @@
+/** @file
+ Public header file for the VMGEXIT Support library class.
+
+ This library class defines some routines used when invoking the VMGEXIT
+ instruction in support of SEV-ES.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __VMG_EXIT_LIB_H__
+#define __VMG_EXIT_LIB_H__
+
+#include <Register/Amd/Ghcb.h>
+
+
+/**
+ Perform VMGEXIT.
+
+ Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction and
+ then handles the return actions.
+
+ @param[in] GHCB A pointer to the GHCB
+ @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode field of
+ the GHCB.
+ @param[in] ExitInfo1 VMGEXIT information to be assigned to the SwExitInfo1
+ field of the GHCB.
+ @param[in] ExitInfo2 VMGEXIT information to be assigned to the SwExitInfo2
+ field of the GHCB.
+
+ @retval 0 VMGEXIT succeeded.
+ @retval Others VMGEXIT processing did not succeed. Exception number to
+ be issued.
+
+**/
+UINTN
+EFIAPI
+VmgExit (
+ GHCB *Ghcb,
+ UINT64 ExitCode,
+ UINT64 ExitInfo1,
+ UINT64 ExitInfo2
+ );
+
+/**
+ Perform pre-VMGEXIT initialization/preparation.
+
+ Performs the necessary steps in preparation for invoking VMGEXIT.
+
+ @param[in] GHCB A pointer to the GHCB
+
+**/
+VOID
+EFIAPI
+VmgInit (
+ GHCB *Ghcb
+ );
+
+/**
+ Perform post-VMGEXIT cleanup.
+
+ Performs the necessary steps to cleanup after invoking VMGEXIT.
+
+ @param[in] GHCB A pointer to the GHCB
+
+**/
+VOID
+EFIAPI
+VmgDone (
+ GHCB *Ghcb
+ );
+
+#define VMGMMIO_READ False
+#define VMGMMIO_WRITE True
+
+/**
+ Perform MMIO write of a buffer to a non-MMIO marked range.
+
+ Performs an MMIO write without taking a #VC. This is useful
+ for Flash devices, which are marked read-only.
+
+ @param[in] UINT8 A pointer to the destination buffer
+ @param[in] UINTN The immediate value to write
+ @param[in] UINTN Number of bytes to write
+
+**/
+VOID
+EFIAPI
+VmgMmioWrite (
+ UINT8 *Dest,
+ UINT8 *Src,
+ UINTN Bytes
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c
new file mode 100644
index 000000000000..23965b7ff022
--- /dev/null
+++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c
@@ -0,0 +1,132 @@
+/** @file
+ VMGEXIT Support Library.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Register/Amd/Ghcb.h>
+#include <Register/Amd/Msr.h>
+
+STATIC
+UINTN
+VmgExitErrorCheck (
+ GHCB *Ghcb
+ )
+{
+ GHCB_EXIT_INFO ExitInfo;
+ UINTN Reason, Action;
+
+ if (!Ghcb->SaveArea.SwExitInfo1) {
+ return 0;
+ }
+
+ ExitInfo.Uint64 = Ghcb->SaveArea.SwExitInfo1;
+ Action = ExitInfo.Elements.Lower32Bits;
+ if (Action == 1) {
+ Reason = ExitInfo.Elements.Upper32Bits;
+
+ switch (Reason) {
+ case UD_EXCEPTION:
+ case GP_EXCEPTION:
+ return Reason;
+ }
+ }
+
+ ASSERT (0);
+ return GP_EXCEPTION;
+}
+
+UINTN
+EFIAPI
+VmgExit (
+ GHCB *Ghcb,
+ UINT64 ExitCode,
+ UINT64 ExitInfo1,
+ UINT64 ExitInfo2
+ )
+{
+ Ghcb->SaveArea.SwExitCode = ExitCode;
+ Ghcb->SaveArea.SwExitInfo1 = ExitInfo1;
+ Ghcb->SaveArea.SwExitInfo2 = ExitInfo2;
+ AsmVmgExit ();
+
+ return VmgExitErrorCheck (Ghcb);
+}
+
+VOID
+EFIAPI
+VmgInit (
+ GHCB *Ghcb
+ )
+{
+ SetMem (&Ghcb->SaveArea, sizeof (Ghcb->SaveArea), 0);
+}
+
+VOID
+EFIAPI
+VmgDone (
+ GHCB *Ghcb
+ )
+{
+}
+
+UINTN
+EFIAPI
+VmgMmio (
+ UINT8 *MmioAddress,
+ UINT8 *Buffer,
+ UINTN Bytes,
+ BOOLEAN Write
+ )
+{
+ UINT64 MmioOp;
+ UINT64 ExitInfo1, ExitInfo2;
+ UINTN Status;
+ GHCB *Ghcb;
+ MSR_SEV_ES_GHCB_REGISTER Msr;
+
+ Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
+ Ghcb = Msr.Ghcb;
+
+ if (Write) {
+ MmioOp = SvmExitMmioWrite;
+ } else {
+ MmioOp = SvmExitMmioRead;
+ }
+
+ ExitInfo1 = (UINT64) (UINTN) MmioAddress;
+ ExitInfo2 = Bytes;
+
+ if (Write) {
+ CopyMem (Ghcb->SharedBuffer, Buffer, Bytes);
+ }
+
+ Ghcb->SaveArea.SwScratch = (UINT64) (UINTN) Ghcb->SharedBuffer;
+ Status = VmgExit (Ghcb, MmioOp, ExitInfo1, ExitInfo2);
+ if (Status != 0) {
+ return Status;
+ }
+
+ if (!Write) {
+ CopyMem (Buffer, Ghcb->SharedBuffer, Bytes);
+ }
+
+ return 0;
+}
+
+VOID
+EFIAPI
+VmgMmioWrite (
+ UINT8 *Dest,
+ UINT8 *Src,
+ UINTN Bytes
+ )
+{
+ VmgMmio (Dest, Src, Bytes, TRUE);
+}
+
diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni
new file mode 100644
index 000000000000..e8656aae4726
--- /dev/null
+++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni
@@ -0,0 +1,15 @@
+// /** @file
+// VMGEXIT support library instance.
+//
+// VMGEXIT support library instance.
+//
+// Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "VMGEXIT Support Library."
+
+#string STR_MODULE_DESCRIPTION #language en-US "VMGEXIT Support Library."
+
--
2.17.1


[RFC PATCH v3 06/43] MdePkg/BaseLib: Add support for the VMGEXIT instruction

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

VMGEXIT is a new instruction used for Hypervisor/Guest communication when
running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE)
to occur, resulting in a #VMEXIT with an exit code value of 0x403.

Provide the necessary support to execute the VMGEXIT instruction, which
is "rep; vmmcall".

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 2 ++
MdePkg/Include/Library/BaseLib.h | 14 +++++++++
MdePkg/Library/BaseLib/Ia32/GccInline.c | 17 +++++++++++
MdePkg/Library/BaseLib/X64/GccInline.c | 17 +++++++++++
MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 37 ++++++++++++++++++++++++
MdePkg/Library/BaseLib/X64/VmgExit.nasm | 32 ++++++++++++++++++++
6 files changed, 119 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index d7a1dd017e95..62a09197b8a8 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -153,6 +153,7 @@ [Sources.Ia32]
Ia32/EnableCache.c | MSFT
Ia32/DisableCache.c | MSFT
Ia32/XGetBv.nasm | MSFT
+ Ia32/VmgExit.nasm | MSFT


Ia32/GccInline.c | GCC
@@ -288,6 +289,7 @@ [Sources.X64]
X64/ReadCr0.nasm| MSFT
X64/ReadEflags.nasm| MSFT
X64/XGetBv.nasm | MSFT
+ X64/VmgExit.nasm | MSFT


X64/Non-existing.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 8b710dcc0aad..378f5c1b18fb 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -7897,6 +7897,20 @@ AsmXGetBv (
);


+/**
+ Executes a VMGEXIT instruction (VMMCALL with a REP prefix)
+
+ Executes a VMGEXIT instruction. This function is only available on IA-32 and
+ x64.
+
+**/
+VOID
+EFIAPI
+AsmVmgExit (
+ VOID
+ );
+
+
/**
Patch the immediate operand of an IA32 or X64 instruction such that the byte,
word, dword or qword operand is encoded at the end of the instruction's
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 591f0bb0e097..ee8c62c79c93 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1791,3 +1791,20 @@ AsmXGetBv (
}


+/**
+ Executes a VMGEXIT instruction.
+
+ Executes a VMGEXIT instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmVmgExit (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("rep; vmmcall":::"memory");
+}
+
+
diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLib/X64/GccInline.c
index 3eed1205adb2..277974eff9ee 100644
--- a/MdePkg/Library/BaseLib/X64/GccInline.c
+++ b/MdePkg/Library/BaseLib/X64/GccInline.c
@@ -1828,3 +1828,20 @@ AsmXGetBv (
}


+/**
+ Executes a VMGEXIT instruction.
+
+ Executes a VMGEXIT instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmVmgExit (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("rep; vmmcall":::"memory");
+}
+
+
diff --git a/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm b/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm
new file mode 100644
index 000000000000..85e6260b4e2c
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; VmgExit.Asm
+;
+; Abstract:
+;
+; AsmVmgExit function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmVmgExit (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmVmgExit)
+ASM_PFX(AsmVmgExit):
+;
+; NASM doesn't support the vmmcall instruction in 32-bit mode, so work around
+; this by temporarily switching to 64-bit mode.
+;
+BITS 64
+ rep vmmcall
+BITS 32
+ ret
+
diff --git a/MdePkg/Library/BaseLib/X64/VmgExit.nasm b/MdePkg/Library/BaseLib/X64/VmgExit.nasm
new file mode 100644
index 000000000000..400d0302c4a3
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/VmgExit.nasm
@@ -0,0 +1,32 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; VmgExit.Asm
+;
+; Abstract:
+;
+; AsmVmgExit function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmVmgExit (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmVmgExit)
+ASM_PFX(AsmVmgExit):
+ rep vmmcall
+ ret
+
--
2.17.1


[RFC PATCH v3 05/43] MdePkg/BaseLib: Add support for the XGETBV instruction

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Under SEV-ES, a CPUID instruction requires the current value of the XCR0
register. In order to retrieve that value, the XGETBV instruction needs
to be executed.

Provide the necessary support to execute the XGETBV instruction.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 2 ++
MdePkg/Include/Library/BaseLib.h | 17 +++++++++++++
MdePkg/Library/BaseLib/Ia32/GccInline.c | 28 ++++++++++++++++++++
MdePkg/Library/BaseLib/X64/GccInline.c | 30 ++++++++++++++++++++++
MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 ++++++++++++++++++++++
MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 +++++++++++++++++++++++++
6 files changed, 142 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3586beb0ab5c..d7a1dd017e95 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -152,6 +152,7 @@ [Sources.Ia32]
Ia32/ARShiftU64.c | MSFT
Ia32/EnableCache.c | MSFT
Ia32/DisableCache.c | MSFT
+ Ia32/XGetBv.nasm | MSFT


Ia32/GccInline.c | GCC
@@ -286,6 +287,7 @@ [Sources.X64]
X64/ReadCr2.nasm| MSFT
X64/ReadCr0.nasm| MSFT
X64/ReadEflags.nasm| MSFT
+ X64/XGetBv.nasm | MSFT


X64/Non-existing.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 2a75bc023f56..8b710dcc0aad 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -7880,6 +7880,23 @@ AsmLfence (
VOID
);

+/**
+ Executes a XGETBV instruction
+
+ Executes a XGETBV instruction. This function is only available on IA-32 and
+ x64.
+
+ @param[in] Index Extended control register index
+
+ @retval The current value of the extended control register
+**/
+UINT64
+EFIAPI
+AsmXGetBv (
+ IN UINT32 Index
+ );
+
+
/**
Patch the immediate operand of an IA32 or X64 instruction such that the byte,
word, dword or qword operand is encoded at the end of the instruction's
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 5287200f8754..591f0bb0e097 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1763,3 +1763,31 @@ AsmFlushCacheLine (
}


+/**
+ Executes a XGETBV instruction
+
+ Executes a XGETBV instruction. This function is only available on IA-32 and
+ x64.
+
+ @param[in] Index Extended control register index
+
+ @retval The current value of the extended control register
+**/
+UINT64
+EFIAPI
+AsmXGetBv (
+ IN UINT32 Index
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "xgetbv"
+ : "=A" (Data)
+ : "c" (Index)
+ );
+
+ return Data;
+}
+
+
diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLib/X64/GccInline.c
index 154ce1f57e92..3eed1205adb2 100644
--- a/MdePkg/Library/BaseLib/X64/GccInline.c
+++ b/MdePkg/Library/BaseLib/X64/GccInline.c
@@ -1798,3 +1798,33 @@ AsmFlushCacheLine (
}


+/**
+ Executes a XGETBV instruction
+
+ Executes a XGETBV instruction. This function is only available on IA-32 and
+ x64.
+
+ @param[in] Index Extended control register index
+
+ @retval The current value of the extended control register
+**/
+UINT64
+EFIAPI
+AsmXGetBv (
+ IN UINT32 Index
+ )
+{
+ UINT32 LowData;
+ UINT32 HighData;
+
+ __asm__ __volatile__ (
+ "xgetbv"
+ : "=a" (LowData),
+ "=d" (HighData)
+ : "c" (Index)
+ );
+
+ return (((UINT64)HighData) << 32) | LowData;
+}
+
+
diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
new file mode 100644
index 000000000000..23ad38df0710
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
@@ -0,0 +1,31 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XGetBv.Asm
+;
+; Abstract:
+;
+; AsmXgetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXGetBv (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXGetBv)
+ASM_PFX(AsmXGetBv):
+ mov ecx, [esp + 4]
+ xgetbv
+ ret
diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/MdePkg/Library/BaseLib/X64/XGetBv.nasm
new file mode 100644
index 000000000000..cd73e972d31b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XGetBv.Asm
+;
+; Abstract:
+;
+; AsmXgetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXGetBv (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXGetBv)
+ASM_PFX(AsmXGetBv):
+ xgetbv
+ shl rdx, 32
+ or rax, rdx
+ ret
+
--
2.17.1


[RFC PATCH v3 04/43] MdeModulePkg/DxeIplPeim: Support GHCB pages when creating page tables

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

GHCB pages must be mapped as shared pages, so modify the process of
creating identity mapped pagetable entries so that GHCB entries are
created without the encryption bit set.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 +
.../Core/DxeIplPeim/X64/VirtualMemory.h | 12 ++++-
.../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +-
.../Core/DxeIplPeim/X64/DxeLoadFunc.c | 11 ++++-
.../Core/DxeIplPeim/X64/VirtualMemory.c | 49 ++++++++++++++-----
5 files changed, 62 insertions(+), 16 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 98bc17fc9d1f..5e6b78e295e6 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -111,6 +111,8 @@ [Pcd.IA32,Pcd.X64]
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES

[Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIMES_CONSUMES
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
index 2d0493f109e8..6b7c38a441d6 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
@@ -201,6 +201,8 @@ EnableExecuteDisableBit (
@param[in, out] PageEntry2M Pointer to 2M page entry.
@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
+ @param[in] GhcbBase GHCB page area base address.
+ @param[in] GhcbSize GHCB page area size.

**/
VOID
@@ -208,7 +210,9 @@ Split2MPageTo4K (
IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
IN OUT UINT64 *PageEntry2M,
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
);

/**
@@ -217,6 +221,8 @@ Split2MPageTo4K (

@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
+ @param[in] GhcbBase GHCB page area base address.
+ @param[in] GhcbSize GHCB page area size.

@return The address of 4 level page map.

@@ -224,7 +230,9 @@ Split2MPageTo4K (
UINTN
CreateIdentityMappingPageTables (
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbkSize
);


diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
index 6e8ca824d469..284b34818ca7 100644
--- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
@@ -123,7 +123,7 @@ Create4GPageTablesIa32Pae (
//
// Need to split this 2M page that covers stack range.
//
- Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
+ Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, 0, 0);
} else {
//
// Fill in the Page Directory entries
@@ -282,7 +282,7 @@ HandOffToDxeCore (
//
// Create page table and save PageMapLevel4 to CR3
//
- PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE);
+ PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE, 0, 0);

//
// End of PEI phase signal
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
index f465eb1d8ac4..156a477d8467 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c
@@ -35,6 +35,8 @@ HandOffToDxeCore (
UINT32 Index;
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
+ VOID *GhcbBase;
+ UINTN GhcbSize;

//
// Clear page 0 and mark it as allocated if NULL pointer detection is enabled.
@@ -81,12 +83,19 @@ HandOffToDxeCore (
TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);

+ //
+ // Get the address and size of the GHCB pages
+ //
+ GhcbBase = (VOID *) PcdGet64 (PcdGhcbBase);
+ GhcbSize = PcdGet64 (PcdGhcbSize);
+
PageTables = 0;
if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
//
// Create page table and save PageMapLevel4 to CR3
//
- PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE);
+ PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE,
+ (EFI_PHYSICAL_ADDRESS) (UINTN) GhcbBase, GhcbSize);
} else {
//
// Set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 516cf908bc88..32a81d1f3c21 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -181,6 +181,8 @@ EnableExecuteDisableBit (
@param Size Size of the given physical memory.
@param StackBase Base address of stack.
@param StackSize Size of stack.
+ @param GhcbBase Base address of GHCB pages.
+ @param GhcbSize Size of GHCB area.

@retval TRUE Page table should be split.
@retval FALSE Page table should not be split.
@@ -190,7 +192,9 @@ ToSplitPageTable (
IN EFI_PHYSICAL_ADDRESS Address,
IN UINTN Size,
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
if (IsNullDetectionEnabled () && Address == 0) {
@@ -209,6 +213,12 @@ ToSplitPageTable (
}
}

+ if (GhcbBase) {
+ if ((Address < GhcbBase + GhcbSize) && ((Address + Size) > GhcbBase)) {
+ return TRUE;
+ }
+ }
+
return FALSE;
}
/**
@@ -322,6 +332,8 @@ AllocatePageTableMemory (
@param[in, out] PageEntry2M Pointer to 2M page entry.
@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
+ @param[in] GhcbBase GHCB page area base address.
+ @param[in] GhcbSize GHCB page area size.

**/
VOID
@@ -329,7 +341,9 @@ Split2MPageTo4K (
IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
IN OUT UINT64 *PageEntry2M,
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
EFI_PHYSICAL_ADDRESS PhysicalAddress4K;
@@ -355,7 +369,12 @@ Split2MPageTo4K (
//
// Fill in the Page Table entries
//
- PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
+ PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K;
+ if (!GhcbBase
+ || (PhysicalAddress4K < GhcbBase)
+ || (PhysicalAddress4K >= GhcbBase + GhcbSize)) {
+ PageTableEntry->Uint64 |= AddressEncMask;
+ }
PageTableEntry->Bits.ReadWrite = 1;

if ((IsNullDetectionEnabled () && PhysicalAddress4K == 0) ||
@@ -383,6 +402,8 @@ Split2MPageTo4K (
@param[in, out] PageEntry1G Pointer to 1G page entry.
@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
+ @param[in] GhcbBase GHCB page area base address.
+ @param[in] GhcbSize GHCB page area size.

**/
VOID
@@ -390,7 +411,9 @@ Split1GPageTo2M (
IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
IN OUT UINT64 *PageEntry1G,
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
EFI_PHYSICAL_ADDRESS PhysicalAddress2M;
@@ -413,11 +436,11 @@ Split1GPageTo2M (

PhysicalAddress2M = PhysicalAddress;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
- if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSize)) {
+ if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSize, GhcbBase, GhcbSize)) {
//
// Need to split this 2M page that covers NULL or stack range.
//
- Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
+ Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
@@ -616,6 +639,8 @@ EnablePageTableProtection (

@param[in] StackBase Stack base address.
@param[in] StackSize Stack size.
+ @param[in] GhcbBase GHCB base address.
+ @param[in] GhcbSize GHCB size.

@return The address of 4 level page map.

@@ -623,7 +648,9 @@ EnablePageTableProtection (
UINTN
CreateIdentityMappingPageTables (
IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
UINT32 RegEax;
@@ -809,8 +836,8 @@ CreateIdentityMappingPageTables (
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;

for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
- if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)) {
- Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);
+ if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize, GhcbBase, GhcbSize)) {
+ Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
@@ -840,11 +867,11 @@ CreateIdentityMappingPageTables (
PageDirectoryPointerEntry->Bits.Present = 1;

for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
- if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize)) {
+ if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize, GhcbBase, GhcbSize)) {
//
// Need to split this 2M page that covers NULL or stack range.
//
- Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
+ Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
--
2.17.1


[RFC PATCH v3 03/43] MdePkg: Add a structure definition for the GHCB

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

The GHCB is used by an SEV-ES guest for communicating between the guest
and the hypervisor. Create the GHCB definition as defined by the GHCB
protocol definition.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdePkg/Include/Register/Amd/Ghcb.h | 117 +++++++++++++++++++++++++++++
1 file changed, 117 insertions(+)
create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h

diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h
new file mode 100644
index 000000000000..e7ccca91f93d
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -0,0 +1,117 @@
+/** @file
+ Guest-Hypervisor Communication Block (GHCB) Definition.
+
+ Provides data types allowing an SEV-ES guest to interact with the hypervisor
+ using the GHCB protocol.
+
+ Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ SEV-ES Guest-Hypervisor Communication Block Standardization
+
+**/
+
+#ifndef __GHCB_H__
+#define __GHCB_H__
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+#define UD_EXCEPTION 6
+#define GP_EXCEPTION 13
+
+#define GHCB_VERSION_MIN 1
+#define GHCB_VERSION_MAX 1
+
+#define GHCB_STANDARD_USAGE 0
+
+typedef enum {
+ SvmExitDr7Read = 0x27,
+ SvmExitDr7Write = 0x37,
+ SvmExitRdtsc = 0x6E,
+ SvmExitRdpmc,
+ SvmExitCpuid = 0x72,
+ SvmExitInvd = 0x76,
+ SvmExitIoioProt = 0x7B,
+ SvmExitMsr,
+ SvmExitVmmCall = 0x81,
+ SvmExitRdtscp = 0x87,
+ SvmExitWbinvd = 0x89,
+ SvmExitMonitor,
+ SvmExitMwait,
+ SvmExitNpf = 0x400,
+
+ // VMG special exits
+ SvmExitMmioRead = 0x80000001,
+ SvmExitMmioWrite,
+ SvmExitNmiComplete,
+ SvmExitApResetHold,
+
+ SvmExitUnsupported = 0x8000FFFF,
+} SVM_EXITCODE;
+
+typedef enum {
+ GhcbCpl = 25,
+ GhcbRflags = 46,
+ GhcbRip,
+ GhcbRsp = 59,
+ GhcbRax = 63,
+ GhcbRcx = 97,
+ GhcbRdx,
+ GhcbRbx,
+ GhcbRbp = 101,
+ GhcbRsi,
+ GhcbRdi,
+ GhcbR8,
+ GhcbR9,
+ GhcbR10,
+ GhcbR11,
+ GhcbR12,
+ GhcbR13,
+ GhcbR14,
+ GhcbR15,
+ GhcbXCr0 = 125,
+} GHCB_REGISTER;
+
+typedef struct {
+ UINT8 Reserved1[203];
+ UINT8 Cpl;
+ UINT8 Reserved2[148];
+ UINT64 Dr7;
+ UINT8 Reserved3[144];
+ UINT64 Rax;
+ UINT8 Reserved4[264];
+ UINT64 Rcx;
+ UINT64 Rdx;
+ UINT64 Rbx;
+ UINT8 Reserved5[112];
+ UINT64 SwExitCode;
+ UINT64 SwExitInfo1;
+ UINT64 SwExitInfo2;
+ UINT64 SwScratch;
+ UINT8 Reserved6[56];
+ UINT64 XCr0;
+ UINT8 ValidBitmap[16];
+ UINT64 X87StateGpa;
+ UINT8 Reserved7[1016];
+} __attribute__ ((__packed__)) GHCB_SAVE_AREA;
+
+typedef struct {
+ GHCB_SAVE_AREA SaveArea;
+ UINT8 SharedBuffer[2032];
+ UINT8 Reserved1[10];
+ UINT16 ProtocolVersion;
+ UINT32 GhcbUsage;
+} __attribute__ ((__packed__)) __attribute__ ((aligned(SIZE_4KB))) GHCB;
+
+typedef union {
+ struct {
+ UINT32 Lower32Bits;
+ UINT32 Upper32Bits;
+ } Elements;
+
+ UINT64 Uint64;
+} GHCB_EXIT_INFO;
+
+#endif
--
2.17.1


[RFC PATCH v3 02/43] MdePkg: Add the MSR definition for the GHCB register

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

For SEV-ES, the GHCB page address is stored in the GHCB MSR register
(0xc0010130). Define the register and the format used for register
during GHCB protocol negotiation.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdePkg/Include/Register/Amd/Fam17Msr.h | 28 ++++++++++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
index 37b935dcdb30..55a5723e164e 100644
--- a/MdePkg/Include/Register/Amd/Fam17Msr.h
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -17,6 +17,34 @@
#ifndef __FAM17_MSR_H__
#define __FAM17_MSR_H__

+/**
+ Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
+
+**/
+#define MSR_SEV_ES_GHCB 0xc0010130
+
+/**
+ MSR information returned for #MSR_SEV_ES_GHCB
+**/
+typedef union {
+ struct {
+ UINT32 GhcbNegotiateBit:1;
+
+ UINT32 Reserved:31;
+ } Bits;
+
+ struct {
+ UINT8 Reserved[3];
+ UINT8 SevEncryptionBitPos;
+ UINT16 SevEsProtocolMin;
+ UINT16 SevEsProtocolMax;
+ } GhcbProtocol;
+
+ VOID *Ghcb;
+
+ UINT64 GhcbPhysicalAddress;
+} MSR_SEV_ES_GHCB_REGISTER;
+
/**
Secure Encrypted Virtualization (SEV) status register

--
2.17.1


[RFC PATCH v3 01/43] MdePkg: Create PCDs to be used in support of SEV-ES

Lendacky, Thomas
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198

Two new fixed PCSs are needed to support SEV-ES under OVMF:
- PcdSecGhcbBase UINT64 value that is the base address of the GHCB
used during the SEC phase.
- PcdSecGhcbSize UINT64 value that is the size, in bytes, of the GHCB
area used during the SEC phase.

Three new dynamic PCDs are needed to support SEV-ES under OVMF:
- PcdSevEsIsEnabled: BOOLEAN value used to indicate if SEV-ES is enabled
- PcdGhcbBase: UINT64 value that is the base address of the GHCB
allocation.
- PcdGhcbSize: UINT64 value that is the size, in bytes, of the
GHCB allocation (size is dependent on the number of
APs).

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
---
MdeModulePkg/MdeModulePkg.dec | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 41b9e70a1ac8..c3bdfcc80971 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -1037,6 +1037,14 @@ [PcdsFixedAtBuild]
# @Prompt Enable UEFI Stack Guard.
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055

+ ## The base address of the SEC GHCB page.
+ # @Prompt SEC GHCB Base Address
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecGhcbBase|0|UINT32|0x30001056
+
+ ## The total size of the SEC GHCB page.
+ # @Prompt SEC GHCB Size
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecGhcbSize|0|UINT32|0x30001057
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## Dynamic type PCD can be registered callback function for Pcd setting action.
# PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of callback function
@@ -2053,6 +2061,21 @@ [PcdsDynamic, PcdsDynamicEx]
# @Prompt If there is any test key used by the platform.
gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed|FALSE|BOOLEAN|0x00030003

+ ## This dynamic PCD indicates whether SEV-ES is enabled
+ # TRUE - SEV-ES is enabled
+ # FALSE - SEV-ES is not enabled
+ # @Prompt SEV-ES Status
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x00030007
+
+ ## This dynamic PCD holds the base address of the GHCB pool allocation.
+ # @Prompt GHCB Pool Base Address
+ gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0|UINT64|0x00030008
+
+ ## This dynamic PCD holds the total size of the GHCB pool allocation.
+ # The amount of memory allocated for GHCBs is dependent on the number of APs.
+ # @Prompt GHCB Pool Size
+ gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030009
+
[PcdsDynamicEx]
## This dynamic PCD enables the default variable setting.
# Its value is the default store ID value. The default value is zero as Standard default.
--
2.17.1


[RFC PATCH v3 00/43] SEV-ES guest support

Lendacky, Thomas
 

This patch series provides support for running EDK2/OVMF under SEV-ES.

Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the
SEV support to protect the guest register state from the hypervisor. See
"AMD64 Architecture Programmer's Manual Volume 2: System Programming",
section "15.35 Encrypted State (SEV-ES)" [1].

In order to allow a hypervisor to perform functions on behalf of a guest,
there is architectural support for notifying a guest's operating system
when certain types of VMEXITs are about to occur. This allows the guest to
selectively share information with the hypervisor to satisfy the requested
function. The notification is performed using a new exception, the VMM
Communication exception (#VC). The information is shared through the
Guest-Hypervisor Communication Block (GHCB) using the VMGEXIT instruction.
The GHCB format and the protocol for using it is documented in "SEV-ES
Guest-Hypervisor Communication Block Standardization" [2].

The main areas of the EDK2 code that are updated to support SEV-ES are
around the exception handling support and the AP boot support.

Exception support is required starting in Sec, continuing through Pei
and into Dxe in order to handle #VC exceptions that are generated. Each
AP requires it's own GHCB page as well as a page to hold values specific
to that AP.

AP booting poses some interesting challenges. The INIT-SIPI-SIPI sequence
is typically used to boot the APs. However, the hypervisor is not allowed
to update the guest registers. The GHCB document [2] talks about how SMP
booting under SEV-ES is performed.

Since the GHCB page must be a shared (unencrypted) page, the processor
must be running in long mode in order for the guest and hypervisor to
communicate with each other. As a result, SEV-ES is only supported under
the X64 architecture.

[1] https://www.amd.com/system/files/TechDocs/24593.pdf
[2] https://developer.amd.com/wp-content/resources/56421.pdf

---

These patches are based on commit:
cc6854506c2b ("Readme.md: remove positional references from submodule description")

Proper execution of SEV-ES relies on Bugzilla 2340 being fixed.

A version of the tree (with an extra patch to workaround Bugzilla 2340) can
be found at:
https://github.com/AMDESE/ovmf/tree/sev-es-v9

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ray Ni <ray.ni@intel.com>

Changes since v2:
- Added a way to locate the SEV-ES fixed AP RIP address for starting
AP's to avoid updating the actual flash image (build time location
that is identified with a GUID value).
- Create a VmgExit library to replace static inline functions.
- Move some PCDs to the appropriate packages
- Add support for writing to QEMU flash under SEV-ES
- Add additional MMIO opcode support
- Cleaned up the GHCB MSR CPUID protocol support

Changes since v1:
- Patches reworked to be more specific to the component/area being updated
and order of definition/usage
- Created a library for VMGEXIT-related functions to replace use of inline
functions
- Allocation method for GDT changed from AllocatePool to AllocatePages
- Early caching only enabled for SEV-ES guests
- Ensure AP loop mode set to halt loop mode for SEV-ES guests
- Reserved SEC GHCB-related memory areas when S3 is enabled

Tom Lendacky (43):
MdePkg: Create PCDs to be used in support of SEV-ES
MdePkg: Add the MSR definition for the GHCB register
MdePkg: Add a structure definition for the GHCB
MdeModulePkg/DxeIplPeim: Support GHCB pages when creating page tables
MdePkg/BaseLib: Add support for the XGETBV instruction
MdePkg/BaseLib: Add support for the VMGEXIT instruction
UefiCpuPkg: Implement library support for VMGEXIT
UefiCpuPkg/CpuExceptionHandler: Add base support for the #VC exception
UefiCpuPkg/CpuExceptionHandler: Add support for IOIO_PROT NAE events
UefiCpuPkg/CpuExceptionHandler: Support string IO for IOIO_PROT NAE
events
UefiCpuPkg/CpuExceptionHandler: Add support for CPUID NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for MSR_PROT NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for NPF NAE events (MMIO)
UefiCpuPkg/CpuExceptionHandler: Add support for WBINVD NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for RDTSC NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for RDPMC NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for INVD NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for VMMCALL NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for RDTSCP NAE events
UefiCpuPkg/CpuExceptionHandler: Add support for MONITOR/MONITORX NAE
events
UefiCpuPkg/CpuExceptionHandler: Add support for MWAIT/MWAITX NAE
events
UefiCpuPkg/CpuExceptionHandler: Add support for DR7 Read/Write NAE
events
OvmfPkg/MemEncryptSevLib: Add an SEV-ES guest indicator function
OvmfPkg: Add support to perform SEV-ES initialization
OvmfPkg/ResetVector: Add support for a 32-bit SEV check
OvmfPkg: Create a GHCB page for use during Sec phase
OvmfPkg/PlatformPei: Reserve GHCB-related areas if S3 is supported
OvmfPkg: Create GHCB pages for use during Pei and Dxe phase
OvmfPkg/PlatformPei: Move early GDT into ram when SEV-ES is enabled
OvmfPkg/Sec: Add #VC exception handling for Sec phase
OvmfPkg/Sec: Enable cache early to speed up booting
OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash detection with
SEV-ES is enabled
MdeModulePkg: Reserve a 16-bit protected mode code segment descriptor
UefiCpuPkg: Add a 16-bit protected mode code segment descriptor
UefiCpuPkg/MpInitLib: Add a CPU MP data flag to indicate if SEV-ES is
enabled
UefiCpuPkg: Allow AP booting under SEV-ES
OvmfPkg: Reserve a page in memory for the SEV-ES AP reset vector
OvmfPkg: Move the GHCB allocations into reserved memory
MdePkg: Add a finalization function to the CPU protocol
UefiCpuPkg/MpInitLib: Add MP finalization interface to MpInitLib
UefiCpuPkg/MpInitLib: Prepare SEV-ES guest APs for OS use
UefiCpuPkg/CpuDxe: Provide an DXE MP finalization routine to support
SEV-ES
MdeModulePkg/DxeCore: Perform the CPU protocol finalization support

MdeModulePkg/MdeModulePkg.dec | 23 +
OvmfPkg/OvmfPkg.dec | 5 +
UefiCpuPkg/UefiCpuPkg.dec | 8 +
OvmfPkg/OvmfPkgIa32.dsc | 11 +
OvmfPkg/OvmfPkgIa32X64.dsc | 11 +
OvmfPkg/OvmfPkgX64.dsc | 11 +
UefiCpuPkg/UefiCpuPkg.dsc | 5 +
UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 2 +
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 2 +
OvmfPkg/OvmfPkgX64.fdf | 9 +
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 +
MdePkg/Library/BaseLib/BaseLib.inf | 4 +
OvmfPkg/PlatformPei/PlatformPei.inf | 7 +
.../FvbServicesRuntimeDxe.inf | 2 +
OvmfPkg/ResetVector/ResetVector.inf | 9 +
OvmfPkg/Sec/SecMain.inf | 1 +
.../DxeCpuExceptionHandlerLib.inf | 5 +
.../PeiCpuExceptionHandlerLib.inf | 5 +
.../SecPeiCpuExceptionHandlerLib.inf | 8 +
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 4 +
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 +
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf | 33 +
.../Core/DxeIplPeim/X64/VirtualMemory.h | 12 +-
MdePkg/Include/Library/BaseLib.h | 31 +
MdePkg/Include/Protocol/Cpu.h | 18 +
MdePkg/Include/Register/Amd/Fam17Msr.h | 28 +
MdePkg/Include/Register/Amd/Ghcb.h | 117 ++
OvmfPkg/Include/Library/MemEncryptSevLib.h | 12 +
UefiCpuPkg/CpuDxe/CpuDxe.h | 12 +
UefiCpuPkg/CpuDxe/CpuGdt.h | 4 +-
UefiCpuPkg/Include/Library/MpInitLib.h | 14 +
UefiCpuPkg/Include/Library/VmgExitLib.h | 96 ++
.../CpuExceptionHandlerLib/AMDSevVcCommon.h | 26 +
.../CpuExceptionCommon.h | 2 +
UefiCpuPkg/Library/MpInitLib/MpLib.h | 79 +-
MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 5 +
.../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 6 +-
.../Core/DxeIplPeim/X64/DxeLoadFunc.c | 11 +-
.../Core/DxeIplPeim/X64/VirtualMemory.c | 49 +-
MdePkg/Library/BaseLib/Ia32/GccInline.c | 45 +
MdePkg/Library/BaseLib/X64/GccInline.c | 47 +
.../MemEncryptSevLibInternal.c | 77 +-
OvmfPkg/PlatformPei/AmdSev.c | 82 ++
OvmfPkg/PlatformPei/MemDetect.c | 23 +
.../QemuFlash.c | 38 +-
OvmfPkg/Sec/SecMain.c | 74 +-
UefiCpuPkg/CpuDxe/CpuDxe.c | 21 +-
UefiCpuPkg/CpuDxe/CpuGdt.c | 8 +-
.../CpuExceptionCommon.c | 2 +-
.../Ia32/AMDSevVcCommon.c | 20 +
.../PeiDxeAMDSevVcHandler.c | 29 +
.../PeiDxeSmmCpuException.c | 16 +
.../SecAMDSevVcHandler.c | 50 +
.../SecPeiCpuException.c | 16 +
.../X64/AMDSevVcCommon.c | 1230 +++++++++++++++++
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 136 +-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 280 +++-
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 35 +
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c | 132 ++
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +-
MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 37 +
MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 +
MdePkg/Library/BaseLib/X64/VmgExit.nasm | 32 +
MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 +
OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 94 ++
OvmfPkg/ResetVector/Ia32/PageTables64.asm | 337 ++++-
OvmfPkg/ResetVector/ResetVector.nasmb | 19 +
.../X64/ExceptionHandlerAsm.nasm | 15 +
UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 2 +-
.../Library/MpInitLib/Ia32/MpFuncs.nasm | 15 +
UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 4 +-
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 370 ++++-
UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni | 15 +
.../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +
74 files changed, 3969 insertions(+), 101 deletions(-)
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf
create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h
create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/AMDSevVcCommon.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeAMDSevVcHandler.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/SecAMDSevVcHandler.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c
create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm
create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm
create mode 100644 OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm
create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni

--
2.17.1


Re: [PATCH] BaseTools:fix regression issue for platform .map file

Liming Gao
 

Does this fix only impact Platform.map generation? If so, I prefer to catch it into this stable tag.

Thanks
Liming

-----Original Message-----
From: Fan, ZhijuX <zhijux.fan@intel.com>
Sent: Wednesday, November 20, 2019 6:07 PM
To: devel@edk2.groups.io
Cc: Gao, Liming <liming.gao@intel.com>; Feng, Bob C <bob.c.feng@intel.com>
Subject: [PATCH] BaseTools:fix regression issue for platform .map file

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2363

The line of IMAGE=*** is missing in platform .map file.For example,
in Ovmf.map, there is no line of (IMAGE= ) under each of modules item.
This is a regression issue.

this patch is going to fix this issue

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
---
BaseTools/Source/Python/build/build.py | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index bcd832c525..e24f040a93 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -2216,6 +2216,7 @@ class Build():
Wa, self.BuildModules = self.PerformAutoGen(BuildTarget,ToolChain)
Pa = Wa.AutoGenObjectList[0]
GlobalData.gAutoGenPhase = False
+ self.LoadFixAddress = Wa.Platform.LoadFixAddress

if GlobalData.gBinCacheSource:
EdkLogger.quiet("Total cache hit driver num: %s, cache miss driver num: %s" % (len(set(self.HashSkipModules)),
len(set(self.BuildModules))))
@@ -2267,6 +2268,10 @@ class Build():
self.CreateAsBuiltInf()
if GlobalData.gBinCacheDest:
self.UpdateBuildCache()
+ #
+ # Get Module List
+ #
+ ModuleList = {ma.Guid.upper(): ma for ma in self.BuildModules}
self.BuildModules = []
self.MakeTime += int(round((time.time() - MakeContiue)))
#
@@ -2285,10 +2290,6 @@ class Build():
#
if (Arch == 'IA32' or Arch == 'ARM') and self.LoadFixAddress != 0xFFFFFFFFFFFFFFFF and
self.LoadFixAddress >= 0x100000000:
EdkLogger.error("build", PARAMETER_INVALID, "FIX_LOAD_TOP_MEMORY_ADDRESS can't be set to
larger than or equal to 4G for the platorm with IA32 or ARM arch modules")
- #
- # Get Module List
- #
- ModuleList = {ma.Guid.upper():ma for ma in self.BuildModules}

#
# Rebase module to the preferred memory address before GenFds
--
2.14.1.windows.1


Re: Patch List for 201911 stable tag

Liming Gao
 

Laszlo and Leif:
Thanks for your detail review. I will continue to monitor the coming changes for 201911 stable tag.

Thanks
Liming

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Leif Lindholm
Sent: Wednesday, November 20, 2019 3:02 AM
To: Laszlo Ersek <lersek@redhat.com>
Cc: Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; 'afish@apple.com' <afish@apple.com>;
devel@edk2.groups.io
Subject: Re: [edk2-devel] Patch List for 201911 stable tag

On Tue, Nov 19, 2019 at 06:50:19PM +0100, Laszlo Ersek wrote:
On 11/19/19 15:25, Gao, Liming wrote:
Hi Stewards and all:
I collect current patch lists in devel mail list. Those patch
contributors request to add them for 201911 stable tag. Because the
time is close to Hard Feature Freeze, I want to collect your
feedback for below patches.

Feature List (those all have pass code review):
https://edk2.groups.io/g/devel/message/50602 [PATCH V2] BaseTools: Add [packages] section in dsc file
This patch can be merged during the Soft Feature Freeze. It was posted
before the Soft Feature Freeze, and also reviewed (by Bob, i.e. a
BaseTools Maintainer) before the Soft Feature Freeze.

As far as I can see, there is still an outstanding question from you, to
Zhiju ("Can you show what test are done for this new support?"), so I
think we should await the response to that.

Note that the patch should not be merged once the Hard Feature Freeze
starts, so there are ~3 days for Zhiju to answer the question about
testing (and for you to acknowledge that you are OK with the reply).
Agreed.

Bug List (those all have pass code review):
https://edk2.groups.io/g/devel/message/50625 [PATCH v1] MdeModulePkg/NvmExpressDxe: Fix wrong queue size for async IO
queues

Looks very much like a bugfix to me, so it's suitable for merging even
during the Hard Feature Freeze.
I agree. But I am still slightly nervous about changing such a
fundamental part of such a fundamental driver. Certainly if it is
going in, I want it in ASAP, not just at the end of soft freeze - to
give us as much time as possible to revert it if the fix exposes
latent errors in previously working systems.

https://edk2.groups.io/g/devel/message/50406 [PATCH 1/1] MdePkg/Include: Add missing definitions of SMBIOS type 42h in
SmBios.h

Based on Abner's response in the thread, this change does not appear
necessary for fixing actual functionality bugs; it rather completes a
previously incomplete feature addition. And Abner is not in a rush to
catch the upcoming stable tag with the patch. I suggest to delay it.

If others disagree, I won't insist; the above is just my preference.
I'm OK either way.

https://edk2.groups.io/g/devel/message/50661 [PATCH] UefiCpuPkg: Update the coding styles
Hmmm, quite undecided on this one. Does not fix a functionality bug
either, but what it fixes *are* a coding style bugs, and the patch is
low risk. I'm leaning towards merging it.
I am against merging this, even though it's low-risk.

The process says:
"By the date of the soft feature freeze, developers must have sent
their patches to the mailing list and received positive maintainer
reviews (Reviewed-by or Acked-by tags)."
This received Acks 4 days late.

If it came with a commit message indicating the incorrect comment
syntax caused problems with document generation, then maybe it could
be considered from a bugfix standpoint. But it didn't and it's too
late to re-scope the change at this point.

I also dislike the mixing of doxygen formating changes and plain
whitespace changes. Even though trivial, it ought to be split up.

https://edk2.groups.io/g/devel/message/50662 [PATCH] MdePkg: Update the comments of IsLanguageSupported
This was even reviewed by a package maintainer (= you) before the SFF,
so it can definitely go in.
Agree (if cutting it close).

https://edk2.groups.io/g/devel/message/50663 [PATCH 0/3] Add missing strings for uni files
First of all, the structure of this series is wrong; please see my
feedback here:

https://edk2.groups.io/g/devel/message/50666

(The two patches discussed just above were incorrectly included in the
same posting.)

Second, the three patches for the UNI files add too much brand new text
for my taste, for them to be considered bugfixes. The patches were
posted in time for the SFF, but the maintainer reviews came too late:

https://edk2.groups.io/g/devel/message/50872
https://edk2.groups.io/g/devel/message/50869
https://edk2.groups.io/g/devel/message/50870

I suggest postponing.
Agree.

https://edk2.groups.io/g/devel/message/50866 [PATCH V1 0/2] Improve PeiInstallPeiMemory() description
I'm seriously confused by the subject prefixes in this patch thread.
What's going on with the version numbers?

[edk2-devel] [PATCH V1 0/2] Improve PeiInstallPeiMemory() description
[edk2-devel] [PATCH V3 1/2] MdeModulePkg PeiCore: Improve PeiInstallPeiMemory() description
[edk2-devel] [PATCH V1 2/2] MdePkg PiPeiCis.h: Improve PeiInstallPeiMemory() description

Other than that... I'm torn. I guess I could be convinced that these
patches are indeed bugfixes, so I'm leaning towards merging them.
Non-functional change submitted after start of soft-freeze?
I don't see why it should be considered.

https://edk2.groups.io/g/devel/message/50841 [PATCH V2 1/1] MdeModulePkg PeiCore: Fix typos
Personally I'm not happy about this patch. It's way too large for my taste:

MdeModulePkg/Core/Pei/PeiMain.inf | 10 ++--
MdeModulePkg/Core/Pei/FwVol/FwVol.h | 20 +++----
MdeModulePkg/Core/Pei/PeiMain.h | 52 ++++++++--------
MdeModulePkg/Core/Pei/Dependency/Dependency.c | 12 ++--
MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 51 ++++++++--------
MdeModulePkg/Core/Pei/FwVol/FwVol.c | 63 ++++++++++----------
MdeModulePkg/Core/Pei/Hob/Hob.c | 4 +-
MdeModulePkg/Core/Pei/Image/Image.c | 10 ++--
MdeModulePkg/Core/Pei/Memory/MemoryServices.c | 18 +++---
MdeModulePkg/Core/Pei/PeiMain/PeiMain.c | 2 +-
MdeModulePkg/Core/Pei/Ppi/Ppi.c | 4 +-
MdeModulePkg/Core/Pei/Security/Security.c | 12 ++--
12 files changed, 129 insertions(+), 129 deletions(-)

and it mixes multiple kinds of changes:

"Fixes typos and clarifies some wording throughout PeiCore."

When reviewing such a patch, the reviewer has a difficult time telling
apart purely syntactic (typo) fixes from semantic (wording) fixes. As a
reviewer I would suggest splitting this patch at least in two (typos vs.
semantics). Then I could be convinced such a set of two patches is
purely a bugfix.

I'm leaning towards "postpone" on this one, but I can see why people
would think "that's arbitrary". I guess I'll have to defer to others in
this instance.
Non-functional change submitted after start of soft-freeze?
I don't see why it should be considered.

I also agree on the needs splitting up bit.

Best Regards,

Leif


Re: [edk2-non-osi] [PATCH V2 0/1] Add ME Firmware Binaries for Cascade Lake

wvervoorn@...
 

Hi,

This is great news.

What I don't understand yet is how this relates to the removal of the Purley platform and the comments made when the bug report requesting Cascade Lake support was closed.

Does this mean a replacement for the Purley Refresh platform that supports the MinPlatform architecture can be expected shortly?

Best Regards,
Wim Vervoorn

Eltan B.V.
Ambachtstraat 23
5481 SM Schijndel
The Netherlands

T : +31-(0)73-594 46 64
E : wvervoorn@eltan.com
W : http://www.eltan.com


"THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES."

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Nate DeSimone
Sent: Wednesday, November 20, 2019 3:39 AM
To: devel@edk2.groups.io
Cc: Isaac W Oram <isaac.w.oram@intel.com>; Vincent Zimmer <vincent.zimmer@intel.com>; Michael Kubacki <michael.a.kubacki@intel.com>
Subject: [edk2-devel] [edk2-non-osi] [PATCH V2 0/1] Add ME Firmware Binaries for Cascade Lake

This patch series adds ignition ME firmware binaries for the 2nd Generation Intel® Xeon® Scalable Processors and chipsets formerly known as Cascade Lake to the edk2-non-osi repository.

Ignition Firmware is a variant of ME firmware that is intended to provide lightweight chipset initialization. It does not contain all the features of the Intel® Server Platform Services (SPS) ME firmware. Ignition Firmware is consequently much smaller than Intel® SPS Firmware (~0.5 MB vs. ~3 MB).

This patch series represents a milestone for Intel as it is the first time Intel has provided a ME firmware binary under a redistributable license to the public. The license is identical to the license for Microcode and FSP.

Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Vincent Zimmer <vincent.zimmer@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Nate DeSimone (1):
Intel/PurleySiliconBinPkg: Add Ignition ME Firmware 1.0.2.29

.../MeFirmware/IgnitionFirmware/License.txt | 37 +++++++++
.../MeFirmware/IgnitionFirmware/MeRegion.bin | Bin 0 -> 471040 bytes
.../Other_Licenses/libgcc_License.txt | 73 ++++++++++++++++++
.../MeFirmware/IgnitionFirmware/README.md | 15 ++++
.../PurleySiliconBinPkg/MeFirmware/README.md | 5 ++
5 files changed, 130 insertions(+)
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/MeFirmware/IgnitionFirmware/License.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/MeFirmware/IgnitionFirmware/MeRegion.bin
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/MeFirmware/IgnitionFirmware/Other_Licenses/libgcc_License.txt
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/MeFirmware/IgnitionFirmware/README.md
create mode 100644 Silicon/Intel/PurleySiliconBinPkg/MeFirmware/README.md

--
2.24.0.windows.2


[PATCH] BaseTools:fixed Build failed issue for Non-English OS

Fan, ZhijuX
 

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2365

Build failed on Non-English OS if structurePcd is used in platform
dsc file.
When the output of some functions is converted to code,
Because different OS Character encoding form differently,
there may be problems with some functions

The patch is going to fixed this issue

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
---
BaseTools/Source/Python/Workspace/DscBuildData.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py b/BaseTools/Source/Python/Workspace/DscBuildData.py
index 9192077f90..901d95a413 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -1752,7 +1752,7 @@ class DscBuildData(PlatformBuildClassObject):
except:
EdkLogger.error('Build', COMMAND_FAILURE, 'Can not execute command: %s' % Command)
Result = Process.communicate()
- return Process.returncode, Result[0].decode(), Result[1].decode()
+ return Process.returncode, Result[0].decode(errors='ignore'), Result[1].decode(errors='ignore')

@staticmethod
def IntToCString(Value, ValueSize):
--
2.14.1.windows.1


Re: [edk2-platforms][PATCH 1/8] Platform/RPi: Add model family detection

Leif Lindholm
 

On Tue, Nov 19, 2019 at 04:30:05PM +0000, Pete Batard wrote:
Please keep in mind that when open source maintainers take ownership
of your code, they assume the responsibility to ensure that it doesn't
get broken by future updates elsewhere in the codebase, often way
beyond the commercial lifetime of the product that is supported by
that code. This is a sizable effort, and an important part of managing
that effort is ensuring that the code is in an acceptable shape to
begin with, and what 'acceptable' means differs between different
maintainers. Not being able to revert a patch easily because it
touches unrelated code may make our lives more difficult years after
you have stopped caring about this platform entirely.
I think you are actually exposing the root of the problem without realizing
it here.
That is quite a condescending thing to say.

Elements that may make a maintainer's life more difficult years after the
contributor stopped working on it can actually be elements that makes, and
will continue to make, a whole lot of developers' lives much easier right
now.
Much easier than occasionally using git add --patch or git-gui to
stage individual hunks?

Splitting occasional minor changes out into separate patches should be
< 1min effort.

For instance, someone today or tomorrow (rather than 2 or 5 years down the
line) can very well copy from code that got rejected as an "Also" (say, the
one instance I found in the Pi source where a %s was used instead of a %a,
which is an easy thing to miss if you're not paying attention) and find out
they are wasting time on an issue that they would never have had to contend
with, had the EDK2 maintainership been flexible with regards to what might
be acceptable to piggyback on a patch that pertains to a specific file (IMO,
fixing typos or style should always be acceptable as a piggyback, and I'd
really like to hear how including such changes is effectively going to make
the maintainers' job that harder down the line).
Ard gave a very specific example in the email you are replying to.

I can give (and have given) you others, but since those have seen no
reaction (either acknowledgment or detraction) from you, there seems
to be little point in adding more.

And though this is a not directly related issue, I could also speak volumes
on how myself, and I assume many, many other developers, have wasted
countless hours (my current estimate puts that to around 4 to 5 hours in my
case) on the current CRLF enforcing situation with the EDK2 codebase.
That is a completely unrelated issue, which I have certainly also
wasted spectacular amounts of time on. And am working towards getting
rid of.

All this to re-state that I wish there existed a balance between the well
established needs of the maintainers, and what they envision might emerge as
issues in the long run (which I assert tends to encourage them to preserve
an existing status-quo), and the possibly not so well publicized pain points
and time wastage that consumers of the codebase encounter, who, of course
(and, depending on how this discussion goes, I might come to see as perhaps
the wisest choice) generally tend to avoid venting their frustration on a
mailing list that aims at concerning itself solely with technical
discussions...
This isn't a balance discussion. Either you believe that open source
development happens in changesets or you do not. Either you see the
value in that for debugging, or you do not.

If what you care about is the ability to go back to what the tree
looked like at a given point in time, then sure, a lot of this will
seem very tedious to you.

This does not mean that any amount of debating the topic will convince
anyone who relies on the fundamentality of changesets for their
workflow.

In other words, if you are willing to consider how much more painful
allowing the piggybacking of low-hanging "Also"'s onto existing patch may
make your life as a maintainer down the line, please also be willing to
envision the scenarios in which not allowing the same thing might actually
be making the life of people who work with the codebase, and I'd really like
to stress out that I'm really not talking only about myself here, harder
right now.
You do realise that apart from reviewing patches, we also write and
contribute code ourselves - including to several other projects?
All which follow the exact same rule.

Suffice to say, this aspect of TianoCore is no more negotiable than
the same aspect of linux, u-boot or QEMU.

I will be sorry to see you stop contributing to TianoCore if that is
the effect, but I am not willing to continue to rehash the very
fundamentals of open source development.

/

Leif


[PATCH] BaseTools:fix regression issue for platform .map file

Fan, ZhijuX
 

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2363

The line of IMAGE=*** is missing in platform .map file.For example,
in Ovmf.map, there is no line of (IMAGE= ) under each of modules item.
This is a regression issue.

this patch is going to fix this issue

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
---
BaseTools/Source/Python/build/build.py | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/build/build.py b/BaseTools/Source/Python/build/build.py
index bcd832c525..e24f040a93 100755
--- a/BaseTools/Source/Python/build/build.py
+++ b/BaseTools/Source/Python/build/build.py
@@ -2216,6 +2216,7 @@ class Build():
Wa, self.BuildModules = self.PerformAutoGen(BuildTarget,ToolChain)
Pa = Wa.AutoGenObjectList[0]
GlobalData.gAutoGenPhase = False
+ self.LoadFixAddress = Wa.Platform.LoadFixAddress

if GlobalData.gBinCacheSource:
EdkLogger.quiet("Total cache hit driver num: %s, cache miss driver num: %s" % (len(set(self.HashSkipModules)), len(set(self.BuildModules))))
@@ -2267,6 +2268,10 @@ class Build():
self.CreateAsBuiltInf()
if GlobalData.gBinCacheDest:
self.UpdateBuildCache()
+ #
+ # Get Module List
+ #
+ ModuleList = {ma.Guid.upper(): ma for ma in self.BuildModules}
self.BuildModules = []
self.MakeTime += int(round((time.time() - MakeContiue)))
#
@@ -2285,10 +2290,6 @@ class Build():
#
if (Arch == 'IA32' or Arch == 'ARM') and self.LoadFixAddress != 0xFFFFFFFFFFFFFFFF and self.LoadFixAddress >= 0x100000000:
EdkLogger.error("build", PARAMETER_INVALID, "FIX_LOAD_TOP_MEMORY_ADDRESS can't be set to larger than or equal to 4G for the platorm with IA32 or ARM arch modules")
- #
- # Get Module List
- #
- ModuleList = {ma.Guid.upper():ma for ma in self.BuildModules}

#
# Rebase module to the preferred memory address before GenFds
--
2.14.1.windows.1


Re: [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts

Abner Chang
 

Thanks Mark!
This is actually the problem of using latest RISC-V gnu toolchain which causes system hangs in the early POST. GNU toolchain at commit 64879b24 doesn't have this problem. Thanks for catching this and I am looking for the solution in edk2 build tool to fix this issue instead of changing lds file. We would like to use the common lds instead of creating specific one for RISC-V.

Or do you know is there any link options could avoid those special sections?

br
Abner

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Mark Salter
Sent: Wednesday, November 20, 2019 2:18 AM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
<abner.chang@hpe.com>
Cc: Bob Feng <bob.c.feng@intel.com>; Liming Gao <liming.gao@intel.com>;
Leif Lindholm <leif.lindholm@linaro.org>; Chen, Gilbert
<gilbert.chen@hpe.com>
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39]
BaseTools/Scripts

On Mon, 2019-10-28 at 09:59 +0800, Abner Chang wrote:
Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
GccBase.lds causes PE32 relocation error.
This is the temporaty solution untill we find the root casue.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
BaseTools/Scripts/GccBaseRiscV.lds | 79
++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds

diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
b/BaseTools/Scripts/GccBaseRiscV.lds
new file mode 100644
index 0000000..91937aa
--- /dev/null
+++ b/BaseTools/Scripts/GccBaseRiscV.lds
@@ -0,0 +1,79 @@
+/** @file
+
+ Unified linker script for GCC based builds
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights
+ reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
+ reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
+ Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+SECTIONS {
+
+ /*
+ * The PE/COFF binary consists of DOS and PE/COFF headers, and a
sequence of
+ * section headers adding up to PECOFF_HEADER_SIZE bytes (which
differs
+ * between 32-bit and 64-bit builds). The actual start of the .text section
+ * will be rounded up based on its actual alignment.
+ */
+ . = PECOFF_HEADER_SIZE;
+
+ .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.text .text.* .stub .gnu.linkonce.t.*)
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
So, I tried running this risc-v port on a HiFive Unleashed board but it crashed
pretty early on. It turned out that the linker was placing some const data at
the start of .text before any actual code. That didn't work out well. I got
around that and was able to boot into the efi shell by adding this to tell the
linker explicitly where to put that data:

*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)

+ *(.got .got.*)
+
+ /*
+ * The contents of AutoGen.c files are mostly constant from the POV of
the
+ * program, but most of it ends up in .data or .bss by default since few
of
+ * the variable definitions that get emitted are declared as CONST.
+ * Unfortunately, we cannot pull it into the .text section entirely, since
+ * patchable PCDs are also emitted here, but we can at least move all of
the
+ * emitted GUIDs here.
+ */
+ *:AutoGen.obj(.data.g*Guid)
+ }
+
+ /*
+ * The alignment of the .data section should be less than or equal to the
+ * alignment of the .text section. This ensures that the relative offset
+ * between these sections is the same in the ELF and the PE/COFF
versions of
+ * this binary.
+ */
+ .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
{
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.bss .bss.*)
+ }
+
+ .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ KEEP (*(.eh_frame))
+ }
+
+ .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ *(.rela .rela.*)
+ }
+
+ .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ KEEP (*(.hii))
+ }
+
+ /*
+ * Retain the GNU build id but in a non-allocatable section so GenFw
+ * does not copy it into the PE/COFF image.
+ */
+ .build-id (INFO) : { *(.note.gnu.build-id) }
+
+ /DISCARD/ : {
+ *(.note.GNU-stack)
+ *(.gnu_debuglink)
+ *(.interp)
+ *(.dynsym)
+ *(.dynstr)
+ *(.dynamic)
+ *(.hash .gnu.hash)
+ *(.comment)
+ *(COMMON)
+ }
+}



Re: [PATCH] MdeModulePkg: LzmaCustomDecompressLib.inf don't support EBC anymore

Liming Gao
 

Reviewed-by: Liming Gao <liming.gao@intel.com>

-----Original Message-----
From: Liu, Zhiguang
Sent: Wednesday, November 20, 2019 2:35 PM
To: devel@edk2.groups.io
Cc: Gao, Liming <liming.gao@intel.com>; Wang, Jian J
<jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
Subject: [PATCH] MdeModulePkg: LzmaCustomDecompressLib.inf don't
support EBC anymore

After unifying the definition of size_t, EBC compiler has failure.
So don't compile this inf file for EBC

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2338

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---

MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre
ssLib.inf | 2 +-
MdeModulePkg/MdeModulePkg.dsc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git
a/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompr
essLib.inf
b/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecomp
ressLib.inf
index 42b741c64b..e8061f54f9 100644
---
a/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompr
essLib.inf
+++
b/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecomp
ressLib.inf
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the
build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC
+# VALID_ARCHITECTURES = IA32 X64
#

[Sources]
diff --git a/MdeModulePkg/MdeModulePkg.dsc
b/MdeModulePkg/MdeModulePkg.dsc
index 4320839abf..f7dbb27ce2 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -299,7 +299,6 @@
MdeModulePkg/Library/PeiDebugPrintHobLib/PeiDebugPrintHobLib.inf

MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLi
bNull.inf

MdeModulePkg/Library/PlatformHookLibSerialPortPpi/PlatformHookLibSerial
PortPpi.inf
-
MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre
ssLib.inf

MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLib
ReportStatusCode.inf
MdeModulePkg/Library/PeiDebugLibDebugPpi/PeiDebugLibDebugPpi.inf
MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -433,6 +432,7 @@

[Components.IA32, Components.X64, Components.ARM,
Components.AARCH64]

MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompre
ssLib.inf
+
MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre
ssLib.inf
MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
--
2.16.2.windows.1


[PATCH] MdeModulePkg: LzmaCustomDecompressLib.inf don't support EBC anymore

Zhiguang Liu
 

After unifying the definition of size_t, EBC compiler has failure.
So don't compile this inf file for EBC

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2338

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf | 2 +-
MdeModulePkg/MdeModulePkg.dsc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf b/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
index 42b741c64b..e8061f54f9 100644
--- a/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+++ b/MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC
+# VALID_ARCHITECTURES = IA32 X64
#

[Sources]
diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index 4320839abf..f7dbb27ce2 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -299,7 +299,6 @@
MdeModulePkg/Library/PeiDebugPrintHobLib/PeiDebugPrintHobLib.inf
MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
MdeModulePkg/Library/PlatformHookLibSerialPortPpi/PlatformHookLibSerialPortPpi.inf
- MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
MdeModulePkg/Library/PeiDebugLibDebugPpi/PeiDebugLibDebugPpi.inf
MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
@@ -433,6 +432,7 @@

[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf
+ MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
--
2.16.2.windows.1


Re: [PATCH V2] BaseTools:Add [packages] section in dsc file

Liming Gao
 

The test case is ok to me.

Acked-by: Liming Gao <liming.gao@intel.com>

Thanks
Liming

-----Original Message-----
From: Fan, ZhijuX
Sent: Wednesday, November 20, 2019 10:46 AM
To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@intel.com>
Subject: RE: [PATCH V2] BaseTools:Add [packages] section in dsc file

Hi:

regression test:
pass build for minplatforms, WhitleyRp, TigerLake

functional test:

Define a PCD in a dec file (e.g. StandaloneMmPkg.dec) that none of the
modules depend on,
it is defined in a [PcdsFixedAtBuild] or [PcdsFeatureFlag] section
Create the [Packages] section in the DSC file and add "
StandaloneMmPkg.dec" in [Packages] section

Test whether this PCD can be used in conditional statements in DSC/FDF files


Any question, please let me know. Thanks.

Best Regards
Fan Zhiju



-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Friday, November 15, 2019 9:55 AM
To: Fan, ZhijuX <zhijux.fan@intel.com>; devel@edk2.groups.io
Cc: Feng, Bob C <bob.c.feng@intel.com>
Subject: RE: [PATCH V2] BaseTools:Add [packages] section in dsc file

Zhiju:
Can you show what test are done for this new support?

Thanks
Liming
-----Original Message-----
From: Fan, ZhijuX
Sent: Thursday, November 14, 2019 9:28 AM
To: devel@edk2.groups.io
Cc: Gao, Liming <liming.gao@intel.com>; Feng, Bob C
<bob.c.feng@intel.com>
Subject: [PATCH V2] BaseTools:Add [packages] section in dsc file

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2270

Currently a PCD (e.g. FeaturePCD) cannot be used in a conditional
statement in a DSC/FDF file without a module in the build referencing
the PCD package DEC file.

An example implementation that to support this is to allow a [Packages]
section in the DSC file to list additional package dependencies for PCD
references in the package DSC/FDF files.

this patch is going to add the ability to have the [packages] section
defined in the DSC file

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
---
BaseTools/Source/Python/AutoGen/ModuleAutoGen.py | 29
+++++++++++++++++-----
BaseTools/Source/Python/AutoGen/PlatformAutoGen.py | 1 +
.../Source/Python/AutoGen/WorkspaceAutoGen.py | 1 +
BaseTools/Source/Python/Common/DataType.py | 1 +
BaseTools/Source/Python/Workspace/DscBuildData.py | 23
++++++++++++++++-
.../Source/Python/Workspace/MetaFileParser.py | 14 +++++++++++
.../Source/Python/Workspace/WorkspaceCommon.py | 2 ++
.../Source/Python/Workspace/WorkspaceDatabase.py | 4 +++
8 files changed, 68 insertions(+), 7 deletions(-)

diff --git a/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py
b/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py
index f0812b6887..e6d6c43810 100755
--- a/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/ModuleAutoGen.py
@@ -462,14 +462,31 @@ class ModuleAutoGen(AutoGen):
def BuildCommand(self):
return self.PlatformInfo.BuildCommand

- ## Get object list of all packages the module and its dependent libraries
belong to
+ ## Get Module package and Platform package
+ #
+ # @retval list The list of package object
+ #
+ @cached_property
+ def PackageList(self):
+ PkagList = []
+ if self.Module.Packages:
+ PkagList.extend(self.Module.Packages)
+ Platform = self.BuildDatabase[self.PlatformInfo.MetaFile,
+ self.Arch,
self.BuildTarget, self.ToolChain]
+ for Package in Platform.Packages:
+ if Package in PkagList:
+ continue
+ PkagList.append(Package)
+ return PkagList
+
+ ## Get object list of all packages the module and its dependent
+ libraries
belong to and the Platform depends on
#
# @retval list The list of package object
#
@cached_property
def DerivedPackageList(self):
PackageList = []
- for M in [self.Module] + self.DependentLibraryList:
+ PackageList.extend(self.PackageList)
+ for M in self.DependentLibraryList:
for Package in M.Packages:
if Package in PackageList:
continue
@@ -938,13 +955,13 @@ class ModuleAutoGen(AutoGen):
self.Targets
return self._FileTypes

- ## Get the list of package object the module depends on
+ ## Get the list of package object the module depends on and the
+ Platform
depends on
#
# @retval list The package object list
#
@cached_property
def DependentPackageList(self):
- return self.Module.Packages
+ return self.PackageList

## Return the list of auto-generated code file
#
@@ -1101,7 +1118,7 @@ class ModuleAutoGen(AutoGen):
RetVal.append(self.MetaFile.Dir)
RetVal.append(self.DebugDir)

- for Package in self.Module.Packages:
+ for Package in self.PackageList:
PackageDir = mws.join(self.WorkspaceDir, Package.MetaFile.Dir)
if PackageDir not in RetVal:
RetVal.append(PackageDir) @@ -1125,7 +1142,7 @@ class
ModuleAutoGen(AutoGen):
@cached_property
def PackageIncludePathList(self):
IncludesList = []
- for Package in self.Module.Packages:
+ for Package in self.PackageList:
PackageDir = mws.join(self.WorkspaceDir, Package.MetaFile.Dir)
IncludesList = Package.Includes
if Package._PrivateIncludes:
diff --git a/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
b/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
index debeb46f58..4c3cdf82d5 100644
--- a/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
@@ -975,6 +975,7 @@ class PlatformAutoGen(AutoGen):
continue
ModuleData = self.BuildDatabase[ModuleFile, self.Arch,
self.BuildTarget, self.ToolChain]
RetVal.update(ModuleData.Packages)
+ RetVal.update(self.Platform.Packages)
return list(RetVal)

@cached_property
diff --git a/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
b/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
index 9d8040905e..fde48b4b27 100644
--- a/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/WorkspaceAutoGen.py
@@ -420,6 +420,7 @@ class WorkspaceAutoGen(AutoGen):
continue
ModuleData = self.BuildDatabase[ModuleFile, Arch,
self.BuildTarget, self.ToolChain]
PkgSet.update(ModuleData.Packages)
+ PkgSet.update(Platform.Packages)
Pkgs[Arch] = list(PkgSet)
return Pkgs

diff --git a/BaseTools/Source/Python/Common/DataType.py
b/BaseTools/Source/Python/Common/DataType.py
index 5d49afb0a9..8d80b41089 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -519,6 +519,7 @@ SECTIONS_HAVE_ITEM_AFTER_ARCH_SET =
{TAB_LIBRARY_CLASSES.upper(), TAB_DEPEX.uppe
PCDS_DYNAMICEX_VPD.upper(),
PCDS_DYNAMICEX_HII.upper(),
TAB_BUILD_OPTIONS.upper(),
+ TAB_PACKAGES.upper(),
TAB_INCLUDES.upper()}

#
diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py
b/BaseTools/Source/Python/Workspace/DscBuildData.py
index 9192077f90..03a15bbf3e 100644
--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
@@ -719,6 +719,24 @@ class DscBuildData(PlatformBuildClassObject):

self._RawData.DisableOverrideComponent(Components[(file_guid_str,str
(
M
oduleFile))])
Components[(file_guid_str,str(ModuleFile))] = ModuleId
self._RawData._PostProcessed = False
+
+ ## Retrieve packages this Platform depends on
+ @cached_property
+ def Packages(self):
+ RetVal = set()
+ RecordList = self._RawData[MODEL_META_DATA_PACKAGE,
self._Arch]
+ Macros = self._Macros
+ for Record in RecordList:
+ File = PathClass(NormPath(Record[0], Macros),
GlobalData.gWorkspace, Arch=self._Arch)
+ # check the file validation
+ ErrorCode, ErrorInfo = File.Validate('.dec')
+ if ErrorCode != 0:
+ LineNo = Record[-1]
+ EdkLogger.error('build', ErrorCode,
+ ExtraData=ErrorInfo,
File=self.MetaFile, Line=LineNo)
+ # parse this package now. we need it to get protocol/ppi/guid value
+ RetVal.add(self._Bdb[File, self._Arch, self._Target, self._Toolchain])
+ return RetVal
+
## Retrieve [Components] section information
@property
def Modules(self):
@@ -896,7 +914,8 @@ class DscBuildData(PlatformBuildClassObject):
continue
ModuleData = self._Bdb[ModuleFile, self._Arch,
self._Target, self._Toolchain]
PkgSet.update(ModuleData.Packages)
-
+ if self.Packages:
+ PkgSet.update(self.Packages)
self._DecPcds, self._GuidDict = GetDeclaredPcd(self,
self._Bdb, self._Arch, self._Target, self._Toolchain, PkgSet)
self._GuidDict.update(GlobalData.gPlatformPcds)

@@ -3320,6 +3339,8 @@ class DscBuildData(PlatformBuildClassObject):
continue
ModuleData = self._Bdb[ModuleFile, self._Arch,
self._Target, self._Toolchain]
PkgSet.update(ModuleData.Packages)
+ if self.Packages:
+ PkgSet.update(self.Packages)
self._DecPcds, self._GuidDict = GetDeclaredPcd(self,
self._Bdb, self._Arch, self._Target, self._Toolchain, PkgSet)
self._GuidDict.update(GlobalData.gPlatformPcds)
return self._DecPcds
diff --git a/BaseTools/Source/Python/Workspace/MetaFileParser.py
b/BaseTools/Source/Python/Workspace/MetaFileParser.py
index 806fc322c5..3f96ce0564 100644
--- a/BaseTools/Source/Python/Workspace/MetaFileParser.py
+++ b/BaseTools/Source/Python/Workspace/MetaFileParser.py
@@ -160,6 +160,7 @@ class MetaFileParser(object):
self.MetaFile = FilePath
self._FileDir = self.MetaFile.Dir
self._Defines = {}
+ self._Packages = []
self._FileLocalMacros = {}
self._SectionsMacroDict = defaultdict(dict)

@@ -351,6 +352,13 @@ class MetaFileParser(object):
# If the section information is needed later, it should be
stored in database
self._ValueList[0] = self._SectionName

+ ## [packages] section parser
+ @ParseMacro
+ def _PackageParser(self):
+ self._CurrentLine = CleanString(self._CurrentLine)
+ self._Packages.append(self._CurrentLine)
+ self._ValueList[0] = self._CurrentLine
+
## [defines] section parser
@ParseMacro
def _DefineParser(self):
@@ -848,6 +856,7 @@ class DscParser(MetaFileParser):
TAB_LIBRARIES.upper() : MODEL_EFI_LIBRARY_INSTANCE,
TAB_LIBRARY_CLASSES.upper() : MODEL_EFI_LIBRARY_CLASS,
TAB_BUILD_OPTIONS.upper() :
MODEL_META_DATA_BUILD_OPTION,
+ TAB_PACKAGES.upper() :
MODEL_META_DATA_PACKAGE,
TAB_PCDS_FIXED_AT_BUILD_NULL.upper() :
MODEL_PCD_FIXED_AT_BUILD,
TAB_PCDS_PATCHABLE_IN_MODULE_NULL.upper() :
MODEL_PCD_PATCHABLE_IN_MODULE,
TAB_PCDS_FEATURE_FLAG_NULL.upper() :
MODEL_PCD_FEATURE_FLAG,
@@ -1339,6 +1348,7 @@ class DscParser(MetaFileParser):
MODEL_META_DATA_DEFINE : self.__ProcessDefine,
MODEL_META_DATA_GLOBAL_DEFINE :
self.__ProcessDefine,
MODEL_META_DATA_INCLUDE :
self.__ProcessDirective,
+ MODEL_META_DATA_PACKAGE :
self.__ProcessPackages,
MODEL_META_DATA_CONDITIONAL_STATEMENT_IF :
self.__ProcessDirective,
MODEL_META_DATA_CONDITIONAL_STATEMENT_ELSE :
self.__ProcessDirective,
MODEL_META_DATA_CONDITIONAL_STATEMENT_IFDEF :
self.__ProcessDirective,
@@ -1642,6 +1652,9 @@ class DscParser(MetaFileParser):
self._ValueList = None
self._ContentIndex -= 1

+ def __ProcessPackages(self):
+ self._ValueList[0] = ReplaceMacro(self._ValueList[0],
+ self._Macros)
+
def __ProcessSkuId(self):
self._ValueList = [ReplaceMacro(Value, self._Macros, RaiseError=True)
for Value in self._ValueList] @@ -1720,6
+1733,7 @@ class DscParser(MetaFileParser):
MODEL_META_DATA_COMPONENT : _ComponentParser,
MODEL_META_DATA_BUILD_OPTION : _BuildOptionParser,
MODEL_UNKNOWN : MetaFileParser._Skip,
+ MODEL_META_DATA_PACKAGE :
MetaFileParser._PackageParser,
MODEL_META_DATA_USER_EXTENSION :
MetaFileParser._SkipUserExtension,
MODEL_META_DATA_SECTION_HEADER :
MetaFileParser._SectionHeaderParser,
MODEL_META_DATA_SUBSECTION_HEADER :
_SubsectionHeaderParser,
diff --git a/BaseTools/Source/Python/Workspace/WorkspaceCommon.py
b/BaseTools/Source/Python/Workspace/WorkspaceCommon.py
index 0b11ec2d59..913e710fd9 100644
--- a/BaseTools/Source/Python/Workspace/WorkspaceCommon.py
+++ b/BaseTools/Source/Python/Workspace/WorkspaceCommon.py
@@ -37,6 +37,8 @@ class OrderedListDict(OrderedDict):
#
def GetPackageList(Platform, BuildDatabase, Arch, Target, Toolchain):
PkgSet = set()
+ if Platform.Packages:
+ PkgSet.update(Platform.Packages)
for ModuleFile in Platform.Modules:
Data = BuildDatabase[ModuleFile, Arch, Target, Toolchain]
PkgSet.update(Data.Packages)
diff --git a/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
b/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
index ab7b4506c1..9420eaa608 100644
--- a/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
+++ b/BaseTools/Source/Python/Workspace/WorkspaceDatabase.py
@@ -186,6 +186,10 @@ class WorkspaceDatabase(object):
for Package in LibObj.Packages:
if Package not in PackageList:
PackageList.append(Package)
+ for Package in Pa.Packages:
+ if Package in PackageList:
+ continue
+ PackageList.append(Package)

return PackageList

--
2.14.1.windows.1


Re: [PATCH v2 1/1] ShellPkg: acpiview: Update SRAT parser to ACPI 6.3

Gao, Zhichao
 

The patch fixed the rebase issue before. Before, one patch aimed to remove the redundant forward declaration. That cause the rebase error. But this patch add it back for ValidateSratReserved function. I'd like the format to be aligned.

Thanks,
Zhichao

-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Wednesday, November 20, 2019 5:43 AM
To: devel@edk2.groups.io; krzysztof.koch@arm.com; Sami Mujawar
<Sami.Mujawar@arm.com>
Cc: Ni, Ray <ray.ni@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>;
Matteo Carlini <Matteo.Carlini@arm.com>; nd <nd@arm.com>; Gao, Liming
<liming.gao@intel.com>
Subject: RE: [edk2-devel] [PATCH v2 1/1] ShellPkg: acpiview: Update SRAT parser
to ACPI 6.3

So, this patch passes the review before the soft feature freeze. If it gets Tested-
By before hard feature freeze, will it plan to catch 201911 stable tag?

Thanks
Liming
-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Krzysztof Koch
Sent: Tuesday, November 19, 2019 10:44 PM
To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io; Sami
Mujawar <Sami.Mujawar@arm.com>
Cc: Ni, Ray <ray.ni@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>;
Matteo Carlini <Matteo.Carlini@arm.com>; nd <nd@arm.com>
Subject: Re: [edk2-devel] [PATCH v2 1/1] ShellPkg: acpiview: Update
SRAT parser to ACPI 6.3

Hi Liming,

This is a feature support. This patch is a rebased version of a
reviewed patch that was pending to be merged due to a lack of 'tested-by', see:
https://edk2.groups.io/g/devel/message/42297?p=,,,20,0,0,0::Created,,Kr
zys
ztof+Koch+SRAT,20,2,0,32042587
https://edk2.groups.io/g/devel/message/42665?p=,,,20,0,0,0::Created,,We
+c
an+review+for+your+code+change.+And+for+our+personal+point%2C+the+
change+is+OK.,20,2,0,32042696

Kind regards,
Krzysztof


-----Original Message-----
From: Gao, Liming <liming.gao@intel.com>
Sent: Tuesday, November 19, 2019 14:24
To: devel@edk2.groups.io; Sami Mujawar <Sami.Mujawar@arm.com>;
Krzysztof Koch <Krzysztof.Koch@arm.com>
Cc: Ni, Ray <ray.ni@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>;
Matteo Carlini <Matteo.Carlini@arm.com>; nd <nd@arm.com>
Subject: RE: [edk2-devel] [PATCH v2 1/1] ShellPkg: acpiview: Update
SRAT parser to ACPI 6.3

Krzysztof:
Does this patch plan to catch to edk2 201911 stable tag? This change
is like a feature support. But, it doesn't pass review before soft feature freeze.

Thanks
Liming
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sami
Mujawar
Sent: Monday, November 18, 2019 5:33 PM
To: Krzysztof Koch <Krzysztof.Koch@arm.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>;
Matteo Carlini <Matteo.Carlini@arm.com>; nd <nd@arm.com>
Subject: Re: [edk2-devel] [PATCH v2 1/1] ShellPkg: acpiview: Update
SRAT parser to ACPI 6.3

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar
-----Original Message-----
From: Krzysztof Koch <krzysztof.koch@arm.com>
Sent: 12 November 2019 02:40 PM
To: devel@edk2.groups.io
Cc: ray.ni@intel.com; zhichao.gao@intel.com; Matteo Carlini
<Matteo.Carlini@arm.com>; Sami Mujawar <Sami.Mujawar@arm.com>; nd
<nd@arm.com>
Subject: [PATCH v2 1/1] ShellPkg: acpiview: Update SRAT parser to
ACPI
6.3

Add support for parsing revision 3 of System Resource Affinity Table (SRAT).

Decode and dump the new Generic Initiator Affinity Structure.

Validate the Device Handle Type field inside the Generic Initiator
Affinity
Structure.

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
---

The changes can be seen at
https://github.com/KrzysztofKoch1/edk2/tree/582_acpiview_6_3_srat_v2

Notes:
v2:
- rebase on latest master [Krzysztof]

Readme.md | 4 +-
ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 33
+++
ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h | 16 +

ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratParser.
c
| 313 ++++++++++++++++++--
4 files changed, 343 insertions(+), 23 deletions(-)

diff --git a/Readme.md b/Readme.md
index
acbcca88d3c62d392e6f94b1ad7de2d8627e3a38..594f16b20756ab78987fef4fe
ac
2
e439743d5b4a 100644
--- a/Readme.md
+++ b/Readme.md
@@ -17,7 +17,7 @@ for the UEFI and PI specifications from www.uefi.org.
<tr>
<td>Windows</td>
<td>VS2019</td>
- <td>edk2-ci</td>
+ <td>master</td>
<td>
<a href="https://dev.azure.com/tianocore/edk2-
ci/_build/latest?definitionId=32&branchName=master">
<img
src="https://dev.azure.com/tianocore/edk2-ci/_apis/build/status/Windo
w s%20VS2019%20CI?branchName=master"/></a>
@@ -34,7 +34,7 @@ for the UEFI and PI specifications from www.uefi.org.
<tr>
<td>Ubuntu</td>
<td>GCC</td>
- <td>edk2-ci</td>
+ <td>master</td>
<td>
<a href="https://dev.azure.com/tianocore/edk2-
ci/_build/latest?definitionId=31&branchName=master">
<img
src="https://dev.azure.com/tianocore/edk2-ci/_apis/build/status/Ubunt
u %20GCC5%20CI?branchName=master"/></a>
diff --git
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index
a569c3c55406ab58536834e56ce9701f7edeffee..2b2ecb93cef9ee28b752e7bf2
d
92
0b059dbf7d6b 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -405,6 +405,39 @@ Dump8Chars (
);
}

+/**
+ This function traces 12 characters which can be optionally
+ formated using the format string if specified.
+
+ If no format string is specified the Format must be NULL.
+
+ @param [in] Format Optional format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+VOID
+EFIAPI
+Dump12Chars (
+ IN CONST CHAR16* Format OPTIONAL,
+ IN UINT8* Ptr
+ )
+{
+ Print (
+ (Format != NULL) ? Format : L"%c%c%c%c%c%c%c%c%c%c%c%c",
+ Ptr[0],
+ Ptr[1],
+ Ptr[2],
+ Ptr[3],
+ Ptr[4],
+ Ptr[5],
+ Ptr[6],
+ Ptr[7],
+ Ptr[8],
+ Ptr[9],
+ Ptr[10],
+ Ptr[11]
+ );
+}
+
/**
This function indents and prints the ACPI table Field Name.

diff --git
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
index
20ca358bddfa5953bfb1d1bebaebbf3079eaba01..0dc721bd2cc59538432d4a9c
a
b6c
21728cc77d33 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.h
@@ -184,6 +184,22 @@ Dump8Chars (
IN UINT8* Ptr
);

+/**
+ This function traces 12 characters which can be optionally
+ formated using the format string if specified.
+
+ If no format string is specified the Format must be NULL.
+
+ @param [in] Format Optional format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+VOID
+EFIAPI
+Dump12Chars (
+ IN CONST CHAR16* Format OPTIONAL,
+ IN UINT8* Ptr
+ );
+
/**
This function indents and prints the ACPI table Field Name.

diff --git
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratParse
r
.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratParse
r
.c index
a8aa420487bb6bf29fc38221d0b221573c64b8b3..d60476eb748e022f45d231e2
4c
32
b2b53e29bbd7 100644
---
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratParse
r
.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratP
+++ a
+++ rs
+++ er.c
@@ -5,7 +5,7 @@
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
- - ACPI 6.2 Specification - Errata A, September 2017
+ - ACPI 6.3 Specification - January 2019
**/

#include <IndustryStandard/Acpi.h>
@@ -17,6 +17,7 @@
// Local Variables
STATIC CONST UINT8* SratRAType;
STATIC CONST UINT8* SratRALength;
+STATIC CONST UINT8* SratDeviceHandleType;
STATIC ACPI_DESCRIPTION_HEADER_INFO AcpiHdrInfo;

/**
@@ -32,13 +33,52 @@ EFIAPI
ValidateSratReserved (
IN UINT8* Ptr,
IN VOID* Context
- )
-{
- if (*(UINT32*)Ptr != 1) {
- IncrementErrorCount ();
- Print (L"\nERROR: Reserved should be 1 for backward compatibility.\n");
- }
-}
+ );
+
+/**
+ This function validates the Device Handle Type field in the
+Generic Initiator
+ Affinity Structure.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateSratDeviceHandleType (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ );
+
+/**
+ This function traces the Device Handle field inside Generic
+Initiator
+ Affinity Structure.
+
+ @param [in] Format Format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+STATIC
+VOID
+EFIAPI
+DumpSratDeviceHandle (
+ IN CONST CHAR16* Format,
+ IN UINT8* Ptr
+ );
+
+/**
+ This function traces the PCI BDF Number field inside Device Handle
+- PCI
+
+ @param [in] Format Format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+STATIC
+VOID
+EFIAPI
+DumpSratPciBdfNumber (
+ IN CONST CHAR16* Format,
+ IN UINT8* Ptr
+ );

/**
This function traces the APIC Proximity Domain field.
@@ -52,14 +92,7 @@ EFIAPI
DumpSratApicProximity (
IN CONST CHAR16* Format,
IN UINT8* Ptr
- )
-{
- UINT32 ProximityDomain;
-
- ProximityDomain = Ptr[0] | (Ptr[1] << 8) | (Ptr[2] << 16);
-
- Print (Format, ProximityDomain);
-}
+ );

/**
An ACPI_PARSER array describing the SRAT Table.
@@ -103,6 +136,41 @@ STATIC CONST ACPI_PARSER
SratGicITSAffinityParser[] = {
{L"ITS Id", 4, 8, L"0x%x", NULL, NULL, NULL, NULL}, };

+/**
+ An ACPI_PARSER array describing the Generic Initiator Affinity
+Structure **/ STATIC CONST ACPI_PARSER
+SratGenericInitiatorAffinityParser[] = {
+ {L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"Length", 1, 1, L"0x%x", NULL, NULL, NULL, NULL},
+
+ {L"Reserved", 1, 2, L"0x%x", NULL, NULL, NULL, NULL}, {L"Device
+ Handle Type", 1, 3, L"%d", NULL,
(VOID**)&SratDeviceHandleType,
+ ValidateSratDeviceHandleType, NULL},
+ {L"Proximity Domain", 4, 4, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"Device Handle", 16, 8, L"%s", DumpSratDeviceHandle, NULL, NULL,
+NULL},
+ {L"Flags", 4, 24, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"Reserved", 4, 28, L"0x%x", NULL, NULL, NULL, NULL} };
+
+/**
+ An ACPI_PARSER array describing the Device Handle - ACPI **/
+STATIC CONST ACPI_PARSER SratDeviceHandleAcpiParser[] = {
+ {L"ACPI_HID", 8, 0, L"0x%lx", NULL, NULL, NULL, NULL},
+ {L"ACPI_UID", 4, 8, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"Reserved", 4, 12, L"0x%x", NULL, NULL, NULL, NULL} };
+
+/**
+ An ACPI_PARSER array describing the Device Handle - PCI **/ STATIC
+CONST ACPI_PARSER SratDeviceHandlePciParser[] = {
+ {L"PCI Segment", 2, 0, L"0x%x", NULL, NULL, NULL, NULL},
+ {L"PCI BDF Number", 2, 2, NULL, DumpSratPciBdfNumber, NULL, NULL,
+NULL},
+ {L"Reserved", 12, 4, L"%x %x %x %x - %x %x %x %x - %x %x %x %x",
Dump12Chars,
+ NULL, NULL, NULL}
+};
+
/**
An ACPI_PARSER array describing the Memory Affinity structure.
**/
@@ -152,6 +220,190 @@ STATIC CONST ACPI_PARSER
SratX2ApciAffinityParser[] = {
{L"Reserved", 4, 20, L"0x%x", NULL, NULL, NULL, NULL} };

+/**
+ This function validates the Reserved field in the SRAT table header.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateSratReserved (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ )
+{
+ if (*(UINT32*)Ptr != 1) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Reserved should be 1 for backward
+compatibility.\n");
+ }
+}
+
+/**
+ This function validates the Device Handle Type field in the
+Generic Initiator
+ Affinity Structure.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateSratDeviceHandleType (
+ IN UINT8* Ptr,
+ IN VOID* Context
+ )
+{
+ UINT8 DeviceHandleType;
+
+ DeviceHandleType = *Ptr;
+
+ if (DeviceHandleType > EFI_ACPI_6_3_PCI_DEVICE_HANDLE) {
+ IncrementErrorCount ();
+ Print (
+ L"\nERROR: Invalid Device Handle Type: %d. Must be between 0
and %d.",
+ DeviceHandleType,
+ EFI_ACPI_6_3_PCI_DEVICE_HANDLE
+ );
+ }
+}
+
+/**
+ This function traces the Device Handle field inside Generic
+Initiator
+ Affinity Structure.
+
+ @param [in] Format Format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+STATIC
+VOID
+EFIAPI
+DumpSratDeviceHandle (
+ IN CONST CHAR16* Format,
+ IN UINT8* Ptr
+ )
+{
+ if (SratDeviceHandleType == NULL) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Device Handle Type read incorrectly.\n");
+ return;
+ }
+
+ Print (L"\n");
+
+ if (*SratDeviceHandleType == EFI_ACPI_6_3_ACPI_DEVICE_HANDLE) {
+ ParseAcpi (
+ TRUE,
+ 2,
+ NULL,
+ Ptr,
+ sizeof (EFI_ACPI_6_3_DEVICE_HANDLE_ACPI),
+ PARSER_PARAMS (SratDeviceHandleAcpiParser)
+ );
+ } else if (*SratDeviceHandleType ==
+ EFI_ACPI_6_3_PCI_DEVICE_HANDLE)
{
+ ParseAcpi (
+ TRUE,
+ 2,
+ NULL,
+ Ptr,
+ sizeof (EFI_ACPI_6_3_DEVICE_HANDLE_PCI),
+ PARSER_PARAMS (SratDeviceHandlePciParser)
+ );
+ }
+}
+
+/**
+ This function traces the PCI BDF Number field inside Device Handle
+- PCI
+
+ @param [in] Format Format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+STATIC
+VOID
+EFIAPI
+DumpSratPciBdfNumber (
+ IN CONST CHAR16* Format,
+ IN UINT8* Ptr
+ )
+{
+ CHAR16 Buffer[OUTPUT_FIELD_COLUMN_WIDTH];
+
+ Print (L"\n");
+
+ /*
+ The PCI BDF Number subfields are printed in the order specified
+ in the
ACPI
+ specification. The format of the 16-bit PCI BDF Number field is as follows:
+
+ +-----+------+------+
+ |DEV | FUNC | BUS |
+ +-----+------+------+
+ |15:11| 10:8 | 7:0 |
+ +-----+------+------+
+ */
+
+ // Print PCI Bus Number (Bits 7:0 of Byte 2) UnicodeSPrint (
+ Buffer,
+ sizeof (Buffer),
+ L"PCI Bus Number"
+ );
+ PrintFieldName (4, Buffer);
+ Print (
+ L"0x%x\n",
+ *Ptr
+ );
+
+ Ptr++;
+
+ // Print PCI Device Number (Bits 7:3 of Byte 3) UnicodeSPrint (
+ Buffer,
+ sizeof (Buffer),
+ L"PCI Device Number"
+ );
+ PrintFieldName (4, Buffer);
+ Print (
+ L"0x%x\n",
+ (*Ptr & (BIT7 | BIT6 | BIT5 | BIT4 | BIT3)) >> 3
+ );
+
+ // PCI Function Number (Bits 2:0 of Byte 3)
+ UnicodeSPrint (
+ Buffer,
+ sizeof (Buffer),
+ L"PCI Function Number"
+ );
+ PrintFieldName (4, Buffer);
+ Print (
+ L"0x%x\n",
+ *Ptr & (BIT2 | BIT1 | BIT0)
+ );
+}
+
+/**
+ This function traces the APIC Proximity Domain field.
+
+ @param [in] Format Format string for tracing the data.
+ @param [in] Ptr Pointer to the start of the buffer.
+**/
+STATIC
+VOID
+EFIAPI
+DumpSratApicProximity (
+ IN CONST CHAR16* Format,
+ IN UINT8* Ptr
+ )
+{
+ UINT32 ProximityDomain;
+
+ ProximityDomain = Ptr[0] | (Ptr[1] << 8) | (Ptr[2] << 16);
+
+ Print (Format, ProximityDomain);
+}
+
/**
This function parses the ACPI SRAT table.
When trace is enabled this function parses the SRAT table and @@
-183,6
+435,7 @@ ParseAcpiSrat (
UINT8* ResourcePtr;
UINT32 GicCAffinityIndex;
UINT32 GicITSAffinityIndex;
+ UINT32 GenericInitiatorAffinityIndex;
UINT32 MemoryAffinityIndex;
UINT32 ApicSapicAffinityIndex;
UINT32 X2ApicAffinityIndex;
@@ -190,6 +443,7 @@ ParseAcpiSrat (

GicCAffinityIndex = 0;
GicITSAffinityIndex = 0;
+ GenericInitiatorAffinityIndex = 0;
MemoryAffinityIndex = 0;
ApicSapicAffinityIndex = 0;
X2ApicAffinityIndex = 0;
@@ -232,7 +486,7 @@ ParseAcpiSrat (
}

switch (*SratRAType) {
- case EFI_ACPI_6_2_GICC_AFFINITY:
+ case EFI_ACPI_6_3_GICC_AFFINITY:
AsciiSPrint (
Buffer,
sizeof (Buffer),
@@ -249,7 +503,7 @@ ParseAcpiSrat (
);
break;

- case EFI_ACPI_6_2_GIC_ITS_AFFINITY:
+ case EFI_ACPI_6_3_GIC_ITS_AFFINITY:
AsciiSPrint (
Buffer,
sizeof (Buffer),
@@ -266,7 +520,24 @@ ParseAcpiSrat (
);
break;

- case EFI_ACPI_6_2_MEMORY_AFFINITY:
+ case EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY:
+ AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "Generic Initiator Affinity Structure [%d]",
+ GenericInitiatorAffinityIndex++
+ );
+ ParseAcpi (
+ TRUE,
+ 2,
+ Buffer,
+ ResourcePtr,
+ *SratRALength,
+ PARSER_PARAMS (SratGenericInitiatorAffinityParser)
+ );
+ break;
+
+ case EFI_ACPI_6_3_MEMORY_AFFINITY:
AsciiSPrint (
Buffer,
sizeof (Buffer),
@@ -283,7 +554,7 @@ ParseAcpiSrat (
);
break;

- case EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY:
+ case EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY:
AsciiSPrint (
Buffer,
sizeof (Buffer),
@@ -300,7 +571,7 @@ ParseAcpiSrat (
);
break;

- case EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY:
+ case EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY:
AsciiSPrint (
Buffer,
sizeof (Buffer),
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'