Date   
Re: [Patch 12/12] OvmfPkg SecMain: Add build option "-fno-omit-frame-pointer" for CLANG9 X64

Laszlo Ersek
 

On 10/11/19 03:30, Liming Gao wrote:
Laszlo:

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@...]
Sent: Friday, October 11, 2019 1:35 AM
To: devel@edk2.groups.io; Gao, Liming <liming.gao@...>; Justen,
Jordan L <jordan.l.justen@...>
Subject: Re: [edk2-devel] [Patch 12/12] OvmfPkg SecMain: Add build option "-
fno-omit-frame-pointer" for CLANG9 X64

Hi Liming,

On 10/10/19 16:08, Liming Gao wrote:
Laszlo:
Option (a) works. Jordan patch can fix this issue.
Option (b) doesn't work. Even if disable optimization, CLANG doesn't
generate the code with push rbp & pop rbp.

So, Jordan patch becomes only option. We can discuss this topic again. But,
I don't think this is the block issue
to add new CLANG9 tool chain. I will try to add CLANG9 tool chain patch
without this change, and use BZ 2024 to track this issue.

not sure I understand you correctly.

- If you intend to drop this patch from the series, and enable CLANG9
for edk2 without enabling it for OvmfPkg specifically (for the time
being), that's fine with me.
I mean to drop this patch from this patch set. I will use BZ 2024 to track this issue.
Without this fix, CLANG9 OVMF X64 boot will hang. CLANG9 OVMF Ia32 and Ia32X64 boots fine.
OK, thank you.
Laszlo

- If you'd like to push this patch first, and work on the general PEI
Core issue second, then I defer to Jordan for reviewing this patch. I'd
like to neither approve nor reject this patch myself, in that case.

Thanks
Laszlo

Re: [PATCH v1 1/1] NetworkPkg/SnpDxe: Remove ExitBootServices event

Laszlo Ersek
 

On 10/11/19 02:14, Fu, Siyuan wrote:
-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: 2019年10月11日 0:06
To: Fu, Siyuan <@sfu5>; devel@edk2.groups.io; Rabeda,
Maciej <maciej.rabeda@...>
Cc: Wu, Jiaxin <jiaxin.wu@...>
Subject: Re: [edk2-devel] [PATCH v1 1/1] NetworkPkg/SnpDxe: Remove
ExitBootServices event

On 10/10/19 11:29, Fu, Siyuan wrote:
-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: 2019年10月10日 16:06
To: Fu, Siyuan <@sfu5>; devel@edk2.groups.io; Rabeda,
Maciej <maciej.rabeda@...>
Cc: Wu, Jiaxin <jiaxin.wu@...>
Subject: Re: [edk2-devel] [PATCH v1 1/1] NetworkPkg/SnpDxe: Remove
ExitBootServices event

On 10/10/19 05:32, Fu, Siyuan wrote:
Hi, Maciej

Considering that this patch has to co-work with corresponding UNDI
device
driver
bug fix, in order to avoid potential compatibility problem, please add a
PCD
to
NetworkPkg for this fix, and set the default value to disable state (no
behavior
change). The platform which need this fix could set the PCD to enable in
its
platform DSC.
Should the new PCD go into "NetworkPkg/NetworkPcds.dsc.inc", and be
gated with a new build flag defined in
"NetworkPkg/NetworkDefines.dsc.inc"?

Currently not all the network package PCDs are listed in the
NetworkPcds.dsc.inc,
But I do not oppose it if you think this PCD should be controlled by a build
flag.

I mainly asked from a consistency point of view.

The inclusion of SnpDxe is already controlled by NETWORK_SNP_ENABLE, at
least in platforms that utilize the NetworkPkg *.inc files. And the PCD
in question would control the behavior of SnpDxe at ExitBootServices(),
if I understand correctly.

This is similar to NETWORK_HTTP_BOOT_ENABLE and
NETWORK_ALLOW_HTTP_CONNECTIONS:
- The former includes HttpDxe and HttpBootDxe (and some other drivers).
- The latter controls PcdAllowHttpConnections, which is consumed by
HttpDxe and HttpBootDxe.

I don't feel too strongly about it, I just thought it worth raising.
It's not an existing "consistency" in current network package. The current macros
are mostly used for control more high level feature enable/disable, not such kind
of bug fix,
For example, NETWORK_ISCSI_ENABLE includes IScsiDxe driver, while
PcdIScsiAIPNetworkBootPolicy is consumed by IScsiDriver, but not controlled by
a macro. And also other PXE, DHCP and PXE related PCDs.
Good point!

So, I'm fine if the new feature PCD is not exposed with a build flag.

Thanks
Laszlo

Re: [Patch 11/12] OvmfPkg: Enable CLANG9 tool chain

Laszlo Ersek
 

Hi Liming,

On 10/09/19 16:44, Gao, Liming wrote:

The difference between XCODE/CLANG and GCCXX is the linker. Current
patches are introduced for the different linker. Clang supports most
usage of GCC compiler. So, CLANG and XCODE uses GCC family. When I
enable XCODE or CLANG tool chain in the platform, I don't find other
incompatible behavior with GCC compiler. So, I think it is safe to let
CLANG inherit GCC option except for these two cases. When you make new
changes, and verify them with GCC compiler, that's enough. You don't
need to specially verify them with XCODE or CLANG. In most case, GCC
compiler pass, XCODE or CLANG can also pass.
I'd like to provide a counter-example for this.

Consider the issue that Tom reported, at

http://mid.mail-archive.com/8eb55d97-0ba3-c217-a160-c24730b9f036@...
https://edk2.groups.io/g/devel/message/48762

in point (2).

(Both links point to the same message, just in different archives.)

Let me summarize that problem.

- In BZ#849, an XCODE toolchain bug was reported, and a workaround was
requested.

- The workaround was commit 2db0ccc2d7fe ("UefiCpuPkg: Update
CpuExceptionHandlerLib pass XCODE5 tool chain", 2018-01-16).

- The workaround is binary patching (self-modification) in the exception
handler's assembly code.

- Unfortunately, this code is also linked into SEC modules, which run
from flash. Therefore, self-modification is not permitted, and the
workaround is not good enough for SEC. (Nor for PEI modules that run
from flash.)

Now, let's consider how we could mitigate this issue for *temporarily*,
for all toolchains *except* XCODE5, until the issue is fixed. Clearly,
toolchains other than XCODE5 have no problems with the original assembly
code (i.e., with the 64-bit absolute address relocations). Therefore, we
could consider reverting the commit, and capturing the results of the
revert in a *separate* NASM source file. This source file (that is, the
original, pre-2db0ccc2d7fe assembly code) would apply to all toolchain
families, except the XCODE family.

Let's say the new NASM source files would be called
- X64/ExceptionHandlerAsmGeneric.nasm -- all except XCODE,
- X64/ExceptionHandlerAsmXcode.nasm -- XCODE,

replacing the current file

- X64/ExceptionHandlerAsm.nasm

So, how can we use the new files, in the INF file

UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf

?

We could attempt,

[Sources.X64]
X64/ExceptionHandlerAsmGeneric.nasm | GCC
X64/ExceptionHandlerAsmXcode.nasm | XCODE
X64/ExceptionHandlerAsmGeneric.nasm | INTEL
X64/ExceptionHandlerAsmGeneric.nasm | MSFT
Unfortunately, this does not work.

While it solves the issue on GCC, INTEL and MSFT, it breaks on XCODE:
XCODE picks up *both* the GCC line and the XCODE line. And that's
because XCODE inherits GCC, and there is presently no way to express
"real GCC only".

But, at least, this suggests a solution too. In
"BaseTools/Conf/tools_def.template", for *every* toolchain that
specifies FAMILY=GCC, we should spell out an explicit BUILDRULEFAMILY.
Like this:

@@ -1995,6 +1995,7 @@
#
####################################################################################
*_GCC48_*_*_FAMILY = GCC
+*_GCC48_*_*_BUILDRULEFAMILY = GENUINE_GCC

*_GCC48_*_MAKE_PATH = DEF(GCC_HOST_PREFIX)make
*_GCC48_*_*_DLL = ENV(GCC48_DLL)
@@ -2134,6 +2135,7 @@
#
####################################################################################
*_GCC49_*_*_FAMILY = GCC
+*_GCC49_*_*_BUILDRULEFAMILY = GENUINE_GCC

*_GCC49_*_MAKE_PATH = DEF(GCC_HOST_PREFIX)make
*_GCC49_*_*_DLL = ENV(GCC49_DLL)
@@ -2280,6 +2282,7 @@
#
####################################################################################
*_GCC5_*_*_FAMILY = GCC
+*_GCC5_*_*_BUILDRULEFAMILY = GENUINE_GCC

*_GCC5_*_MAKE_PATH = DEF(GCC_HOST_PREFIX)make
*_GCC5_*_*_DLL = ENV(GCC5_DLL)
@@ -2437,6 +2440,7 @@
#
####################################################################################
*_CLANG35_*_*_FAMILY = GCC
+*_CLANG35_*_*_BUILDRULEFAMILY = CLANG

*_CLANG35_*_MAKE_PATH = make
*_CLANG35_*_*_DLL = ENV(CLANG35_DLL)
@@ -2517,6 +2521,8 @@
#
####################################################################################
*_CLANG38_*_*_FAMILY = GCC
+*_CLANG38_*_*_BUILDRULEFAMILY = CLANG
+
*_CLANG38_*_MAKE_PATH = make
*_CLANG38_*_*_DLL = ENV(CLANG38_DLL)
*_CLANG38_*_ASL_PATH = DEF(UNIX_IASL_BIN)
And then we could write:

[Sources.X64]
X64/ExceptionHandlerAsmGeneric.nasm | GENUINE_GCC
X64/ExceptionHandlerAsmGeneric.nasm | CLANG
X64/ExceptionHandlerAsmXcode.nasm | XCODE
X64/ExceptionHandlerAsmGeneric.nasm | INTEL
X64/ExceptionHandlerAsmGeneric.nasm | MSFT
replacing plain "GCC", which XCODE inherits, with "GENUINE_GCC" and
"CLANG", neither of which XCODE inherits.

Would you accept the above patch, for
"BaseTools/Conf/tools_def.template"?

Thanks,
Laszlo

Re: [RFC PATCH v2 38/44] UefiCpuPkg: Allow AP booting under SEV-ES

Laszlo Ersek
 

On 10/11/19 01:17, Lendacky, Thomas wrote:
On 10/3/19 10:12 AM, Tom Lendacky wrote:


On 10/3/19 5:32 AM, Laszlo Ersek wrote:
On 10/03/19 12:12, Laszlo Ersek wrote:

UINT32 ApEntryPoint;
EFI_GUID SevEsFooterGuid;
UINT16 Size;
It's probably better to reverse the order of "Size" and
"SevEsFooterGuid", like this:

UINT32 ApEntryPoint;
UINT16 Size;
EFI_GUID SevEsFooterGuid;

because then even the "Size" field can be changed (or resized), as a
function of the footer GUID.
Cool, I'll look into doing this and see how it works out.
Just an update on this idea. This has worked out well, but has a couple of
caveats. Removing the Qemu change to make the flash mapped read-only in
the nested page tables, caused the following:

1. QemuFlashDetected() will attempt to detect how the flash memory device
behaves. Because it is marked as read-only by the hypervisor, writing
to the area results in a #NPF for the write-fault. With SEV-ES,
emulation of the instruction can't be performed (can't read guest
memory and not provided the faulting instruction bytes), so the vCPU is
just restarted. This results in an infinite #NPF occurring.

The solution here was to check for SEV-ES being enabled and just return
false from QemuFlashDetected(). Any downfalls to doing that?
Short-circuiting QemuFlashDetected() on SEV-ES seems appropriate.

However, I don't understand why you return FALSE in that case. You
should return TRUE. If QemuFlashDetected() returns FALSE, then the UEFI
variable store will not be backed by the real pflash chip, it will be
emulated with an \NvVars file on the EFI system partition. That
emulation should really not be used nowadays.

So IMO the right approach here is:
- declare that SEV-ES only targets the "two pflash chips" setup
- return TRUE from QemuFlashDetected() when SEV-ES is on.


2. Commit 2db0ccc2d7fe ("UefiCpuPkg: Update CpuExceptionHandlerLib pass
XCODE5 tool chain") causes a similar situation to #1. It attempts to do
some address fixups and write to the flash device.
That's... stunning.

Commit 2db0ccc2d7fe changes the file

UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm

such that it does in-place binary patching.

This source file is referenced from:

UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf

as well. Note "SecPei".

That makes the commit buggy, to my eyes, regardless of SEV-ES. Because:

The binary patching appears to occur in the SEC phase as well, i.e. at a
time when the exception handler is located in flash. That's incorrect on
physical hardware too.

Upon re-reading <https://bugzilla.tianocore.org/show_bug.cgi?id=849>,
this commit worked around an XCODE toolchain bug.

Unfortunately, the workaround is not suitable for the SEC phase. (Also
not suitable for the PEI phase, for such PEIMs that still execute from
flash.)

Please open a new bug for UefiCpuPkg in the TianoCore Bugzilla,
reference BZ#849 in the See Also field, and please also make the new bug
block BZ#2198.

(I'll comment on this issue in a different thread too; I'll CC you on it.)

Reverting that commit fixes the issue. I don't think that will be an
acceptable solution, though, so need to think about what to do here.

After those two changes, the above method works well.
I'm happy to hear!

Thanks,
Laszlo

Re: [PATCH v2 2/2] UefiCpuPkg/MpInitLib: honor the platform's boot CPU count in AP detection

Ni, Ray
 

Laszlo, the comments couldn't be better! Thanks!!

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: Thursday, October 10, 2019 7:30 PM
To: edk2-devel-groups-io <devel@edk2.groups.io>
Cc: Dong, Eric <eric.dong@...>; Ni, Ray <ray.ni@...>
Subject: [PATCH v2 2/2] UefiCpuPkg/MpInitLib: honor the platform's boot
CPU count in AP detection

- If a platform boots such that the boot CPU count is smaller than
PcdCpuMaxLogicalProcessorNumber, then the platform cannot use the
"fast
AP detection" logic added in commit 6e1987f19af7. (Which has been
documented as a subset of use case (2) in the previous patch.)

Said logic depends on the boot CPU count being equal to
PcdCpuMaxLogicalProcessorNumber. If the equality does not hold, the
platform either has to wait too long, or risk missing APs due to an
early timeout.

- The platform may not be able to use the variant added in commit
0594ec417c89 either. (Which has been documented as use case (1) in the
previous patch.)

See commit 861218740d6d. When OVMF runs on QEMU/KVM, APs may
check in
with the BSP in arbitrary order, plus the individual AP may take
arbitrarily long to check-in. If "NumApsExecuting" falls to zero
mid-enumeration, APs will be missed.

Allow platforms to specify the exact boot CPU count, independently of
PcdCpuMaxLogicalProcessorNumber. In this mode, the BSP waits for all APs
to check-in regardless of timeout. If at least one AP fails to check-in, then the
AP enumeration hangs forever. That is the desired behavior when the exact
boot CPU count is known in advance. (A hung boot is better than an AP
checking-in after timeout, and executing code from released
storage.)

Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515
Signed-off-by: Laszlo Ersek <lersek@...>
---

Notes:
v2:
- update commit message
- update docs in DEC file
- add code comments
- no functional changes

UefiCpuPkg/UefiCpuPkg.dec | 13 +++
UefiCpuPkg/UefiCpuPkg.uni | 4 +
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 +
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 3 +-
UefiCpuPkg/Library/MpInitLib/MpLib.c | 99 ++++++++++++--------
5 files changed, 80 insertions(+), 40 deletions(-)

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 031a2ccd680a..12f4413ea5b0 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -227,6 +227,19 @@ [PcdsFixedAtBuild, PcdsPatchableInModule,
PcdsDynamic, PcdsDynamicEx]
## Specifies timeout value in microseconds for the BSP to detect all APs for
the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.

gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|
UINT32|0x00000004
+ ## Specifies the number of Logical Processors that are available in
+ the # preboot environment after platform reset, including BSP and
+ APs. Possible # values:<BR><BR> # zero (default) -
+ PcdCpuBootLogicalProcessorNumber is ignored, and
+ # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
+ # detection by the BSP.<BR>
+ # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The
initial
+ # AP detection finishes only when the detected CPU count
+ # (BSP plus APs) reaches the value of
+ # PcdCpuBootLogicalProcessorNumber, regardless of how long
+ # that takes.<BR>
+ # @Prompt Number of Logical Processors available after platform reset.
+
+
gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT
32|0x
+ 00000008
## Specifies the base address of the first microcode Patch in the microcode
Region.
# @Prompt Microcode Region base address.

gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|
0x00000005
diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index
fbf768072668..a7e279c5cb14 100644
--- a/UefiCpuPkg/UefiCpuPkg.uni
+++ b/UefiCpuPkg/UefiCpuPkg.uni
@@ -37,6 +37,10 @@

#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApInitTimeOutInMicroSeconds_
HELP #language en-US "Specifies timeout value in microseconds for the BSP
to detect all APs for the first time."

+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_PR
OMPT #language en-US "Number of Logical Processors available after
platform reset."
+
+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_HE
LP #language en-US "Specifies the number of Logical Processors that are
available in the preboot environment after platform reset, including BSP and
APs."
+
#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_PROMP
T #language en-US "Microcode Region base address."

#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_HELP
#language en-US "Specifies the base address of the first microcode Patch in
the microcode Region."
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index 37b3f64e578a..cd912ab0c5ee 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -61,6 +61,7 @@ [Guids]

[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ##
CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ##
SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
CONSUMES
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
index 82b77b63ea87..1538185ef99a 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -53,7 +53,8 @@ [LibraryClasses]

[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ##
CONSUMES
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ##
CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber ##
CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ##
SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ##
CONSUMES
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 594a035d8b92..622b70ca3c4e 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1044,46 +1044,67 @@ WakeUpAP (
SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart);
}
if (CpuMpData->InitFlag == ApInitConfig) {
- //
- // The AP enumeration algorithm below is suitable for two use cases.
- //
- // (1) The check-in time for an individual AP is bounded, and APs run
- // through their initialization routines strongly concurrently. In
- // particular, the number of concurrently running APs
- // ("NumApsExecuting") is never expected to fall to zero
- // *temporarily* -- it is expected to fall to zero only when all
- // APs have checked-in.
- //
- // In this case, the platform is supposed to set
- // PcdCpuApInitTimeOutInMicroSeconds to a low-ish value (just long
- // enough for one AP to start initialization). The timeout will be
- // reached soon, and remaining APs are collected by watching
- // NumApsExecuting fall to zero. If NumApsExecuting falls to zero
- // mid-process, while some APs have not completed initialization,
- // the behavior is undefined.
- //
- // (2) The check-in time for an individual AP is unbounded, and/or APs
- // may complete their initializations widely spread out. In
- // particular, some APs may finish initialization before some APs
- // even start.
- //
- // In this case, the platform is supposed to set
- // PcdCpuApInitTimeOutInMicroSeconds to a high-ish value. The AP
- // enumeration will always take that long (except when the boot CPU
- // count happens to be maximal, that is,
- // PcdCpuMaxLogicalProcessorNumber). All APs are expected to
- // check-in before the timeout, and NumApsExecuting is assumed zero
- // at timeout. APs that miss the time-out may cause undefined
- // behavior.
- //
- TimedWaitForApFinish (
- CpuMpData,
- PcdGet32 (PcdCpuMaxLogicalProcessorNumber) - 1,
- PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds)
- );
+ if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {
+ //
+ // The AP enumeration algorithm below is suitable only when the
+ // platform can tell us the *exact* boot CPU count in advance.
+ //
+ // The wait below finishes only when the detected AP count reaches
+ // (PcdCpuBootLogicalProcessorNumber - 1), regardless of how long
that
+ // takes. If at least one AP fails to check in (meaning a platform
+ // hardware bug), the detection hangs forever, by design. If the actual
+ // boot CPU count in the system is higher than
+ // PcdCpuBootLogicalProcessorNumber (meaning a platform
+ // misconfiguration), then some APs may complete initialization after
+ // the wait finishes, and cause undefined behavior.
+ //
+ TimedWaitForApFinish (
+ CpuMpData,
+ PcdGet32 (PcdCpuBootLogicalProcessorNumber) - 1,
+ MAX_UINT32 // approx. 71 minutes
+ );
+ } else {
+ //
+ // The AP enumeration algorithm below is suitable for two use cases.
+ //
+ // (1) The check-in time for an individual AP is bounded, and APs run
+ // through their initialization routines strongly concurrently. In
+ // particular, the number of concurrently running APs
+ // ("NumApsExecuting") is never expected to fall to zero
+ // *temporarily* -- it is expected to fall to zero only when all
+ // APs have checked-in.
+ //
+ // In this case, the platform is supposed to set
+ // PcdCpuApInitTimeOutInMicroSeconds to a low-ish value (just long
+ // enough for one AP to start initialization). The timeout will be
+ // reached soon, and remaining APs are collected by watching
+ // NumApsExecuting fall to zero. If NumApsExecuting falls to zero
+ // mid-process, while some APs have not completed initialization,
+ // the behavior is undefined.
+ //
+ // (2) The check-in time for an individual AP is unbounded, and/or APs
+ // may complete their initializations widely spread out. In
+ // particular, some APs may finish initialization before some APs
+ // even start.
+ //
+ // In this case, the platform is supposed to set
+ // PcdCpuApInitTimeOutInMicroSeconds to a high-ish value. The AP
+ // enumeration will always take that long (except when the boot CPU
+ // count happens to be maximal, that is,
+ // PcdCpuMaxLogicalProcessorNumber). All APs are expected to
+ // check-in before the timeout, and NumApsExecuting is assumed
zero
+ // at timeout. APs that miss the time-out may cause undefined
+ // behavior.
+ //
+ TimedWaitForApFinish (
+ CpuMpData,
+ PcdGet32 (PcdCpuMaxLogicalProcessorNumber) - 1,
+ PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds)
+ );

- while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {
- CpuPause();
+ while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {
+ CpuPause();
+ }
}
} else {
//
--
2.19.1.3.g30247aa5d201

Re: [PATCH v2 1/2] UefiCpuPkg/MpInitLib: expand comment on initial AP enumeration

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: Laszlo Ersek <lersek@...>
Sent: Thursday, October 10, 2019 7:30 PM
To: edk2-devel-groups-io <devel@edk2.groups.io>
Cc: Dong, Eric <eric.dong@...>; Ni, Ray <ray.ni@...>
Subject: [PATCH v2 1/2] UefiCpuPkg/MpInitLib: expand comment on initial
AP enumeration

Before adding another AP enumeration mode, clarify the documentation on
the current logic. No functional changes.

Cc: Eric Dong <eric.dong@...>
Cc: Ray Ni <ray.ni@...>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515
Signed-off-by: Laszlo Ersek <lersek@...>
---

Notes:
v2:
- new patch

UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++++++++++++++-----
1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index d6f84c6f45c0..594a035d8b92 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1045,14 +1045,36 @@ WakeUpAP (
}
if (CpuMpData->InitFlag == ApInitConfig) {
//
- // Here support two methods to collect AP count through adjust
- // PcdCpuApInitTimeOutInMicroSeconds values.
- //
- // one way is set a value to just let the first AP to start the
- // initialization, then through the later while loop to wait all Aps
- // finsh the initialization.
- // The other way is set a value to let all APs finished the initialzation.
- // In this case, the later while loop is useless.
+ // The AP enumeration algorithm below is suitable for two use cases.
+ //
+ // (1) The check-in time for an individual AP is bounded, and APs run
+ // through their initialization routines strongly concurrently. In
+ // particular, the number of concurrently running APs
+ // ("NumApsExecuting") is never expected to fall to zero
+ // *temporarily* -- it is expected to fall to zero only when all
+ // APs have checked-in.
+ //
+ // In this case, the platform is supposed to set
+ // PcdCpuApInitTimeOutInMicroSeconds to a low-ish value (just long
+ // enough for one AP to start initialization). The timeout will be
+ // reached soon, and remaining APs are collected by watching
+ // NumApsExecuting fall to zero. If NumApsExecuting falls to zero
+ // mid-process, while some APs have not completed initialization,
+ // the behavior is undefined.
+ //
+ // (2) The check-in time for an individual AP is unbounded, and/or APs
+ // may complete their initializations widely spread out. In
+ // particular, some APs may finish initialization before some APs
+ // even start.
+ //
+ // In this case, the platform is supposed to set
+ // PcdCpuApInitTimeOutInMicroSeconds to a high-ish value. The AP
+ // enumeration will always take that long (except when the boot CPU
+ // count happens to be maximal, that is,
+ // PcdCpuMaxLogicalProcessorNumber). All APs are expected to
+ // check-in before the timeout, and NumApsExecuting is assumed zero
+ // at timeout. APs that miss the time-out may cause undefined
+ // behavior.
//
TimedWaitForApFinish (
CpuMpData,
--
2.19.1.3.g30247aa5d201

Re: [edk2-platforms: PATCH v3 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD

Marcin Wojtas
 

Leif,

pt., 11 paź 2019 o 09:30 Marcin Wojtas <mw@...> napisał(a):

Hi Leif,

pt., 11 paź 2019 o 01:51 Leif Lindholm <leif.lindholm@...> napisał(a):

On Fri, Oct 11, 2019 at 01:33:49AM +0200, Marcin Wojtas wrote:
Hi Leif,

pt., 11 paź 2019 o 01:04 Leif Lindholm <leif.lindholm@...> napisał(a):

On Thu, Oct 10, 2019 at 07:42:18AM +0200, Marcin Wojtas wrote:
From: Patryk Duda <pdk@...>

This patch implements convenient way of changing strings included
in SMBIOS Table1, Table2, Table3.

Strings can be altered by defining following PCDs:
gMarvellTokenSpaceGuid.PcdProductManufacturer
gMarvellTokenSpaceGuid.PcdProductPlatformName
gMarvellTokenSpaceGuid.PcdProductVersion
gMarvellTokenSpaceGuid.PcdProductSerial

This patch adds also limit for length of string which can be increased
if necessary in future.

Signed-off-by: Patryk Duda <pdk@...>
---
Silicon/Marvell/Marvell.dec | 6 ++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 4 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 79 +++++++++++++++++---
3 files changed, 78 insertions(+), 11 deletions(-)

diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index d337d3e..a84b056 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -169,6 +169,12 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035

+#Platform description
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell \0"|VOID*|0x50000100
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board \0"|VOID*|0x50000101
+ gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set \0"|VOID*|0x50000103
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown \0"|VOID*|0x50000102
+
I'm not too pleased about this random number of spaces. I'm cool with
the strings, but they should be treated as such, not magical data
structures.
In v4 the trailing spaces will be removed from the defaults (as well as "\0").

+STATIC
+VOID
+MvSmbiosCopyStrings (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductManufacturer),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductPlatformName),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductVersion),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductSerial),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
Especially given the current design, these ASSERTs seem a bit
... unhelpful. In fact, this whole MAX_SIZE thing seems ... restricted
by the implementation, not by external constraints. What is the
benefit? Not having to do a bunch of pointer conversions at
SetVirtualAddressMap?
The default static tables require constant initializers and the
placeholders should have some predefined size in current approach. So
max of 32 characters was picked and with the asserts, ensuring the
user will not exceed it. Do you think they should be removed?
Oh, you're saying this is basically "TO BE FILLED BY OEM"?
*yurgh*.

I still say it's horrible, but not more horrible than most existing
platforms. Nevertheless, the arbitrary size should be something
defined by the code generating the tables - it shouldn't depend on
what's in the .dec (or more usefully, the .dsc).

I also feel that if it is effectively "TO BE FILLED BY OEM", it would
be better if it said that than something that looks like it may be
proper names.

I would also prefer a compilation failure over an ASSERT if the string
ended up not fitting.
I think I found a solution to remove any fixed size constraint and asserts:
STATIC CHAR8 mSysInfoManufacturer[sizeof ((CHAR8 *)PcdGetPtr
(PcdProductManufacturer))];
STATIC CHAR8 mSysInfoProductName[sizeof ((CHAR8 *)PcdGetPtr
(PcdProductPlatformName))];
STATIC CHAR8 mSysInfoVersion[sizeof ((CHAR8 *)PcdGetPtr (PcdProductVersion))];
STATIC CHAR8 mSysInfoSerial[sizeof ((CHAR8 *)PcdGetPtr (PcdProductSerial))];
Compilation test was not enough, please ignore my previous email - I
have to find out something better :)

Best regards,
Marcin




+
+ Status = AsciiStrCpyS (mSysInfoManufacturer,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductManufacturer));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoProductName,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductPlatformName));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoVersion,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductVersion));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoSerial,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductSerial));
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
Install all structures from the DefaultTables structure

@param Smbios SMBIOS protocol
@@ -760,6 +815,8 @@ SmbiosInstallAllStructures (
FirmwareMajorRevisionNumber = (PcdGet32 (PcdFirmwareRevision) >> 16) & 0xFF;
FirmwareMinorRevisionNumber = PcdGet32 (PcdFirmwareRevision) & 0xFF;

+ MvSmbiosCopyStrings();
+
//
// Update Firmware Revision, CPU and DRAM frequencies.
//
--
2.7.4

Re: [PATCH v1 0/4] Support HTTPS HostName validation feature(CVE-2019-14553)

Wu, Jiaxin
 

I'm surprising my detailed and patient explanation become a poor excuses! If you think there is anything wrong with my explanation, please correct me instead of blaming directly.

I think I have *repeated* several times that we are targeting to fix
the HostName validation issue, not the IP or email address. *But*
even so, the series patches for UEFI TLS is also allowable to
specify IP as host name for CN or dNSName of SAN in the certificate.
That's why I said "if the CN or SAN in the certificate are set
correctly, it should be OK to pass the verification". The failure you
mentioned here is to set the IP in iPAddress of SAN, I agree it's the
routine and suggested setting, *but* obviously, it's not the target
we are supported according the implementation/description of
TlsSetVerifyHost. We are targeting to the hostname verification, and
meanwhile compatible with the IP in the URI (But need the *correct*
certificate setting).

IP addresses stored in the DNS names and CN are of cause ignored by
X509_check_ip & X509_check_ip_asc().
I cannot coherently express how disappointed I am by this response.

The current state is that EDK2 doesn't check the subject of the
certificate at all.
Highlight again: we do check the certificate peername in SAN & Subject CommonName (CN) instead of nothing.


We're trying to fix that, and you have expended more effort typing in
poor excuses for doing an incomplete job, than the typing it would have
taken just to get it right in the first place.
My typing is only poor excuses? I'm trying my best to explain the patch intention. I said in the previous email, "We are targeting to the hostname verification, and meanwhile compatible with the IP in the URI". I also agree your suggestion & requires is reasonable & meaning to support the IP check in the certificate. So, my friendly advice is to separate the issues you raised instead of mixing them up.


Thanks,
Jiaxin

Re: question about qemu+kvm+ovmf+winxp

Junhao Gao
 

Hi David

I have found this compiled OVMF-with-csm.fd can support winxp booting up.
OVMF-with-csm.fd path: https://www.kraxel.org/repos/jenkins/seabios/seabios.git-csm-1.12.0-33.63.g43f5df7.x86_64.rpm
Then could you help to provide me the compile method and base code to reproduce this OVMF-with-csm.fd?

Thanks,
Junhao

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Junhao Gao
Sent: Friday, October 11, 2019 9:33 AM
To: devel@edk2.groups.io; lersek@...
Cc: David Woodhouse <dwmw2@...>
Subject: Re: [edk2-devel] question about qemu+kvm+ovmf+winxp

Hi Laszlo
Thank you very much for your great support.

Hi David
Refer to http://www.linux-kvm.org/downloads/lersek/ovmf-whitepaper-c770f8c.txt.

Interested users and developers should look for OVMF's "-D CSM_ENABLE"
build-time option, and check out the <https://www.kraxel.org/repos/> continuous
integration repository, which provides CSM-enabled OVMF builds.

Could you help me to choose which branch supporting CSM, and more details, thanks very much.

Thanks,
Junhao

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Laszlo Ersek
Sent: Friday, October 11, 2019 2:11 AM
To: Gao, Junhao <junhao.gao@...>
Cc: devel@edk2.groups.io; David Woodhouse <dwmw2@...>
Subject: Re: [edk2-devel] question about qemu+kvm+ovmf+winxp

On 10/10/19 16:37, Junhao Gao wrote:
Hi edk2 members

I have a question for your help.
I want to enable qemu+kvm+ovmf to boot up windows xp,
then ovmf support winxp starting-up?
To my understanding, the first Windows "family" with any kind of UEFI support is Windows 7.

OvmfPkg/README has some comments on Windows support:

* UEFI Windows 8 boots
* UEFI Windows 7 & Windows 2008 Server boot (see important notes
below!)
and

=== UEFI Windows 7 & Windows 2008 Server ===

* One of the '-vga std' and '-vga qxl' QEMU options should be used.
* Only one video mode, 1024x768x32, is supported at OS runtime.
* The '-vga qxl' QEMU option is recommended. After booting the installed
guest OS, select the video card in Device Manager, and upgrade its driver
to the QXL XDDM one. Download location:
<http://www.spice-space.org/download.html>, Guest | Windows binaries.
This enables further resolutions at OS runtime, and provides S3
(suspend/resume) capability.
If you'd like to virtualize Windows XP on QEMU/KVM, please use SeaBIOS for guest firmware.

You can also try to build OVMF with -D CSM_ENABLE, but for that, you'll have to build SeaBIOS in CSM mode first, and embed that binary into OVMF at build time. Please ask David for details (CC'd).

Thanks
Laszlo

qemu command:
qemu-system-x86_64 -hda winxp.img -boot c -enable-kvm -cpu host -bios ./OVMF.fd -m 512 -vga cirrus -net nic,model=rtl8139 -net user -usbdevice tablet -localtime
Then if ovmf support, could you provide me the way to compile the OVMF.fd?

Thanks,
Junhao




Re: [edk2-platforms: PATCH v3 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD

Marcin Wojtas
 

Hi Leif,

pt., 11 paź 2019 o 01:51 Leif Lindholm <leif.lindholm@...> napisał(a):

On Fri, Oct 11, 2019 at 01:33:49AM +0200, Marcin Wojtas wrote:
Hi Leif,

pt., 11 paź 2019 o 01:04 Leif Lindholm <leif.lindholm@...> napisał(a):

On Thu, Oct 10, 2019 at 07:42:18AM +0200, Marcin Wojtas wrote:
From: Patryk Duda <pdk@...>

This patch implements convenient way of changing strings included
in SMBIOS Table1, Table2, Table3.

Strings can be altered by defining following PCDs:
gMarvellTokenSpaceGuid.PcdProductManufacturer
gMarvellTokenSpaceGuid.PcdProductPlatformName
gMarvellTokenSpaceGuid.PcdProductVersion
gMarvellTokenSpaceGuid.PcdProductSerial

This patch adds also limit for length of string which can be increased
if necessary in future.

Signed-off-by: Patryk Duda <pdk@...>
---
Silicon/Marvell/Marvell.dec | 6 ++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 4 +
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 79 +++++++++++++++++---
3 files changed, 78 insertions(+), 11 deletions(-)

diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index d337d3e..a84b056 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -169,6 +169,12 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035

+#Platform description
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell \0"|VOID*|0x50000100
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board \0"|VOID*|0x50000101
+ gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set \0"|VOID*|0x50000103
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown \0"|VOID*|0x50000102
+
I'm not too pleased about this random number of spaces. I'm cool with
the strings, but they should be treated as such, not magical data
structures.
In v4 the trailing spaces will be removed from the defaults (as well as "\0").

+STATIC
+VOID
+MvSmbiosCopyStrings (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductManufacturer),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductPlatformName),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductVersion),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
+ ASSERT (AsciiStrnLenS ((CHAR8 *)PcdGetPtr (PcdProductSerial),
+ MV_SMBIOS_STRING_MAX_SIZE) < MV_SMBIOS_STRING_MAX_SIZE);
Especially given the current design, these ASSERTs seem a bit
... unhelpful. In fact, this whole MAX_SIZE thing seems ... restricted
by the implementation, not by external constraints. What is the
benefit? Not having to do a bunch of pointer conversions at
SetVirtualAddressMap?
The default static tables require constant initializers and the
placeholders should have some predefined size in current approach. So
max of 32 characters was picked and with the asserts, ensuring the
user will not exceed it. Do you think they should be removed?
Oh, you're saying this is basically "TO BE FILLED BY OEM"?
*yurgh*.

I still say it's horrible, but not more horrible than most existing
platforms. Nevertheless, the arbitrary size should be something
defined by the code generating the tables - it shouldn't depend on
what's in the .dec (or more usefully, the .dsc).

I also feel that if it is effectively "TO BE FILLED BY OEM", it would
be better if it said that than something that looks like it may be
proper names.

I would also prefer a compilation failure over an ASSERT if the string
ended up not fitting.
I think I found a solution to remove any fixed size constraint and asserts:
STATIC CHAR8 mSysInfoManufacturer[sizeof ((CHAR8 *)PcdGetPtr
(PcdProductManufacturer))];
STATIC CHAR8 mSysInfoProductName[sizeof ((CHAR8 *)PcdGetPtr
(PcdProductPlatformName))];
STATIC CHAR8 mSysInfoVersion[sizeof ((CHAR8 *)PcdGetPtr (PcdProductVersion))];
STATIC CHAR8 mSysInfoSerial[sizeof ((CHAR8 *)PcdGetPtr (PcdProductSerial))];

Please let know, if it's acceptable for you.

Best regards,
Marcin




+
+ Status = AsciiStrCpyS (mSysInfoManufacturer,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductManufacturer));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoProductName,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductPlatformName));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoVersion,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductVersion));
+ ASSERT_EFI_ERROR (Status);
+ Status = AsciiStrCpyS (mSysInfoSerial,
+ MV_SMBIOS_STRING_MAX_SIZE,
+ (CHAR8 *)PcdGetPtr (PcdProductSerial));
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
Install all structures from the DefaultTables structure

@param Smbios SMBIOS protocol
@@ -760,6 +815,8 @@ SmbiosInstallAllStructures (
FirmwareMajorRevisionNumber = (PcdGet32 (PcdFirmwareRevision) >> 16) & 0xFF;
FirmwareMinorRevisionNumber = PcdGet32 (PcdFirmwareRevision) & 0xFF;

+ MvSmbiosCopyStrings();
+
//
// Update Firmware Revision, CPU and DRAM frequencies.
//
--
2.7.4

Re: [PATCH v1 0/4] Support HTTPS HostName validation feature(CVE-2019-14553)

David Woodhouse
 

On Fri, 2019-10-11 at 02:24 +0000, Wu, Jiaxin wrote:
Hi Laszlo & David,

I think I have *repeated* several times that we are targeting to fix
the HostName validation issue, not the IP or email address. *But*
even so, the series patches for UEFI TLS is also allowable to
specify IP as host name for CN or dNSName of SAN in the certificate.
That's why I said "if the CN or SAN in the certificate are set
correctly, it should be OK to pass the verification". The failure you
mentioned here is to set the IP in iPAddress of SAN, I agree it's the
routine and suggested setting, *but* obviously, it's not the target
we are supported according the implementation/description of
TlsSetVerifyHost. We are targeting to the hostname verification, and
meanwhile compatible with the IP in the URI (But need the *correct*
certificate setting).

IP addresses stored in the DNS names and CN are of cause ignored by
X509_check_ip & X509_check_ip_asc().
I cannot coherently express how disappointed I am by this response.

The current state is that EDK2 doesn't check the subject of the
certificate at all.

We're trying to fix that, and you have expended more effort typing in
poor excuses for doing an incomplete job, than the typing it would have
taken just to get it right in the first place.

Re: [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation

Wu, Hao A
 

Hello Ashish,

 

I think the IOMMU feature is added for the protection of FW integrity against

HW devices, which is the motivation to use IOMMU PPI for memory allocation.

 

The fix is easy for the DXE part since the IOMMU part has been integrated to the

implementation of the PciIo protocol.

 

As for the XhciPei case, my thought is that a new helper function (maybe called

'IoMmuAllocateAlignedBuffer') can be added in DmaMem.c file. The main differece

between IoMmuAllocateAlignedBuffer() and existing IoMmuAllocateBuffer() will be:

 

1. If IOMMU PPI exists, mIoMmu->AllocateBuffer() should be called with bigger

number of pages for alignment and mIoMmu->FreeBuffer() can be called right after

to free the unused pages.

 

2. If IOMMU PPI does not exist, this case will fall back to a similar fix for

the DXE case.

 

Ideally, IoMmuFreeBuffer() can be reused to free the aligned buffer.

Please help to raise if you observe any open for the above proposal, thanks.

 

Best Regards,

Hao Wu

 

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ashish Singhal
Sent: Friday, October 11, 2019 11:30 AM
To: Wu, Hao A; devel@edk2.groups.io; Ni, Ray
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation

 

Hello Hao,

 

What is your motivation towards using IoMMUPei for memory allocation now instead of Pei Services? The fix would be simple if we just change the number of pages needed to accommodate for the alignment. The call to free the pages would not do anything.

 

If we use IoMMUPei, we may need to change function definition for allocate to return how many pages were allocated for each call so that freeing can be done correctly as well. This may need more refactoring of the code that initially thought of.

 

Thanks

Ashish

 

From: Wu, Hao A <hao.a.wu@...>
Sent: Thursday, October 10, 2019 9:00 PM
To: devel@edk2.groups.io; Ashish Singhal <ashishsingha@...>; Ni, Ray <ray.ni@...>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation

 

Thanks Ashish,

 

Please help to send out the fix for XhciPei in a separate patch as well.

I can help to see if verification can be done on my side.

 

Best Regards,

Hao Wu

 

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ashish Singhal
Sent: Friday, October 11, 2019 1:51 AM
To: Wu, Hao A; devel@edk2.groups.io; Ni, Ray
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation

 

Hello Hao,

 

I agree that for completeness we should fix the issue in both DXE as well as PEI but on my target, we do not have any PEI phase for me to be able to verify any change that I will be making. If you still want, I can still make the change so that someone else can verify or we can have someone else fix PEI and push my change meanwhile to fix the issue in DXE.

 

Thanks

Ashish


From: Wu, Hao A <hao.a.wu@...>
Sent: Wednesday, October 9, 2019 8:09 PM
To: Ashish Singhal <ashishsingha@...>; devel@edk2.groups.io <devel@edk2.groups.io>; Ni, Ray <ray.ni@...>
Subject: RE: [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation

 

> -----Original Message-----
> From: Ashish Singhal [mailto:ashishsingha@...]
> Sent: Thursday, October 10, 2019 9:58 AM
> To: Wu, Hao A; devel@edk2.groups.io; Ni, Ray
> Subject: RE: [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation
>
> Hello Hao,
>
> I can see that the PEI also has the same issue and take a look at that as well
> but I have no way to verify that as we are not using it. For the change I have
> made in DXE, I have verified it with an alignment of 4K and 64K.


Is it possible for you to verify the PEI case with a test PEI module that
performs read operation to a USB storage device? I think this will trigger
the affecting codes.

In my opinion, it would be better for the fix to be complete.

Best Regards,
Hao Wu


>
> Thanks
> Ashish
>
> -----Original Message-----
> From: Wu, Hao A <hao.a.wu@...>
> Sent: Wednesday, October 9, 2019 7:33 PM
> To: Ashish Singhal <ashishsingha@...>; devel@edk2.groups.io; Ni,
> Ray <ray.ni@...>
> Subject: RE: [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation
>
> > -----Original Message-----
> > From: Ashish Singhal [mailto:ashishsingha@...]
> > Sent: Thursday, October 10, 2019 1:02 AM
> > To: devel@edk2.groups.io; Wu, Hao A; Ni, Ray
> > Cc: Ashish Singhal
> > Subject: [PATCH] MdeModulePkg/XhciDxe: Fix Aligned Page Allocation
> >
> > While allocating pages aligned at an alignment higher than 4K,
> > allocate memory taking into consideration the padding required for
> > that alignment. The calls to free pages takes care of this already.
> >
> > Signed-off-by: Ashish Singhal <ashishsingha@...>
> > ---
> >  MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
> > b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
> > index fd79988..aa69c47 100644
> > --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
> > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c
> > @@ -656,7 +656,7 @@ UsbHcAllocateAlignedPages (
> >                        PciIo,
> >                        AllocateAnyPages,
> >                        EfiBootServicesData,
> > -                      Pages,
> > +                      RealPages,
> >                        &Memory,
> >                        0
> >                        );
>
>
> Hello,
>
> The change looks good to me.
>
> Just a couple of things to confirm:
>
> 1. I think there is a similar case within the XhciPei driver Could you help to
> resolve it as well?
>
> I think for the PEI counterpart you may need to update both
> UsbHcAllocateAlignedPages() and UsbHcFreeAlignedPages(), since the
> IOMMU helper functions like IoMmuAllocateBuffer() and IoMmuFreeBuffer()
> might not be suitable now. Instead, I think services in the IoMmu PPI can be
> used.
>
> 2. Could you help to provide the information on what test has been done for
> the proposed patch?
>
> Thanks in advance.
>
> Best Regards,
> Hao Wu
>
>
> > --
> > 2.7.4
>
> -----------------------------------------------------------------------------------
> This email message is for the sole use of the intended recipient(s) and may
> contain
> confidential information.  Any unauthorized review, use, disclosure or
> distribution
> is prohibited.  If you are not the intended recipient, please contact the
> sender by
> reply email and destroy all copies of the original message.
> -----------------------------------------------------------------------------------

Re: OVMF is crashing for me in master

Andrew Fish
 

Liming,

Thanks for looking into this!

Can someone also answer my question about the expected behavior of taking an exception in OVMF?  Is the CpuDeadloop() expected? 

Thanks,

Andrew Fish

On Oct 10, 2019, at 6:19 PM, Gao, Liming <liming.gao@...> wrote:

Andrew:
  I verify the change (2de1f611be06ded3a59726a4052a9039be7d459b MdeModulePkg/BdsDxe: Also call PlatformBootManagerWaitCallback on 0) in Emulator.
  It works, because PCD value is set to 10 in Emulator.
 
  Before this change, if TimeOut PCD is zero, BdsEntry doesn’t call PlatformBootManagerWaitCallback().
  After this change,  if TimeOut PCD is zero, BdsEntry still call PlatformBootManagerWaitCallback(). So, it trigs this issue. I agree your fix.
 
Pete:
  Will you contribute the patch to fix this hang issue in OVMF?
 
Thanks
Liming
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Andrew Fish via Groups.Io
Sent: Friday, October 11, 2019 5:12 AM
To: devel@edk2.groups.io; Pete Batard <pete@...>
Subject: [edk2-devel] OVMF is crashing for me in master
 
This is my flavor of OVMF:  build -p OvmfPkg/OvmfPkgX64.dsc -a X64 -t XCODE5
 
It looks like I took an exception? Is it expected that an unhandled exception just hang in a dead loop? I would have expected some serial  output about the failure? 
 
Looks like a divide by zero exception. The exception context has PC and FP so I can manually walk the stack. Yikes I see PlatformBootManagerWaitCallback() will fault if PcdPlatformBootTimeOut is zero? 
/Volumes/Case/UDK2018(master)>git grep PcdPlatformBootTimeOut -- *.dsc
ArmVirtPkg/ArmVirtQemu.dsc:194:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
ArmVirtPkg/ArmVirtQemuKernel.dsc:191:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
ArmVirtPkg/ArmVirtXen.dsc:122:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
EmulatorPkg/EmulatorPkg.dsc:236:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
OvmfPkg/OvmfPkgIa32.dsc:541:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
OvmfPkg/OvmfPkgIa32X64.dsc:553:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
OvmfPkg/OvmfPkgX64.dsc:552:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
OvmfPkg/OvmfXen.dsc:470:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
UefiPayloadPkg/UefiPayloadPkgIa32.dsc:344:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc:345:  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3


OK PcdPlatformBootTimeOut is zero on Ovmf, so how did this ever work?


Ahhh gotom.... 
/Volumes/Case/UDK2018(master)>git blame -L344,344  /Volumes/Case/UDK2018/MdeModulePkg/Universal/BdsDxe/BdsEntry.c 
2de1f611be0 (Pete Batard 2019-09-25 23:50:05 +0800 344)   PlatformBootManagerWaitCallback (0);


This call causes a divide by zero if PcdPlatformBootTimeOut == 0. 
 
This fixes my crash:
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
index 70df6b841a..d6ae43e900 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -1634,6 +1634,11 @@ PlatformBootManagerWaitCallback (
   UINT16                              Timeout;
 
   Timeout = PcdGet16 (PcdPlatformBootTimeOut);
+  if (Timeout ==  0) {
+    Timeout = 100;
+  } else {
+    Timeout = (Timeout - TimeoutRemain) * 100 / Timeout;
+  }
 
   Black.Raw = 0x00000000;
   White.Raw = 0x00FFFFFF;
@@ -1643,7 +1648,7 @@ PlatformBootManagerWaitCallback (
     Black.Pixel,
     L"Start boot option",
     White.Pixel,
-    (Timeout - TimeoutRemain) * 100 / Timeout,
+    Timeout,
     0
     );
 }


 
lldb debugger output:
 
(lldb) bt
* thread #1, stop reason = signal SIGTRAP
  * frame #0: 0x0000000007b58a70 CpuDxe.dll:CpuDeadLoop() + 13 at /Volumes/Case/UDK2018/MdePkg/Library/BaseLib/CpuDeadLoop.c:31
    frame #1: 0x0000000007b61222 CpuDxe.dll:CommonExceptionHandlerWorker() + 674 at /Volumes/Case/UDK2018/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c:115
    frame #2: 0x0000000007b61624 CpuDxe.dll:CommonExceptionHandler() + 36 at /Volumes/Case/UDK2018/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c:40
    frame #3: 0x0000000007b5ff26 CpuDxe.dll:HasErrorCode() + 230
(lldb) fr sel 1
frame #1: 0x0000000007b61222 CpuDxe.dll:CommonExceptionHandlerWorker() + 674 at /Volumes/Case/UDK2018/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c:115
   91             (ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
   92           } else if (ExceptionType < CPU_EXCEPTION_NUM) {
   93             //
   94             // Get Spinlock to display CPU information
   95             //
   96             while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {
   97               CpuPause ();
   98             }
   99             //
   100           // Initialize the serial port before dumping.
   101           //
   102           SerialPortInitialize ();
   103           //
   104           // Display ExceptionType, CPU information and Image information
   105           //
   106           DumpImageAndCpuContent (ExceptionType, SystemContext);
   107           //
   108           // Release Spinlock of output message
   109           //
   110           ReleaseSpinLock (&ExceptionHandlerData->DisplayMessageSpinLock);
   111           //
   112           // Enter a dead loop if needn't to execute old IDT handler further
   113           //
   114           if (ReservedVectors[ExceptionType].Attribute != EFI_VECTOR_HANDOFF_HOOK_BEFORE) {
-> 115            CpuDeadLoop ();
   116           }
   117         }
   118       }
   119      
(lldb) p ExceptionType
(EFI_EXCEPTION_TYPE) $0 = 0
(lldb) p SystemContext.SystemContextX64->Rip
(UINT64) $1 = 0x0000000007a9cc38
(lldb) p SystemContext.SystemContextX64->Rbp
(UINT64) $2 = 0x0000000007e8fc20
(lldb) efi_backtrace --pc 0x0000000007a9cc38 --frame 0x0000000007e8fc20 --symbols
  frame  0: 0x07a9cc38 BdsDxe:PlatformBootManagerWaitCallback + 35 at /Volumes/Case/UDK2018/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c:1646:37
  frame  1: 0x07a9e744 BdsDxe:BdsWait + 269 at /Volumes/Case/UDK2018/MdeModulePkg/Universal/BdsDxe/BdsEntry.c:344:3
  frame  2: 0x07a9dff9 BdsDxe:BdsEntry + 2620 at /Volumes/Case/UDK2018/MdeModulePkg/Universal/BdsDxe/BdsEntry.c:1002:5
  frame  3: 0x07eb367d DxeCore:DxeMain + 2680 at /Volumes/Case/UDK2018/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c:544:3
  frame  4: 0x07e943cb DxeCore:_ModuleEntryPoint + 20 at /Volumes/Case/UDK2018/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.c:48:3
  frame  5: 0x07edc947 DxeIpl.dll`AsmEnableCache
  frame  6: 0x07ee1e4e DxeIpl:HandOffToDxeCore + 509 at /Volumes/Case/UDK2018/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c:113:3
  frame  7: 0x07ee0604 DxeIpl:DxeLoadCore + 1354 at /Volumes/Case/UDK2018/MdeModulePkg/Core/DxeIplPeim/DxeLoad.c:449:3
  frame  8: 0x07eeff2f PeiCore.dll`PeiCore.cold.3 + 847
  frame  9: 0x07ee9d04 PeiCore:PeiCore + 163 at /Volumes/Case/UDK2018/MdeModulePkg/Core/Pei/PeiMain/PeiMain.c:502:3
  frame 10: 0x0082c387 0x0082c387
  frame 11: 0x00825dd7 0x00825dd7
  frame 12: 0x0082ad27 0x0082ad27
  frame 13: 0x0082b3a8 0x0082b3a8
  frame 14: 0x0082bf23 0x0082bf23
  frame 15: 0x00825e24 0x00825e24
  frame 16: 0x00823af2 0x00823af2
  frame 17: 0xfffd1db8 SecMain:SecStartupPhase2 + 67 at /Volumes/Case/UDK2018/OvmfPkg/Sec/SecMain.c:858:3
  frame 18: 0xfffd1d67 SecMain:SecCoreStartupWithStack + 420 at /Volumes/Case/UDK2018/OvmfPkg/Sec/SecMain.c:821:3
  frame 19: 0xfffd1e14 SecMain:ProcessLibraryConstructorList + 0 at /Volumes/Case/UDK2018/Build/OvmfX64/DEBUG_XCODE5/X64/OvmfPkg/Sec/SecMain/DEBUG/AutoGen.c:201
 
(lldb) l /Volumes/Case/UDK2018/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c:1646
   1646         (Timeout - TimeoutRemain) * 100 / Timeout,
   1647         0
   1648         );
   1649     }
   1650    
   1651     /**
   1652       The function is called when no boot option could be launched,
   1653       including platform recovery options and options pointing to applications
   1654       built into firmware volumes.
   1655    
(lldb) l /Volumes/Case/UDK2018/MdeModulePkg/Universal/BdsDxe/BdsEntry.c:344
   344         PlatformBootManagerWaitCallback (0);
   345         DEBUG ((EFI_D_INFO, "[Bds]Exit the waiting!\n"));
   346       }
   347      
   348       /**
   349         Attempt to boot each boot option in the BootOptions array.
   350      
   351         @param BootOptions       Input boot option array.
   352         @param BootOptionCount   Input boot option count.
   353         @param BootManagerMenu   Input boot manager menu.
   354      
 
 
Thanks,
 
Andrew Fish
 

Re: [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique token namespace

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Agyeman, Prince <prince.agyeman@...>; Wei, David Y <david.y.wei@...>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique token namespace

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2249

PCDs declared in the SimicsOpenBoardPkg currently use the GUID gBoardModuleTokenSpaceGuid. The same name is used in other board packages and a package has been added called BoardModulePkg so this name is now misleading.

This change assigns a unique GUID value and a name specific to the package to provide differentiation from PCDs in other board packages.

Cc: Agyeman Prince <prince.agyeman@...>
Cc: Wei David Y <david.y.wei@...>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec | 72 ++++++++++----------
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 14 ++--
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf | 12 ++--
Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 14 ++--
Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf | 10 +--
Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 10 +--
Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf | 18 ++---
Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf | 36 +++++-----
Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf | 2 +-
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc | 6 +-
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc | 16 ++---
11 files changed, 105 insertions(+), 105 deletions(-)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec
index 40487820fa..421c464023 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec
@@ -17,57 +17,57 @@
Include

[Guids]
- gBoardModuleTokenSpaceGuid = {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a, 0xea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}}
+ gSimicsOpenBoardPkgTokenSpaceGuid = {0x75fd61da, 0x3931, 0x49aa,
+ {0x8f, 0x11, 0x18, 0x25, 0xf6, 0x31, 0x21, 0xd2}}
gSimicsBoardConfigGuid = {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a, 0xea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}}

[PcdsFixedAtBuild]
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x15
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x16
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x1
+ 5
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x1
+ 6

#TODO: Remove these two when we integrate new PlatformPei
- gBoardModuleTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32|2
- gBoardModuleTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32|3
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32
+ |2
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32
+ |3

- gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase|0x0|UINT32|0x8
- gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize|0x0|UINT32|0x9
- gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0xa
- gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32|0xb
- gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase|0x0|UINT32|0xc
- gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase|0x0|UINT32|0xd
- gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe
- gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0xf
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT32|0x11
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT32|0x12
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT32|0x13
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT32|0x14
- gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT32|0x18
- gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT32|0x19
- gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a
- gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0|UINT32|0x1f
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase|
+ 0x0|UINT32|0x8
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize|
+ 0x0|UINT32|0x9
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0
+ xa
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32|
+ 0xb
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase|
+ 0x0|UINT32|0xc
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase|
+ 0x0|UINT32|0xd
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBas
+ e|0x0|UINT32|0xe
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0x
+ f
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT3
+ 2|0x11
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT3
+ 2|0x12
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT3
+ 2|0x13
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT3
+ 2|0x14
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT
+ 32|0x18
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT
+ 32|0x19
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0
+ |UINT32|0x1a
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0
+ |UINT32|0x1f

[PcdsDynamic, PcdsDynamicEx]

# TODO: investigate whether next two Pcds are needed
- gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28
- gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UINT16|0x1b
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BO
+ OLEAN|0x10
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UIN
+ T16|0x1b

## The IO port aperture shared by all PCI root bridges.
#
- gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
- gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23

## The 32-bit MMIO aperture shared by all PCI root bridges.
#
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25

## The 64-bit MMIO aperture shared by all PCI root bridges.
#
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27

[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]
## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined<BR><BR> @@ -131,7 +131,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
## FFS filename to find the shell application.
# @Prompt FFS Name of Shell Application
- gBoardModuleTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x40000004
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04,
+ 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0,
+ 0xB4, 0xD1 }|VOID*|0x40000004

## ISA Bus features to support DMA, SlaveDMA and ISA Memory. <BR><BR>
# BIT0 indicates if DMA is supported<BR> @@ -140,10 +140,10 @@
# Other BITs are reseved and must be zero.
# If more than one features are supported, the different BIT will be enabled at the same time.
# @Prompt ISA Bus Features
- # @Expression 0x80000002 | (gBoardModuleTokenSpaceGuid.PcdIsaBusSupportedFeatures & 0xF8) == 0
- gBoardModuleTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT8|0x00010040
+ # @Expression 0x80000002 |
+ (gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusSupportedFeatures & 0xF8)
+ == 0
+
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT
+ 8|0x00010040

- gBoardModuleTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2, 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }|VOID*|0x00010037
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2,
+ 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F,
+ 0xC1, 0x4D }|VOID*|0x00010037

[Protocols]
##
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index 29cd2455f6..0298e4b12d 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
+++ c
@@ -235,13 +235,13 @@
######################################
# Board Configuration
######################################
- gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0
- gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0

######################################
# Advanced Feature Configuration
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
index 6c1579bef7..75a99a5270 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
@@ -80,23 +80,23 @@ BlockSize = 0x10000
NumBlocks = 0xB0

0x000000|0x006000
-gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesSize
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|gSimicsOpe
+nBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize

0x006000|0x001000
-gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gSimicsOp
+enBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize

0x007000|0x001000
-gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
+gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gSimicsOpe
+nBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize

0x010000|0x008000
-gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gSimicsOpe
+nBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize

0x020000|0x0E0000
-gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|gSimicsOpenBoar
+dPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize
FV = FvPreMemory

0x100000|0xA00000
-gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|gSimicsOpenBoar
+dPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize
FV = DXEFV

################################################################################
diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index e1920bd2ff..372e0c9651 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHost
+++ BridgeLib.inf
@@ -41,11 +41,11 @@
PciLib

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdPciIoBase
- gBoardModuleTokenSpaceGuid.PcdPciIoSize
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Base
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Size
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Base
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Size
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
index bc85420f97..5d2e39532c 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReport
+++ FvLib.inf
@@ -48,9 +48,9 @@
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire
diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index cdb6e242e8..3fb76c3564 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/P
+++ latformBootManagerLib.inf
@@ -50,12 +50,12 @@
LogoLib

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent
- gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
- gBoardModuleTokenSpaceGuid.PcdShellFile
- gBoardModuleTokenSpaceGuid.PcdLogoFile
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile

[Pcd.IA32, Pcd.X64]
gEfiMdePkgTokenSpaceGuid.PcdFSBClock
diff --git a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf b/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf
index b1d319c5ea..61ca2c0613 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf
@@ -58,16 +58,16 @@
gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
- gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd

[FeaturePcd]
gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire
diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf
index e466d57e4e..9499d2aad5 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf
@@ -55,25 +55,25 @@
PcdLib

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase
- gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize
- gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase
- gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase
- gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
- gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
- gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
- gBoardModuleTokenSpaceGuid.PcdPciIoBase
- gBoardModuleTokenSpaceGuid.PcdPciIoSize
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Base
- gBoardModuleTokenSpaceGuid.PcdPciMmio32Size
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Base
- gBoardModuleTokenSpaceGuid.PcdPciMmio64Size
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size
gSimicsX58PkgTokenSpaceGuid.PcdX58TsegMbytes
gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire
gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf
index 002cb56826..e0eee30985 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf
+++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.in
+++ f
@@ -70,5 +70,5 @@

[Pcd]
gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion
- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
+ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc
index ae9a625da9..af583ecde6 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.
+++ fdf.inc
@@ -45,7 +45,7 @@
# The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 + # PcdSimicsDxeMemFvSize).

-DEFINE OUTPUT_SIZE = (128 + gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 + gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize)
+DEFINE OUTPUT_SIZE = (128 +
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 +
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize)

# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see # SCRATCH_BUFFER_REQUEST_SIZE in @@ -58,10 +58,10 @@ DEFINE DECOMP_SCRATCH_SIZE = 0x00010000 # # The calculation below mirrors DecompressMemFvs() [SimicsX58Pkg/Sec/SecMain.c].

-DEFINE OUTPUT_BASE = ($(MEMFD_BASE_ADDRESS) + gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000)
+DEFINE OUTPUT_BASE = ($(MEMFD_BASE_ADDRESS) + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000)
DEFINE DECOMP_SCRATCH_BASE_UNALIGNED = ($(OUTPUT_BASE) + $(OUTPUT_SIZE)) DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT = 0x000FFFFF
DEFINE DECOMP_SCRATCH_BASE_MASK = 0xFFF00000
DEFINE DECOMP_SCRATCH_BASE = (($(DECOMP_SCRATCH_BASE_UNALIGNED) + $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & $(DECOMP_SCRATCH_BASE_MASK))

-SET gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd = $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE)
+SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd
+= $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
index 044129c941..9c2436c3ad 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.i
+++ nc
@@ -29,20 +29,20 @@ DEFINE SECFV_OFFSET = 0x001EC000
DEFINE SECFV_SIZE = 0x14000


-SET gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress = $(FW_BASE_ADDRESS)
-SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize = $(FW_SIZE)
-SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize = $(BLOCK_SIZE)
+SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress = $(FW_BASE_ADDRESS)
+SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize = $(FW_SIZE)
+SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize =
+$(BLOCK_SIZE)

-SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase = $(FW_BASE_ADDRESS)
+SET
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =
+$(FW_BASE_ADDRESS)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0xE000

-SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase = gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
-SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize = $(BLOCK_SIZE)
+SET
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase +
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+SET
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =
+$(BLOCK_SIZE)

-SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase = gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase + gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize
+SET
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase
+= gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase
++ gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(BLOCK_SIZE)

-SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase = gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+SET
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =
+gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase
++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x10000

SET gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFFE00000
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 16/17] SimicsOpenBoardPkg/BoardX58Ich10: DSC cleanup

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Agyeman, Prince <prince.agyeman@...>; Wei, David Y <david.y.wei@...>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 16/17] SimicsOpenBoardPkg/BoardX58Ich10: DSC cleanup

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2244

This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability.

The same pattern made in this change for BoardX58Ich10 is being applied to all existing board packages in Platform/Intel to improve overall consistency.

Cc: Agyeman Prince <prince.agyeman@...>
Cc: Wei David Y <david.y.wei@...>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 282 +++++++------
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 418 +++++++++-----------
2 files changed, 361 insertions(+), 339 deletions(-)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 40f864ae17..4f8ab4170d 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -1,6 +1,7 @@
## @file
+# The main build description file for the X58Ich10 board.
#
-# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,7 +34,7 @@
DEFINE SMM_REQUIRE = TRUE

#
- #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64 platform
+ # PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64
+ platform
#
DEFINE PLATFORMX64_ENABLE = TRUE
DEFINE NETWORK_TLS_ENABLE = FALSE
@@ -45,7 +46,7 @@

################################################################################
#
-# SKU Identification section - list of all SKU IDs supported by this Platform.
+# SKU Identification section - list of all SKU IDs supported by this board.
#
################################################################################
[SkuIds]
@@ -53,173 +54,232 @@

################################################################################
#
-# Library Class section - list of all Library Classes needed by this Platform.
+# Includes section - other DSC file contents included for this board build.
#
################################################################################

- !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
- !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
- !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
- !include $(PCH_PKG)/IchCommonLib.dsc
+#######################################
+# Library Includes
+#######################################
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+!include $(PCH_PKG)/IchCommonLib.dsc
+
+#######################################
+# Component Includes
+#######################################
+[Components.IA32]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+!include $(SKT_PKG)/SktPkgPei.dsc
+
+[Components.X64]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+!include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc
+
+#######################################
+# Build Option Includes
+#######################################
+!include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc
+
+#######################################################################
+#########
+#
+# Library Class section - list of all Library Classes needed by this board.
+#
+#######################################################################
+#########

[LibraryClasses]
- ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+ #######################################
+ # Edk2 Packages
+ #######################################
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+ CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull
+ /CpuExceptionHandlerLibNull.inf
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScr
+ iptLib.inf
SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
+
+ #####################################
+ # Platform Package
+ #####################################
+
+ AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUp
+ dateLib.inf
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull
+ /BoardInitLibNull.inf
+ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSim
+ ple/PciSegmentInfoLibSimple.inf
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNu
+ ll/TestPointCheckLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf
+ LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf
NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf
+ ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/SerializeVariablesLib.inf
- DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf
- CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
-
- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
- BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf
SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
- PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
- S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
- AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
- LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf

[LibraryClasses.common.SEC]
+ #######################################
+ # Edk2 Packages
+ #######################################
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf

[LibraryClasses.common.PEIM]
+ #######################################
+ # Edk2 Packages
+ #######################################
PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf

-[LibraryClasses.IA32]
+ #####################################
+ # Platform Package
+ #####################################
!if $(TARGET) == DEBUG
- TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P
+ eiTestPointCheckLib.inf
!endif
- TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoin
+ tLib.inf

[LibraryClasses.common.DXE_DRIVER]
+ #######################################
+ # Board Package
+ #######################################
PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

[LibraryClasses.common.DXE_SMM_DRIVER]
+ #######################################
+ # Silicon Initialization Package
+ #######################################
SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf

[Components.IA32]
- $(BOARD_PKG)/SecCore/SecMain.inf {
- <LibraryClasses>
- NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- }
- !include $(SKT_PKG)/SktPkgPei.dsc
- !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
-
- $(BOARD_PKG)/SimicsPei/SimicsPei.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- }
-# S3 SMM driver
-# UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+ #######################################
+ # Edk2 Packages
+ #######################################
+ # S3 SMM driver
+ # @todo: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
<LibraryClasses>
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
}

+ #######################################
+ # Silicon Initialization Package
+ #######################################
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
$(SKT_PKG)/Smm/Access/SmmAccessPei.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
}
!endif
- $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf

- MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ #####################################
+ # Platform Package
+ #####################################
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in
+ f {
<LibraryClasses>
BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
}
- MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i
+ nf {
<LibraryClasses>
BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
}
- MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
- MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM
+ em.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost
+ Mem.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ $(BOARD_PKG)/SecCore/SecMain.inf {
+ <LibraryClasses>
+
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompress
+ Lib.inf
+ }
+
+ $(BOARD_PKG)/SimicsPei/SimicsPei.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }

[Components.X64]
- !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
- !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc
-
- MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-
- MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
- #
- # ISA Support
- #
- $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
- MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
-
- $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
- $(BOARD_PKG)/AcpiTables/AcpiTables.inf
- #
- # Video support
- #
- $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf
-
- MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
- MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
- $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf
- MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
- MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
-
- SimicsIch10BinPkg/UndiBinary/UndiDxe.inf
-
- #
- # Shell
- #
- ShellPkg/Application/Shell/Shell.inf {
- <PcdsFixedAtBuild>
- gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
- <LibraryClasses>
- NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
- ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
- HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
- BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
- ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
- ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
- }
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
- $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf
- $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf
- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
- $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf
- MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
- UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
- MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf {
- <LibraryClasses>
- LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
- }
-!endif
- MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ #######################################
+ # Edk2 Packages
+ #######################################
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
PciHostBridgeLib|$(BOARD_PKG)/Library/PciHostBridgeLib/PciHostBridgeLib.inf
}
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
-
- UefiCpuPkg/CpuDxe/CpuDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
- #
- # ACPI Support
- #
MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
+
+MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe
+.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+ MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf {
+ <LibraryClasses>
+
+LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+ }
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+!endif
+ UefiCpuPkg/CpuDxe/CpuDxe.inf

+ ShellPkg/Application/Shell/Shell.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ }
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SimicsIch10BinPkg/UndiBinary/UndiDxe.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf
+ $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf
+ $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf
+!endif
+
+ #####################################
+ # Platform Package
+ #####################################
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+!endif
+
+ #######################################
+ # Advanced Feature Package
+ #######################################
!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf
!endif

- !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc
+ #######################################
+ # Board Package
+ #######################################
+ $(BOARD_PKG)/AcpiTables/AcpiTables.inf
+ $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
+ $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
+ $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf
+ $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf
+ $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index ad5e0c5a38..29cd2455f6 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
+++ c
@@ -1,4 +1,5 @@
## @file
+# PCD configuration build description file for the X58Ich10 board.
#
# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> # @@ -8,18 +9,53 @@

################################################################################
#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+# Pcd Section - list of all PCD Entries used by this board.
#
################################################################################
-[PcdsFixedAtBuild]
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
+ #
+ # Please select the Boot Stage here.
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ #
gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4

[PcdsFeatureFlag.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE
+!if $(TARGET) == RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE

!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
@@ -44,231 +80,54 @@
gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
!endif

- !if $(TARGET) == DEBUG
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
- !else
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
- !endif
+!if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+!endif

- gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+ ######################################
+ # Silicon Configuration
+ ######################################
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE
+!endif

+ ######################################
+ # Advanced Feature Configuration
+ ######################################
gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE

-!if $(TARGET) == RELEASE
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
-!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
-!endif
- # Server doesn't support capsle update on Reset.
- gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
- gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
-
-
-#S3 add
- gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
-#S3 add
-
- ## This PCD specified whether ACPI SDT protocol is installed.
- gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
-
[PcdsFeatureFlag.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE

-[PcdsFeatureFlag]
- gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
-
-[PcdsDynamicExDefault]
-
[PcdsFixedAtBuild.common]
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
-!if $(TARGET) == "RELEASE"
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
-!else
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
-!endif
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
- gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
-#S3 modified
- gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
-#S3 modified
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
- gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
- gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000
-
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
-
- ## Specifies delay value in microseconds after sending out an INIT IPI.
- # @Prompt Configure delay value after send an INIT IPI
- gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
-
- ## Specifies max supported number of Logical Processors.
- # @Prompt Configure max supported number of Logical Processorss
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
-!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
-!endif
-
- ## Defines the ACPI register set base address.
- # The invalid 0xFFFF is as its default value. It must be configured to the real value.
- # @Prompt ACPI Timer IO Port Address
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0400
-
- ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
- # @Prompt ACPI Hardware PCI Bus Number
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
+ ######################################
+ # Edk2 Configuration
+ ######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013
-
- ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
- # The invalid 0xFF is as its default value. It must be configured to the real value.
- # @Prompt ACPI Hardware PCI Device Number
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
-
- ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
- # The invalid 0xFF is as its default value. It must be configured to the real value.
- # @Prompt ACPI Hardware PCI Function Number
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x00
-
- ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
- # The invalid 0xFFFF is as its default value. It must be configured to the real value.
- # @Prompt ACPI Hardware PCI Register Offset
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
-
- ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
- # @Prompt ACPI Hardware PCI Bar Enable BitMask
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
-
- ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
- # The invalid 0xFFFF is as its default value. It must be configured to the real value.
- # @Prompt ACPI Hardware PCI Bar Register Offset
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
-
- ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
- # @Prompt Offset to 32-bit Timer register in ACPI BAR
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
-
- ## Defines the bit mask to retrieve ACPI IO Port Base Address
- # @Prompt ACPI IO Port Base Address Mask
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC
-
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
-
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4
- gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
- gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0
- gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003
- gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420
- gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
-
-[PcdsFixedAtBuild.X64]
- gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
- gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
- gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
- # Change PcdBootManagerMenuFile to UiApp -##
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
-
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
-
- [PcdsPatchableInModule.common]
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
-!endif
-
- gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
-
- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0
- gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0
-
-[PcdsDynamicExDefault.common.DEFAULT]
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
- gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
-
-[PcdsDynamicExHii.common.DEFAULT]
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|50 # Variable: L"Timeout"
- gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
-
-
-[PcdsDynamicExDefault]
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x45, 0x4C, 0x20}
- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030363253
-
-[PcdsDynamicExDefault.X64]
-
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
-
- gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
-
-[PcdsFeatureFlag]
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
- #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE
- #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
- gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE
-!endif
-
-[PcdsFixedAtBuild]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
- gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000
-
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
-
# DEBUG_INIT 0x00000001 // Initialization
# DEBUG_WARN 0x00000002 // Warnings
# DEBUG_LOAD 0x00000004 // Load events
@@ -291,34 +150,137 @@
# DEBUG_ERROR 0x80000000 // Error
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask| 0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x0040
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber| 0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber| 0x1F
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x0044
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber| 0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x0400
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x0008
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000

- #
- # PCI feature overrides.
- #
- gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
-
-################################################################################
-#
-# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform -# -################################################################################
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+
+[PcdsFixedAtBuild.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa,
+0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66,
+0x23, 0x31 }
+ gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ [PcdsPatchableInModule.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0

[PcdsDynamicDefault]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0

- gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0
+ ######################################
+ # Board Configuration
+ ######################################
gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0
gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0
gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0
gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0
gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0
gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000
+ gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0

+ ######################################
+ # Advanced Feature Configuration
+ ######################################
+ gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"2019-08-09"
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ver.1.0.0"
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|"QSP UEFI BIOS"
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|"QSP UEFI BIOS"
- gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"2019-08-09"

- gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
+[PcdsDynamicExDefault]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54,
+0x45, 0x4C, 0x20}
+
+gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030363
+253
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
+
+[PcdsDynamicExDefault.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
+
+[PcdsDynamicExHii.common.DEFAULT]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|50 # Variable: L"Timeout"
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 15/17] SimicsOpenBoardPkg/BoardX58Ich10: Remove OpenBoardPkgConfig.dsc

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Agyeman, Prince <prince.agyeman@...>; Wei, David Y <david.y.wei@...>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 15/17] SimicsOpenBoardPkg/BoardX58Ich10: Remove OpenBoardPkgConfig.dsc

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2244

The location for PCD configuration is currently inconsistent in SimicsOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including
FeaturePCD) are located in OpenBoardPkgPcd.dsc.

This change consolidates PCD configuration for the BoardX58Ich10 board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc.

Cc: Agyeman Prince <prince.agyeman@...>
Cc: Wei David Y <david.y.wei@...>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 -
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc | 56 --------------------
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 43 +++++++++++++++
3 files changed, 43 insertions(+), 57 deletions(-)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index be29737c16..40f864ae17 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -40,7 +40,6 @@
DEFINE NETWORK_ISCSI_ENABLE = FALSE
DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE

- !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc
!include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc
!include NetworkPkg/NetworkDefines.dsc.inc

diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc
deleted file mode 100644
index 75de60e5bc..0000000000
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc
+++ /dev/null
@@ -1,56 +0,0 @@
-## @file
-#
-# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
-
-#
-# TRUE is ENABLE. FALSE is DISABLE.
-#
-
-[PcdsFixedAtBuild]
- gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
-
-[PcdsFeatureFlag]
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
-!endif
-
- !if $(TARGET) == DEBUG
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
- !else
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
- !endif
-
- gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
-
- gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE
- gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
-
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index 3bf10ee524..ad5e0c5a38 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.ds
+++ c
@@ -11,7 +11,50 @@
# Pcd Section - list of all EDK II PCD Entries defined by this Platform # ################################################################################
+[PcdsFixedAtBuild]
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
[PcdsFeatureFlag.common]
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+ !if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ !else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+ !endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+
+ gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE
+ gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+
!if $(TARGET) == RELEASE
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
!else
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 14/17] SimicsOpenBoardPkg/BoardX58Ich10: Relocate DSC includes

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Agyeman, Prince <prince.agyeman@...>; Wei, David Y <david.y.wei@...>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 14/17] SimicsOpenBoardPkg/BoardX58Ich10: Relocate DSC includes

This change moves the following DSC file includes to the top of the OpenBoardPkg.dsc file. This is to improve visibility and align placement of the include with other board DSC files.

* OpenBoardPkgConfig.dsc
* OpenBoardPkgPcd.dsc
* CorePeiLib.dsc
* CoreDxeLib.dsc

Cc: Agyeman Prince <prince.agyeman@...>
Cc: Wei David Y <david.y.wei@...>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 21 +++++++-------------
1 file changed, 7 insertions(+), 14 deletions(-)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 59e13154a7..be29737c16 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -39,7 +39,11 @@
DEFINE NETWORK_TLS_ENABLE = FALSE
DEFINE NETWORK_ISCSI_ENABLE = FALSE
DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
+
+ !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc
+ !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc
!include NetworkPkg/NetworkDefines.dsc.inc
+
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.
@@ -54,12 +58,9 @@
#
################################################################################

-[PcdsFeatureFlag]
- #
- # Platform On/Off features are defined here
- #
- !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc
!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+ !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+ !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
!include $(PCH_PKG)/IchCommonLib.dsc

[LibraryClasses]
@@ -76,17 +77,13 @@
SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf
SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
-
- !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
-
S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf
+
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf

-[LibraryClasses.common.PEI_CORE]
-
[LibraryClasses.common.PEIM]
PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -97,16 +94,12 @@
!endif
TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf

- !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
-
[LibraryClasses.common.DXE_DRIVER]
PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

[LibraryClasses.common.DXE_SMM_DRIVER]
SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf

- !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc
-
[Components.IA32]
$(BOARD_PKG)/SecCore/SecMain.inf {
<LibraryClasses>
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 13/17] WhiskeylakeOpenBoardPkg: Assign unique token namespace

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: Kubacki, Michael A <michael.a.kubacki@...>
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <@natedesimone>
Subject: [edk2-platforms][PATCH V1 13/17] WhiskeylakeOpenBoardPkg: Assign unique token namespace

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2248

PCDs declared in the WhiskeylakeOpenBoardPkg currently use the GUID
gBoardModuleTokenSpaceGuid. The same name is used in other board
packages and a package has been added called BoardModulePkg so
this name is now misleading.

This change assigns a unique GUID value and a name specific to the
package to provide differentiation from PCDs in other board
packages.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <@natedesimone>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec | 684 ++++++++++----------
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 14 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 34 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf | 4 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 14 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf | 26 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf | 2 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 22 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 64 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf | 14 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 280 ++++----
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf | 164 ++---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf | 12 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 2 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 2 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf | 14 +-
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 112 ++--
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 214 +++---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 316 ++++-----
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf | 66 +-
21 files changed, 1031 insertions(+), 1031 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
index 8de48077f0..34494d0168 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
@@ -26,7 +26,7 @@ WhiskeylakeURvp/Include

[Guids]

-gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid = {0xec265230, 0x3a23, 0x4650, {0xb7, 0xb6, 0x52, 0x1d, 0x33, 0xd6, 0x6f, 0x78}}

gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}

@@ -72,8 +72,8 @@ gPeiTbtPolicyBoardInitDonePpiGuid = {0x970f9c60, 0x8547, 0x49d7, { 0xa4, 0x

[PcdsFixedAtBuild]

-gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004
-gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005

gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x90000003
gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004
@@ -102,455 +102,455 @@ gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48|UINT8|0x900000
gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505
gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001003

-gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
-gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
-gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
-gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
-gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
-gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000021
-gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x90000022
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000021
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x90000022

[PcdsDynamic]
# Board GPIO Table
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114

# Board Expander GPIO Table
-gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044
-gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045
-gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046
-gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047

# TouchPanel & SDHC CD GPIO Table
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048

# PCH-LP HSIO PTSS Table
-gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A
-gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B
-gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x0000004C
-gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x0000004D
-gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E
-gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F
-gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x00000050
-gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x00000051
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x0000004C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x0000004D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x00000050
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x00000051

# PCH-H HSIO PTSS Table
-gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052
-gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053
-gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054
-gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055
-gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056
-gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057
-gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000058
-gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000059
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000058
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000059

# HDA Verb Table
-gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
-gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
-gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
-gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D
-gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E
-gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F
-gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060

# SA Misc Configuration
-gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
-gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
-gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101

# DRAM Configuration
-gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068
-gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
-gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
-gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B
-gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C
-gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D
-gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x0000006E
-gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F
-gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
-gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x0000006E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071

# PEG RESET GPIO
-gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072
-gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073
-gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
-gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A
-gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B
-gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C
-gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D
-gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E
-gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F

# SPD Address Table
-gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099
-gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A
-gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B
-gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C

# CA Vref Configuration
-gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D

# USB 2.0 Port AFE
-gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
-gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
-gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
-gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
-gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
-gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
-gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
-gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
-gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
-gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
-gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
-gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
-gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
-gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
-gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
-gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE

# USB 2.0 Port Over Current Pin
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD
-gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE

# USB 3.0 Port Over Current Pin
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7
-gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8

# Misc
-gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC

# TBT
-gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
-gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4
-gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5
-gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA
-gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
-gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
-gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
-gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
-gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
-gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
-gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
-gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
-gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107
-gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108
-gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109

# UCMC GPIO Table
-gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111
-gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112

-gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
-gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
-gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
-gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
-gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006
-gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009
-gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A
-gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B
-gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C

# 0: Type-C
# 1: Stacked-Jack
-gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012

-gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013

# gIntelPeiGraphicsVbtGuid = {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}}
-gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014
#==============================================================
#
# The PCD which indicates the Memory Slot Population.
#
-gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x00101027
-gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x00000010
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x00101027
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x00000010

# Board GPIO Table
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x001000115
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16|0x001000116
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x001000117
-gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT16|0x001000118
-gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x0010020C
-gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E
-gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F
-gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230
-gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231
-gBoardModuleTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234
-gBoardModuleTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235
-gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x001000115
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16|0x001000116
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x001000117
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT16|0x001000118
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x0010020C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236

# UCMC GPIO Table
-gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
-gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034

# PEG RESET GPIO
-gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074
-gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075
-gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105
-gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106

# PCIE RTD3 GPIO
-gBoardModuleTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076
-gBoardModuleTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077
-gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104
-gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078

-gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080
-gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081
-gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082
-gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083
-gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084
-gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085
-gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086
-gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x00000087
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x00000087

-gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088
-gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089
-gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A
-gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B
-gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C
-gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D
-gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E
-gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008F
-gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130
-gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131
-gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132
-gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133
-gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134
-gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135
-gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136
-gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x00000137
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x00000137

# Root Port Clock Info
-gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
-gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
-gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
-gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
-gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
-gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
-gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
-gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
-gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
-gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
-gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
-gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
-gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
-gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
-gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
-gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD

# GPIO Group Tier
-gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
-gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
-gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB

# Board related PCH PmConfig
-gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000F6
-gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7
-gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000F6
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8

# Misc
-gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED
-gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE
-gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF
-gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0
-gBoardModuleTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1
-gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2
-gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9
-#gBoardModuleTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9
+#gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC

#PlatformInfoPcd
-gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101000
-gBoardModuleTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001
-gBoardModuleTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002
-gBoardModuleTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003
-gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004
-gBoardModuleTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005
-gBoardModuleTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF"|VOID*|0x00101007
-gBoardModuleTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008
-gBoardModuleTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009
-gBoardModuleTokenSpaceGuid.PcdBiosVersion|L"0123456789012345678901234567890123456789"|VOID*|0x0010100E
-gBoardModuleTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x0010100F
-gBoardModuleTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x00101010
-gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011
-gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
-gBoardModuleTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013
-gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014
-gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015
-gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016
-gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017
-gBoardModuleTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018
-gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019
-gBoardModuleTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101000
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF"|VOID*|0x00101007
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBiosVersion|L"0123456789012345678901234567890123456789"|VOID*|0x0010100E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x0010100F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x00101010
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A

# PCH Misc Configuration
-gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061
-gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065
-gBoardModuleTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102
-gBoardModuleTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103
-gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110

# Control PCD to dump default silicon policy
gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x00010064

# Pch SerialIo I2c Pads Termination
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030
-gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031
#
# The PCD which holds the pointer of Smbios Platform Info table
#
-gBoardModuleTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B
#
# The PCD which used to enable / disable the code to use RVP Smbios Board Info
#
-gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x0010101C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x0010101C
#
# The PCD which holds the pointer of RVP Smbios Board Info
#
-gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D
#
# CoEngineering Custom Defaults PCD
#
-gBoardModuleTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x00100227
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x00100227
#
# The PCD which is defined to enable/disable the SMBus Alert function.
#
-gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E
#
# The PCD which is defined to enable/disable the SATA LED function.
#
-gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F
#
# The PCD which is defined to enable/disable the VR Alert function.
#
-gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020
#
# The PCD which is defined to enable/disable the PCH thermal hot threshold function.
#
-gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021
#
# The PCD which is defined to enable/disable the memory thermal sensor GPIO C/D function.
#
-gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BOOLEAN|0x00101022
-gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BOOLEAN|0x00101023
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BOOLEAN|0x00101022
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BOOLEAN|0x00101023
#
# The PCD defines the I2C bus number to which PSS chip connected.
#
-gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024
-gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025
-gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026
#
# The PCD defines the USB port number to which BLE connected.
#
-gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber |0x0|UINT8|0x00101028
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support |0x00|UINT8|0x00100113
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support |0x00|UINT8|0x00100114
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support |0x00|UINT8|0x00100115
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support |0x00|UINT8|0x00100116
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support |0x00|UINT8|0x00100117
-gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support |0x00|UINT8|0x00100118
-gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|BOOLEAN|0x00100119
-gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|BOOLEAN|0x0010011A
-gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|BOOLEAN|0x0010011B
-gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|BOOLEAN|0x0010011C
-gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|BOOLEAN|0x0010011D
-gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport |FALSE|BOOLEAN|0x0010011F
-gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|UINT32|0x00100120
-gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|BOOLEAN|0x00100121
-gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|BOOLEAN|0x00100122
-gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature |FALSE|BOOLEAN|0x00100123
-gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UINT8|0x00100124
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213
-gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204
-gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205
-gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209
-gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A
-gBoardModuleTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B
-gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F
-gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber |0x0|UINT8|0x00101028
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support |0x00|UINT8|0x00100113
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support |0x00|UINT8|0x00100114
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support |0x00|UINT8|0x00100115
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support |0x00|UINT8|0x00100116
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support |0x00|UINT8|0x00100117
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support |0x00|UINT8|0x00100118
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|BOOLEAN|0x00100119
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|BOOLEAN|0x0010011A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|BOOLEAN|0x0010011B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|BOOLEAN|0x0010011C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|BOOLEAN|0x0010011D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport |FALSE|BOOLEAN|0x0010011F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|UINT32|0x00100120
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|BOOLEAN|0x00100121
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|BOOLEAN|0x00100122
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature |FALSE|BOOLEAN|0x00100123
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent |0x0|UINT8|0x00100124
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210

-gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio |0x0|UINT32|0x00100126
-gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber |0x0|UINT8|0x00100127
-gBoardModuleTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200
-gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio |0x0|UINT32|0x00100125
-gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201
-gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202
-gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203
-gBoardModuleTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215
-gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A
-gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D
-gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040
-gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043
-gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046
-gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048
-gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049
-gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A
-gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed |0x0|UINT8|0x00100128
-gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed |0x0|UINT8|0x00100129
-gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed |0x0|UINT8|0x0010012A
-gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed |0x0|UINT8|0x0010012B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio |0x0|UINT32|0x00100126
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber |0x0|UINT8|0x00100127
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio |0x0|UINT32|0x00100125
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed |0x0|UINT8|0x00100128
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed |0x0|UINT8|0x00100129
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed |0x0|UINT8|0x0010012A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed |0x0|UINT8|0x0010012B

# Super IO Pcd
gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100
gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104
gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105
-gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport |FALSE|BOOLEAN|0x00100112
-gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|UINT32|0x00100111
-gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|UINT8|0x00100103
-gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|UINT8|0x00100104
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport |FALSE|BOOLEAN|0x00100112
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|UINT32|0x00100111
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control |0x00|UINT8|0x00100103
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control |0x00|UINT8|0x00100104

-gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221
-gBoardModuleTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E
-gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D
-gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOLEAN|0x0010022C
-gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B
-gBoardModuleTokenSpaceGuid.PcdMipiCamSensor |FALSE|BOOLEAN|0x00100105
-gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|BOOLEAN|0x0010010A
-gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|BOOLEAN|0x00100107
-gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|BOOLEAN|0x00100108
-gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|BOOLEAN|0x00100109
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOLEAN|0x0010022C
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor |FALSE|BOOLEAN|0x00100105
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO |FALSE|BOOLEAN|0x0010010A
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM |FALSE|BOOLEAN|0x00100107
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO |FALSE|BOOLEAN|0x00100108
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|BOOLEAN|0x00100109

[PcdsDynamicEx]

@@ -559,7 +559,7 @@ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|BOOLEA
[PcdsPatchableInModule]

[PcdsFeatureFlag]
-gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062
-gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF0000000
-gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x000000115
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF0000000
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x000000115

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index d6eb66a880..423fa88c12 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -130,7 +130,7 @@
PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
# Thunderbolt
-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
!endif

@@ -169,7 +169,7 @@
# Board Package
#######################################
# Thunderbolt
-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
!endif
@@ -282,7 +282,7 @@
$(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
<LibraryClasses>
- !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
!else
NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -292,7 +292,7 @@

$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
<LibraryClasses>
- !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
!else
NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -318,7 +318,7 @@
# Board Package
#######################################
# Thunderbolt
-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
!endif

@@ -397,7 +397,7 @@

$(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
<LibraryClasses>
- !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
!else
NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -417,7 +417,7 @@
}

# Thunderbolt
-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
$(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 5cf0aa9d86..adbd48f6d7 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -166,9 +166,9 @@
######################################
# Board Configuration
######################################
- gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
- gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
- gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE

[PcdsFixedAtBuild.common]
######################################
@@ -367,20 +367,20 @@
######################################

# Thunderbolt Configuration
- gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
- gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0
- gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
- gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
- gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
- gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
- gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
- gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
- gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1
- gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1

[PcdsDynamicHii.X64.DEFAULT]
######################################
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
index 30ce0b9b79..320e444aae 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
@@ -613,7 +613,7 @@ READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305

-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
!endif

@@ -655,7 +655,7 @@ READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D

-!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
index 2bbc3cb9e2..af5c8f1c06 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
@@ -51,14 +51,14 @@
gEfiGlobalNvsAreaProtocolGuid

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress

- gBoardModuleTokenSpaceGuid.PcdAcpiSleepState
- gBoardModuleTokenSpaceGuid.PcdAcpiHibernate
- gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle
- gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints
- gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints
- gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints

[Depex]
gEfiAcpiTableProtocolGuid AND
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
index f2330b5b71..75c4f8118d 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
@@ -40,19 +40,19 @@


[Pcd]
-gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES
-gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber

[Sources]
TbtCommonLib.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
index b74e641e16..7ede75d14e 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
@@ -37,7 +37,7 @@ GpioLib
IntelSiliconPkg/IntelSiliconPkg.dec

[Pcd]
-gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES
+gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES

[Sources]
PeiTbtPolicyLib.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index 3d4e6ceea0..bfe299d733 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -45,7 +45,7 @@
CoffeelakeSiliconPkg/SiPkg.dec

[Pcd]
-# gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
+# gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES

[FixedPcd]
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
index bd39cd60b7..8146d0fa03 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
@@ -75,17 +75,17 @@
[Pcd]
gSiPkgTokenSpaceGuid.PcdTsegSize
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
- gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES

[Ppis]
gSiPolicyPpiGuid ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index 994cf93e33..c6dea37402 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -90,45 +90,45 @@
PeiLib

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdData
- gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize


- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
- gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
- gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
- gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size

- gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
- gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size

- gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid

# SPD Address Table
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3

[Guids]
gFspNonVolatileStorageHobGuid ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
index b09dc6b139..31b42bf4ab 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
@@ -59,10 +59,10 @@
PcdLib

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdHdaVerbTable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
index 3095a7333e..ad3146dc7b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -71,174 +71,174 @@
gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardBomId ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
- gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES

# SA Misc Config
- gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES

# Display DDI
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES

# PEG Reset By GPIO
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive ## CONSUMES

# PCIE RTD3 GPIO
- gBoardModuleTokenSpaceGuid.PcdRootPortDev ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdRootPortFunc ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive ## CONSUMES

# SPD Address Table
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES

# CA Vref Configuration
- gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMobileDramPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent ## CONSUMES

# PCIe Clock Info
- gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 ## CONSUMES

# USB 2.0 Port AFE
- gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe ## CONSUMES

# USB 2.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES

# USB 3.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES

# Pch SerialIo I2c Pads Termination
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdEcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent

- gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSataLedEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdVrAlertEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
index 65c531a532..3233375d65 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf
@@ -49,105 +49,105 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
- gBoardModuleTokenSpaceGuid.PcdPlatformFlavor
- gBoardModuleTokenSpaceGuid.PcdPlatformType
- gBoardModuleTokenSpaceGuid.PcdEcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent
gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
- gBoardModuleTokenSpaceGuid.PcdTbtEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable
gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable ## CONSUMES
gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ## CONSUMES
gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication ## CONSUMES
gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication ## CONSUMES
gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
- gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
- gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
- gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
- gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport
- gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport
- gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin
- gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
- gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
- gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature
- gBoardModuleTokenSpaceGuid.PcdBatteryPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent

- gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support
- gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support

#
# PSS Board Configuration.
#
- gBoardModuleTokenSpaceGuid.PcdPssReadSN
- gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber
- gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress

- gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature
- gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile
- gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio
- gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio
- gBoardModuleTokenSpaceGuid.PcdGnssResetGpio
- gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio
- gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio

- gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio
- gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber
- gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber
- gBoardModuleTokenSpaceGuid.PcdEcSmiGpio
- gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio
- gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad
- gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck
- gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride
- gBoardModuleTokenSpaceGuid.PcdDDISelection
- gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6
- gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch
- gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties
- gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed
- gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed
- gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed
- gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed
gPlatformModuleTokenSpaceGuid.PcdH8S2113Present
gPlatformModuleTokenSpaceGuid.PcdNat87393Present
gPlatformModuleTokenSpaceGuid.PcdNct677FPresent
- gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport
- gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin
- gBoardModuleTokenSpaceGuid.PcdRealBattery1Control
- gBoardModuleTokenSpaceGuid.PcdRealBattery2Control
- gBoardModuleTokenSpaceGuid.PcdDimmPopulationError
- gBoardModuleTokenSpaceGuid.PcdBtIrqGpio
- gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio
- gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable
- gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported
- gBoardModuleTokenSpaceGuid.PcdMipiCamSensor
- gBoardModuleTokenSpaceGuid.PcdH8S2113SIO
- gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM
- gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO
- gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON
- gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable
- gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWhlErbRtd3TableEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate

[Sources]
PolicyInitDxe.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 143bb89c63..9f45d6ca4b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -37,16 +37,16 @@

[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSUMES
gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSUMES

[FixedPcd]
- gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
- gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES

[Sources]
BasePlatformHookLib.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
index 8ad32a55dc..c3fd60007a 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
@@ -38,7 +38,7 @@
CoffeelakeSiliconPkg/SiPkg.dec

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES

[Protocols]

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
index 27001c3b7f..eaf46ad4ef 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -38,7 +38,7 @@
CoffeelakeSiliconPkg/SiPkg.dec

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES

[Protocols]

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
index 91cc569388..9bf4d127c5 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
@@ -42,14 +42,14 @@
GpioTableWhiskeylakeUDdr4Rvp.c

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel

- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize

- gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
- gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize

gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 9361c3df3e..4ab80f9eb3 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -38,79 +38,79 @@
PeiBoardInitPreMemLib.c

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort

# PCH-LP HSIO PTSS Table
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size

# SA Misc Config
- gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
- gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
- gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
- gBoardModuleTokenSpaceGuid.PcdMrcSpdData
- gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize

# PEG Reset By GPIO
- gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive


# SPD Address Table
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3

# USB 2.0 Port AFE
- gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe

# USB 2.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13

# USB 3.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5

# Misc
- gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent



diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
index c7330439fb..c043e32638 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -50,152 +50,152 @@
[FixedPcd]

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel

- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize

- gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable
- gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize

#===========================================================
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase
# Board Init Table List

- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize

# WWAN Full Card Power Off and reset pins
- gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
- gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio
- gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio
- gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity

# SA Misc Config
- gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
- gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit

# Display DDI
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES

# PEG Reset By GPIO
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive

# PCIE RTD3 GPIO
- gBoardModuleTokenSpaceGuid.PcdRootPortDev
- gBoardModuleTokenSpaceGuid.PcdRootPortFunc
- gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex

- gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive

- gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive

- gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive

# CA Vref Configuration
- gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig

# PCIe Clock Info
- gBoardModuleTokenSpaceGuid.PcdPcieClock0
- gBoardModuleTokenSpaceGuid.PcdPcieClock1
- gBoardModuleTokenSpaceGuid.PcdPcieClock2
- gBoardModuleTokenSpaceGuid.PcdPcieClock3
- gBoardModuleTokenSpaceGuid.PcdPcieClock4
- gBoardModuleTokenSpaceGuid.PcdPcieClock5
- gBoardModuleTokenSpaceGuid.PcdPcieClock6
- gBoardModuleTokenSpaceGuid.PcdPcieClock7
- gBoardModuleTokenSpaceGuid.PcdPcieClock8
- gBoardModuleTokenSpaceGuid.PcdPcieClock9
- gBoardModuleTokenSpaceGuid.PcdPcieClock10
- gBoardModuleTokenSpaceGuid.PcdPcieClock11
- gBoardModuleTokenSpaceGuid.PcdPcieClock12
- gBoardModuleTokenSpaceGuid.PcdPcieClock13
- gBoardModuleTokenSpaceGuid.PcdPcieClock14
- gBoardModuleTokenSpaceGuid.PcdPcieClock15
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15

# USB 2.0 Port AFE
- gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe

# USB 2.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15

# USB 3.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9

# GPIO Group Tier
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2

# Pch PmConfig Policy
- gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport

# Misc
- gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent
- gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable
- gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent
- gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio
- gBoardModuleTokenSpaceGuid.PcdMobileDramPresent
- gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable


- gBoardModuleTokenSpaceGuid.PcdSpdPresent
- gBoardModuleTokenSpaceGuid.PcdBoardRev
- gBoardModuleTokenSpaceGuid.PcdBoardBomId
- gBoardModuleTokenSpaceGuid.PcdPlatformType
- gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType

- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable
- gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable
# TPM interrupt
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 927a89d401..cd0315377a 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -60,225 +60,225 @@
gTcoWdtHobGuid ## CONSUMES

[Pcd]
- gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort

# PCH-LP HSIO PTSS Table
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
- gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size

# PCH-H HSIO PTSS Table
- #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1
- #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2
- #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
- #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size

# SA Misc Config
- gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
- gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
- gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
- gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
- gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
- gBoardModuleTokenSpaceGuid.PcdMrcSpdData
- gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize

# PEG Reset By GPIO
- gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive


# SPD Address Table
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
- gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3

# USB 2.0 Port AFE
- gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe

# USB 2.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13

# USB 3.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5

# Misc
- gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent

#===========================================================
# Board Init Table List

- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize

# WWAN Full Card Power Off and reset pins
- gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
- gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio
- gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio
- gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity

# SA Misc Config
- gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
- gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
- gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit

# Display DDI
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
- gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES

# PEG Reset By GPIO
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl
- gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad
- gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad
- gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive

# PCIE RTD3 GPIO
- gBoardModuleTokenSpaceGuid.PcdRootPortDev
- gBoardModuleTokenSpaceGuid.PcdRootPortFunc
- gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex

- gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport

- gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive

- gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive

- gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport
- gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
- gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive

# CA Vref Configuration
- gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig

# PCIe Clock Info
- gBoardModuleTokenSpaceGuid.PcdPcieClock0
- gBoardModuleTokenSpaceGuid.PcdPcieClock1
- gBoardModuleTokenSpaceGuid.PcdPcieClock2
- gBoardModuleTokenSpaceGuid.PcdPcieClock3
- gBoardModuleTokenSpaceGuid.PcdPcieClock4
- gBoardModuleTokenSpaceGuid.PcdPcieClock5
- gBoardModuleTokenSpaceGuid.PcdPcieClock6
- gBoardModuleTokenSpaceGuid.PcdPcieClock7
- gBoardModuleTokenSpaceGuid.PcdPcieClock8
- gBoardModuleTokenSpaceGuid.PcdPcieClock9
- gBoardModuleTokenSpaceGuid.PcdPcieClock10
- gBoardModuleTokenSpaceGuid.PcdPcieClock11
- gBoardModuleTokenSpaceGuid.PcdPcieClock12
- gBoardModuleTokenSpaceGuid.PcdPcieClock13
- gBoardModuleTokenSpaceGuid.PcdPcieClock14
- gBoardModuleTokenSpaceGuid.PcdPcieClock15
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15

# USB 2.0 Port AFE
- gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe
- gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe

# USB 2.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
- gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15

# USB 3.0 Port Over Current Pin
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
- gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9

# GPIO Group Tier
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2

# Pch PmConfig Policy
- gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport
- gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport

# Misc
- gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent
- gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable
- gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent
- gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio
- gBoardModuleTokenSpaceGuid.PcdMobileDramPresent
- gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable


- gBoardModuleTokenSpaceGuid.PcdSpdPresent
- gBoardModuleTokenSpaceGuid.PcdBoardRev
- gBoardModuleTokenSpaceGuid.PcdBoardBomId
- gBoardModuleTokenSpaceGuid.PcdPlatformType
- gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType

gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable
- gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress


diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
index 079fb70ecb..d66290e79b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
@@ -40,45 +40,45 @@
CoffeelakeSiliconPkg/SiPkg.dec

[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
- gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize

# GPIO Group Tier
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES

# Misc
- gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES
- gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES

- gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio
- gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable
- gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround

[Sources]
PeiPlatformHooklib.c
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 11/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Update FSP base PCDs

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <@natedesimone>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 11/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Update FSP base PCDs

Sets the FSP-T, FSP-M, and FSP-S base address PCDs based on the flash map.

Previously these were hardcoded in the DSC file.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <@natedesimone>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf | 3 +++
1 file changed, 3 insertions(+)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
index 611078e4b4..30ce0b9b79 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf
@@ -55,6 +55,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdBiosSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdBiosSize
################################################################################
--
2.16.2.windows.1

Re: [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: DSC cleanup

Nate DeSimone
 

Reviewed-by: Nate DeSimone <@natedesimone>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kubacki, Michael A
Sent: Monday, October 7, 2019 10:17 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <@natedesimone>
Subject: [edk2-devel] [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: DSC cleanup

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2243

This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to
consolidate redundant sections and better group file content to
improve maintainability and readability.

The same pattern made in this change for WhiskeylakeURvp is being
applied to all existing board packages in Platform/Intel to improve
overall consistency.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <@natedesimone>
Signed-off-by: Michael Kubacki <michael.a.kubacki@...>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 502 +++++++++++---------
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 441 +++++++++--------
2 files changed, 510 insertions(+), 433 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index 1d07fdea84..d6eb66a880 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -1,20 +1,13 @@
## @file
-# Platform description.
-#
+# The main build description file for the WhiskeylakeURvp board.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#
##

[Defines]
- #
- # Set platform specific package/folder name, same as passed from PREBUILD script.
- # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder
- # DEFINE only takes effect at R9 DSC and FDF.
- #
DEFINE PLATFORM_PACKAGE = MinPlatformPkg
DEFINE PLATFORM_SI_PACKAGE = CoffeelakeSiliconPkg
DEFINE PLATFORM_SI_BIN_PACKAGE = CoffeelakeSiliconBinPkg
@@ -24,7 +17,7 @@
DEFINE PROJECT = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)

#
- # Platform On/Off features are defined here
+ # Include PCD configuration for this board.
#
!include OpenBoardPkgPcd.dsc

@@ -42,8 +35,6 @@
SUPPORTED_ARCHITECTURES = IA32|X64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = ALL
-
-
FLASH_DEFINITION = $(PROJECT)/OpenBoardPkg.fdf

FIX_LOAD_TOP_MEMORY_ADDRESS = 0x0
@@ -56,163 +47,238 @@

################################################################################
#
-# SKU Identification section - list of all SKU IDs supported by this
-# Platform.
+# SKU Identification section - list of all SKU IDs supported by this board.
#
################################################################################
[SkuIds]
- 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+ 0|DEFAULT # 0|DEFAULT is reserved and always required.
0x60|WhiskeylakeURvp

################################################################################
#
-# Library Class section - list of all Library Classes needed by this Platform.
+# Includes section - other DSC file contents included for this board build.
#
################################################################################

- !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
- !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
- !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+#######################################
+# Library Includes
+#######################################
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+
+#######################################
+# Component Includes
+#######################################
+[Components.IA32]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
+
+[Components.X64]
+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
+!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
+
+#######################################
+# Build Option Includes
+#######################################
+!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
+!include OpenBoardPkgBuildOption.dsc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this board.
+#
+################################################################################

[LibraryClasses.common]
-
- PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
- ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
-
- PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
- PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
- PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
- I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
-
- PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf
-
- FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
-
+ #######################################
+ # Edk2 Packages
+ #######################################
FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf

- FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
- SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
-
+ #######################################
+ # Silicon Initialization Package
+ #######################################
ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
- BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
- TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
-
- # Tbt
- !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
- TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
- !endif
- DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
- #
- # Silicon Init Package
- #
- !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
- PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxeSmmPchHsioLib.inf
MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf
+ PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxeSmmPchHsioLib.inf
PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf

- TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
-
-[LibraryClasses.IA32]
- #
- # PEI phase common
- #
- SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+ #####################################
+ # Platform Package
+ #####################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
- !if $(TARGET) == DEBUG
- TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
- !endif
- TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
- MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
- BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
- TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+ PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf
+ PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
+ PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
+ I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
+ PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+ # Thunderbolt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+ TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
+!endif

- # Tbt
- !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
- PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
- PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
- !endif
-
- #
- # Silicon Init Package
- #
- !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
- PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf
- PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
- PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
- PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
- !if $(TARGET) == DEBUG
- GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
- !else
- GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
- !endif
+ #######################################
+ # Board-specific
+ #######################################
+ PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookLib.inf

[LibraryClasses.IA32.SEC]
+ #######################################
+ # Platform Package
+ #######################################
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+
+ #######################################
+ # Board Package
+ #######################################
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+ TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+[LibraryClasses.common.PEIM]
+ #######################################
+ # Platform Package
+ #######################################
+ BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+ PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
+ PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
+!endif
+ PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf
+ PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
+ SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf

-[LibraryClasses.X64]
- #
- # DXE phase common
- #
- FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf
- !if $(TARGET) == DEBUG
- TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
- !endif
- TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf
- MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ #######################################
+ # Board-specific
+ #######################################
+ PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
+
+!if $(TARGET) == DEBUG
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
+!else
+ GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
+!endif
+
+[LibraryClasses.common.DXE_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Platform Package
+ #######################################
+ BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf
MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
- BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
+ MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf

- DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf
- #
- # Silicon Init Package
- #
- !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
+ DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
+
+ #######################################
+ # Board-specific
+ #######################################
+ DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
+
[LibraryClasses.X64.DXE_SMM_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+ #######################################
+ # Silicon Initialization Package
+ #######################################
SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
- !if $(TARGET) == DEBUG
- TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
- !endif
- TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
- MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+
+ #######################################
+ # Platform Package
+ #######################################
BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-
-[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
- ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
+ TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf
+!if $(TARGET) == DEBUG
+ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+!endif

[Components.IA32]
- #
- # Common
- #
- !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
-
- #
- # FSP wrapper SEC Core
- #
+ #######################################
+ # Edk2 Packages
+ #######################################
UefiCpuPkg/SecCore/SecCore.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
}

#
- # Silicon
+ # In FSP API mode the policy has to be installed before FSP Wrapper updating UPD.
+ # Add policy as dependency for FSP Wrapper
#
- !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf

- #
- # Platform
- #
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+ IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+
+ #######################################
+ # Platform Package
+ #######################################
$(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
<LibraryClasses>
@@ -223,12 +289,7 @@
!endif
NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
}
- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
- $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf {
- <LibraryClasses>
- SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
- SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
- }
+
$(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
<LibraryClasses>
!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
@@ -237,51 +298,43 @@
NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
!endif
}
- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
-#to do $(PLATFORM_PACKAGE)/FspWrapper/FspWrapperPeim/FspWrapperPeim.inf
+
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
$(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf {
<LibraryClasses>
- SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
- SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
}

- #
- # Security
- #
+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
+!endif

- !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
- $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
- !endif
-
- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
- IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
-
- # Tbt
- !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
- $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
- !endif
+ #######################################
+ # Board Package
+ #######################################
+ # Thunderbolt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
+!endif

[Components.X64]
-
- #
- # Common
- #
- !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
-
- $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
-
- UefiCpuPkg/CpuDxe/CpuDxe.inf
+ #######################################
+ # Edk2 Packages
+ #######################################
+ IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
-
MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
- MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
- MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf

- #
- # Shell
- #
ShellPkg/Application/Shell/Shell.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
@@ -301,57 +354,7 @@
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
}

- #
- # Silicon
- #
- !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
-
- # Tbt
- !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
- $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
- $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
- $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
- !endif
-
- #
- # Platform
- #
- $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
- <LibraryClasses>
- NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
- }
-
- $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf {
- <LibraryClasses>
- SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
- SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
- }
- $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
- IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
-
- $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
-
- $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
- $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
-
- #
- # OS Boot
- #
- !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
- $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
- $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
- $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
- <LibraryClasses>
- !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
- BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
- !else
- NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
- !endif
- }
-
- $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
- $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
-
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
<PcdsPatchableInModule>
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
@@ -360,25 +363,66 @@
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
!endif
}
+!endif

- !endif
-
- #
- # Security
- #
- $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
-
- !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
- $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
- !endif
-
+ #######################################
+ # Silicon Initialization Package
+ #######################################
IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
-
- #
- # Other
- #
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
$(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf

- !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
- !include OpenBoardPkgBuildOption.dsc
+ #######################################
+ # Platform Package
+ #######################################
+ $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf {
+ <LibraryClasses>
+ SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+ SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+ }
+ $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
+ $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf

+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
+ $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+
+ $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
+ BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ !else
+ NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
+ !endif
+ }
+
+ $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
+
+!endif
+
+ #######################################
+ # Board Package
+ #######################################
+ $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
+ <LibraryClasses>
+ NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
+ }
+
+ # Thunderbolt
+!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
+ $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+!endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 24e3da6686..5cf0aa9d86 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,22 +1,24 @@
## @file
-# Platform description.
+# PCD configuration build description file for the WhiskeylakeURvp board.
#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##

################################################################################
#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+# Pcd Section - list of all PCD Entries used by this board.
#
################################################################################
-[PcdsFixedAtBuild]
+
+[PcdsFixedAtBuild.common]
+ ######################################
+ # Key Boot Stage and FSP configuration
+ ######################################
#
- # Please select BootStage here.
+ # Please select the Boot Stage here.
# Stage 1 - enable debug (system deadloop after debug init)
# Stage 2 - mem init (system deadloop after mem init)
# Stage 3 - boot to shell only
@@ -25,56 +27,74 @@
#
gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4

+ #
+ # 0: FSP Wrapper is running in Dispatch mode.
+ # 1: FSP Wrapper is running in API mode.
+ # Note: Dispatch mode is currently NOT supported for this board.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+
+ #
+ # FALSE: The board is not a FSP wrapper (FSP binary not used)
+ # TRUE: The board is a FSP wrapper (FSP binary is used)
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+ gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
+ gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+
+ #
+ # FSP API mode does not share stack with the boot loader,
+ # so FSP needs more temporary memory for FSP heap + stack size.
+ #
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
+ #
+ # FSP API mode does not need to enlarge the boot loader stack size
+ # since the stacks are separate.
+ #
+ gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+
[PcdsFeatureFlag.common]
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
- gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(TARGET) == RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
!endif
-
- gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE
- #
- # More fine granularity control below:
- #
-
- gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
-
-#
-# TRUE is ENABLE. FALSE is DISABLE.
-#
-#
-# BIOS build switches configuration
-#
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ######################################
+ # Silicon Configuration
+ ######################################
+ # Build switches
gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE

-# CPU
+ # CPU
+ gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE

-# SA
+ # SA
+ gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
@@ -82,166 +102,132 @@
gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE

-# ME
+ # ME
gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE

+ # Others
gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
- gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.
- gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
+ gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
+ gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254 timer is used.

- gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
- gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE

-#
-# Override some PCDs for specific build requirements.
-#
- #
- # Disable USB debug message when Source Level Debug is enabled
- # because they cannot be enabled at the same time.
- #
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif

- gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif

- !if $(TARGET) == DEBUG
- gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
- !else
- gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
- !endif
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif

- !if $(TARGET) == DEBUG
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
- !else
- gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
- !endif
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif

- gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif

- #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
-!if $(TARGET) == RELEASE
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
!endif
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
-
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+ ######################################
+ # Board Configuration
+ ######################################
gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
+ gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
+ gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE

[PcdsFixedAtBuild.common]
- gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
- gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
-!endif
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
-!endif
-
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
- gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
-
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
- gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
- gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
- gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
- gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
- gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
-
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000
-
- gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ ######################################
+ # Edk2 Configuration
+ ######################################
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
!else
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
!endif
- gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
- gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
-
-#
-# 8MB Default
-#
-gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
-
-#
-# 16MB TSEG in Debug build only.
-#
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
!if $(TARGET) == DEBUG
- gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
!endif

+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
- gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08

- !if $(TARGET) == RELEASE
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
- !else
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
- !endif
+ # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000

-
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
- !if $(TARGET) == RELEASE
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
- !else
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
- !endif
-
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEAC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFDC0000
+ #
+ # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
+ # (They will be DynamicEx in FSP Dispatch mode)
+ #

## Specifies the size of the microcode Region.
# @Prompt Microcode Region size.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0

- ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
- # @Prompt Timeout for the BSP to detect all APs for the first time.
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
-
## Specifies the AP wait loop state during POST phase.
# The value is defined as below.
# 1: Place AP in the Hlt-Loop state.
@@ -250,6 +236,17 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
# @Prompt The AP wait loop state.
gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2

+ ######################################
+ # Silicon Configuration
+ ######################################
+ gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+
+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2

#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -262,6 +259,19 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
#
gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07

+!if $(TARGET) == RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
+!if $(TARGET) == RELEASE
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
+!endif
+
!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
!endif
@@ -287,75 +297,98 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
!endif

[PcdsFixedAtBuild.IA32]
+ ######################################
+ # Edk2 Configuration
+ ######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000

+ ######################################
+ # Platform Configuration
+ ######################################
+ gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
+
[PcdsFixedAtBuild.X64]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+
# Default platform supported RFC 4646 languages: (American) English
gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"

-
[PcdsPatchableInModule.common]
+ ######################################
+ # Edk2 Configuration
+ ######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046

+ ######################################
+ # Silicon Configuration
+ ######################################
!if $(TARGET) == DEBUG
gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
!endif

-[PcdsDynamicHii.X64.DEFAULT]
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
- gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
-
-!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
-!endif
-
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD50000
- # Platform will pre-allocate UPD buffer and pass it to FspWrapper
- # Those dummy address will be patched before FspWrapper executing
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
-
- ## Specifies max supported number of Logical Processors.
- # @Prompt Configure max supported number of Logical Processors
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
-
-[PcdsDynamicDefault.common.DEFAULT]
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+ ######################################
+ # Edk2 Configuration
+ ######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
#
# Set video to native resolution as Windows 8 WHCK requirement.
#
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0

- gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
-
gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00

-[PcdsDynamicDefault.common.DEFAULT]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0

- # Tbt
- gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13
- gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011
- gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0
- gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0
- gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0
+ # Platform will pre-allocate UPD buffer and pass it to FspWrapper
+ # Those dummy address will be patched before FspWrapper executing
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0

- gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1
- gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1
- gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26
- gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100
- gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16

+ ######################################
+ # Board Configuration
+ ######################################
+
+ # Thunderbolt Configuration
+ gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0
+ gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0
+ gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011
+ gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13
+ gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1
+ gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1
+ gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1
+ gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26
+ gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28
+ gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100
+ gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1
+ gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0
+ gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1
+ gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1
+
+[PcdsDynamicHii.X64.DEFAULT]
+ ######################################
+ # Edk2 Configuration
+ ######################################
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+!endif
--
2.16.2.windows.1