Date   

Re: [PATCH 0/3] Arm builds on Visual Studio

Leif Lindholm
 

Thanks Baptiste,

Ard: I would appreciate if you could sanity check the syntax
conversion in 2/3 - it looks correct to me.

From my point of view, for the series:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

But we also need a nod from the MdePkg maintainers.

/
Leif

On Wed, Sep 18, 2019 at 06:05:21PM +0200, Baptiste Gerondeau wrote:
EDIT: Resending the series since I mistakenly used the wrong email,
sorry !

We are currently making an effort to make ARM (and AARCH64 eventually)
builds using Microsoft's Visual Studio Compiler (aka MSVC/MSFT).

These 3 patches correspond to an effort to make the assembler work with
MSFT, which entails :
- Feeding MSFT the RVCT .asm files, since they share syntax
requirements.
- Fixing some instructions syntax in those .asm files, in order to make
them palatable for MSFT.
- Fixing some minor formatting issue in INF files, while we're at it.

This set enables the assembler, meanwhile the C also require changes,
which will come in a set later. This set makes the RVCT toolchain family
and profiles obsolete, unblocking :
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1750

As mentioned in the above bug, dropping RVCT would entail orphanating
the .asm files that powered the RVCT build. Since Visual Studio uses the
same file syntax, those can be reused to power the VS build.

These patches have been tested on VS2019 (v15.9.11) and VS2017 (v16.0.1)

Baptiste GERONDEAU (3):
ArmPkg/MdePkg : Unify INF files format
ARM/Assembler: Correct syntax from RVCT for MSFT
ARM/Assembler: Reuse RVCT assembler for MSFT build

ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 2 +-
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++++++-------------
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 2 +-
ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 2 +-
ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 2 +-
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++--
ArmPkg/Library/ArmLib/ArmBaseLib.inf | 8 ++++----
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 4 ++--
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 2 +-
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 2 +-
ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 2 +-
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | 2 +-
ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | 2 +-
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 6 +++---
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 6 +++---
ArmPlatformPkg/PrePi/PeiMPCore.inf | 2 +-
ArmPlatformPkg/PrePi/PeiUniCore.inf | 2 +-
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++---------
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 2 +-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 20 ++++++++++----------
MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 2 +-
21 files changed, 65 insertions(+), 59 deletions(-)

--
2.23.0


Re: [PATCH 01/35] DO NOT APPLY: edk2: turn standard handle types into pointers to non-VOID

Leif Lindholm
 

On Wed, Sep 18, 2019 at 08:55:42AM -0700, Andrew Fish via Groups.Io wrote:
#ifndef STRICTER_UEFI_TYPES
typedef VOID *EFI_PEI_FV_HANDLE;
#else
struct EFI_PEI_FV_OBJECT;
typedef struct EFI_PEI_FV_OBJECT *EFI_PEI_FV_HANDLE;
#endif
Technically, this would work well.

However, if we wanted to allow new projects to #define
STRICTER_UEFI_TYPES as their normal mode of operation (and not just for
a sanity check in CI), then we'd have to update the UEFI spec too.

Otherwise, code that is technically spec-conformant (albeit semantically
nonsensical), like I mentioned up-thread, would no longer compile:
I think helping people NOT write nonsensical code is good. It is
very good idea and I'd like to add it to the spec but as you point
out it would break a lot of existing code so I'm not sure it is
possible. I guess we could try to add a strict mode to the spec but
given the types are defined in tables that may be problematic.
I think adding a strict mode to the specification should be doable -
an important aspect is that this should[1] only break *builds* of
existing code, never the execution of existing applications/drivers on
firmware built to the strict mode. (Unless I'm missing something
obvious.)

[1] It is always possible *some* toolchain does something weird that
is already wrong but not visible, and this change would expose the
underlying fault. This is not necessarily bad.

The specification could then describe the problematic types within
#ifdef starements.

Best Regards,

Leif

We have coding standards that are more strict than what the C spec
allows. So I would see the STRICT_UEFI_TYPES as more of a enforce
the coding standard kind of thing?

Thanks,

Andrew Fish

EFI_HANDLE Foobar;
UINT64 Val;

Foobar = &Val;

Thanks
Laszlo




[PATCH 3/3] ARM/Assembler: Reuse RVCT assembler for MSFT build

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <baptiste.gerondeau@linaro.org>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1750"

Since RVCT shares the same assembler syntax as MSFT, use .asm files
and associate them with MSFT, which would be a first step to addressing
the above Bugzilla issue.
RVCT will also have to be erased from BaseTools/rest of the build
infrastructure, to fully address BZ#1750 ; this patch only addresses the
"code" in itself.

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 2 =
+-
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 2 =
+-
ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 2 =
+-
ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 2 =
+-
ArmPkg/Library/ArmLib/ArmBaseLib.inf | 8 =
++++----
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 =
+-
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 2 =
+-
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 2 =
+-
ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 2 =
+-
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | 2 =
+-
ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | 2 =
+-
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 6 =
+++---
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 6 =
+++---
ArmPlatformPkg/PrePi/PeiMPCore.inf | 2 =
+-
ArmPlatformPkg/PrePi/PeiUniCore.inf | 2 =
+-
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 2 =
+-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 =
+++++-----
MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 2 =
+-
18 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/Ar=
mGicLib.inf
index 5e23c732bfab..4fccb938eb6d 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -22,7 +22,7 @@ [Sources]
=0D
[Sources.ARM]=0D
GicV3/Arm/ArmGicV3.S | GCC=0D
- GicV3/Arm/ArmGicV3.asm | RVCT=0D
+ GicV3/Arm/ArmGicV3.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
GicV3/AArch64/ArmGicV3.S=0D
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf b/ArmPkg/Li=
brary/ArmExceptionLib/ArmExceptionLib.inf
index fdb9c24d21bc..58b2ddbff858 100644
--- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
@@ -33,7 +33,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmException.c=0D
- Arm/ExceptionSupport.asm | RVCT=0D
+ Arm/ExceptionSupport.asm | MSFT=0D
Arm/ExceptionSupport.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf b/A=
rmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
index ef1a43a27c45..a404ca2ccf82 100644
--- a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
+++ b/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
@@ -28,7 +28,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmException.c=0D
- Arm/ExceptionSupport.asm | RVCT=0D
+ Arm/ExceptionSupport.asm | MSFT=0D
Arm/ExceptionSupport.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf b/ArmPkg/Library/ArmHvc=
Lib/ArmHvcLib.inf
index 69f68f63d7a6..be8d8a228865 100644
--- a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+++ b/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
@@ -15,7 +15,7 @@ [Defines]
LIBRARY_CLASS =3D ArmHvcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmHvc.asm | RVCT=0D
+ Arm/ArmHvc.asm | MSFT=0D
Arm/ArmHvc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A=
rmBaseLib.inf
index 5e70990872f2..63e175623393 100644
--- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf
+++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf
@@ -30,10 +30,10 @@ [Sources.ARM]
Arm/ArmV7Support.S | GCC=0D
Arm/ArmV7ArchTimerSupport.S | GCC=0D
=0D
- Arm/ArmLibSupport.asm | RVCT=0D
- Arm/ArmLibSupportV7.asm | RVCT=0D
- Arm/ArmV7Support.asm | RVCT=0D
- Arm/ArmV7ArchTimerSupport.asm | RVCT=0D
+ Arm/ArmLibSupport.asm | MSFT=0D
+ Arm/ArmLibSupportV7.asm | MSFT=0D
+ Arm/ArmV7Support.asm | MSFT=0D
+ Arm/ArmV7ArchTimerSupport.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
AArch64/AArch64Lib.h=0D
diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar=
mMmuLib/ArmMmuBaseLib.inf
index 33dddf1e2b97..44366f02c6d9 100644
--- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
@@ -23,7 +23,7 @@ [Sources.AARCH64]
[Sources.ARM]=0D
Arm/ArmMmuLibCore.c=0D
Arm/ArmMmuLibV7Support.S | GCC=0D
- Arm/ArmMmuLibV7Support.asm |RVCT =0D
+ Arm/ArmMmuLibV7Support.asm | MSFT=0D
=0D
[Packages]=0D
ArmPkg/ArmPkg.dec=0D
diff --git a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf b/ArmPkg/Library/ArmSmc=
Lib/ArmSmcLib.inf
index 4f4b09f4528a..af8c0e53cc2b 100644
--- a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+++ b/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
@@ -14,7 +14,7 @@ [Defines]
LIBRARY_CLASS =3D ArmSmcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmSmc.asm | RVCT=0D
+ Arm/ArmSmc.asm | MSFT=0D
Arm/ArmSmc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemL=
ib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.i=
nf
index fa19bf649131..f4c9e5510b9a 100644
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
@@ -21,7 +21,7 @@ [Sources.AARCH64]
=0D
[Sources.ARM]=0D
Arm/Reset.S | GCC=0D
- Arm/Reset.asm | RVCT=0D
+ Arm/Reset.asm | MSFT=0D
=0D
[Sources]=0D
ArmSmcPsciResetSystemLib.c=0D
diff --git a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf b/ArmPkg/Library/ArmSvc=
Lib/ArmSvcLib.inf
index 744a29fbf723..6631e40df130 100644
--- a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
+++ b/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
@@ -14,7 +14,7 @@ [Defines]
LIBRARY_CLASS =3D ArmSvcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmSvc.asm | RVCT=0D
+ Arm/ArmSvc.asm | MSFT=0D
Arm/ArmSvc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.i=
nf b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
index e0d0028d8224..cc791a3a68fd 100644
--- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
+++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
@@ -29,7 +29,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmPlatformHelper.S | GCC=0D
- Arm/ArmPlatformHelper.asm | RVCT=0D
+ Arm/ArmPlatformHelper.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArmPlatformHelper.S=0D
diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib=
.inf b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
index 76f809c80d9f..e88330c1c382 100644
--- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
@@ -21,7 +21,7 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec=0D
=0D
[Sources.ARM]=0D
- Arm/ArmPlatformStackLib.asm | RVCT=0D
+ Arm/ArmPlatformStackLib.asm | MSFT=0D
Arm/ArmPlatformStackLib.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPk=
g/PrePeiCore/PrePeiCoreMPCore.inf
index f2ac45d171bc..b663ff749182 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -21,11 +21,11 @@ [Sources.common]
=0D
[Sources.ARM]=0D
Arm/ArchPrePeiCore.c=0D
- Arm/PrePeiCoreEntryPoint.asm | RVCT=0D
+ Arm/PrePeiCoreEntryPoint.asm | MSFT=0D
Arm/PrePeiCoreEntryPoint.S | GCC=0D
- Arm/SwitchStack.asm | RVCT=0D
+ Arm/SwitchStack.asm | MSFT=0D
Arm/SwitchStack.S | GCC=0D
- Arm/Exception.asm | RVCT=0D
+ Arm/Exception.asm | MSFT=0D
Arm/Exception.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformP=
kg/PrePeiCore/PrePeiCoreUniCore.inf
index 84c319c3679b..6d05ed096c4c 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
@@ -21,11 +21,11 @@ [Sources.common]
=0D
[Sources.ARM]=0D
Arm/ArchPrePeiCore.c=0D
- Arm/PrePeiCoreEntryPoint.asm | RVCT=0D
+ Arm/PrePeiCoreEntryPoint.asm | MSFT=0D
Arm/PrePeiCoreEntryPoint.S | GCC=0D
- Arm/SwitchStack.asm | RVCT=0D
+ Arm/SwitchStack.asm | MSFT=0D
Arm/SwitchStack.S | GCC=0D
- Arm/Exception.asm | RVCT=0D
+ Arm/Exception.asm | MSFT=0D
Arm/Exception.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiM=
PCore.inf
index 9c5da0d42a7b..fd2a35e59591 100644
--- a/ArmPlatformPkg/PrePi/PeiMPCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf
@@ -22,7 +22,7 @@ [Sources]
[Sources.ARM]=0D
Arm/ArchPrePi.c=0D
Arm/ModuleEntryPoint.S | GCC=0D
- Arm/ModuleEntryPoint.asm | RVCT=0D
+ Arm/ModuleEntryPoint.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArchPrePi.c=0D
diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/Pei=
UniCore.inf
index ee9b05b25337..de3abadfeac6 100644
--- a/ArmPlatformPkg/PrePi/PeiUniCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf
@@ -22,7 +22,7 @@ [Sources]
[Sources.ARM]=0D
Arm/ArchPrePi.c=0D
Arm/ModuleEntryPoint.S | GCC=0D
- Arm/ModuleEntryPoint.asm | RVCT=0D
+ Arm/ModuleEntryPoint.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArchPrePi.c=0D
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.in=
f b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
index ad68f841fb6b..62b46377116c 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
@@ -31,7 +31,7 @@ [Sources]
[Sources.ARM]=0D
IoLibArmVirt.c=0D
Arm/ArmVirtMmio.S | GCC=0D
- Arm/ArmVirtMmio.asm | RVCT=0D
+ Arm/ArmVirtMmio.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
IoLibArmVirt.c=0D
diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M=
dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
index d38e1397eee1..79ba2a2dfc39 100644
--- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
@@ -85,11 +85,11 @@ [Sources.ARM]
Arm/CompareMem.S | GCC=0D
Arm/CompareGuid.S | GCC=0D
=0D
- Arm/ScanMem.asm |RVCT=0D
- Arm/SetMem.asm |RVCT=0D
- Arm/CopyMem.asm |RVCT=0D
- Arm/CompareMem.asm |RVCT=0D
- Arm/CompareGuid.asm |RVCT=0D
+ Arm/ScanMem.asm | MSFT=0D
+ Arm/SetMem.asm | MSFT=0D
+ Arm/CopyMem.asm | MSFT=0D
+ Arm/CompareMem.asm | MSFT=0D
+ Arm/CompareGuid.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
AArch64/ScanMem.S=0D
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i=
nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63eb..39c503a28a2c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -70,7 +70,7 @@ [Sources.EBC]
=0D
[Sources.ARM]=0D
Synchronization.c=0D
- Arm/Synchronization.asm | RVCT=0D
+ Arm/Synchronization.asm | MSFT=0D
Arm/Synchronization.S | GCC=0D
=0D
[Sources.AARCH64]=0D
--=20
2.23.0


[PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <baptiste.gerondeau@linaro.org>

RVCT and MSFT's ARM assembler share the same file syntax, but some
instructions use pre-UAL syntax that is not picked up
by MSFT's ARM assembler, this commit translates those instructions
into MSFT-buildable ones (subset of UAL/THUMB).

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++=
++++-------------
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++--
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++----=
-----
3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmP=
kg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
index aa0229d2e85f..880246bd6206 100644
--- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
+++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
@@ -90,7 +90,7 @@ Fiq
ResetEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -102,7 +102,7 @@ UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in Commo=
nExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -113,7 +113,7 @@ UndefinedInstructionEntry
SoftwareInterruptEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -125,7 +125,7 @@ PrefetchAbortEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -137,7 +137,7 @@ DataAbortEntry
sub LR,LR,#8=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -148,7 +148,7 @@ DataAbortEntry
ReservedExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -160,7 +160,7 @@ IrqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -172,7 +172,7 @@ FiqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
; Since we have already switch to SV=
C R8_fiq - R12_fiq=0D
@@ -213,9 +213,11 @@ AsmCommonExceptionEntry
and R3, R1, #0x1f ; Check CPSR to see if User or System =
Mode=0D
cmp R3, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R3, #0x10 ;=0D
- stmeqed R2, {lr}^ ; save unbanked lr=0D
+ mrseq R8, lr_usr ; save unbanked lr to R8=0D
+ streq R2, [R8] ; make R2 point to R8=0D
; else=0D
- stmneed R2, {lr} ; save SVC lr=0D
+ mrsne R8, lr_svc ; save SVC lr to R8=0D
+ strne R2, [R8] ; make R2 point to R8=0D
=0D
=0D
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd=0D
@@ -280,15 +282,17 @@ CommonCExceptionHandler (
and R1, R1, #0x1f ; Check to see if User or System Mode=
=0D
cmp R1, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R1, #0x10 ;=0D
- ldmeqed R2, {lr}^ ; restore unbanked lr=0D
+ ldreq R8, [R2] ; load sys/usr lr from R2 pointer=0D
+ msreq lr_usr, R8 ; restore unbanked lr=0D
; else=0D
- ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
+ ldrne R8, [R3] ; load SVC lr from R3 pointer=0D
+ msrne lr_svc, R8 ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
=0D
ldmfd SP!,{R0-R12} ; Restore general purpose registers=0D
; Exception handler can not change SP=
=0D
=0D
add SP,SP,#0x20 ; Clear out the remaining stack space=
=0D
- ldmfd SP!,{LR} ; restore the link register for this c=
ontext=0D
+ pop {LR} ; restore the link register for this c=
ontext=0D
rfefd SP! ; return from exception via srsfd stac=
k slot=0D
=0D
END=0D
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/Ar=
mLib/Arm/ArmV7Support.asm
index 3146c2b52181..724306399e6c 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
@@ -200,8 +200,10 @@ Loop2
mov R9, R4 ; R9 working copy of the max way size (rig=
ht aligned)=0D
=0D
Loop3=0D
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache numbe=
r into R11=0D
- orr R0, R0, R7, LSL R2 ; factor in the index number=0D
+ lsl R8, R9, R5=0D
+ orr R0, R10, R8 ; factor in the way number and cache numbe=
r=0D
+ lsl R8, R7, R2=0D
+ orr R0, R0, R8 ; factor in the index number=0D
=0D
blx R1=0D
=0D
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm b/MdePkg=
/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
index 5a423df16bff..a46d70e41433 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
@@ -5,16 +5,16 @@
;=0D
=0D
=0D
-AREA IoLibMmio, CODE, READONLY=0D
+ AREA IoLibMmio, CODE, READONLY=0D
=0D
-EXPORT MmioRead8Internal=0D
-EXPORT MmioWrite8Internal=0D
-EXPORT MmioRead16Internal=0D
-EXPORT MmioWrite16Internal=0D
-EXPORT MmioRead32Internal=0D
-EXPORT MmioWrite32Internal=0D
-EXPORT MmioRead64Internal=0D
-EXPORT MmioWrite64Internal=0D
+ EXPORT MmioRead8Internal=0D
+ EXPORT MmioWrite8Internal=0D
+ EXPORT MmioRead16Internal=0D
+ EXPORT MmioWrite16Internal=0D
+ EXPORT MmioRead32Internal=0D
+ EXPORT MmioWrite32Internal=0D
+ EXPORT MmioRead64Internal=0D
+ EXPORT MmioWrite64Internal=0D
=0D
;=0D
; Reads an 8-bit MMIO register.=0D
--=20
2.23.0


[PATCH 1/3] ArmPkg/MdePkg : Unify INF files format

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <baptiste.gerondeau@linaro.org>

Add a space between the '|' and the name of the toolchain to use,
as is the case in all other INF files.
Note that I did not touch the RVCT lines, since a following commit in
the set will address those.

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 +-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar=
mMmuLib/ArmMmuBaseLib.inf
index f4fecbb4098a..33dddf1e2b97 100644
--- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
@@ -22,7 +22,7 @@ [Sources.AARCH64]
=0D
[Sources.ARM]=0D
Arm/ArmMmuLibCore.c=0D
- Arm/ArmMmuLibV7Support.S |GCC =0D
+ Arm/ArmMmuLibV7Support.S | GCC=0D
Arm/ArmMmuLibV7Support.asm |RVCT =0D
=0D
[Packages]=0D
diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M=
dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
index e4e3d532e7b8..d38e1397eee1 100644
--- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
@@ -79,11 +79,11 @@ [Defines.ARM, Defines.AARCH64]
LIBRARY_CLASS =3D BaseMemoryLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER U=
EFI_DRIVER UEFI_APPLICATION=0D
=0D
[Sources.ARM]=0D
- Arm/ScanMem.S |GCC=0D
- Arm/SetMem.S |GCC=0D
- Arm/CopyMem.S |GCC=0D
- Arm/CompareMem.S |GCC=0D
- Arm/CompareGuid.S |GCC=0D
+ Arm/ScanMem.S | GCC=0D
+ Arm/SetMem.S | GCC=0D
+ Arm/CopyMem.S | GCC=0D
+ Arm/CompareMem.S | GCC=0D
+ Arm/CompareGuid.S | GCC=0D
=0D
Arm/ScanMem.asm |RVCT=0D
Arm/SetMem.asm |RVCT=0D
--=20
2.23.0


Re: [PATCH 01/35] DO NOT APPLY: edk2: turn standard handle types into pointers to non-VOID

Andrew Fish
 



On Sep 18, 2019, at 1:41 AM, Laszlo Ersek <lersek@...> wrote:

On 09/17/19 22:22, Andrew Fish wrote:


On Sep 17, 2019, at 1:06 PM, Ni, Ray <ray.ni@...> wrote:

Laszlo,
Thank you very much for this work.
They are quite helpful to detect potential issues.

But without this specific patch being checked in, future break will still happen.
I don't want it to be checked in ASAP because I know that there are quite a lot of close source code that may get build break due to this change.
Besides that, what prevent you make the decision to check in the changes?


Ray,

I was thinking the same thing. Could we make this an optional feature via a #define? We could always default to the Spec Behavior, and new projects could opt into the stricter version. 

#ifndef STRICTER_UEFI_TYPES
typedef VOID    *EFI_PEI_FV_HANDLE;
#else
struct EFI_PEI_FV_OBJECT;
typedef struct EFI_PEI_FV_OBJECT *EFI_PEI_FV_HANDLE;
#endif

Technically, this would work well.

However, if we wanted to allow new projects to #define
STRICTER_UEFI_TYPES as their normal mode of operation (and not just for
a sanity check in CI), then we'd have to update the UEFI spec too.

Otherwise, code that is technically spec-conformant (albeit semantically
nonsensical), like I mentioned up-thread, would no longer compile:


Laszlo,

I think helping people NOT write nonsensical code is good. It is very good idea and I'd like to add it to the spec but as you point out it would break a lot of existing code so I'm not sure it is possible. I guess we could try to add a strict mode to the spec but given the types are defined in tables that may be problematic. 

We have coding standards that are more strict than what the C spec allows. So I would see the STRICT_UEFI_TYPES as more of a enforce the coding standard kind of thing? 

Thanks,

Andrew Fish

 EFI_HANDLE Foobar;
 UINT64     Val;

 Foobar = &Val;

Thanks
Laszlo



[Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock

John E Lofgren
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
V3 changes:
change to mov instruction (non locking instuction) instead
of xchg to simplify design.

V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used

Split lock happens when a locking instruction is used on mis-aligned data
that crosses two cachelines. If close source platform enables Alignment Check
Exception(#AC), They can hit a double fault due to split lock being in
CpuExceptionHandlerLib.

sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.

Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
---
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 4db1a09f28..19198f2731 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -184,17 +184,19 @@ HasErrorCode:
push rax
push rax
sidt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ mov bx, word [rsp]
+ mov rax, qword [rsp + 2]
+ mov qword [rsp], rax
+ mov word [rsp + 8], bx

xor rax, rax
push rax
push rax
sgdt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ mov bx, word [rsp]
+ mov rax, qword [rsp + 2]
+ mov qword [rsp], rax
+ mov word [rsp + 8], bx

;; UINT64 Ldtr, Tr;
xor rax, rax
--
2.16.2.windows.1


Re: [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock

John E Lofgren
 

Sorry. I forgot amend it to the commit. Ill fix it.

Sorry Again,
John

-----Original Message-----
From: Laszlo Ersek [mailto:lersek@redhat.com]
Sent: Wednesday, September 18, 2019 1:52 AM
To: devel@edk2.groups.io; Lofgren, John E <john.e.lofgren@intel.com>
Subject: Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix
split lock

On 09/18/19 00:49, John E Lofgren wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
V3 changes:
change to mov instruction (non locking instuction) instead of xchg to
simplify design.
I think something's wrong -- the v3 update described above isn't actually
implemented in the patch (it continues using XCHG, rather than MOV).

Thanks
Laszlo


V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used

Split lock happens when a locking instruction is used on mis-aligned
data that crosses two cachelines. If close source platform enables
Alignment Check Exception(#AC), They can hit a double fault due to
split lock being in CpuExceptionHandlerLib.

sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.

Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
---

UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas
m
| 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)

diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
sm
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
sm
index 4db1a09f28..7b7642b290 100644
---
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.na
sm
+++
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs
+++ m.nasm
@@ -180,21 +180,29 @@ HasErrorCode:
push qword [rbp + 24]

;; UINT64 Gdtr[2], Idtr[2];
+ ; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes =
limit.
+ ; To avoid #AC split lock when separating base and limit into their
+ ; own separate 64 bit memory, we can’t use 64 bit xchg since base [63:48]
bits
+ ; may cross the cache line.
xor rax, rax
push rax
push rax
sidt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]

xor rax, rax
push rax
push rax
sgdt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]

;; UINT64 Ldtr, Tr;
xor rax, rax


Re: [PATCH 01/35] DO NOT APPLY: edk2: turn standard handle types into pointers to non-VOID

Michael D Kinney
 

-----Original Message-----
From: Laszlo Ersek <lersek@redhat.com>
Sent: Wednesday, September 18, 2019 1:42 AM
To: Andrew Fish <afish@apple.com>; Ni, Ray
<ray.ni@intel.com>
Cc: devel@edk2.groups.io; Achin Gupta
<achin.gupta@arm.com>; Anthony Perard
<anthony.perard@citrix.com>; Ard Biesheuvel
<ard.biesheuvel@linaro.org>; You, Benjamin
<benjamin.you@intel.com>; Zhang, Chao B
<chao.b.zhang@intel.com>; Bi, Dandan
<dandan.bi@intel.com>; David Woodhouse
<dwmw2@infradead.org>; Dong, Eric
<eric.dong@intel.com>; Dong, Guo <guo.dong@intel.com>;
Wu, Hao A <hao.a.wu@intel.com>; Carsey, Jaben
<jaben.carsey@intel.com>; Wang, Jian J
<jian.j.wang@intel.com>; Wu, Jiaxin
<jiaxin.wu@intel.com>; Yao, Jiewen
<jiewen.yao@intel.com>; Justen, Jordan L
<jordan.l.justen@intel.com>; Julien Grall
<julien.grall@arm.com>; Leif Lindholm
<leif.lindholm@linaro.org>; Gao, Liming
<liming.gao@intel.com>; Ma, Maurice
<maurice.ma@intel.com>; Kinney, Michael D
<michael.d.kinney@intel.com>; Fu, Siyuan
<siyuan.fu@intel.com>; Supreeth Venkatesh
<supreeth.venkatesh@arm.com>; Gao, Zhichao
<zhichao.gao@intel.com>
Subject: Re: [edk2-devel] [PATCH 01/35] DO NOT APPLY:
edk2: turn standard handle types into pointers to non-
VOID

On 09/17/19 22:22, Andrew Fish wrote:


On Sep 17, 2019, at 1:06 PM, Ni, Ray
<ray.ni@intel.com> wrote:

Laszlo,
Thank you very much for this work.
They are quite helpful to detect potential issues.

But without this specific patch being checked in,
future break will still happen.
I don't want it to be checked in ASAP because I know
that there are quite a lot of close source code that
may get build break due to this change.
Besides that, what prevent you make the decision to
check in the changes?
Ray,

I was thinking the same thing. Could we make this an
optional feature via a #define? We could always default
to the Spec Behavior, and new projects could opt into
the stricter version.

#ifndef STRICTER_UEFI_TYPES
typedef VOID *EFI_PEI_FV_HANDLE;
#else
struct EFI_PEI_FV_OBJECT;
typedef struct EFI_PEI_FV_OBJECT *EFI_PEI_FV_HANDLE;
#endif

Technically, this would work well.

However, if we wanted to allow new projects to #define
STRICTER_UEFI_TYPES as their normal mode of operation
(and not just for a sanity check in CI), then we'd have
to update the UEFI spec too.

Otherwise, code that is technically spec-conformant
(albeit semantically nonsensical), like I mentioned up-
thread, would no longer compile:

EFI_HANDLE Foobar;
UINT64 Val;

Foobar = &Val;
Does this example build without warnings on all compilers.
I thought we usually have to add some typecasts:

Foobar = (EFI_HANDLE)&Val;

Or

Foobar = (EFI_HANDLE)(UINTN)&Val;

For examples like this, adding an explicit typecast would be an
improvement. So finding and reviewing and fixing these would be
a good improvement.


Thanks
Laszlo


[PATCH 3/3] ARM/Assembler: Reuse RVCT assembler for MSFT build

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <bgerondeau@gmail.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1750"

Since RVCT shares the same assembler syntax as MSFT, use .asm files
and associate them with MSFT, which would be a first step to addressing
the above Bugzilla issue.
RVCT will also have to be erased from BaseTools/rest of the build
infrastructure, to fully address BZ#1750 ; this patch only addresses the
"code" in itself.

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 2 =
+-
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 2 =
+-
ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 2 =
+-
ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 2 =
+-
ArmPkg/Library/ArmLib/ArmBaseLib.inf | 8 =
++++----
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 =
+-
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 2 =
+-
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 2 =
+-
ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 2 =
+-
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | 2 =
+-
ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | 2 =
+-
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 6 =
+++---
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 6 =
+++---
ArmPlatformPkg/PrePi/PeiMPCore.inf | 2 =
+-
ArmPlatformPkg/PrePi/PeiUniCore.inf | 2 =
+-
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 2 =
+-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 =
+++++-----
MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 2 =
+-
18 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/Ar=
mGicLib.inf
index 5e23c732bfab..4fccb938eb6d 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf
@@ -22,7 +22,7 @@ [Sources]
=0D
[Sources.ARM]=0D
GicV3/Arm/ArmGicV3.S | GCC=0D
- GicV3/Arm/ArmGicV3.asm | RVCT=0D
+ GicV3/Arm/ArmGicV3.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
GicV3/AArch64/ArmGicV3.S=0D
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf b/ArmPkg/Li=
brary/ArmExceptionLib/ArmExceptionLib.inf
index fdb9c24d21bc..58b2ddbff858 100644
--- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
@@ -33,7 +33,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmException.c=0D
- Arm/ExceptionSupport.asm | RVCT=0D
+ Arm/ExceptionSupport.asm | MSFT=0D
Arm/ExceptionSupport.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf b/A=
rmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
index ef1a43a27c45..a404ca2ccf82 100644
--- a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
+++ b/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
@@ -28,7 +28,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmException.c=0D
- Arm/ExceptionSupport.asm | RVCT=0D
+ Arm/ExceptionSupport.asm | MSFT=0D
Arm/ExceptionSupport.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf b/ArmPkg/Library/ArmHvc=
Lib/ArmHvcLib.inf
index 69f68f63d7a6..be8d8a228865 100644
--- a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
+++ b/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
@@ -15,7 +15,7 @@ [Defines]
LIBRARY_CLASS =3D ArmHvcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmHvc.asm | RVCT=0D
+ Arm/ArmHvc.asm | MSFT=0D
Arm/ArmHvc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A=
rmBaseLib.inf
index 5e70990872f2..63e175623393 100644
--- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf
+++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf
@@ -30,10 +30,10 @@ [Sources.ARM]
Arm/ArmV7Support.S | GCC=0D
Arm/ArmV7ArchTimerSupport.S | GCC=0D
=0D
- Arm/ArmLibSupport.asm | RVCT=0D
- Arm/ArmLibSupportV7.asm | RVCT=0D
- Arm/ArmV7Support.asm | RVCT=0D
- Arm/ArmV7ArchTimerSupport.asm | RVCT=0D
+ Arm/ArmLibSupport.asm | MSFT=0D
+ Arm/ArmLibSupportV7.asm | MSFT=0D
+ Arm/ArmV7Support.asm | MSFT=0D
+ Arm/ArmV7ArchTimerSupport.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
AArch64/AArch64Lib.h=0D
diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar=
mMmuLib/ArmMmuBaseLib.inf
index 33dddf1e2b97..44366f02c6d9 100644
--- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
@@ -23,7 +23,7 @@ [Sources.AARCH64]
[Sources.ARM]=0D
Arm/ArmMmuLibCore.c=0D
Arm/ArmMmuLibV7Support.S | GCC=0D
- Arm/ArmMmuLibV7Support.asm |RVCT =0D
+ Arm/ArmMmuLibV7Support.asm | MSFT=0D
=0D
[Packages]=0D
ArmPkg/ArmPkg.dec=0D
diff --git a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf b/ArmPkg/Library/ArmSmc=
Lib/ArmSmcLib.inf
index 4f4b09f4528a..af8c0e53cc2b 100644
--- a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+++ b/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
@@ -14,7 +14,7 @@ [Defines]
LIBRARY_CLASS =3D ArmSmcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmSmc.asm | RVCT=0D
+ Arm/ArmSmc.asm | MSFT=0D
Arm/ArmSmc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemL=
ib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.i=
nf
index fa19bf649131..f4c9e5510b9a 100644
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
@@ -21,7 +21,7 @@ [Sources.AARCH64]
=0D
[Sources.ARM]=0D
Arm/Reset.S | GCC=0D
- Arm/Reset.asm | RVCT=0D
+ Arm/Reset.asm | MSFT=0D
=0D
[Sources]=0D
ArmSmcPsciResetSystemLib.c=0D
diff --git a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf b/ArmPkg/Library/ArmSvc=
Lib/ArmSvcLib.inf
index 744a29fbf723..6631e40df130 100644
--- a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
+++ b/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
@@ -14,7 +14,7 @@ [Defines]
LIBRARY_CLASS =3D ArmSvcLib=0D
=0D
[Sources.ARM]=0D
- Arm/ArmSvc.asm | RVCT=0D
+ Arm/ArmSvc.asm | MSFT=0D
Arm/ArmSvc.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.i=
nf b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
index e0d0028d8224..cc791a3a68fd 100644
--- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
+++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf
@@ -29,7 +29,7 @@ [Sources.common]
=0D
[Sources.Arm]=0D
Arm/ArmPlatformHelper.S | GCC=0D
- Arm/ArmPlatformHelper.asm | RVCT=0D
+ Arm/ArmPlatformHelper.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArmPlatformHelper.S=0D
diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib=
.inf b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
index 76f809c80d9f..e88330c1c382 100644
--- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
@@ -21,7 +21,7 @@ [Packages]
ArmPlatformPkg/ArmPlatformPkg.dec=0D
=0D
[Sources.ARM]=0D
- Arm/ArmPlatformStackLib.asm | RVCT=0D
+ Arm/ArmPlatformStackLib.asm | MSFT=0D
Arm/ArmPlatformStackLib.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPk=
g/PrePeiCore/PrePeiCoreMPCore.inf
index f2ac45d171bc..b663ff749182 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -21,11 +21,11 @@ [Sources.common]
=0D
[Sources.ARM]=0D
Arm/ArchPrePeiCore.c=0D
- Arm/PrePeiCoreEntryPoint.asm | RVCT=0D
+ Arm/PrePeiCoreEntryPoint.asm | MSFT=0D
Arm/PrePeiCoreEntryPoint.S | GCC=0D
- Arm/SwitchStack.asm | RVCT=0D
+ Arm/SwitchStack.asm | MSFT=0D
Arm/SwitchStack.S | GCC=0D
- Arm/Exception.asm | RVCT=0D
+ Arm/Exception.asm | MSFT=0D
Arm/Exception.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformP=
kg/PrePeiCore/PrePeiCoreUniCore.inf
index 84c319c3679b..6d05ed096c4c 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
@@ -21,11 +21,11 @@ [Sources.common]
=0D
[Sources.ARM]=0D
Arm/ArchPrePeiCore.c=0D
- Arm/PrePeiCoreEntryPoint.asm | RVCT=0D
+ Arm/PrePeiCoreEntryPoint.asm | MSFT=0D
Arm/PrePeiCoreEntryPoint.S | GCC=0D
- Arm/SwitchStack.asm | RVCT=0D
+ Arm/SwitchStack.asm | MSFT=0D
Arm/SwitchStack.S | GCC=0D
- Arm/Exception.asm | RVCT=0D
+ Arm/Exception.asm | MSFT=0D
Arm/Exception.S | GCC=0D
=0D
[Sources.AARCH64]=0D
diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiM=
PCore.inf
index 9c5da0d42a7b..fd2a35e59591 100644
--- a/ArmPlatformPkg/PrePi/PeiMPCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf
@@ -22,7 +22,7 @@ [Sources]
[Sources.ARM]=0D
Arm/ArchPrePi.c=0D
Arm/ModuleEntryPoint.S | GCC=0D
- Arm/ModuleEntryPoint.asm | RVCT=0D
+ Arm/ModuleEntryPoint.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArchPrePi.c=0D
diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/Pei=
UniCore.inf
index ee9b05b25337..de3abadfeac6 100644
--- a/ArmPlatformPkg/PrePi/PeiUniCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf
@@ -22,7 +22,7 @@ [Sources]
[Sources.ARM]=0D
Arm/ArchPrePi.c=0D
Arm/ModuleEntryPoint.S | GCC=0D
- Arm/ModuleEntryPoint.asm | RVCT=0D
+ Arm/ModuleEntryPoint.asm | MSFT=0D
=0D
[Sources.AArch64]=0D
AArch64/ArchPrePi.c=0D
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.in=
f b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
index ad68f841fb6b..62b46377116c 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
@@ -31,7 +31,7 @@ [Sources]
[Sources.ARM]=0D
IoLibArmVirt.c=0D
Arm/ArmVirtMmio.S | GCC=0D
- Arm/ArmVirtMmio.asm | RVCT=0D
+ Arm/ArmVirtMmio.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
IoLibArmVirt.c=0D
diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M=
dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
index d38e1397eee1..79ba2a2dfc39 100644
--- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
@@ -85,11 +85,11 @@ [Sources.ARM]
Arm/CompareMem.S | GCC=0D
Arm/CompareGuid.S | GCC=0D
=0D
- Arm/ScanMem.asm |RVCT=0D
- Arm/SetMem.asm |RVCT=0D
- Arm/CopyMem.asm |RVCT=0D
- Arm/CompareMem.asm |RVCT=0D
- Arm/CompareGuid.asm |RVCT=0D
+ Arm/ScanMem.asm | MSFT=0D
+ Arm/SetMem.asm | MSFT=0D
+ Arm/CopyMem.asm | MSFT=0D
+ Arm/CompareMem.asm | MSFT=0D
+ Arm/CompareGuid.asm | MSFT=0D
=0D
[Sources.AARCH64]=0D
AArch64/ScanMem.S=0D
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i=
nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19b63eb..39c503a28a2c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -70,7 +70,7 @@ [Sources.EBC]
=0D
[Sources.ARM]=0D
Synchronization.c=0D
- Arm/Synchronization.asm | RVCT=0D
+ Arm/Synchronization.asm | MSFT=0D
Arm/Synchronization.S | GCC=0D
=0D
[Sources.AARCH64]=0D
--=20
2.23.0


[PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <bgerondeau@gmail.com>

RVCT and MSFT's ARM assembler share the same file syntax, but some
instructions use pre-UAL syntax that is not picked up
by MSFT's ARM assembler, this commit translates those instructions
into MSFT-buildable ones (subset of UAL/THUMB).

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++=
++++-------------
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++--
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++----=
-----
3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmP=
kg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
index aa0229d2e85f..880246bd6206 100644
--- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
+++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
@@ -90,7 +90,7 @@ Fiq
ResetEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -102,7 +102,7 @@ UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in Commo=
nExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -113,7 +113,7 @@ UndefinedInstructionEntry
SoftwareInterruptEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -125,7 +125,7 @@ PrefetchAbortEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -137,7 +137,7 @@ DataAbortEntry
sub LR,LR,#8=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -148,7 +148,7 @@ DataAbortEntry
ReservedExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -160,7 +160,7 @@ IrqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -172,7 +172,7 @@ FiqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
; Since we have already switch to SV=
C R8_fiq - R12_fiq=0D
@@ -213,9 +213,11 @@ AsmCommonExceptionEntry
and R3, R1, #0x1f ; Check CPSR to see if User or System =
Mode=0D
cmp R3, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R3, #0x10 ;=0D
- stmeqed R2, {lr}^ ; save unbanked lr=0D
+ mrseq R8, lr_usr ; save unbanked lr to R8=0D
+ streq R2, [R8] ; make R2 point to R8=0D
; else=0D
- stmneed R2, {lr} ; save SVC lr=0D
+ mrsne R8, lr_svc ; save SVC lr to R8=0D
+ strne R2, [R8] ; make R2 point to R8=0D
=0D
=0D
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd=0D
@@ -280,15 +282,17 @@ CommonCExceptionHandler (
and R1, R1, #0x1f ; Check to see if User or System Mode=
=0D
cmp R1, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R1, #0x10 ;=0D
- ldmeqed R2, {lr}^ ; restore unbanked lr=0D
+ ldreq R8, [R2] ; load sys/usr lr from R2 pointer=0D
+ msreq lr_usr, R8 ; restore unbanked lr=0D
; else=0D
- ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
+ ldrne R8, [R3] ; load SVC lr from R3 pointer=0D
+ msrne lr_svc, R8 ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
=0D
ldmfd SP!,{R0-R12} ; Restore general purpose registers=0D
; Exception handler can not change SP=
=0D
=0D
add SP,SP,#0x20 ; Clear out the remaining stack space=
=0D
- ldmfd SP!,{LR} ; restore the link register for this c=
ontext=0D
+ pop {LR} ; restore the link register for this c=
ontext=0D
rfefd SP! ; return from exception via srsfd stac=
k slot=0D
=0D
END=0D
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/Ar=
mLib/Arm/ArmV7Support.asm
index 3146c2b52181..724306399e6c 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
@@ -200,8 +200,10 @@ Loop2
mov R9, R4 ; R9 working copy of the max way size (rig=
ht aligned)=0D
=0D
Loop3=0D
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache numbe=
r into R11=0D
- orr R0, R0, R7, LSL R2 ; factor in the index number=0D
+ lsl R8, R9, R5=0D
+ orr R0, R10, R8 ; factor in the way number and cache numbe=
r=0D
+ lsl R8, R7, R2=0D
+ orr R0, R0, R8 ; factor in the index number=0D
=0D
blx R1=0D
=0D
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm b/MdePkg=
/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
index 5a423df16bff..a46d70e41433 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
@@ -5,16 +5,16 @@
;=0D
=0D
=0D
-AREA IoLibMmio, CODE, READONLY=0D
+ AREA IoLibMmio, CODE, READONLY=0D
=0D
-EXPORT MmioRead8Internal=0D
-EXPORT MmioWrite8Internal=0D
-EXPORT MmioRead16Internal=0D
-EXPORT MmioWrite16Internal=0D
-EXPORT MmioRead32Internal=0D
-EXPORT MmioWrite32Internal=0D
-EXPORT MmioRead64Internal=0D
-EXPORT MmioWrite64Internal=0D
+ EXPORT MmioRead8Internal=0D
+ EXPORT MmioWrite8Internal=0D
+ EXPORT MmioRead16Internal=0D
+ EXPORT MmioWrite16Internal=0D
+ EXPORT MmioRead32Internal=0D
+ EXPORT MmioWrite32Internal=0D
+ EXPORT MmioRead64Internal=0D
+ EXPORT MmioWrite64Internal=0D
=0D
;=0D
; Reads an 8-bit MMIO register.=0D
--=20
2.23.0


[PATCH 1/3] ArmPkg/MdePkg : Unify INF files format

Baptiste Gerondeau
 

From: Baptiste GERONDEAU <bgerondeau@gmail.com>

Add a space between the '|' and the name of the toolchain to use,
as is the case in all other INF files.
Note that I did not touch the RVCT lines, since a following commit in
the set will address those.

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 +-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar=
mMmuLib/ArmMmuBaseLib.inf
index f4fecbb4098a..33dddf1e2b97 100644
--- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
@@ -22,7 +22,7 @@ [Sources.AARCH64]
=0D
[Sources.ARM]=0D
Arm/ArmMmuLibCore.c=0D
- Arm/ArmMmuLibV7Support.S |GCC =0D
+ Arm/ArmMmuLibV7Support.S | GCC=0D
Arm/ArmMmuLibV7Support.asm |RVCT =0D
=0D
[Packages]=0D
diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M=
dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
index e4e3d532e7b8..d38e1397eee1 100644
--- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
@@ -79,11 +79,11 @@ [Defines.ARM, Defines.AARCH64]
LIBRARY_CLASS =3D BaseMemoryLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER U=
EFI_DRIVER UEFI_APPLICATION=0D
=0D
[Sources.ARM]=0D
- Arm/ScanMem.S |GCC=0D
- Arm/SetMem.S |GCC=0D
- Arm/CopyMem.S |GCC=0D
- Arm/CompareMem.S |GCC=0D
- Arm/CompareGuid.S |GCC=0D
+ Arm/ScanMem.S | GCC=0D
+ Arm/SetMem.S | GCC=0D
+ Arm/CopyMem.S | GCC=0D
+ Arm/CompareMem.S | GCC=0D
+ Arm/CompareGuid.S | GCC=0D
=0D
Arm/ScanMem.asm |RVCT=0D
Arm/SetMem.asm |RVCT=0D
--=20
2.23.0


[PATCH 0/3] Arm builds on Visual Studio

Baptiste Gerondeau
 

We are currently making an effort to make ARM (and AARCH64 eventually)
builds using Microsoft's Visual Studio Compiler (aka MSVC/MSFT).

These 3 patches correspond to an effort to make the assembler work with
MSFT, which entails :
- Feeding MSFT the RVCT .asm files, since they share syntax
requirements.
- Fixing some instructions syntax in those .asm files, in order to make
them palatable for MSFT.
- Fixing some minor formatting issue in INF files, while we're at it.

This set enables the assembler, meanwhile the C also require changes,
which will come in a set later. This set makes the RVCT toolchain family
and profiles obsolete, unblocking :
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1750

As mentioned in the above bug, dropping RVCT would entail orphanating
the .asm files that powered the RVCT build. Since Visual Studio uses the
same file syntax, those can be reused to power the VS build.

These patches have been tested on VS2019 (v15.9.11) and VS2017 (v16.0.1)

Baptiste GERONDEAU (3):
ArmPkg/MdePkg : Unify INF files format
ARM/Assembler: Correct syntax from RVCT for MSFT
ARM/Assembler: Reuse RVCT assembler for MSFT build

ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 2 +-
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++++++-------------
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 2 +-
ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 2 +-
ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 2 +-
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++--
ArmPkg/Library/ArmLib/ArmBaseLib.inf | 8 ++++----
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 4 ++--
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 2 +-
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 2 +-
ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 2 +-
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | 2 +-
ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | 2 +-
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 6 +++---
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 6 +++---
ArmPlatformPkg/PrePi/PeiMPCore.inf | 2 +-
ArmPlatformPkg/PrePi/PeiUniCore.inf | 2 +-
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++---------
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 2 +-
MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 20 ++++++++++----------
MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 2 +-
21 files changed, 65 insertions(+), 59 deletions(-)

--
2.23.0


Re: 答复: [edk2-devel] [edk2] DxeIpl : create page table, occupied too much memory range

Tiger Liu(BJ-RD)
 

Hi, Laszlo:
Thanks for your reply!

Is Using PcdUse5LevelPageTable also a method to reduce paging table's memory requirement?

I find PcdUse1GPageTable's default value is false, why?

PcdUse5LevelPageTable's default value is true, and DxeIpl module will create 5-level paging for Dxe's long mode?

Best wishes,

-----邮件原件-----
发件人: Laszlo Ersek <lersek@redhat.com>
发送时间: 2019年9月17日 20:07
收件人: devel@edk2.groups.io; Tiger Liu(BJ-RD) <TigerLiu@zhaoxin.com>
主题: Re: [edk2-devel] [edk2] DxeIpl : create page table, occupied too much memory range

On 09/17/19 13:08, Tiger Liu(BJ-RD) wrote:
Hi, Expert:
I have a question about creating page table.
If a CPU support 48bit physical address line, then creating page tables(Page size=2MB) will occupy too much memory region.

Now, developer could only use PcdUse1GPageTable to avoid occupy too much memory region?
Not only. See <https://bugzilla.tianocore.org/show_bug.cgi?id=2008>.

Thanks
Laszlo


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Re: [PATCH 22/35] OvmfPkg/XenBusDxe: fix UninstallMultipleProtocolInterfaces() call

Julien Grall
 

Hi,

On 17/09/2019 20:49, Laszlo Ersek wrote:
Unlike the InstallMultipleProtocolInterfaces() boot service, which takes
an (EFI_HANDLE*) as first parameter, the
UninstallMultipleProtocolInterfaces() boot service takes an EFI_HANDLE as
first parameter.
This is an actual bug. It must have remained hidden until now because it's
on an error path. Fix the UninstallMultipleProtocolInterfaces() call.
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien.grall@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>

Cheers,

--
Julien Grall


Re: [PATCH edk2-CCSS 0/3] Coding Standards: add rule for documenting spurious variable assignments

Laszlo Ersek
 

On 09/17/19 21:10, Michael D Kinney wrote:
Series Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

I also agree that the macros would be cleaner, easy to review, and
and fewer lines of code without the comment block. If I objected
previously, then I have also changed my mind. I agree we can go
ahead and push the series in its current form and continue the
discussion on the macros.
Thank you all for the help, I've pushed the series:

d096859f15b9..f5ad35ec2c6d

Cheers,
Laszlo


[PATCH] BaseTools:Change the way that get some VpdPcd information

Fan, ZhijuX
 

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2201

An error occurs using special VpdPcd that is not used in the Inf file

In dsc:
[PcdsDynamicExVpd.common.DEFAULT]
gBoardModuleTokenSpaceGuid.test1|*|{CODE({
{0x0} // terminator
})}

In dec:
[PcdsDynamicEx]
# Vpd GPIO table
gBoardModuleTokenSpaceGuid.test1|{0}|GPIO_INIT_CONFIG[]|0x50000018 {
<HeaderFiles>
Library/GpioLib.h
<Packages>
MdePkg/MdePkg.dec
}
ValueError: invalid literal for int() with base 0: '*'

This Patch is going to fix issue by Change the way that get
some VpdPcd information

Cc: Liming Gao <liming.gao@intel.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Zhiju.Fan <zhijux.fan@intel.com>
---
BaseTools/Source/Python/build/BuildReport.py | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/Python/build/BuildReport.py b/BaseTools/Source/Python/build/BuildReport.py
index 6b26f1c3b0..880459d367 100644
--- a/BaseTools/Source/Python/build/BuildReport.py
+++ b/BaseTools/Source/Python/build/BuildReport.py
@@ -1419,10 +1419,19 @@ class PcdReport(object):
FileWrite(File, '%*s' % (self.MaxLen + 4, SkuInfo.VpdOffset))
VPDPcdItem = (Pcd.TokenSpaceGuidCName + '.' + PcdTokenCName, SkuIdName, SkuInfo.VpdOffset, Pcd.MaxDatumSize, SkuInfo.DefaultValue)
if VPDPcdItem not in VPDPcdList:
- VPDPcdList.append(VPDPcdItem)
+ PcdGuidList = self.UnusedPcds.get(Pcd.TokenSpaceGuidCName)
+ if PcdGuidList:
+ PcdList = PcdGuidList.get(Pcd.Type)
+ if not PcdList:
+ VPDPcdList.append(VPDPcdItem)
+ for VpdPcd in PcdList:
+ if PcdTokenCName == VpdPcd.TokenCName:
+ break
+ else:
+ VPDPcdList.append(VPDPcdItem)
if IsStructure:
FiledOverrideFlag = False
- OverrideValues = Pcd.SkuOverrideValues[Sku]
+ OverrideValues = Pcd.SkuOverrideValues.get(Sku)
if OverrideValues:
Keys = list(OverrideValues.keys())
OverrideFieldStruct = self.OverrideFieldValue(Pcd, OverrideValues[Keys[0]])
--
2.14.1.windows.1


Re: [PATCH 22/35] OvmfPkg/XenBusDxe: fix UninstallMultipleProtocolInterfaces() call

Anthony PERARD
 

On Tue, Sep 17, 2019 at 09:49:22PM +0200, Laszlo Ersek wrote:
Unlike the InstallMultipleProtocolInterfaces() boot service, which takes
an (EFI_HANDLE*) as first parameter, the
UninstallMultipleProtocolInterfaces() boot service takes an EFI_HANDLE as
first parameter.

This is an actual bug. It must have remained hidden until now because it's
on an error path. Fix the UninstallMultipleProtocolInterfaces() call.

Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Julien Grall <julien.grall@arm.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>

Thanks,

--
Anthony PERARD


Re: [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock

Laszlo Ersek
 

On 09/18/19 00:49, John E Lofgren wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
V3 changes:
change to mov instruction (non locking instuction) instead
of xchg to simplify design.
I think something's wrong -- the v3 update described above isn't
actually implemented in the patch (it continues using XCHG, rather than
MOV).

Thanks
Laszlo


V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used

Split lock happens when a locking instruction is used on mis-aligned data
that crosses two cachelines. If close source platform enables Alignment Check
Exception(#AC), They can hit a double fault due to split lock being in
CpuExceptionHandlerLib.

sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.

Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
---
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index 4db1a09f28..7b7642b290 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -180,21 +180,29 @@ HasErrorCode:
push qword [rbp + 24]

;; UINT64 Gdtr[2], Idtr[2];
+ ; sidt and sgdt saves 10 bytes to memory, 8 bytes = base and 2 bytes = limit.
+ ; To avoid #AC split lock when separating base and limit into their
+ ; own separate 64 bit memory, we can’t use 64 bit xchg since base [63:48] bits
+ ; may cross the cache line.
xor rax, rax
push rax
push rax
sidt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]

xor rax, rax
push rax
push rax
sgdt [rsp]
- xchg rax, [rsp + 2]
- xchg rax, [rsp]
- xchg rax, [rsp + 8]
+ xchg eax, [rsp + 2]
+ xchg eax, [rsp]
+ xchg eax, [rsp + 8]
+ xchg ax, [rsp + 6]
+ xchg ax, [rsp + 4]

;; UINT64 Ldtr, Tr;
xor rax, rax


[PATCH v2 1/1] uefi-sct/SctPkg AdapterInfo SetInformation may return unsupported

Tom Zhao
 

If AdapterInfo.SetInformation() is unsupported, it will return
EFI_UNSUPPORTED. Do not fail the test in this case.

Cc: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Cc: Eric Jin <eric.jin@intel.com>
Signed-off-by: Tom Zhao <tzhao@solarflare.com>
---

Notes:
v2:
- Change commit message to be closer to similar issues.

uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestConformance.c | 4 ++--
uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestFunction.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)

diff --git
a/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestConformance.c
b/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestConformance.c
index fb42398e4a97..3dc048db5333 100644
---
a/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestConformance.c
+++
b/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestConformance.c
@@ -556,8 +556,8 @@ BBTestSetInformationConformanceTestCheckpoint2 (
NULL,
InformationBlockSize
);
- - if ( Status != EFI_INVALID_PARAMETER && Status !=
EFI_WRITE_PROTECTED) {
+
+ if ( Status != EFI_INVALID_PARAMETER && Status !=
EFI_WRITE_PROTECTED && Status != EFI_UNSUPPORTED) {
AssertionType = EFI_TEST_ASSERTION_FAILED;
} else {
AssertionType = EFI_TEST_ASSERTION_PASSED;
diff --git
a/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestFunction.c
b/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestFunction.c
index 334bb9edc493..4b054b0ef7d8 100644
---
a/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestFunction.c
+++
b/uefi-sct/SctPkg/TestCase/UEFI/IHV/Protocol/AdapterInfo/BlackBoxTest/AdapterInfoBBTestFunction.c
@@ -372,11 +372,11 @@ BBTestSetInformationFunctionTestCheckpoint1 (
InformationBlockSize1
);
- if (Status == EFI_SUCCESS || Status == EFI_WRITE_PROTECTED)
- AssertionType = EFI_TEST_ASSERTION_PASSED; + if (Status ==
EFI_SUCCESS || Status == EFI_WRITE_PROTECTED || Status == EFI_UNSUPPORTED)
+ AssertionType = EFI_TEST_ASSERTION_PASSED;
else
- AssertionType = EFI_TEST_ASSERTION_FAILED; - +
AssertionType = EFI_TEST_ASSERTION_FAILED;
+
StandardLib->RecordAssertion (
StandardLib,
AssertionType,
--
2.21.0