Date   

Re: [PATCH v2 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Gao, Zhichao
 

Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: Zhang, Shenglei
Sent: Friday, August 16, 2019 2:11 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>;
Gao, Zhichao <zhichao.gao@intel.com>
Subject: [PATCH v2 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace
shift logical left

Replace the operation to shift logical left with the function LShiftU64, which
has the same functionality.
The original code causes ShellPkg build failure with build target"-b NOOPT".

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
v2: There is no return target from LShiftU64 in v1 patch.
So update code to "Val = LShiftU64(Val,32)".

ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 94bafa22ef4c..a569c3c55406 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -294,7 +294,7 @@ DumpUint64 (

Val = *(UINT32*)(Ptr + sizeof (UINT32));

- Val <<= 32;
+ Val = LShiftU64(Val,32);
Val |= (UINT64)*(UINT32*)Ptr;

Print (Format, Val);
--
2.18.0.windows.1


[PATCH v2 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Zhang, Shenglei
 

Replace the operation to shift logical left with the function
LShiftU64, which has the same functionality.
The original code causes ShellPkg build failure with build
target"-b NOOPT".

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
v2: There is no return target from LShiftU64 in v1 patch.
So update code to "Val = LShiftU64(Val,32)".

ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 94bafa22ef4c..a569c3c55406 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -294,7 +294,7 @@ DumpUint64 (

Val = *(UINT32*)(Ptr + sizeof (UINT32));

- Val <<= 32;
+ Val = LShiftU64(Val,32);
Val |= (UINT64)*(UINT32*)Ptr;

Print (Format, Val);
--
2.18.0.windows.1


Re: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Gao, Zhichao
 

Thanks for correcting my mistake.

Shenglei,
Please fix it.

Thanks,
Zhichao

-----Original Message-----
From: Gao, Liming
Sent: Friday, August 16, 2019 2:00 PM
To: devel@edk2.groups.io; Gao, Zhichao <zhichao.gao@intel.com>; Zhang,
Shenglei <shenglei.zhang@intel.com>
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH 1/1]
ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Shenglei:

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Gao, Zhichao
Sent: Friday, August 16, 2019 12:08 PM
To: Zhang, Shenglei <shenglei.zhang@intel.com>; devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: Re: [edk2-devel] [PATCH 1/1]
ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: Zhang, Shenglei
Sent: Thursday, August 15, 2019 3:38 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray
<ray.ni@intel.com>; Gao, Zhichao <zhichao.gao@intel.com>
Subject: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace
shift logical left

Replace the operation to shift logical left with the function
LShiftU64, which has the same functionality.
The original code causes ShellPkg build failure with build target"-b
NOOPT".

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 2d6ff80e299e..2e6d99145beb 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -290,7 +290,7 @@ DumpUint64 (

Val = *(UINT32*)(Ptr + sizeof (UINT32));

- Val <<= 32;
+ LShiftU64(Val,32);
The logic should be:

Val = LShiftU64(Val,32);

Thanks
Liming

Val |= (UINT64)*(UINT32*)Ptr;

Print (Format, Val);
--
2.18.0.windows.1


Re: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Liming Gao
 

Shenglei:

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Gao, Zhichao
Sent: Friday, August 16, 2019 12:08 PM
To: Zhang, Shenglei <shenglei.zhang@intel.com>; devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: Re: [edk2-devel] [PATCH 1/1]
ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: Zhang, Shenglei
Sent: Thursday, August 15, 2019 3:38 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>;
Gao, Zhichao <zhichao.gao@intel.com>
Subject: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift
logical left

Replace the operation to shift logical left with the function LShiftU64, which
has the same functionality.
The original code causes ShellPkg build failure with build target"-b NOOPT".

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 2d6ff80e299e..2e6d99145beb 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -290,7 +290,7 @@ DumpUint64 (

Val = *(UINT32*)(Ptr + sizeof (UINT32));

- Val <<= 32;
+ LShiftU64(Val,32);
The logic should be:

Val = LShiftU64(Val,32);

Thanks
Liming

Val |= (UINT64)*(UINT32*)Ptr;

Print (Format, Val);
--
2.18.0.windows.1


Re: [Patch V4 10/10] BaseTools/tools_def.template: Add -gdwarf to XCODE5 X64

Liming Gao
 

Reviewed-by: Liming Gao <liming.gao@intel.com>

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Michael D Kinney
Sent: Friday, August 16, 2019 10:15 AM
To: devel@edk2.groups.io
Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Ni, Ray <ray.ni@intel.com>;
Andrew Fish <afish@apple.com>
Subject: [edk2-devel] [Patch V4 10/10] BaseTools/tools_def.template: Add -
gdwarf to XCODE5 X64

Add -gdwarf to XCODE5 X64 builds to generate symbols for
source level debug using lldb.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Andrew Fish <afish@apple.com>
---
BaseTools/Conf/tools_def.template | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Conf/tools_def.template
b/BaseTools/Conf/tools_def.template
index 26a2cf604f..8f0e6cb6c2 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2593,8 +2593,8 @@ RELEASE_XCODE5_X64_ASM_FLAGS = -arch x86_64
*_XCODE5_*_PP_FLAGS = -E -x assembler-with-cpp -include
$(DEST_DIR_DEBUG)/AutoGen.h
*_XCODE5_*_VFRPP_FLAGS = -x c -E -P -DVFRCOMPILE -include
$(DEST_DIR_DEBUG)/$(MODULE_NAME)StrDefs.h

- DEBUG_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -
Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-
extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-
field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -
D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
- NOOPT_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -
O0 -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-
extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-
field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs
-ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -
D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+ DEBUG_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -
gdwarf -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -
fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-
implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -
Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare
-Wno-varargs -ftrap-
function=undefined_behavior_has_been_optimized_away_by_clang -D
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+ NOOPT_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -
gdwarf -O0 -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -
fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-
implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -
Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare
-Wno-varargs -ftrap-
function=undefined_behavior_has_been_optimized_away_by_clang -D
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os
-Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-
extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float
-mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-
field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs
-Wno-unused-const-variable -ftrap-
function=undefined_behavior_has_been_optimized_away_by_clang -D
NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)


###########################################################
#########################
--
2.21.0.windows.1



Re: [PATCH] UefiCpuPkg: Adding a new TSC library by using CPUID(0x15) TSC leaf

Dong, Eric
 

Reviewed-by: Eric Dong <eric.dong@intel.com>

-----Original Message-----
From: Kuo, Donald
Sent: Thursday, August 15, 2019 5:11 PM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Zeng, Star <star.zeng@intel.com>; Dong, Eric
<eric.dong@intel.com>; Chan, Amy <amy.chan@intel.com>; Chaganty,
Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [PATCH] UefiCpuPkg: Adding a new TSC library by using CPUID(0x15)
TSC leaf

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1909

Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Donald Kuo <donald.kuo@intel.com>
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c | 41 +++
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 35 +++
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.uni | 17 ++
UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c | 279
+++++++++++++++++++++
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c | 85 +++++++
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf | 37 +++
UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni | 17 ++
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c | 58 +++++
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf | 36 +++
UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni | 17 ++
UefiCpuPkg/UefiCpuPkg.dec | 8 +
UefiCpuPkg/UefiCpuPkg.dsc | 3 +
UefiCpuPkg/UefiCpuPkg.uni | 10 +
13 files changed, 643 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.uni
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
create mode 100644 UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
new file mode 100644
index 0000000000..6ddf917bad
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
@@ -0,0 +1,41 @@
+/** @file
+ CPUID Leaf 0x15 for Core Crystal Clock frequency instance as Base Timer
Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+
+/**
+ CPUID Leaf 0x15 for Core Crystal Clock Frequency.
+
+ The TSC counting frequency is determined by using CPUID leaf 0x15.
Frequency in MHz = Core XTAL frequency * EBX/EAX.
+ In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not
supported.
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+CpuidCoreClockCalculateTscFrequency (
+ VOID
+ );
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ )
+{
+ return CpuidCoreClockCalculateTscFrequency (); }
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
new file mode 100644
index 0000000000..fd93adc5f1
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Base CPU Timer Library
+#
+# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance # counter features are provided by the processors time
stamp counter.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseCpuTimerLib
+ FILE_GUID = F10B5B91-D15A-496C-B044-B5235721AA08
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib|SEC PEI_CORE PEIM
+ MODULE_UNI_FILE = BaseCpuTimerLib.uni
+
+[Sources]
+ CpuTimerLib.c
+ BaseCpuTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
+CONSUMES
diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.uni
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.uni
new file mode 100644
index 0000000000..fcf2b0fbcb
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.uni
@@ -0,0 +1,17 @@
+// /** @file
+// Base CPU Timer Library
+//
+// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance // counter features are provided by the processors time
stamp counter.
+//
+// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> //
+// SPDX-License-Identifier: BSD-2-Clause-Patent // // **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Timer
Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Provides basic
timer support using CPUID Leaf 0x15 XTAL frequency."
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
new file mode 100644
index 0000000000..192a401fe6
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
@@ -0,0 +1,279 @@
+/** @file
+ CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Register/Cpuid.h>
+
+GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, {
+0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } };
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ );
+
+/**
+ CPUID Leaf 0x15 for Core Crystal Clock Frequency.
+
+ The TSC counting frequency is determined by using CPUID leaf 0x15.
Frequency in MHz = Core XTAL frequency * EBX/EAX.
+ In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not
supported.
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+CpuidCoreClockCalculateTscFrequency (
+ VOID
+ )
+{
+ UINT64 TscFrequency;
+ UINT64 CoreXtalFrequency;
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+
+ //
+ // Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal
+ Clock Information // EBX returns 0 if not supported. ECX, if non zero,
provides Core Xtal Frequency in hertz.
+ // TSC frequency = (ECX, Core Xtal Frequency) * EBX/EAX.
+ //
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &RegEax, &RegEbx, &RegEcx,
NULL);
+
+ //
+ // If EAX or EBX returns 0, the XTAL ratio is not enumerated.
+ //
+ if (RegEax == 0 || RegEbx ==0 ) {
+ ASSERT (RegEax != 0);
+ ASSERT (RegEbx != 0);
+ return 0;
+ }
+ //
+ // If ECX returns 0, the XTAL frequency is not enumerated.
+ // And PcdCpuCoreCrystalClockFrequency defined should base on processor
series.
+ //
+ if (RegEcx == 0) {
+ CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency);
+ } else {
+ CoreXtalFrequency = (UINT64) RegEcx; }
+
+ //
+ // Calculate TSC frequency = (ECX, Core Xtal Frequency) * EBX/EAX //
+ TscFrequency = DivU64x32 (MultU64x32 (CoreXtalFrequency, RegEbx) +
+ (UINT64)(RegEax >> 1), RegEax);
+
+ return TscFrequency;
+}
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked
+ by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalCpuDelay (
+ IN UINT64 Delay
+ )
+{
+ UINT64 Ticks;
+
+ //
+ // The target timer count is calculated here // Ticks =
+ AsmReadTsc() + Delay;
+
+ //
+ // Wait until time out
+ // Timer wrap-arounds are NOT handled correctly by this function.
+ // Thus, this function must be called within 10 years of reset since
+ // Intel guarantees a minimum of 10 years before the TSC wraps.
+ //
+ while (AsmReadTsc() <= Ticks) {
+ CpuPause();
+ }
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param[in] MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+
+ InternalCpuDelay (
+ DivU64x32 (
+ MultU64x64 (
+ MicroSeconds,
+ InternalGetPerformanceCounterFrequency ()
+ ),
+ 1000000u
+ )
+ );
+
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+
+ InternalCpuDelay (
+ DivU64x32 (
+ MultU64x64 (
+ NanoSeconds,
+ InternalGetPerformanceCounterFrequency ()
+ ),
+ 1000000000u
+ )
+ );
+
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance
+ counter. The counter can either count up by 1 or count down by 1. If
+ the physical performance counter counts by a larger increment, then
+ the counter values must be translated. The properties of the counter
+ can be retrieved from GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return AsmReadTsc ();
+}
+
+/**
+ Retrieves the 64-bit frequency in Hz and the range of performance
+counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance
+ counter starts with immediately after is it rolls over is returned in
+ StartValue. If EndValue is not NULL, then the value that the
+ performance counter end with immediately before it rolls over is
+ returned in EndValue. The 64-bit frequency of the performance counter
+ in Hz is always returned. If StartValue is less than EndValue, then
+ the performance counter counts up. If StartValue is greater than
+ EndValue, then the performance counter counts down. For example, a
+ 64-bit free running counter that counts up would have a StartValue of
+ 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter that
counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with
before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = 0xffffffffffffffffULL;
+ }
+ return InternalGetPerformanceCounterFrequency (); }
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance
+ counter to time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance
counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 Frequency;
+ UINT64 NanoSeconds;
+ UINT64 Remainder;
+ INTN Shift;
+
+ Frequency = GetPerformanceCounterProperties (NULL, NULL);
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency,
+ &Remainder), 1000000000u);
+
+ //
+ // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
+ // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should <
+ 2^(64-30) = 2^34, // i.e. highest bit set in Remainder should <= 33.
+ //
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33); Remainder =
+ RShiftU64 (Remainder, (UINTN) Shift); Frequency = RShiftU64
+ (Frequency, (UINTN) Shift); NanoSeconds += DivU64x64Remainder
+ (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
+
+ return NanoSeconds;
+}
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
new file mode 100644
index 0000000000..269e5a3e83
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.c
@@ -0,0 +1,85 @@
+/** @file
+ CPUID Leaf 0x15 for Core Crystal Clock frequency instance of Timer Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+
+extern GUID mCpuCrystalFrequencyHobGuid;
+
+/**
+ CPUID Leaf 0x15 for Core Crystal Clock Frequency.
+
+ The TSC counting frequency is determined by using CPUID leaf 0x15.
Frequency in MHz = Core XTAL frequency * EBX/EAX.
+ In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not
supported.
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+CpuidCoreClockCalculateTscFrequency (
+ VOID
+ );
+
+//
+// Cached CPU Crystal counter frequency //
+UINT64 mCpuCrystalCounterFrequency = 0;
+
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ )
+{
+ return mCpuCrystalCounterFrequency;
+}
+
+/**
+ The constructor function is to initialize CpuCrystalCounterFrequency.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+DxeCpuTimerLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ //
+ // Initialize CpuCrystalCounterFrequency // GuidHob =
+ GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid); if (GuidHob != NULL)
+ {
+ mCpuCrystalCounterFrequency = *(UINT64*)GET_GUID_HOB_DATA
+ (GuidHob); } else {
+ mCpuCrystalCounterFrequency = CpuidCoreClockCalculateTscFrequency
+ (); }
+
+ if (mCpuCrystalCounterFrequency == 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
new file mode 100644
index 0000000000..6c83549c87
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
@@ -0,0 +1,37 @@
+## @file
+# DXE CPU Timer Library
+#
+# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance # counter features are provided by the processors time
stamp counter.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeCpuTimerLib
+ FILE_GUID = F22CC0DA-E7DB-4E4D-ABE2-A608188233A2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib|DXE_CORE DXE_DRIVER
DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
SMM_CORE
+ CONSTRUCTOR = DxeCpuTimerLibConstructor
+ MODULE_UNI_FILE = DxeCpuTimerLib.uni
+
+[Sources]
+ CpuTimerLib.c
+ DxeCpuTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ HobLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
+CONSUMES
diff --git a/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
new file mode 100644
index 0000000000..f55b92abac
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.uni
@@ -0,0 +1,17 @@
+// /** @file
+// DXE CPU Timer Library
+//
+// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance // counter features are provided by the processors time
stamp counter.
+//
+// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> //
+// SPDX-License-Identifier: BSD-2-Clause-Patent // // **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Timer
Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Provides basic
timer support using CPUID Leaf 0x15 XTAL frequency."
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
new file mode 100644
index 0000000000..91a7212056
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.c
@@ -0,0 +1,58 @@
+/** @file
+ CPUID Leaf 0x15 for Core Crystal Clock frequency instance as PEI Timer
Library.
+
+ Copyright (c) 2019 Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+
+extern GUID mCpuCrystalFrequencyHobGuid;
+
+/**
+ CPUID Leaf 0x15 for Core Crystal Clock Frequency.
+
+ The TSC counting frequency is determined by using CPUID leaf 0x15.
Frequency in MHz = Core XTAL frequency * EBX/EAX.
+ In newer flavors of the CPU, core xtal frequency is returned in ECX or 0 if not
supported.
+ @return The number of TSC counts per second.
+
+**/
+UINT64
+CpuidCoreClockCalculateTscFrequency (
+ VOID
+ );
+
+/**
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ Internal function to retrieves the 64-bit frequency in Hz.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+InternalGetPerformanceCounterFrequency (
+ VOID
+ )
+{
+ UINT64 *CpuCrystalCounterFrequency;
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ CpuCrystalCounterFrequency = NULL;
+ GuidHob = GetFirstGuidHob (&mCpuCrystalFrequencyHobGuid); if
+ (GuidHob == NULL) {
+ CpuCrystalCounterFrequency =
(UINT64*)BuildGuidHob(&mCpuCrystalFrequencyHobGuid, sizeof
(*CpuCrystalCounterFrequency));
+ ASSERT (CpuCrystalCounterFrequency != NULL);
+ *CpuCrystalCounterFrequency = CpuidCoreClockCalculateTscFrequency
+ (); } else {
+ CpuCrystalCounterFrequency = (UINT64*)GET_GUID_HOB_DATA
(GuidHob);
+ }
+
+ return *CpuCrystalCounterFrequency;
+}
+
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
new file mode 100644
index 0000000000..7af0fc44a6
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf
@@ -0,0 +1,36 @@
+## @file
+# PEI CPU Timer Library
+#
+# Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance # counter features are provided by the processors time
stamp counter.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiCpuTimerLib
+ FILE_GUID = 2B13DE00-1A5F-4DD7-A298-01B08AF1015A
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib|PEI_CORE PEIM
+ MODULE_UNI_FILE = PeiCpuTimerLib.uni
+
+[Sources]
+ CpuTimerLib.c
+ PeiCpuTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ HobLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
+CONSUMES
diff --git a/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
new file mode 100644
index 0000000000..49beb44908
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.uni
@@ -0,0 +1,17 @@
+// /** @file
+// PEI CPU Timer Library
+//
+// Provides basic timer support using CPUID Leaf 0x15 XTAL frequency.
+The performance // counter features are provided by the processors time
stamp counter.
+//
+// Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> //
+// SPDX-License-Identifier: BSD-2-Clause-Patent // // **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Timer
Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Provides basic
timer support using CPUID Leaf 0x15 XTAL frequency."
+
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index
14ddaa8633..86ad61f64b 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -211,6 +211,14 @@
# @Prompt If CPU features will be initialized during S3 resume.

gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLE
AN|0x0000001D

+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal
Clock Frequency.
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H =
25000000 (25MHz)
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor
Family = 24000000 (24MHz)
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID
signature 06_5CH = 19200000 (19.2MHz)
+ # @Prompt This PCD is the nominal frequency of the core crystal clock
+ in Hz as is CPUID Leaf 0x15:ECX
+
+
gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|U
IN
+ T64|0x32132113
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processors diff --git
a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index
bf690d3978..e7dfe30eda 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -101,6 +101,9 @@
UefiCpuPkg/CpuIoPei/CpuIoPei.inf

UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
UefiCpuPkg/Application/Cpuid/Cpuid.inf
+ UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+ UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf
+ UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf

[Components.IA32, Components.X64]
UefiCpuPkg/CpuDxe/CpuDxe.inf
diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index
80af4fc1d2..fbf7680726 100644
--- a/UefiCpuPkg/UefiCpuPkg.uni
+++ b/UefiCpuPkg/UefiCpuPkg.uni
@@ -242,3 +242,13 @@
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuKnownGoodStackSize_HELP
#language en-US "Size of good stack for an exception.\n"
"This PCD will only take into
effect if PcdCpuStackGuard is enabled.\n"

+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_PROM
PT #language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and
Nominal Core Crystal Clock Frequency."
+
+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_HELP
#language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal
Core Crystal Clock Frequency.<BR><BR>\n"
+ "TSC Frequency = ECX (core
crystal clock frequency) * EBX/EAX.<BR><BR>\n"
+ "This PCD is the nominal
frequency of the core crystal clock in Hz as is CPUID Leaf
0x15:ECX.<BR><BR>\n"
+ "Default value is 24000000
for 6th and 7th generation Intel Core processors and Intel Xeon W Processor
Family.<BR>\n"
+ "25000000 - Intel Xeon
Processor Scalable Family with CPUID signature 06_55H(25MHz).<BR>\n"
+ "24000000 - 6th and 7th
generation Intel Core processors and Intel Xeon W Processor
Family(24MHz).<BR>\n"
+ "19200000 - Intel Atom
processors based on Goldmont Microarchitecture with CPUID signature
06_5CH(19.2MHz).<BR>\n"
+
--
2.14.2.windows.3


Re: [PATCH 1/1] UefiCpuPkg/Cpuid: Add description for parameter LeafFunction

Dong, Eric
 

Reviewed-by: Eric Dong <eric.dong@intel.com>

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Zhang, Shenglei
Sent: Thursday, August 15, 2019 4:15 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo
Ersek <lersek@redhat.com>
Subject: [edk2-devel] [PATCH 1/1] UefiCpuPkg/Cpuid: Add description for
parameter LeafFunction

LeafFunction needs to be described in comments.
https://bugzilla.tianocore.org/show_bug.cgi?id=2052

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
UefiCpuPkg/Application/Cpuid/Cpuid.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c
b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index 7a994eba9ac8..f39a7fb33ae5 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -708,6 +708,8 @@ CpuidArchitecturalPerformanceMonitoring (
/**
Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.

+ @param[in] LeafFunction Leaf function index for
CPUID_EXTENDED_TOPOLOGY.
+
**/
VOID
CpuidExtendedTopology (
--
2.18.0.windows.1



Re: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Initialize local variables

Gao, Zhichao
 

Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Zhang, Shenglei
Sent: Thursday, August 15, 2019 1:42 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>;
Gao, Zhichao <zhichao.gao@intel.com>
Subject: [edk2-devel] [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib:
Initialize local variables

At latest edk2 version, there is build failure when building ShellPkg with
VS2012x86, which results from uninitialized local variables.

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
.../Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 8 ++++++++
.../Library/UefiShellAcpiViewCommandLib/AcpiView.c | 10 ++++++++++
2 files changed, 18 insertions(+)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 2d6ff80e299e..94bafa22ef4c 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -121,6 +121,10 @@ VerifyChecksum (
UINT8 Checksum;
UINTN OriginalAttribute;

+ //
+ // set local variables to suppress incorrect compiler/analyzer
+ warnings // OriginalAttribute = 0;
ByteCount = 0;
Checksum = 0;

@@ -472,6 +476,10 @@ ParseAcpi (
BOOLEAN HighLight;
UINTN OriginalAttribute;

+ //
+ // set local variables to suppress incorrect compiler/analyzer
+ warnings // OriginalAttribute = 0;
Offset = 0;

// Increment the Indent
diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiView.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiView.c
index 9feb2df2078f..de0851dd5fba 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiView.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiView.c
@@ -211,6 +211,10 @@ ProcessTableReportOptions (
BOOLEAN Log;
BOOLEAN HighLight;

+ //
+ // set local variables to suppress incorrect compiler/analyzer
+ warnings // OriginalAttribute = 0;
SignaturePtr = (UINT8*)(UINTN)&Signature;
Log = FALSE;
HighLight = GetColourHighlighting (); @@ -347,6 +351,12 @@ AcpiView (
PARSE_ACPI_TABLE_PROC RsdpParserProc;
BOOLEAN Trace;

+ //
+ // set local variables to suppress incorrect compiler/analyzer
+ warnings // EfiConfigurationTable = NULL; OriginalAttribute = 0;
+
// Search the table for an entry that matches the ACPI Table Guid
FoundAcpiTable = FALSE;
for (Index = 0; Index < SystemTable->NumberOfTableEntries; Index++) {
--
2.18.0.windows.1



Re: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift logical left

Gao, Zhichao
 

Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>

Thanks,
Zhichao

-----Original Message-----
From: Zhang, Shenglei
Sent: Thursday, August 15, 2019 3:38 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>;
Gao, Zhichao <zhichao.gao@intel.com>
Subject: [PATCH 1/1] ShellPkg/UefiShellAcpiViewCommandLib: Replace shift
logical left

Replace the operation to shift logical left with the function LShiftU64, which
has the same functionality.
The original code causes ShellPkg build failure with build target"-b NOOPT".

Cc: Jaben Carsey <jaben.carsey@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
index 2d6ff80e299e..2e6d99145beb 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c
@@ -290,7 +290,7 @@ DumpUint64 (

Val = *(UINT32*)(Ptr + sizeof (UINT32));

- Val <<= 32;
+ LShiftU64(Val,32);
Val |= (UINT64)*(UINT32*)Ptr;

Print (Format, Val);
--
2.18.0.windows.1


Re: [PATCH v6 0/5] Build cache enhancement

Bob Feng
 

For this patch set,

Reviewed-by: Bob Feng <bob.c.feng@intel.com>

-----Original Message-----
From: Shi, Steven
Sent: Thursday, August 15, 2019 10:26 PM
To: devel@edk2.groups.io
Cc: Gao, Liming <liming.gao@intel.com>; Feng, Bob C <bob.c.feng@intel.com>; Rodriguez, Christian <christian.rodriguez@intel.com>; Johnson, Michael <michael.johnson@intel.com>; lersek@redhat.com; leif.lindholm@linaro.org; afish@apple.com; Cetola, Stephano <stephano.cetola@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Shi, Steven <steven.shi@intel.com>
Subject: [PATCH v6 0/5] Build cache enhancement

From: "Shi, Steven" <steven.shi@intel.com>

This patch set is for the 201908 stable tag

Enhance the edk2 build cache with below patches:
Patch 01/05: Improve the cache hit rate through new cache checkpoint and hash algorithm Patch 02/05: Print more info to explain why a module build cache miss Patch 03/05: Fix the unsafe [self.Arch][self.Name] key usage in build cache Patch 04/05 Add the GenFds multi-thread support in build cache Patch 05/05 Improve the file saving and copying functions reliability in build cache


You can directly try this patch set in the branch:
https://github.com/shijunjing/edk2/tree/build_cache_improve_v6_3

V6:
In the patch 5, add error handling to skip hash calculation if find module cache already crashed

V5:
Fix the method name typo in Misc.py from EdkLogger.quite() to EdkLogger.quiet()

V4:
Change single global lock into two locks, which are cache_lock and file_lock, for better cache performance and IO reliability in windows

V3:
Add patch 5. To improve the autogen CopyFileOnChange() and SaveFileOnChange() functions reliability for build cache

V2:
Enhance the SaveHashChainFileToCache() function in ModuleAutoGen.py and not need to call f.close() in the "with open(xxx) as f:" block. The with block will close the file automatically

V1:
Initial patch set

Shi, Steven (5):
BaseTools: Improve the cache hit in the edk2 build cache
BaseTools: Print first cache missing file for build cachle
BaseTools: Change the [Arch][Name] module key in Build cache
BaseTools: Add GenFds multi-thread support in build cache
BaseTools: Improve the file saving and copying reliability

.../Source/Python/AutoGen/AutoGenWorker.py | 27 +-
BaseTools/Source/Python/AutoGen/CacheIR.py | 29 +
BaseTools/Source/Python/AutoGen/DataPipe.py | 6 +
BaseTools/Source/Python/AutoGen/GenC.py | 0
BaseTools/Source/Python/AutoGen/GenMake.py | 233 +++---
.../Source/Python/AutoGen/ModuleAutoGen.py | 791 ++++++++++++++++--
BaseTools/Source/Python/Common/GlobalData.py | 11 +
BaseTools/Source/Python/Common/Misc.py | 44 +-
BaseTools/Source/Python/build/build.py | 182 ++--
9 files changed, 1073 insertions(+), 250 deletions(-) mode change 100644 => 100755 BaseTools/Source/Python/AutoGen/AutoGenWorker.py
create mode 100755 BaseTools/Source/Python/AutoGen/CacheIR.py
mode change 100644 => 100755 BaseTools/Source/Python/AutoGen/DataPipe.py
mode change 100644 => 100755 BaseTools/Source/Python/AutoGen/GenC.py
mode change 100644 => 100755 BaseTools/Source/Python/AutoGen/GenMake.py
mode change 100644 => 100755 BaseTools/Source/Python/AutoGen/ModuleAutoGen.py
mode change 100644 => 100755 BaseTools/Source/Python/Common/GlobalData.py
mode change 100644 => 100755 BaseTools/Source/Python/Common/Misc.py
mode change 100644 => 100755 BaseTools/Source/Python/build/build.py

--
2.17.1


Re: [PATCH v1 00/11] Test against invalid pointers in acpiview

Liming Gao
 

Krzysztof:
Can you submit BZ in https://bugzilla.tianocore.org/ for this change?

Thanks
Liming

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Krzysztof Koch
Sent: Thursday, August 15, 2019 9:11 PM
To: devel@edk2.groups.io
Cc: Carsey, Jaben <jaben.carsey@intel.com>; Ni, Ray <ray.ni@intel.com>; Gao,
Zhichao <zhichao.gao@intel.com>; Sami.Mujawar@arm.com;
Matteo.Carlini@arm.com; nd@arm.com
Subject: [edk2-devel] [PATCH v1 00/11] Test against invalid pointers in
acpiview

Prevent the use of invalid pointers when parsing ACPI tables in the UEFI
shell acpiview tool.

The parsing of ACPI tables is often controlled with the values read
earlier from the same table. For example, the 'Offset' or 'Count' fields
found in a structure are later used to parse the substructures. If such
fields lie outside the structure's buffer length provided, then there
is a possibility for a wild or dangling pointer.

Currently, if the ParseAcpi() function terminates early because the end
of the input table data buffer has been reached, then the pointers
which were supposed to be updated by this function are left untouched.
This is a security issue as the values pointed to by these pointers are
later used for flow control.

This patch series aims to solve this security issue by explicitly
initializing any pointers lying outside the input ACPI data buffer to
NULL and testing for NULL whenever these pointers are dereferenced.

Changes can be seet at:
https://github.com/KrzysztofKoch1/edk2/tree/612_add_pointer_validation_
v1

Krzysztof Koch (11):
ShellPkg: acpiview: Set ItemPtr to NULL for unprocessed table fields
ShellPkg: acpiview: RSDP: Validate global pointer before use
ShellPkg: acpiview: FADT: Validate global pointer before use
ShellPkg: acpiview: SLIT: Validate global pointer before use
ShellPkg: acpiview: SLIT: Validate System Locality count
ShellPkg: acpiview: SRAT: Validate global pointers before use
ShellPkg: acpiview: MADT: Validate global pointers before use
ShellPkg: acpiview: PPTT: Validate global pointers before use
ShellPkg: acpiview: IORT: Validate global pointers before use
ShellPkg: acpiview: GTDT: Validate global pointers before use
ShellPkg: acpiview: DBG2: Validate global pointers before use

ShellPkg/Library/UefiShellAcpiViewCommandLib/AcpiParser.c | 9 ++-
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Dbg2/Dbg2Parser.c
| 43 ++++++++++++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Fadt/FadtParser.c |
14 +++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Gtdt/GtdtParser.c
| 37 ++++++++++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Iort/IortParser.c |
52 +++++++++++++++++

ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c
| 13 +++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c |
25 ++++++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Rsdp/RsdpParser.c
| 12 ++++
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Slit/SlitParser.c | 61
++++++++++++++++++--
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Srat/SratParser.c |
13 +++++
10 files changed, 272 insertions(+), 7 deletions(-)

--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'




Re: [PATCH 1/1] CryptoPkg/OpensslLib: Add missing header files in INF file

Wang, Jian J
 

Pushed at 8906f076de35b222a7d62bcf6ed1a4a2498a5791

Regards,
Jian

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
Wang, Jian J
Sent: Thursday, August 15, 2019 4:59 PM
To: Zhang, Shenglei <shenglei.zhang@intel.com>; devel@edk2.groups.io
Cc: Ye, Ting <ting.ye@intel.com>
Subject: Re: [edk2-devel] [PATCH 1/1] CryptoPkg/OpensslLib: Add missing
header files in INF file


Reviewed-by: Jian J Wang <jian.j.wang@intel.com>

-----Original Message-----
From: Zhang, Shenglei
Sent: Tuesday, August 13, 2019 4:50 PM
To: devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@intel.com>; Ye, Ting <ting.ye@intel.com>
Subject: [PATCH 1/1] CryptoPkg/OpensslLib: Add missing header files in
INF
file

The header files are used but missing in INF,which causes
warning message when building them.
https://bugzilla.tianocore.org/show_bug.cgi?id=2036

Cc: Jian Wang <jian.j.wang@intel.com>
Cc: Ting Ye <ting.ye@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
---
CryptoPkg/Library/OpensslLib/OpensslLib.inf | 59
+++++++++++++++++++
.../Library/OpensslLib/OpensslLibCrypto.inf | 53 ++++++++++++++++-
2 files changed, 111 insertions(+), 1 deletion(-)

diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index 5f36edeeef3c..7432321fd431 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -22,6 +22,8 @@ [Defines]
#

[Sources]
+ buildinf.h
+ rand_pool_noise.h
$(OPENSSL_PATH)/e_os.h
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
@@ -32,7 +34,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/aes/aes_misc.c
$(OPENSSL_PATH)/crypto/aes/aes_ofb.c
$(OPENSSL_PATH)/crypto/aes/aes_wrap.c
+ $(OPENSSL_PATH)/crypto/aes/aes_locl.h
$(OPENSSL_PATH)/crypto/aria/aria.c
+ $(OPENSSL_PATH)/crypto/arm_arch.h
$(OPENSSL_PATH)/crypto/asn1/a_bitstr.c
$(OPENSSL_PATH)/crypto/asn1/a_d2i_fp.c
$(OPENSSL_PATH)/crypto/asn1/a_digest.c
@@ -97,12 +101,21 @@ [Sources]
$(OPENSSL_PATH)/crypto/asn1/x_sig.c
$(OPENSSL_PATH)/crypto/asn1/x_spki.c
$(OPENSSL_PATH)/crypto/asn1/x_val.c
+ $(OPENSSL_PATH)/crypto/asn1/standard_methods.h
+ $(OPENSSL_PATH)/crypto/asn1/charmap.h
+ $(OPENSSL_PATH)/crypto/asn1/tbl_standard.h
+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.h
+ $(OPENSSL_PATH)/crypto/asn1/asn1_locl.h
$(OPENSSL_PATH)/crypto/async/arch/async_null.c
$(OPENSSL_PATH)/crypto/async/arch/async_posix.c
$(OPENSSL_PATH)/crypto/async/arch/async_win.c
$(OPENSSL_PATH)/crypto/async/async.c
$(OPENSSL_PATH)/crypto/async/async_err.c
$(OPENSSL_PATH)/crypto/async/async_wait.c
+ $(OPENSSL_PATH)/crypto/async/arch/async_win.h
+ $(OPENSSL_PATH)/crypto/async/async_locl.h
+ $(OPENSSL_PATH)/crypto/async/arch/async_posix.h
+ $(OPENSSL_PATH)/crypto/async/arch/async_null.h
$(OPENSSL_PATH)/crypto/bio/b_addr.c
$(OPENSSL_PATH)/crypto/bio/b_dump.c
$(OPENSSL_PATH)/crypto/bio/b_sock.c
@@ -125,6 +138,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/bio/bss_mem.c
$(OPENSSL_PATH)/crypto/bio/bss_null.c
$(OPENSSL_PATH)/crypto/bio/bss_sock.c
+ $(OPENSSL_PATH)/crypto/bio/bio_lcl.h
$(OPENSSL_PATH)/crypto/bn/bn_add.c
$(OPENSSL_PATH)/crypto/bn/bn_asm.c
$(OPENSSL_PATH)/crypto/bn/bn_blind.c
@@ -156,6 +170,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/bn/bn_srp.c
$(OPENSSL_PATH)/crypto/bn/bn_word.c
$(OPENSSL_PATH)/crypto/bn/bn_x931p.c
+ $(OPENSSL_PATH)/crypto/bn/rsaz_exp.h
+ $(OPENSSL_PATH)/crypto/bn/bn_prime.h
+ $(OPENSSL_PATH)/crypto/bn/bn_lcl.h
$(OPENSSL_PATH)/crypto/buffer/buf_err.c
$(OPENSSL_PATH)/crypto/buffer/buffer.c
$(OPENSSL_PATH)/crypto/cmac/cm_ameth.c
@@ -164,6 +181,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/comp/c_zlib.c
$(OPENSSL_PATH)/crypto/comp/comp_err.c
$(OPENSSL_PATH)/crypto/comp/comp_lib.c
+ $(OPENSSL_PATH)/crypto/comp/comp_lcl.h
$(OPENSSL_PATH)/crypto/conf/conf_api.c
$(OPENSSL_PATH)/crypto/conf/conf_def.c
$(OPENSSL_PATH)/crypto/conf/conf_err.c
@@ -172,6 +190,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/conf/conf_mod.c
$(OPENSSL_PATH)/crypto/conf/conf_sap.c
$(OPENSSL_PATH)/crypto/conf/conf_ssl.c
+ $(OPENSSL_PATH)/crypto/conf/conf_lcl.h
+ $(OPENSSL_PATH)/crypto/conf/conf_def.h
$(OPENSSL_PATH)/crypto/cpt_err.c
$(OPENSSL_PATH)/crypto/cryptlib.c
$(OPENSSL_PATH)/crypto/ctype.c
@@ -195,6 +215,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/des/set_key.c
$(OPENSSL_PATH)/crypto/des/str2key.c
$(OPENSSL_PATH)/crypto/des/xcbc_enc.c
+ $(OPENSSL_PATH)/crypto/des/spr.h
+ $(OPENSSL_PATH)/crypto/des/des_locl.h
$(OPENSSL_PATH)/crypto/dh/dh_ameth.c
$(OPENSSL_PATH)/crypto/dh/dh_asn1.c
$(OPENSSL_PATH)/crypto/dh/dh_check.c
@@ -209,6 +231,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/dh/dh_prn.c
$(OPENSSL_PATH)/crypto/dh/dh_rfc5114.c
$(OPENSSL_PATH)/crypto/dh/dh_rfc7919.c
+ $(OPENSSL_PATH)/crypto/dh/dh_locl.h
$(OPENSSL_PATH)/crypto/dso/dso_dl.c
$(OPENSSL_PATH)/crypto/dso/dso_dlfcn.c
$(OPENSSL_PATH)/crypto/dso/dso_err.c
@@ -216,6 +239,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/dso/dso_openssl.c
$(OPENSSL_PATH)/crypto/dso/dso_vms.c
$(OPENSSL_PATH)/crypto/dso/dso_win32.c
+ $(OPENSSL_PATH)/crypto/dso/dso_locl.h
$(OPENSSL_PATH)/crypto/ebcdic.c
$(OPENSSL_PATH)/crypto/err/err.c
$(OPENSSL_PATH)/crypto/err/err_prn.c
@@ -280,11 +304,13 @@ [Sources]
$(OPENSSL_PATH)/crypto/evp/pmeth_fn.c
$(OPENSSL_PATH)/crypto/evp/pmeth_gn.c
$(OPENSSL_PATH)/crypto/evp/pmeth_lib.c
+ $(OPENSSL_PATH)/crypto/evp/evp_locl.h
$(OPENSSL_PATH)/crypto/ex_data.c
$(OPENSSL_PATH)/crypto/getenv.c
$(OPENSSL_PATH)/crypto/hmac/hm_ameth.c
$(OPENSSL_PATH)/crypto/hmac/hm_pmeth.c
$(OPENSSL_PATH)/crypto/hmac/hmac.c
+ $(OPENSSL_PATH)/crypto/hmac/hmac_lcl.h
$(OPENSSL_PATH)/crypto/init.c
$(OPENSSL_PATH)/crypto/kdf/hkdf.c
$(OPENSSL_PATH)/crypto/kdf/kdf_err.c
@@ -292,10 +318,13 @@ [Sources]
$(OPENSSL_PATH)/crypto/kdf/tls1_prf.c
$(OPENSSL_PATH)/crypto/lhash/lh_stats.c
$(OPENSSL_PATH)/crypto/lhash/lhash.c
+ $(OPENSSL_PATH)/crypto/lhash/lhash_lcl.h
$(OPENSSL_PATH)/crypto/md4/md4_dgst.c
$(OPENSSL_PATH)/crypto/md4/md4_one.c
+ $(OPENSSL_PATH)/crypto/md4/md4_locl.h
$(OPENSSL_PATH)/crypto/md5/md5_dgst.c
$(OPENSSL_PATH)/crypto/md5/md5_one.c
+ $(OPENSSL_PATH)/crypto/md5/md5_locl.h
$(OPENSSL_PATH)/crypto/mem.c
$(OPENSSL_PATH)/crypto/mem_clr.c
$(OPENSSL_PATH)/crypto/mem_dbg.c
@@ -310,6 +339,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/modes/ofb128.c
$(OPENSSL_PATH)/crypto/modes/wrap128.c
$(OPENSSL_PATH)/crypto/modes/xts128.c
+ $(OPENSSL_PATH)/crypto/modes/modes_lcl.h
$(OPENSSL_PATH)/crypto/o_dir.c
$(OPENSSL_PATH)/crypto/o_fips.c
$(OPENSSL_PATH)/crypto/o_fopen.c
@@ -321,6 +351,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/objects/obj_err.c
$(OPENSSL_PATH)/crypto/objects/obj_lib.c
$(OPENSSL_PATH)/crypto/objects/obj_xref.c
+ $(OPENSSL_PATH)/crypto/objects/obj_dat.h
+ $(OPENSSL_PATH)/crypto/objects/obj_xref.h
+ $(OPENSSL_PATH)/crypto/objects/obj_lcl.h
$(OPENSSL_PATH)/crypto/ocsp/ocsp_asn.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_cl.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_err.c
@@ -331,6 +364,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/ocsp/ocsp_srv.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_vfy.c
$(OPENSSL_PATH)/crypto/ocsp/v3_ocsp.c
+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_lcl.h
$(OPENSSL_PATH)/crypto/pem/pem_all.c
$(OPENSSL_PATH)/crypto/pem/pem_err.c
$(OPENSSL_PATH)/crypto/pem/pem_info.c
@@ -358,6 +392,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/pkcs12/p12_sbag.c
$(OPENSSL_PATH)/crypto/pkcs12/p12_utl.c
$(OPENSSL_PATH)/crypto/pkcs12/pk12err.c
+ $(OPENSSL_PATH)/crypto/pkcs12/p12_lcl.h
$(OPENSSL_PATH)/crypto/pkcs7/bio_pk7.c
$(OPENSSL_PATH)/crypto/pkcs7/pk7_asn1.c
$(OPENSSL_PATH)/crypto/pkcs7/pk7_attr.c
@@ -366,6 +401,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/pkcs7/pk7_mime.c
$(OPENSSL_PATH)/crypto/pkcs7/pk7_smime.c
$(OPENSSL_PATH)/crypto/pkcs7/pkcs7err.c
+ $(OPENSSL_PATH)/crypto/ppc_arch.h
$(OPENSSL_PATH)/crypto/rand/drbg_ctr.c
$(OPENSSL_PATH)/crypto/rand/drbg_lib.c
$(OPENSSL_PATH)/crypto/rand/rand_egd.c
@@ -374,8 +410,10 @@ [Sources]
$(OPENSSL_PATH)/crypto/rand/rand_unix.c
$(OPENSSL_PATH)/crypto/rand/rand_vms.c
$(OPENSSL_PATH)/crypto/rand/rand_win.c
+ $(OPENSSL_PATH)/crypto/rand/rand_lcl.h
$(OPENSSL_PATH)/crypto/rc4/rc4_enc.c
$(OPENSSL_PATH)/crypto/rc4/rc4_skey.c
+ $(OPENSSL_PATH)/crypto/rc4/rc4_locl.h
$(OPENSSL_PATH)/crypto/rsa/rsa_ameth.c
$(OPENSSL_PATH)/crypto/rsa/rsa_asn1.c
$(OPENSSL_PATH)/crypto/rsa/rsa_chk.c
@@ -398,18 +436,24 @@ [Sources]
$(OPENSSL_PATH)/crypto/rsa/rsa_ssl.c
$(OPENSSL_PATH)/crypto/rsa/rsa_x931.c
$(OPENSSL_PATH)/crypto/rsa/rsa_x931g.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_locl.h
+ $(OPENSSL_PATH)/crypto/s390x_arch.h
$(OPENSSL_PATH)/crypto/sha/keccak1600.c
$(OPENSSL_PATH)/crypto/sha/sha1_one.c
$(OPENSSL_PATH)/crypto/sha/sha1dgst.c
$(OPENSSL_PATH)/crypto/sha/sha256.c
$(OPENSSL_PATH)/crypto/sha/sha512.c
+ $(OPENSSL_PATH)/crypto/sha/sha_locl.h
$(OPENSSL_PATH)/crypto/siphash/siphash.c
$(OPENSSL_PATH)/crypto/siphash/siphash_ameth.c
$(OPENSSL_PATH)/crypto/siphash/siphash_pmeth.c
+ $(OPENSSL_PATH)/crypto/siphash/siphash_local.h
$(OPENSSL_PATH)/crypto/sm3/m_sm3.c
$(OPENSSL_PATH)/crypto/sm3/sm3.c
+ $(OPENSSL_PATH)/crypto/sm3/sm3_locl.h
$(OPENSSL_PATH)/crypto/sm4/sm4.c
$(OPENSSL_PATH)/crypto/stack/stack.c
+ $(OPENSSL_PATH)/crypto/sparc_arch.h
$(OPENSSL_PATH)/crypto/threads_none.c
$(OPENSSL_PATH)/crypto/threads_pthread.c
$(OPENSSL_PATH)/crypto/threads_win.c
@@ -419,6 +463,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/ui/ui_null.c
$(OPENSSL_PATH)/crypto/ui/ui_openssl.c
$(OPENSSL_PATH)/crypto/ui/ui_util.c
+ $(OPENSSL_PATH)/crypto/ui/ui_locl.h
+ $(OPENSSL_PATH)/crypto/vms_rms.h
$(OPENSSL_PATH)/crypto/uid.c
$(OPENSSL_PATH)/crypto/x509/by_dir.c
$(OPENSSL_PATH)/crypto/x509/by_file.c
@@ -456,6 +502,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/x509/x_req.c
$(OPENSSL_PATH)/crypto/x509/x_x509.c
$(OPENSSL_PATH)/crypto/x509/x_x509a.c
+ $(OPENSSL_PATH)/crypto/x509/x509_lcl.h
$(OPENSSL_PATH)/crypto/x509v3/pcy_cache.c
$(OPENSSL_PATH)/crypto/x509v3/pcy_data.c
$(OPENSSL_PATH)/crypto/x509v3/pcy_lib.c
@@ -493,6 +540,11 @@ [Sources]
$(OPENSSL_PATH)/crypto/x509v3/v3_tlsf.c
$(OPENSSL_PATH)/crypto/x509v3/v3_utl.c
$(OPENSSL_PATH)/crypto/x509v3/v3err.c
+ $(OPENSSL_PATH)/crypto/x509v3/pcy_int.h
+ $(OPENSSL_PATH)/crypto/x509v3/v3_admis.h
+ $(OPENSSL_PATH)/crypto/x509v3/standard_exts.h
+ $(OPENSSL_PATH)/crypto/x509v3/ext_dat.h
+ $(OPENSSL_PATH)/ms/uplink.h
$(OPENSSL_PATH)/ssl/bio_ssl.c
$(OPENSSL_PATH)/ssl/d1_lib.c
$(OPENSSL_PATH)/ssl/d1_msg.c
@@ -537,6 +589,13 @@ [Sources]
$(OPENSSL_PATH)/ssl/t1_trce.c
$(OPENSSL_PATH)/ssl/tls13_enc.c
$(OPENSSL_PATH)/ssl/tls_srp.c
+ $(OPENSSL_PATH)/ssl/record/record_locl.h
+ $(OPENSSL_PATH)/ssl/statem/statem.h
+ $(OPENSSL_PATH)/ssl/statem/statem_locl.h
+ $(OPENSSL_PATH)/ssl/ssl_locl.h
+ $(OPENSSL_PATH)/ssl/record/record.h
+ $(OPENSSL_PATH)/ssl/ssl_cert_table.h
+ $(OPENSSL_PATH)/ssl/packet_locl.h
# Autogenerated files list ends here

ossl_store.c
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
index de05cac931d9..8134b45eda25 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
@@ -23,6 +23,7 @@ [Defines]

[Sources]
$(OPENSSL_PATH)/e_os.h
+ $(OPENSSL_PATH)/ms/uplink.h
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
$(OPENSSL_PATH)/crypto/aes/aes_cfb.c
@@ -32,7 +33,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/aes/aes_misc.c
$(OPENSSL_PATH)/crypto/aes/aes_ofb.c
$(OPENSSL_PATH)/crypto/aes/aes_wrap.c
+ $(OPENSSL_PATH)/crypto/aes/aes_locl.h
$(OPENSSL_PATH)/crypto/aria/aria.c
+ $(OPENSSL_PATH)/crypto/arm_arch.h
$(OPENSSL_PATH)/crypto/asn1/a_bitstr.c
$(OPENSSL_PATH)/crypto/asn1/a_d2i_fp.c
$(OPENSSL_PATH)/crypto/asn1/a_digest.c
@@ -97,12 +100,21 @@ [Sources]
$(OPENSSL_PATH)/crypto/asn1/x_sig.c
$(OPENSSL_PATH)/crypto/asn1/x_spki.c
$(OPENSSL_PATH)/crypto/asn1/x_val.c
+ $(OPENSSL_PATH)/crypto/asn1/standard_methods.h
+ $(OPENSSL_PATH)/crypto/asn1/charmap.h
+ $(OPENSSL_PATH)/crypto/asn1/tbl_standard.h
+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.h
+ $(OPENSSL_PATH)/crypto/asn1/asn1_locl.h
$(OPENSSL_PATH)/crypto/async/arch/async_null.c
$(OPENSSL_PATH)/crypto/async/arch/async_posix.c
$(OPENSSL_PATH)/crypto/async/arch/async_win.c
+ $(OPENSSL_PATH)/crypto/async/arch/async_posix.h
+ $(OPENSSL_PATH)/crypto/async/arch/async_null.h
+ $(OPENSSL_PATH)/crypto/async/arch/async_win.h
$(OPENSSL_PATH)/crypto/async/async.c
$(OPENSSL_PATH)/crypto/async/async_err.c
$(OPENSSL_PATH)/crypto/async/async_wait.c
+ $(OPENSSL_PATH)/crypto/async/async_locl.h
$(OPENSSL_PATH)/crypto/bio/b_addr.c
$(OPENSSL_PATH)/crypto/bio/b_dump.c
$(OPENSSL_PATH)/crypto/bio/b_sock.c
@@ -125,6 +137,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/bio/bss_mem.c
$(OPENSSL_PATH)/crypto/bio/bss_null.c
$(OPENSSL_PATH)/crypto/bio/bss_sock.c
+ $(OPENSSL_PATH)/crypto/bio/bio_lcl.h
$(OPENSSL_PATH)/crypto/bn/bn_add.c
$(OPENSSL_PATH)/crypto/bn/bn_asm.c
$(OPENSSL_PATH)/crypto/bn/bn_blind.c
@@ -156,6 +169,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/bn/bn_srp.c
$(OPENSSL_PATH)/crypto/bn/bn_word.c
$(OPENSSL_PATH)/crypto/bn/bn_x931p.c
+ $(OPENSSL_PATH)/crypto/bn/rsaz_exp.h
+ $(OPENSSL_PATH)/crypto/bn/bn_prime.h
+ $(OPENSSL_PATH)/crypto/bn/bn_lcl.h
$(OPENSSL_PATH)/crypto/buffer/buf_err.c
$(OPENSSL_PATH)/crypto/buffer/buffer.c
$(OPENSSL_PATH)/crypto/cmac/cm_ameth.c
@@ -164,6 +180,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/comp/c_zlib.c
$(OPENSSL_PATH)/crypto/comp/comp_err.c
$(OPENSSL_PATH)/crypto/comp/comp_lib.c
+ $(OPENSSL_PATH)/crypto/comp/comp_lcl.h
$(OPENSSL_PATH)/crypto/conf/conf_api.c
$(OPENSSL_PATH)/crypto/conf/conf_def.c
$(OPENSSL_PATH)/crypto/conf/conf_err.c
@@ -172,6 +189,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/conf/conf_mod.c
$(OPENSSL_PATH)/crypto/conf/conf_sap.c
$(OPENSSL_PATH)/crypto/conf/conf_ssl.c
+ $(OPENSSL_PATH)/crypto/conf/conf_lcl.h
+ $(OPENSSL_PATH)/crypto/conf/conf_def.h
$(OPENSSL_PATH)/crypto/cpt_err.c
$(OPENSSL_PATH)/crypto/cryptlib.c
$(OPENSSL_PATH)/crypto/ctype.c
@@ -195,6 +214,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/des/set_key.c
$(OPENSSL_PATH)/crypto/des/str2key.c
$(OPENSSL_PATH)/crypto/des/xcbc_enc.c
+ $(OPENSSL_PATH)/crypto/des/spr.h
+ $(OPENSSL_PATH)/crypto/des/des_locl.h
$(OPENSSL_PATH)/crypto/dh/dh_ameth.c
$(OPENSSL_PATH)/crypto/dh/dh_asn1.c
$(OPENSSL_PATH)/crypto/dh/dh_check.c
@@ -209,6 +230,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/dh/dh_prn.c
$(OPENSSL_PATH)/crypto/dh/dh_rfc5114.c
$(OPENSSL_PATH)/crypto/dh/dh_rfc7919.c
+ $(OPENSSL_PATH)/crypto/dh/dh_locl.h
$(OPENSSL_PATH)/crypto/dso/dso_dl.c
$(OPENSSL_PATH)/crypto/dso/dso_dlfcn.c
$(OPENSSL_PATH)/crypto/dso/dso_err.c
@@ -216,6 +238,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/dso/dso_openssl.c
$(OPENSSL_PATH)/crypto/dso/dso_vms.c
$(OPENSSL_PATH)/crypto/dso/dso_win32.c
+ $(OPENSSL_PATH)/crypto/dso/dso_locl.h
$(OPENSSL_PATH)/crypto/ebcdic.c
$(OPENSSL_PATH)/crypto/err/err.c
$(OPENSSL_PATH)/crypto/err/err_prn.c
@@ -257,6 +280,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/evp/evp_pkey.c
$(OPENSSL_PATH)/crypto/evp/m_md2.c
$(OPENSSL_PATH)/crypto/evp/m_md4.c
+ $(OPENSSL_PATH)/crypto/md4/md4_locl.h
$(OPENSSL_PATH)/crypto/evp/m_md5.c
$(OPENSSL_PATH)/crypto/evp/m_md5_sha1.c
$(OPENSSL_PATH)/crypto/evp/m_mdc2.c
@@ -280,11 +304,13 @@ [Sources]
$(OPENSSL_PATH)/crypto/evp/pmeth_fn.c
$(OPENSSL_PATH)/crypto/evp/pmeth_gn.c
$(OPENSSL_PATH)/crypto/evp/pmeth_lib.c
+ $(OPENSSL_PATH)/crypto/evp/evp_locl.h
$(OPENSSL_PATH)/crypto/ex_data.c
$(OPENSSL_PATH)/crypto/getenv.c
$(OPENSSL_PATH)/crypto/hmac/hm_ameth.c
$(OPENSSL_PATH)/crypto/hmac/hm_pmeth.c
$(OPENSSL_PATH)/crypto/hmac/hmac.c
+ $(OPENSSL_PATH)/crypto/hmac/hmac_lcl.h
$(OPENSSL_PATH)/crypto/init.c
$(OPENSSL_PATH)/crypto/kdf/hkdf.c
$(OPENSSL_PATH)/crypto/kdf/kdf_err.c
@@ -292,10 +318,12 @@ [Sources]
$(OPENSSL_PATH)/crypto/kdf/tls1_prf.c
$(OPENSSL_PATH)/crypto/lhash/lh_stats.c
$(OPENSSL_PATH)/crypto/lhash/lhash.c
+ $(OPENSSL_PATH)/crypto/lhash/lhash_lcl.h
$(OPENSSL_PATH)/crypto/md4/md4_dgst.c
$(OPENSSL_PATH)/crypto/md4/md4_one.c
$(OPENSSL_PATH)/crypto/md5/md5_dgst.c
$(OPENSSL_PATH)/crypto/md5/md5_one.c
+ $(OPENSSL_PATH)/crypto/md5/md5_locl.h
$(OPENSSL_PATH)/crypto/mem.c
$(OPENSSL_PATH)/crypto/mem_clr.c
$(OPENSSL_PATH)/crypto/mem_dbg.c
@@ -310,6 +338,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/modes/ofb128.c
$(OPENSSL_PATH)/crypto/modes/wrap128.c
$(OPENSSL_PATH)/crypto/modes/xts128.c
+ $(OPENSSL_PATH)/crypto/modes/modes_lcl.h
$(OPENSSL_PATH)/crypto/o_dir.c
$(OPENSSL_PATH)/crypto/o_fips.c
$(OPENSSL_PATH)/crypto/o_fopen.c
@@ -321,6 +350,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/objects/obj_err.c
$(OPENSSL_PATH)/crypto/objects/obj_lib.c
$(OPENSSL_PATH)/crypto/objects/obj_xref.c
+ $(OPENSSL_PATH)/crypto/objects/obj_dat.h
+ $(OPENSSL_PATH)/crypto/objects/obj_xref.h
+ $(OPENSSL_PATH)/crypto/objects/obj_lcl.h
$(OPENSSL_PATH)/crypto/ocsp/ocsp_asn.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_cl.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_err.c
@@ -331,6 +363,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/ocsp/ocsp_srv.c
$(OPENSSL_PATH)/crypto/ocsp/ocsp_vfy.c
$(OPENSSL_PATH)/crypto/ocsp/v3_ocsp.c
+ $(OPENSSL_PATH)/crypto/ocsp/ocsp_lcl.h
$(OPENSSL_PATH)/crypto/pem/pem_all.c
$(OPENSSL_PATH)/crypto/pem/pem_err.c
$(OPENSSL_PATH)/crypto/pem/pem_info.c
@@ -366,6 +399,8 @@ [Sources]
$(OPENSSL_PATH)/crypto/pkcs7/pk7_mime.c
$(OPENSSL_PATH)/crypto/pkcs7/pk7_smime.c
$(OPENSSL_PATH)/crypto/pkcs7/pkcs7err.c
+ $(OPENSSL_PATH)/crypto/pkcs12/p12_lcl.h
+ $(OPENSSL_PATH)/crypto/ppc_arch.h
$(OPENSSL_PATH)/crypto/rand/drbg_ctr.c
$(OPENSSL_PATH)/crypto/rand/drbg_lib.c
$(OPENSSL_PATH)/crypto/rand/rand_egd.c
@@ -374,8 +409,10 @@ [Sources]
$(OPENSSL_PATH)/crypto/rand/rand_unix.c
$(OPENSSL_PATH)/crypto/rand/rand_vms.c
$(OPENSSL_PATH)/crypto/rand/rand_win.c
+ $(OPENSSL_PATH)/crypto/rand/rand_lcl.h
$(OPENSSL_PATH)/crypto/rc4/rc4_enc.c
$(OPENSSL_PATH)/crypto/rc4/rc4_skey.c
+ $(OPENSSL_PATH)/crypto/rc4/rc4_locl.h
$(OPENSSL_PATH)/crypto/rsa/rsa_ameth.c
$(OPENSSL_PATH)/crypto/rsa/rsa_asn1.c
$(OPENSSL_PATH)/crypto/rsa/rsa_chk.c
@@ -398,18 +435,24 @@ [Sources]
$(OPENSSL_PATH)/crypto/rsa/rsa_ssl.c
$(OPENSSL_PATH)/crypto/rsa/rsa_x931.c
$(OPENSSL_PATH)/crypto/rsa/rsa_x931g.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_locl.h
$(OPENSSL_PATH)/crypto/sha/keccak1600.c
$(OPENSSL_PATH)/crypto/sha/sha1_one.c
$(OPENSSL_PATH)/crypto/sha/sha1dgst.c
$(OPENSSL_PATH)/crypto/sha/sha256.c
$(OPENSSL_PATH)/crypto/sha/sha512.c
+ $(OPENSSL_PATH)/crypto/sha/sha_locl.h
$(OPENSSL_PATH)/crypto/siphash/siphash.c
$(OPENSSL_PATH)/crypto/siphash/siphash_ameth.c
$(OPENSSL_PATH)/crypto/siphash/siphash_pmeth.c
+ $(OPENSSL_PATH)/crypto/siphash/siphash_local.h
$(OPENSSL_PATH)/crypto/sm3/m_sm3.c
$(OPENSSL_PATH)/crypto/sm3/sm3.c
+ $(OPENSSL_PATH)/crypto/sm3/sm3_locl.h
$(OPENSSL_PATH)/crypto/sm4/sm4.c
$(OPENSSL_PATH)/crypto/stack/stack.c
+ $(OPENSSL_PATH)/crypto/s390x_arch.h
+ $(OPENSSL_PATH)/crypto/sparc_arch.h
$(OPENSSL_PATH)/crypto/threads_none.c
$(OPENSSL_PATH)/crypto/threads_pthread.c
$(OPENSSL_PATH)/crypto/threads_win.c
@@ -419,7 +462,9 @@ [Sources]
$(OPENSSL_PATH)/crypto/ui/ui_null.c
$(OPENSSL_PATH)/crypto/ui/ui_openssl.c
$(OPENSSL_PATH)/crypto/ui/ui_util.c
+ $(OPENSSL_PATH)/crypto/ui/ui_locl.h
$(OPENSSL_PATH)/crypto/uid.c
+ $(OPENSSL_PATH)/crypto/vms_rms.h
$(OPENSSL_PATH)/crypto/x509/by_dir.c
$(OPENSSL_PATH)/crypto/x509/by_file.c
$(OPENSSL_PATH)/crypto/x509/t_crl.c
@@ -456,6 +501,7 @@ [Sources]
$(OPENSSL_PATH)/crypto/x509/x_req.c
$(OPENSSL_PATH)/crypto/x509/x_x509.c
$(OPENSSL_PATH)/crypto/x509/x_x509a.c
+ $(OPENSSL_PATH)/crypto/x509/x509_lcl.h
$(OPENSSL_PATH)/crypto/x509v3/pcy_cache.c
$(OPENSSL_PATH)/crypto/x509v3/pcy_data.c
$(OPENSSL_PATH)/crypto/x509v3/pcy_lib.c
@@ -493,8 +539,13 @@ [Sources]
$(OPENSSL_PATH)/crypto/x509v3/v3_tlsf.c
$(OPENSSL_PATH)/crypto/x509v3/v3_utl.c
$(OPENSSL_PATH)/crypto/x509v3/v3err.c
+ $(OPENSSL_PATH)/crypto/x509v3/pcy_int.h
+ $(OPENSSL_PATH)/crypto/x509v3/v3_admis.h
+ $(OPENSSL_PATH)/crypto/x509v3/standard_exts.h
+ $(OPENSSL_PATH)/crypto/x509v3/ext_dat.h
# Autogenerated files list ends here
-
+ buildinf.h
+ rand_pool_noise.h
ossl_store.c
rand_pool.c

--
2.18.0.windows.1


Re: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.

Dong, Eric
 

Hi Liming & Star,

-----Original Message-----
From: Gao, Liming
Sent: Friday, August 16, 2019 11:44 AM
To: Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>;
devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Yao,
Jiewen <jiewen.yao@intel.com>; Kinney, Michael D
<michael.d.kinney@intel.com>
Subject: RE: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test
Then Write" Macros.

Eric:

-----Original Message-----
From: Dong, Eric
Sent: Friday, August 16, 2019 10:20 AM
To: Zeng, Star <star.zeng@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Yao,
Jiewen <jiewen.yao@intel.com>; Gao, Liming <liming.gao@intel.com>;
Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add
"Test Then Write" Macros.



-----Original Message-----
From: Zeng, Star
Sent: Friday, August 16, 2019 10:08 AM
To: Dong, Eric <eric.dong@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>;
Yao, Jiewen <jiewen.yao@intel.com>; Gao, Liming
<liming.gao@intel.com>;
Kinney,
Michael D <michael.d.kinney@intel.com>; Zeng, Star
<star.zeng@intel.com>
Subject: RE: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add
"Test Then Write" Macros.



-----Original Message-----
From: Dong, Eric
Sent: Friday, August 16, 2019 9:27 AM
To: Zeng, Star <star.zeng@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>
Subject: RE: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add
"Test Then Write" Macros.

-----Original Message-----
From: Zeng, Star
Sent: Friday, August 16, 2019 9:15 AM
To: Dong, Eric <eric.dong@intel.com>; devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>;
Zeng, Star <star.zeng@intel.com>
Subject: RE: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib:
Add "Test Then Write" Macros.



-----Original Message-----
From: Dong, Eric
Sent: Thursday, August 15, 2019 10:51 AM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek
<lersek@redhat.com>; Zeng, Star <star.zeng@intel.com>
Subject: [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add
"Test Then Write" Macros.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Add below new micros which test the current value before write
the new value. Only write new value when current value not same
as new
value.
CPU_REGISTER_TABLE_TEST_THEN_WRITE32
CPU_REGISTER_TABLE_TEST_THEN_WRITE64
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD

Also add below API:
CpuRegisterTableTestThenWrite

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Star Zeng <star.zeng@intel.com>
---
UefiCpuPkg/Include/AcpiCpuData.h | 1 +
.../Include/Library/RegisterCpuFeaturesLib.h | 91
+++++++++++++++++++
.../RegisterCpuFeaturesLib.c | 45 ++++++++-
3 files changed, 134 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/Include/AcpiCpuData.h
b/UefiCpuPkg/Include/AcpiCpuData.h
index b963a2f592..472a1a8070 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -81,6 +81,7 @@ typedef struct {
UINT16 Reserved; // offset 10 - 11
UINT32 HighIndex; // offset 12-15, only valid for
MemoryMapped
UINT64 Value; // offset 16-23
+ UINT8 TestThenWrite; // 0ffset 24
Could we use one byte of the Reserved field, but not add new field?
And use BOOLEAN type for it?
I'm not sure whether use the Reserved field is an correct approach,
do you have samples which use the reserved fields?
But I think add new field is a more safe one.
What "more safe" means here? Adding new field extends the structure,
from
the structure layout view of point, it is an incompatible change, the
structure size is not just from 24 to 25 bytes, but to be nature
aligned, the structure
size
will be (24 + 8) 32. Since there is Reserved field can be reused,
that size
impact
can be removed.
Yes, agree the size impact. I'm just not clear whether the Reserved
field can be used. Whether it has compatible impact.


FspGlobalData.h:
SHA-1: a2e61f341d26a78751b2f19b5004c6bbfc8b4fa9
* IntelFsp2Pkg: Support FSP Dispatch mode

MemoryProfile.h
SHA-1: 072a3ca1d36a42aec97f871c808776ee7038ca06 (related to
94092aa60341a3e4b1e1ea7c362781b8404ac538)
* MdeModulePkg MemoryProfile.h:two bytes of Reserved[4] as
ActionStringOffset
If so many examples already did it. I think we can also do it.


If needed, more comments from Ray, Laszlo, Jiewen, Liming and Mike
will
be
better.
Yes, I think we need get more comments from them.
I think to reuse the reserved field is a good solution.
Thanks for this valuable input, I will send V4 patch to use Reserved field.

Thanks,
Eric


Thanks
Liming

Thanks,
Eric


Thanks,
Star


Thanks,
Eric

Thanks,
Star

} CPU_REGISTER_TABLE_ENTRY;

//
diff --git
a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index e420e7f075..5bd464b32e 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -348,6 +348,32 @@ CpuRegisterTableWrite (
IN UINT64 Value
);

+/**
+ Adds an entry in specified register table.
+
+ This function adds an entry in specified register table,
+ with given register type, register index, bit section and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a
+ register
table entry
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] ValueMask Mask of bits in register to write
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+VOID
+EFIAPI
+CpuRegisterTableTestThenWrite (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
+ );
+
/**
Adds an entry in specified Pre-SMM register table.

@@ -390,6 +416,26 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType,
Index, MAX_UINT32, Value); \
} while(FALSE);

+/**
+ Adds a 32-bit register write entry in specified register table.
+
+ This macro adds an entry in specified register table, with
+ given register type, register index, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a
+ register
table entry.
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+#define
CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber,
RegisterType, Index, Value) \
+ do { \
+ CpuRegisterTableTestThenWrite (ProcessorNumber,
+RegisterType, Index, MAX_UINT32, Value); \
+ } while(FALSE);
+
/**
Adds a 64-bit register write entry in specified register table.

@@ -408,6 +454,26 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType,
Index, MAX_UINT64, Value); \
} while(FALSE);

+/**
+ Adds a 64-bit register write entry in specified register table.
+
+ This macro adds an entry in specified register table, with
+ given register type, register index, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a
+ register
table entry.
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+#define
CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber,
RegisterType, Index, Value) \
+ do { \
+ CpuRegisterTableTestThenWrite (ProcessorNumber,
+RegisterType, Index, MAX_UINT64, Value); \
+ } while(FALSE);
+
/**
Adds a bit field write entry in specified register table.

@@ -431,6 +497,31 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index,
~ValueMask, Value); \
} while(FALSE);

+/**
+ Adds a bit field write entry in specified register table.
+
+ This macro adds an entry in specified register table, with
+ given register type, register index, bit field section, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a
+ register
table entry.
+ @param[in] RegisterType Type of the register to program.
+ @param[in] Index Index of the register to program.
+ @param[in] Type The data type name of a register structure.
+ @param[in] Field The bit fiel name in register structure to
write.
+ @param[in] Value Value to write to the bit field.
+
+ @note This service could be called by BSP only.
+**/
+#define
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber,
RegisterType, Index, Type, Field, Value) \
+ do { \
+ UINT64 ValueMask; \
+ ValueMask = MAX_UINT64;
\
+ ((Type *)(&ValueMask))->Field = 0;
\
+ CpuRegisterTableTestThenWrite (ProcessorNumber,
+ RegisterType, Index,
~ValueMask, Value); \
+ } while(FALSE);
+
/**
Adds a 32-bit register write entry in specified register table.

diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib
.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib
.c index 67885bf69b..e9769882b9 100644
---
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib
.c
+++
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib
.c @@ -1025,6 +1025,8 @@ EnlargeRegisterTable (
@param[in] ValidBitStart Start of the bit section
@param[in] ValidBitLength Length of the bit section
@param[in] Value Value to write
+ @param[in] TestThenWrite Whether need to test current Value
before
writing.
+
**/
VOID
CpuRegisterTableWriteWorker (
@@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker (
IN UINT64 Index,
IN UINT8 ValidBitStart,
IN UINT8 ValidBitLength,
- IN UINT64 Value
+ IN UINT64 Value,
+ IN UINT8 TestThenWrite
)
{
CPU_FEATURES_DATA *CpuFeaturesData;
@@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker (
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart
= ValidBitStart;

RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =
ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
+ RegisterTableEntry[RegisterTable->TableLength].TestThenWrite
+ = TestThenWrite;

RegisterTable->TableLength++; } @@ -1105,7 +1109,42 @@
CpuRegisterTableWrite (
Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
- CpuRegisterTableWriteWorker (FALSE, ProcessorNumber,
RegisterType, Index, Start, Length, Value);
+ CpuRegisterTableWriteWorker (FALSE, ProcessorNumber,
+RegisterType, Index, Start, Length, Value, FALSE); }
+
+/**
+ Adds an entry in specified register table.
+
+ This function adds an entry in specified register table,
+ with given register type, register index, bit section and value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a
+ register
table entry
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] ValueMask Mask of bits in register to write
+ @param[in] Value Value to write
+ @param[in] TestThenWrite Whether need to test current Value
before
writing.
+
+ @note This service could be called by BSP only.
+**/
+VOID
+EFIAPI
+CpuRegisterTableTestThenWrite (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
+ )
+{
+ UINT8 Start;
+ UINT8 End;
+ UINT8 Length;
+
+ Start = (UINT8)LowBitSet64 (ValueMask);
+ End = (UINT8)HighBitSet64 (ValueMask);
+ Length = End - Start + 1;
+ CpuRegisterTableWriteWorker (FALSE, ProcessorNumber,
+ RegisterType, Index, Start, Length, Value, TRUE);
}

/**
@@ -1139,7 +1178,7 @@ PreSmmCpuRegisterTableWrite (
Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
- CpuRegisterTableWriteWorker (TRUE, ProcessorNumber,
RegisterType, Index, Start, Length, Value);
+ CpuRegisterTableWriteWorker (TRUE, ProcessorNumber,
+ RegisterType, Index, Start, Length, Value, FALSE);
}

/**
--
2.21.0.windows.1


[Patch v4 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.

Dong, Eric
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}

1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.

The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.

The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
---
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 --
.../CpuCommonFeaturesLib.c | 8 +-
.../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------
.../CpuCommonFeaturesLib/MachineCheck.c | 23 ++-
4 files changed, 58 insertions(+), 129 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index 25d0174727..b2390e6c39 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -848,21 +848,6 @@ X2ApicInitialize (
IN BOOLEAN State
);

-/**
- Prepares for the data used by CPU feature detection and initialization.
-
- @param[in] NumberOfProcessors The number of CPUs in the platform.
-
- @return Pointer to a buffer of CPU related configuration data.
-
- @note This service could be called by BSP only.
-**/
-VOID *
-EFIAPI
-FeatureControlGetConfigData (
- IN UINTN NumberOfProcessors
- );
-
/**
Prepares for the data used by CPU feature detection and initialization.

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index fd43b8d662..f0dd3a3b43 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature (
"Lock Feature Control Register",
- FeatureControlGetConfigData,
+ NULL,
LockFeatureControlRegisterSupport,
LockFeatureControlRegisterInitialize,
CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER,
@@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature (
"SMX",
- FeatureControlGetConfigData,
+ NULL,
SmxSupport,
SmxInitialize,
CPU_FEATURE_SMX,
@@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature (
"VMX",
- FeatureControlGetConfigData,
+ NULL,
VmxSupport,
VmxInitialize,
CPU_FEATURE_VMX,
@@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature (
"LMCE",
- FeatureControlGetConfigData,
+ NULL,
LmceSupport,
LmceInitialize,
CPU_FEATURE_LMCE,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index 3712ef1e5c..6679df8ba4 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -8,28 +8,6 @@

#include "CpuCommonFeatures.h"

-/**
- Prepares for the data used by CPU feature detection and initialization.
-
- @param[in] NumberOfProcessors The number of CPUs in the platform.
-
- @return Pointer to a buffer of CPU related configuration data.
-
- @note This service could be called by BSP only.
-**/
-VOID *
-EFIAPI
-FeatureControlGetConfigData (
- IN UINTN NumberOfProcessors
- )
-{
- VOID *ConfigData;
-
- ConfigData = AllocateZeroPool (sizeof (MSR_IA32_FEATURE_CONTROL_REGISTER) * NumberOfProcessors);
- ASSERT (ConfigData != NULL);
- return ConfigData;
-}
-
/**
Detects if VMX feature supported on current processor.

@@ -54,11 +32,6 @@ VmxSupport (
IN VOID *ConfigData OPTIONAL
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- MsrRegister[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX == 1);
}

@@ -88,8 +61,6 @@ VmxInitialize (
IN BOOLEAN State
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
//
// The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL is core for
// below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
@@ -103,18 +74,15 @@ VmxInitialize (
}
}

- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.EnableVmxOutsideSmx,
- (State) ? 1 : 0
- );
- }
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.EnableVmxOutsideSmx,
+ (State) ? 1 : 0
+ );
+
return RETURN_SUCCESS;
}

@@ -142,11 +110,6 @@ LockFeatureControlRegisterSupport (
IN VOID *ConfigData OPTIONAL
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- MsrRegister[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
return TRUE;
}

@@ -176,8 +139,6 @@ LockFeatureControlRegisterInitialize (
IN BOOLEAN State
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
//
// The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
// below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
@@ -191,18 +152,15 @@ LockFeatureControlRegisterInitialize (
}
}

- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.Lock,
- 1
- );
- }
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.Lock,
+ 1
+ );
+
return RETURN_SUCCESS;
}

@@ -230,11 +188,6 @@ SmxSupport (
IN VOID *ConfigData OPTIONAL
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- MsrRegister[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX == 1);
}

@@ -265,7 +218,6 @@ SmxInitialize (
IN BOOLEAN State
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
RETURN_STATUS Status;

//
@@ -288,35 +240,32 @@ SmxInitialize (
Status = RETURN_UNSUPPORTED;
}

- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.SenterLocalFunctionEnables,
- (State) ? 0x7F : 0
- );
-
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.SenterGlobalEnable,
- (State) ? 1 : 0
- );
-
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.EnableVmxInsideSmx,
- (State) ? 1 : 0
- );
- }
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.SenterLocalFunctionEnables,
+ (State) ? 0x7F : 0
+ );
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.SenterGlobalEnable,
+ (State) ? 1 : 0
+ );
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.EnableVmxInsideSmx,
+ (State) ? 1 : 0
+ );
+
return Status;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index 2528e0044e..01fd6bb54d 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -319,8 +319,6 @@ LmceInitialize (
IN BOOLEAN State
)
{
- MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister;
-
//
// The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program
// MSR_IA32_MISC_ENABLE for thread 0 in each core.
@@ -333,17 +331,14 @@ LmceInitialize (
}
}

- ASSERT (ConfigData != NULL);
- MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;
- if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
- CPU_REGISTER_TABLE_WRITE_FIELD (
- ProcessorNumber,
- Msr,
- MSR_IA32_FEATURE_CONTROL,
- MSR_IA32_FEATURE_CONTROL_REGISTER,
- Bits.LmceOn,
- (State) ? 1 : 0
- );
- }
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.LmceOn,
+ (State) ? 1 : 0
+ );
+
return RETURN_SUCCESS;
}
--
2.21.0.windows.1


[Patch v4 5/6] UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic.

Dong, Eric
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Supports new logic which test current value before write new value.
Only write new value when current value not same as new value.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
---
.../CpuFeaturesInitialize.c | 31 ++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 63bc50a55f..0a4fcff033 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -826,6 +826,7 @@ ProgramProcessorRegister (
UINTN ValidThreadCount;
UINT32 *ValidCoreCountPerPackage;
EFI_STATUS Status;
+ UINT64 CurrentValue;

//
// Traverse Register Table of this logical processor
@@ -848,7 +849,16 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) {
break;
}
-
+ if (RegisterTableEntry->TestThenWrite) {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -857,10 +867,29 @@ ProgramProcessorRegister (
);
ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
break;
+
//
// The specified register is Model Specific Register
//
case Msr:
+ if (RegisterTableEntry->TestThenWrite) {
+ Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ if (Value == RegisterTableEntry->Value) {
+ break;
+ }
+ } else {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
+ }
+
if (RegisterTableEntry->ValidBitLength >= 64) {
//
// If length is not less than 64 bits, then directly write without reading
--
2.21.0.windows.1


[Patch v4 4/6] UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.

Dong, Eric
 

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
---
.../CpuFeaturesInitialize.c | 110 ++++++++++--------
1 file changed, 63 insertions(+), 47 deletions(-)

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index fb0535edd6..63bc50a55f 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -744,6 +744,58 @@ LibWaitForSemaphore (
) != Value);
}

+/**
+ Read / write CR value.
+
+ @param[in] CrIndex The CR index which need to read/write.
+ @param[in] Read Read or write. TRUE is read.
+ @param[in,out] CrValue CR value.
+
+ @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPORTED.
+**/
+UINTN
+ReadWriteCr (
+ IN UINT32 CrIndex,
+ IN BOOLEAN Read,
+ IN OUT UINTN *CrValue
+ )
+{
+ switch (CrIndex) {
+ case 0:
+ if (Read) {
+ *CrValue = AsmReadCr0 ();
+ } else {
+ AsmWriteCr0 (*CrValue);
+ }
+ break;
+ case 2:
+ if (Read) {
+ *CrValue = AsmReadCr2 ();
+ } else {
+ AsmWriteCr2 (*CrValue);
+ }
+ break;
+ case 3:
+ if (Read) {
+ *CrValue = AsmReadCr3 ();
+ } else {
+ AsmWriteCr3 (*CrValue);
+ }
+ break;
+ case 4:
+ if (Read) {
+ *CrValue = AsmReadCr4 ();
+ } else {
+ AsmWriteCr4 (*CrValue);
+ }
+ break;
+ default:
+ return EFI_UNSUPPORTED;;
+ }
+
+ return EFI_SUCCESS;
+}
+
/**
Initialize the CPU registers from a register table.

@@ -773,6 +825,7 @@ ProgramProcessorRegister (
UINTN ProcessorIndex;
UINTN ValidThreadCount;
UINT32 *ValidCoreCountPerPackage;
+ EFI_STATUS Status;

//
// Traverse Register Table of this logical processor
@@ -791,55 +844,18 @@ ProgramProcessorRegister (
// The specified register is Control Register
//
case ControlRegister:
- switch (RegisterTableEntry->Index) {
- case 0:
- Value = AsmReadCr0 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- AsmWriteCr0 (Value);
- break;
- case 2:
- Value = AsmReadCr2 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- AsmWriteCr2 (Value);
- break;
- case 3:
- Value = AsmReadCr3 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- AsmWriteCr3 (Value);
- break;
- case 4:
- Value = AsmReadCr4 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- AsmWriteCr4 (Value);
- break;
- case 8:
- //
- // Do we need to support CR8?
- //
- break;
- default:
+ Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
+ if (EFI_ERROR (Status)) {
break;
}
+
+ Value = (UINTN) BitFieldWrite64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
break;
//
// The specified register is Model Specific Register
--
2.21.0.windows.1


[Patch v4 3/6] UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic.

Dong, Eric
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Supports new logic which test current value before write new value.
Only write new value when current value not same as new value.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 627a3b87ac..ba5cc0194c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -241,6 +241,7 @@ ProgramProcessorRegister (
UINTN ValidThreadCount;
UINT32 *ValidCoreCountPerPackage;
EFI_STATUS Status;
+ UINT64 CurrentValue;

//
// Traverse Register Table of this logical processor
@@ -263,6 +264,16 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) {
break;
}
+ if (RegisterTableEntry->TestThenWrite) {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -275,6 +286,24 @@ ProgramProcessorRegister (
// The specified register is Model Specific Register
//
case Msr:
+ if (RegisterTableEntry->TestThenWrite) {
+ Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ if (Value == RegisterTableEntry->Value) {
+ break;
+ }
+ } else {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
+ }
+
//
// If this function is called to restore register setting after INIT signal,
// there is no need to restore MSRs in register table.
--
2.21.0.windows.1


[Patch v4 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action.

Dong, Eric
 

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 104 ++++++++++++++++++------------
1 file changed, 62 insertions(+), 42 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index d8c6b19ead..627a3b87ac 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -159,6 +159,58 @@ S3WaitForSemaphore (
) != Value);
}

+/**
+ Read / write CR value.
+
+ @param[in] CrIndex The CR index which need to read/write.
+ @param[in] Read Read or write. TRUE is read.
+ @param[in,out] CrValue CR value.
+
+ @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPORTED.
+**/
+UINTN
+ReadWriteCr (
+ IN UINT32 CrIndex,
+ IN BOOLEAN Read,
+ IN OUT UINTN *CrValue
+ )
+{
+ switch (CrIndex) {
+ case 0:
+ if (Read) {
+ *CrValue = AsmReadCr0 ();
+ } else {
+ AsmWriteCr0 (*CrValue);
+ }
+ break;
+ case 2:
+ if (Read) {
+ *CrValue = AsmReadCr2 ();
+ } else {
+ AsmWriteCr2 (*CrValue);
+ }
+ break;
+ case 3:
+ if (Read) {
+ *CrValue = AsmReadCr3 ();
+ } else {
+ AsmWriteCr3 (*CrValue);
+ }
+ break;
+ case 4:
+ if (Read) {
+ *CrValue = AsmReadCr4 ();
+ } else {
+ AsmWriteCr4 (*CrValue);
+ }
+ break;
+ default:
+ return EFI_UNSUPPORTED;;
+ }
+
+ return EFI_SUCCESS;
+}
+
/**
Initialize the CPU registers from a register table.

@@ -188,6 +240,7 @@ ProgramProcessorRegister (
UINTN ProcessorIndex;
UINTN ValidThreadCount;
UINT32 *ValidCoreCountPerPackage;
+ EFI_STATUS Status;

//
// Traverse Register Table of this logical processor
@@ -206,50 +259,17 @@ ProgramProcessorRegister (
// The specified register is Control Register
//
case ControlRegister:
- switch (RegisterTableEntry->Index) {
- case 0:
- Value = AsmReadCr0 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINTN) RegisterTableEntry->Value
- );
- AsmWriteCr0 (Value);
- break;
- case 2:
- Value = AsmReadCr2 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINTN) RegisterTableEntry->Value
- );
- AsmWriteCr2 (Value);
- break;
- case 3:
- Value = AsmReadCr3 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINTN) RegisterTableEntry->Value
- );
- AsmWriteCr3 (Value);
- break;
- case 4:
- Value = AsmReadCr4 ();
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINTN) RegisterTableEntry->Value
- );
- AsmWriteCr4 (Value);
- break;
- default:
+ Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
+ if (EFI_ERROR (Status)) {
break;
}
+ Value = (UINTN) BitFieldWrite64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
break;
//
// The specified register is Model Specific Register
--
2.21.0.windows.1


[Patch v4 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.

Dong, Eric
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Add below new micros which test the current value before write the new
value. Only write new value when current value not same as new value.
CPU_REGISTER_TABLE_TEST_THEN_WRITE32
CPU_REGISTER_TABLE_TEST_THEN_WRITE64
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD

Also add below API:
CpuRegisterTableTestThenWrite

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Star Zeng <star.zeng@intel.com>
---
UefiCpuPkg/Include/AcpiCpuData.h | 3 +-
.../Include/Library/RegisterCpuFeaturesLib.h | 91 +++++++++++++++++++
.../RegisterCpuFeaturesLib.c | 44 ++++++++-
3 files changed, 134 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index b963a2f592..77da5d4455 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -78,7 +78,8 @@ typedef struct {
UINT32 Index; // offset 4 - 7
UINT8 ValidBitStart; // offset 8
UINT8 ValidBitLength; // offset 9
- UINT16 Reserved; // offset 10 - 11
+ BOOLEAN TestThenWrite; // offset 10
+ UINT8 Reserved1; // offset 11
UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped
UINT64 Value; // offset 16-23
} CPU_REGISTER_TABLE_ENTRY;
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index e420e7f075..5bd464b32e 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -348,6 +348,32 @@ CpuRegisterTableWrite (
IN UINT64 Value
);

+/**
+ Adds an entry in specified register table.
+
+ This function adds an entry in specified register table, with given register type,
+ register index, bit section and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a register table entry
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] ValueMask Mask of bits in register to write
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+VOID
+EFIAPI
+CpuRegisterTableTestThenWrite (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
+ );
+
/**
Adds an entry in specified Pre-SMM register table.

@@ -390,6 +416,26 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT32, Value); \
} while(FALSE);

+/**
+ Adds a 32-bit register write entry in specified register table.
+
+ This macro adds an entry in specified register table, with given register type,
+ register index, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a register table entry.
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+#define CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber, RegisterType, Index, Value) \
+ do { \
+ CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, MAX_UINT32, Value); \
+ } while(FALSE);
+
/**
Adds a 64-bit register write entry in specified register table.

@@ -408,6 +454,26 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT64, Value); \
} while(FALSE);

+/**
+ Adds a 64-bit register write entry in specified register table.
+
+ This macro adds an entry in specified register table, with given register type,
+ register index, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a register table entry.
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+#define CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber, RegisterType, Index, Value) \
+ do { \
+ CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, MAX_UINT64, Value); \
+ } while(FALSE);
+
/**
Adds a bit field write entry in specified register table.

@@ -431,6 +497,31 @@ PreSmmCpuRegisterTableWrite (
CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMask, Value); \
} while(FALSE);

+/**
+ Adds a bit field write entry in specified register table.
+
+ This macro adds an entry in specified register table, with given register type,
+ register index, bit field section, and value.
+
+ Driver will test the current value before setting new value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a register table entry.
+ @param[in] RegisterType Type of the register to program.
+ @param[in] Index Index of the register to program.
+ @param[in] Type The data type name of a register structure.
+ @param[in] Field The bit fiel name in register structure to write.
+ @param[in] Value Value to write to the bit field.
+
+ @note This service could be called by BSP only.
+**/
+#define CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber, RegisterType, Index, Type, Field, Value) \
+ do { \
+ UINT64 ValueMask; \
+ ValueMask = MAX_UINT64; \
+ ((Type *)(&ValueMask))->Field = 0; \
+ CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, ~ValueMask, Value); \
+ } while(FALSE);
+
/**
Adds a 32-bit register write entry in specified register table.

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 67885bf69b..58910b8891 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -1025,6 +1025,8 @@ EnlargeRegisterTable (
@param[in] ValidBitStart Start of the bit section
@param[in] ValidBitLength Length of the bit section
@param[in] Value Value to write
+ @param[in] TestThenWrite Whether need to test current Value before writing.
+
**/
VOID
CpuRegisterTableWriteWorker (
@@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker (
IN UINT64 Index,
IN UINT8 ValidBitStart,
IN UINT8 ValidBitLength,
- IN UINT64 Value
+ IN UINT64 Value,
+ IN BOOLEAN TestThenWrite
)
{
CPU_FEATURES_DATA *CpuFeaturesData;
@@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker (
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
+ RegisterTableEntry[RegisterTable->TableLength].TestThenWrite = TestThenWrite;

RegisterTable->TableLength++;
}
@@ -1105,7 +1109,41 @@ CpuRegisterTableWrite (
Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
- CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value);
+ CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);
+}
+
+/**
+ Adds an entry in specified register table.
+
+ This function adds an entry in specified register table, with given register type,
+ register index, bit section and value.
+
+ @param[in] ProcessorNumber The index of the CPU to add a register table entry
+ @param[in] RegisterType Type of the register to program
+ @param[in] Index Index of the register to program
+ @param[in] ValueMask Mask of bits in register to write
+ @param[in] Value Value to write
+
+ @note This service could be called by BSP only.
+**/
+VOID
+EFIAPI
+CpuRegisterTableTestThenWrite (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
+ )
+{
+ UINT8 Start;
+ UINT8 End;
+ UINT8 Length;
+
+ Start = (UINT8)LowBitSet64 (ValueMask);
+ End = (UINT8)HighBitSet64 (ValueMask);
+ Length = End - Start + 1;
+ CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, TRUE);
}

/**
@@ -1139,7 +1177,7 @@ PreSmmCpuRegisterTableWrite (
Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
- CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index, Start, Length, Value);
+ CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);
}

/**
--
2.21.0.windows.1


[Patch v4 0/6] Add "test then write" mechanism

Dong, Eric
 

v4 changes:
1. Split Reserved field and use one byte as TestThenWrite field.

v3 changes:
1. Avoid changing exist API CpuRegisterTableWrite, add new API CpuRegisterTableTestThenWrite which align new adds macros.
Only 1/6 patch been changed in v3.

V2 changes:
1. Split CR read/write action in to one discrete patch 2. Keep the old logic which continue the process if error found.

Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}

With below steps, the Bits.Lock bit will lose its value:
1. Trig normal boot, the Bits.Lock is 0. 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table during normal boot phase. so it's
still 0 after resume.
This is not an expect behavior. The expect result is the value should always 1 after booting or resuming from S3.

The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot. So the insert
action may be skip after warm reboot.

The solution for this issue is:
1. Always add "Test then Set" action for above referred MSRs.
2. Detect current value before set new value. Only set new value when
current value not same as new value.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>


Eric Dong (6):
UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.
UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action.
UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic.
UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.
UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value
logic.
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.

UefiCpuPkg/Include/AcpiCpuData.h | 1 +
.../Include/Library/RegisterCpuFeaturesLib.h | 91 +++++++++++
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 --
.../CpuCommonFeaturesLib.c | 8 +-
.../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------
.../CpuCommonFeaturesLib/MachineCheck.c | 23 ++-
.../CpuFeaturesInitialize.c | 139 +++++++++++------
.../RegisterCpuFeaturesLib.c | 45 +++++-
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 133 +++++++++++------
9 files changed, 375 insertions(+), 221 deletions(-)

--
2.21.0.windows.1