[PATCH 1/3] OvmfPkg/PlatformInitLib: update address space layout comment


Gerd Hoffmann
 

Move the commment up so it is placed just before the address space
calculations start. Also add q35 memory layout.

Signed-off-by: Gerd Hoffmann <kraxel@...>
---
OvmfPkg/Library/PlatformInitLib/Platform.c | 36 ++++++++++++----------
1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
index 9fee6e481038..678e8e329023 100644
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -152,26 +152,12 @@ PlatformMemMapInitialization (
return;
}

- PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
- PciExBarBase = 0;
- if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- //
- // The MMCONFIG area is expected to fall between the top of low RAM and
- // the base of the 32-bit PCI host aperture.
- //
- PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);
- ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase);
- ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
- PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
- } else {
- ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base);
- PciBase = PlatformInfoHob->Uc32Base;
- }
-
//
// address purpose size
// ------------ -------- -------------------------
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) (pc)
+ // 0xB0000000 MMCONFIG 256 MB (q35)
+ // 0xC0000000 PCI MMIO 960 MB (q35)
// 0xFC000000 gap 44 MB
// 0xFEC00000 IO-APIC 4 KB
// 0xFEC01000 gap 1020 KB
@@ -181,6 +167,22 @@ PlatformMemMapInitialization (
// 0xFED20000 gap 896 KB
// 0xFEE00000 LAPIC 1 MB
//
+ PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
+ PciExBarBase = 0;
+ if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+ //
+ // The MMCONFIG area is expected to fall between the top of low RAM and
+ // the base of the 32-bit PCI host aperture.
+ //
+ PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);
+ ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase);
+ ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
+ PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
+ } else {
+ ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base);
+ PciBase = PlatformInfoHob->Uc32Base;
+ }
+
PciSize = 0xFC000000 - PciBase;
PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);

--
2.39.1

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